Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/sparc.ad @ 6179:8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland
| author | kvn |
|---|---|
| date | Fri, 15 Jun 2012 01:25:19 -0700 |
| parents | 8b0a4867acf0 |
| children | da91efe96a93 |
| rev | line source |
|---|---|
| 0 | 1 // |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
|
1007
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
| 0 | 429 %} |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 3892 | 463 extern bool use_block_zeroing(Node* count); |
| 464 | |
| 0 | 465 // Macros to extract hi & lo halves from a long pair. |
| 466 // G0 is not part of any long pair, so assert on that. | |
| 605 | 467 // Prevents accidentally using G1 instead of G0. |
| 0 | 468 #define LONG_HI_REG(x) (x) |
| 469 #define LONG_LO_REG(x) (x) | |
| 470 | |
| 471 %} | |
| 472 | |
| 473 source %{ | |
| 474 #define __ _masm. | |
| 475 | |
| 476 // tertiary op of a LoadP or StoreP encoding | |
| 477 #define REGP_OP true | |
| 478 | |
| 479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 481 static Register reg_to_register_object(int register_encoding); | |
| 482 | |
| 483 // Used by the DFA in dfa_sparc.cpp. | |
| 484 // Check for being able to use a V9 branch-on-register. Requires a | |
| 485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 486 // extended. Doesn't work following an integer ADD, for example, because of | |
| 487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 489 // replace them with zero, which could become sign-extension in a different OS | |
| 490 // release. There's no obvious reason why an interrupt will ever fill these | |
| 491 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 492 // instructions which either zero-fill or sign-fill). | |
| 493 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 494 if( !BranchOnRegister ) return false; | |
| 495 #ifdef _LP64 | |
| 496 if( cmp->Opcode() == Op_CmpP ) | |
| 497 return true; // No problems with pointer compares | |
| 498 #endif | |
| 499 if( cmp->Opcode() == Op_CmpL ) | |
| 500 return true; // No problems with long compares | |
| 501 | |
| 502 if( !SparcV9RegsHiBitsZero ) return false; | |
| 503 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 504 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 505 return false; | |
| 506 | |
| 507 // Check for comparing against a 'safe' value. Any operation which | |
| 508 // clears out the high word is safe. Thus, loads and certain shifts | |
| 509 // are safe, as are non-negative constants. Any operation which | |
| 510 // preserves zero bits in the high word is safe as long as each of its | |
| 511 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 512 // inputs are safe. At present, the only important case to recognize | |
| 513 // seems to be loads. Constants should fold away, and shifts & | |
| 514 // logicals can use the 'cc' forms. | |
| 515 Node *x = cmp->in(1); | |
| 516 if( x->is_Load() ) return true; | |
| 517 if( x->is_Phi() ) { | |
| 518 for( uint i = 1; i < x->req(); i++ ) | |
| 519 if( !x->in(i)->is_Load() ) | |
| 520 return false; | |
| 521 return true; | |
| 522 } | |
| 523 return false; | |
| 524 } | |
| 525 | |
| 3892 | 526 bool use_block_zeroing(Node* count) { |
| 527 // Use BIS for zeroing if count is not constant | |
| 528 // or it is >= BlockZeroingLowLimit. | |
| 529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
| 530 } | |
| 531 | |
| 0 | 532 // **************************************************************************** |
| 533 | |
| 534 // REQUIRED FUNCTIONALITY | |
| 535 | |
| 536 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 537 // from the start of the call to the point where the return address | |
| 538 // will point. | |
| 539 // The "return address" is the address of the call instruction, plus 8. | |
| 540 | |
| 541 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 542 int offset = NativeCall::instruction_size; // call; delay slot |
| 543 if (_method_handle_invoke) | |
| 544 offset += 4; // restore SP | |
| 545 return offset; | |
| 0 | 546 } |
| 547 | |
| 548 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 549 int vtable_index = this->_vtable_index; | |
| 550 if (vtable_index < 0) { | |
| 551 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 552 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 553 return (NativeMovConstReg::instruction_size + | |
| 554 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 555 } else { | |
| 556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 557 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
559 int klass_load_size; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
560 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
561 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
562 if (Universe::narrow_oop_base() == NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
564 else |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
565 klass_load_size = 3*BytesPerInstWord; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
566 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
567 klass_load_size = 1*BytesPerInstWord; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
568 } |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
569 if (Assembler::is_simm13(v_off)) { |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
570 return klass_load_size + |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 572 NativeCall::instruction_size); // call; delay slot |
| 573 } else { | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
574 return klass_load_size + |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 576 NativeCall::instruction_size); // call; delay slot |
| 577 } | |
| 578 } | |
| 579 } | |
| 580 | |
| 581 int MachCallRuntimeNode::ret_addr_offset() { | |
| 582 #ifdef _LP64 | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
583 if (MacroAssembler::is_far_target(entry_point())) { |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
584 return NativeFarCall::instruction_size; |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
585 } else { |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
586 return NativeCall::instruction_size; |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
587 } |
| 0 | 588 #else |
| 589 return NativeCall::instruction_size; // call; delay slot | |
| 590 #endif | |
| 591 } | |
| 592 | |
| 593 // Indicate if the safepoint node needs the polling page as an input. | |
| 594 // Since Sparc does not have absolute addressing, it does. | |
| 595 bool SafePointNode::needs_polling_address_input() { | |
| 596 return true; | |
| 597 } | |
| 598 | |
| 599 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 600 void emit_break(CodeBuffer &cbuf) { | |
| 601 MacroAssembler _masm(&cbuf); | |
| 602 __ breakpoint_trap(); | |
| 603 } | |
| 604 | |
| 605 #ifndef PRODUCT | |
| 606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 607 st->print("TA"); | |
| 608 } | |
| 609 #endif | |
| 610 | |
| 611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 612 emit_break(cbuf); | |
| 613 } | |
| 614 | |
| 615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 616 return MachNode::size(ra_); | |
| 617 } | |
| 618 | |
| 619 // Traceable jump | |
| 620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 621 MacroAssembler _masm(&cbuf); | |
| 622 Register rdest = reg_to_register_object(jump_target); | |
| 623 __ JMP(rdest, 0); | |
| 624 __ delayed()->nop(); | |
| 625 } | |
| 626 | |
| 627 // Traceable jump and set exception pc | |
| 628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 629 MacroAssembler _masm(&cbuf); | |
| 630 Register rdest = reg_to_register_object(jump_target); | |
| 631 __ JMP(rdest, 0); | |
| 632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 633 } | |
| 634 | |
| 635 void emit_nop(CodeBuffer &cbuf) { | |
| 636 MacroAssembler _masm(&cbuf); | |
| 637 __ nop(); | |
| 638 } | |
| 639 | |
| 640 void emit_illtrap(CodeBuffer &cbuf) { | |
| 641 MacroAssembler _masm(&cbuf); | |
| 642 __ illtrap(0); | |
| 643 } | |
| 644 | |
| 645 | |
| 646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 647 assert(n->rule() != loadUB_rule, ""); | |
| 648 | |
| 649 intptr_t offset = 0; | |
| 650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 651 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 653 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 654 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 655 atype = atype->add_offset(offset); | |
| 656 assert(disp32 == offset, "wrong disp32"); | |
| 657 return atype->_offset; | |
| 658 } | |
| 659 | |
| 660 | |
| 661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 662 assert(n->rule() != loadUB_rule, ""); | |
| 663 | |
| 664 intptr_t offset = 0; | |
| 665 Node* addr = n->in(2); | |
| 666 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 668 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 669 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 671 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 672 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 673 } | |
| 674 offset = atype->is_ptr()->_offset; | |
| 675 if (offset != Type::OffsetBot) offset += disp32; | |
| 676 return offset; | |
| 677 } | |
| 678 | |
| 2008 | 679 static inline jdouble replicate_immI(int con, int count, int width) { |
| 680 // Load a constant replicated "count" times with width "width" | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
681 assert(count*width == 8 && width <= 4, "sanity"); |
| 2008 | 682 int bit_width = width * 8; |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
683 jlong val = con; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
| 2008 | 685 for (int i = 0; i < count - 1; i++) { |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
686 val |= (val << bit_width); |
| 2008 | 687 } |
| 688 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 689 return dval; | |
| 690 } | |
| 691 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
692 static inline jdouble replicate_immF(float con) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
693 // Replicate float con 2 times and pack into vector. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
694 int val = *((int*)&con); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
695 jlong lval = val; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
697 jdouble dval = *((jdouble*) &lval); // coerce to double type |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
698 return dval; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
699 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
700 |
| 0 | 701 // Standard Sparc opcode form2 field breakdown |
| 702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 703 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 704 int op = (f30 << 30) | | |
| 705 (f29 << 29) | | |
| 706 (f25 << 25) | | |
| 707 (f22 << 22) | | |
| 708 (f20 << 20) | | |
| 709 (f19 << 19) | | |
| 710 (f0 << 0); | |
| 1748 | 711 cbuf.insts()->emit_int32(op); |
| 0 | 712 } |
| 713 | |
| 714 // Standard Sparc opcode form2 field breakdown | |
| 715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 716 f0 >>= 10; // Drop 10 bits | |
| 717 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 718 int op = (f30 << 30) | | |
| 719 (f25 << 25) | | |
| 720 (f22 << 22) | | |
| 721 (f0 << 0); | |
| 1748 | 722 cbuf.insts()->emit_int32(op); |
| 0 | 723 } |
| 724 | |
| 725 // Standard Sparc opcode form3 field breakdown | |
| 726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 727 int op = (f30 << 30) | | |
| 728 (f25 << 25) | | |
| 729 (f19 << 19) | | |
| 730 (f14 << 14) | | |
| 731 (f5 << 5) | | |
| 732 (f0 << 0); | |
| 1748 | 733 cbuf.insts()->emit_int32(op); |
| 0 | 734 } |
| 735 | |
| 736 // Standard Sparc opcode form3 field breakdown | |
| 737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 738 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 739 int op = (f30 << 30) | | |
| 740 (f25 << 25) | | |
| 741 (f19 << 19) | | |
| 742 (f14 << 14) | | |
| 743 (1 << 13) | // bit to indicate immediate-mode | |
| 744 (simm13<<0); | |
| 1748 | 745 cbuf.insts()->emit_int32(op); |
| 0 | 746 } |
| 747 | |
| 748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 749 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 751 } | |
| 752 | |
| 753 #ifdef ASSERT | |
| 754 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 756 warning("VerifyOops encountered unexpected instruction:"); | |
| 757 n->dump(2); | |
| 758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 759 } | |
| 760 #endif | |
| 761 | |
| 762 | |
| 763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 764 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 765 | |
| 766 #ifdef ASSERT | |
| 767 // The following code implements the +VerifyOops feature. | |
| 768 // It verifies oop values which are loaded into or stored out of | |
| 769 // the current method activation. +VerifyOops complements techniques | |
| 770 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 771 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 772 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 773 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 774 // to their point of creation. It can also serve as a cross-check | |
| 775 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 776 | |
| 777 // It would be good to verify oops at other points, especially | |
| 778 // when an oop is used as a base pointer for a load or store. | |
| 779 // This is presently difficult, because it is hard to know when | |
| 780 // a base address is biased or not. (If we had such information, | |
| 781 // it would be easy and useful to make a two-argument version of | |
| 782 // verify_oop which unbiases the base, and performs verification.) | |
| 783 | |
| 784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 785 bool is_verified_oop_base = false; | |
| 786 bool is_verified_oop_load = false; | |
| 787 bool is_verified_oop_store = false; | |
| 788 int tmp_enc = -1; | |
| 789 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 790 // classify the op, mainly for an assert check | |
| 791 int st_op = 0, ld_op = 0; | |
| 792 switch (primary) { | |
| 793 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 794 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 796 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 797 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 798 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 799 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 800 | |
| 801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 805 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 807 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 808 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 809 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 810 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 812 | |
| 813 default: ShouldNotReachHere(); | |
| 814 } | |
| 815 if (tertiary == REGP_OP) { | |
| 816 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 818 else ShouldNotReachHere(); | |
| 819 if (st_op) { | |
| 820 // a store | |
| 821 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 822 Node* n2 = n->in(3); | |
| 823 if (n2 != NULL) { | |
| 824 const Type* t = n2->bottom_type(); | |
| 825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 826 } | |
| 827 } else { | |
| 828 // a load | |
| 829 const Type* t = n->bottom_type(); | |
| 830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 831 } | |
| 832 } | |
| 833 | |
| 834 if (ld_op) { | |
| 835 // a Load | |
| 836 // inputs are (0:control, 1:memory, 2:address) | |
| 837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
| 3898 | 850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
| 0 | 852 !(n->rule() == loadUB_rule)) { |
| 853 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 854 } | |
| 855 } else if (st_op) { | |
| 856 // a Store | |
| 857 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
| 0 | 864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 865 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 866 } | |
| 867 } | |
| 868 | |
| 869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 870 Node* addr = n->in(2); | |
| 871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 873 if (atype != NULL) { | |
| 874 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 876 if (offset != offset_2) { | |
| 877 get_offset_from_base(n, atype, disp32); | |
| 878 get_offset_from_base_2(n, atype, disp32); | |
| 879 } | |
| 880 assert(offset == offset_2, "different offsets"); | |
| 881 if (offset == disp32) { | |
| 882 // we now know that src1 is a true oop pointer | |
| 883 is_verified_oop_base = true; | |
| 884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 885 if( primary == Assembler::ldd_op3 ) { | |
| 886 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 887 } else { | |
| 888 tmp_enc = dst_enc; | |
| 889 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 890 assert(src1_enc != dst_enc, ""); | |
| 891 } | |
| 892 } | |
| 893 } | |
| 894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 895 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 896 // loading the mark should not be allowed either, but | |
| 897 // we don't check this since it conflicts with InlineObjectHash | |
| 898 // usage of LoadINode to get the mark. We could keep the | |
| 899 // check if we create a new LoadMarkNode | |
| 900 // but do not verify the object before its header is initialized | |
| 901 ShouldNotReachHere(); | |
| 902 } | |
| 903 } | |
| 904 } | |
| 905 } | |
| 906 } | |
| 907 #endif | |
| 908 | |
| 909 uint instr; | |
| 910 instr = (Assembler::ldst_op << 30) | |
| 911 | (dst_enc << 25) | |
| 912 | (primary << 19) | |
| 913 | (src1_enc << 14); | |
| 914 | |
| 915 uint index = src2_enc; | |
| 916 int disp = disp32; | |
| 917 | |
| 918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 919 disp += STACK_BIAS; | |
| 920 | |
| 921 // We should have a compiler bailout here rather than a guarantee. | |
| 922 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 924 | |
| 925 if( disp == 0 ) { | |
| 926 // use reg-reg form | |
| 927 // bit 13 is already zero | |
| 928 instr |= index; | |
| 929 } else { | |
| 930 // use reg-imm form | |
| 931 instr |= 0x00002000; // set bit 13 to one | |
| 932 instr |= disp & 0x1FFF; | |
| 933 } | |
| 934 | |
| 1748 | 935 cbuf.insts()->emit_int32(instr); |
| 0 | 936 |
| 937 #ifdef ASSERT | |
| 938 { | |
| 939 MacroAssembler _masm(&cbuf); | |
| 940 if (is_verified_oop_base) { | |
| 941 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 942 } | |
| 943 if (is_verified_oop_store) { | |
| 944 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 945 } | |
| 946 if (tmp_enc != -1) { | |
| 947 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 948 } | |
| 949 if (is_verified_oop_load) { | |
| 950 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 951 } | |
| 952 } | |
| 953 #endif | |
| 954 } | |
| 955 | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
| 0 | 957 // The method which records debug information at every safepoint |
| 958 // expects the call to be the first instruction in the snippet as | |
| 959 // it creates a PcDesc structure which tracks the offset of a call | |
| 960 // from the start of the codeBlob. This offset is computed as | |
| 961 // code_end() - code_begin() of the code which has been emitted | |
| 962 // so far. | |
| 963 // In this particular case we have skirted around the problem by | |
| 964 // putting the "mov" instruction in the delay slot but the problem | |
| 965 // may bite us again at some other point and a cleaner/generic | |
| 966 // solution using relocations would be needed. | |
| 967 MacroAssembler _masm(&cbuf); | |
| 968 __ set_inst_mark(); | |
| 969 | |
| 970 // We flush the current window just so that there is a valid stack copy | |
| 971 // the fact that the current window becomes active again instantly is | |
| 972 // not a problem there is nothing live in it. | |
| 973 | |
| 974 #ifdef ASSERT | |
| 975 int startpos = __ offset(); | |
| 976 #endif /* ASSERT */ | |
| 977 | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
978 __ call((address)entry_point, rtype); |
| 0 | 979 |
| 980 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 981 else __ delayed()->nop(); | |
| 982 | |
| 983 if (preserve_g2) __ mov(L7, G2); | |
| 984 | |
| 985 #ifdef ASSERT | |
| 986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 987 #ifdef _LP64 | |
| 988 // Trash argument dump slots. | |
| 989 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 990 __ mov(G1, G5); | |
| 991 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 992 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 993 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 994 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 995 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 996 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 997 #else // _LP64 | |
| 998 // this is also a native call, so smash the first 7 stack locations, | |
| 999 // and the various registers | |
| 1000 | |
| 1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 1002 // while [SP+0x44..0x58] are the argument dump slots. | |
| 1003 __ set((intptr_t)0xbaadf00d, G1); | |
| 1004 __ mov(G1, G5); | |
| 1005 __ sllx(G1, 32, G1); | |
| 1006 __ or3(G1, G5, G1); | |
| 1007 __ mov(G1, G5); | |
| 1008 __ stx(G1, SP, 0x40); | |
| 1009 __ stx(G1, SP, 0x48); | |
| 1010 __ stx(G1, SP, 0x50); | |
| 1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1012 #endif // _LP64 | |
| 1013 } | |
| 1014 #endif /*ASSERT*/ | |
| 1015 } | |
| 1016 | |
| 1017 //============================================================================= | |
| 1018 // REQUIRED FUNCTIONALITY for encoding | |
| 1019 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1020 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1021 | |
| 1022 | |
| 1023 //============================================================================= | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
| 2008 | 1025 |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1026 int Compile::ConstantTable::calculate_table_base_offset() const { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1027 if (UseRDPCForConstantTableBase) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1028 // The table base offset might be less but then it fits into |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1030 return Assembler::min_simm13(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1031 } else { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1032 int offset = -(size() / 2); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1033 if (!Assembler::is_simm13(offset)) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1034 offset = Assembler::min_simm13(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1035 } |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1036 return offset; |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1037 } |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1038 } |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1039 |
| 2008 | 1040 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 1041 Compile* C = ra_->C; | |
| 1042 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1043 MacroAssembler _masm(&cbuf); | |
| 1044 | |
| 1045 Register r = as_Register(ra_->get_encode(this)); | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1046 CodeSection* consts_section = __ code()->consts(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1047 int consts_size = consts_section->align_at_start(consts_section->size()); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1048 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
| 2008 | 1049 |
| 1050 if (UseRDPCForConstantTableBase) { | |
| 1051 // For the following RDPC logic to work correctly the consts | |
| 1052 // section must be allocated right before the insts section. This | |
| 1053 // assert checks for that. The layout and the SECT_* constants | |
| 1054 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1055 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1056 int insts_offset = __ offset(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1057 |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1058 // Layout: |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1059 // |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1060 // |----------- consts section ------------|----------- insts section -----------... |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1061 // |------ constant table -----|- padding -|------------------x---- |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1062 // \ current PC (RDPC instruction) |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1063 // |<------------- consts_size ----------->|<- insts_offset ->| |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1064 // \ table base |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1065 // The table base offset is later added to the load displacement |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1066 // so it has to be negative. |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1067 int table_base_offset = -(consts_size + insts_offset); |
| 2008 | 1068 int disp; |
| 1069 | |
| 1070 // If the displacement from the current PC to the constant table | |
| 1071 // base fits into simm13 we set the constant table base to the | |
| 1072 // current PC. | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1073 if (Assembler::is_simm13(table_base_offset)) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1074 constant_table.set_table_base_offset(table_base_offset); |
| 2008 | 1075 disp = 0; |
| 1076 } else { | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1077 // Otherwise we set the constant table base offset to the |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1078 // maximum negative displacement of load instructions to keep |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1079 // the disp as small as possible: |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1080 // |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1081 // |<------------- consts_size ----------->|<- insts_offset ->| |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1082 // |<--------- min_simm13 --------->|<-------- disp --------->| |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1083 // \ table base |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1084 table_base_offset = Assembler::min_simm13(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1085 constant_table.set_table_base_offset(table_base_offset); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1086 disp = (consts_size + insts_offset) + table_base_offset; |
| 2008 | 1087 } |
| 1088 | |
| 1089 __ rdpc(r); | |
| 1090 | |
| 1091 if (disp != 0) { | |
| 1092 assert(r != O7, "need temporary"); | |
| 1093 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1094 } | |
| 1095 } | |
| 1096 else { | |
| 1097 // Materialize the constant table base. | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1098 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
| 2008 | 1099 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
| 1100 AddressLiteral base(baseaddr, rspec); | |
| 1101 __ set(base, r); | |
| 1102 } | |
| 1103 } | |
| 1104 | |
| 1105 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1106 if (UseRDPCForConstantTableBase) { | |
| 1107 // This is really the worst case but generally it's only 1 instruction. | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1108 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
| 2008 | 1109 } else { |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1110 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
| 2008 | 1111 } |
| 1112 } | |
| 1113 | |
| 1114 #ifndef PRODUCT | |
| 1115 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1116 char reg[128]; | |
| 1117 ra_->dump_register(this, reg); | |
| 1118 if (UseRDPCForConstantTableBase) { | |
| 1119 st->print("RDPC %s\t! constant table base", reg); | |
| 1120 } else { | |
| 1121 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1122 } | |
| 1123 } | |
| 1124 #endif | |
| 1125 | |
| 1126 | |
| 1127 //============================================================================= | |
| 0 | 1128 |
| 1129 #ifndef PRODUCT | |
| 1130 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1131 Compile* C = ra_->C; | |
| 1132 | |
| 1133 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1134 st->print_cr("NOP"); st->print("\t"); | |
| 1135 } | |
| 1136 | |
| 1137 if( VerifyThread ) { | |
| 1138 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1139 } | |
| 1140 | |
| 1141 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1142 | |
| 1143 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1144 // We require that their callers must bang for them. But be careful, because | |
| 1145 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1146 // stack. But the stack safety zone should account for that. | |
| 1147 // See bugs 4446381, 4468289, 4497237. | |
| 1148 if (C->need_stack_bang(framesize)) { | |
| 1149 st->print_cr("! stack bang"); st->print("\t"); | |
| 1150 } | |
| 1151 | |
| 1152 if (Assembler::is_simm13(-framesize)) { | |
| 1153 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1154 } else { | |
| 1155 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1156 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1157 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1158 } | |
| 1159 | |
| 1160 } | |
| 1161 #endif | |
| 1162 | |
| 1163 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1164 Compile* C = ra_->C; | |
| 1165 MacroAssembler _masm(&cbuf); | |
| 1166 | |
| 1167 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1168 __ nop(); | |
| 1169 } | |
| 1170 | |
| 1171 __ verify_thread(); | |
| 1172 | |
| 1173 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1174 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1175 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1176 | |
| 1177 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1178 // We require that their callers must bang for them. But be careful, because | |
| 1179 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1180 // stack. But the stack safety zone should account for that. | |
| 1181 // See bugs 4446381, 4468289, 4497237. | |
| 1182 if (C->need_stack_bang(framesize)) { | |
| 1183 __ generate_stack_overflow_check(framesize); | |
| 1184 } | |
| 1185 | |
| 1186 if (Assembler::is_simm13(-framesize)) { | |
| 1187 __ save(SP, -framesize, SP); | |
| 1188 } else { | |
| 1189 __ sethi(-framesize & ~0x3ff, G3); | |
| 1190 __ add(G3, -framesize & 0x3ff, G3); | |
| 1191 __ save(SP, G3, SP); | |
| 1192 } | |
| 1193 C->set_frame_complete( __ offset() ); | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1194 |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1195 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1196 // NOTE: We set the table base offset here because users might be |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1197 // emitted before MachConstantBaseNode. |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1198 Compile::ConstantTable& constant_table = C->constant_table(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1199 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1200 } |
| 0 | 1201 } |
| 1202 | |
| 1203 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1204 return MachNode::size(ra_); | |
| 1205 } | |
| 1206 | |
| 1207 int MachPrologNode::reloc() const { | |
| 1208 return 10; // a large enough number | |
| 1209 } | |
| 1210 | |
| 1211 //============================================================================= | |
| 1212 #ifndef PRODUCT | |
| 1213 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1214 Compile* C = ra_->C; | |
| 1215 | |
| 1216 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1217 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1218 #ifdef _LP64 | |
| 1219 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1220 #else | |
| 1221 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1222 #endif | |
| 1223 } | |
| 1224 | |
| 1225 if( do_polling() ) | |
| 1226 st->print("RET\n\t"); | |
| 1227 | |
| 1228 st->print("RESTORE"); | |
| 1229 } | |
| 1230 #endif | |
| 1231 | |
| 1232 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1233 MacroAssembler _masm(&cbuf); | |
| 1234 Compile* C = ra_->C; | |
| 1235 | |
| 1236 __ verify_thread(); | |
| 1237 | |
| 1238 // If this does safepoint polling, then do it here | |
| 1239 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1240 AddressLiteral polling_page(os::get_polling_page()); |
| 1241 __ sethi(polling_page, L0); | |
| 0 | 1242 __ relocate(relocInfo::poll_return_type); |
| 1243 __ ld_ptr( L0, 0, G0 ); | |
| 1244 } | |
| 1245 | |
| 1246 // If this is a return, then stuff the restore in the delay slot | |
| 1247 if( do_polling() ) { | |
| 1248 __ ret(); | |
| 1249 __ delayed()->restore(); | |
| 1250 } else { | |
| 1251 __ restore(); | |
| 1252 } | |
| 1253 } | |
| 1254 | |
| 1255 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1256 return MachNode::size(ra_); | |
| 1257 } | |
| 1258 | |
| 1259 int MachEpilogNode::reloc() const { | |
| 1260 return 16; // a large enough number | |
| 1261 } | |
| 1262 | |
| 1263 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1264 return MachNode::pipeline_class(); | |
| 1265 } | |
| 1266 | |
| 1267 int MachEpilogNode::safepoint_offset() const { | |
| 1268 assert( do_polling(), "no return for this epilog node"); | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1269 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
| 0 | 1270 } |
| 1271 | |
| 1272 //============================================================================= | |
| 1273 | |
| 1274 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1275 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1276 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1277 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1278 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1279 VMReg r = OptoReg::as_VMReg(reg); | |
| 1280 if (r->is_Register()) return rc_int; | |
| 1281 assert(r->is_FloatRegister(), "must be"); | |
| 1282 return rc_float; | |
| 1283 } | |
| 1284 | |
| 1285 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1286 if( cbuf ) { | |
| 1287 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1288 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1289 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1290 } else { | |
| 1291 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1292 } | |
| 1293 } | |
| 1294 #ifndef PRODUCT | |
| 1295 else if( !do_size ) { | |
| 1296 if( size != 0 ) st->print("\n\t"); | |
| 1297 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1298 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1299 } | |
| 1300 #endif | |
| 1301 return size+4; | |
| 1302 } | |
| 1303 | |
| 1304 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1305 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1306 #ifndef PRODUCT | |
| 1307 else if( !do_size ) { | |
| 1308 if( size != 0 ) st->print("\n\t"); | |
| 1309 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1310 } | |
| 1311 #endif | |
| 1312 return size+4; | |
| 1313 } | |
| 1314 | |
| 1315 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1316 PhaseRegAlloc *ra_, | |
| 1317 bool do_size, | |
| 1318 outputStream* st ) const { | |
| 1319 // Get registers to move | |
| 1320 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1321 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1322 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1323 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1324 | |
| 1325 enum RC src_second_rc = rc_class(src_second); | |
| 1326 enum RC src_first_rc = rc_class(src_first); | |
| 1327 enum RC dst_second_rc = rc_class(dst_second); | |
| 1328 enum RC dst_first_rc = rc_class(dst_first); | |
| 1329 | |
| 1330 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1331 | |
| 1332 // Generate spill code! | |
| 1333 int size = 0; | |
| 1334 | |
| 1335 if( src_first == dst_first && src_second == dst_second ) | |
| 1336 return size; // Self copy, no move | |
| 1337 | |
| 1338 // -------------------------------------- | |
| 1339 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1340 // the float-store case. | |
| 1341 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1342 int offset = ra_->reg2offset(src_first); | |
| 1343 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1344 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1345 src_second = OptoReg::Name(R_F31_num); | |
| 1346 src_second_rc = rc_float; | |
| 1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1348 } else { | |
| 1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1350 } | |
| 1351 src_first = OptoReg::Name(R_F30_num); | |
| 1352 src_first_rc = rc_float; | |
| 1353 } | |
| 1354 | |
| 1355 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1356 int offset = ra_->reg2offset(src_second); | |
| 1357 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1358 src_second = OptoReg::Name(R_F31_num); | |
| 1359 src_second_rc = rc_float; | |
| 1360 } | |
| 1361 | |
| 1362 // -------------------------------------- | |
| 1363 // Check for float->int copy; requires a trip through memory | |
| 3804 | 1364 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
| 0 | 1365 int offset = frame::register_save_words*wordSize; |
| 3804 | 1366 if (cbuf) { |
| 0 | 1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
| 1368 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1369 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1371 } | |
| 1372 #ifndef PRODUCT | |
| 3804 | 1373 else if (!do_size) { |
| 1374 if (size != 0) st->print("\n\t"); | |
| 0 | 1375 st->print( "SUB R_SP,16,R_SP\n"); |
| 1376 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1377 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1378 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1379 } | |
| 1380 #endif | |
| 1381 size += 16; | |
| 1382 } | |
| 1383 | |
| 3804 | 1384 // Check for float->int copy on T4 |
| 1385 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
| 1386 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1387 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1388 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
| 1389 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
| 1390 } | |
| 1391 // Check for int->float copy on T4 | |
| 1392 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
| 1393 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1394 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1395 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
| 1396 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
| 1397 } | |
| 1398 | |
| 0 | 1399 // -------------------------------------- |
| 1400 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1401 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1402 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1403 // there. Misaligned sources only come from native-long-returns (handled | |
| 1404 // special below). | |
| 1405 #ifndef _LP64 | |
| 1406 if( src_first_rc == rc_int && // source is already big-endian | |
| 1407 src_second_rc != rc_bad && // 64-bit move | |
| 1408 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1409 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1410 // Do the big-endian flop. | |
| 1411 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1412 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1413 } | |
| 1414 #endif | |
| 1415 | |
| 1416 // -------------------------------------- | |
| 1417 // Check for integer reg-reg copy | |
| 1418 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1419 #ifndef _LP64 | |
| 1420 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1421 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1422 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1423 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1424 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1425 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1426 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1427 if( cbuf ) { | |
| 1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1430 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1431 #ifndef PRODUCT | |
| 1432 } else if( !do_size ) { | |
| 1433 if( size != 0 ) st->print("\n\t"); | |
| 1434 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1435 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1436 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1437 #endif | |
| 1438 } | |
| 1439 return size+12; | |
| 1440 } | |
| 1441 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1442 // returning a long value in I0/I1 | |
| 1443 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1444 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1445 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1446 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1447 OptoReg::Name tdest = dst_first; | |
| 1448 | |
| 1449 if (src_first == dst_first) { | |
| 1450 tdest = OptoReg::Name(R_O7_num); | |
| 1451 size += 4; | |
| 1452 } | |
| 1453 | |
| 1454 if( cbuf ) { | |
| 1455 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1456 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1457 // ShrL_reg_imm6 | |
| 1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1459 // ShrR_reg_imm6 src, 0, dst | |
| 1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1461 if (tdest != dst_first) { | |
| 1462 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1463 } | |
| 1464 } | |
| 1465 #ifndef PRODUCT | |
| 1466 else if( !do_size ) { | |
| 1467 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1468 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1469 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1470 if (tdest != dst_first) { | |
| 1471 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1472 } | |
| 1473 } | |
| 1474 #endif // PRODUCT | |
| 1475 return size+8; | |
| 1476 } | |
| 1477 #endif // !_LP64 | |
| 1478 // Else normal reg-reg copy | |
| 1479 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1480 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1481 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1482 // This moves an aligned adjacent pair. | |
| 1483 // See if we are done. | |
| 1484 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1485 return size; | |
| 1486 } | |
| 1487 | |
| 1488 // Check for integer store | |
| 1489 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1490 int offset = ra_->reg2offset(dst_first); | |
| 1491 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1493 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1494 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1495 } | |
| 1496 | |
| 1497 // Check for integer load | |
| 1498 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1499 int offset = ra_->reg2offset(src_first); | |
| 1500 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1501 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1502 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1503 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1504 } | |
| 1505 | |
| 1506 // Check for float reg-reg copy | |
| 1507 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1508 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1509 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1510 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1511 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1512 } | |
| 1513 | |
| 1514 // Check for float store | |
| 1515 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1516 int offset = ra_->reg2offset(dst_first); | |
| 1517 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1518 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1519 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1520 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1521 } | |
| 1522 | |
| 1523 // Check for float load | |
| 1524 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1525 int offset = ra_->reg2offset(src_first); | |
| 1526 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1527 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1528 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1529 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1530 } | |
| 1531 | |
| 1532 // -------------------------------------------------------------------- | |
| 1533 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1534 // arguments to native calls. | |
| 1535 if( src_second == dst_second ) | |
| 1536 return size; // Self copy; no move | |
| 1537 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1538 | |
| 1539 #ifndef _LP64 | |
| 1540 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1541 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1542 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1543 // all sorts of silly alignment problems. | |
| 1544 | |
| 1545 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1546 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1547 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1548 // happened already as part of a 64-bit move) | |
| 1549 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1550 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1551 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1552 // Shift src_second down to dst_second's low bits. | |
| 1553 if( cbuf ) { | |
| 1554 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1555 #ifndef PRODUCT | |
| 1556 } else if( !do_size ) { | |
| 1557 if( size != 0 ) st->print("\n\t"); | |
| 1558 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1559 #endif | |
| 1560 } | |
| 1561 return size+4; | |
| 1562 } | |
| 1563 | |
| 1564 // Check for high word integer store. Must down-shift the hi bits | |
| 1565 // into a temp register, then fall into the case of storing int bits. | |
| 1566 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1567 // Shift src_second down to dst_second's low bits. | |
| 1568 if( cbuf ) { | |
| 1569 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1570 #ifndef PRODUCT | |
| 1571 } else if( !do_size ) { | |
| 1572 if( size != 0 ) st->print("\n\t"); | |
| 1573 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1574 #endif | |
| 1575 } | |
| 1576 size+=4; | |
| 1577 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1578 } | |
| 1579 | |
| 1580 // Check for high word integer load | |
| 1581 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1582 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1583 | |
| 1584 // Check for high word integer store | |
| 1585 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1586 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1587 | |
| 1588 // Check for high word float store | |
| 1589 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1590 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1591 | |
| 1592 #endif // !_LP64 | |
| 1593 | |
| 1594 Unimplemented(); | |
| 1595 } | |
| 1596 | |
| 1597 #ifndef PRODUCT | |
| 1598 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1599 implementation( NULL, ra_, false, st ); | |
| 1600 } | |
| 1601 #endif | |
| 1602 | |
| 1603 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1604 implementation( &cbuf, ra_, false, NULL ); | |
| 1605 } | |
| 1606 | |
| 1607 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1608 return implementation( NULL, ra_, true, NULL ); | |
| 1609 } | |
| 1610 | |
| 1611 //============================================================================= | |
| 1612 #ifndef PRODUCT | |
| 1613 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1614 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1615 } | |
| 1616 #endif | |
| 1617 | |
| 1618 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1619 MacroAssembler _masm(&cbuf); | |
| 1620 for(int i = 0; i < _count; i += 1) { | |
| 1621 __ nop(); | |
| 1622 } | |
| 1623 } | |
| 1624 | |
| 1625 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1626 return 4 * _count; | |
| 1627 } | |
| 1628 | |
| 1629 | |
| 1630 //============================================================================= | |
| 1631 #ifndef PRODUCT | |
| 1632 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1634 int reg = ra_->get_reg_first(this); | |
| 1635 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1636 } | |
| 1637 #endif | |
| 1638 | |
| 1639 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1640 MacroAssembler _masm(&cbuf); | |
| 1641 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1642 int reg = ra_->get_encode(this); | |
| 1643 | |
| 1644 if (Assembler::is_simm13(offset)) { | |
| 1645 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1646 } else { | |
| 1647 __ set(offset, O7); | |
| 1648 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1649 } | |
| 1650 } | |
| 1651 | |
| 1652 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1653 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1654 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1655 return ra_->C->scratch_emit_size(this); | |
| 1656 } | |
| 1657 | |
| 1658 //============================================================================= | |
| 1659 | |
| 1660 // emit call stub, compiled java to interpretor | |
| 1661 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1662 | |
| 1663 // Stub is fixed up when the corresponding call is converted from calling | |
| 1664 // compiled code to calling interpreted code. | |
| 1665 // set (empty), G5 | |
| 1666 // jmp -1 | |
| 1667 | |
| 1748 | 1668 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 0 | 1669 |
| 1670 MacroAssembler _masm(&cbuf); | |
| 1671 | |
| 1672 address base = | |
| 1673 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1674 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1675 | |
| 1676 // static stub relocation stores the instruction address of the call | |
| 1677 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1678 | |
| 1679 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1680 | |
| 1681 __ set_inst_mark(); | |
| 727 | 1682 AddressLiteral addrlit(-1); |
| 1683 __ JUMP(addrlit, G3, 0); | |
| 0 | 1684 |
| 1685 __ delayed()->nop(); | |
| 1686 | |
| 1687 // Update current stubs pointer and restore code_end. | |
| 1688 __ end_a_stub(); | |
| 1689 } | |
| 1690 | |
| 1691 // size of call stub, compiled java to interpretor | |
| 1692 uint size_java_to_interp() { | |
| 1693 // This doesn't need to be accurate but it must be larger or equal to | |
| 1694 // the real size of the stub. | |
| 1695 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1696 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1697 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1698 } | |
| 1699 // relocation entries for call stub, compiled java to interpretor | |
| 1700 uint reloc_java_to_interp() { | |
| 1701 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1702 } | |
| 1703 | |
| 1704 | |
| 1705 //============================================================================= | |
| 1706 #ifndef PRODUCT | |
| 1707 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1708 st->print_cr("\nUEP:"); | |
| 1709 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1710 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1711 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1712 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1713 st->print_cr("\tSLL R_G5,3,R_G5"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1714 if (Universe::narrow_oop_base() != NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1715 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1716 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1717 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1718 } |
| 0 | 1719 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1720 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1721 #else // _LP64 | |
| 1722 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1723 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1724 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1725 #endif // _LP64 | |
| 1726 } | |
| 1727 #endif | |
| 1728 | |
| 1729 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1730 MacroAssembler _masm(&cbuf); | |
| 1731 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1732 Register temp_reg = G3; | |
| 1733 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1734 | |
| 605 | 1735 // Load klass from receiver |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1736 __ load_klass(O0, temp_reg); |
| 0 | 1737 // Compare against expected klass |
| 1738 __ cmp(temp_reg, G5_ic_reg); | |
| 1739 // Branch to miss code, checks xcc or icc depending | |
| 1740 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1741 } | |
| 1742 | |
| 1743 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1744 return MachNode::size(ra_); | |
| 1745 } | |
| 1746 | |
| 1747 | |
| 1748 //============================================================================= | |
| 1749 | |
| 1750 uint size_exception_handler() { | |
| 1751 if (TraceJumps) { | |
| 1752 return (400); // just a guess | |
| 1753 } | |
| 1754 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1755 } | |
| 1756 | |
| 1757 uint size_deopt_handler() { | |
| 1758 if (TraceJumps) { | |
| 1759 return (400); // just a guess | |
| 1760 } | |
| 1761 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1762 } | |
| 1763 | |
| 1764 // Emit exception handler code. | |
| 1765 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1766 Register temp_reg = G3; | |
| 1748 | 1767 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1768 MacroAssembler _masm(&cbuf); |
| 1769 | |
| 1770 address base = | |
| 1771 __ start_a_stub(size_exception_handler()); | |
| 1772 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1773 | |
| 1774 int offset = __ offset(); | |
| 1775 | |
| 727 | 1776 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1777 __ delayed()->nop(); |
| 1778 | |
| 1779 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1780 | |
| 1781 __ end_a_stub(); | |
| 1782 | |
| 1783 return offset; | |
| 1784 } | |
| 1785 | |
| 1786 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1787 // Can't use any of the current frame's registers as we may have deopted | |
| 1788 // at a poll and everything (including G3) can be live. | |
| 1789 Register temp_reg = L0; | |
| 727 | 1790 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1791 MacroAssembler _masm(&cbuf); |
| 1792 | |
| 1793 address base = | |
| 1794 __ start_a_stub(size_deopt_handler()); | |
| 1795 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1796 | |
| 1797 int offset = __ offset(); | |
| 1798 __ save_frame(0); | |
| 727 | 1799 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1800 __ delayed()->restore(); |
| 1801 | |
| 1802 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1803 | |
| 1804 __ end_a_stub(); | |
| 1805 return offset; | |
| 1806 | |
| 1807 } | |
| 1808 | |
| 1809 // Given a register encoding, produce a Integer Register object | |
| 1810 static Register reg_to_register_object(int register_encoding) { | |
| 1811 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1812 return as_Register(register_encoding); | |
| 1813 } | |
| 1814 | |
| 1815 // Given a register encoding, produce a single-precision Float Register object | |
| 1816 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1817 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1818 return as_SingleFloatRegister(register_encoding); | |
| 1819 } | |
| 1820 | |
| 1821 // Given a register encoding, produce a double-precision Float Register object | |
| 1822 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1823 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1824 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1825 return as_DoubleFloatRegister(register_encoding); | |
| 1826 } | |
| 1827 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1828 const bool Matcher::match_rule_supported(int opcode) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1829 if (!has_match_rule(opcode)) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1830 return false; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1831 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1832 switch (opcode) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1833 case Op_CountLeadingZerosI: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1834 case Op_CountLeadingZerosL: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1835 case Op_CountTrailingZerosI: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1836 case Op_CountTrailingZerosL: |
|
5934
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
never
parents:
4777
diff
changeset
|
1837 case Op_PopCountI: |
|
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
never
parents:
4777
diff
changeset
|
1838 case Op_PopCountL: |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1839 if (!UsePopCountInstruction) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1840 return false; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1841 break; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1842 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1843 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1844 return true; // Per default match rules are supported. |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1845 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1846 |
| 0 | 1847 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1848 return regnum - 32; // The FP registers are in the second chunk | |
| 1849 } | |
| 1850 | |
| 1851 #ifdef ASSERT | |
| 1852 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1853 #endif | |
| 1854 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1855 // Map Types to machine register types |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1856 const int Matcher::base2reg[Type::lastype] = { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1857 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1858 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1859 0, Op_RegD, 0, 0, /* Vectors */ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1860 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1861 0, 0/*abio*/, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1862 Op_RegP /* Return address */, 0, /* the memories */ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1863 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1864 0 /*bottom*/ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1865 }; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1866 |
| 0 | 1867 // Vector width in bytes |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1868 const int Matcher::vector_width_in_bytes(BasicType bt) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1869 assert(MaxVectorSize == 8, ""); |
| 0 | 1870 return 8; |
| 1871 } | |
| 1872 | |
| 1873 // Vector ideal reg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1874 const int Matcher::vector_ideal_reg(int size) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1875 assert(MaxVectorSize == 8, ""); |
| 0 | 1876 return Op_RegD; |
| 1877 } | |
| 1878 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1879 // Limits on vector size (number of elements) loaded into vector. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1880 const int Matcher::max_vector_size(const BasicType bt) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1881 assert(is_java_primitive(bt), "only primitive type vectors"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1882 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1883 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1884 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1885 const int Matcher::min_vector_size(const BasicType bt) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1886 return max_vector_size(bt); // Same as max. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1887 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1888 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1889 // SPARC doesn't support misaligned vectors store/load. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1890 const bool Matcher::misaligned_vectors_ok() { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1891 return false; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1892 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1893 |
| 0 | 1894 // USII supports fxtof through the whole range of number, USIII doesn't |
| 1895 const bool Matcher::convL2FSupported(void) { | |
| 1896 return VM_Version::has_fast_fxtof(); | |
| 1897 } | |
| 1898 | |
| 1899 // Is this branch offset short enough that a short branch can be used? | |
| 1900 // | |
| 1901 // NOTE: If the platform does not provide any short branch variants, then | |
| 1902 // this method should return false for offset 0. | |
| 3851 | 1903 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1904 // The passed offset is relative to address of the branch. | |
| 1905 // Don't need to adjust the offset. | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1906 return UseCBCond && Assembler::is_simm12(offset); |
| 0 | 1907 } |
| 1908 | |
| 1909 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1910 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1911 // Depends on optimizations in MacroAssembler::setx. | |
| 1912 int hi = (int)(value >> 32); | |
| 1913 int lo = (int)(value & ~0); | |
| 1914 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1915 } | |
| 1916 | |
| 1917 // No scaling for the parameter the ClearArray node. | |
| 1918 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1919 | |
| 1920 // Threshold size for cleararray. | |
| 1921 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1922 | |
| 4047 | 1923 // No additional cost for CMOVL. |
| 1924 const int Matcher::long_cmove_cost() { return 0; } | |
| 1925 | |
| 1926 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
| 1927 const int Matcher::float_cmove_cost() { | |
| 1928 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
| 1929 } | |
| 1930 | |
| 0 | 1931 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1932 // be subsumed into complex addressing expressions or compute them into | |
| 1933 // registers? True for Intel but false for most RISCs | |
| 1934 const bool Matcher::clone_shift_expressions = false; | |
| 1935 | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1936 // Do we need to mask the count passed to shift instructions or does |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1937 // the cpu only look at the lower 5/6 bits anyway? |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1938 const bool Matcher::need_masked_shift_count = false; |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1939 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1940 bool Matcher::narrow_oop_use_complex_address() { |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1941 NOT_LP64(ShouldNotCallThis()); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1942 assert(UseCompressedOops, "only for compressed oops code"); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1943 return false; |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1944 } |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1945 |
| 0 | 1946 // Is it better to copy float constants, or load them directly from memory? |
| 1947 // Intel can load a float constant from a direct address, requiring no | |
| 1948 // extra registers. Most RISCs will have to materialize an address into a | |
| 1949 // register first, so they would do better to copy the constant from stack. | |
| 1950 const bool Matcher::rematerialize_float_constants = false; | |
| 1951 | |
| 1952 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1953 // needed. Else we split the double into 2 integer pieces and move it | |
| 1954 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1955 // Java calling convention forces doubles to be aligned. | |
| 1956 #ifdef _LP64 | |
| 1957 const bool Matcher::misaligned_doubles_ok = true; | |
| 1958 #else | |
| 1959 const bool Matcher::misaligned_doubles_ok = false; | |
| 1960 #endif | |
| 1961 | |
| 1962 // No-op on SPARC. | |
| 1963 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1964 } | |
| 1965 | |
| 1966 // Advertise here if the CPU requires explicit rounding operations | |
| 1967 // to implement the UseStrictFP mode. | |
| 1968 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1969 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1970 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1971 // Sparc does not handle callee-save floats. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1972 bool Matcher::float_in_double() { return false; } |
| 0 | 1973 |
| 1974 // Do ints take an entire long register or just half? | |
| 1975 // Note that we if-def off of _LP64. | |
| 1976 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1977 // the whole long is written but de-opt'ing will have to extract | |
| 1978 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1979 #ifdef _LP64 | |
| 1980 const bool Matcher::int_in_long = true; | |
| 1981 #else | |
| 1982 const bool Matcher::int_in_long = false; | |
| 1983 #endif | |
| 1984 | |
| 1985 // Return whether or not this register is ever used as an argument. This | |
| 1986 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1987 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1988 // arguments in those registers not be available to the callee. | |
| 1989 bool Matcher::can_be_java_arg( int reg ) { | |
| 1990 // Standard sparc 6 args in registers | |
| 1991 if( reg == R_I0_num || | |
| 1992 reg == R_I1_num || | |
| 1993 reg == R_I2_num || | |
| 1994 reg == R_I3_num || | |
| 1995 reg == R_I4_num || | |
| 1996 reg == R_I5_num ) return true; | |
| 1997 #ifdef _LP64 | |
| 1998 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1999 // the high I registers | |
| 2000 if( reg == R_I0H_num || | |
| 2001 reg == R_I1H_num || | |
| 2002 reg == R_I2H_num || | |
| 2003 reg == R_I3H_num || | |
| 2004 reg == R_I4H_num || | |
| 2005 reg == R_I5H_num ) return true; | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2006 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2007 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2008 return true; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2009 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2010 |
| 0 | 2011 #else |
| 2012 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 2013 // Longs cannot be passed in O regs, because O regs become I regs | |
| 2014 // after a 'save' and I regs get their high bits chopped off on | |
| 2015 // interrupt. | |
| 2016 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 2017 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 2018 #endif | |
| 2019 // A few float args in registers | |
| 2020 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 2021 | |
| 2022 return false; | |
| 2023 } | |
| 2024 | |
| 2025 bool Matcher::is_spillable_arg( int reg ) { | |
| 2026 return can_be_java_arg(reg); | |
| 2027 } | |
| 2028 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2029 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2030 // Use hardware SDIVX instruction when it is |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2031 // faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2032 return VM_Version::has_fast_idiv(); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2033 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2034 |
| 0 | 2035 // Register for DIVI projection of divmodI |
| 2036 RegMask Matcher::divI_proj_mask() { | |
| 2037 ShouldNotReachHere(); | |
| 2038 return RegMask(); | |
| 2039 } | |
| 2040 | |
| 2041 // Register for MODI projection of divmodI | |
| 2042 RegMask Matcher::modI_proj_mask() { | |
| 2043 ShouldNotReachHere(); | |
| 2044 return RegMask(); | |
| 2045 } | |
| 2046 | |
| 2047 // Register for DIVL projection of divmodL | |
| 2048 RegMask Matcher::divL_proj_mask() { | |
| 2049 ShouldNotReachHere(); | |
| 2050 return RegMask(); | |
| 2051 } | |
| 2052 | |
| 2053 // Register for MODL projection of divmodL | |
| 2054 RegMask Matcher::modL_proj_mask() { | |
| 2055 ShouldNotReachHere(); | |
| 2056 return RegMask(); | |
| 2057 } | |
| 2058 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
2059 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
2060 return L7_REGP_mask(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
2061 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
2062 |
| 0 | 2063 %} |
| 2064 | |
| 2065 | |
| 2066 // The intptr_t operand types, defined by textual substitution. | |
| 2067 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 2068 #ifdef _LP64 | |
| 824 | 2069 #define immX immL |
| 2070 #define immX13 immL13 | |
| 2071 #define immX13m7 immL13m7 | |
| 2072 #define iRegX iRegL | |
| 2073 #define g1RegX g1RegL | |
| 0 | 2074 #else |
| 824 | 2075 #define immX immI |
| 2076 #define immX13 immI13 | |
| 2077 #define immX13m7 immI13m7 | |
| 2078 #define iRegX iRegI | |
| 2079 #define g1RegX g1RegI | |
| 0 | 2080 #endif |
| 2081 | |
| 2082 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2083 // This block specifies the encoding classes used by the compiler to output | |
| 2084 // byte streams. Encoding classes are parameterized macros used by | |
| 2085 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2086 // instruction. Operands specify their base encoding interface with the | |
| 2087 // interface keyword. There are currently supported four interfaces, | |
| 2088 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2089 // operand to generate a function which returns its register number when | |
| 2090 // queried. CONST_INTER causes an operand to generate a function which | |
| 2091 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2092 // operand to generate four functions which return the Base Register, the | |
| 2093 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2094 // queried. COND_INTER causes an operand to generate six functions which | |
| 2095 // return the encoding code (ie - encoding bits for the instruction) | |
| 2096 // associated with each basic boolean condition for a conditional instruction. | |
| 2097 // | |
| 2098 // Instructions specify two basic values for encoding. Again, a function | |
| 2099 // is available to check if the constant displacement is an oop. They use the | |
| 2100 // ins_encode keyword to specify their encoding classes (which must be | |
| 2101 // a sequence of enc_class names, and their parameters, specified in | |
| 2102 // the encoding block), and they use the | |
| 2103 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2104 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2105 // needs for encoding need to be specified. | |
| 2106 encode %{ | |
| 2107 enc_class enc_untested %{ | |
| 2108 #ifdef ASSERT | |
| 2109 MacroAssembler _masm(&cbuf); | |
| 2110 __ untested("encoding"); | |
| 2111 #endif | |
| 2112 %} | |
| 2113 | |
| 2114 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 2115 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 2116 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 2117 %} | |
| 2118 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2119 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2120 emit_form3_mem_reg(cbuf, this, $primary, -1, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2121 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2122 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2123 |
| 0 | 2124 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2125 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2126 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2127 %} | |
| 2128 | |
| 2129 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2130 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2131 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2132 %} | |
| 2133 | |
| 2134 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2135 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2136 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
| 0 | 2137 guarantee($mem$$index == R_G0_enc, "double index?"); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2138 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2139 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2140 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2141 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2142 %} | |
| 2143 | |
| 2144 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2145 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2146 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
| 0 | 2147 guarantee($mem$$index == R_G0_enc, "double index?"); |
| 2148 // Load long with 2 instructions | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2149 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2150 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2151 %} |
| 2152 | |
| 2153 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2154 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2155 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2156 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2157 %} |
| 2158 | |
| 2159 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2160 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2161 if( $rs2$$reg != $rd$$reg ) | |
| 2162 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2163 %} | |
| 2164 | |
| 2165 // Target lo half of long | |
| 2166 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2167 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2168 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2169 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2170 %} | |
| 2171 | |
| 2172 // Source lo half of long | |
| 2173 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2174 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2175 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2176 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2177 %} | |
| 2178 | |
| 2179 // Target hi half of long | |
| 2180 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2181 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2182 %} | |
| 2183 | |
| 2184 // Source lo half of long, and leave it sign extended. | |
| 2185 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2186 // Sign extend low half | |
| 2187 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2188 %} | |
| 2189 | |
| 2190 // Source hi half of long, and leave it sign extended. | |
| 2191 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2192 // Shift high half to low half | |
| 2193 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2194 %} | |
| 2195 | |
| 2196 // Source hi half of long | |
| 2197 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2198 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2199 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2200 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2201 %} | |
| 2202 | |
| 2203 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2204 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2205 %} | |
| 2206 | |
| 2207 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2208 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2209 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2210 %} | |
| 2211 | |
| 2212 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2213 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2214 // clear if nothing else is happening | |
| 2215 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2216 // blt,a,pn done | |
| 2217 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2218 // mov dst,-1 in delay slot | |
| 2219 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2220 %} | |
| 2221 | |
| 2222 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2223 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2224 %} | |
| 2225 | |
| 2226 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2227 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2228 %} | |
| 2229 | |
| 2230 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2231 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2232 %} | |
| 2233 | |
| 2234 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2235 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2236 %} | |
| 2237 | |
| 2238 enc_class move_return_pc_to_o1() %{ | |
| 2239 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2240 %} | |
| 2241 | |
| 2242 #ifdef _LP64 | |
| 2243 /* %%% merge with enc_to_bool */ | |
| 2244 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2245 MacroAssembler _masm(&cbuf); | |
| 2246 | |
| 2247 Register src_reg = reg_to_register_object($src$$reg); | |
| 2248 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2249 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2250 %} | |
| 2251 #endif | |
| 2252 | |
| 2253 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2254 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2255 MacroAssembler _masm(&cbuf); | |
| 2256 | |
| 2257 Register p_reg = reg_to_register_object($p$$reg); | |
| 2258 Register q_reg = reg_to_register_object($q$$reg); | |
| 2259 Register y_reg = reg_to_register_object($y$$reg); | |
| 2260 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2261 | |
| 2262 __ subcc( p_reg, q_reg, p_reg ); | |
| 2263 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2264 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2265 %} | |
| 2266 | |
| 2267 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2268 // fcmp %fcc0,$src,$src | |
| 2269 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2270 // branch %fcc0 not-nan, predict taken | |
| 2271 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2272 // fdtoi $src,$dst | |
| 2273 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2274 // fitos $dst,$dst (if nan) | |
| 2275 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2276 // clear $dst (if nan) | |
| 2277 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2278 // carry on here... | |
| 2279 %} | |
| 2280 | |
| 2281 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2282 // fcmp %fcc0,$src,$src check for NAN | |
| 2283 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2284 // branch %fcc0 not-nan, predict taken | |
| 2285 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2286 // fdtox $src,$dst convert in delay slot | |
| 2287 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2288 // fxtod $dst,$dst (if nan) | |
| 2289 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2290 // clear $dst (if nan) | |
| 2291 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2292 // carry on here... | |
| 2293 %} | |
| 2294 | |
| 2295 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2296 // fcmps %fcc0,$src,$src | |
| 2297 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2298 // branch %fcc0 not-nan, predict taken | |
| 2299 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2300 // fstoi $src,$dst | |
| 2301 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2302 // fitos $dst,$dst (if nan) | |
| 2303 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2304 // clear $dst (if nan) | |
| 2305 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2306 // carry on here... | |
| 2307 %} | |
| 2308 | |
| 2309 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2310 // fcmps %fcc0,$src,$src | |
| 2311 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2312 // branch %fcc0 not-nan, predict taken | |
| 2313 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2314 // fstox $src,$dst | |
| 2315 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2316 // fxtod $dst,$dst (if nan) | |
| 2317 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2318 // clear $dst (if nan) | |
| 2319 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2320 // carry on here... | |
| 2321 %} | |
| 2322 | |
| 2323 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2324 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2325 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2326 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2327 | |
| 2328 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2329 | |
| 2330 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2331 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2332 | |
| 2333 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2334 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2335 %} | |
| 2336 | |
| 2337 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2338 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2339 %} | |
| 2340 | |
| 2341 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2342 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2343 %} | |
| 2344 | |
| 2345 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2346 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2347 %} | |
| 2348 | |
| 2349 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2350 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2351 %} | |
| 2352 | |
| 2353 // Encloding class for traceable jumps | |
| 2354 enc_class form_jmpl(g3RegP dest) %{ | |
| 2355 emit_jmpl(cbuf, $dest$$reg); | |
| 2356 %} | |
| 2357 | |
| 2358 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2359 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2360 %} | |
| 2361 | |
| 2362 enc_class form2_nop() %{ | |
| 2363 emit_nop(cbuf); | |
| 2364 %} | |
| 2365 | |
| 2366 enc_class form2_illtrap() %{ | |
| 2367 emit_illtrap(cbuf); | |
| 2368 %} | |
| 2369 | |
| 2370 | |
| 2371 // Compare longs and convert into -1, 0, 1. | |
| 2372 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2373 // CMP $src1,$src2 | |
| 2374 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2375 // blt,a,pn done | |
| 2376 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2377 // mov dst,-1 in delay slot | |
| 2378 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2379 // bgt,a,pn done | |
| 2380 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2381 // mov dst,1 in delay slot | |
| 2382 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2383 // CLR $dst | |
| 2384 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2385 %} | |
| 2386 | |
| 2387 enc_class enc_PartialSubtypeCheck() %{ | |
| 2388 MacroAssembler _masm(&cbuf); | |
| 2389 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2390 __ delayed()->nop(); | |
| 2391 %} | |
| 2392 | |
| 3839 | 2393 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
| 0 | 2394 MacroAssembler _masm(&cbuf); |
| 3839 | 2395 Label* L = $labl$$label; |
| 0 | 2396 Assembler::Predict predict_taken = |
| 3839 | 2397 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2398 | |
| 2399 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 0 | 2400 __ delayed()->nop(); |
| 2401 %} | |
| 2402 | |
| 3839 | 2403 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
| 0 | 2404 MacroAssembler _masm(&cbuf); |
| 3839 | 2405 Label* L = $labl$$label; |
| 0 | 2406 Assembler::Predict predict_taken = |
| 3839 | 2407 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2408 | |
| 2409 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
| 0 | 2410 __ delayed()->nop(); |
| 2411 %} | |
| 2412 | |
| 2413 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2414 int op = (Assembler::arith_op << 30) | | |
| 2415 ($dst$$reg << 25) | | |
| 2416 (Assembler::movcc_op3 << 19) | | |
| 2417 (1 << 18) | // cc2 bit for 'icc' | |
| 2418 ($cmp$$cmpcode << 14) | | |
| 2419 (0 << 13) | // select register move | |
| 2420 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2421 ($src$$reg << 0); | |
| 1748 | 2422 cbuf.insts()->emit_int32(op); |
| 0 | 2423 %} |
| 2424 | |
| 2425 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2426 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2427 int op = (Assembler::arith_op << 30) | | |
| 2428 ($dst$$reg << 25) | | |
| 2429 (Assembler::movcc_op3 << 19) | | |
| 2430 (1 << 18) | // cc2 bit for 'icc' | |
| 2431 ($cmp$$cmpcode << 14) | | |
| 2432 (1 << 13) | // select immediate move | |
| 2433 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2434 (simm11 << 0); | |
| 1748 | 2435 cbuf.insts()->emit_int32(op); |
| 0 | 2436 %} |
| 2437 | |
| 2438 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2439 int op = (Assembler::arith_op << 30) | | |
| 2440 ($dst$$reg << 25) | | |
| 2441 (Assembler::movcc_op3 << 19) | | |
| 2442 (0 << 18) | // cc2 bit for 'fccX' | |
| 2443 ($cmp$$cmpcode << 14) | | |
| 2444 (0 << 13) | // select register move | |
| 2445 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2446 ($src$$reg << 0); | |
| 1748 | 2447 cbuf.insts()->emit_int32(op); |
| 0 | 2448 %} |
| 2449 | |
| 2450 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2451 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2452 int op = (Assembler::arith_op << 30) | | |
| 2453 ($dst$$reg << 25) | | |
| 2454 (Assembler::movcc_op3 << 19) | | |
| 2455 (0 << 18) | // cc2 bit for 'fccX' | |
| 2456 ($cmp$$cmpcode << 14) | | |
| 2457 (1 << 13) | // select immediate move | |
| 2458 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2459 (simm11 << 0); | |
| 1748 | 2460 cbuf.insts()->emit_int32(op); |
| 0 | 2461 %} |
| 2462 | |
| 2463 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2464 int op = (Assembler::arith_op << 30) | | |
| 2465 ($dst$$reg << 25) | | |
| 2466 (Assembler::fpop2_op3 << 19) | | |
| 2467 (0 << 18) | | |
| 2468 ($cmp$$cmpcode << 14) | | |
| 2469 (1 << 13) | // select register move | |
| 2470 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2471 ($primary << 5) | // select single, double or quad | |
| 2472 ($src$$reg << 0); | |
| 1748 | 2473 cbuf.insts()->emit_int32(op); |
| 0 | 2474 %} |
| 2475 | |
| 2476 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2477 int op = (Assembler::arith_op << 30) | | |
| 2478 ($dst$$reg << 25) | | |
| 2479 (Assembler::fpop2_op3 << 19) | | |
| 2480 (0 << 18) | | |
| 2481 ($cmp$$cmpcode << 14) | | |
| 2482 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2483 ($primary << 5) | // select single, double or quad | |
| 2484 ($src$$reg << 0); | |
| 1748 | 2485 cbuf.insts()->emit_int32(op); |
| 0 | 2486 %} |
| 2487 | |
| 2488 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2489 // the condition comes from opcode-field instead of an argument. | |
| 2490 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2491 int op = (Assembler::arith_op << 30) | | |
| 2492 ($dst$$reg << 25) | | |
| 2493 (Assembler::movcc_op3 << 19) | | |
| 2494 (1 << 18) | // cc2 bit for 'icc' | |
| 2495 ($primary << 14) | | |
| 2496 (0 << 13) | // select register move | |
| 2497 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2498 ($src$$reg << 0); | |
| 1748 | 2499 cbuf.insts()->emit_int32(op); |
| 0 | 2500 %} |
| 2501 | |
| 2502 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2503 int op = (Assembler::arith_op << 30) | | |
| 2504 ($dst$$reg << 25) | | |
| 2505 (Assembler::movcc_op3 << 19) | | |
| 2506 (6 << 16) | // cc2 bit for 'xcc' | |
| 2507 ($primary << 14) | | |
| 2508 (0 << 13) | // select register move | |
| 2509 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2510 ($src$$reg << 0); | |
| 1748 | 2511 cbuf.insts()->emit_int32(op); |
| 0 | 2512 %} |
| 2513 | |
| 2514 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2515 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2516 %} | |
| 2517 | |
| 2518 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2519 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2520 %} | |
| 2521 | |
| 2522 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2523 MacroAssembler _masm(&cbuf); | |
| 2524 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2525 %} | |
| 2526 | |
| 2527 enc_class call_epilog %{ | |
| 2528 if( VerifyStackAtCalls ) { | |
| 2529 MacroAssembler _masm(&cbuf); | |
| 2530 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2531 Register temp_reg = G3; | |
| 2532 __ add(SP, framesize, temp_reg); | |
| 2533 __ cmp(temp_reg, FP); | |
| 2534 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2535 } | |
| 2536 %} | |
| 2537 | |
| 2538 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2539 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2540 // pair. | |
| 2541 enc_class adjust_long_from_native_call %{ | |
| 2542 #ifndef _LP64 | |
| 2543 if (returns_long()) { | |
| 2544 // sllx O0,32,O0 | |
| 2545 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2546 // srl O1,0,O1 | |
| 2547 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2548 // or O0,O1,G1 | |
| 2549 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2550 } | |
| 2551 #endif | |
| 2552 %} | |
| 2553 | |
| 2554 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2555 // CALL directly to the runtime | |
| 2556 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2557 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
2558 /*preserve_g2=*/true); |
| 0 | 2559 %} |
| 2560 | |
| 1567 | 2561 enc_class preserve_SP %{ |
| 2562 MacroAssembler _masm(&cbuf); | |
| 2563 __ mov(SP, L7_mh_SP_save); | |
| 2564 %} | |
| 2565 | |
| 2566 enc_class restore_SP %{ | |
| 2567 MacroAssembler _masm(&cbuf); | |
| 2568 __ mov(L7_mh_SP_save, SP); | |
| 2569 %} | |
| 2570 | |
| 0 | 2571 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2572 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2573 // who we intended to call. | |
| 2574 if ( !_method ) { | |
| 2575 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2576 } else if (_optimized_virtual) { | |
| 2577 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2578 } else { | |
| 2579 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2580 } | |
| 2581 if( _method ) { // Emit stub for static call | |
| 2582 emit_java_to_interp(cbuf); | |
| 2583 } | |
| 2584 %} | |
| 2585 | |
| 2586 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2587 MacroAssembler _masm(&cbuf); | |
| 2588 __ set_inst_mark(); | |
| 2589 int vtable_index = this->_vtable_index; | |
| 2590 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2591 if (vtable_index < 0) { | |
| 2592 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2593 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2594 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2595 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2596 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2597 // !!!!! | |
| 2598 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2599 // emit_call_dynamic_prologue( cbuf ); | |
| 2600 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2601 | |
| 2602 address virtual_call_oop_addr = __ inst_mark(); | |
| 2603 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2604 // who we intended to call. | |
| 2605 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2606 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2607 } else { | |
| 2608 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2609 // Just go thru the vtable | |
| 2610 // get receiver klass (receiver already checked for non-null) | |
| 2611 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2612 int off = __ offset(); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2613 __ load_klass(O0, G3_scratch); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2614 int klass_load_size; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2615 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2616 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2617 if (Universe::narrow_oop_base() == NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2618 klass_load_size = 2*BytesPerInstWord; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2619 else |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2620 klass_load_size = 3*BytesPerInstWord; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2621 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2622 klass_load_size = 1*BytesPerInstWord; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2623 } |
| 0 | 2624 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2625 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2626 if (Assembler::is_simm13(v_off)) { |
| 0 | 2627 __ ld_ptr(G3, v_off, G5_method); |
| 2628 } else { | |
| 2629 // Generate 2 instructions | |
| 2630 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2631 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2632 // ld_ptr, set_hi, set | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2633 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2634 "Unexpected instruction size(s)"); |
| 0 | 2635 __ ld_ptr(G3, G5_method, G5_method); |
| 2636 } | |
| 2637 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2638 // However it may very well end up in handle_wrong_method if the | |
| 2639 // method is abstract for the particular class. | |
| 2640 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2641 // jump to target (either compiled code or c2iadapter) | |
| 2642 __ jmpl(G3_scratch, G0, O7); | |
| 2643 __ delayed()->nop(); | |
| 2644 } | |
| 2645 %} | |
| 2646 | |
| 2647 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2648 MacroAssembler _masm(&cbuf); | |
| 2649 | |
| 2650 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2651 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2652 // we might be calling a C2I adapter which needs it. | |
| 2653 | |
| 2654 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2655 // Load nmethod | |
| 2656 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2657 | |
| 2658 // CALL to compiled java, indirect the contents of G3 | |
| 2659 __ set_inst_mark(); | |
| 2660 __ callr(temp_reg, G0); | |
| 2661 __ delayed()->nop(); | |
| 2662 %} | |
| 2663 | |
| 2664 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2665 MacroAssembler _masm(&cbuf); | |
| 2666 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2667 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2668 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2669 | |
| 2670 __ sra(Rdivisor, 0, Rdivisor); | |
| 2671 __ sra(Rdividend, 0, Rdividend); | |
| 2672 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2673 %} | |
| 2674 | |
| 2675 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2676 MacroAssembler _masm(&cbuf); | |
| 2677 | |
| 2678 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2679 int divisor = $imm$$constant; | |
| 2680 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2681 | |
| 2682 __ sra(Rdividend, 0, Rdividend); | |
| 2683 __ sdivx(Rdividend, divisor, Rresult); | |
| 2684 %} | |
| 2685 | |
| 2686 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2687 MacroAssembler _masm(&cbuf); | |
| 2688 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2689 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2690 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2691 | |
| 2692 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2693 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2694 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2695 __ srlx( Rdst, 32, Rdst ); | |
| 2696 %} | |
| 2697 | |
| 2698 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2699 MacroAssembler _masm(&cbuf); | |
| 2700 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2701 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2702 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2703 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2704 | |
| 2705 assert(Rdividend != Rscratch, ""); | |
| 2706 assert(Rdivisor != Rscratch, ""); | |
| 2707 | |
| 2708 __ sra(Rdividend, 0, Rdividend); | |
| 2709 __ sra(Rdivisor, 0, Rdivisor); | |
| 2710 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2711 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2712 __ sub(Rdividend, Rscratch, Rresult); | |
| 2713 %} | |
| 2714 | |
| 2715 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2716 MacroAssembler _masm(&cbuf); | |
| 2717 | |
| 2718 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2719 int divisor = $imm$$constant; | |
| 2720 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2721 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2722 | |
| 2723 assert(Rdividend != Rscratch, ""); | |
| 2724 | |
| 2725 __ sra(Rdividend, 0, Rdividend); | |
| 2726 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2727 __ mulx(Rscratch, divisor, Rscratch); | |
| 2728 __ sub(Rdividend, Rscratch, Rresult); | |
| 2729 %} | |
| 2730 | |
| 2731 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2732 MacroAssembler _masm(&cbuf); | |
| 2733 | |
| 2734 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2735 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2736 | |
| 2737 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2738 %} | |
| 2739 | |
| 2740 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2741 MacroAssembler _masm(&cbuf); | |
| 2742 | |
| 2743 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2744 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2745 | |
| 2746 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2747 %} | |
| 2748 | |
| 2749 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2750 MacroAssembler _masm(&cbuf); | |
| 2751 | |
| 2752 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2753 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2754 | |
| 2755 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2756 %} | |
| 2757 | |
| 2758 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2759 MacroAssembler _masm(&cbuf); | |
| 2760 | |
| 2761 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2762 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2763 | |
| 2764 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2765 %} | |
| 2766 | |
| 2767 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2768 MacroAssembler _masm(&cbuf); | |
| 2769 | |
| 2770 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2771 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2772 | |
| 2773 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2774 %} | |
| 2775 | |
| 2776 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2777 MacroAssembler _masm(&cbuf); | |
| 2778 | |
| 2779 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2780 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2781 | |
| 2782 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2783 %} | |
| 2784 | |
| 2785 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2786 MacroAssembler _masm(&cbuf); | |
| 2787 | |
| 2788 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2789 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2790 | |
| 2791 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2792 %} | |
| 2793 | |
| 2794 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2795 MacroAssembler _masm(&cbuf); | |
| 2796 | |
| 2797 Register Roop = reg_to_register_object($oop$$reg); | |
| 2798 Register Rbox = reg_to_register_object($box$$reg); | |
| 2799 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2800 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2801 | |
| 2802 assert(Roop != Rscratch, ""); | |
| 2803 assert(Roop != Rmark, ""); | |
| 2804 assert(Rbox != Rscratch, ""); | |
| 2805 assert(Rbox != Rmark, ""); | |
| 2806 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2807 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2808 %} |
| 2809 | |
| 2810 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2811 MacroAssembler _masm(&cbuf); | |
| 2812 | |
| 2813 Register Roop = reg_to_register_object($oop$$reg); | |
| 2814 Register Rbox = reg_to_register_object($box$$reg); | |
| 2815 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2816 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2817 | |
| 2818 assert(Roop != Rscratch, ""); | |
| 2819 assert(Roop != Rmark, ""); | |
| 2820 assert(Rbox != Rscratch, ""); | |
| 2821 assert(Rbox != Rmark, ""); | |
| 2822 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2823 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2824 %} |
| 2825 | |
| 2826 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2827 MacroAssembler _masm(&cbuf); | |
| 2828 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2829 Register Rold = reg_to_register_object($old$$reg); | |
| 2830 Register Rnew = reg_to_register_object($new$$reg); | |
| 2831 | |
| 2832 // casx_under_lock picks 1 of 3 encodings: | |
| 2833 // For 32-bit pointers you get a 32-bit CAS | |
| 2834 // For 64-bit pointers you get a 64-bit CASX | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2835 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2836 __ cmp( Rold, Rnew ); |
| 2837 %} | |
| 2838 | |
| 2839 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2840 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2841 Register Rold = reg_to_register_object($old$$reg); | |
| 2842 Register Rnew = reg_to_register_object($new$$reg); | |
| 2843 | |
| 2844 MacroAssembler _masm(&cbuf); | |
| 2845 __ mov(Rnew, O7); | |
| 2846 __ casx(Rmem, Rold, O7); | |
| 2847 __ cmp( Rold, O7 ); | |
| 2848 %} | |
| 2849 | |
| 2850 // raw int cas, used for compareAndSwap | |
| 2851 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2852 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2853 Register Rold = reg_to_register_object($old$$reg); | |
| 2854 Register Rnew = reg_to_register_object($new$$reg); | |
| 2855 | |
| 2856 MacroAssembler _masm(&cbuf); | |
| 2857 __ mov(Rnew, O7); | |
| 2858 __ cas(Rmem, Rold, O7); | |
| 2859 __ cmp( Rold, O7 ); | |
| 2860 %} | |
| 2861 | |
| 2862 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2863 Register Rres = reg_to_register_object($res$$reg); | |
| 2864 | |
| 2865 MacroAssembler _masm(&cbuf); | |
| 2866 __ mov(1, Rres); | |
| 2867 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2868 %} | |
| 2869 | |
| 2870 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2871 Register Rres = reg_to_register_object($res$$reg); | |
| 2872 | |
| 2873 MacroAssembler _masm(&cbuf); | |
| 2874 __ mov(1, Rres); | |
| 2875 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2876 %} | |
| 2877 | |
| 2878 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2879 MacroAssembler _masm(&cbuf); | |
| 2880 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2881 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2882 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2883 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2884 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2885 | |
| 2886 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2887 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2888 %} | |
| 2889 | |
| 2890 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2891 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2892 Label Ldone, Lloop; |
| 2893 MacroAssembler _masm(&cbuf); | |
| 2894 | |
| 2895 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2896 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2897 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2898 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2899 Register result_reg = reg_to_register_object($result$$reg); |
| 2900 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2901 assert(result_reg != str1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2902 result_reg != str2_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2903 result_reg != cnt1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2904 result_reg != cnt2_reg , |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2905 "need different registers"); |
| 0 | 2906 |
| 2907 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2908 // difference of the string lengths (stack) | |
| 2909 | |
| 2910 // See if the lengths are different, and calculate min in str1_reg. | |
| 2911 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2912 Label Lskip; | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2913 __ subcc(cnt1_reg, cnt2_reg, O7); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2914 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2915 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2916 // cnt2 is shorter, so use its count: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2917 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2918 __ bind(Lskip); |
| 2919 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2920 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2921 // Note: limit_reg holds the string length pre-scaled by 2 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2922 Register limit_reg = cnt1_reg; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2923 Register chr2_reg = cnt2_reg; |
| 0 | 2924 Register chr1_reg = result_reg; |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2925 // str{12} are the base pointers |
| 0 | 2926 |
| 2927 // Is the minimum length zero? | |
| 2928 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2929 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2930 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2931 | |
| 2932 // Load first characters | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2933 __ lduh(str1_reg, 0, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2934 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2935 |
| 2936 // Compare first characters | |
| 2937 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2938 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2939 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2940 __ delayed()->nop(); | |
| 2941 | |
| 2942 { | |
| 2943 // Check after comparing first character to see if strings are equivalent | |
| 2944 Label LSkip2; | |
| 2945 // Check if the strings start at same location | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2946 __ cmp(str1_reg, str2_reg); |
| 0 | 2947 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2948 __ delayed()->nop(); | |
| 2949 | |
| 2950 // Check if the length difference is zero (in O7) | |
| 2951 __ cmp(G0, O7); | |
| 2952 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2953 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2954 | |
| 2955 // Strings might not be equal | |
| 2956 __ bind(LSkip2); | |
| 2957 } | |
| 2958 | |
| 2959 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2960 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2961 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2962 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2963 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2964 __ add(str1_reg, limit_reg, str1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2965 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2966 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2967 | |
| 2968 // Compare the rest of the characters | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2969 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2970 __ bind(Lloop); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2971 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2972 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2973 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2974 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2975 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2976 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2977 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2978 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2979 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2980 |
| 2981 // If strings are equal up to min length, return the length difference. | |
| 2982 __ mov(O7, result_reg); | |
| 2983 | |
| 2984 // Otherwise, return the difference between the first mismatched chars. | |
| 2985 __ bind(Ldone); | |
| 2986 %} | |
| 2987 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2988 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2989 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2990 MacroAssembler _masm(&cbuf); |
| 2991 | |
| 2992 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2993 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2994 Register cnt_reg = reg_to_register_object($cnt$$reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2995 Register tmp1_reg = O7; |
| 681 | 2996 Register result_reg = reg_to_register_object($result$$reg); |
| 2997 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2998 assert(result_reg != str1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2999 result_reg != str2_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3000 result_reg != cnt_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3001 result_reg != tmp1_reg , |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3002 "need different registers"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3003 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3004 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 3005 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 3006 __ delayed()->add(G0, 1, result_reg); | |
| 3007 | |
| 3839 | 3008 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3009 __ delayed()->add(G0, 1, result_reg); // count == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3010 |
| 681 | 3011 //rename registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3012 Register limit_reg = cnt_reg; |
| 681 | 3013 Register chr1_reg = result_reg; |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3014 Register chr2_reg = tmp1_reg; |
| 681 | 3015 |
| 3016 //check for alignment and position the pointers to the ends | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3017 __ or3(str1_reg, str2_reg, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3018 __ andcc(chr1_reg, 0x3, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3019 // notZero means at least one not 4-byte aligned. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3020 // We could optimize the case when both arrays are not aligned |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3021 // but it is not frequent case and it requires additional checks. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3022 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3023 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3024 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3025 // Compare char[] arrays aligned to 4 bytes. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3026 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3027 chr1_reg, chr2_reg, Ldone); |
| 3839 | 3028 __ ba(Ldone); |
| 681 | 3029 __ delayed()->add(G0, 1, result_reg); |
| 3030 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3031 // char by char compare |
| 681 | 3032 __ bind(Lchar); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3033 __ add(str1_reg, limit_reg, str1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3034 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 3035 __ neg(limit_reg); //negate count |
| 3036 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3037 __ lduh(str1_reg, limit_reg, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3038 // Lchar_loop |
| 681 | 3039 __ bind(Lchar_loop); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3040 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 3041 __ cmp(chr1_reg, chr2_reg); |
| 3042 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 3043 __ delayed()->mov(G0, result_reg); //not equal | |
| 3044 __ inccc(limit_reg, sizeof(jchar)); | |
| 3045 // annul LDUH if branch is not taken to prevent access past end of string | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3046 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3047 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 3048 |
| 3049 __ add(G0, 1, result_reg); //equal | |
| 3050 | |
| 3051 __ bind(Ldone); | |
| 3052 %} | |
| 3053 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3054 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 3055 Label Lvector, Ldone, Lloop; |
| 3056 MacroAssembler _masm(&cbuf); | |
| 3057 | |
| 3058 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3059 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3060 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3061 Register tmp2_reg = O7; |
| 681 | 3062 Register result_reg = reg_to_register_object($result$$reg); |
| 3063 | |
| 3064 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3065 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3066 | |
| 3067 // return true if the same array | |
| 3068 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3069 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3070 __ delayed()->add(G0, 1, result_reg); // equal |
| 3071 | |
| 3072 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3073 __ delayed()->mov(G0, result_reg); // not equal | |
| 3074 | |
| 3075 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3076 __ delayed()->mov(G0, result_reg); // not equal | |
| 3077 | |
| 3078 //load the lengths of arrays | |
| 727 | 3079 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3080 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3081 |
| 3082 // return false if the two arrays are not equal length | |
| 3083 __ cmp(tmp1_reg, tmp2_reg); | |
| 3084 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3085 __ delayed()->mov(G0, result_reg); // not equal | |
| 3086 | |
| 3839 | 3087 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
| 681 | 3088 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3089 | |
| 3090 // load array addresses | |
| 3091 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3092 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3093 | |
| 3094 // renaming registers | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3095 Register chr1_reg = result_reg; // for characters in ary1 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3096 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3097 Register limit_reg = tmp1_reg; // length |
| 3098 | |
| 3099 // set byte count | |
| 3100 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3101 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3102 // Compare char[] arrays aligned to 4 bytes. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3103 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3104 chr1_reg, chr2_reg, Ldone); |
| 681 | 3105 __ add(G0, 1, result_reg); // equals |
| 3106 | |
| 3107 __ bind(Ldone); | |
| 3108 %} | |
| 3109 | |
| 0 | 3110 enc_class enc_rethrow() %{ |
| 1748 | 3111 cbuf.set_insts_mark(); |
| 0 | 3112 Register temp_reg = G3; |
| 727 | 3113 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3114 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3115 MacroAssembler _masm(&cbuf); | |
| 3116 #ifdef ASSERT | |
| 3117 __ save_frame(0); | |
| 727 | 3118 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3119 __ sethi(last_rethrow_addrlit, L1); | |
| 3120 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3121 __ get_pc(L2); |
| 3122 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3123 __ st_ptr(L2, addr); |
| 0 | 3124 __ restore(); |
| 3125 #endif | |
| 727 | 3126 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3127 __ delayed()->nop(); |
| 3128 %} | |
| 3129 | |
| 3130 enc_class emit_mem_nop() %{ | |
| 3131 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3132 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3133 %} |
| 3134 | |
| 3135 enc_class emit_fadd_nop() %{ | |
| 3136 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3137 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3138 %} |
| 3139 | |
| 3140 enc_class emit_br_nop() %{ | |
| 3141 // Generates the instruction BPN,PN . | |
| 1748 | 3142 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3143 %} |
| 3144 | |
| 3145 enc_class enc_membar_acquire %{ | |
| 3146 MacroAssembler _masm(&cbuf); | |
| 3147 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3148 %} | |
| 3149 | |
| 3150 enc_class enc_membar_release %{ | |
| 3151 MacroAssembler _masm(&cbuf); | |
| 3152 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3153 %} | |
| 3154 | |
| 3155 enc_class enc_membar_volatile %{ | |
| 3156 MacroAssembler _masm(&cbuf); | |
| 3157 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3158 %} | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3159 |
| 0 | 3160 %} |
| 3161 | |
| 3162 //----------FRAME-------------------------------------------------------------- | |
| 3163 // Definition of frame structure and management information. | |
| 3164 // | |
| 3165 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3166 // | (to get allocators register number | |
| 3167 // G Owned by | | v add VMRegImpl::stack0) | |
| 3168 // r CALLER | | | |
| 3169 // o | +--------+ pad to even-align allocators stack-slot | |
| 3170 // w V | pad0 | numbers; owned by CALLER | |
| 3171 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3172 // h ^ | in | 5 | |
| 3173 // | | args | 4 Holes in incoming args owned by SELF | |
| 3174 // | | | | 3 | |
| 3175 // | | +--------+ | |
| 3176 // V | | old out| Empty on Intel, window on Sparc | |
| 3177 // | old |preserve| Must be even aligned. | |
| 3178 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3179 // | | in | 3 area for Intel ret address | |
| 3180 // Owned by |preserve| Empty on Sparc. | |
| 3181 // SELF +--------+ | |
| 3182 // | | pad2 | 2 pad to align old SP | |
| 3183 // | +--------+ 1 | |
| 3184 // | | locks | 0 | |
| 3185 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3186 // | | pad1 | 11 pad to align new SP | |
| 3187 // | +--------+ | |
| 3188 // | | | 10 | |
| 3189 // | | spills | 9 spills | |
| 3190 // V | | 8 (pad0 slot for callee) | |
| 3191 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3192 // ^ | out | 7 | |
| 3193 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3194 // Owned by +--------+ | |
| 3195 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3196 // | new |preserve| Must be even-aligned. | |
| 3197 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3198 // | | | | |
| 3199 // | |
| 3200 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3201 // known from SELF's arguments and the Java calling convention. | |
| 3202 // Region 6-7 is determined per call site. | |
| 3203 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3204 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3205 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3206 // incoming area, as the Java calling convention is completely under | |
| 3207 // the control of the AD file. Doubles can be sorted and packed to | |
| 3208 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3209 // varargs C calling conventions. | |
| 3210 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3211 // even aligned with pad0 as needed. | |
| 3212 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3213 // region 6-11 is even aligned; it may be padded out more so that | |
| 3214 // the region from SP to FP meets the minimum stack alignment. | |
| 3215 | |
| 3216 frame %{ | |
| 3217 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3218 stack_direction(TOWARDS_LOW); | |
| 3219 | |
| 3220 // These two registers define part of the calling convention | |
| 3221 // between compiled code and the interpreter. | |
| 3222 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3223 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3224 | |
| 3225 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3226 cisc_spilling_operand_name(indOffset); | |
| 3227 | |
| 3228 // Number of stack slots consumed by a Monitor enter | |
| 3229 #ifdef _LP64 | |
| 3230 sync_stack_slots(2); | |
| 3231 #else | |
| 3232 sync_stack_slots(1); | |
| 3233 #endif | |
| 3234 | |
| 3235 // Compiled code's Frame Pointer | |
| 3236 frame_pointer(R_SP); | |
| 3237 | |
| 3238 // Stack alignment requirement | |
| 3239 stack_alignment(StackAlignmentInBytes); | |
| 3240 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3241 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3242 | |
| 3243 // Number of stack slots between incoming argument block and the start of | |
| 3244 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3245 // EPILOG must remove this many slots. | |
| 3246 in_preserve_stack_slots(0); | |
| 3247 | |
| 3248 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3249 // for calls to C. Supports the var-args backing area for register parms. | |
| 3250 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3251 #ifdef _LP64 | |
| 3252 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3253 varargs_C_out_slots_killed(12); | |
| 3254 #else | |
| 3255 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3256 varargs_C_out_slots_killed( 7); | |
| 3257 #endif | |
| 3258 | |
| 3259 // The after-PROLOG location of the return address. Location of | |
| 3260 // return address specifies a type (REG or STACK) and a number | |
| 3261 // representing the register number (i.e. - use a register name) or | |
| 3262 // stack slot. | |
| 3263 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3264 | |
| 3265 // Body of function which returns an OptoRegs array locating | |
| 3266 // arguments either in registers or in stack slots for calling | |
| 3267 // java | |
| 3268 calling_convention %{ | |
| 3269 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3270 | |
| 3271 %} | |
| 3272 | |
| 3273 // Body of function which returns an OptoRegs array locating | |
| 3274 // arguments either in registers or in stack slots for callin | |
| 3275 // C. | |
| 3276 c_calling_convention %{ | |
| 3277 // This is obviously always outgoing | |
| 3278 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3279 %} | |
| 3280 | |
| 3281 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3282 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3283 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3284 // to and from the register pairs is done by the appropriate call and epilog | |
| 3285 // opcodes. This simplifies the register allocator. | |
| 3286 c_return_value %{ | |
| 3287 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3288 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3289 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3290 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3291 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3292 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3293 #else // !_LP64 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3294 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3295 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3296 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3297 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3298 #endif |
| 3299 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3300 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3301 %} | |
| 3302 | |
| 3303 // Location of compiled Java return values. Same as C | |
| 3304 return_value %{ | |
| 3305 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3306 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3307 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3308 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3309 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3310 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3311 #else // !_LP64 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3312 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3313 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3314 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3315 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3316 #endif |
| 3317 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3318 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3319 %} | |
| 3320 | |
| 3321 %} | |
| 3322 | |
| 3323 | |
| 3324 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3325 //----------Operand Attributes------------------------------------------------- | |
| 3326 op_attrib op_cost(1); // Required cost attribute | |
| 3327 | |
| 3328 //----------Instruction Attributes--------------------------------------------- | |
| 3329 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3842 | 3330 ins_attrib ins_size(32); // Required size attribute (in bits) |
| 3851 | 3331 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
| 3842 | 3332 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
| 3333 // non-matching short branch variant of some | |
| 0 | 3334 // long branch? |
| 3335 | |
| 3336 //----------OPERANDS----------------------------------------------------------- | |
| 3337 // Operand definitions must precede instruction definitions for correct parsing | |
| 3338 // in the ADLC because operands constitute user defined types which are used in | |
| 3339 // instruction definitions. | |
| 3340 | |
| 3341 //----------Simple Operands---------------------------------------------------- | |
| 3342 // Immediate Operands | |
| 3343 // Integer Immediate: 32-bit | |
| 3344 operand immI() %{ | |
| 3345 match(ConI); | |
| 3346 | |
| 3347 op_cost(0); | |
| 3348 // formats are generated automatically for constants and base registers | |
| 3349 format %{ %} | |
| 3350 interface(CONST_INTER); | |
| 3351 %} | |
| 3352 | |
| 824 | 3353 // Integer Immediate: 8-bit |
| 3354 operand immI8() %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3355 predicate(Assembler::is_simm8(n->get_int())); |
| 824 | 3356 match(ConI); |
| 3357 op_cost(0); | |
| 3358 format %{ %} | |
| 3359 interface(CONST_INTER); | |
| 3360 %} | |
| 3361 | |
| 0 | 3362 // Integer Immediate: 13-bit |
| 3363 operand immI13() %{ | |
| 3364 predicate(Assembler::is_simm13(n->get_int())); | |
| 3365 match(ConI); | |
| 3366 op_cost(0); | |
| 3367 | |
| 3368 format %{ %} | |
| 3369 interface(CONST_INTER); | |
| 3370 %} | |
| 3371 | |
| 785 | 3372 // Integer Immediate: 13-bit minus 7 |
| 3373 operand immI13m7() %{ | |
| 3374 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3375 match(ConI); | |
| 3376 op_cost(0); | |
| 3377 | |
| 3378 format %{ %} | |
| 3379 interface(CONST_INTER); | |
| 3380 %} | |
| 3381 | |
| 824 | 3382 // Integer Immediate: 16-bit |
| 3383 operand immI16() %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3384 predicate(Assembler::is_simm16(n->get_int())); |
| 824 | 3385 match(ConI); |
| 3386 op_cost(0); | |
| 3387 format %{ %} | |
| 3388 interface(CONST_INTER); | |
| 3389 %} | |
| 3390 | |
| 0 | 3391 // Unsigned (positive) Integer Immediate: 13-bit |
| 3392 operand immU13() %{ | |
| 3393 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3394 match(ConI); | |
| 3395 op_cost(0); | |
| 3396 | |
| 3397 format %{ %} | |
| 3398 interface(CONST_INTER); | |
| 3399 %} | |
| 3400 | |
| 3401 // Integer Immediate: 6-bit | |
| 3402 operand immU6() %{ | |
| 3403 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3404 match(ConI); | |
| 3405 op_cost(0); | |
| 3406 format %{ %} | |
| 3407 interface(CONST_INTER); | |
| 3408 %} | |
| 3409 | |
| 3410 // Integer Immediate: 11-bit | |
| 3411 operand immI11() %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3412 predicate(Assembler::is_simm11(n->get_int())); |
| 0 | 3413 match(ConI); |
| 3414 op_cost(0); | |
| 3415 format %{ %} | |
| 3416 interface(CONST_INTER); | |
| 3417 %} | |
| 3418 | |
| 3851 | 3419 // Integer Immediate: 5-bit |
| 3420 operand immI5() %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3421 predicate(Assembler::is_simm5(n->get_int())); |
| 3851 | 3422 match(ConI); |
| 3423 op_cost(0); | |
| 3424 format %{ %} | |
| 3425 interface(CONST_INTER); | |
| 3426 %} | |
| 3427 | |
| 0 | 3428 // Integer Immediate: 0-bit |
| 3429 operand immI0() %{ | |
| 3430 predicate(n->get_int() == 0); | |
| 3431 match(ConI); | |
| 3432 op_cost(0); | |
| 3433 | |
| 3434 format %{ %} | |
| 3435 interface(CONST_INTER); | |
| 3436 %} | |
| 3437 | |
| 3438 // Integer Immediate: the value 10 | |
| 3439 operand immI10() %{ | |
| 3440 predicate(n->get_int() == 10); | |
| 3441 match(ConI); | |
| 3442 op_cost(0); | |
| 3443 | |
| 3444 format %{ %} | |
| 3445 interface(CONST_INTER); | |
| 3446 %} | |
| 3447 | |
| 3448 // Integer Immediate: the values 0-31 | |
| 3449 operand immU5() %{ | |
| 3450 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3451 match(ConI); | |
| 3452 op_cost(0); | |
| 3453 | |
| 3454 format %{ %} | |
| 3455 interface(CONST_INTER); | |
| 3456 %} | |
| 3457 | |
| 3458 // Integer Immediate: the values 1-31 | |
| 3459 operand immI_1_31() %{ | |
| 3460 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3461 match(ConI); | |
| 3462 op_cost(0); | |
| 3463 | |
| 3464 format %{ %} | |
| 3465 interface(CONST_INTER); | |
| 3466 %} | |
| 3467 | |
| 3468 // Integer Immediate: the values 32-63 | |
| 3469 operand immI_32_63() %{ | |
| 3470 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3471 match(ConI); | |
| 3472 op_cost(0); | |
| 3473 | |
| 3474 format %{ %} | |
| 3475 interface(CONST_INTER); | |
| 3476 %} | |
| 3477 | |
| 785 | 3478 // Immediates for special shifts (sign extend) |
| 3479 | |
| 3480 // Integer Immediate: the value 16 | |
| 3481 operand immI_16() %{ | |
| 3482 predicate(n->get_int() == 16); | |
| 3483 match(ConI); | |
| 3484 op_cost(0); | |
| 3485 | |
| 3486 format %{ %} | |
| 3487 interface(CONST_INTER); | |
| 3488 %} | |
| 3489 | |
| 3490 // Integer Immediate: the value 24 | |
| 3491 operand immI_24() %{ | |
| 3492 predicate(n->get_int() == 24); | |
| 3493 match(ConI); | |
| 3494 op_cost(0); | |
| 3495 | |
| 3496 format %{ %} | |
| 3497 interface(CONST_INTER); | |
| 3498 %} | |
| 3499 | |
| 0 | 3500 // Integer Immediate: the value 255 |
| 3501 operand immI_255() %{ | |
| 3502 predicate( n->get_int() == 255 ); | |
| 3503 match(ConI); | |
| 3504 op_cost(0); | |
| 3505 | |
| 3506 format %{ %} | |
| 3507 interface(CONST_INTER); | |
| 3508 %} | |
| 3509 | |
| 785 | 3510 // Integer Immediate: the value 65535 |
| 3511 operand immI_65535() %{ | |
| 3512 predicate(n->get_int() == 65535); | |
| 3513 match(ConI); | |
| 3514 op_cost(0); | |
| 3515 | |
| 3516 format %{ %} | |
| 3517 interface(CONST_INTER); | |
| 3518 %} | |
| 3519 | |
| 0 | 3520 // Long Immediate: the value FF |
| 3521 operand immL_FF() %{ | |
| 3522 predicate( n->get_long() == 0xFFL ); | |
| 3523 match(ConL); | |
| 3524 op_cost(0); | |
| 3525 | |
| 3526 format %{ %} | |
| 3527 interface(CONST_INTER); | |
| 3528 %} | |
| 3529 | |
| 3530 // Long Immediate: the value FFFF | |
| 3531 operand immL_FFFF() %{ | |
| 3532 predicate( n->get_long() == 0xFFFFL ); | |
| 3533 match(ConL); | |
| 3534 op_cost(0); | |
| 3535 | |
| 3536 format %{ %} | |
| 3537 interface(CONST_INTER); | |
| 3538 %} | |
| 3539 | |
| 3540 // Pointer Immediate: 32 or 64-bit | |
| 3541 operand immP() %{ | |
| 3542 match(ConP); | |
| 3543 | |
| 3544 op_cost(5); | |
| 3545 // formats are generated automatically for constants and base registers | |
| 3546 format %{ %} | |
| 3547 interface(CONST_INTER); | |
| 3548 %} | |
| 3549 | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3550 #ifdef _LP64 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3551 // Pointer Immediate: 64-bit |
| 2008 | 3552 operand immP_set() %{ |
| 2080 | 3553 predicate(!VM_Version::is_niagara_plus()); |
| 2008 | 3554 match(ConP); |
| 3555 | |
| 3556 op_cost(5); | |
| 3557 // formats are generated automatically for constants and base registers | |
| 3558 format %{ %} | |
| 3559 interface(CONST_INTER); | |
| 3560 %} | |
| 3561 | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3562 // Pointer Immediate: 64-bit |
| 2008 | 3563 // From Niagara2 processors on a load should be better than materializing. |
| 3564 operand immP_load() %{ | |
| 2080 | 3565 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
| 2008 | 3566 match(ConP); |
| 3567 | |
| 3568 op_cost(5); | |
| 3569 // formats are generated automatically for constants and base registers | |
| 3570 format %{ %} | |
| 3571 interface(CONST_INTER); | |
| 3572 %} | |
| 3573 | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3574 // Pointer Immediate: 64-bit |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3575 operand immP_no_oop_cheap() %{ |
| 2080 | 3576 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3577 match(ConP); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3578 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3579 op_cost(5); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3580 // formats are generated automatically for constants and base registers |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3581 format %{ %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3582 interface(CONST_INTER); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3583 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3584 #endif |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3585 |
| 0 | 3586 operand immP13() %{ |
| 3587 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3588 match(ConP); | |
| 3589 op_cost(0); | |
| 3590 | |
| 3591 format %{ %} | |
| 3592 interface(CONST_INTER); | |
| 3593 %} | |
| 3594 | |
| 3595 operand immP0() %{ | |
| 3596 predicate(n->get_ptr() == 0); | |
| 3597 match(ConP); | |
| 3598 op_cost(0); | |
| 3599 | |
| 3600 format %{ %} | |
| 3601 interface(CONST_INTER); | |
| 3602 %} | |
| 3603 | |
| 3604 operand immP_poll() %{ | |
| 3605 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3606 match(ConP); | |
| 3607 | |
| 3608 // formats are generated automatically for constants and base registers | |
| 3609 format %{ %} | |
| 3610 interface(CONST_INTER); | |
| 3611 %} | |
| 3612 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3613 // Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3614 operand immN() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3615 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3616 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3617 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3618 op_cost(10); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3619 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3620 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3621 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3622 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3623 // NULL Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3624 operand immN0() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3625 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3626 predicate(n->get_narrowcon() == 0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3627 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3628 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3629 op_cost(0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3630 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3631 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3632 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3633 |
| 0 | 3634 operand immL() %{ |
| 3635 match(ConL); | |
| 3636 op_cost(40); | |
| 3637 // formats are generated automatically for constants and base registers | |
| 3638 format %{ %} | |
| 3639 interface(CONST_INTER); | |
| 3640 %} | |
| 3641 | |
| 3642 operand immL0() %{ | |
| 3643 predicate(n->get_long() == 0L); | |
| 3644 match(ConL); | |
| 3645 op_cost(0); | |
| 3646 // formats are generated automatically for constants and base registers | |
| 3647 format %{ %} | |
| 3648 interface(CONST_INTER); | |
| 3649 %} | |
| 3650 | |
| 3851 | 3651 // Integer Immediate: 5-bit |
| 3652 operand immL5() %{ | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3653 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
| 3851 | 3654 match(ConL); |
| 3655 op_cost(0); | |
| 3656 format %{ %} | |
| 3657 interface(CONST_INTER); | |
| 3658 %} | |
| 3659 | |
| 0 | 3660 // Long Immediate: 13-bit |
| 3661 operand immL13() %{ | |
| 3662 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3663 match(ConL); | |
| 3664 op_cost(0); | |
| 3665 | |
| 3666 format %{ %} | |
| 3667 interface(CONST_INTER); | |
| 3668 %} | |
| 3669 | |
| 785 | 3670 // Long Immediate: 13-bit minus 7 |
| 3671 operand immL13m7() %{ | |
| 3672 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3673 match(ConL); | |
| 3674 op_cost(0); | |
| 3675 | |
| 3676 format %{ %} | |
| 3677 interface(CONST_INTER); | |
| 3678 %} | |
| 3679 | |
| 0 | 3680 // Long Immediate: low 32-bit mask |
| 3681 operand immL_32bits() %{ | |
| 3682 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3683 match(ConL); | |
| 3684 op_cost(0); | |
| 3685 | |
| 3686 format %{ %} | |
| 3687 interface(CONST_INTER); | |
| 3688 %} | |
| 3689 | |
| 2008 | 3690 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3691 operand immL_cheap() %{ | |
| 2080 | 3692 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
| 2008 | 3693 match(ConL); |
| 3694 op_cost(0); | |
| 3695 | |
| 3696 format %{ %} | |
| 3697 interface(CONST_INTER); | |
| 3698 %} | |
| 3699 | |
| 3700 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3701 operand immL_expensive() %{ | |
| 2080 | 3702 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
| 2008 | 3703 match(ConL); |
| 3704 op_cost(0); | |
| 3705 | |
| 3706 format %{ %} | |
| 3707 interface(CONST_INTER); | |
| 3708 %} | |
| 3709 | |
| 0 | 3710 // Double Immediate |
| 3711 operand immD() %{ | |
| 3712 match(ConD); | |
| 3713 | |
| 3714 op_cost(40); | |
| 3715 format %{ %} | |
| 3716 interface(CONST_INTER); | |
| 3717 %} | |
| 3718 | |
| 3719 operand immD0() %{ | |
| 3720 #ifdef _LP64 | |
| 3721 // on 64-bit architectures this comparision is faster | |
| 3722 predicate(jlong_cast(n->getd()) == 0); | |
| 3723 #else | |
| 3724 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3725 #endif | |
| 3726 match(ConD); | |
| 3727 | |
| 3728 op_cost(0); | |
| 3729 format %{ %} | |
| 3730 interface(CONST_INTER); | |
| 3731 %} | |
| 3732 | |
| 3733 // Float Immediate | |
| 3734 operand immF() %{ | |
| 3735 match(ConF); | |
| 3736 | |
| 3737 op_cost(20); | |
| 3738 format %{ %} | |
| 3739 interface(CONST_INTER); | |
| 3740 %} | |
| 3741 | |
| 3742 // Float Immediate: 0 | |
| 3743 operand immF0() %{ | |
| 3744 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3745 match(ConF); | |
| 3746 | |
| 3747 op_cost(0); | |
| 3748 format %{ %} | |
| 3749 interface(CONST_INTER); | |
| 3750 %} | |
| 3751 | |
| 3752 // Integer Register Operands | |
| 3753 // Integer Register | |
| 3754 operand iRegI() %{ | |
| 3755 constraint(ALLOC_IN_RC(int_reg)); | |
| 3756 match(RegI); | |
| 3757 | |
| 3758 match(notemp_iRegI); | |
| 3759 match(g1RegI); | |
| 3760 match(o0RegI); | |
| 3761 match(iRegIsafe); | |
| 3762 | |
| 3763 format %{ %} | |
| 3764 interface(REG_INTER); | |
| 3765 %} | |
| 3766 | |
| 3767 operand notemp_iRegI() %{ | |
| 3768 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3769 match(RegI); | |
| 3770 | |
| 3771 match(o0RegI); | |
| 3772 | |
| 3773 format %{ %} | |
| 3774 interface(REG_INTER); | |
| 3775 %} | |
| 3776 | |
| 3777 operand o0RegI() %{ | |
| 3778 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3779 match(iRegI); | |
| 3780 | |
| 3781 format %{ %} | |
| 3782 interface(REG_INTER); | |
| 3783 %} | |
| 3784 | |
| 3785 // Pointer Register | |
| 3786 operand iRegP() %{ | |
| 3787 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3788 match(RegP); | |
| 3789 | |
| 3790 match(lock_ptr_RegP); | |
| 3791 match(g1RegP); | |
| 3792 match(g2RegP); | |
| 3793 match(g3RegP); | |
| 3794 match(g4RegP); | |
| 3795 match(i0RegP); | |
| 3796 match(o0RegP); | |
| 3797 match(o1RegP); | |
| 3798 match(l7RegP); | |
| 3799 | |
| 3800 format %{ %} | |
| 3801 interface(REG_INTER); | |
| 3802 %} | |
| 3803 | |
| 3804 operand sp_ptr_RegP() %{ | |
| 3805 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3806 match(RegP); | |
| 3807 match(iRegP); | |
| 3808 | |
| 3809 format %{ %} | |
| 3810 interface(REG_INTER); | |
| 3811 %} | |
| 3812 | |
| 3813 operand lock_ptr_RegP() %{ | |
| 3814 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3815 match(RegP); | |
| 3816 match(i0RegP); | |
| 3817 match(o0RegP); | |
| 3818 match(o1RegP); | |
| 3819 match(l7RegP); | |
| 3820 | |
| 3821 format %{ %} | |
| 3822 interface(REG_INTER); | |
| 3823 %} | |
| 3824 | |
| 3825 operand g1RegP() %{ | |
| 3826 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3827 match(iRegP); | |
| 3828 | |
| 3829 format %{ %} | |
| 3830 interface(REG_INTER); | |
| 3831 %} | |
| 3832 | |
| 3833 operand g2RegP() %{ | |
| 3834 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3835 match(iRegP); | |
| 3836 | |
| 3837 format %{ %} | |
| 3838 interface(REG_INTER); | |
| 3839 %} | |
| 3840 | |
| 3841 operand g3RegP() %{ | |
| 3842 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3843 match(iRegP); | |
| 3844 | |
| 3845 format %{ %} | |
| 3846 interface(REG_INTER); | |
| 3847 %} | |
| 3848 | |
| 3849 operand g1RegI() %{ | |
| 3850 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3851 match(iRegI); | |
| 3852 | |
| 3853 format %{ %} | |
| 3854 interface(REG_INTER); | |
| 3855 %} | |
| 3856 | |
| 3857 operand g3RegI() %{ | |
| 3858 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3859 match(iRegI); | |
| 3860 | |
| 3861 format %{ %} | |
| 3862 interface(REG_INTER); | |
| 3863 %} | |
| 3864 | |
| 3865 operand g4RegI() %{ | |
| 3866 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3867 match(iRegI); | |
| 3868 | |
| 3869 format %{ %} | |
| 3870 interface(REG_INTER); | |
| 3871 %} | |
| 3872 | |
| 3873 operand g4RegP() %{ | |
| 3874 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3875 match(iRegP); | |
| 3876 | |
| 3877 format %{ %} | |
| 3878 interface(REG_INTER); | |
| 3879 %} | |
| 3880 | |
| 3881 operand i0RegP() %{ | |
| 3882 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3883 match(iRegP); | |
| 3884 | |
| 3885 format %{ %} | |
| 3886 interface(REG_INTER); | |
| 3887 %} | |
| 3888 | |
| 3889 operand o0RegP() %{ | |
| 3890 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3891 match(iRegP); | |
| 3892 | |
| 3893 format %{ %} | |
| 3894 interface(REG_INTER); | |
| 3895 %} | |
| 3896 | |
| 3897 operand o1RegP() %{ | |
| 3898 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3899 match(iRegP); | |
| 3900 | |
| 3901 format %{ %} | |
| 3902 interface(REG_INTER); | |
| 3903 %} | |
| 3904 | |
| 3905 operand o2RegP() %{ | |
| 3906 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3907 match(iRegP); | |
| 3908 | |
| 3909 format %{ %} | |
| 3910 interface(REG_INTER); | |
| 3911 %} | |
| 3912 | |
| 3913 operand o7RegP() %{ | |
| 3914 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3915 match(iRegP); | |
| 3916 | |
| 3917 format %{ %} | |
| 3918 interface(REG_INTER); | |
| 3919 %} | |
| 3920 | |
| 3921 operand l7RegP() %{ | |
| 3922 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3923 match(iRegP); | |
| 3924 | |
| 3925 format %{ %} | |
| 3926 interface(REG_INTER); | |
| 3927 %} | |
| 3928 | |
| 3929 operand o7RegI() %{ | |
| 3930 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3931 match(iRegI); | |
| 3932 | |
| 3933 format %{ %} | |
| 3934 interface(REG_INTER); | |
| 3935 %} | |
| 3936 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3937 operand iRegN() %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3938 constraint(ALLOC_IN_RC(int_reg)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3939 match(RegN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3940 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3941 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3942 interface(REG_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3943 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3944 |
| 0 | 3945 // Long Register |
| 3946 operand iRegL() %{ | |
| 3947 constraint(ALLOC_IN_RC(long_reg)); | |
| 3948 match(RegL); | |
| 3949 | |
| 3950 format %{ %} | |
| 3951 interface(REG_INTER); | |
| 3952 %} | |
| 3953 | |
| 3954 operand o2RegL() %{ | |
| 3955 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3956 match(iRegL); | |
| 3957 | |
| 3958 format %{ %} | |
| 3959 interface(REG_INTER); | |
| 3960 %} | |
| 3961 | |
| 3962 operand o7RegL() %{ | |
| 3963 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3964 match(iRegL); | |
| 3965 | |
| 3966 format %{ %} | |
| 3967 interface(REG_INTER); | |
| 3968 %} | |
| 3969 | |
| 3970 operand g1RegL() %{ | |
| 3971 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3972 match(iRegL); | |
| 3973 | |
| 3974 format %{ %} | |
| 3975 interface(REG_INTER); | |
| 3976 %} | |
| 3977 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3978 operand g3RegL() %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3979 constraint(ALLOC_IN_RC(g3_regL)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3980 match(iRegL); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3981 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3982 format %{ %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3983 interface(REG_INTER); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3984 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3985 |
| 0 | 3986 // Int Register safe |
| 3987 // This is 64bit safe | |
| 3988 operand iRegIsafe() %{ | |
| 3989 constraint(ALLOC_IN_RC(long_reg)); | |
| 3990 | |
| 3991 match(iRegI); | |
| 3992 | |
| 3993 format %{ %} | |
| 3994 interface(REG_INTER); | |
| 3995 %} | |
| 3996 | |
| 3997 // Condition Code Flag Register | |
| 3998 operand flagsReg() %{ | |
| 3999 constraint(ALLOC_IN_RC(int_flags)); | |
| 4000 match(RegFlags); | |
| 4001 | |
| 4002 format %{ "ccr" %} // both ICC and XCC | |
| 4003 interface(REG_INTER); | |
| 4004 %} | |
| 4005 | |
| 4006 // Condition Code Register, unsigned comparisons. | |
| 4007 operand flagsRegU() %{ | |
| 4008 constraint(ALLOC_IN_RC(int_flags)); | |
| 4009 match(RegFlags); | |
| 4010 | |
| 4011 format %{ "icc_U" %} | |
| 4012 interface(REG_INTER); | |
| 4013 %} | |
| 4014 | |
| 4015 // Condition Code Register, pointer comparisons. | |
| 4016 operand flagsRegP() %{ | |
| 4017 constraint(ALLOC_IN_RC(int_flags)); | |
| 4018 match(RegFlags); | |
| 4019 | |
| 4020 #ifdef _LP64 | |
| 4021 format %{ "xcc_P" %} | |
| 4022 #else | |
| 4023 format %{ "icc_P" %} | |
| 4024 #endif | |
| 4025 interface(REG_INTER); | |
| 4026 %} | |
| 4027 | |
| 4028 // Condition Code Register, long comparisons. | |
| 4029 operand flagsRegL() %{ | |
| 4030 constraint(ALLOC_IN_RC(int_flags)); | |
| 4031 match(RegFlags); | |
| 4032 | |
| 4033 format %{ "xcc_L" %} | |
| 4034 interface(REG_INTER); | |
| 4035 %} | |
| 4036 | |
| 4037 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4038 operand flagsRegF() %{ | |
| 4039 constraint(ALLOC_IN_RC(float_flags)); | |
| 4040 match(RegFlags); | |
| 4041 match(flagsRegF0); | |
| 4042 | |
| 4043 format %{ %} | |
| 4044 interface(REG_INTER); | |
| 4045 %} | |
| 4046 | |
| 4047 operand flagsRegF0() %{ | |
| 4048 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4049 match(RegFlags); | |
| 4050 | |
| 4051 format %{ %} | |
| 4052 interface(REG_INTER); | |
| 4053 %} | |
| 4054 | |
| 4055 | |
| 4056 // Condition Code Flag Register used by long compare | |
| 4057 operand flagsReg_long_LTGE() %{ | |
| 4058 constraint(ALLOC_IN_RC(int_flags)); | |
| 4059 match(RegFlags); | |
| 4060 format %{ "icc_LTGE" %} | |
| 4061 interface(REG_INTER); | |
| 4062 %} | |
| 4063 operand flagsReg_long_EQNE() %{ | |
| 4064 constraint(ALLOC_IN_RC(int_flags)); | |
| 4065 match(RegFlags); | |
| 4066 format %{ "icc_EQNE" %} | |
| 4067 interface(REG_INTER); | |
| 4068 %} | |
| 4069 operand flagsReg_long_LEGT() %{ | |
| 4070 constraint(ALLOC_IN_RC(int_flags)); | |
| 4071 match(RegFlags); | |
| 4072 format %{ "icc_LEGT" %} | |
| 4073 interface(REG_INTER); | |
| 4074 %} | |
| 4075 | |
| 4076 | |
| 4077 operand regD() %{ | |
| 4078 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4079 match(RegD); | |
| 4080 | |
| 551 | 4081 match(regD_low); |
| 4082 | |
| 0 | 4083 format %{ %} |
| 4084 interface(REG_INTER); | |
| 4085 %} | |
| 4086 | |
| 4087 operand regF() %{ | |
| 4088 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4089 match(RegF); | |
| 4090 | |
| 4091 format %{ %} | |
| 4092 interface(REG_INTER); | |
| 4093 %} | |
| 4094 | |
| 4095 operand regD_low() %{ | |
| 4096 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4097 match(regD); |
| 0 | 4098 |
| 4099 format %{ %} | |
| 4100 interface(REG_INTER); | |
| 4101 %} | |
| 4102 | |
| 4103 // Special Registers | |
| 4104 | |
| 4105 // Method Register | |
| 4106 operand inline_cache_regP(iRegP reg) %{ | |
| 4107 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4108 match(reg); | |
| 4109 format %{ %} | |
| 4110 interface(REG_INTER); | |
| 4111 %} | |
| 4112 | |
| 4113 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4114 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4115 match(reg); | |
| 4116 format %{ %} | |
| 4117 interface(REG_INTER); | |
| 4118 %} | |
| 4119 | |
| 4120 | |
| 4121 //----------Complex Operands--------------------------------------------------- | |
| 4122 // Indirect Memory Reference | |
| 4123 operand indirect(sp_ptr_RegP reg) %{ | |
| 4124 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4125 match(reg); | |
| 4126 | |
| 4127 op_cost(100); | |
| 4128 format %{ "[$reg]" %} | |
| 4129 interface(MEMORY_INTER) %{ | |
| 4130 base($reg); | |
| 4131 index(0x0); | |
| 4132 scale(0x0); | |
| 4133 disp(0x0); | |
| 4134 %} | |
| 4135 %} | |
| 4136 | |
| 785 | 4137 // Indirect with simm13 Offset |
| 0 | 4138 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4139 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4140 match(AddP reg offset); | |
| 4141 | |
| 4142 op_cost(100); | |
| 4143 format %{ "[$reg + $offset]" %} | |
| 4144 interface(MEMORY_INTER) %{ | |
| 4145 base($reg); | |
| 4146 index(0x0); | |
| 4147 scale(0x0); | |
| 4148 disp($offset); | |
| 4149 %} | |
| 4150 %} | |
| 4151 | |
| 785 | 4152 // Indirect with simm13 Offset minus 7 |
| 4153 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4154 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4155 match(AddP reg offset); | |
| 4156 | |
| 4157 op_cost(100); | |
| 4158 format %{ "[$reg + $offset]" %} | |
| 4159 interface(MEMORY_INTER) %{ | |
| 4160 base($reg); | |
| 4161 index(0x0); | |
| 4162 scale(0x0); | |
| 4163 disp($offset); | |
| 4164 %} | |
| 4165 %} | |
| 4166 | |
| 0 | 4167 // Note: Intel has a swapped version also, like this: |
| 4168 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4169 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4170 // match(AddP offset reg); | |
| 4171 // | |
| 4172 // op_cost(100); | |
| 4173 // format %{ "[$reg + $offset]" %} | |
| 4174 // interface(MEMORY_INTER) %{ | |
| 4175 // base($reg); | |
| 4176 // index(0x0); | |
| 4177 // scale(0x0); | |
| 4178 // disp($offset); | |
| 4179 // %} | |
| 4180 //%} | |
| 4181 //// However, it doesn't make sense for SPARC, since | |
| 4182 // we have no particularly good way to embed oops in | |
| 4183 // single instructions. | |
| 4184 | |
| 4185 // Indirect with Register Index | |
| 4186 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4187 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4188 match(AddP addr index); | |
| 4189 | |
| 4190 op_cost(100); | |
| 4191 format %{ "[$addr + $index]" %} | |
| 4192 interface(MEMORY_INTER) %{ | |
| 4193 base($addr); | |
| 4194 index($index); | |
| 4195 scale(0x0); | |
| 4196 disp(0x0); | |
| 4197 %} | |
| 4198 %} | |
| 4199 | |
| 4200 //----------Special Memory Operands-------------------------------------------- | |
| 4201 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4202 // values on the stack where a match requires a value to | |
| 4203 // flow through memory. | |
| 4204 operand stackSlotI(sRegI reg) %{ | |
| 4205 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4206 op_cost(100); | |
| 4207 //match(RegI); | |
| 4208 format %{ "[$reg]" %} | |
| 4209 interface(MEMORY_INTER) %{ | |
| 4210 base(0xE); // R_SP | |
| 4211 index(0x0); | |
| 4212 scale(0x0); | |
| 4213 disp($reg); // Stack Offset | |
| 4214 %} | |
| 4215 %} | |
| 4216 | |
| 4217 operand stackSlotP(sRegP reg) %{ | |
| 4218 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4219 op_cost(100); | |
| 4220 //match(RegP); | |
| 4221 format %{ "[$reg]" %} | |
| 4222 interface(MEMORY_INTER) %{ | |
| 4223 base(0xE); // R_SP | |
| 4224 index(0x0); | |
| 4225 scale(0x0); | |
| 4226 disp($reg); // Stack Offset | |
| 4227 %} | |
| 4228 %} | |
| 4229 | |
| 4230 operand stackSlotF(sRegF reg) %{ | |
| 4231 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4232 op_cost(100); | |
| 4233 //match(RegF); | |
| 4234 format %{ "[$reg]" %} | |
| 4235 interface(MEMORY_INTER) %{ | |
| 4236 base(0xE); // R_SP | |
| 4237 index(0x0); | |
| 4238 scale(0x0); | |
| 4239 disp($reg); // Stack Offset | |
| 4240 %} | |
| 4241 %} | |
| 4242 operand stackSlotD(sRegD reg) %{ | |
| 4243 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4244 op_cost(100); | |
| 4245 //match(RegD); | |
| 4246 format %{ "[$reg]" %} | |
| 4247 interface(MEMORY_INTER) %{ | |
| 4248 base(0xE); // R_SP | |
| 4249 index(0x0); | |
| 4250 scale(0x0); | |
| 4251 disp($reg); // Stack Offset | |
| 4252 %} | |
| 4253 %} | |
| 4254 operand stackSlotL(sRegL reg) %{ | |
| 4255 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4256 op_cost(100); | |
| 4257 //match(RegL); | |
| 4258 format %{ "[$reg]" %} | |
| 4259 interface(MEMORY_INTER) %{ | |
| 4260 base(0xE); // R_SP | |
| 4261 index(0x0); | |
| 4262 scale(0x0); | |
| 4263 disp($reg); // Stack Offset | |
| 4264 %} | |
| 4265 %} | |
| 4266 | |
| 4267 // Operands for expressing Control Flow | |
| 4268 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4269 // the AD file. It is generically handled within the ADLC. | |
| 4270 | |
| 4271 //----------Conditional Branch Operands---------------------------------------- | |
| 4272 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4273 // the following set of codes: | |
| 4274 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4275 // | |
| 4276 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4277 // by the comparison instruction that sets a condition code flags register. | |
| 4278 // That result is represented by a flags operand whose subtype is appropriate | |
| 4279 // to the unsignedness (etc.) of the comparison. | |
| 4280 // | |
| 4281 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4282 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4283 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4284 | |
| 4285 operand cmpOp() %{ | |
| 4286 match(Bool); | |
| 4287 | |
| 4288 format %{ "" %} | |
| 4289 interface(COND_INTER) %{ | |
| 4290 equal(0x1); | |
| 4291 not_equal(0x9); | |
| 4292 less(0x3); | |
| 4293 greater_equal(0xB); | |
| 4294 less_equal(0x2); | |
| 4295 greater(0xA); | |
| 4296 %} | |
| 4297 %} | |
| 4298 | |
| 4299 // Comparison Op, unsigned | |
| 4300 operand cmpOpU() %{ | |
| 4301 match(Bool); | |
| 4302 | |
| 4303 format %{ "u" %} | |
| 4304 interface(COND_INTER) %{ | |
| 4305 equal(0x1); | |
| 4306 not_equal(0x9); | |
| 4307 less(0x5); | |
| 4308 greater_equal(0xD); | |
| 4309 less_equal(0x4); | |
| 4310 greater(0xC); | |
| 4311 %} | |
| 4312 %} | |
| 4313 | |
| 4314 // Comparison Op, pointer (same as unsigned) | |
| 4315 operand cmpOpP() %{ | |
| 4316 match(Bool); | |
| 4317 | |
| 4318 format %{ "p" %} | |
| 4319 interface(COND_INTER) %{ | |
| 4320 equal(0x1); | |
| 4321 not_equal(0x9); | |
| 4322 less(0x5); | |
| 4323 greater_equal(0xD); | |
| 4324 less_equal(0x4); | |
| 4325 greater(0xC); | |
| 4326 %} | |
| 4327 %} | |
| 4328 | |
| 4329 // Comparison Op, branch-register encoding | |
| 4330 operand cmpOp_reg() %{ | |
| 4331 match(Bool); | |
| 4332 | |
| 4333 format %{ "" %} | |
| 4334 interface(COND_INTER) %{ | |
| 4335 equal (0x1); | |
| 4336 not_equal (0x5); | |
| 4337 less (0x3); | |
| 4338 greater_equal(0x7); | |
| 4339 less_equal (0x2); | |
| 4340 greater (0x6); | |
| 4341 %} | |
| 4342 %} | |
| 4343 | |
| 4344 // Comparison Code, floating, unordered same as less | |
| 4345 operand cmpOpF() %{ | |
| 4346 match(Bool); | |
| 4347 | |
| 4348 format %{ "fl" %} | |
| 4349 interface(COND_INTER) %{ | |
| 4350 equal(0x9); | |
| 4351 not_equal(0x1); | |
| 4352 less(0x3); | |
| 4353 greater_equal(0xB); | |
| 4354 less_equal(0xE); | |
| 4355 greater(0x6); | |
| 4356 %} | |
| 4357 %} | |
| 4358 | |
| 4359 // Used by long compare | |
| 4360 operand cmpOp_commute() %{ | |
| 4361 match(Bool); | |
| 4362 | |
| 4363 format %{ "" %} | |
| 4364 interface(COND_INTER) %{ | |
| 4365 equal(0x1); | |
| 4366 not_equal(0x9); | |
| 4367 less(0xA); | |
| 4368 greater_equal(0x2); | |
| 4369 less_equal(0xB); | |
| 4370 greater(0x3); | |
| 4371 %} | |
| 4372 %} | |
| 4373 | |
| 4374 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4375 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4376 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4377 // instructions for every form of operand when the instruction accepts |
| 4378 // multiple operand types with the same basic encoding and format. The classic | |
| 4379 // case of this is memory operands. | |
| 4380 opclass memory( indirect, indOffset13, indIndex ); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
4381 opclass indIndexMemory( indIndex ); |
| 0 | 4382 |
| 4383 //----------PIPELINE----------------------------------------------------------- | |
| 4384 pipeline %{ | |
| 4385 | |
| 4386 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4387 attributes %{ | |
| 4388 fixed_size_instructions; // Fixed size instructions | |
| 4389 branch_has_delay_slot; // Branch has delay slot following | |
| 4390 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4391 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4392 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4393 instruction_fetch_units = 1; // of 16 bytes | |
| 4394 | |
| 4395 // List of nop instructions | |
| 4396 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4397 %} | |
| 4398 | |
| 4399 //----------RESOURCES---------------------------------------------------------- | |
| 4400 // Resources are the functional units available to the machine | |
| 4401 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4402 | |
| 4403 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4404 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4405 | |
| 4406 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4407 | |
| 4408 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4409 // Pipeline Classes describe the stages in which input and output are | |
| 4410 // referenced by the hardware pipeline. | |
| 4411 | |
| 4412 // Integer ALU reg-reg operation | |
| 4413 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4414 single_instruction; | |
| 4415 dst : E(write); | |
| 4416 src1 : R(read); | |
| 4417 src2 : R(read); | |
| 4418 IALU : R; | |
| 4419 %} | |
| 4420 | |
| 4421 // Integer ALU reg-reg long operation | |
| 4422 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4423 instruction_count(2); | |
| 4424 dst : E(write); | |
| 4425 src1 : R(read); | |
| 4426 src2 : R(read); | |
| 4427 IALU : R; | |
| 4428 IALU : R; | |
| 4429 %} | |
| 4430 | |
| 4431 // Integer ALU reg-reg long dependent operation | |
| 4432 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4433 instruction_count(1); multiple_bundles; | |
| 4434 dst : E(write); | |
| 4435 src1 : R(read); | |
| 4436 src2 : R(read); | |
| 4437 cr : E(write); | |
| 4438 IALU : R(2); | |
| 4439 %} | |
| 4440 | |
| 4441 // Integer ALU reg-imm operaion | |
| 4442 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4443 single_instruction; | |
| 4444 dst : E(write); | |
| 4445 src1 : R(read); | |
| 4446 IALU : R; | |
| 4447 %} | |
| 4448 | |
| 4449 // Integer ALU reg-reg operation with condition code | |
| 4450 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4451 single_instruction; | |
| 4452 dst : E(write); | |
| 4453 cr : E(write); | |
| 4454 src1 : R(read); | |
| 4455 src2 : R(read); | |
| 4456 IALU : R; | |
| 4457 %} | |
| 4458 | |
| 4459 // Integer ALU reg-imm operation with condition code | |
| 4460 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4461 single_instruction; | |
| 4462 dst : E(write); | |
| 4463 cr : E(write); | |
| 4464 src1 : R(read); | |
| 4465 IALU : R; | |
| 4466 %} | |
| 4467 | |
| 4468 // Integer ALU zero-reg operation | |
| 4469 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4470 single_instruction; | |
| 4471 dst : E(write); | |
| 4472 src2 : R(read); | |
| 4473 IALU : R; | |
| 4474 %} | |
| 4475 | |
| 4476 // Integer ALU zero-reg operation with condition code only | |
| 4477 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4478 single_instruction; | |
| 4479 cr : E(write); | |
| 4480 src : R(read); | |
| 4481 IALU : R; | |
| 4482 %} | |
| 4483 | |
| 4484 // Integer ALU reg-reg operation with condition code only | |
| 4485 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4486 single_instruction; | |
| 4487 cr : E(write); | |
| 4488 src1 : R(read); | |
| 4489 src2 : R(read); | |
| 4490 IALU : R; | |
| 4491 %} | |
| 4492 | |
| 4493 // Integer ALU reg-imm operation with condition code only | |
| 4494 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4495 single_instruction; | |
| 4496 cr : E(write); | |
| 4497 src1 : R(read); | |
| 4498 IALU : R; | |
| 4499 %} | |
| 4500 | |
| 4501 // Integer ALU reg-reg-zero operation with condition code only | |
| 4502 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4503 single_instruction; | |
| 4504 cr : E(write); | |
| 4505 src1 : R(read); | |
| 4506 src2 : R(read); | |
| 4507 IALU : R; | |
| 4508 %} | |
| 4509 | |
| 4510 // Integer ALU reg-imm-zero operation with condition code only | |
| 4511 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4512 single_instruction; | |
| 4513 cr : E(write); | |
| 4514 src1 : R(read); | |
| 4515 IALU : R; | |
| 4516 %} | |
| 4517 | |
| 4518 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4519 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4520 single_instruction; | |
| 4521 cr : E(write); | |
| 4522 src1 : E(write); | |
| 4523 src1 : R(read); | |
| 4524 src2 : R(read); | |
| 4525 IALU : R; | |
| 4526 %} | |
| 4527 | |
| 4528 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4529 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4530 single_instruction; | |
| 4531 cr : E(write); | |
| 4532 src1 : E(write); | |
| 4533 src1 : R(read); | |
| 4534 IALU : R; | |
| 4535 %} | |
| 4536 | |
| 4537 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4538 multiple_bundles; | |
| 4539 dst : E(write)+4; | |
| 4540 cr : E(write); | |
| 4541 src1 : R(read); | |
| 4542 src2 : R(read); | |
| 4543 IALU : R(3); | |
| 4544 BR : R(2); | |
| 4545 %} | |
| 4546 | |
| 4547 // Integer ALU operation | |
| 4548 pipe_class ialu_none(iRegI dst) %{ | |
| 4549 single_instruction; | |
| 4550 dst : E(write); | |
| 4551 IALU : R; | |
| 4552 %} | |
| 4553 | |
| 4554 // Integer ALU reg operation | |
| 4555 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4556 single_instruction; may_have_no_code; | |
| 4557 dst : E(write); | |
| 4558 src : R(read); | |
| 4559 IALU : R; | |
| 4560 %} | |
| 4561 | |
| 4562 // Integer ALU reg conditional operation | |
| 4563 // This instruction has a 1 cycle stall, and cannot execute | |
| 4564 // in the same cycle as the instruction setting the condition | |
| 4565 // code. We kludge this by pretending to read the condition code | |
| 4566 // 1 cycle earlier, and by marking the functional units as busy | |
| 4567 // for 2 cycles with the result available 1 cycle later than | |
| 4568 // is really the case. | |
| 4569 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4570 single_instruction; | |
| 4571 op2_out : C(write); | |
| 4572 op1 : R(read); | |
| 4573 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4574 BR : R(2); | |
| 4575 MS : R(2); | |
| 4576 %} | |
| 4577 | |
| 4578 #ifdef _LP64 | |
| 4579 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4580 instruction_count(1); multiple_bundles; | |
| 4581 dst : C(write)+1; | |
| 4582 src : R(read)+1; | |
| 4583 IALU : R(1); | |
| 4584 BR : E(2); | |
| 4585 MS : E(2); | |
| 4586 %} | |
| 4587 #endif | |
| 4588 | |
| 4589 // Integer ALU reg operation | |
| 4590 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4591 single_instruction; may_have_no_code; | |
| 4592 dst : E(write); | |
| 4593 src : R(read); | |
| 4594 IALU : R; | |
| 4595 %} | |
| 4596 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4597 single_instruction; may_have_no_code; | |
| 4598 dst : E(write); | |
| 4599 src : R(read); | |
| 4600 IALU : R; | |
| 4601 %} | |
| 4602 | |
| 4603 // Two integer ALU reg operations | |
| 4604 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4605 instruction_count(2); | |
| 4606 dst : E(write); | |
| 4607 src : R(read); | |
| 4608 A0 : R; | |
| 4609 A1 : R; | |
| 4610 %} | |
| 4611 | |
| 4612 // Two integer ALU reg operations | |
| 4613 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4614 instruction_count(2); may_have_no_code; | |
| 4615 dst : E(write); | |
| 4616 src : R(read); | |
| 4617 A0 : R; | |
| 4618 A1 : R; | |
| 4619 %} | |
| 4620 | |
| 4621 // Integer ALU imm operation | |
| 4622 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4623 single_instruction; | |
| 4624 dst : E(write); | |
| 4625 IALU : R; | |
| 4626 %} | |
| 4627 | |
| 4628 // Integer ALU reg-reg with carry operation | |
| 4629 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4630 single_instruction; | |
| 4631 dst : E(write); | |
| 4632 src1 : R(read); | |
| 4633 src2 : R(read); | |
| 4634 IALU : R; | |
| 4635 %} | |
| 4636 | |
| 4637 // Integer ALU cc operation | |
| 4638 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4639 single_instruction; | |
| 4640 dst : E(write); | |
| 4641 cc : R(read); | |
| 4642 IALU : R; | |
| 4643 %} | |
| 4644 | |
| 4645 // Integer ALU cc / second IALU operation | |
| 4646 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4647 instruction_count(1); multiple_bundles; | |
| 4648 dst : E(write)+1; | |
| 4649 src : R(read); | |
| 4650 IALU : R; | |
| 4651 %} | |
| 4652 | |
| 4653 // Integer ALU cc / second IALU operation | |
| 4654 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4655 instruction_count(1); multiple_bundles; | |
| 4656 dst : E(write)+1; | |
| 4657 p : R(read); | |
| 4658 q : R(read); | |
| 4659 IALU : R; | |
| 4660 %} | |
| 4661 | |
| 4662 // Integer ALU hi-lo-reg operation | |
| 4663 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4664 instruction_count(1); multiple_bundles; | |
| 4665 dst : E(write)+1; | |
| 4666 IALU : R(2); | |
| 4667 %} | |
| 4668 | |
| 4669 // Float ALU hi-lo-reg operation (with temp) | |
| 4670 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4671 instruction_count(1); multiple_bundles; | |
| 4672 dst : E(write)+1; | |
| 4673 IALU : R(2); | |
| 4674 %} | |
| 4675 | |
| 4676 // Long Constant | |
| 4677 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4678 instruction_count(2); multiple_bundles; | |
| 4679 dst : E(write)+1; | |
| 4680 IALU : R(2); | |
| 4681 IALU : R(2); | |
| 4682 %} | |
| 4683 | |
| 4684 // Pointer Constant | |
| 4685 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4686 instruction_count(0); multiple_bundles; | |
| 4687 fixed_latency(6); | |
| 4688 %} | |
| 4689 | |
| 4690 // Polling Address | |
| 4691 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4692 #ifdef _LP64 | |
| 4693 instruction_count(0); multiple_bundles; | |
| 4694 fixed_latency(6); | |
| 4695 #else | |
| 4696 dst : E(write); | |
| 4697 IALU : R; | |
| 4698 #endif | |
| 4699 %} | |
| 4700 | |
| 4701 // Long Constant small | |
| 4702 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4703 instruction_count(2); | |
| 4704 dst : E(write); | |
| 4705 IALU : R; | |
| 4706 IALU : R; | |
| 4707 %} | |
| 4708 | |
| 4709 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4710 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4711 instruction_count(1); multiple_bundles; | |
| 4712 src : R(read); | |
| 4713 dst : M(write)+1; | |
| 4714 IALU : R; | |
| 4715 MS : E; | |
| 4716 %} | |
| 4717 | |
| 4718 // Integer ALU nop operation | |
| 4719 pipe_class ialu_nop() %{ | |
| 4720 single_instruction; | |
| 4721 IALU : R; | |
| 4722 %} | |
| 4723 | |
| 4724 // Integer ALU nop operation | |
| 4725 pipe_class ialu_nop_A0() %{ | |
| 4726 single_instruction; | |
| 4727 A0 : R; | |
| 4728 %} | |
| 4729 | |
| 4730 // Integer ALU nop operation | |
| 4731 pipe_class ialu_nop_A1() %{ | |
| 4732 single_instruction; | |
| 4733 A1 : R; | |
| 4734 %} | |
| 4735 | |
| 4736 // Integer Multiply reg-reg operation | |
| 4737 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4738 single_instruction; | |
| 4739 dst : E(write); | |
| 4740 src1 : R(read); | |
| 4741 src2 : R(read); | |
| 4742 MS : R(5); | |
| 4743 %} | |
| 4744 | |
| 4745 // Integer Multiply reg-imm operation | |
| 4746 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4747 single_instruction; | |
| 4748 dst : E(write); | |
| 4749 src1 : R(read); | |
| 4750 MS : R(5); | |
| 4751 %} | |
| 4752 | |
| 4753 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4754 single_instruction; | |
| 4755 dst : E(write)+4; | |
| 4756 src1 : R(read); | |
| 4757 src2 : R(read); | |
| 4758 MS : R(6); | |
| 4759 %} | |
| 4760 | |
| 4761 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4762 single_instruction; | |
| 4763 dst : E(write)+4; | |
| 4764 src1 : R(read); | |
| 4765 MS : R(6); | |
| 4766 %} | |
| 4767 | |
| 4768 // Integer Divide reg-reg | |
| 4769 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4770 instruction_count(1); multiple_bundles; | |
| 4771 dst : E(write); | |
| 4772 temp : E(write); | |
| 4773 src1 : R(read); | |
| 4774 src2 : R(read); | |
| 4775 temp : R(read); | |
| 4776 MS : R(38); | |
| 4777 %} | |
| 4778 | |
| 4779 // Integer Divide reg-imm | |
| 4780 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4781 instruction_count(1); multiple_bundles; | |
| 4782 dst : E(write); | |
| 4783 temp : E(write); | |
| 4784 src1 : R(read); | |
| 4785 temp : R(read); | |
| 4786 MS : R(38); | |
| 4787 %} | |
| 4788 | |
| 4789 // Long Divide | |
| 4790 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4791 dst : E(write)+71; | |
| 4792 src1 : R(read); | |
| 4793 src2 : R(read)+1; | |
| 4794 MS : R(70); | |
| 4795 %} | |
| 4796 | |
| 4797 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4798 dst : E(write)+71; | |
| 4799 src1 : R(read); | |
| 4800 MS : R(70); | |
| 4801 %} | |
| 4802 | |
| 4803 // Floating Point Add Float | |
| 4804 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4805 single_instruction; | |
| 4806 dst : X(write); | |
| 4807 src1 : E(read); | |
| 4808 src2 : E(read); | |
| 4809 FA : R; | |
| 4810 %} | |
| 4811 | |
| 4812 // Floating Point Add Double | |
| 4813 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4814 single_instruction; | |
| 4815 dst : X(write); | |
| 4816 src1 : E(read); | |
| 4817 src2 : E(read); | |
| 4818 FA : R; | |
| 4819 %} | |
| 4820 | |
| 4821 // Floating Point Conditional Move based on integer flags | |
| 4822 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4823 single_instruction; | |
| 4824 dst : X(write); | |
| 4825 src : E(read); | |
| 4826 cr : R(read); | |
| 4827 FA : R(2); | |
| 4828 BR : R(2); | |
| 4829 %} | |
| 4830 | |
| 4831 // Floating Point Conditional Move based on integer flags | |
| 4832 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4833 single_instruction; | |
| 4834 dst : X(write); | |
| 4835 src : E(read); | |
| 4836 cr : R(read); | |
| 4837 FA : R(2); | |
| 4838 BR : R(2); | |
| 4839 %} | |
| 4840 | |
| 4841 // Floating Point Multiply Float | |
| 4842 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4843 single_instruction; | |
| 4844 dst : X(write); | |
| 4845 src1 : E(read); | |
| 4846 src2 : E(read); | |
| 4847 FM : R; | |
| 4848 %} | |
| 4849 | |
| 4850 // Floating Point Multiply Double | |
| 4851 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4852 single_instruction; | |
| 4853 dst : X(write); | |
| 4854 src1 : E(read); | |
| 4855 src2 : E(read); | |
| 4856 FM : R; | |
| 4857 %} | |
| 4858 | |
| 4859 // Floating Point Divide Float | |
| 4860 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4861 single_instruction; | |
| 4862 dst : X(write); | |
| 4863 src1 : E(read); | |
| 4864 src2 : E(read); | |
| 4865 FM : R; | |
| 4866 FDIV : C(14); | |
| 4867 %} | |
| 4868 | |
| 4869 // Floating Point Divide Double | |
| 4870 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4871 single_instruction; | |
| 4872 dst : X(write); | |
| 4873 src1 : E(read); | |
| 4874 src2 : E(read); | |
| 4875 FM : R; | |
| 4876 FDIV : C(17); | |
| 4877 %} | |
| 4878 | |
| 4879 // Floating Point Move/Negate/Abs Float | |
| 4880 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4881 single_instruction; | |
| 4882 dst : W(write); | |
| 4883 src : E(read); | |
| 4884 FA : R(1); | |
| 4885 %} | |
| 4886 | |
| 4887 // Floating Point Move/Negate/Abs Double | |
| 4888 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4889 single_instruction; | |
| 4890 dst : W(write); | |
| 4891 src : E(read); | |
| 4892 FA : R; | |
| 4893 %} | |
| 4894 | |
| 4895 // Floating Point Convert F->D | |
| 4896 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4897 single_instruction; | |
| 4898 dst : X(write); | |
| 4899 src : E(read); | |
| 4900 FA : R; | |
| 4901 %} | |
| 4902 | |
| 4903 // Floating Point Convert I->D | |
| 4904 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4905 single_instruction; | |
| 4906 dst : X(write); | |
| 4907 src : E(read); | |
| 4908 FA : R; | |
| 4909 %} | |
| 4910 | |
| 4911 // Floating Point Convert LHi->D | |
| 4912 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4913 single_instruction; | |
| 4914 dst : X(write); | |
| 4915 src : E(read); | |
| 4916 FA : R; | |
| 4917 %} | |
| 4918 | |
| 4919 // Floating Point Convert L->D | |
| 4920 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4921 single_instruction; | |
| 4922 dst : X(write); | |
| 4923 src : E(read); | |
| 4924 FA : R; | |
| 4925 %} | |
| 4926 | |
| 4927 // Floating Point Convert L->F | |
| 4928 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4929 single_instruction; | |
| 4930 dst : X(write); | |
| 4931 src : E(read); | |
| 4932 FA : R; | |
| 4933 %} | |
| 4934 | |
| 4935 // Floating Point Convert D->F | |
| 4936 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4937 single_instruction; | |
| 4938 dst : X(write); | |
| 4939 src : E(read); | |
| 4940 FA : R; | |
| 4941 %} | |
| 4942 | |
| 4943 // Floating Point Convert I->L | |
| 4944 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4945 single_instruction; | |
| 4946 dst : X(write); | |
| 4947 src : E(read); | |
| 4948 FA : R; | |
| 4949 %} | |
| 4950 | |
| 4951 // Floating Point Convert D->F | |
| 4952 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4953 instruction_count(1); multiple_bundles; | |
| 4954 dst : X(write)+6; | |
| 4955 src : E(read); | |
| 4956 FA : R; | |
| 4957 %} | |
| 4958 | |
| 4959 // Floating Point Convert D->L | |
| 4960 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4961 instruction_count(1); multiple_bundles; | |
| 4962 dst : X(write)+6; | |
| 4963 src : E(read); | |
| 4964 FA : R; | |
| 4965 %} | |
| 4966 | |
| 4967 // Floating Point Convert F->I | |
| 4968 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4969 instruction_count(1); multiple_bundles; | |
| 4970 dst : X(write)+6; | |
| 4971 src : E(read); | |
| 4972 FA : R; | |
| 4973 %} | |
| 4974 | |
| 4975 // Floating Point Convert F->L | |
| 4976 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4977 instruction_count(1); multiple_bundles; | |
| 4978 dst : X(write)+6; | |
| 4979 src : E(read); | |
| 4980 FA : R; | |
| 4981 %} | |
| 4982 | |
| 4983 // Floating Point Convert I->F | |
| 4984 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4985 single_instruction; | |
| 4986 dst : X(write); | |
| 4987 src : E(read); | |
| 4988 FA : R; | |
| 4989 %} | |
| 4990 | |
| 4991 // Floating Point Compare | |
| 4992 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4993 single_instruction; | |
| 4994 cr : X(write); | |
| 4995 src1 : E(read); | |
| 4996 src2 : E(read); | |
| 4997 FA : R; | |
| 4998 %} | |
| 4999 | |
| 5000 // Floating Point Compare | |
| 5001 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 5002 single_instruction; | |
| 5003 cr : X(write); | |
| 5004 src1 : E(read); | |
| 5005 src2 : E(read); | |
| 5006 FA : R; | |
| 5007 %} | |
| 5008 | |
| 5009 // Floating Add Nop | |
| 5010 pipe_class fadd_nop() %{ | |
| 5011 single_instruction; | |
| 5012 FA : R; | |
| 5013 %} | |
| 5014 | |
| 5015 // Integer Store to Memory | |
| 5016 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5017 single_instruction; | |
| 5018 mem : R(read); | |
| 5019 src : C(read); | |
| 5020 MS : R; | |
| 5021 %} | |
| 5022 | |
| 5023 // Integer Store to Memory | |
| 5024 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5025 single_instruction; | |
| 5026 mem : R(read); | |
| 5027 src : C(read); | |
| 5028 MS : R; | |
| 5029 %} | |
| 5030 | |
| 5031 // Integer Store Zero to Memory | |
| 5032 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5033 single_instruction; | |
| 5034 mem : R(read); | |
| 5035 MS : R; | |
| 5036 %} | |
| 5037 | |
| 5038 // Special Stack Slot Store | |
| 5039 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5040 single_instruction; | |
| 5041 stkSlot : R(read); | |
| 5042 src : C(read); | |
| 5043 MS : R; | |
| 5044 %} | |
| 5045 | |
| 5046 // Special Stack Slot Store | |
| 5047 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5048 instruction_count(2); multiple_bundles; | |
| 5049 stkSlot : R(read); | |
| 5050 src : C(read); | |
| 5051 MS : R(2); | |
| 5052 %} | |
| 5053 | |
| 5054 // Float Store | |
| 5055 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5056 single_instruction; | |
| 5057 mem : R(read); | |
| 5058 src : C(read); | |
| 5059 MS : R; | |
| 5060 %} | |
| 5061 | |
| 5062 // Float Store | |
| 5063 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5064 single_instruction; | |
| 5065 mem : R(read); | |
| 5066 MS : R; | |
| 5067 %} | |
| 5068 | |
| 5069 // Double Store | |
| 5070 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5071 instruction_count(1); | |
| 5072 mem : R(read); | |
| 5073 src : C(read); | |
| 5074 MS : R; | |
| 5075 %} | |
| 5076 | |
| 5077 // Double Store | |
| 5078 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5079 single_instruction; | |
| 5080 mem : R(read); | |
| 5081 MS : R; | |
| 5082 %} | |
| 5083 | |
| 5084 // Special Stack Slot Float Store | |
| 5085 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5086 single_instruction; | |
| 5087 stkSlot : R(read); | |
| 5088 src : C(read); | |
| 5089 MS : R; | |
| 5090 %} | |
| 5091 | |
| 5092 // Special Stack Slot Double Store | |
| 5093 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5094 single_instruction; | |
| 5095 stkSlot : R(read); | |
| 5096 src : C(read); | |
| 5097 MS : R; | |
| 5098 %} | |
| 5099 | |
| 5100 // Integer Load (when sign bit propagation not needed) | |
| 5101 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5102 single_instruction; | |
| 5103 mem : R(read); | |
| 5104 dst : C(write); | |
| 5105 MS : R; | |
| 5106 %} | |
| 5107 | |
| 5108 // Integer Load from stack operand | |
| 5109 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5110 single_instruction; | |
| 5111 mem : R(read); | |
| 5112 dst : C(write); | |
| 5113 MS : R; | |
| 5114 %} | |
| 5115 | |
| 5116 // Integer Load (when sign bit propagation or masking is needed) | |
| 5117 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5118 single_instruction; | |
| 5119 mem : R(read); | |
| 5120 dst : M(write); | |
| 5121 MS : R; | |
| 5122 %} | |
| 5123 | |
| 5124 // Float Load | |
| 5125 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5126 single_instruction; | |
| 5127 mem : R(read); | |
| 5128 dst : M(write); | |
| 5129 MS : R; | |
| 5130 %} | |
| 5131 | |
| 5132 // Float Load | |
| 5133 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5134 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5135 mem : R(read); | |
| 5136 dst : M(write); | |
| 5137 MS : R; | |
| 5138 %} | |
| 5139 | |
| 5140 // Float Load | |
| 5141 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5142 single_instruction; | |
| 5143 stkSlot : R(read); | |
| 5144 dst : M(write); | |
| 5145 MS : R; | |
| 5146 %} | |
| 5147 | |
| 5148 // Float Load | |
| 5149 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5150 single_instruction; | |
| 5151 stkSlot : R(read); | |
| 5152 dst : M(write); | |
| 5153 MS : R; | |
| 5154 %} | |
| 5155 | |
| 5156 // Memory Nop | |
| 5157 pipe_class mem_nop() %{ | |
| 5158 single_instruction; | |
| 5159 MS : R; | |
| 5160 %} | |
| 5161 | |
| 5162 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5163 single_instruction; | |
| 5164 dst : E(write); | |
| 5165 IALU : R; | |
| 5166 %} | |
| 5167 | |
| 5168 pipe_class loadPollP(iRegP poll) %{ | |
| 5169 single_instruction; | |
| 5170 poll : R(read); | |
| 5171 MS : R; | |
| 5172 %} | |
| 5173 | |
| 5174 pipe_class br(Universe br, label labl) %{ | |
| 5175 single_instruction_with_delay_slot; | |
| 5176 BR : R; | |
| 5177 %} | |
| 5178 | |
| 5179 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5180 single_instruction_with_delay_slot; | |
| 5181 cr : E(read); | |
| 5182 BR : R; | |
| 5183 %} | |
| 5184 | |
| 5185 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5186 single_instruction_with_delay_slot; | |
| 5187 op1 : E(read); | |
| 5188 BR : R; | |
| 5189 MS : R; | |
| 5190 %} | |
| 5191 | |
| 3851 | 5192 // Compare and branch |
| 5193 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
| 5194 instruction_count(2); has_delay_slot; | |
| 5195 cr : E(write); | |
| 5196 src1 : R(read); | |
| 5197 src2 : R(read); | |
| 5198 IALU : R; | |
| 5199 BR : R; | |
| 5200 %} | |
| 5201 | |
| 5202 // Compare and branch | |
| 5203 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
| 5204 instruction_count(2); has_delay_slot; | |
| 5205 cr : E(write); | |
| 5206 src1 : R(read); | |
| 5207 IALU : R; | |
| 5208 BR : R; | |
| 5209 %} | |
| 5210 | |
| 5211 // Compare and branch using cbcond | |
| 5212 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
| 5213 single_instruction; | |
| 5214 src1 : E(read); | |
| 5215 src2 : E(read); | |
| 5216 IALU : R; | |
| 5217 BR : R; | |
| 5218 %} | |
| 5219 | |
| 5220 // Compare and branch using cbcond | |
| 5221 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
| 5222 single_instruction; | |
| 5223 src1 : E(read); | |
| 5224 IALU : R; | |
| 5225 BR : R; | |
| 5226 %} | |
| 5227 | |
| 0 | 5228 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
| 5229 single_instruction_with_delay_slot; | |
| 5230 cr : E(read); | |
| 5231 BR : R; | |
| 5232 %} | |
| 5233 | |
| 5234 pipe_class br_nop() %{ | |
| 5235 single_instruction; | |
| 5236 BR : R; | |
| 5237 %} | |
| 5238 | |
| 5239 pipe_class simple_call(method meth) %{ | |
| 5240 instruction_count(2); multiple_bundles; force_serialization; | |
| 5241 fixed_latency(100); | |
| 5242 BR : R(1); | |
| 5243 MS : R(1); | |
| 5244 A0 : R(1); | |
| 5245 %} | |
| 5246 | |
| 5247 pipe_class compiled_call(method meth) %{ | |
| 5248 instruction_count(1); multiple_bundles; force_serialization; | |
| 5249 fixed_latency(100); | |
| 5250 MS : R(1); | |
| 5251 %} | |
| 5252 | |
| 5253 pipe_class call(method meth) %{ | |
| 5254 instruction_count(0); multiple_bundles; force_serialization; | |
| 5255 fixed_latency(100); | |
| 5256 %} | |
| 5257 | |
| 5258 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5259 single_instruction; has_delay_slot; | |
| 5260 fixed_latency(100); | |
| 5261 BR : R(1); | |
| 5262 MS : R(1); | |
| 5263 %} | |
| 5264 | |
| 5265 pipe_class ret(Universe ignore) %{ | |
| 5266 single_instruction; has_delay_slot; | |
| 5267 BR : R(1); | |
| 5268 MS : R(1); | |
| 5269 %} | |
| 5270 | |
| 5271 pipe_class ret_poll(g3RegP poll) %{ | |
| 5272 instruction_count(3); has_delay_slot; | |
| 5273 poll : E(read); | |
| 5274 MS : R; | |
| 5275 %} | |
| 5276 | |
| 5277 // The real do-nothing guy | |
| 5278 pipe_class empty( ) %{ | |
| 5279 instruction_count(0); | |
| 5280 %} | |
| 5281 | |
| 5282 pipe_class long_memory_op() %{ | |
| 5283 instruction_count(0); multiple_bundles; force_serialization; | |
| 5284 fixed_latency(25); | |
| 5285 MS : R(1); | |
| 5286 %} | |
| 5287 | |
| 5288 // Check-cast | |
| 5289 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5290 array : R(read); | |
| 5291 match : R(read); | |
| 5292 IALU : R(2); | |
| 5293 BR : R(2); | |
| 5294 MS : R; | |
| 5295 %} | |
| 5296 | |
| 5297 // Convert FPU flags into +1,0,-1 | |
| 5298 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5299 src1 : E(read); | |
| 5300 src2 : E(read); | |
| 5301 dst : E(write); | |
| 5302 FA : R; | |
| 5303 MS : R(2); | |
| 5304 BR : R(2); | |
| 5305 %} | |
| 5306 | |
| 5307 // Compare for p < q, and conditionally add y | |
| 5308 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5309 p : E(read); | |
| 5310 q : E(read); | |
| 5311 y : E(read); | |
| 5312 IALU : R(3) | |
| 5313 %} | |
| 5314 | |
| 5315 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5316 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5317 src2 : E(read); | |
| 5318 srcdst : E(read); | |
| 5319 IALU : R; | |
| 5320 BR : R; | |
| 5321 %} | |
| 5322 | |
| 5323 // Define the class for the Nop node | |
| 5324 define %{ | |
| 5325 MachNop = ialu_nop; | |
| 5326 %} | |
| 5327 | |
| 5328 %} | |
| 5329 | |
| 5330 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5331 | |
| 5332 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5333 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5334 // No match rule to avoid chain rule match. | |
| 5335 effect(DEF dst, USE src); | |
| 5336 ins_cost(MEMORY_REF_COST); | |
| 5337 size(4); | |
| 5338 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5339 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5340 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5341 ins_pipe(floadF_stk); |
| 5342 %} | |
| 5343 | |
| 5344 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5345 // No match rule to avoid chain rule match. | |
| 5346 effect(DEF dst, USE src); | |
| 5347 ins_cost(MEMORY_REF_COST); | |
| 5348 size(4); | |
| 5349 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5350 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5351 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5352 ins_pipe(floadD_stk); |
| 5353 %} | |
| 5354 | |
| 5355 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5356 // No match rule to avoid chain rule match. | |
| 5357 effect(DEF dst, USE src); | |
| 5358 ins_cost(MEMORY_REF_COST); | |
| 5359 size(4); | |
| 5360 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5361 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5362 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5363 ins_pipe(fstoreF_stk_reg); |
| 5364 %} | |
| 5365 | |
| 5366 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5367 // No match rule to avoid chain rule match. | |
| 5368 effect(DEF dst, USE src); | |
| 5369 ins_cost(MEMORY_REF_COST); | |
| 5370 size(4); | |
| 5371 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5372 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5373 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5374 ins_pipe(fstoreD_stk_reg); |
| 5375 %} | |
| 5376 | |
| 5377 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5378 effect(DEF dst, USE src); | |
| 5379 ins_cost(MEMORY_REF_COST*2); | |
| 5380 size(8); | |
| 5381 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5382 "STW R_G0,$dst.lo" %} | |
| 5383 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5384 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5385 ins_pipe(lstoreI_stk_reg); |
| 5386 %} | |
| 5387 | |
| 5388 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5389 // No match rule to avoid chain rule match. | |
| 5390 effect(DEF dst, USE src); | |
| 5391 ins_cost(MEMORY_REF_COST); | |
| 5392 size(4); | |
| 5393 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5394 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5395 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5396 ins_pipe(istore_stk_reg); |
| 5397 %} | |
| 5398 | |
| 5399 //---------- Chain stack slots between similar types -------- | |
| 5400 | |
| 5401 // Load integer from stack slot | |
| 5402 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5403 match(Set dst src); | |
| 5404 ins_cost(MEMORY_REF_COST); | |
| 5405 | |
| 5406 size(4); | |
| 5407 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5408 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5409 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5410 ins_pipe(iload_mem); |
| 5411 %} | |
| 5412 | |
| 5413 // Store integer to stack slot | |
| 5414 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5415 match(Set dst src); | |
| 5416 ins_cost(MEMORY_REF_COST); | |
| 5417 | |
| 5418 size(4); | |
| 5419 format %{ "STW $src,$dst\t!stk" %} | |
| 5420 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5421 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5422 ins_pipe(istore_mem_reg); |
| 5423 %} | |
| 5424 | |
| 5425 // Load long from stack slot | |
| 5426 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5427 match(Set dst src); | |
| 5428 | |
| 5429 ins_cost(MEMORY_REF_COST); | |
| 5430 size(4); | |
| 5431 format %{ "LDX $src,$dst\t! long" %} | |
| 5432 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5433 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5434 ins_pipe(iload_mem); |
| 5435 %} | |
| 5436 | |
| 5437 // Store long to stack slot | |
| 5438 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5439 match(Set dst src); | |
| 5440 | |
| 5441 ins_cost(MEMORY_REF_COST); | |
| 5442 size(4); | |
| 5443 format %{ "STX $src,$dst\t! long" %} | |
| 5444 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5445 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5446 ins_pipe(istore_mem_reg); |
| 5447 %} | |
| 5448 | |
| 5449 #ifdef _LP64 | |
| 5450 // Load pointer from stack slot, 64-bit encoding | |
| 5451 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5452 match(Set dst src); | |
| 5453 ins_cost(MEMORY_REF_COST); | |
| 5454 size(4); | |
| 5455 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5456 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5457 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5458 ins_pipe(iload_mem); |
| 5459 %} | |
| 5460 | |
| 5461 // Store pointer to stack slot | |
| 5462 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5463 match(Set dst src); | |
| 5464 ins_cost(MEMORY_REF_COST); | |
| 5465 size(4); | |
| 5466 format %{ "STX $src,$dst\t!ptr" %} | |
| 5467 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5468 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5469 ins_pipe(istore_mem_reg); |
| 5470 %} | |
| 5471 #else // _LP64 | |
| 5472 // Load pointer from stack slot, 32-bit encoding | |
| 5473 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5474 match(Set dst src); | |
| 5475 ins_cost(MEMORY_REF_COST); | |
| 5476 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5477 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5478 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5479 ins_pipe(iload_mem); |
| 5480 %} | |
| 5481 | |
| 5482 // Store pointer to stack slot | |
| 5483 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5484 match(Set dst src); | |
| 5485 ins_cost(MEMORY_REF_COST); | |
| 5486 format %{ "STW $src,$dst\t!ptr" %} | |
| 5487 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5488 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5489 ins_pipe(istore_mem_reg); |
| 5490 %} | |
| 5491 #endif // _LP64 | |
| 5492 | |
| 5493 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5494 // Nop using the A0 functional unit | |
| 5495 instruct Nop_A0() %{ | |
| 5496 ins_cost(0); | |
| 5497 | |
| 5498 format %{ "NOP ! Alu Pipeline" %} | |
| 5499 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5500 ins_encode( form2_nop() ); | |
| 5501 ins_pipe(ialu_nop_A0); | |
| 5502 %} | |
| 5503 | |
| 5504 // Nop using the A1 functional unit | |
| 5505 instruct Nop_A1( ) %{ | |
| 5506 ins_cost(0); | |
| 5507 | |
| 5508 format %{ "NOP ! Alu Pipeline" %} | |
| 5509 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5510 ins_encode( form2_nop() ); | |
| 5511 ins_pipe(ialu_nop_A1); | |
| 5512 %} | |
| 5513 | |
| 5514 // Nop using the memory functional unit | |
| 5515 instruct Nop_MS( ) %{ | |
| 5516 ins_cost(0); | |
| 5517 | |
| 5518 format %{ "NOP ! Memory Pipeline" %} | |
| 5519 ins_encode( emit_mem_nop ); | |
| 5520 ins_pipe(mem_nop); | |
| 5521 %} | |
| 5522 | |
| 5523 // Nop using the floating add functional unit | |
| 5524 instruct Nop_FA( ) %{ | |
| 5525 ins_cost(0); | |
| 5526 | |
| 5527 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5528 ins_encode( emit_fadd_nop ); | |
| 5529 ins_pipe(fadd_nop); | |
| 5530 %} | |
| 5531 | |
| 5532 // Nop using the branch functional unit | |
| 5533 instruct Nop_BR( ) %{ | |
| 5534 ins_cost(0); | |
| 5535 | |
| 5536 format %{ "NOP ! Branch Pipeline" %} | |
| 5537 ins_encode( emit_br_nop ); | |
| 5538 ins_pipe(br_nop); | |
| 5539 %} | |
| 5540 | |
| 5541 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5542 //----------Load Instructions-------------------------------------------------- | |
| 5543 // Load Byte (8bit signed) | |
| 5544 instruct loadB(iRegI dst, memory mem) %{ | |
| 5545 match(Set dst (LoadB mem)); | |
| 5546 ins_cost(MEMORY_REF_COST); | |
| 5547 | |
| 5548 size(4); | |
| 624 | 5549 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5550 ins_encode %{ |
| 5551 __ ldsb($mem$$Address, $dst$$Register); | |
| 5552 %} | |
| 624 | 5553 ins_pipe(iload_mask_mem); |
| 5554 %} | |
| 5555 | |
| 5556 // Load Byte (8bit signed) into a Long Register | |
| 5557 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5558 match(Set dst (ConvI2L (LoadB mem))); | |
| 5559 ins_cost(MEMORY_REF_COST); | |
| 5560 | |
| 5561 size(4); | |
| 5562 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5563 ins_encode %{ |
| 5564 __ ldsb($mem$$Address, $dst$$Register); | |
| 5565 %} | |
| 0 | 5566 ins_pipe(iload_mask_mem); |
| 5567 %} | |
| 5568 | |
| 624 | 5569 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5570 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5571 match(Set dst (LoadUB mem)); | |
| 0 | 5572 ins_cost(MEMORY_REF_COST); |
| 5573 | |
| 5574 size(4); | |
| 624 | 5575 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5576 ins_encode %{ |
| 5577 __ ldub($mem$$Address, $dst$$Register); | |
| 5578 %} | |
| 824 | 5579 ins_pipe(iload_mem); |
| 624 | 5580 %} |
| 5581 | |
| 5582 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5583 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5584 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5585 ins_cost(MEMORY_REF_COST); | |
| 5586 | |
| 5587 size(4); | |
| 5588 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5589 ins_encode %{ |
| 5590 __ ldub($mem$$Address, $dst$$Register); | |
| 5591 %} | |
| 824 | 5592 ins_pipe(iload_mem); |
| 5593 %} | |
| 5594 | |
| 5595 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5596 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5597 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5598 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5599 | |
| 5600 size(2*4); | |
| 5601 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5602 "AND $dst,$mask,$dst" %} | |
| 5603 ins_encode %{ | |
| 5604 __ ldub($mem$$Address, $dst$$Register); | |
| 5605 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5606 %} | |
| 5607 ins_pipe(iload_mem); | |
| 0 | 5608 %} |
| 5609 | |
| 624 | 5610 // Load Short (16bit signed) |
| 5611 instruct loadS(iRegI dst, memory mem) %{ | |
| 5612 match(Set dst (LoadS mem)); | |
| 5613 ins_cost(MEMORY_REF_COST); | |
| 5614 | |
| 5615 size(4); | |
| 5616 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5617 ins_encode %{ |
| 5618 __ ldsh($mem$$Address, $dst$$Register); | |
| 5619 %} | |
| 624 | 5620 ins_pipe(iload_mask_mem); |
| 5621 %} | |
| 5622 | |
| 785 | 5623 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5624 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5625 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5626 ins_cost(MEMORY_REF_COST); | |
| 5627 | |
| 5628 size(4); | |
| 5629 | |
| 5630 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5631 ins_encode %{ | |
| 5632 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5633 %} | |
| 5634 ins_pipe(iload_mask_mem); | |
| 5635 %} | |
| 5636 | |
| 624 | 5637 // Load Short (16bit signed) into a Long Register |
| 5638 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5639 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5640 ins_cost(MEMORY_REF_COST); |
| 5641 | |
| 5642 size(4); | |
| 624 | 5643 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5644 ins_encode %{ |
| 5645 __ ldsh($mem$$Address, $dst$$Register); | |
| 5646 %} | |
| 624 | 5647 ins_pipe(iload_mask_mem); |
| 5648 %} | |
| 5649 | |
| 5650 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5651 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5652 match(Set dst (LoadUS mem)); | |
| 5653 ins_cost(MEMORY_REF_COST); | |
| 5654 | |
| 5655 size(4); | |
| 5656 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5657 ins_encode %{ |
| 5658 __ lduh($mem$$Address, $dst$$Register); | |
| 5659 %} | |
| 824 | 5660 ins_pipe(iload_mem); |
| 0 | 5661 %} |
| 5662 | |
| 785 | 5663 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5664 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5665 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5666 ins_cost(MEMORY_REF_COST); | |
| 5667 | |
| 5668 size(4); | |
| 5669 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5670 ins_encode %{ | |
| 5671 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5672 %} | |
| 5673 ins_pipe(iload_mask_mem); | |
| 5674 %} | |
| 5675 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
5676 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5677 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5678 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5679 ins_cost(MEMORY_REF_COST); |
| 5680 | |
| 5681 size(4); | |
| 624 | 5682 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5683 ins_encode %{ |
| 5684 __ lduh($mem$$Address, $dst$$Register); | |
| 5685 %} | |
| 824 | 5686 ins_pipe(iload_mem); |
| 5687 %} | |
| 5688 | |
| 5689 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5690 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5691 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5692 ins_cost(MEMORY_REF_COST); | |
| 5693 | |
| 5694 size(4); | |
| 5695 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5696 ins_encode %{ | |
| 5697 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5698 %} | |
| 5699 ins_pipe(iload_mem); | |
| 5700 %} | |
| 5701 | |
| 5702 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5703 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5704 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5705 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5706 | |
| 5707 size(2*4); | |
| 5708 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5709 "AND $dst,$mask,$dst" %} | |
| 5710 ins_encode %{ | |
| 5711 Register Rdst = $dst$$Register; | |
| 5712 __ lduh($mem$$Address, Rdst); | |
| 5713 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5714 %} | |
| 5715 ins_pipe(iload_mem); | |
| 5716 %} | |
| 5717 | |
| 5718 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5719 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5720 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5721 effect(TEMP dst, TEMP tmp); | |
| 5722 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5723 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5724 size((3+1)*4); // set may use two instructions. |
| 824 | 5725 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5726 "SET $mask,$tmp\n\t" | |
| 5727 "AND $dst,$tmp,$dst" %} | |
| 5728 ins_encode %{ | |
| 5729 Register Rdst = $dst$$Register; | |
| 5730 Register Rtmp = $tmp$$Register; | |
| 5731 __ lduh($mem$$Address, Rdst); | |
| 5732 __ set($mask$$constant, Rtmp); | |
| 5733 __ and3(Rdst, Rtmp, Rdst); | |
| 5734 %} | |
| 5735 ins_pipe(iload_mem); | |
| 0 | 5736 %} |
| 5737 | |
| 5738 // Load Integer | |
| 5739 instruct loadI(iRegI dst, memory mem) %{ | |
| 5740 match(Set dst (LoadI mem)); | |
| 5741 ins_cost(MEMORY_REF_COST); | |
| 624 | 5742 |
| 5743 size(4); | |
| 5744 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5745 ins_encode %{ |
| 5746 __ lduw($mem$$Address, $dst$$Register); | |
| 5747 %} | |
| 624 | 5748 ins_pipe(iload_mem); |
| 5749 %} | |
| 5750 | |
| 785 | 5751 // Load Integer to Byte (8 bit signed) |
| 5752 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5753 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5754 ins_cost(MEMORY_REF_COST); | |
| 5755 | |
| 5756 size(4); | |
| 5757 | |
| 5758 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5759 ins_encode %{ | |
| 5760 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5761 %} | |
| 5762 ins_pipe(iload_mask_mem); | |
| 5763 %} | |
| 5764 | |
| 5765 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5766 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5767 match(Set dst (AndI (LoadI mem) mask)); | |
| 5768 ins_cost(MEMORY_REF_COST); | |
| 5769 | |
| 5770 size(4); | |
| 5771 | |
| 5772 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5773 ins_encode %{ | |
| 5774 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5775 %} | |
| 5776 ins_pipe(iload_mask_mem); | |
| 5777 %} | |
| 5778 | |
| 5779 // Load Integer to Short (16 bit signed) | |
| 5780 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5781 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5782 ins_cost(MEMORY_REF_COST); | |
| 5783 | |
| 5784 size(4); | |
| 5785 | |
| 5786 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5787 ins_encode %{ | |
| 5788 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5789 %} | |
| 5790 ins_pipe(iload_mask_mem); | |
| 5791 %} | |
| 5792 | |
| 5793 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5794 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5795 match(Set dst (AndI (LoadI mem) mask)); | |
| 5796 ins_cost(MEMORY_REF_COST); | |
| 5797 | |
| 5798 size(4); | |
| 5799 | |
| 5800 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5801 ins_encode %{ | |
| 5802 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5803 %} | |
| 5804 ins_pipe(iload_mask_mem); | |
| 5805 %} | |
| 5806 | |
| 624 | 5807 // Load Integer into a Long Register |
| 5808 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5809 match(Set dst (ConvI2L (LoadI mem))); | |
| 5810 ins_cost(MEMORY_REF_COST); | |
| 5811 | |
| 5812 size(4); | |
| 5813 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5814 ins_encode %{ |
| 5815 __ ldsw($mem$$Address, $dst$$Register); | |
| 5816 %} | |
| 824 | 5817 ins_pipe(iload_mask_mem); |
| 5818 %} | |
| 5819 | |
| 5820 // Load Integer with mask 0xFF into a Long Register | |
| 5821 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5822 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5823 ins_cost(MEMORY_REF_COST); | |
| 5824 | |
| 5825 size(4); | |
| 5826 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5827 ins_encode %{ | |
| 5828 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5829 %} | |
| 5830 ins_pipe(iload_mem); | |
| 5831 %} | |
| 5832 | |
| 5833 // Load Integer with mask 0xFFFF into a Long Register | |
| 5834 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5835 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5836 ins_cost(MEMORY_REF_COST); | |
| 5837 | |
| 5838 size(4); | |
| 5839 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5840 ins_encode %{ | |
| 5841 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5842 %} | |
| 5843 ins_pipe(iload_mem); | |
| 5844 %} | |
| 5845 | |
| 5846 // Load Integer with a 13-bit mask into a Long Register | |
| 5847 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5848 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5849 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5850 | |
| 5851 size(2*4); | |
| 5852 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5853 "AND $dst,$mask,$dst" %} | |
| 5854 ins_encode %{ | |
| 5855 Register Rdst = $dst$$Register; | |
| 5856 __ lduw($mem$$Address, Rdst); | |
| 5857 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5858 %} | |
| 5859 ins_pipe(iload_mem); | |
| 5860 %} | |
| 5861 | |
| 5862 // Load Integer with a 32-bit mask into a Long Register | |
| 5863 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5864 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5865 effect(TEMP dst, TEMP tmp); | |
| 5866 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5867 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5868 size((3+1)*4); // set may use two instructions. |
| 824 | 5869 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5870 "SET $mask,$tmp\n\t" | |
| 5871 "AND $dst,$tmp,$dst" %} | |
| 5872 ins_encode %{ | |
| 5873 Register Rdst = $dst$$Register; | |
| 5874 Register Rtmp = $tmp$$Register; | |
| 5875 __ lduw($mem$$Address, Rdst); | |
| 5876 __ set($mask$$constant, Rtmp); | |
| 5877 __ and3(Rdst, Rtmp, Rdst); | |
| 5878 %} | |
| 624 | 5879 ins_pipe(iload_mem); |
| 5880 %} | |
| 5881 | |
| 5882 // Load Unsigned Integer into a Long Register | |
| 5883 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5884 match(Set dst (LoadUI2L mem)); | |
| 5885 ins_cost(MEMORY_REF_COST); | |
| 5886 | |
| 5887 size(4); | |
| 5888 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5889 ins_encode %{ |
| 5890 __ lduw($mem$$Address, $dst$$Register); | |
| 5891 %} | |
| 0 | 5892 ins_pipe(iload_mem); |
| 5893 %} | |
| 5894 | |
| 5895 // Load Long - aligned | |
| 5896 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5897 match(Set dst (LoadL mem)); | |
| 5898 ins_cost(MEMORY_REF_COST); | |
| 624 | 5899 |
| 0 | 5900 size(4); |
| 5901 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5902 ins_encode %{ |
| 5903 __ ldx($mem$$Address, $dst$$Register); | |
| 5904 %} | |
| 0 | 5905 ins_pipe(iload_mem); |
| 5906 %} | |
| 5907 | |
| 5908 // Load Long - UNaligned | |
| 5909 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5910 match(Set dst (LoadL_unaligned mem)); | |
| 5911 effect(KILL tmp); | |
| 5912 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5913 size(16); | |
| 5914 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5915 "\tLDUW $mem ,$dst\n" | |
| 5916 "\tSLLX #32, $dst, $dst\n" | |
| 5917 "\tOR $dst, R_O7, $dst" %} | |
| 5918 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5919 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5920 ins_pipe(iload_mem); |
| 5921 %} | |
| 5922 | |
| 5923 // Load Range | |
| 5924 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5925 match(Set dst (LoadRange mem)); | |
| 5926 ins_cost(MEMORY_REF_COST); | |
| 5927 | |
| 5928 size(4); | |
| 5929 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5930 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5931 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5932 ins_pipe(iload_mem); |
| 5933 %} | |
| 5934 | |
| 5935 // Load Integer into %f register (for fitos/fitod) | |
| 5936 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5937 match(Set dst (LoadI mem)); | |
| 5938 ins_cost(MEMORY_REF_COST); | |
| 5939 size(4); | |
| 5940 | |
| 5941 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5942 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5943 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5944 ins_pipe(floadF_mem); |
| 5945 %} | |
| 5946 | |
| 5947 // Load Pointer | |
| 5948 instruct loadP(iRegP dst, memory mem) %{ | |
| 5949 match(Set dst (LoadP mem)); | |
| 5950 ins_cost(MEMORY_REF_COST); | |
| 5951 size(4); | |
| 5952 | |
| 5953 #ifndef _LP64 | |
| 5954 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5955 ins_encode %{ |
| 5956 __ lduw($mem$$Address, $dst$$Register); | |
| 5957 %} | |
| 0 | 5958 #else |
| 5959 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5960 ins_encode %{ |
| 5961 __ ldx($mem$$Address, $dst$$Register); | |
| 5962 %} | |
| 0 | 5963 #endif |
| 5964 ins_pipe(iload_mem); | |
| 5965 %} | |
| 5966 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5967 // Load Compressed Pointer |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5968 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5969 match(Set dst (LoadN mem)); |
| 5970 ins_cost(MEMORY_REF_COST); | |
| 5971 size(4); | |
| 5972 | |
| 5973 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5974 ins_encode %{ | |
| 5975 __ lduw($mem$$Address, $dst$$Register); | |
| 5976 %} | |
| 5977 ins_pipe(iload_mem); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5978 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5979 |
| 0 | 5980 // Load Klass Pointer |
| 5981 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5982 match(Set dst (LoadKlass mem)); | |
| 5983 ins_cost(MEMORY_REF_COST); | |
| 5984 size(4); | |
| 5985 | |
| 5986 #ifndef _LP64 | |
| 5987 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 5988 ins_encode %{ |
| 5989 __ lduw($mem$$Address, $dst$$Register); | |
| 5990 %} | |
| 0 | 5991 #else |
| 5992 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 5993 ins_encode %{ |
| 5994 __ ldx($mem$$Address, $dst$$Register); | |
| 5995 %} | |
| 0 | 5996 #endif |
| 5997 ins_pipe(iload_mem); | |
| 5998 %} | |
| 5999 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6000 // Load narrow Klass Pointer |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6001 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6002 match(Set dst (LoadNKlass mem)); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6003 ins_cost(MEMORY_REF_COST); |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
164
diff
changeset
|
6004 size(4); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6005 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6006 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6007 ins_encode %{ |
| 727 | 6008 __ lduw($mem$$Address, $dst$$Register); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6009 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6010 ins_pipe(iload_mem); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6011 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6012 |
| 0 | 6013 // Load Double |
| 6014 instruct loadD(regD dst, memory mem) %{ | |
| 6015 match(Set dst (LoadD mem)); | |
| 6016 ins_cost(MEMORY_REF_COST); | |
| 6017 | |
| 6018 size(4); | |
| 6019 format %{ "LDDF $mem,$dst" %} | |
| 6020 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6021 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6022 ins_pipe(floadD_mem); |
| 6023 %} | |
| 6024 | |
| 6025 // Load Double - UNaligned | |
| 6026 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6027 match(Set dst (LoadD_unaligned mem)); | |
| 6028 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6029 size(8); | |
| 6030 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6031 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6032 opcode(Assembler::ldf_op3); | |
| 6033 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6034 ins_pipe(iload_mem); | |
| 6035 %} | |
| 6036 | |
| 6037 // Load Float | |
| 6038 instruct loadF(regF dst, memory mem) %{ | |
| 6039 match(Set dst (LoadF mem)); | |
| 6040 ins_cost(MEMORY_REF_COST); | |
| 6041 | |
| 6042 size(4); | |
| 6043 format %{ "LDF $mem,$dst" %} | |
| 6044 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6045 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6046 ins_pipe(floadF_mem); |
| 6047 %} | |
| 6048 | |
| 6049 // Load Constant | |
| 6050 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6051 match(Set dst src); | |
| 6052 ins_cost(DEFAULT_COST * 3/2); | |
| 6053 format %{ "SET $src,$dst" %} | |
| 6054 ins_encode( Set32(src, dst) ); | |
| 6055 ins_pipe(ialu_hi_lo_reg); | |
| 6056 %} | |
| 6057 | |
| 6058 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6059 match(Set dst src); | |
| 6060 | |
| 6061 size(4); | |
| 6062 format %{ "MOV $src,$dst" %} | |
| 6063 ins_encode( Set13( src, dst ) ); | |
| 6064 ins_pipe(ialu_imm); | |
| 6065 %} | |
| 6066 | |
| 2008 | 6067 #ifndef _LP64 |
| 6068 instruct loadConP(iRegP dst, immP con) %{ | |
| 6069 match(Set dst con); | |
| 6070 ins_cost(DEFAULT_COST * 3/2); | |
| 6071 format %{ "SET $con,$dst\t!ptr" %} | |
| 6072 ins_encode %{ | |
| 6073 // [RGV] This next line should be generated from ADLC | |
| 6074 if (_opnds[1]->constant_is_oop()) { | |
| 6075 intptr_t val = $con$$constant; | |
| 6076 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6077 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6078 __ set($con$$constant, $dst$$Register); | |
| 6079 } | |
| 6080 %} | |
| 6081 ins_pipe(loadConP); | |
| 6082 %} | |
| 6083 #else | |
| 6084 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6085 match(Set dst con); | |
| 0 | 6086 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6087 format %{ "SET $con,$dst\t! ptr" %} |
| 6088 ins_encode %{ | |
| 6089 // [RGV] This next line should be generated from ADLC | |
| 6090 if (_opnds[1]->constant_is_oop()) { | |
| 6091 intptr_t val = $con$$constant; | |
| 6092 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6093 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6094 __ set($con$$constant, $dst$$Register); | |
| 6095 } | |
| 6096 %} | |
| 0 | 6097 ins_pipe(loadConP); |
| 2008 | 6098 %} |
| 6099 | |
| 6100 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6101 match(Set dst con); | |
| 6102 ins_cost(MEMORY_REF_COST); | |
| 6103 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6104 ins_encode %{ | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6105 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6106 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6107 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6108 ins_pipe(loadConP); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6109 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6110 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6111 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6112 match(Set dst con); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6113 ins_cost(DEFAULT_COST * 3/2); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6114 format %{ "SET $con,$dst\t! non-oop ptr" %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6115 ins_encode %{ |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6116 __ set($con$$constant, $dst$$Register); |
| 2008 | 6117 %} |
| 6118 ins_pipe(loadConP); | |
| 6119 %} | |
| 6120 #endif // _LP64 | |
| 0 | 6121 |
| 6122 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6123 match(Set dst src); | |
| 6124 | |
| 6125 size(4); | |
| 6126 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6127 ins_encode %{ |
| 6128 __ clr($dst$$Register); | |
| 6129 %} | |
| 0 | 6130 ins_pipe(ialu_imm); |
| 6131 %} | |
| 6132 | |
| 6133 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6134 match(Set dst src); | |
| 6135 ins_cost(DEFAULT_COST); | |
| 6136 format %{ "SET $src,$dst\t!ptr" %} | |
| 6137 ins_encode %{ | |
| 727 | 6138 AddressLiteral polling_page(os::get_polling_page()); |
| 6139 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6140 %} |
| 6141 ins_pipe(loadConP_poll); | |
| 6142 %} | |
| 6143 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6144 instruct loadConN0(iRegN dst, immN0 src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6145 match(Set dst src); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6146 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6147 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6148 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6149 ins_encode %{ |
| 6150 __ clr($dst$$Register); | |
| 6151 %} | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6152 ins_pipe(ialu_imm); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6153 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6154 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6155 instruct loadConN(iRegN dst, immN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6156 match(Set dst src); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6157 ins_cost(DEFAULT_COST * 3/2); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6158 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6159 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6160 Register dst = $dst$$Register; |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6161 __ set_narrow_oop((jobject)$src$$constant, dst); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6162 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6163 ins_pipe(ialu_hi_lo_reg); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6164 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6165 |
| 2008 | 6166 // Materialize long value (predicated by immL_cheap). |
| 6167 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6168 match(Set dst con); | |
| 0 | 6169 effect(KILL tmp); |
| 2008 | 6170 ins_cost(DEFAULT_COST * 3); |
| 6171 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6172 ins_encode %{ | |
| 6173 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6174 %} | |
| 6175 ins_pipe(loadConL); | |
| 6176 %} | |
| 6177 | |
| 6178 // Load long value from constant table (predicated by immL_expensive). | |
| 6179 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6180 match(Set dst con); | |
| 6181 ins_cost(MEMORY_REF_COST); | |
| 6182 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6183 ins_encode %{ | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6184 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6185 __ ldx($constanttablebase, con_offset, $dst$$Register); |
| 2008 | 6186 %} |
| 0 | 6187 ins_pipe(loadConL); |
| 6188 %} | |
| 6189 | |
| 6190 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6191 match(Set dst src); | |
| 6192 ins_cost(DEFAULT_COST); | |
| 6193 size(4); | |
| 6194 format %{ "CLR $dst\t! long" %} | |
| 6195 ins_encode( Set13( src, dst ) ); | |
| 6196 ins_pipe(ialu_imm); | |
| 6197 %} | |
| 6198 | |
| 6199 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6200 match(Set dst src); | |
| 6201 ins_cost(DEFAULT_COST * 2); | |
| 6202 | |
| 6203 size(4); | |
| 6204 format %{ "MOV $src,$dst\t! long" %} | |
| 6205 ins_encode( Set13( src, dst ) ); | |
| 6206 ins_pipe(ialu_imm); | |
| 6207 %} | |
| 6208 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6209 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
| 2008 | 6210 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6211 effect(KILL tmp); |
| 2008 | 6212 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
| 727 | 6213 ins_encode %{ |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6214 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6215 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
| 727 | 6216 %} |
| 0 | 6217 ins_pipe(loadConFD); |
| 6218 %} | |
| 6219 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6220 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
| 2008 | 6221 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6222 effect(KILL tmp); |
| 2008 | 6223 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
| 727 | 6224 ins_encode %{ |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6225 // XXX This is a quick fix for 6833573. |
| 2008 | 6226 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6227 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6228 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 727 | 6229 %} |
| 0 | 6230 ins_pipe(loadConFD); |
| 6231 %} | |
| 6232 | |
| 6233 // Prefetch instructions. | |
| 6234 // Must be safe to execute with invalid address (cannot fault). | |
| 6235 | |
| 6236 instruct prefetchr( memory mem ) %{ | |
| 6237 match( PrefetchRead mem ); | |
| 6238 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6239 size(4); |
| 0 | 6240 |
| 6241 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6242 opcode(Assembler::prefetch_op3); | |
| 6243 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6244 ins_pipe(iload_mem); | |
| 6245 %} | |
| 6246 | |
| 6247 instruct prefetchw( memory mem ) %{ | |
| 6248 match( PrefetchWrite mem ); | |
| 6249 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6250 size(4); |
| 0 | 6251 |
| 6252 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6253 opcode(Assembler::prefetch_op3); | |
| 6254 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6255 ins_pipe(iload_mem); | |
| 6256 %} | |
| 6257 | |
| 3854 | 6258 // Prefetch instructions for allocation. |
| 6259 | |
| 6260 instruct prefetchAlloc( memory mem ) %{ | |
| 6261 predicate(AllocatePrefetchInstr == 0); | |
| 6262 match( PrefetchAllocation mem ); | |
| 6263 ins_cost(MEMORY_REF_COST); | |
| 6264 size(4); | |
| 6265 | |
| 6266 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
| 6267 opcode(Assembler::prefetch_op3); | |
| 6268 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6269 ins_pipe(iload_mem); | |
| 6270 %} | |
| 6271 | |
| 6272 // Use BIS instruction to prefetch for allocation. | |
| 6273 // Could fault, need space at the end of TLAB. | |
| 6274 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
| 6275 predicate(AllocatePrefetchInstr == 1); | |
| 6276 match( PrefetchAllocation dst ); | |
| 6277 ins_cost(MEMORY_REF_COST); | |
| 6278 size(4); | |
| 6279 | |
| 6280 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
| 6281 ins_encode %{ | |
| 6282 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6283 %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6284 ins_pipe(istore_mem_reg); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6285 %} |
| 0 | 6286 |
| 3854 | 6287 // Next code is used for finding next cache line address to prefetch. |
| 6288 #ifndef _LP64 | |
| 6289 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
| 6290 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
| 6291 ins_cost(DEFAULT_COST); | |
| 6292 size(4); | |
| 6293 | |
| 6294 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6295 ins_encode %{ | |
| 6296 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6297 %} | |
| 6298 ins_pipe(ialu_reg_imm); | |
| 6299 %} | |
| 6300 #else | |
| 6301 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
| 6302 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
| 6303 ins_cost(DEFAULT_COST); | |
| 6304 size(4); | |
| 6305 | |
| 6306 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6307 ins_encode %{ | |
| 6308 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6309 %} | |
| 6310 ins_pipe(ialu_reg_imm); | |
| 6311 %} | |
| 6312 #endif | |
| 6313 | |
| 0 | 6314 //----------Store Instructions------------------------------------------------- |
| 6315 // Store Byte | |
| 6316 instruct storeB(memory mem, iRegI src) %{ | |
| 6317 match(Set mem (StoreB mem src)); | |
| 6318 ins_cost(MEMORY_REF_COST); | |
| 6319 | |
| 6320 size(4); | |
| 6321 format %{ "STB $src,$mem\t! byte" %} | |
| 6322 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6323 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6324 ins_pipe(istore_mem_reg); |
| 6325 %} | |
| 6326 | |
| 6327 instruct storeB0(memory mem, immI0 src) %{ | |
| 6328 match(Set mem (StoreB mem src)); | |
| 6329 ins_cost(MEMORY_REF_COST); | |
| 6330 | |
| 6331 size(4); | |
| 6332 format %{ "STB $src,$mem\t! byte" %} | |
| 6333 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6334 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6335 ins_pipe(istore_mem_zero); |
| 6336 %} | |
| 6337 | |
| 6338 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6339 match(Set mem (StoreCM mem src)); | |
| 6340 ins_cost(MEMORY_REF_COST); | |
| 6341 | |
| 6342 size(4); | |
| 6343 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6344 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6345 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6346 ins_pipe(istore_mem_zero); |
| 6347 %} | |
| 6348 | |
| 6349 // Store Char/Short | |
| 6350 instruct storeC(memory mem, iRegI src) %{ | |
| 6351 match(Set mem (StoreC mem src)); | |
| 6352 ins_cost(MEMORY_REF_COST); | |
| 6353 | |
| 6354 size(4); | |
| 6355 format %{ "STH $src,$mem\t! short" %} | |
| 6356 opcode(Assembler::sth_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6357 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6358 ins_pipe(istore_mem_reg); |
| 6359 %} | |
| 6360 | |
| 6361 instruct storeC0(memory mem, immI0 src) %{ | |
| 6362 match(Set mem (StoreC mem src)); | |
| 6363 ins_cost(MEMORY_REF_COST); | |
| 6364 | |
| 6365 size(4); | |
| 6366 format %{ "STH $src,$mem\t! short" %} | |
| 6367 opcode(Assembler::sth_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6368 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6369 ins_pipe(istore_mem_zero); |
| 6370 %} | |
| 6371 | |
| 6372 // Store Integer | |
| 6373 instruct storeI(memory mem, iRegI src) %{ | |
| 6374 match(Set mem (StoreI mem src)); | |
| 6375 ins_cost(MEMORY_REF_COST); | |
| 6376 | |
| 6377 size(4); | |
| 6378 format %{ "STW $src,$mem" %} | |
| 6379 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6380 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6381 ins_pipe(istore_mem_reg); |
| 6382 %} | |
| 6383 | |
| 6384 // Store Long | |
| 6385 instruct storeL(memory mem, iRegL src) %{ | |
| 6386 match(Set mem (StoreL mem src)); | |
| 6387 ins_cost(MEMORY_REF_COST); | |
| 6388 size(4); | |
| 6389 format %{ "STX $src,$mem\t! long" %} | |
| 6390 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6391 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6392 ins_pipe(istore_mem_reg); |
| 6393 %} | |
| 6394 | |
| 6395 instruct storeI0(memory mem, immI0 src) %{ | |
| 6396 match(Set mem (StoreI mem src)); | |
| 6397 ins_cost(MEMORY_REF_COST); | |
| 6398 | |
| 6399 size(4); | |
| 6400 format %{ "STW $src,$mem" %} | |
| 6401 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6402 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6403 ins_pipe(istore_mem_zero); |
| 6404 %} | |
| 6405 | |
| 6406 instruct storeL0(memory mem, immL0 src) %{ | |
| 6407 match(Set mem (StoreL mem src)); | |
| 6408 ins_cost(MEMORY_REF_COST); | |
| 6409 | |
| 6410 size(4); | |
| 6411 format %{ "STX $src,$mem" %} | |
| 6412 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6413 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6414 ins_pipe(istore_mem_zero); |
| 6415 %} | |
| 6416 | |
| 6417 // Store Integer from float register (used after fstoi) | |
| 6418 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6419 match(Set mem (StoreI mem src)); | |
| 6420 ins_cost(MEMORY_REF_COST); | |
| 6421 | |
| 6422 size(4); | |
| 6423 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6424 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6425 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6426 ins_pipe(fstoreF_mem_reg); |
| 6427 %} | |
| 6428 | |
| 6429 // Store Pointer | |
| 6430 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6431 match(Set dst (StoreP dst src)); | |
| 6432 ins_cost(MEMORY_REF_COST); | |
| 6433 size(4); | |
| 6434 | |
| 6435 #ifndef _LP64 | |
| 6436 format %{ "STW $src,$dst\t! ptr" %} | |
| 6437 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6438 #else | |
| 6439 format %{ "STX $src,$dst\t! ptr" %} | |
| 6440 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6441 #endif | |
| 6442 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6443 ins_pipe(istore_mem_spORreg); | |
| 6444 %} | |
| 6445 | |
| 6446 instruct storeP0(memory dst, immP0 src) %{ | |
| 6447 match(Set dst (StoreP dst src)); | |
| 6448 ins_cost(MEMORY_REF_COST); | |
| 6449 size(4); | |
| 6450 | |
| 6451 #ifndef _LP64 | |
| 6452 format %{ "STW $src,$dst\t! ptr" %} | |
| 6453 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6454 #else | |
| 6455 format %{ "STX $src,$dst\t! ptr" %} | |
| 6456 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6457 #endif | |
| 6458 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6459 ins_pipe(istore_mem_zero); | |
| 6460 %} | |
| 6461 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6462 // Store Compressed Pointer |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6463 instruct storeN(memory dst, iRegN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6464 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6465 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6466 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6467 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6468 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6469 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6470 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6471 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6472 Register src = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6473 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6474 __ stw(src, base, index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6475 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6476 __ stw(src, base, $dst$$disp); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6477 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6478 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6479 ins_pipe(istore_mem_spORreg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6480 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6481 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6482 instruct storeN0(memory dst, immN0 src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6483 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6484 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6485 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6486 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6487 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6488 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6489 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6490 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6491 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6492 __ stw(0, base, index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6493 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6494 __ stw(0, base, $dst$$disp); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6495 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6496 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6497 ins_pipe(istore_mem_zero); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6498 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6499 |
| 0 | 6500 // Store Double |
| 6501 instruct storeD( memory mem, regD src) %{ | |
| 6502 match(Set mem (StoreD mem src)); | |
| 6503 ins_cost(MEMORY_REF_COST); | |
| 6504 | |
| 6505 size(4); | |
| 6506 format %{ "STDF $src,$mem" %} | |
| 6507 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6508 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6509 ins_pipe(fstoreD_mem_reg); |
| 6510 %} | |
| 6511 | |
| 6512 instruct storeD0( memory mem, immD0 src) %{ | |
| 6513 match(Set mem (StoreD mem src)); | |
| 6514 ins_cost(MEMORY_REF_COST); | |
| 6515 | |
| 6516 size(4); | |
| 6517 format %{ "STX $src,$mem" %} | |
| 6518 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6519 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6520 ins_pipe(fstoreD_mem_zero); |
| 6521 %} | |
| 6522 | |
| 6523 // Store Float | |
| 6524 instruct storeF( memory mem, regF src) %{ | |
| 6525 match(Set mem (StoreF mem src)); | |
| 6526 ins_cost(MEMORY_REF_COST); | |
| 6527 | |
| 6528 size(4); | |
| 6529 format %{ "STF $src,$mem" %} | |
| 6530 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6531 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6532 ins_pipe(fstoreF_mem_reg); |
| 6533 %} | |
| 6534 | |
| 6535 instruct storeF0( memory mem, immF0 src) %{ | |
| 6536 match(Set mem (StoreF mem src)); | |
| 6537 ins_cost(MEMORY_REF_COST); | |
| 6538 | |
| 6539 size(4); | |
| 6540 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6541 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6542 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6543 ins_pipe(fstoreF_mem_zero); |
| 6544 %} | |
| 6545 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6546 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6547 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6548 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6549 match(Set dst (EncodeP src)); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6550 format %{ "encode_heap_oop $src, $dst" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6551 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6552 __ encode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6553 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6554 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6555 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6556 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6557 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6558 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6559 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6560 format %{ "encode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6561 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6562 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6563 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6564 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6565 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6566 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6567 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6568 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6569 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6570 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6571 format %{ "decode_heap_oop $src, $dst" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6572 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6573 __ decode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6574 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6575 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6576 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6577 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6578 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6579 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6580 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6581 match(Set dst (DecodeN src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6582 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6583 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6584 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6585 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6586 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6587 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6588 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6589 |
| 0 | 6590 //----------MemBar Instructions----------------------------------------------- |
| 6591 // Memory barrier flavors | |
| 6592 | |
| 6593 instruct membar_acquire() %{ | |
| 6594 match(MemBarAcquire); | |
| 6595 ins_cost(4*MEMORY_REF_COST); | |
| 6596 | |
| 6597 size(0); | |
| 6598 format %{ "MEMBAR-acquire" %} | |
| 6599 ins_encode( enc_membar_acquire ); | |
| 6600 ins_pipe(long_memory_op); | |
| 6601 %} | |
| 6602 | |
| 6603 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6604 match(MemBarAcquireLock); |
| 0 | 6605 ins_cost(0); |
| 6606 | |
| 6607 size(0); | |
| 6608 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6609 ins_encode( ); | |
| 6610 ins_pipe(empty); | |
| 6611 %} | |
| 6612 | |
| 6613 instruct membar_release() %{ | |
| 6614 match(MemBarRelease); | |
| 6615 ins_cost(4*MEMORY_REF_COST); | |
| 6616 | |
| 6617 size(0); | |
| 6618 format %{ "MEMBAR-release" %} | |
| 6619 ins_encode( enc_membar_release ); | |
| 6620 ins_pipe(long_memory_op); | |
| 6621 %} | |
| 6622 | |
| 6623 instruct membar_release_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6624 match(MemBarReleaseLock); |
| 0 | 6625 ins_cost(0); |
| 6626 | |
| 6627 size(0); | |
| 6628 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6629 ins_encode( ); | |
| 6630 ins_pipe(empty); | |
| 6631 %} | |
| 6632 | |
| 6633 instruct membar_volatile() %{ | |
| 6634 match(MemBarVolatile); | |
| 6635 ins_cost(4*MEMORY_REF_COST); | |
| 6636 | |
| 6637 size(4); | |
| 6638 format %{ "MEMBAR-volatile" %} | |
| 6639 ins_encode( enc_membar_volatile ); | |
| 6640 ins_pipe(long_memory_op); | |
| 6641 %} | |
| 6642 | |
| 6643 instruct unnecessary_membar_volatile() %{ | |
| 6644 match(MemBarVolatile); | |
| 6645 predicate(Matcher::post_store_load_barrier(n)); | |
| 6646 ins_cost(0); | |
| 6647 | |
| 6648 size(0); | |
| 6649 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6650 ins_encode( ); | |
| 6651 ins_pipe(empty); | |
| 6652 %} | |
| 6653 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6654 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6655 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6656 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6657 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6658 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6659 format %{ "!MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6660 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6661 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6662 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6663 |
| 0 | 6664 //----------Register Move Instructions----------------------------------------- |
| 6665 instruct roundDouble_nop(regD dst) %{ | |
| 6666 match(Set dst (RoundDouble dst)); | |
| 6667 ins_cost(0); | |
| 6668 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6669 ins_encode( ); | |
| 6670 ins_pipe(empty); | |
| 6671 %} | |
| 6672 | |
| 6673 | |
| 6674 instruct roundFloat_nop(regF dst) %{ | |
| 6675 match(Set dst (RoundFloat dst)); | |
| 6676 ins_cost(0); | |
| 6677 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6678 ins_encode( ); | |
| 6679 ins_pipe(empty); | |
| 6680 %} | |
| 6681 | |
| 6682 | |
| 6683 // Cast Index to Pointer for unsafe natives | |
| 6684 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6685 match(Set dst (CastX2P src)); | |
| 6686 | |
| 6687 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6688 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6689 ins_pipe(ialu_reg); | |
| 6690 %} | |
| 6691 | |
| 6692 // Cast Pointer to Index for unsafe natives | |
| 6693 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6694 match(Set dst (CastP2X src)); | |
| 6695 | |
| 6696 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6697 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6698 ins_pipe(ialu_reg); | |
| 6699 %} | |
| 6700 | |
| 6701 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6702 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6703 match(Set stkSlot src); // chain rule | |
| 6704 ins_cost(MEMORY_REF_COST); | |
| 6705 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6706 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6707 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6708 ins_pipe(fstoreD_stk_reg); |
| 6709 %} | |
| 6710 | |
| 6711 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6712 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6713 match(Set dst stkSlot); // chain rule | |
| 6714 ins_cost(MEMORY_REF_COST); | |
| 6715 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6716 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6717 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6718 ins_pipe(floadD_stk); |
| 6719 %} | |
| 6720 | |
| 6721 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6722 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6723 match(Set stkSlot src); // chain rule | |
| 6724 ins_cost(MEMORY_REF_COST); | |
| 6725 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6726 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6727 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6728 ins_pipe(fstoreF_stk_reg); |
| 6729 %} | |
| 6730 | |
| 6731 //----------Conditional Move--------------------------------------------------- | |
| 6732 // Conditional move | |
| 6733 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6734 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6735 ins_cost(150); | |
| 6736 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6737 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6738 ins_pipe(ialu_reg); | |
| 6739 %} | |
| 6740 | |
| 6741 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6742 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6743 ins_cost(140); | |
| 6744 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6745 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6746 ins_pipe(ialu_imm); | |
| 6747 %} | |
| 6748 | |
| 6749 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6750 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6751 ins_cost(150); | |
| 6752 size(4); | |
| 6753 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6754 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6755 ins_pipe(ialu_reg); | |
| 6756 %} | |
| 6757 | |
| 6758 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6759 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6760 ins_cost(140); | |
| 6761 size(4); | |
| 6762 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6763 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6764 ins_pipe(ialu_imm); | |
| 6765 %} | |
| 6766 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6767 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6768 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6769 ins_cost(150); | |
| 6770 size(4); | |
| 6771 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6772 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6773 ins_pipe(ialu_reg); | |
| 6774 %} | |
| 6775 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6776 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6777 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6778 ins_cost(140); | |
| 6779 size(4); | |
| 6780 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6781 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6782 ins_pipe(ialu_imm); | |
| 6783 %} | |
| 6784 | |
| 6785 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6786 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6787 ins_cost(150); | |
| 6788 size(4); | |
| 6789 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6790 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6791 ins_pipe(ialu_reg); | |
| 6792 %} | |
| 6793 | |
| 6794 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6795 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6796 ins_cost(140); | |
| 6797 size(4); | |
| 6798 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6799 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6800 ins_pipe(ialu_imm); | |
| 6801 %} | |
| 6802 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6803 // Conditional move for RegN. Only cmov(reg,reg). |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6804 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6805 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6806 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6807 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6808 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6809 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6810 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6811 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6812 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6813 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6814 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6815 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6816 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6817 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6818 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6819 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6820 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6821 |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6822 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6823 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6824 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6825 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6826 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6827 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6828 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6829 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6830 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6831 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6832 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6833 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6834 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6835 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6836 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6837 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6838 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6839 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6840 |
| 0 | 6841 // Conditional move |
| 6842 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6843 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6844 ins_cost(150); | |
| 6845 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6846 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6847 ins_pipe(ialu_reg); | |
| 6848 %} | |
| 6849 | |
| 6850 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6851 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6852 ins_cost(140); | |
| 6853 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6854 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6855 ins_pipe(ialu_imm); | |
| 6856 %} | |
| 6857 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6858 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6859 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6860 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6861 ins_cost(150); | |
| 6862 | |
| 6863 size(4); | |
| 6864 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6865 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6866 ins_pipe(ialu_reg); | |
| 6867 %} | |
| 6868 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6869 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6870 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6871 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6872 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6873 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6874 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6875 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6876 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6877 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6878 |
| 0 | 6879 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6880 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6881 ins_cost(140); | |
| 6882 | |
| 6883 size(4); | |
| 6884 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6885 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6886 ins_pipe(ialu_imm); | |
| 6887 %} | |
| 6888 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6889 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6890 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6891 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6892 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6893 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6894 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6895 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6896 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6897 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6898 |
| 0 | 6899 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6900 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6901 ins_cost(150); | |
| 6902 size(4); | |
| 6903 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6904 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6905 ins_pipe(ialu_imm); | |
| 6906 %} | |
| 6907 | |
| 6908 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6909 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6910 ins_cost(140); | |
| 6911 size(4); | |
| 6912 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6913 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6914 ins_pipe(ialu_imm); | |
| 6915 %} | |
| 6916 | |
| 6917 // Conditional move | |
| 6918 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6919 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6920 ins_cost(150); | |
| 6921 opcode(0x101); | |
| 6922 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6923 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6924 ins_pipe(int_conditional_float_move); | |
| 6925 %} | |
| 6926 | |
| 6927 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6928 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6929 ins_cost(150); | |
| 6930 | |
| 6931 size(4); | |
| 6932 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6933 opcode(0x101); | |
| 6934 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6935 ins_pipe(int_conditional_float_move); | |
| 6936 %} | |
| 6937 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6938 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6939 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6940 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6941 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6942 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6943 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6944 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6945 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6946 ins_pipe(int_conditional_float_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6947 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6948 |
| 0 | 6949 // Conditional move, |
| 6950 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6951 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6952 ins_cost(150); | |
| 6953 size(4); | |
| 6954 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6955 opcode(0x1); | |
| 6956 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6957 ins_pipe(int_conditional_double_move); | |
| 6958 %} | |
| 6959 | |
| 6960 // Conditional move | |
| 6961 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6962 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6963 ins_cost(150); | |
| 6964 size(4); | |
| 6965 opcode(0x102); | |
| 6966 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6967 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6968 ins_pipe(int_conditional_double_move); | |
| 6969 %} | |
| 6970 | |
| 6971 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 6972 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 6973 ins_cost(150); | |
| 6974 | |
| 6975 size(4); | |
| 6976 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 6977 opcode(0x102); | |
| 6978 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6979 ins_pipe(int_conditional_double_move); | |
| 6980 %} | |
| 6981 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6982 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6983 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6984 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6985 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6986 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6987 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6988 opcode(0x102); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6989 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6990 ins_pipe(int_conditional_double_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6991 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6992 |
| 0 | 6993 // Conditional move, |
| 6994 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 6995 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 6996 ins_cost(150); | |
| 6997 size(4); | |
| 6998 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 6999 opcode(0x2); | |
| 7000 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7001 ins_pipe(int_conditional_double_move); | |
| 7002 %} | |
| 7003 | |
| 7004 // Conditional move | |
| 7005 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7006 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7007 ins_cost(150); | |
| 7008 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7009 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7010 ins_pipe(ialu_reg); | |
| 7011 %} | |
| 7012 | |
| 7013 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7014 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7015 ins_cost(140); | |
| 7016 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7017 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7018 ins_pipe(ialu_imm); | |
| 7019 %} | |
| 7020 | |
| 7021 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7022 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7023 ins_cost(150); | |
| 7024 | |
| 7025 size(4); | |
| 7026 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7027 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7028 ins_pipe(ialu_reg); | |
| 7029 %} | |
| 7030 | |
| 7031 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7032 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7033 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7034 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7035 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7036 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7037 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7038 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7039 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7040 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7041 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7042 |
| 0 | 7043 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7044 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7045 ins_cost(150); | |
| 7046 | |
| 7047 size(4); | |
| 7048 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7049 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7050 ins_pipe(ialu_reg); | |
| 7051 %} | |
| 7052 | |
| 7053 | |
| 7054 | |
| 7055 //----------OS and Locking Instructions---------------------------------------- | |
| 7056 | |
| 7057 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7058 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7059 // for this guy. | |
| 7060 instruct tlsLoadP(g2RegP dst) %{ | |
| 7061 match(Set dst (ThreadLocal)); | |
| 7062 | |
| 7063 size(0); | |
| 7064 ins_cost(0); | |
| 7065 format %{ "# TLS is in G2" %} | |
| 7066 ins_encode( /*empty encoding*/ ); | |
| 7067 ins_pipe(ialu_none); | |
| 7068 %} | |
| 7069 | |
| 7070 instruct checkCastPP( iRegP dst ) %{ | |
| 7071 match(Set dst (CheckCastPP dst)); | |
| 7072 | |
| 7073 size(0); | |
| 7074 format %{ "# checkcastPP of $dst" %} | |
| 7075 ins_encode( /*empty encoding*/ ); | |
| 7076 ins_pipe(empty); | |
| 7077 %} | |
| 7078 | |
| 7079 | |
| 7080 instruct castPP( iRegP dst ) %{ | |
| 7081 match(Set dst (CastPP dst)); | |
| 7082 format %{ "# castPP of $dst" %} | |
| 7083 ins_encode( /*empty encoding*/ ); | |
| 7084 ins_pipe(empty); | |
| 7085 %} | |
| 7086 | |
| 7087 instruct castII( iRegI dst ) %{ | |
| 7088 match(Set dst (CastII dst)); | |
| 7089 format %{ "# castII of $dst" %} | |
| 7090 ins_encode( /*empty encoding*/ ); | |
| 7091 ins_cost(0); | |
| 7092 ins_pipe(empty); | |
| 7093 %} | |
| 7094 | |
| 7095 //----------Arithmetic Instructions-------------------------------------------- | |
| 7096 // Addition Instructions | |
| 7097 // Register Addition | |
| 7098 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7099 match(Set dst (AddI src1 src2)); | |
| 7100 | |
| 7101 size(4); | |
| 7102 format %{ "ADD $src1,$src2,$dst" %} | |
| 7103 ins_encode %{ | |
| 7104 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7105 %} | |
| 7106 ins_pipe(ialu_reg_reg); | |
| 7107 %} | |
| 7108 | |
| 7109 // Immediate Addition | |
| 7110 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7111 match(Set dst (AddI src1 src2)); | |
| 7112 | |
| 7113 size(4); | |
| 7114 format %{ "ADD $src1,$src2,$dst" %} | |
| 7115 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7116 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7117 ins_pipe(ialu_reg_imm); | |
| 7118 %} | |
| 7119 | |
| 7120 // Pointer Register Addition | |
| 7121 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7122 match(Set dst (AddP src1 src2)); | |
| 7123 | |
| 7124 size(4); | |
| 7125 format %{ "ADD $src1,$src2,$dst" %} | |
| 7126 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7127 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7128 ins_pipe(ialu_reg_reg); | |
| 7129 %} | |
| 7130 | |
| 7131 // Pointer Immediate Addition | |
| 7132 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7133 match(Set dst (AddP src1 src2)); | |
| 7134 | |
| 7135 size(4); | |
| 7136 format %{ "ADD $src1,$src2,$dst" %} | |
| 7137 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7138 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7139 ins_pipe(ialu_reg_imm); | |
| 7140 %} | |
| 7141 | |
| 7142 // Long Addition | |
| 7143 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7144 match(Set dst (AddL src1 src2)); | |
| 7145 | |
| 7146 size(4); | |
| 7147 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7148 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7149 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7150 ins_pipe(ialu_reg_reg); | |
| 7151 %} | |
| 7152 | |
| 7153 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7154 match(Set dst (AddL src1 con)); | |
| 7155 | |
| 7156 size(4); | |
| 7157 format %{ "ADD $src1,$con,$dst" %} | |
| 7158 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7159 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7160 ins_pipe(ialu_reg_imm); | |
| 7161 %} | |
| 7162 | |
| 7163 //----------Conditional_store-------------------------------------------------- | |
| 7164 // Conditional-store of the updated heap-top. | |
| 7165 // Used during allocation of the shared heap. | |
| 7166 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7167 | |
| 7168 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7169 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7170 match(Set dst (LoadPLocked mem)); | |
| 7171 ins_cost(MEMORY_REF_COST); | |
| 7172 | |
| 7173 #ifndef _LP64 | |
| 7174 size(4); | |
| 7175 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7176 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7177 #else | |
| 7178 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7179 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7180 #endif | |
| 7181 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7182 ins_pipe(iload_mem); | |
| 7183 %} | |
| 7184 | |
| 7185 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7186 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7187 effect( KILL newval ); | |
| 7188 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7189 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7190 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7191 ins_pipe( long_memory_op ); | |
| 7192 %} | |
| 7193 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7194 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7195 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7196 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7197 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7198 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7199 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7200 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7201 ins_pipe( long_memory_op ); |
| 7202 %} | |
| 7203 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7204 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7205 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7206 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7207 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7208 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7209 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7210 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7211 ins_pipe( long_memory_op ); |
| 7212 %} | |
| 7213 | |
| 7214 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7215 | |
| 7216 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7217 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7218 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7219 format %{ | |
| 7220 "MOV $newval,O7\n\t" | |
| 7221 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7222 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7223 "MOV 1,$res\n\t" | |
| 7224 "MOVne xcc,R_G0,$res" | |
| 7225 %} | |
| 7226 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7227 enc_lflags_ne_to_boolean(res) ); | |
| 7228 ins_pipe( long_memory_op ); | |
| 7229 %} | |
| 7230 | |
| 7231 | |
| 7232 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7233 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7234 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7235 format %{ | |
| 7236 "MOV $newval,O7\n\t" | |
| 7237 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7238 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7239 "MOV 1,$res\n\t" | |
| 7240 "MOVne icc,R_G0,$res" | |
| 7241 %} | |
| 7242 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7243 enc_iflags_ne_to_boolean(res) ); | |
| 7244 ins_pipe( long_memory_op ); | |
| 7245 %} | |
| 7246 | |
| 7247 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7248 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7249 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7250 format %{ | |
| 7251 "MOV $newval,O7\n\t" | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7252 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7253 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7254 "MOV 1,$res\n\t" | |
| 7255 "MOVne xcc,R_G0,$res" | |
| 7256 %} | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7257 #ifdef _LP64 |
| 0 | 7258 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7259 enc_lflags_ne_to_boolean(res) ); | |
| 7260 #else | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7261 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7262 enc_iflags_ne_to_boolean(res) ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7263 #endif |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7264 ins_pipe( long_memory_op ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7265 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7266 |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7267 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7268 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7269 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7270 format %{ |
| 7271 "MOV $newval,O7\n\t" | |
| 7272 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7273 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7274 "MOV 1,$res\n\t" | |
| 7275 "MOVne icc,R_G0,$res" | |
| 7276 %} | |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7277 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7278 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7279 ins_pipe( long_memory_op ); |
| 7280 %} | |
| 7281 | |
| 7282 //--------------------- | |
| 7283 // Subtraction Instructions | |
| 7284 // Register Subtraction | |
| 7285 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7286 match(Set dst (SubI src1 src2)); | |
| 7287 | |
| 7288 size(4); | |
| 7289 format %{ "SUB $src1,$src2,$dst" %} | |
| 7290 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7291 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7292 ins_pipe(ialu_reg_reg); | |
| 7293 %} | |
| 7294 | |
| 7295 // Immediate Subtraction | |
| 7296 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7297 match(Set dst (SubI src1 src2)); | |
| 7298 | |
| 7299 size(4); | |
| 7300 format %{ "SUB $src1,$src2,$dst" %} | |
| 7301 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7302 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7303 ins_pipe(ialu_reg_imm); | |
| 7304 %} | |
| 7305 | |
| 7306 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7307 match(Set dst (SubI zero src2)); | |
| 7308 | |
| 7309 size(4); | |
| 7310 format %{ "NEG $src2,$dst" %} | |
| 7311 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7312 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7313 ins_pipe(ialu_zero_reg); | |
| 7314 %} | |
| 7315 | |
| 7316 // Long subtraction | |
| 7317 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7318 match(Set dst (SubL src1 src2)); | |
| 7319 | |
| 7320 size(4); | |
| 7321 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7322 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7323 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7324 ins_pipe(ialu_reg_reg); | |
| 7325 %} | |
| 7326 | |
| 7327 // Immediate Subtraction | |
| 7328 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7329 match(Set dst (SubL src1 con)); | |
| 7330 | |
| 7331 size(4); | |
| 7332 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7333 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7334 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7335 ins_pipe(ialu_reg_imm); | |
| 7336 %} | |
| 7337 | |
| 7338 // Long negation | |
| 7339 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7340 match(Set dst (SubL zero src2)); | |
| 7341 | |
| 7342 size(4); | |
| 7343 format %{ "NEG $src2,$dst\t! long" %} | |
| 7344 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7345 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7346 ins_pipe(ialu_zero_reg); | |
| 7347 %} | |
| 7348 | |
| 7349 // Multiplication Instructions | |
| 7350 // Integer Multiplication | |
| 7351 // Register Multiplication | |
| 7352 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7353 match(Set dst (MulI src1 src2)); | |
| 7354 | |
| 7355 size(4); | |
| 7356 format %{ "MULX $src1,$src2,$dst" %} | |
| 7357 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7358 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7359 ins_pipe(imul_reg_reg); | |
| 7360 %} | |
| 7361 | |
| 7362 // Immediate Multiplication | |
| 7363 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7364 match(Set dst (MulI src1 src2)); | |
| 7365 | |
| 7366 size(4); | |
| 7367 format %{ "MULX $src1,$src2,$dst" %} | |
| 7368 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7369 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7370 ins_pipe(imul_reg_imm); | |
| 7371 %} | |
| 7372 | |
| 7373 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7374 match(Set dst (MulL src1 src2)); | |
| 7375 ins_cost(DEFAULT_COST * 5); | |
| 7376 size(4); | |
| 7377 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7378 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7379 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7380 ins_pipe(mulL_reg_reg); | |
| 7381 %} | |
| 7382 | |
| 7383 // Immediate Multiplication | |
| 7384 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7385 match(Set dst (MulL src1 src2)); | |
| 7386 ins_cost(DEFAULT_COST * 5); | |
| 7387 size(4); | |
| 7388 format %{ "MULX $src1,$src2,$dst" %} | |
| 7389 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7390 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7391 ins_pipe(mulL_reg_imm); | |
| 7392 %} | |
| 7393 | |
| 7394 // Integer Division | |
| 7395 // Register Division | |
| 7396 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7397 match(Set dst (DivI src1 src2)); | |
| 7398 ins_cost((2+71)*DEFAULT_COST); | |
| 7399 | |
| 7400 format %{ "SRA $src2,0,$src2\n\t" | |
| 7401 "SRA $src1,0,$src1\n\t" | |
| 7402 "SDIVX $src1,$src2,$dst" %} | |
| 7403 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7404 ins_pipe(sdiv_reg_reg); | |
| 7405 %} | |
| 7406 | |
| 7407 // Immediate Division | |
| 7408 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7409 match(Set dst (DivI src1 src2)); | |
| 7410 ins_cost((2+71)*DEFAULT_COST); | |
| 7411 | |
| 7412 format %{ "SRA $src1,0,$src1\n\t" | |
| 7413 "SDIVX $src1,$src2,$dst" %} | |
| 7414 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7415 ins_pipe(sdiv_reg_imm); | |
| 7416 %} | |
| 7417 | |
| 7418 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7419 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7420 // Expand rule only, not matched | |
| 7421 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7422 effect( DEF dst, USE src1, USE src2 ); | |
| 7423 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7424 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7425 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7426 ins_pipe(sdiv_reg_reg); | |
| 7427 %} | |
| 7428 | |
| 605 | 7429 // Magic constant, reciprocal of 10 |
| 0 | 7430 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7431 effect( DEF dst ); | |
| 7432 | |
| 7433 size(8); | |
| 7434 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7435 ins_encode( Set32(0x66666667, dst) ); | |
| 7436 ins_pipe(ialu_hi_lo_reg); | |
| 7437 %} | |
| 7438 | |
| 605 | 7439 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7440 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7441 effect( DEF dst, USE src ); | |
| 7442 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7443 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7444 ins_pipe(ialu_reg_reg); | |
| 7445 %} | |
| 7446 | |
| 7447 // Arithmetic Shift Right by 8-bit immediate | |
| 7448 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7449 effect( DEF dst, USE src ); | |
| 7450 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7451 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7452 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7453 ins_pipe(ialu_reg_imm); | |
| 7454 %} | |
| 7455 | |
| 7456 // Integer DIV with 10 | |
| 7457 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7458 match(Set dst (DivI src div)); | |
| 7459 ins_cost((6+6)*DEFAULT_COST); | |
| 7460 expand %{ | |
| 7461 iRegIsafe tmp1; // Killed temps; | |
| 7462 iRegIsafe tmp2; // Killed temps; | |
| 7463 iRegI tmp3; // Killed temps; | |
| 7464 iRegI tmp4; // Killed temps; | |
| 7465 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7466 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7467 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7468 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7469 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7470 %} | |
| 7471 %} | |
| 7472 | |
| 7473 // Register Long Division | |
| 7474 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7475 match(Set dst (DivL src1 src2)); | |
| 7476 ins_cost(DEFAULT_COST*71); | |
| 7477 size(4); | |
| 7478 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7479 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7480 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7481 ins_pipe(divL_reg_reg); | |
| 7482 %} | |
| 7483 | |
| 7484 // Register Long Division | |
| 7485 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7486 match(Set dst (DivL src1 src2)); | |
| 7487 ins_cost(DEFAULT_COST*71); | |
| 7488 size(4); | |
| 7489 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7490 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7491 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7492 ins_pipe(divL_reg_imm); | |
| 7493 %} | |
| 7494 | |
| 7495 // Integer Remainder | |
| 7496 // Register Remainder | |
| 7497 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7498 match(Set dst (ModI src1 src2)); | |
| 7499 effect( KILL ccr, KILL temp); | |
| 7500 | |
| 7501 format %{ "SREM $src1,$src2,$dst" %} | |
| 7502 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7503 ins_pipe(sdiv_reg_reg); | |
| 7504 %} | |
| 7505 | |
| 7506 // Immediate Remainder | |
| 7507 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7508 match(Set dst (ModI src1 src2)); | |
| 7509 effect( KILL ccr, KILL temp); | |
| 7510 | |
| 7511 format %{ "SREM $src1,$src2,$dst" %} | |
| 7512 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7513 ins_pipe(sdiv_reg_imm); | |
| 7514 %} | |
| 7515 | |
| 7516 // Register Long Remainder | |
| 7517 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7518 effect(DEF dst, USE src1, USE src2); | |
| 7519 size(4); | |
| 7520 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7521 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7522 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7523 ins_pipe(divL_reg_reg); | |
| 7524 %} | |
| 7525 | |
| 7526 // Register Long Division | |
| 7527 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7528 effect(DEF dst, USE src1, USE src2); | |
| 7529 size(4); | |
| 7530 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7531 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7532 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7533 ins_pipe(divL_reg_imm); | |
| 7534 %} | |
| 7535 | |
| 7536 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7537 effect(DEF dst, USE src1, USE src2); | |
| 7538 size(4); | |
| 7539 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7540 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7541 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7542 ins_pipe(mulL_reg_reg); | |
| 7543 %} | |
| 7544 | |
| 7545 // Immediate Multiplication | |
| 7546 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7547 effect(DEF dst, USE src1, USE src2); | |
| 7548 size(4); | |
| 7549 format %{ "MULX $src1,$src2,$dst" %} | |
| 7550 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7551 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7552 ins_pipe(mulL_reg_imm); | |
| 7553 %} | |
| 7554 | |
| 7555 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7556 effect(DEF dst, USE src1, USE src2); | |
| 7557 size(4); | |
| 7558 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7559 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7560 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7561 ins_pipe(ialu_reg_reg); | |
| 7562 %} | |
| 7563 | |
| 7564 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7565 effect(DEF dst, USE src1, USE src2); | |
| 7566 size(4); | |
| 7567 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7568 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7569 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7570 ins_pipe(ialu_reg_reg); | |
| 7571 %} | |
| 7572 | |
| 7573 // Register Long Remainder | |
| 7574 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7575 match(Set dst (ModL src1 src2)); | |
| 7576 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7577 expand %{ | |
| 7578 iRegL tmp1; | |
| 7579 iRegL tmp2; | |
| 7580 divL_reg_reg_1(tmp1, src1, src2); | |
| 7581 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7582 subL_reg_reg_1(dst, src1, tmp2); | |
| 7583 %} | |
| 7584 %} | |
| 7585 | |
| 7586 // Register Long Remainder | |
| 7587 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7588 match(Set dst (ModL src1 src2)); | |
| 7589 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7590 expand %{ | |
| 7591 iRegL tmp1; | |
| 7592 iRegL tmp2; | |
| 7593 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7594 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7595 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7596 %} | |
| 7597 %} | |
| 7598 | |
| 7599 // Integer Shift Instructions | |
| 7600 // Register Shift Left | |
| 7601 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7602 match(Set dst (LShiftI src1 src2)); | |
| 7603 | |
| 7604 size(4); | |
| 7605 format %{ "SLL $src1,$src2,$dst" %} | |
| 7606 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7607 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7608 ins_pipe(ialu_reg_reg); | |
| 7609 %} | |
| 7610 | |
| 7611 // Register Shift Left Immediate | |
| 7612 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7613 match(Set dst (LShiftI src1 src2)); | |
| 7614 | |
| 7615 size(4); | |
| 7616 format %{ "SLL $src1,$src2,$dst" %} | |
| 7617 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7618 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7619 ins_pipe(ialu_reg_imm); | |
| 7620 %} | |
| 7621 | |
| 7622 // Register Shift Left | |
| 7623 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7624 match(Set dst (LShiftL src1 src2)); | |
| 7625 | |
| 7626 size(4); | |
| 7627 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7628 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7629 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7630 ins_pipe(ialu_reg_reg); | |
| 7631 %} | |
| 7632 | |
| 7633 // Register Shift Left Immediate | |
| 7634 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7635 match(Set dst (LShiftL src1 src2)); | |
| 7636 | |
| 7637 size(4); | |
| 7638 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7639 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7640 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7641 ins_pipe(ialu_reg_imm); | |
| 7642 %} | |
| 7643 | |
| 7644 // Register Arithmetic Shift Right | |
| 7645 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7646 match(Set dst (RShiftI src1 src2)); | |
| 7647 size(4); | |
| 7648 format %{ "SRA $src1,$src2,$dst" %} | |
| 7649 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7650 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7651 ins_pipe(ialu_reg_reg); | |
| 7652 %} | |
| 7653 | |
| 7654 // Register Arithmetic Shift Right Immediate | |
| 7655 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7656 match(Set dst (RShiftI src1 src2)); | |
| 7657 | |
| 7658 size(4); | |
| 7659 format %{ "SRA $src1,$src2,$dst" %} | |
| 7660 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7661 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7662 ins_pipe(ialu_reg_imm); | |
| 7663 %} | |
| 7664 | |
| 7665 // Register Shift Right Arithmatic Long | |
| 7666 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7667 match(Set dst (RShiftL src1 src2)); | |
| 7668 | |
| 7669 size(4); | |
| 7670 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7671 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7672 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7673 ins_pipe(ialu_reg_reg); | |
| 7674 %} | |
| 7675 | |
| 7676 // Register Shift Left Immediate | |
| 7677 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7678 match(Set dst (RShiftL src1 src2)); | |
| 7679 | |
| 7680 size(4); | |
| 7681 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7682 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7683 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7684 ins_pipe(ialu_reg_imm); | |
| 7685 %} | |
| 7686 | |
| 7687 // Register Shift Right | |
| 7688 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7689 match(Set dst (URShiftI src1 src2)); | |
| 7690 | |
| 7691 size(4); | |
| 7692 format %{ "SRL $src1,$src2,$dst" %} | |
| 7693 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7694 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7695 ins_pipe(ialu_reg_reg); | |
| 7696 %} | |
| 7697 | |
| 7698 // Register Shift Right Immediate | |
| 7699 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7700 match(Set dst (URShiftI src1 src2)); | |
| 7701 | |
| 7702 size(4); | |
| 7703 format %{ "SRL $src1,$src2,$dst" %} | |
| 7704 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7705 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7706 ins_pipe(ialu_reg_imm); | |
| 7707 %} | |
| 7708 | |
| 7709 // Register Shift Right | |
| 7710 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7711 match(Set dst (URShiftL src1 src2)); | |
| 7712 | |
| 7713 size(4); | |
| 7714 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7715 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7716 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7717 ins_pipe(ialu_reg_reg); | |
| 7718 %} | |
| 7719 | |
| 7720 // Register Shift Right Immediate | |
| 7721 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7722 match(Set dst (URShiftL src1 src2)); | |
| 7723 | |
| 7724 size(4); | |
| 7725 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7726 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7727 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7728 ins_pipe(ialu_reg_imm); | |
| 7729 %} | |
| 7730 | |
| 7731 // Register Shift Right Immediate with a CastP2X | |
| 7732 #ifdef _LP64 | |
| 7733 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7734 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7735 size(4); | |
| 7736 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7737 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7738 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7739 ins_pipe(ialu_reg_imm); | |
| 7740 %} | |
| 7741 #else | |
| 7742 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7743 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7744 size(4); | |
| 7745 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7746 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7747 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7748 ins_pipe(ialu_reg_imm); | |
| 7749 %} | |
| 7750 #endif | |
| 7751 | |
| 7752 | |
| 7753 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7754 | |
| 7755 // Add float single precision | |
| 7756 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7757 match(Set dst (AddF src1 src2)); | |
| 7758 | |
| 7759 size(4); | |
| 7760 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7761 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7762 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7763 ins_pipe(faddF_reg_reg); | |
| 7764 %} | |
| 7765 | |
| 7766 // Add float double precision | |
| 7767 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7768 match(Set dst (AddD src1 src2)); | |
| 7769 | |
| 7770 size(4); | |
| 7771 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7773 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7774 ins_pipe(faddD_reg_reg); | |
| 7775 %} | |
| 7776 | |
| 7777 // Sub float single precision | |
| 7778 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7779 match(Set dst (SubF src1 src2)); | |
| 7780 | |
| 7781 size(4); | |
| 7782 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7783 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7784 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7785 ins_pipe(faddF_reg_reg); | |
| 7786 %} | |
| 7787 | |
| 7788 // Sub float double precision | |
| 7789 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7790 match(Set dst (SubD src1 src2)); | |
| 7791 | |
| 7792 size(4); | |
| 7793 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7794 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7795 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7796 ins_pipe(faddD_reg_reg); | |
| 7797 %} | |
| 7798 | |
| 7799 // Mul float single precision | |
| 7800 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7801 match(Set dst (MulF src1 src2)); | |
| 7802 | |
| 7803 size(4); | |
| 7804 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7805 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7806 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7807 ins_pipe(fmulF_reg_reg); | |
| 7808 %} | |
| 7809 | |
| 7810 // Mul float double precision | |
| 7811 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7812 match(Set dst (MulD src1 src2)); | |
| 7813 | |
| 7814 size(4); | |
| 7815 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7816 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7817 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7818 ins_pipe(fmulD_reg_reg); | |
| 7819 %} | |
| 7820 | |
| 7821 // Div float single precision | |
| 7822 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7823 match(Set dst (DivF src1 src2)); | |
| 7824 | |
| 7825 size(4); | |
| 7826 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7827 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7828 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7829 ins_pipe(fdivF_reg_reg); | |
| 7830 %} | |
| 7831 | |
| 7832 // Div float double precision | |
| 7833 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7834 match(Set dst (DivD src1 src2)); | |
| 7835 | |
| 7836 size(4); | |
| 7837 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7838 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7839 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7840 ins_pipe(fdivD_reg_reg); | |
| 7841 %} | |
| 7842 | |
| 7843 // Absolute float double precision | |
| 7844 instruct absD_reg(regD dst, regD src) %{ | |
| 7845 match(Set dst (AbsD src)); | |
| 7846 | |
| 7847 format %{ "FABSd $src,$dst" %} | |
| 7848 ins_encode(fabsd(dst, src)); | |
| 7849 ins_pipe(faddD_reg); | |
| 7850 %} | |
| 7851 | |
| 7852 // Absolute float single precision | |
| 7853 instruct absF_reg(regF dst, regF src) %{ | |
| 7854 match(Set dst (AbsF src)); | |
| 7855 | |
| 7856 format %{ "FABSs $src,$dst" %} | |
| 7857 ins_encode(fabss(dst, src)); | |
| 7858 ins_pipe(faddF_reg); | |
| 7859 %} | |
| 7860 | |
| 7861 instruct negF_reg(regF dst, regF src) %{ | |
| 7862 match(Set dst (NegF src)); | |
| 7863 | |
| 7864 size(4); | |
| 7865 format %{ "FNEGs $src,$dst" %} | |
| 7866 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7867 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7868 ins_pipe(faddF_reg); | |
| 7869 %} | |
| 7870 | |
| 7871 instruct negD_reg(regD dst, regD src) %{ | |
| 7872 match(Set dst (NegD src)); | |
| 7873 | |
| 7874 format %{ "FNEGd $src,$dst" %} | |
| 7875 ins_encode(fnegd(dst, src)); | |
| 7876 ins_pipe(faddD_reg); | |
| 7877 %} | |
| 7878 | |
| 7879 // Sqrt float double precision | |
| 7880 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7881 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7882 | |
| 7883 size(4); | |
| 7884 format %{ "FSQRTS $src,$dst" %} | |
| 7885 ins_encode(fsqrts(dst, src)); | |
| 7886 ins_pipe(fdivF_reg_reg); | |
| 7887 %} | |
| 7888 | |
| 7889 // Sqrt float double precision | |
| 7890 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7891 match(Set dst (SqrtD src)); | |
| 7892 | |
| 7893 size(4); | |
| 7894 format %{ "FSQRTD $src,$dst" %} | |
| 7895 ins_encode(fsqrtd(dst, src)); | |
| 7896 ins_pipe(fdivD_reg_reg); | |
| 7897 %} | |
| 7898 | |
| 7899 //----------Logical Instructions----------------------------------------------- | |
| 7900 // And Instructions | |
| 7901 // Register And | |
| 7902 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7903 match(Set dst (AndI src1 src2)); | |
| 7904 | |
| 7905 size(4); | |
| 7906 format %{ "AND $src1,$src2,$dst" %} | |
| 7907 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7908 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7909 ins_pipe(ialu_reg_reg); | |
| 7910 %} | |
| 7911 | |
| 7912 // Immediate And | |
| 7913 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7914 match(Set dst (AndI src1 src2)); | |
| 7915 | |
| 7916 size(4); | |
| 7917 format %{ "AND $src1,$src2,$dst" %} | |
| 7918 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7919 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7920 ins_pipe(ialu_reg_imm); | |
| 7921 %} | |
| 7922 | |
| 7923 // Register And Long | |
| 7924 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7925 match(Set dst (AndL src1 src2)); | |
| 7926 | |
| 7927 ins_cost(DEFAULT_COST); | |
| 7928 size(4); | |
| 7929 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7930 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7931 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7932 ins_pipe(ialu_reg_reg); | |
| 7933 %} | |
| 7934 | |
| 7935 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7936 match(Set dst (AndL src1 con)); | |
| 7937 | |
| 7938 ins_cost(DEFAULT_COST); | |
| 7939 size(4); | |
| 7940 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7941 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7942 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7943 ins_pipe(ialu_reg_imm); | |
| 7944 %} | |
| 7945 | |
| 7946 // Or Instructions | |
| 7947 // Register Or | |
| 7948 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7949 match(Set dst (OrI src1 src2)); | |
| 7950 | |
| 7951 size(4); | |
| 7952 format %{ "OR $src1,$src2,$dst" %} | |
| 7953 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7954 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7955 ins_pipe(ialu_reg_reg); | |
| 7956 %} | |
| 7957 | |
| 7958 // Immediate Or | |
| 7959 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7960 match(Set dst (OrI src1 src2)); | |
| 7961 | |
| 7962 size(4); | |
| 7963 format %{ "OR $src1,$src2,$dst" %} | |
| 7964 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7965 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7966 ins_pipe(ialu_reg_imm); | |
| 7967 %} | |
| 7968 | |
| 7969 // Register Or Long | |
| 7970 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7971 match(Set dst (OrL src1 src2)); | |
| 7972 | |
| 7973 ins_cost(DEFAULT_COST); | |
| 7974 size(4); | |
| 7975 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 7976 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7977 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7978 ins_pipe(ialu_reg_reg); | |
| 7979 %} | |
| 7980 | |
| 7981 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7982 match(Set dst (OrL src1 con)); | |
| 7983 ins_cost(DEFAULT_COST*2); | |
| 7984 | |
| 7985 ins_cost(DEFAULT_COST); | |
| 7986 size(4); | |
| 7987 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 7988 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7989 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7990 ins_pipe(ialu_reg_imm); | |
| 7991 %} | |
| 7992 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7993 #ifndef _LP64 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7994 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7995 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7996 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7997 match(Set dst (OrI src1 (CastP2X src2))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7998 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7999 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8000 format %{ "OR $src1,$src2,$dst" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8001 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8002 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8003 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8004 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8005 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8006 #else |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8007 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8008 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8009 match(Set dst (OrL src1 (CastP2X src2))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8010 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8011 ins_cost(DEFAULT_COST); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8012 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8013 format %{ "OR $src1,$src2,$dst\t! long" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8014 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8015 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8016 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8017 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8018 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8019 #endif |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8020 |
| 0 | 8021 // Xor Instructions |
| 8022 // Register Xor | |
| 8023 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8024 match(Set dst (XorI src1 src2)); | |
| 8025 | |
| 8026 size(4); | |
| 8027 format %{ "XOR $src1,$src2,$dst" %} | |
| 8028 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8030 ins_pipe(ialu_reg_reg); | |
| 8031 %} | |
| 8032 | |
| 8033 // Immediate Xor | |
| 8034 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8035 match(Set dst (XorI src1 src2)); | |
| 8036 | |
| 8037 size(4); | |
| 8038 format %{ "XOR $src1,$src2,$dst" %} | |
| 8039 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8040 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8041 ins_pipe(ialu_reg_imm); | |
| 8042 %} | |
| 8043 | |
| 8044 // Register Xor Long | |
| 8045 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8046 match(Set dst (XorL src1 src2)); | |
| 8047 | |
| 8048 ins_cost(DEFAULT_COST); | |
| 8049 size(4); | |
| 8050 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8051 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8052 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8053 ins_pipe(ialu_reg_reg); | |
| 8054 %} | |
| 8055 | |
| 8056 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8057 match(Set dst (XorL src1 con)); | |
| 8058 | |
| 8059 ins_cost(DEFAULT_COST); | |
| 8060 size(4); | |
| 8061 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8062 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8063 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8064 ins_pipe(ialu_reg_imm); | |
| 8065 %} | |
| 8066 | |
| 8067 //----------Convert to Boolean------------------------------------------------- | |
| 8068 // Nice hack for 32-bit tests but doesn't work for | |
| 8069 // 64-bit pointers. | |
| 8070 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8071 match(Set dst (Conv2B src)); | |
| 8072 effect( KILL ccr ); | |
| 8073 ins_cost(DEFAULT_COST*2); | |
| 8074 format %{ "CMP R_G0,$src\n\t" | |
| 8075 "ADDX R_G0,0,$dst" %} | |
| 8076 ins_encode( enc_to_bool( src, dst ) ); | |
| 8077 ins_pipe(ialu_reg_ialu); | |
| 8078 %} | |
| 8079 | |
| 8080 #ifndef _LP64 | |
| 8081 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8082 match(Set dst (Conv2B src)); | |
| 8083 effect( KILL ccr ); | |
| 8084 ins_cost(DEFAULT_COST*2); | |
| 8085 format %{ "CMP R_G0,$src\n\t" | |
| 8086 "ADDX R_G0,0,$dst" %} | |
| 8087 ins_encode( enc_to_bool( src, dst ) ); | |
| 8088 ins_pipe(ialu_reg_ialu); | |
| 8089 %} | |
| 8090 #else | |
| 8091 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8092 match(Set dst (Conv2B src)); | |
| 8093 ins_cost(DEFAULT_COST*2); | |
| 8094 format %{ "MOV $src,$dst\n\t" | |
| 8095 "MOVRNZ $src,1,$dst" %} | |
| 8096 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8097 ins_pipe(ialu_clr_and_mover); | |
| 8098 %} | |
| 8099 #endif | |
| 8100 | |
|
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8101 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8102 match(Set dst (CmpLTMask src zero)); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8103 effect(KILL ccr); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8104 size(4); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8105 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8106 ins_encode %{ |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8107 __ sra($src$$Register, 31, $dst$$Register); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8108 %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8109 ins_pipe(ialu_reg_imm); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8110 %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8111 |
| 0 | 8112 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
| 8113 match(Set dst (CmpLTMask p q)); | |
| 8114 effect( KILL ccr ); | |
| 8115 ins_cost(DEFAULT_COST*4); | |
| 8116 format %{ "CMP $p,$q\n\t" | |
| 8117 "MOV #0,$dst\n\t" | |
| 8118 "BLT,a .+8\n\t" | |
| 8119 "MOV #-1,$dst" %} | |
| 8120 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8121 ins_pipe(ialu_reg_reg_ialu); | |
| 8122 %} | |
| 8123 | |
| 8124 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8125 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8126 effect(KILL ccr, TEMP tmp); | |
| 8127 ins_cost(DEFAULT_COST*3); | |
| 8128 | |
| 8129 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8130 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
|
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8131 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
| 0 | 8132 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); |
| 8133 ins_pipe( cadd_cmpltmask ); | |
| 8134 %} | |
| 8135 | |
| 3804 | 8136 |
| 8137 //----------------------------------------------------------------- | |
| 8138 // Direct raw moves between float and general registers using VIS3. | |
| 8139 | |
| 8140 // ins_pipe(faddF_reg); | |
| 8141 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
| 8142 predicate(UseVIS >= 3); | |
| 8143 match(Set dst (MoveF2I src)); | |
| 8144 | |
| 8145 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
| 8146 ins_encode %{ | |
| 8147 __ movstouw($src$$FloatRegister, $dst$$Register); | |
| 8148 %} | |
| 8149 ins_pipe(ialu_reg_reg); | |
| 8150 %} | |
| 8151 | |
| 8152 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
| 8153 predicate(UseVIS >= 3); | |
| 8154 match(Set dst (MoveI2F src)); | |
| 8155 | |
| 8156 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
| 8157 ins_encode %{ | |
| 8158 __ movwtos($src$$Register, $dst$$FloatRegister); | |
| 8159 %} | |
| 0 | 8160 ins_pipe(ialu_reg_reg); |
| 8161 %} | |
| 8162 | |
| 3804 | 8163 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
| 8164 predicate(UseVIS >= 3); | |
| 8165 match(Set dst (MoveD2L src)); | |
| 8166 | |
| 8167 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
| 8168 ins_encode %{ | |
| 8169 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
| 8170 %} | |
| 0 | 8171 ins_pipe(ialu_reg_reg); |
| 8172 %} | |
| 8173 | |
| 3804 | 8174 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
| 8175 predicate(UseVIS >= 3); | |
| 8176 match(Set dst (MoveL2D src)); | |
| 8177 | |
| 8178 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
| 8179 ins_encode %{ | |
| 8180 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
| 8181 %} | |
| 0 | 8182 ins_pipe(ialu_reg_reg); |
| 8183 %} | |
| 8184 | |
| 3804 | 8185 |
| 8186 // Raw moves between float and general registers using stack. | |
| 8187 | |
| 0 | 8188 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
| 8189 match(Set dst (MoveF2I src)); | |
| 8190 effect(DEF dst, USE src); | |
| 8191 ins_cost(MEMORY_REF_COST); | |
| 8192 | |
| 8193 size(4); | |
| 8194 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8195 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8196 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8197 ins_pipe(iload_mem); |
| 8198 %} | |
| 8199 | |
| 8200 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8201 match(Set dst (MoveI2F src)); | |
| 8202 effect(DEF dst, USE src); | |
| 8203 ins_cost(MEMORY_REF_COST); | |
| 8204 | |
| 8205 size(4); | |
| 8206 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8207 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8208 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8209 ins_pipe(floadF_stk); |
| 8210 %} | |
| 8211 | |
| 8212 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8213 match(Set dst (MoveD2L src)); | |
| 8214 effect(DEF dst, USE src); | |
| 8215 ins_cost(MEMORY_REF_COST); | |
| 8216 | |
| 8217 size(4); | |
| 8218 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8219 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8220 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8221 ins_pipe(iload_mem); |
| 8222 %} | |
| 8223 | |
| 8224 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8225 match(Set dst (MoveL2D src)); | |
| 8226 effect(DEF dst, USE src); | |
| 8227 ins_cost(MEMORY_REF_COST); | |
| 8228 | |
| 8229 size(4); | |
| 8230 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8231 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8232 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8233 ins_pipe(floadD_stk); |
| 8234 %} | |
| 8235 | |
| 8236 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8237 match(Set dst (MoveF2I src)); | |
| 8238 effect(DEF dst, USE src); | |
| 8239 ins_cost(MEMORY_REF_COST); | |
| 8240 | |
| 8241 size(4); | |
| 3804 | 8242 format %{ "STF $src,$dst\t! MoveF2I" %} |
| 0 | 8243 opcode(Assembler::stf_op3); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8244 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8245 ins_pipe(fstoreF_stk_reg); |
| 8246 %} | |
| 8247 | |
| 8248 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8249 match(Set dst (MoveI2F src)); | |
| 8250 effect(DEF dst, USE src); | |
| 8251 ins_cost(MEMORY_REF_COST); | |
| 8252 | |
| 8253 size(4); | |
| 3804 | 8254 format %{ "STW $src,$dst\t! MoveI2F" %} |
| 0 | 8255 opcode(Assembler::stw_op3); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8256 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8257 ins_pipe(istore_mem_reg); |
| 8258 %} | |
| 8259 | |
| 8260 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8261 match(Set dst (MoveD2L src)); | |
| 8262 effect(DEF dst, USE src); | |
| 8263 ins_cost(MEMORY_REF_COST); | |
| 8264 | |
| 8265 size(4); | |
| 3804 | 8266 format %{ "STDF $src,$dst\t! MoveD2L" %} |
| 0 | 8267 opcode(Assembler::stdf_op3); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8268 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8269 ins_pipe(fstoreD_stk_reg); |
| 8270 %} | |
| 8271 | |
| 8272 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8273 match(Set dst (MoveL2D src)); | |
| 8274 effect(DEF dst, USE src); | |
| 8275 ins_cost(MEMORY_REF_COST); | |
| 8276 | |
| 8277 size(4); | |
| 3804 | 8278 format %{ "STX $src,$dst\t! MoveL2D" %} |
| 0 | 8279 opcode(Assembler::stx_op3); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8280 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8281 ins_pipe(istore_mem_reg); |
| 8282 %} | |
| 8283 | |
| 8284 | |
| 3804 | 8285 //----------Arithmetic Conversion Instructions--------------------------------- |
| 8286 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8287 | |
| 8288 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8289 match(Set dst (ConvD2F src)); | |
| 8290 size(4); | |
| 8291 format %{ "FDTOS $src,$dst" %} | |
| 8292 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8293 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8294 ins_pipe(fcvtD2F); | |
| 8295 %} | |
| 8296 | |
| 8297 | |
| 8298 // Convert a double to an int in a float register. | |
| 8299 // If the double is a NAN, stuff a zero in instead. | |
| 8300 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8301 effect(DEF dst, USE src, KILL fcc0); | |
| 8302 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8303 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8304 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8305 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8306 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8307 "skip:" %} | |
| 8308 ins_encode(form_d2i_helper(src,dst)); | |
| 8309 ins_pipe(fcvtD2I); | |
| 8310 %} | |
| 8311 | |
| 8312 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
| 8313 match(Set dst (ConvD2I src)); | |
| 8314 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8315 expand %{ | |
| 8316 regF tmp; | |
| 8317 convD2I_helper(tmp, src); | |
| 8318 regF_to_stkI(dst, tmp); | |
| 8319 %} | |
| 8320 %} | |
| 8321 | |
| 8322 instruct convD2I_reg(iRegI dst, regD src) %{ | |
| 8323 predicate(UseVIS >= 3); | |
| 8324 match(Set dst (ConvD2I src)); | |
| 8325 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8326 expand %{ | |
| 8327 regF tmp; | |
| 8328 convD2I_helper(tmp, src); | |
| 8329 MoveF2I_reg_reg(dst, tmp); | |
| 8330 %} | |
| 8331 %} | |
| 8332 | |
| 8333 | |
| 8334 // Convert a double to a long in a double register. | |
| 8335 // If the double is a NAN, stuff a zero in instead. | |
| 8336 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8337 effect(DEF dst, USE src, KILL fcc0); | |
| 8338 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8339 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8340 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8341 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8342 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8343 "skip:" %} | |
| 8344 ins_encode(form_d2l_helper(src,dst)); | |
| 8345 ins_pipe(fcvtD2L); | |
| 8346 %} | |
| 8347 | |
| 8348 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
| 8349 match(Set dst (ConvD2L src)); | |
| 8350 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8351 expand %{ | |
| 8352 regD tmp; | |
| 8353 convD2L_helper(tmp, src); | |
| 8354 regD_to_stkL(dst, tmp); | |
| 8355 %} | |
| 8356 %} | |
| 8357 | |
| 8358 instruct convD2L_reg(iRegL dst, regD src) %{ | |
| 8359 predicate(UseVIS >= 3); | |
| 8360 match(Set dst (ConvD2L src)); | |
| 8361 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8362 expand %{ | |
| 8363 regD tmp; | |
| 8364 convD2L_helper(tmp, src); | |
| 8365 MoveD2L_reg_reg(dst, tmp); | |
| 8366 %} | |
| 8367 %} | |
| 8368 | |
| 8369 | |
| 8370 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8371 match(Set dst (ConvF2D src)); | |
| 8372 format %{ "FSTOD $src,$dst" %} | |
| 8373 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8374 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8375 ins_pipe(fcvtF2D); | |
| 8376 %} | |
| 8377 | |
| 8378 | |
| 8379 // Convert a float to an int in a float register. | |
| 8380 // If the float is a NAN, stuff a zero in instead. | |
| 8381 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8382 effect(DEF dst, USE src, KILL fcc0); | |
| 8383 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8384 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8385 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8386 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8387 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8388 "skip:" %} | |
| 8389 ins_encode(form_f2i_helper(src,dst)); | |
| 8390 ins_pipe(fcvtF2I); | |
| 8391 %} | |
| 8392 | |
| 8393 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
| 8394 match(Set dst (ConvF2I src)); | |
| 8395 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8396 expand %{ | |
| 8397 regF tmp; | |
| 8398 convF2I_helper(tmp, src); | |
| 8399 regF_to_stkI(dst, tmp); | |
| 8400 %} | |
| 8401 %} | |
| 8402 | |
| 8403 instruct convF2I_reg(iRegI dst, regF src) %{ | |
| 8404 predicate(UseVIS >= 3); | |
| 8405 match(Set dst (ConvF2I src)); | |
| 8406 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8407 expand %{ | |
| 8408 regF tmp; | |
| 8409 convF2I_helper(tmp, src); | |
| 8410 MoveF2I_reg_reg(dst, tmp); | |
| 8411 %} | |
| 8412 %} | |
| 8413 | |
| 8414 | |
| 8415 // Convert a float to a long in a float register. | |
| 8416 // If the float is a NAN, stuff a zero in instead. | |
| 8417 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8418 effect(DEF dst, USE src, KILL fcc0); | |
| 8419 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8420 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8421 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8422 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8423 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8424 "skip:" %} | |
| 8425 ins_encode(form_f2l_helper(src,dst)); | |
| 8426 ins_pipe(fcvtF2L); | |
| 8427 %} | |
| 8428 | |
| 8429 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
| 8430 match(Set dst (ConvF2L src)); | |
| 8431 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8432 expand %{ | |
| 8433 regD tmp; | |
| 8434 convF2L_helper(tmp, src); | |
| 8435 regD_to_stkL(dst, tmp); | |
| 8436 %} | |
| 8437 %} | |
| 8438 | |
| 8439 instruct convF2L_reg(iRegL dst, regF src) %{ | |
| 8440 predicate(UseVIS >= 3); | |
| 8441 match(Set dst (ConvF2L src)); | |
| 8442 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8443 expand %{ | |
| 8444 regD tmp; | |
| 8445 convF2L_helper(tmp, src); | |
| 8446 MoveD2L_reg_reg(dst, tmp); | |
| 8447 %} | |
| 8448 %} | |
| 8449 | |
| 8450 | |
| 8451 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8452 effect(USE tmp, DEF dst); | |
| 8453 format %{ "FITOD $tmp,$dst" %} | |
| 8454 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8455 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8456 ins_pipe(fcvtI2D); | |
| 8457 %} | |
| 8458 | |
| 8459 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
| 8460 match(Set dst (ConvI2D src)); | |
| 8461 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8462 expand %{ | |
| 8463 regF tmp; | |
| 8464 stkI_to_regF(tmp, src); | |
| 8465 convI2D_helper(dst, tmp); | |
| 8466 %} | |
| 8467 %} | |
| 8468 | |
| 8469 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
| 8470 predicate(UseVIS >= 3); | |
| 8471 match(Set dst (ConvI2D src)); | |
| 8472 expand %{ | |
| 8473 regF tmp; | |
| 8474 MoveI2F_reg_reg(tmp, src); | |
| 8475 convI2D_helper(dst, tmp); | |
| 8476 %} | |
| 8477 %} | |
| 8478 | |
| 8479 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
| 8480 match(Set dst (ConvI2D (LoadI mem))); | |
| 8481 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8482 size(8); | |
| 8483 format %{ "LDF $mem,$dst\n\t" | |
| 8484 "FITOD $dst,$dst" %} | |
| 8485 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
| 8486 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8487 ins_pipe(floadF_mem); | |
| 8488 %} | |
| 8489 | |
| 8490 | |
| 8491 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8492 effect(DEF dst, USE tmp); | |
| 8493 format %{ "FITOS $tmp,$dst" %} | |
| 8494 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8495 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8496 ins_pipe(fcvtI2F); | |
| 8497 %} | |
| 8498 | |
| 8499 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
| 8500 match(Set dst (ConvI2F src)); | |
| 8501 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8502 expand %{ | |
| 8503 regF tmp; | |
| 8504 stkI_to_regF(tmp,src); | |
| 8505 convI2F_helper(dst, tmp); | |
| 8506 %} | |
| 8507 %} | |
| 8508 | |
| 8509 instruct convI2F_reg(regF dst, iRegI src) %{ | |
| 8510 predicate(UseVIS >= 3); | |
| 8511 match(Set dst (ConvI2F src)); | |
| 8512 ins_cost(DEFAULT_COST); | |
| 8513 expand %{ | |
| 8514 regF tmp; | |
| 8515 MoveI2F_reg_reg(tmp, src); | |
| 8516 convI2F_helper(dst, tmp); | |
| 8517 %} | |
| 8518 %} | |
| 8519 | |
| 8520 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8521 match(Set dst (ConvI2F (LoadI mem))); | |
| 8522 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8523 size(8); | |
| 8524 format %{ "LDF $mem,$dst\n\t" | |
| 8525 "FITOS $dst,$dst" %} | |
| 8526 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
| 8527 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8528 ins_pipe(floadF_mem); | |
| 8529 %} | |
| 8530 | |
| 8531 | |
| 8532 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8533 match(Set dst (ConvI2L src)); | |
| 8534 size(4); | |
| 8535 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8536 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8537 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8538 ins_pipe(ialu_reg_reg); | |
| 8539 %} | |
| 8540 | |
| 8541 // Zero-extend convert int to long | |
| 8542 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8543 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8544 size(4); | |
| 8545 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8546 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8547 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8548 ins_pipe(ialu_reg_reg); | |
| 8549 %} | |
| 8550 | |
| 8551 // Zero-extend long | |
| 8552 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8553 match(Set dst (AndL src mask) ); | |
| 8554 size(4); | |
| 8555 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8556 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8557 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8558 ins_pipe(ialu_reg_reg); | |
| 8559 %} | |
| 8560 | |
| 8561 | |
| 0 | 8562 //----------- |
| 8563 // Long to Double conversion using V8 opcodes. | |
| 8564 // Still useful because cheetah traps and becomes | |
| 8565 // amazingly slow for some common numbers. | |
| 8566 | |
| 8567 // Magic constant, 0x43300000 | |
| 8568 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8569 effect(DEF dst); | |
| 8570 size(4); | |
| 8571 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8572 ins_encode(SetHi22(0x43300000, dst)); | |
| 8573 ins_pipe(ialu_none); | |
| 8574 %} | |
| 8575 | |
| 8576 // Magic constant, 0x41f00000 | |
| 8577 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8578 effect(DEF dst); | |
| 8579 size(4); | |
| 8580 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8581 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8582 ins_pipe(ialu_none); | |
| 8583 %} | |
| 8584 | |
| 8585 // Construct a double from two float halves | |
| 8586 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8587 effect(DEF dst, USE src1, USE src2); | |
| 8588 size(8); | |
| 8589 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8590 "FMOVS $src2.lo,$dst.lo" %} | |
| 8591 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8592 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8593 ins_pipe(faddD_reg_reg); | |
| 8594 %} | |
| 8595 | |
| 8596 // Convert integer in high half of a double register (in the lower half of | |
| 8597 // the double register file) to double | |
| 8598 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8599 effect(DEF dst, USE src); | |
| 8600 size(4); | |
| 8601 format %{ "FITOD $src,$dst" %} | |
| 8602 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8603 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8604 ins_pipe(fcvtLHi2D); | |
| 8605 %} | |
| 8606 | |
| 8607 // Add float double precision | |
| 8608 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8609 effect(DEF dst, USE src1, USE src2); | |
| 8610 size(4); | |
| 8611 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8612 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8613 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8614 ins_pipe(faddD_reg_reg); | |
| 8615 %} | |
| 8616 | |
| 8617 // Sub float double precision | |
| 8618 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8619 effect(DEF dst, USE src1, USE src2); | |
| 8620 size(4); | |
| 8621 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8622 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8623 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8624 ins_pipe(faddD_reg_reg); | |
| 8625 %} | |
| 8626 | |
| 8627 // Mul float double precision | |
| 8628 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8629 effect(DEF dst, USE src1, USE src2); | |
| 8630 size(4); | |
| 8631 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8632 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8633 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8634 ins_pipe(fmulD_reg_reg); | |
| 8635 %} | |
| 8636 | |
| 8637 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8638 match(Set dst (ConvL2D src)); | |
| 8639 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8640 | |
| 8641 expand %{ | |
| 8642 regD_low tmpsrc; | |
| 8643 iRegI ix43300000; | |
| 8644 iRegI ix41f00000; | |
| 8645 stackSlotL lx43300000; | |
| 8646 stackSlotL lx41f00000; | |
| 8647 regD_low dx43300000; | |
| 8648 regD dx41f00000; | |
| 8649 regD tmp1; | |
| 8650 regD_low tmp2; | |
| 8651 regD tmp3; | |
| 8652 regD tmp4; | |
| 8653 | |
| 8654 stkL_to_regD(tmpsrc, src); | |
| 8655 | |
| 8656 loadConI_x43300000(ix43300000); | |
| 8657 loadConI_x41f00000(ix41f00000); | |
| 8658 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8659 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8660 stkL_to_regD(dx43300000, lx43300000); | |
| 8661 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8662 | |
| 8663 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8664 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8665 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8666 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8667 addD_regD_regD(dst, tmp3, tmp4); | |
| 8668 %} | |
| 8669 %} | |
| 8670 | |
| 8671 // Long to Double conversion using fast fxtof | |
| 8672 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8673 effect(DEF dst, USE tmp); | |
| 8674 size(4); | |
| 8675 format %{ "FXTOD $tmp,$dst" %} | |
| 8676 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8677 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8678 ins_pipe(fcvtL2D); | |
| 8679 %} | |
| 8680 | |
| 3804 | 8681 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
| 0 | 8682 predicate(VM_Version::has_fast_fxtof()); |
| 8683 match(Set dst (ConvL2D src)); | |
| 8684 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8685 expand %{ | |
| 8686 regD tmp; | |
| 8687 stkL_to_regD(tmp, src); | |
| 8688 convL2D_helper(dst, tmp); | |
| 8689 %} | |
| 8690 %} | |
| 8691 | |
| 3804 | 8692 instruct convL2D_reg(regD dst, iRegL src) %{ |
| 8693 predicate(UseVIS >= 3); | |
| 8694 match(Set dst (ConvL2D src)); | |
| 8695 expand %{ | |
| 8696 regD tmp; | |
| 8697 MoveL2D_reg_reg(tmp, src); | |
| 8698 convL2D_helper(dst, tmp); | |
| 8699 %} | |
| 8700 %} | |
| 0 | 8701 |
| 8702 // Long to Float conversion using fast fxtof | |
| 8703 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8704 effect(DEF dst, USE tmp); | |
| 8705 size(4); | |
| 8706 format %{ "FXTOS $tmp,$dst" %} | |
| 8707 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8708 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8709 ins_pipe(fcvtL2F); | |
| 8710 %} | |
| 8711 | |
| 3804 | 8712 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
| 0 | 8713 match(Set dst (ConvL2F src)); |
| 8714 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8715 expand %{ | |
| 8716 regD tmp; | |
| 8717 stkL_to_regD(tmp, src); | |
| 8718 convL2F_helper(dst, tmp); | |
| 8719 %} | |
| 8720 %} | |
| 3804 | 8721 |
| 8722 instruct convL2F_reg(regF dst, iRegL src) %{ | |
| 8723 predicate(UseVIS >= 3); | |
| 8724 match(Set dst (ConvL2F src)); | |
| 8725 ins_cost(DEFAULT_COST); | |
| 8726 expand %{ | |
| 8727 regD tmp; | |
| 8728 MoveL2D_reg_reg(tmp, src); | |
| 8729 convL2F_helper(dst, tmp); | |
| 8730 %} | |
| 8731 %} | |
| 8732 | |
| 0 | 8733 //----------- |
| 8734 | |
| 8735 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8736 match(Set dst (ConvL2I src)); | |
| 8737 #ifndef _LP64 | |
| 8738 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8739 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8740 ins_pipe(ialu_move_reg_I_to_L); | |
| 8741 #else | |
| 8742 size(4); | |
| 8743 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8744 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8745 ins_pipe(ialu_reg); | |
| 8746 #endif | |
| 8747 %} | |
| 8748 | |
| 8749 // Register Shift Right Immediate | |
| 8750 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8751 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8752 | |
| 8753 size(4); | |
| 8754 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8755 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8756 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8757 ins_pipe(ialu_reg_imm); | |
| 8758 %} | |
| 8759 | |
| 8760 //----------Control Flow Instructions------------------------------------------ | |
| 8761 // Compare Instructions | |
| 8762 // Compare Integers | |
| 8763 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8764 match(Set icc (CmpI op1 op2)); | |
| 8765 effect( DEF icc, USE op1, USE op2 ); | |
| 8766 | |
| 8767 size(4); | |
| 8768 format %{ "CMP $op1,$op2" %} | |
| 8769 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8770 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8771 ins_pipe(ialu_cconly_reg_reg); | |
| 8772 %} | |
| 8773 | |
| 8774 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8775 match(Set icc (CmpU op1 op2)); | |
| 8776 | |
| 8777 size(4); | |
| 8778 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8779 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8780 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8781 ins_pipe(ialu_cconly_reg_reg); | |
| 8782 %} | |
| 8783 | |
| 8784 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8785 match(Set icc (CmpI op1 op2)); | |
| 8786 effect( DEF icc, USE op1 ); | |
| 8787 | |
| 8788 size(4); | |
| 8789 format %{ "CMP $op1,$op2" %} | |
| 8790 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8791 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8792 ins_pipe(ialu_cconly_reg_imm); | |
| 8793 %} | |
| 8794 | |
| 8795 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8796 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8797 | |
| 8798 size(4); | |
| 8799 format %{ "BTST $op2,$op1" %} | |
| 8800 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8801 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8802 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8803 %} | |
| 8804 | |
| 8805 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8806 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8807 | |
| 8808 size(4); | |
| 8809 format %{ "BTST $op2,$op1" %} | |
| 8810 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8811 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8812 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8813 %} | |
| 8814 | |
| 8815 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8816 match(Set xcc (CmpL op1 op2)); | |
| 8817 effect( DEF xcc, USE op1, USE op2 ); | |
| 8818 | |
| 8819 size(4); | |
| 8820 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8821 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8822 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8823 ins_pipe(ialu_cconly_reg_reg); | |
| 8824 %} | |
| 8825 | |
| 8826 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8827 match(Set xcc (CmpL op1 con)); | |
| 8828 effect( DEF xcc, USE op1, USE con ); | |
| 8829 | |
| 8830 size(4); | |
| 8831 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8832 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8833 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8834 ins_pipe(ialu_cconly_reg_reg); | |
| 8835 %} | |
| 8836 | |
| 8837 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8838 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8839 effect( DEF xcc, USE op1, USE op2 ); | |
| 8840 | |
| 8841 size(4); | |
| 8842 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8843 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8844 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8845 ins_pipe(ialu_cconly_reg_reg); | |
| 8846 %} | |
| 8847 | |
| 8848 // useful for checking the alignment of a pointer: | |
| 8849 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8850 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8851 effect( DEF xcc, USE op1, USE con ); | |
| 8852 | |
| 8853 size(4); | |
| 8854 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8855 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8856 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8857 ins_pipe(ialu_cconly_reg_reg); | |
| 8858 %} | |
| 8859 | |
| 8860 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8861 match(Set icc (CmpU op1 op2)); | |
| 8862 | |
| 8863 size(4); | |
| 8864 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8865 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8866 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8867 ins_pipe(ialu_cconly_reg_imm); | |
| 8868 %} | |
| 8869 | |
| 8870 // Compare Pointers | |
| 8871 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8872 match(Set pcc (CmpP op1 op2)); | |
| 8873 | |
| 8874 size(4); | |
| 8875 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8876 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8877 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8878 ins_pipe(ialu_cconly_reg_reg); | |
| 8879 %} | |
| 8880 | |
| 8881 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8882 match(Set pcc (CmpP op1 op2)); | |
| 8883 | |
| 8884 size(4); | |
| 8885 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8886 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8887 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8888 ins_pipe(ialu_cconly_reg_imm); | |
| 8889 %} | |
| 8890 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8891 // Compare Narrow oops |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8892 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8893 match(Set icc (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8894 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8895 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8896 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8897 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8898 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8899 ins_pipe(ialu_cconly_reg_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8900 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8901 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8902 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8903 match(Set icc (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8904 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8905 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8906 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8907 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8908 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8909 ins_pipe(ialu_cconly_reg_imm); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8910 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8911 |
| 0 | 8912 //----------Max and Min-------------------------------------------------------- |
| 8913 // Min Instructions | |
| 8914 // Conditional move for min | |
| 8915 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8916 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8917 | |
| 8918 size(4); | |
| 8919 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 8920 opcode(Assembler::less); | |
| 8921 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8922 ins_pipe(ialu_reg_flags); | |
| 8923 %} | |
| 8924 | |
| 8925 // Min Register with Register. | |
| 8926 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 8927 match(Set op2 (MinI op1 op2)); | |
| 8928 ins_cost(DEFAULT_COST*2); | |
| 8929 expand %{ | |
| 8930 flagsReg icc; | |
| 8931 compI_iReg(icc,op1,op2); | |
| 8932 cmovI_reg_lt(op2,op1,icc); | |
| 8933 %} | |
| 8934 %} | |
| 8935 | |
| 8936 // Max Instructions | |
| 8937 // Conditional move for max | |
| 8938 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8939 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8940 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 8941 opcode(Assembler::greater); | |
| 8942 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8943 ins_pipe(ialu_reg_flags); | |
| 8944 %} | |
| 8945 | |
| 8946 // Max Register with Register | |
| 8947 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 8948 match(Set op2 (MaxI op1 op2)); | |
| 8949 ins_cost(DEFAULT_COST*2); | |
| 8950 expand %{ | |
| 8951 flagsReg icc; | |
| 8952 compI_iReg(icc,op1,op2); | |
| 8953 cmovI_reg_gt(op2,op1,icc); | |
| 8954 %} | |
| 8955 %} | |
| 8956 | |
| 8957 | |
| 8958 //----------Float Compares---------------------------------------------------- | |
| 8959 // Compare floating, generate condition code | |
| 8960 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 8961 match(Set fcc (CmpF src1 src2)); | |
| 8962 | |
| 8963 size(4); | |
| 8964 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 8965 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 8966 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 8967 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 8968 %} | |
| 8969 | |
| 8970 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 8971 match(Set fcc (CmpD src1 src2)); | |
| 8972 | |
| 8973 size(4); | |
| 8974 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 8975 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 8976 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 8977 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 8978 %} | |
| 8979 | |
| 8980 | |
| 8981 // Compare floating, generate -1,0,1 | |
| 8982 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 8983 match(Set dst (CmpF3 src1 src2)); | |
| 8984 effect(KILL fcc0); | |
| 8985 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8986 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 8987 // Primary = float | |
| 8988 opcode( true ); | |
| 8989 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8990 ins_pipe( floating_cmp ); | |
| 8991 %} | |
| 8992 | |
| 8993 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 8994 match(Set dst (CmpD3 src1 src2)); | |
| 8995 effect(KILL fcc0); | |
| 8996 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8997 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 8998 // Primary = double (not float) | |
| 8999 opcode( false ); | |
| 9000 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9001 ins_pipe( floating_cmp ); | |
| 9002 %} | |
| 9003 | |
| 9004 //----------Branches--------------------------------------------------------- | |
| 9005 // Jump | |
| 9006 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9007 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9008 match(Jump switch_val); | |
|
4776
5da7201222d5
7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM
kvn
parents:
4763
diff
changeset
|
9009 effect(TEMP table); |
| 0 | 9010 |
| 9011 ins_cost(350); | |
| 9012 | |
| 2008 | 9013 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9014 "LD [O7 + $switch_val], O7\n\t" | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9015 "JUMP O7" %} |
| 2008 | 9016 ins_encode %{ |
| 9017 // Calculate table address into a register. | |
| 9018 Register table_reg; | |
| 9019 Register label_reg = O7; | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9020 // If we are calculating the size of this instruction don't trust |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9021 // zero offsets because they might change when |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9022 // MachConstantBaseNode decides to optimize the constant table |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9023 // base. |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9024 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
| 2008 | 9025 table_reg = $constanttablebase; |
| 9026 } else { | |
| 9027 table_reg = O7; | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
9028 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
9029 __ add($constanttablebase, con_offset, table_reg); |
| 2008 | 9030 } |
| 9031 | |
| 9032 // Jump to base address + switch value | |
| 9033 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9034 __ jmp(label_reg, G0); | |
| 9035 __ delayed()->nop(); | |
| 9036 %} | |
| 0 | 9037 ins_pipe(ialu_reg_reg); |
| 9038 %} | |
| 9039 | |
| 9040 // Direct Branch. Use V8 version with longer range. | |
| 9041 instruct branch(label labl) %{ | |
| 9042 match(Goto); | |
| 9043 effect(USE labl); | |
| 9044 | |
| 9045 size(8); | |
| 9046 ins_cost(BRANCH_COST); | |
| 9047 format %{ "BA $labl" %} | |
| 3839 | 9048 ins_encode %{ |
| 9049 Label* L = $labl$$label; | |
| 9050 __ ba(*L); | |
| 9051 __ delayed()->nop(); | |
| 9052 %} | |
| 0 | 9053 ins_pipe(br); |
| 9054 %} | |
| 9055 | |
| 3851 | 9056 // Direct Branch, short with no delay slot |
| 9057 instruct branch_short(label labl) %{ | |
| 9058 match(Goto); | |
| 9059 predicate(UseCBCond); | |
| 9060 effect(USE labl); | |
| 9061 | |
| 9062 size(4); | |
| 9063 ins_cost(BRANCH_COST); | |
| 9064 format %{ "BA $labl\t! short branch" %} | |
| 9065 ins_encode %{ | |
| 9066 Label* L = $labl$$label; | |
| 9067 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9068 __ ba_short(*L); | |
| 9069 %} | |
| 9070 ins_short_branch(1); | |
| 9071 ins_avoid_back_to_back(1); | |
| 9072 ins_pipe(cbcond_reg_imm); | |
| 9073 %} | |
| 9074 | |
| 0 | 9075 // Conditional Direct Branch |
| 9076 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9077 match(If cmp icc); | |
| 9078 effect(USE labl); | |
| 9079 | |
| 9080 size(8); | |
| 9081 ins_cost(BRANCH_COST); | |
| 9082 format %{ "BP$cmp $icc,$labl" %} | |
| 9083 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9084 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9085 ins_pipe(br_cc); | |
| 9086 %} | |
| 9087 | |
| 9088 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9089 match(If cmp icc); | |
| 9090 effect(USE labl); | |
| 9091 | |
| 3851 | 9092 ins_cost(BRANCH_COST); |
| 0 | 9093 format %{ "BP$cmp $icc,$labl" %} |
| 9094 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9095 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9096 ins_pipe(br_cc); | |
| 9097 %} | |
| 9098 | |
| 9099 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9100 match(If cmp pcc); | |
| 9101 effect(USE labl); | |
| 9102 | |
| 9103 size(8); | |
| 9104 ins_cost(BRANCH_COST); | |
| 9105 format %{ "BP$cmp $pcc,$labl" %} | |
| 3839 | 9106 ins_encode %{ |
| 9107 Label* L = $labl$$label; | |
| 9108 Assembler::Predict predict_taken = | |
| 9109 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9110 | |
| 9111 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9112 __ delayed()->nop(); | |
| 9113 %} | |
| 0 | 9114 ins_pipe(br_cc); |
| 9115 %} | |
| 9116 | |
| 9117 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9118 match(If cmp fcc); | |
| 9119 effect(USE labl); | |
| 9120 | |
| 9121 size(8); | |
| 9122 ins_cost(BRANCH_COST); | |
| 9123 format %{ "FBP$cmp $fcc,$labl" %} | |
| 3839 | 9124 ins_encode %{ |
| 9125 Label* L = $labl$$label; | |
| 9126 Assembler::Predict predict_taken = | |
| 9127 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9128 | |
| 9129 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
| 9130 __ delayed()->nop(); | |
| 9131 %} | |
| 0 | 9132 ins_pipe(br_fcc); |
| 9133 %} | |
| 9134 | |
| 9135 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9136 match(CountedLoopEnd cmp icc); | |
| 9137 effect(USE labl); | |
| 9138 | |
| 9139 size(8); | |
| 9140 ins_cost(BRANCH_COST); | |
| 9141 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9142 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9143 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9144 ins_pipe(br_cc); | |
| 9145 %} | |
| 9146 | |
| 9147 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9148 match(CountedLoopEnd cmp icc); | |
| 9149 effect(USE labl); | |
| 9150 | |
| 9151 size(8); | |
| 9152 ins_cost(BRANCH_COST); | |
| 9153 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9154 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9155 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9156 ins_pipe(br_cc); | |
| 9157 %} | |
| 9158 | |
| 3851 | 9159 // Compare and branch instructions |
| 9160 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9161 match(If cmp (CmpI op1 op2)); | |
| 9162 effect(USE labl, KILL icc); | |
| 9163 | |
| 9164 size(12); | |
| 9165 ins_cost(BRANCH_COST); | |
| 9166 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9167 "BP$cmp $labl" %} | |
| 9168 ins_encode %{ | |
| 9169 Label* L = $labl$$label; | |
| 9170 Assembler::Predict predict_taken = | |
| 9171 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9172 __ cmp($op1$$Register, $op2$$Register); | |
| 9173 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9174 __ delayed()->nop(); | |
| 9175 %} | |
| 9176 ins_pipe(cmp_br_reg_reg); | |
| 9177 %} | |
| 9178 | |
| 9179 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9180 match(If cmp (CmpI op1 op2)); | |
| 9181 effect(USE labl, KILL icc); | |
| 9182 | |
| 9183 size(12); | |
| 9184 ins_cost(BRANCH_COST); | |
| 9185 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9186 "BP$cmp $labl" %} | |
| 9187 ins_encode %{ | |
| 9188 Label* L = $labl$$label; | |
| 9189 Assembler::Predict predict_taken = | |
| 9190 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9191 __ cmp($op1$$Register, $op2$$constant); | |
| 9192 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9193 __ delayed()->nop(); | |
| 9194 %} | |
| 9195 ins_pipe(cmp_br_reg_imm); | |
| 9196 %} | |
| 9197 | |
| 9198 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9199 match(If cmp (CmpU op1 op2)); | |
| 9200 effect(USE labl, KILL icc); | |
| 9201 | |
| 9202 size(12); | |
| 9203 ins_cost(BRANCH_COST); | |
| 9204 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9205 "BP$cmp $labl" %} | |
| 9206 ins_encode %{ | |
| 9207 Label* L = $labl$$label; | |
| 9208 Assembler::Predict predict_taken = | |
| 9209 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9210 __ cmp($op1$$Register, $op2$$Register); | |
| 9211 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9212 __ delayed()->nop(); | |
| 9213 %} | |
| 9214 ins_pipe(cmp_br_reg_reg); | |
| 9215 %} | |
| 9216 | |
| 9217 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9218 match(If cmp (CmpU op1 op2)); | |
| 9219 effect(USE labl, KILL icc); | |
| 9220 | |
| 9221 size(12); | |
| 9222 ins_cost(BRANCH_COST); | |
| 9223 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9224 "BP$cmp $labl" %} | |
| 9225 ins_encode %{ | |
| 9226 Label* L = $labl$$label; | |
| 9227 Assembler::Predict predict_taken = | |
| 9228 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9229 __ cmp($op1$$Register, $op2$$constant); | |
| 9230 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9231 __ delayed()->nop(); | |
| 9232 %} | |
| 9233 ins_pipe(cmp_br_reg_imm); | |
| 9234 %} | |
| 9235 | |
| 9236 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9237 match(If cmp (CmpL op1 op2)); | |
| 9238 effect(USE labl, KILL xcc); | |
| 9239 | |
| 9240 size(12); | |
| 9241 ins_cost(BRANCH_COST); | |
| 9242 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9243 "BP$cmp $labl" %} | |
| 9244 ins_encode %{ | |
| 9245 Label* L = $labl$$label; | |
| 9246 Assembler::Predict predict_taken = | |
| 9247 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9248 __ cmp($op1$$Register, $op2$$Register); | |
| 9249 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9250 __ delayed()->nop(); | |
| 9251 %} | |
| 9252 ins_pipe(cmp_br_reg_reg); | |
| 9253 %} | |
| 9254 | |
| 9255 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9256 match(If cmp (CmpL op1 op2)); | |
| 9257 effect(USE labl, KILL xcc); | |
| 9258 | |
| 9259 size(12); | |
| 9260 ins_cost(BRANCH_COST); | |
| 9261 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9262 "BP$cmp $labl" %} | |
| 9263 ins_encode %{ | |
| 9264 Label* L = $labl$$label; | |
| 9265 Assembler::Predict predict_taken = | |
| 9266 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9267 __ cmp($op1$$Register, $op2$$constant); | |
| 9268 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9269 __ delayed()->nop(); | |
| 9270 %} | |
| 9271 ins_pipe(cmp_br_reg_imm); | |
| 9272 %} | |
| 9273 | |
| 9274 // Compare Pointers and branch | |
| 9275 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9276 match(If cmp (CmpP op1 op2)); | |
| 9277 effect(USE labl, KILL pcc); | |
| 9278 | |
| 9279 size(12); | |
| 9280 ins_cost(BRANCH_COST); | |
| 9281 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
| 9282 "B$cmp $labl" %} | |
| 9283 ins_encode %{ | |
| 9284 Label* L = $labl$$label; | |
| 9285 Assembler::Predict predict_taken = | |
| 9286 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9287 __ cmp($op1$$Register, $op2$$Register); | |
| 9288 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9289 __ delayed()->nop(); | |
| 9290 %} | |
| 9291 ins_pipe(cmp_br_reg_reg); | |
| 9292 %} | |
| 9293 | |
| 9294 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9295 match(If cmp (CmpP op1 null)); | |
| 9296 effect(USE labl, KILL pcc); | |
| 9297 | |
| 9298 size(12); | |
| 9299 ins_cost(BRANCH_COST); | |
| 9300 format %{ "CMP $op1,0\t! ptr\n\t" | |
| 9301 "B$cmp $labl" %} | |
| 9302 ins_encode %{ | |
| 9303 Label* L = $labl$$label; | |
| 9304 Assembler::Predict predict_taken = | |
| 9305 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9306 __ cmp($op1$$Register, G0); | |
| 9307 // bpr() is not used here since it has shorter distance. | |
| 9308 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9309 __ delayed()->nop(); | |
| 9310 %} | |
| 9311 ins_pipe(cmp_br_reg_reg); | |
| 9312 %} | |
| 9313 | |
| 9314 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9315 match(If cmp (CmpN op1 op2)); | |
| 9316 effect(USE labl, KILL icc); | |
| 9317 | |
| 9318 size(12); | |
| 9319 ins_cost(BRANCH_COST); | |
| 9320 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
| 9321 "BP$cmp $labl" %} | |
| 9322 ins_encode %{ | |
| 9323 Label* L = $labl$$label; | |
| 9324 Assembler::Predict predict_taken = | |
| 9325 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9326 __ cmp($op1$$Register, $op2$$Register); | |
| 9327 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9328 __ delayed()->nop(); | |
| 9329 %} | |
| 9330 ins_pipe(cmp_br_reg_reg); | |
| 9331 %} | |
| 9332 | |
| 9333 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9334 match(If cmp (CmpN op1 null)); | |
| 9335 effect(USE labl, KILL icc); | |
| 9336 | |
| 9337 size(12); | |
| 9338 ins_cost(BRANCH_COST); | |
| 9339 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
| 9340 "BP$cmp $labl" %} | |
| 9341 ins_encode %{ | |
| 9342 Label* L = $labl$$label; | |
| 9343 Assembler::Predict predict_taken = | |
| 9344 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9345 __ cmp($op1$$Register, G0); | |
| 9346 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9347 __ delayed()->nop(); | |
| 9348 %} | |
| 9349 ins_pipe(cmp_br_reg_reg); | |
| 9350 %} | |
| 9351 | |
| 9352 // Loop back branch | |
| 9353 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9354 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9355 effect(USE labl, KILL icc); | |
| 9356 | |
| 9357 size(12); | |
| 9358 ins_cost(BRANCH_COST); | |
| 9359 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9360 "BP$cmp $labl\t! Loop end" %} | |
| 9361 ins_encode %{ | |
| 9362 Label* L = $labl$$label; | |
| 9363 Assembler::Predict predict_taken = | |
| 9364 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9365 __ cmp($op1$$Register, $op2$$Register); | |
| 9366 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9367 __ delayed()->nop(); | |
| 9368 %} | |
| 9369 ins_pipe(cmp_br_reg_reg); | |
| 9370 %} | |
| 9371 | |
| 9372 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9373 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9374 effect(USE labl, KILL icc); | |
| 9375 | |
| 9376 size(12); | |
| 9377 ins_cost(BRANCH_COST); | |
| 9378 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9379 "BP$cmp $labl\t! Loop end" %} | |
| 9380 ins_encode %{ | |
| 9381 Label* L = $labl$$label; | |
| 9382 Assembler::Predict predict_taken = | |
| 9383 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9384 __ cmp($op1$$Register, $op2$$constant); | |
| 9385 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9386 __ delayed()->nop(); | |
| 9387 %} | |
| 9388 ins_pipe(cmp_br_reg_imm); | |
| 9389 %} | |
| 9390 | |
| 9391 // Short compare and branch instructions | |
| 9392 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9393 match(If cmp (CmpI op1 op2)); | |
| 9394 predicate(UseCBCond); | |
| 9395 effect(USE labl, KILL icc); | |
| 9396 | |
| 9397 size(4); | |
| 9398 ins_cost(BRANCH_COST); | |
| 9399 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9400 ins_encode %{ | |
| 9401 Label* L = $labl$$label; | |
| 9402 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9403 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9404 %} | |
| 9405 ins_short_branch(1); | |
| 9406 ins_avoid_back_to_back(1); | |
| 9407 ins_pipe(cbcond_reg_reg); | |
| 9408 %} | |
| 9409 | |
| 9410 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9411 match(If cmp (CmpI op1 op2)); | |
| 9412 predicate(UseCBCond); | |
| 9413 effect(USE labl, KILL icc); | |
| 9414 | |
| 9415 size(4); | |
| 9416 ins_cost(BRANCH_COST); | |
| 9417 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9418 ins_encode %{ | |
| 9419 Label* L = $labl$$label; | |
| 9420 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9421 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9422 %} | |
| 9423 ins_short_branch(1); | |
| 9424 ins_avoid_back_to_back(1); | |
| 9425 ins_pipe(cbcond_reg_imm); | |
| 9426 %} | |
| 9427 | |
| 9428 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9429 match(If cmp (CmpU op1 op2)); | |
| 9430 predicate(UseCBCond); | |
| 9431 effect(USE labl, KILL icc); | |
| 9432 | |
| 9433 size(4); | |
| 9434 ins_cost(BRANCH_COST); | |
| 9435 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9436 ins_encode %{ | |
| 9437 Label* L = $labl$$label; | |
| 9438 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9439 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9440 %} | |
| 9441 ins_short_branch(1); | |
| 9442 ins_avoid_back_to_back(1); | |
| 9443 ins_pipe(cbcond_reg_reg); | |
| 9444 %} | |
| 9445 | |
| 9446 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9447 match(If cmp (CmpU op1 op2)); | |
| 9448 predicate(UseCBCond); | |
| 9449 effect(USE labl, KILL icc); | |
| 9450 | |
| 9451 size(4); | |
| 9452 ins_cost(BRANCH_COST); | |
| 9453 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9454 ins_encode %{ | |
| 9455 Label* L = $labl$$label; | |
| 9456 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9457 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9458 %} | |
| 9459 ins_short_branch(1); | |
| 9460 ins_avoid_back_to_back(1); | |
| 9461 ins_pipe(cbcond_reg_imm); | |
| 9462 %} | |
| 9463 | |
| 9464 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9465 match(If cmp (CmpL op1 op2)); | |
| 9466 predicate(UseCBCond); | |
| 9467 effect(USE labl, KILL xcc); | |
| 9468 | |
| 9469 size(4); | |
| 9470 ins_cost(BRANCH_COST); | |
| 9471 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9472 ins_encode %{ | |
| 9473 Label* L = $labl$$label; | |
| 9474 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9475 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
| 9476 %} | |
| 9477 ins_short_branch(1); | |
| 9478 ins_avoid_back_to_back(1); | |
| 9479 ins_pipe(cbcond_reg_reg); | |
| 9480 %} | |
| 9481 | |
| 9482 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9483 match(If cmp (CmpL op1 op2)); | |
| 9484 predicate(UseCBCond); | |
| 9485 effect(USE labl, KILL xcc); | |
| 9486 | |
| 9487 size(4); | |
| 9488 ins_cost(BRANCH_COST); | |
| 9489 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9490 ins_encode %{ | |
| 9491 Label* L = $labl$$label; | |
| 9492 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9493 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
| 9494 %} | |
| 9495 ins_short_branch(1); | |
| 9496 ins_avoid_back_to_back(1); | |
| 9497 ins_pipe(cbcond_reg_imm); | |
| 9498 %} | |
| 9499 | |
| 9500 // Compare Pointers and branch | |
| 9501 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9502 match(If cmp (CmpP op1 op2)); | |
| 9503 predicate(UseCBCond); | |
| 9504 effect(USE labl, KILL pcc); | |
| 9505 | |
| 9506 size(4); | |
| 9507 ins_cost(BRANCH_COST); | |
| 9508 #ifdef _LP64 | |
| 9509 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9510 #else | |
| 9511 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9512 #endif | |
| 9513 ins_encode %{ | |
| 9514 Label* L = $labl$$label; | |
| 9515 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9516 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
| 9517 %} | |
| 9518 ins_short_branch(1); | |
| 9519 ins_avoid_back_to_back(1); | |
| 9520 ins_pipe(cbcond_reg_reg); | |
| 9521 %} | |
| 9522 | |
| 9523 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9524 match(If cmp (CmpP op1 null)); | |
| 9525 predicate(UseCBCond); | |
| 9526 effect(USE labl, KILL pcc); | |
| 9527 | |
| 9528 size(4); | |
| 9529 ins_cost(BRANCH_COST); | |
| 9530 #ifdef _LP64 | |
| 9531 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
| 9532 #else | |
| 9533 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
| 9534 #endif | |
| 9535 ins_encode %{ | |
| 9536 Label* L = $labl$$label; | |
| 9537 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9538 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
| 9539 %} | |
| 9540 ins_short_branch(1); | |
| 9541 ins_avoid_back_to_back(1); | |
| 9542 ins_pipe(cbcond_reg_reg); | |
| 9543 %} | |
| 9544 | |
| 9545 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9546 match(If cmp (CmpN op1 op2)); | |
| 9547 predicate(UseCBCond); | |
| 9548 effect(USE labl, KILL icc); | |
| 9549 | |
| 9550 size(4); | |
| 9551 ins_cost(BRANCH_COST); | |
| 9552 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
| 9553 ins_encode %{ | |
| 9554 Label* L = $labl$$label; | |
| 9555 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9556 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9557 %} | |
| 9558 ins_short_branch(1); | |
| 9559 ins_avoid_back_to_back(1); | |
| 9560 ins_pipe(cbcond_reg_reg); | |
| 9561 %} | |
| 9562 | |
| 9563 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9564 match(If cmp (CmpN op1 null)); | |
| 9565 predicate(UseCBCond); | |
| 9566 effect(USE labl, KILL icc); | |
| 9567 | |
| 9568 size(4); | |
| 9569 ins_cost(BRANCH_COST); | |
| 9570 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
| 9571 ins_encode %{ | |
| 9572 Label* L = $labl$$label; | |
| 9573 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9574 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
| 9575 %} | |
| 9576 ins_short_branch(1); | |
| 9577 ins_avoid_back_to_back(1); | |
| 9578 ins_pipe(cbcond_reg_reg); | |
| 9579 %} | |
| 9580 | |
| 9581 // Loop back branch | |
| 9582 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9583 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9584 predicate(UseCBCond); | |
| 9585 effect(USE labl, KILL icc); | |
| 9586 | |
| 9587 size(4); | |
| 9588 ins_cost(BRANCH_COST); | |
| 9589 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9590 ins_encode %{ | |
| 9591 Label* L = $labl$$label; | |
| 9592 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9593 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9594 %} | |
| 9595 ins_short_branch(1); | |
| 9596 ins_avoid_back_to_back(1); | |
| 9597 ins_pipe(cbcond_reg_reg); | |
| 9598 %} | |
| 9599 | |
| 9600 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9601 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9602 predicate(UseCBCond); | |
| 9603 effect(USE labl, KILL icc); | |
| 9604 | |
| 9605 size(4); | |
| 9606 ins_cost(BRANCH_COST); | |
| 9607 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9608 ins_encode %{ | |
| 9609 Label* L = $labl$$label; | |
| 9610 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9611 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9612 %} | |
| 9613 ins_short_branch(1); | |
| 9614 ins_avoid_back_to_back(1); | |
| 9615 ins_pipe(cbcond_reg_imm); | |
| 9616 %} | |
| 9617 | |
| 9618 // Branch-on-register tests all 64 bits. We assume that values | |
| 9619 // in 64-bit registers always remains zero or sign extended | |
| 9620 // unless our code munges the high bits. Interrupts can chop | |
| 9621 // the high order bits to zero or sign at any time. | |
| 9622 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9623 match(If cmp (CmpI op1 zero)); | |
| 9624 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9625 effect(USE labl); | |
| 9626 | |
| 9627 size(8); | |
| 9628 ins_cost(BRANCH_COST); | |
| 9629 format %{ "BR$cmp $op1,$labl" %} | |
| 9630 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9631 ins_pipe(br_reg); | |
| 9632 %} | |
| 9633 | |
| 9634 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9635 match(If cmp (CmpP op1 null)); | |
| 9636 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9637 effect(USE labl); | |
| 9638 | |
| 9639 size(8); | |
| 9640 ins_cost(BRANCH_COST); | |
| 9641 format %{ "BR$cmp $op1,$labl" %} | |
| 9642 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9643 ins_pipe(br_reg); | |
| 9644 %} | |
| 9645 | |
| 9646 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9647 match(If cmp (CmpL op1 zero)); | |
| 9648 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9649 effect(USE labl); | |
| 9650 | |
| 9651 size(8); | |
| 9652 ins_cost(BRANCH_COST); | |
| 9653 format %{ "BR$cmp $op1,$labl" %} | |
| 9654 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9655 ins_pipe(br_reg); | |
| 9656 %} | |
| 9657 | |
| 9658 | |
| 0 | 9659 // ============================================================================ |
| 9660 // Long Compare | |
| 9661 // | |
| 9662 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9663 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9664 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9665 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9666 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9667 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9668 // NE test is negated from that. | |
| 9669 | |
| 9670 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9671 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9672 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9673 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9674 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9675 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9676 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9677 // both forms beat the trinary form of long-compare and both are very useful | |
| 9678 // on Intel which has so few registers. | |
| 9679 | |
| 9680 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9681 match(If cmp xcc); | |
| 9682 effect(USE labl); | |
| 9683 | |
| 9684 size(8); | |
| 9685 ins_cost(BRANCH_COST); | |
| 9686 format %{ "BP$cmp $xcc,$labl" %} | |
| 3839 | 9687 ins_encode %{ |
| 9688 Label* L = $labl$$label; | |
| 9689 Assembler::Predict predict_taken = | |
| 9690 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9691 | |
| 9692 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9693 __ delayed()->nop(); | |
| 9694 %} | |
| 0 | 9695 ins_pipe(br_cc); |
| 9696 %} | |
| 9697 | |
| 9698 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9699 // This is the test to avoid. | |
| 9700 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9701 match(Set dst (CmpL3 src1 src2) ); | |
| 9702 effect( KILL ccr ); | |
| 9703 ins_cost(6*DEFAULT_COST); | |
| 9704 size(24); | |
| 9705 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9706 "\tBLT,a,pn done\n" | |
| 9707 "\tMOV -1,$dst\t! delay slot\n" | |
| 9708 "\tBGT,a,pn done\n" | |
| 9709 "\tMOV 1,$dst\t! delay slot\n" | |
| 9710 "\tCLR $dst\n" | |
| 9711 "done:" %} | |
| 9712 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9713 ins_pipe(cmpL_reg); | |
| 9714 %} | |
| 9715 | |
| 9716 // Conditional move | |
| 9717 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9718 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9719 ins_cost(150); | |
| 9720 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9721 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9722 ins_pipe(ialu_reg); | |
| 9723 %} | |
| 9724 | |
| 9725 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9726 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9727 ins_cost(140); | |
| 9728 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9729 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9730 ins_pipe(ialu_imm); | |
| 9731 %} | |
| 9732 | |
| 9733 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9734 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9735 ins_cost(150); | |
| 9736 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9737 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9738 ins_pipe(ialu_reg); | |
| 9739 %} | |
| 9740 | |
| 9741 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9742 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9743 ins_cost(140); | |
| 9744 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9745 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9746 ins_pipe(ialu_imm); | |
| 9747 %} | |
| 9748 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9749 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9750 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9751 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9752 format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9753 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9754 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9755 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9756 |
| 0 | 9757 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9758 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9759 ins_cost(150); | |
| 9760 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9761 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9762 ins_pipe(ialu_reg); | |
| 9763 %} | |
| 9764 | |
| 9765 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9766 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9767 ins_cost(140); | |
| 9768 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9769 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9770 ins_pipe(ialu_imm); | |
| 9771 %} | |
| 9772 | |
| 9773 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9774 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9775 ins_cost(150); | |
| 9776 opcode(0x101); | |
| 9777 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9778 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9779 ins_pipe(int_conditional_float_move); | |
| 9780 %} | |
| 9781 | |
| 9782 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9783 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9784 ins_cost(150); | |
| 9785 opcode(0x102); | |
| 9786 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9787 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9788 ins_pipe(int_conditional_float_move); | |
| 9789 %} | |
| 9790 | |
| 9791 // ============================================================================ | |
| 9792 // Safepoint Instruction | |
| 9793 instruct safePoint_poll(iRegP poll) %{ | |
| 9794 match(SafePoint poll); | |
| 9795 effect(USE poll); | |
| 9796 | |
| 9797 size(4); | |
| 9798 #ifdef _LP64 | |
| 9799 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9800 #else | |
| 9801 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9802 #endif | |
| 9803 ins_encode %{ | |
| 9804 __ relocate(relocInfo::poll_type); | |
| 9805 __ ld_ptr($poll$$Register, 0, G0); | |
| 9806 %} | |
| 9807 ins_pipe(loadPollP); | |
| 9808 %} | |
| 9809 | |
| 9810 // ============================================================================ | |
| 9811 // Call Instructions | |
| 9812 // Call Java Static Instruction | |
| 9813 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9814 match(CallStaticJava); | |
| 1567 | 9815 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9816 effect(USE meth); |
| 9817 | |
| 9818 size(8); | |
| 9819 ins_cost(CALL_COST); | |
| 9820 format %{ "CALL,static ; NOP ==> " %} | |
| 9821 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9822 ins_pipe(simple_call); | |
| 9823 %} | |
| 9824 | |
| 1567 | 9825 // Call Java Static Instruction (method handle version) |
| 9826 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9827 match(CallStaticJava); | |
| 9828 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9829 effect(USE meth, KILL l7_mh_SP_save); | |
| 9830 | |
|
3856
bd87c0dcaba5
7079769: JSR 292: incorrect size() for CallStaticJavaHandle on sparc
twisti
parents:
3854
diff
changeset
|
9831 size(16); |
| 1567 | 9832 ins_cost(CALL_COST); |
| 9833 format %{ "CALL,static/MethodHandle" %} | |
| 9834 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9835 ins_pipe(simple_call); | |
| 9836 %} | |
| 9837 | |
| 0 | 9838 // Call Java Dynamic Instruction |
| 9839 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9840 match(CallDynamicJava); | |
| 9841 effect(USE meth); | |
| 9842 | |
| 9843 ins_cost(CALL_COST); | |
| 9844 format %{ "SET (empty),R_G5\n\t" | |
| 9845 "CALL,dynamic ; NOP ==> " %} | |
| 9846 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9847 ins_pipe(call); | |
| 9848 %} | |
| 9849 | |
| 9850 // Call Runtime Instruction | |
| 9851 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9852 match(CallRuntime); | |
| 9853 effect(USE meth, KILL l7); | |
| 9854 ins_cost(CALL_COST); | |
| 9855 format %{ "CALL,runtime" %} | |
| 9856 ins_encode( Java_To_Runtime( meth ), | |
| 9857 call_epilog, adjust_long_from_native_call ); | |
| 9858 ins_pipe(simple_call); | |
| 9859 %} | |
| 9860 | |
| 9861 // Call runtime without safepoint - same as CallRuntime | |
| 9862 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9863 match(CallLeaf); | |
| 9864 effect(USE meth, KILL l7); | |
| 9865 ins_cost(CALL_COST); | |
| 9866 format %{ "CALL,runtime leaf" %} | |
| 9867 ins_encode( Java_To_Runtime( meth ), | |
| 9868 call_epilog, | |
| 9869 adjust_long_from_native_call ); | |
| 9870 ins_pipe(simple_call); | |
| 9871 %} | |
| 9872 | |
| 9873 // Call runtime without safepoint - same as CallLeaf | |
| 9874 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9875 match(CallLeafNoFP); | |
| 9876 effect(USE meth, KILL l7); | |
| 9877 ins_cost(CALL_COST); | |
| 9878 format %{ "CALL,runtime leaf nofp" %} | |
| 9879 ins_encode( Java_To_Runtime( meth ), | |
| 9880 call_epilog, | |
| 9881 adjust_long_from_native_call ); | |
| 9882 ins_pipe(simple_call); | |
| 9883 %} | |
| 9884 | |
| 9885 // Tail Call; Jump from runtime stub to Java code. | |
| 9886 // Also known as an 'interprocedural jump'. | |
| 9887 // Target of jump will eventually return to caller. | |
| 9888 // TailJump below removes the return address. | |
| 9889 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 9890 match(TailCall jump_target method_oop ); | |
| 9891 | |
| 9892 ins_cost(CALL_COST); | |
| 9893 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 9894 ins_encode(form_jmpl(jump_target)); | |
| 9895 ins_pipe(tail_call); | |
| 9896 %} | |
| 9897 | |
| 9898 | |
| 9899 // Return Instruction | |
| 9900 instruct Ret() %{ | |
| 9901 match(Return); | |
| 9902 | |
| 9903 // The epilogue node did the ret already. | |
| 9904 size(0); | |
| 9905 format %{ "! return" %} | |
| 9906 ins_encode(); | |
| 9907 ins_pipe(empty); | |
| 9908 %} | |
| 9909 | |
| 9910 | |
| 9911 // Tail Jump; remove the return address; jump to target. | |
| 9912 // TailCall above leaves the return address around. | |
| 9913 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 9914 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 9915 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 9916 // in %i0. | |
| 9917 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 9918 match( TailJump jump_target ex_oop ); | |
| 9919 ins_cost(CALL_COST); | |
| 9920 format %{ "! discard R_O7\n\t" | |
| 9921 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 9922 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 9923 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 9924 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 9925 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 9926 ins_pipe(tail_call); | |
| 9927 %} | |
| 9928 | |
| 9929 // Create exception oop: created by stack-crawling runtime code. | |
| 9930 // Created exception is now available to this handler, and is setup | |
| 9931 // just prior to jumping to this handler. No code emitted. | |
| 9932 instruct CreateException( o0RegP ex_oop ) | |
| 9933 %{ | |
| 9934 match(Set ex_oop (CreateEx)); | |
| 9935 ins_cost(0); | |
| 9936 | |
| 9937 size(0); | |
| 9938 // use the following format syntax | |
| 9939 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 9940 ins_encode(); | |
| 9941 ins_pipe(empty); | |
| 9942 %} | |
| 9943 | |
| 9944 | |
| 9945 // Rethrow exception: | |
| 9946 // The exception oop will come in the first argument position. | |
| 9947 // Then JUMP (not call) to the rethrow stub code. | |
| 9948 instruct RethrowException() | |
| 9949 %{ | |
| 9950 match(Rethrow); | |
| 9951 ins_cost(CALL_COST); | |
| 9952 | |
| 9953 // use the following format syntax | |
| 9954 format %{ "Jmp rethrow_stub" %} | |
| 9955 ins_encode(enc_rethrow); | |
| 9956 ins_pipe(tail_call); | |
| 9957 %} | |
| 9958 | |
| 9959 | |
| 9960 // Die now | |
| 9961 instruct ShouldNotReachHere( ) | |
| 9962 %{ | |
| 9963 match(Halt); | |
| 9964 ins_cost(CALL_COST); | |
| 9965 | |
| 9966 size(4); | |
| 9967 // Use the following format syntax | |
| 9968 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 9969 ins_encode( form2_illtrap() ); | |
| 9970 ins_pipe(tail_call); | |
| 9971 %} | |
| 9972 | |
| 9973 // ============================================================================ | |
| 9974 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 9975 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 9976 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 9977 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 9978 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 9979 match(Set index (PartialSubtypeCheck sub super)); | |
| 9980 effect( KILL pcc, KILL o7 ); | |
| 9981 ins_cost(DEFAULT_COST*10); | |
| 9982 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 9983 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9984 ins_pipe(partial_subtype_check_pipe); | |
| 9985 %} | |
| 9986 | |
| 9987 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 9988 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 9989 effect( KILL idx, KILL o7 ); | |
| 9990 ins_cost(DEFAULT_COST*10); | |
| 9991 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 9992 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9993 ins_pipe(partial_subtype_check_pipe); | |
| 9994 %} | |
| 9995 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9996 |
| 0 | 9997 // ============================================================================ |
| 9998 // inlined locking and unlocking | |
| 9999 | |
| 4777 | 10000 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
| 0 | 10001 match(Set pcc (FastLock object box)); |
| 10002 | |
| 4777 | 10003 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
| 0 | 10004 ins_cost(100); |
| 10005 | |
| 4777 | 10006 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
| 0 | 10007 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
| 10008 ins_pipe(long_memory_op); | |
| 10009 %} | |
| 10010 | |
| 10011 | |
| 4777 | 10012 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
| 0 | 10013 match(Set pcc (FastUnlock object box)); |
| 4777 | 10014 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
| 0 | 10015 ins_cost(100); |
| 10016 | |
| 4777 | 10017 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
| 0 | 10018 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
| 10019 ins_pipe(long_memory_op); | |
| 10020 %} | |
| 10021 | |
| 3892 | 10022 // The encodings are generic. |
| 0 | 10023 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
| 3892 | 10024 predicate(!use_block_zeroing(n->in(2)) ); |
| 0 | 10025 match(Set dummy (ClearArray cnt base)); |
| 10026 effect(TEMP temp, KILL ccr); | |
| 10027 ins_cost(300); | |
| 10028 format %{ "MOV $cnt,$temp\n" | |
| 10029 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 10030 " BRge loop\t\t! Clearing loop\n" | |
| 10031 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 3892 | 10032 |
| 10033 ins_encode %{ | |
| 10034 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 10035 Register nof_bytes_arg = $cnt$$Register; | |
| 10036 Register nof_bytes_tmp = $temp$$Register; | |
| 10037 Register base_pointer_arg = $base$$Register; | |
| 10038 | |
| 10039 Label loop; | |
| 10040 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 10041 | |
| 10042 // Loop and clear, walking backwards through the array. | |
| 10043 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 10044 __ bind(loop); | |
| 10045 __ deccc(nof_bytes_tmp, 8); | |
| 10046 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 10047 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 10048 // %%%% this mini-loop must not cross a cache boundary! | |
| 10049 %} | |
| 10050 ins_pipe(long_memory_op); | |
| 10051 %} | |
| 10052 | |
| 10053 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
| 10054 predicate(use_block_zeroing(n->in(2))); | |
| 10055 match(Set dummy (ClearArray cnt base)); | |
| 10056 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
| 10057 ins_cost(300); | |
| 10058 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
| 10059 | |
| 10060 ins_encode %{ | |
| 10061 | |
| 10062 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
| 10063 Register to = $base$$Register; | |
| 10064 Register count = $cnt$$Register; | |
| 10065 | |
| 10066 Label Ldone; | |
| 10067 __ nop(); // Separate short branches | |
| 10068 // Use BIS for zeroing (temp is not used). | |
| 10069 __ bis_zeroing(to, count, G0, Ldone); | |
| 10070 __ bind(Ldone); | |
| 10071 | |
| 10072 %} | |
| 10073 ins_pipe(long_memory_op); | |
| 10074 %} | |
| 10075 | |
| 10076 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
| 10077 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
| 10078 match(Set dummy (ClearArray cnt base)); | |
| 10079 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
| 10080 ins_cost(300); | |
| 10081 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
| 10082 | |
| 10083 ins_encode %{ | |
| 10084 | |
| 10085 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
| 10086 Register to = $base$$Register; | |
| 10087 Register count = $cnt$$Register; | |
| 10088 Register temp = $tmp$$Register; | |
| 10089 | |
| 10090 Label Ldone; | |
| 10091 __ nop(); // Separate short branches | |
| 10092 // Use BIS for zeroing | |
| 10093 __ bis_zeroing(to, count, temp, Ldone); | |
| 10094 __ bind(Ldone); | |
| 10095 | |
| 10096 %} | |
| 0 | 10097 ins_pipe(long_memory_op); |
| 10098 %} | |
| 10099 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10100 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10101 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10102 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10103 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 10104 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10105 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10106 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 10107 ins_pipe(long_memory_op); |
| 10108 %} | |
| 10109 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10110 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10111 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10112 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10113 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 10114 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10115 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10116 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 10117 ins_pipe(long_memory_op); |
| 10118 %} | |
| 10119 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10120 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10121 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 10122 match(Set result (AryEq ary1 ary2)); |
| 10123 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 10124 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10125 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10126 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 10127 ins_pipe(long_memory_op); |
| 10128 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10129 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10130 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10131 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10132 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10133 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10134 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10135 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10136 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10137 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10138 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10139 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10140 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10141 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10142 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10143 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10144 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10145 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10146 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10147 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10148 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10149 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10150 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10151 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10152 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10153 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10154 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10155 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10156 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10157 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10158 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10159 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10160 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10161 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10162 __ srl(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10163 __ srl(Rsrc, 0, Rdst); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10164 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10165 __ srl(Rdst, 2, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10166 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10167 __ srl(Rdst, 4, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10168 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10169 __ srl(Rdst, 8, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10170 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10171 __ srl(Rdst, 16, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10172 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10173 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10174 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10175 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10176 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10177 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10178 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10179 |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10180 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10181 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10182 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10183 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10184 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10185 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10186 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10187 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10188 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10189 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10190 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10191 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10192 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10193 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10194 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10195 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10196 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10197 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10198 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10199 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10200 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10201 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10202 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10203 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10204 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10205 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10206 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10207 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10208 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10209 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10210 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10211 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10212 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10213 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10214 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10215 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10216 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10217 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10218 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10219 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10220 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10221 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10222 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10223 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10224 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10225 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10226 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10227 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10228 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10229 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10230 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10231 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10232 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10233 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10234 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10235 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10236 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10237 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10238 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10239 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10240 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10241 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10242 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10243 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10244 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10245 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10246 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10247 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10248 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10249 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10250 |
|
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10251 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10252 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10253 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10254 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10255 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10256 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10257 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10258 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10259 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10260 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10261 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10262 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10263 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10264 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10265 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10266 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10267 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10268 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10269 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10270 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10271 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10272 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10273 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10274 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10275 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10276 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10277 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10278 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10279 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10280 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10281 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10282 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10283 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10284 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10285 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10286 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10287 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10288 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10289 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10290 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10291 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10292 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10293 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10294 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10295 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10296 |
| 0 | 10297 // ============================================================================ |
| 10298 //------------Bytes reverse-------------------------------------------------- | |
| 10299 | |
| 10300 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 10301 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10302 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10303 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10304 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10305 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10306 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10307 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10308 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10309 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10310 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10311 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10312 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10313 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10314 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10315 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10316 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10317 match(Set dst (ReverseBytesL src)); |
| 0 | 10318 |
| 10319 // Op cost is artificially doubled to make sure that load or store | |
| 10320 // instructions are preferred over this one which requires a spill | |
| 10321 // onto a stack slot. | |
| 10322 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10323 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10324 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10325 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10326 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10327 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10328 %} |
| 0 | 10329 ins_pipe( iload_mem ); |
| 10330 %} | |
| 10331 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10332 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10333 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10334 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10335 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10336 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10337 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10338 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10339 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10340 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10341 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10342 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10343 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10344 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10345 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10346 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10347 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10348 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10349 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10350 match(Set dst (ReverseBytesS src)); |
| 0 | 10351 |
| 10352 // Op cost is artificially doubled to make sure that load or store | |
| 10353 // instructions are preferred over this one which requires a spill | |
| 10354 // onto a stack slot. | |
| 10355 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10356 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10357 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10358 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10359 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10360 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10361 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10362 %} |
| 0 | 10363 ins_pipe( iload_mem ); |
| 10364 %} | |
| 10365 | |
| 10366 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10367 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 10368 match(Set dst (ReverseBytesI (LoadI src))); |
| 10369 | |
| 10370 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10371 size(4); |
| 0 | 10372 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 10373 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10374 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10375 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10376 %} |
| 0 | 10377 ins_pipe(iload_mem); |
| 10378 %} | |
| 10379 | |
| 10380 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10381 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 10382 match(Set dst (ReverseBytesL (LoadL src))); |
| 10383 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10384 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10385 size(4); |
| 0 | 10386 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 10387 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10388 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10389 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10390 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10391 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10392 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10393 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10394 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10395 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10396 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10397 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10398 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10399 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10400 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10401 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10402 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10403 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10404 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10405 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10406 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10407 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10408 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10409 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10410 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10411 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10412 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10413 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10414 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10415 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10416 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10417 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10418 %} |
| 0 | 10419 ins_pipe(iload_mem); |
| 10420 %} | |
| 10421 | |
| 10422 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10423 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 10424 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 10425 | |
| 10426 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10427 size(4); |
| 0 | 10428 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 10429 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10430 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10431 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10432 %} |
| 0 | 10433 ins_pipe(istore_mem_reg); |
| 10434 %} | |
| 10435 | |
| 10436 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10437 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 10438 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 10439 | |
| 10440 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10441 size(4); |
| 0 | 10442 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 10443 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10444 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10445 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10446 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10447 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10448 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10449 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10450 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10451 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10452 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10453 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10454 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10455 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10456 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10457 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10458 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10459 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10460 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10461 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10462 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10463 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10464 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10465 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10466 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10467 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10468 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10469 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10470 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10471 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10472 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10473 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10474 %} |
| 0 | 10475 ins_pipe(istore_mem_reg); |
| 10476 %} | |
| 10477 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10478 // ====================VECTOR INSTRUCTIONS===================================== |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10479 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10480 // Load Aligned Packed values into a Double Register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10481 instruct loadV8(regD dst, memory mem) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10482 predicate(n->as_LoadVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10483 match(Set dst (LoadVector mem)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10484 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10485 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10486 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10487 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10488 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10489 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10490 ins_pipe(floadD_mem); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10491 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10492 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10493 // Store Vector in Double register to memory |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10494 instruct storeV8(memory mem, regD src) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10495 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10496 match(Set mem (StoreVector mem src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10497 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10498 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10499 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10500 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10501 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10502 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10503 ins_pipe(fstoreD_mem_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10504 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10505 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10506 // Store Zero into vector in memory |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10507 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10508 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10509 match(Set mem (StoreVector mem (ReplicateB zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10510 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10511 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10512 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10513 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10514 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10515 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10516 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10517 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10518 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10519 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10520 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10521 match(Set mem (StoreVector mem (ReplicateS zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10522 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10523 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10524 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10525 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10526 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10527 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10528 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10529 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10530 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10531 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10532 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10533 match(Set mem (StoreVector mem (ReplicateI zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10534 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10535 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10536 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10537 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10538 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10539 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10540 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10541 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10542 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10543 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10544 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10545 match(Set mem (StoreVector mem (ReplicateF zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10546 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10547 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10548 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10549 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10550 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10551 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10552 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10553 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10554 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10555 // Replicate scalar to packed byte values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10556 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10557 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10558 match(Set dst (ReplicateB src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10559 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10560 format %{ "SLLX $src,56,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10561 "SRLX $tmp, 8,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10562 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10563 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10564 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10565 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10566 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10567 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10568 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10569 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10570 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10571 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10572 __ sllx(Rsrc, 56, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10573 __ srlx(Rtmp, 8, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10574 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10575 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10576 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10577 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10578 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10579 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10580 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10581 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10582 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10583 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10584 // Replicate scalar to packed byte values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10585 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10586 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10587 match(Set dst (ReplicateB src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10588 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10589 format %{ "SLLX $src,56,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10590 "SRLX $tmp, 8,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10591 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10592 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10593 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10594 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10595 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10596 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10597 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10598 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10599 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10600 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10601 __ sllx(Rsrc, 56, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10602 __ srlx(Rtmp, 8, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10603 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10604 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10605 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10606 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10607 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10608 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10609 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10610 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10611 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10612 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10613 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10614 // Replicate scalar constant to packed byte values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10615 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10616 predicate(n->as_Vector()->length() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10617 match(Set dst (ReplicateB con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10618 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10619 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10620 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10621 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10622 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10623 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10624 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10625 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10626 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10627 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10628 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10629 // Replicate scalar to packed char/short values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10630 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10631 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10632 match(Set dst (ReplicateS src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10633 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10634 format %{ "SLLX $src,48,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10635 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10636 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10637 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10638 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10639 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10640 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10641 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10642 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10643 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10644 __ sllx(Rsrc, 48, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10645 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10646 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10647 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10648 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10649 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10650 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10651 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10652 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10653 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10654 // Replicate scalar to packed char/short values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10655 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10656 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10657 match(Set dst (ReplicateS src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10658 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10659 format %{ "SLLX $src,48,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10660 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10661 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10662 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10663 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10664 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10665 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10666 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10667 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10668 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10669 __ sllx(Rsrc, 48, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10670 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10671 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 // Replicate scalar constant to packed char/short values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 predicate(n->as_Vector()->length() == 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 match(Set dst (ReplicateS con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 // Replicate scalar to packed int values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 match(Set dst (ReplicateI src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 format %{ "SLLX $src,32,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 __ sllx(Rsrc, 32, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 // Replicate scalar to packed int values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 match(Set dst (ReplicateI src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 format %{ "SLLX $src,32,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 __ sllx(Rsrc, 32, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 // Replicate scalar zero constant to packed int values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 predicate(n->as_Vector()->length() == 2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 match(Set dst (ReplicateI con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 // Replicate scalar to packed float values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 predicate(n->as_Vector()->length() == 2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 match(Set dst (ReplicateF src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 ins_cost(MEMORY_REF_COST*2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 "STF $src,$dst.lo" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 opcode(Assembler::stf_op3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 ins_pipe(fstoreF_stk_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 // Replicate scalar zero constant to packed float values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 predicate(n->as_Vector()->length() == 2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10768 match(Set dst (ReplicateF con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10769 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10770 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10771 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10772 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10773 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10774 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10775 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10776 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10777 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10778 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10779 |
| 0 | 10780 //----------PEEPHOLE RULES----------------------------------------------------- |
| 10781 // These must follow all instruction definitions as they use the names | |
| 10782 // defined in the instructions definitions. | |
| 10783 // | |
| 605 | 10784 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 10785 // |
| 10786 // peepconstraint %{ | |
| 10787 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 10788 // [, ...] ); | |
| 10789 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 10790 // | |
| 10791 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 10792 // // provide an instruction_number.operand_name for each operand that appears | |
| 10793 // // in the replacement instruction's match rule | |
| 10794 // | |
| 10795 // ---------VM FLAGS--------------------------------------------------------- | |
| 10796 // | |
| 10797 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 10798 // | |
| 10799 // Each peephole rule is given an identifying number starting with zero and | |
| 10800 // increasing by one in the order seen by the parser. An individual peephole | |
| 10801 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 10802 // on the command-line. | |
| 10803 // | |
| 10804 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 10805 // | |
| 10806 // Only match adjacent instructions in same basic block | |
| 10807 // Only equality constraints | |
| 10808 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 10809 // Only one replacement instruction | |
| 10810 // | |
| 10811 // ---------EXAMPLE---------------------------------------------------------- | |
| 10812 // | |
| 10813 // // pertinent parts of existing instructions in architecture description | |
| 10814 // instruct movI(eRegI dst, eRegI src) %{ | |
| 10815 // match(Set dst (CopyI src)); | |
| 10816 // %} | |
| 10817 // | |
| 10818 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 10819 // match(Set dst (AddI dst src)); | |
| 10820 // effect(KILL cr); | |
| 10821 // %} | |
| 10822 // | |
| 10823 // // Change (inc mov) to lea | |
| 10824 // peephole %{ | |
| 10825 // // increment preceeded by register-register move | |
| 10826 // peepmatch ( incI_eReg movI ); | |
| 10827 // // require that the destination register of the increment | |
| 10828 // // match the destination register of the move | |
| 10829 // peepconstraint ( 0.dst == 1.dst ); | |
| 10830 // // construct a replacement instruction that sets | |
| 10831 // // the destination to ( move's source register + one ) | |
| 10832 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 10833 // %} | |
| 10834 // | |
| 10835 | |
| 10836 // // Change load of spilled value to only a spill | |
| 10837 // instruct storeI(memory mem, eRegI src) %{ | |
| 10838 // match(Set mem (StoreI mem src)); | |
| 10839 // %} | |
| 10840 // | |
| 10841 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10842 // match(Set dst (LoadI mem)); | |
| 10843 // %} | |
| 10844 // | |
| 10845 // peephole %{ | |
| 10846 // peepmatch ( loadI storeI ); | |
| 10847 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10848 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 10849 // %} | |
| 10850 | |
| 10851 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 10852 // These must follow all instruction definitions as they use the names | |
| 10853 // defined in the instructions definitions. | |
| 10854 // | |
| 10855 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 10856 | |
| 10857 //----------PIPELINE----------------------------------------------------------- | |
| 10858 // Rules which define the behavior of the target architectures pipeline. |