Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.hpp @ 18357:09550eb6ddfb
replace use of '==' with .equals()
author | Doug Simon <doug.simon@oracle.com> |
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date | Wed, 12 Nov 2014 15:33:20 +0100 |
parents | 52b4284cb496 |
children | 7848fc12602b |
rev | line source |
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0 | 1 /* |
7951 | 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
27 | |
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28 #include "asm/register.hpp" |
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29 |
0 | 30 class BiasedLockingCounters; |
31 | |
32 // Contains all the definitions needed for x86 assembly code generation. | |
33 | |
34 // Calling convention | |
35 class Argument VALUE_OBJ_CLASS_SPEC { | |
36 public: | |
37 enum { | |
38 #ifdef _LP64 | |
39 #ifdef _WIN64 | |
40 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
41 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
42 #else | |
43 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
44 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
45 #endif // _WIN64 | |
46 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
47 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
48 #else | |
49 n_register_parameters = 0 // 0 registers used to pass arguments | |
50 #endif // _LP64 | |
51 }; | |
52 }; | |
53 | |
54 | |
55 #ifdef _LP64 | |
56 // Symbolically name the register arguments used by the c calling convention. | |
57 // Windows is different from linux/solaris. So much for standards... | |
58 | |
59 #ifdef _WIN64 | |
60 | |
61 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
62 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
63 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
64 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
65 | |
304 | 66 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
67 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
68 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
69 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
0 | 70 |
71 #else | |
72 | |
73 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
74 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
75 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
76 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
77 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
78 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
79 | |
304 | 80 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
81 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
82 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
83 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
84 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
85 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
86 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
87 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
0 | 88 |
89 #endif // _WIN64 | |
90 | |
91 // Symbolically name the register arguments used by the Java calling convention. | |
92 // We have control over the convention for java so we can do what we please. | |
93 // What pleases us is to offset the java calling convention so that when | |
94 // we call a suitable jni method the arguments are lined up and we don't | |
95 // have to do little shuffling. A suitable jni method is non-static and a | |
96 // small number of arguments (two fewer args on windows) | |
97 // | |
98 // |-------------------------------------------------------| | |
99 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
100 // |-------------------------------------------------------| | |
101 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
102 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
103 // |-------------------------------------------------------| | |
104 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
105 // |-------------------------------------------------------| | |
106 | |
107 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
108 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
109 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
110 // Windows runs out of register args here | |
111 #ifdef _WIN64 | |
112 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
113 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
114 #else | |
115 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
116 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
117 #endif /* _WIN64 */ | |
118 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
119 | |
304 | 120 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
121 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
122 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
123 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
124 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
125 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
126 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
127 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
0 | 128 |
129 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
130 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
131 | |
304 | 132 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
0 | 133 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
134 | |
304 | 135 #else |
136 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
137 // Using noreg ensures if the dead code is incorrectly live and executed it | |
138 // will cause an assertion failure | |
139 #define rscratch1 noreg | |
2002 | 140 #define rscratch2 noreg |
304 | 141 |
0 | 142 #endif // _LP64 |
143 | |
1564 | 144 // JSR 292 fixed register usages: |
145 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
146 | |
0 | 147 // Address is an abstraction used to represent a memory location |
148 // using any of the amd64 addressing modes with one object. | |
149 // | |
150 // Note: A register location is represented via a Register, not | |
151 // via an address for efficiency & simplicity reasons. | |
152 | |
153 class ArrayAddress; | |
154 | |
155 class Address VALUE_OBJ_CLASS_SPEC { | |
156 public: | |
157 enum ScaleFactor { | |
158 no_scale = -1, | |
159 times_1 = 0, | |
160 times_2 = 1, | |
161 times_4 = 2, | |
304 | 162 times_8 = 3, |
163 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
0 | 164 }; |
622
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165 static ScaleFactor times(int size) { |
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166 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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167 if (size == 8) return times_8; |
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168 if (size == 4) return times_4; |
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169 if (size == 2) return times_2; |
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170 return times_1; |
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171 } |
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172 static int scale_size(ScaleFactor scale) { |
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173 assert(scale != no_scale, ""); |
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174 assert(((1 << (int)times_1) == 1 && |
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175 (1 << (int)times_2) == 2 && |
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176 (1 << (int)times_4) == 4 && |
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177 (1 << (int)times_8) == 8), ""); |
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178 return (1 << (int)scale); |
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179 } |
0 | 180 |
181 private: | |
182 Register _base; | |
183 Register _index; | |
184 ScaleFactor _scale; | |
185 int _disp; | |
186 RelocationHolder _rspec; | |
187 | |
304 | 188 // Easily misused constructors make them private |
189 // %%% can we make these go away? | |
190 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
191 Address(int disp, address loc, relocInfo::relocType rtype); | |
192 Address(int disp, address loc, RelocationHolder spec); | |
0 | 193 |
194 public: | |
304 | 195 |
196 int disp() { return _disp; } | |
0 | 197 // creation |
198 Address() | |
199 : _base(noreg), | |
200 _index(noreg), | |
201 _scale(no_scale), | |
202 _disp(0) { | |
203 } | |
204 | |
205 // No default displacement otherwise Register can be implicitly | |
206 // converted to 0(Register) which is quite a different animal. | |
207 | |
208 Address(Register base, int disp) | |
209 : _base(base), | |
210 _index(noreg), | |
211 _scale(no_scale), | |
212 _disp(disp) { | |
213 } | |
214 | |
215 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
216 : _base (base), | |
217 _index(index), | |
218 _scale(scale), | |
219 _disp (disp) { | |
220 assert(!index->is_valid() == (scale == Address::no_scale), | |
221 "inconsistent address"); | |
222 } | |
223 | |
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224 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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225 : _base (base), |
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226 _index(index.register_or_noreg()), |
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227 _scale(scale), |
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228 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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229 if (!index.is_register()) scale = Address::no_scale; |
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230 assert(!_index->is_valid() == (scale == Address::no_scale), |
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231 "inconsistent address"); |
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232 } |
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233 |
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234 Address plus_disp(int disp) const { |
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235 Address a = (*this); |
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236 a._disp += disp; |
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237 return a; |
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238 } |
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239 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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240 Address a = (*this); |
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241 a._disp += disp.constant_or_zero() * scale_size(scale); |
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242 if (disp.is_register()) { |
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243 assert(!a.index()->is_valid(), "competing indexes"); |
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244 a._index = disp.as_register(); |
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245 a._scale = scale; |
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246 } |
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247 return a; |
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248 } |
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249 bool is_same_address(Address a) const { |
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250 // disregard _rspec |
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251 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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252 } |
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253 |
0 | 254 // The following two overloads are used in connection with the |
255 // ByteSize type (see sizes.hpp). They simplify the use of | |
256 // ByteSize'd arguments in assembly code. Note that their equivalent | |
257 // for the optimized build are the member functions with int disp | |
258 // argument since ByteSize is mapped to an int type in that case. | |
259 // | |
260 // Note: DO NOT introduce similar overloaded functions for WordSize | |
261 // arguments as in the optimized mode, both ByteSize and WordSize | |
262 // are mapped to the same type and thus the compiler cannot make a | |
263 // distinction anymore (=> compiler errors). | |
264 | |
265 #ifdef ASSERT | |
266 Address(Register base, ByteSize disp) | |
267 : _base(base), | |
268 _index(noreg), | |
269 _scale(no_scale), | |
270 _disp(in_bytes(disp)) { | |
271 } | |
272 | |
273 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
274 : _base(base), | |
275 _index(index), | |
276 _scale(scale), | |
277 _disp(in_bytes(disp)) { | |
278 assert(!index->is_valid() == (scale == Address::no_scale), | |
279 "inconsistent address"); | |
280 } | |
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281 |
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282 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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283 : _base (base), |
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284 _index(index.register_or_noreg()), |
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285 _scale(scale), |
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286 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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287 if (!index.is_register()) scale = Address::no_scale; |
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288 assert(!_index->is_valid() == (scale == Address::no_scale), |
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289 "inconsistent address"); |
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290 } |
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291 |
0 | 292 #endif // ASSERT |
293 | |
294 // accessors | |
342
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295 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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296 Register base() const { return _base; } |
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297 Register index() const { return _index; } |
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298 ScaleFactor scale() const { return _scale; } |
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299 int disp() const { return _disp; } |
0 | 300 |
301 // Convert the raw encoding form into the form expected by the constructor for | |
302 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
303 // that to noreg for the Address constructor. | |
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304 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
0 | 305 |
306 static Address make_array(ArrayAddress); | |
307 | |
308 private: | |
309 bool base_needs_rex() const { | |
310 return _base != noreg && _base->encoding() >= 8; | |
311 } | |
312 | |
313 bool index_needs_rex() const { | |
314 return _index != noreg &&_index->encoding() >= 8; | |
315 } | |
316 | |
317 relocInfo::relocType reloc() const { return _rspec.type(); } | |
318 | |
319 friend class Assembler; | |
320 friend class MacroAssembler; | |
321 friend class LIR_Assembler; // base/index/scale/disp | |
322 }; | |
323 | |
324 // | |
325 // AddressLiteral has been split out from Address because operands of this type | |
326 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
327 // the few instructions that need to deal with address literals are unique and the | |
328 // MacroAssembler does not have to implement every instruction in the Assembler | |
329 // in order to search for address literals that may need special handling depending | |
330 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
331 // directories. | |
332 // | |
333 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
334 friend class ArrayAddress; | |
335 RelocationHolder _rspec; | |
336 // Typically we use AddressLiterals we want to use their rval | |
337 // However in some situations we want the lval (effect address) of the item. | |
338 // We provide a special factory for making those lvals. | |
339 bool _is_lval; | |
340 | |
341 // If the target is far we'll need to load the ea of this to | |
342 // a register to reach it. Otherwise if near we can do rip | |
343 // relative addressing. | |
344 | |
345 address _target; | |
346 | |
347 protected: | |
348 // creation | |
349 AddressLiteral() | |
350 : _is_lval(false), | |
351 _target(NULL) | |
352 {} | |
353 | |
354 public: | |
355 | |
356 | |
357 AddressLiteral(address target, relocInfo::relocType rtype); | |
358 | |
359 AddressLiteral(address target, RelocationHolder const& rspec) | |
360 : _rspec(rspec), | |
361 _is_lval(false), | |
362 _target(target) | |
363 {} | |
364 | |
365 AddressLiteral addr() { | |
366 AddressLiteral ret = *this; | |
367 ret._is_lval = true; | |
368 return ret; | |
369 } | |
370 | |
371 | |
372 private: | |
373 | |
374 address target() { return _target; } | |
375 bool is_lval() { return _is_lval; } | |
376 | |
377 relocInfo::relocType reloc() const { return _rspec.type(); } | |
378 const RelocationHolder& rspec() const { return _rspec; } | |
379 | |
380 friend class Assembler; | |
381 friend class MacroAssembler; | |
382 friend class Address; | |
383 friend class LIR_Assembler; | |
384 }; | |
385 | |
386 // Convience classes | |
387 class RuntimeAddress: public AddressLiteral { | |
388 | |
389 public: | |
390 | |
391 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
392 | |
393 }; | |
394 | |
395 class ExternalAddress: public AddressLiteral { | |
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396 private: |
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397 static relocInfo::relocType reloc_for_target(address target) { |
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398 // Sometimes ExternalAddress is used for values which aren't |
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399 // exactly addresses, like the card table base. |
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400 // external_word_type can't be used for values in the first page |
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401 // so just skip the reloc in that case. |
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402 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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403 } |
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404 |
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405 public: |
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406 |
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407 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
0 | 408 |
409 }; | |
410 | |
411 class InternalAddress: public AddressLiteral { | |
412 | |
413 public: | |
414 | |
415 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
416 | |
417 }; | |
418 | |
419 // x86 can do array addressing as a single operation since disp can be an absolute | |
420 // address amd64 can't. We create a class that expresses the concept but does extra | |
421 // magic on amd64 to get the final result | |
422 | |
423 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
424 private: | |
425 | |
426 AddressLiteral _base; | |
427 Address _index; | |
428 | |
429 public: | |
430 | |
431 ArrayAddress() {}; | |
432 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
433 AddressLiteral base() { return _base; } | |
434 Address index() { return _index; } | |
435 | |
436 }; | |
437 | |
304 | 438 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
0 | 439 |
440 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
441 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
442 // is what you get. The Assembler is generating code into a CodeBuffer. | |
443 | |
444 class Assembler : public AbstractAssembler { | |
445 friend class AbstractAssembler; // for the non-virtual hack | |
446 friend class LIR_Assembler; // as_Address() | |
304 | 447 friend class StubGenerator; |
0 | 448 |
449 public: | |
450 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
451 zero = 0x4, | |
452 notZero = 0x5, | |
453 equal = 0x4, | |
454 notEqual = 0x5, | |
455 less = 0xc, | |
456 lessEqual = 0xe, | |
457 greater = 0xf, | |
458 greaterEqual = 0xd, | |
459 below = 0x2, | |
460 belowEqual = 0x6, | |
461 above = 0x7, | |
462 aboveEqual = 0x3, | |
463 overflow = 0x0, | |
464 noOverflow = 0x1, | |
465 carrySet = 0x2, | |
466 carryClear = 0x3, | |
467 negative = 0x8, | |
468 positive = 0x9, | |
469 parity = 0xa, | |
470 noParity = 0xb | |
471 }; | |
472 | |
473 enum Prefix { | |
474 // segment overrides | |
475 CS_segment = 0x2e, | |
476 SS_segment = 0x36, | |
477 DS_segment = 0x3e, | |
478 ES_segment = 0x26, | |
479 FS_segment = 0x64, | |
480 GS_segment = 0x65, | |
481 | |
482 REX = 0x40, | |
483 | |
484 REX_B = 0x41, | |
485 REX_X = 0x42, | |
486 REX_XB = 0x43, | |
487 REX_R = 0x44, | |
488 REX_RB = 0x45, | |
489 REX_RX = 0x46, | |
490 REX_RXB = 0x47, | |
491 | |
492 REX_W = 0x48, | |
493 | |
494 REX_WB = 0x49, | |
495 REX_WX = 0x4A, | |
496 REX_WXB = 0x4B, | |
497 REX_WR = 0x4C, | |
498 REX_WRB = 0x4D, | |
499 REX_WRX = 0x4E, | |
4759 | 500 REX_WRXB = 0x4F, |
501 | |
502 VEX_3bytes = 0xC4, | |
503 VEX_2bytes = 0xC5 | |
504 }; | |
505 | |
506 enum VexPrefix { | |
507 VEX_B = 0x20, | |
508 VEX_X = 0x40, | |
509 VEX_R = 0x80, | |
510 VEX_W = 0x80 | |
511 }; | |
512 | |
513 enum VexSimdPrefix { | |
514 VEX_SIMD_NONE = 0x0, | |
515 VEX_SIMD_66 = 0x1, | |
516 VEX_SIMD_F3 = 0x2, | |
517 VEX_SIMD_F2 = 0x3 | |
518 }; | |
519 | |
520 enum VexOpcode { | |
521 VEX_OPCODE_NONE = 0x0, | |
522 VEX_OPCODE_0F = 0x1, | |
523 VEX_OPCODE_0F_38 = 0x2, | |
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524 VEX_OPCODE_0F_3A = 0x3, |
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525 VEX_OPCODE_MASK = 0x1F |
0 | 526 }; |
527 | |
528 enum WhichOperand { | |
529 // input to locate_operand, and format code for relocations | |
304 | 530 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
0 | 531 disp32_operand = 1, // embedded 32-bit displacement or address |
532 call32_operand = 2, // embedded 32-bit self-relative displacement | |
304 | 533 #ifndef _LP64 |
0 | 534 _WhichOperand_limit = 3 |
304 | 535 #else |
536 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
537 _WhichOperand_limit = 4 | |
538 #endif | |
0 | 539 }; |
540 | |
304 | 541 |
542 | |
543 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
544 // of instructions are freely declared without the need for wrapping them an ifdef. | |
545 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
546 // In the .cpp file the implementations are wrapped so that they are dropped out | |
7951 | 547 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL |
304 | 548 // to the size it was prior to merging up the 32bit and 64bit assemblers. |
549 // | |
550 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
551 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
552 | |
553 private: | |
554 | |
555 | |
556 // 64bit prefixes | |
557 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
558 int prefixq_and_encode(int reg_enc); | |
559 | |
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560 int prefix_and_encode(int dst_enc, int src_enc) { |
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561 return prefix_and_encode(dst_enc, false, src_enc, false); |
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562 } |
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563 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); |
304 | 564 int prefixq_and_encode(int dst_enc, int src_enc); |
565 | |
566 void prefix(Register reg); | |
567 void prefix(Address adr); | |
568 void prefixq(Address adr); | |
569 | |
570 void prefix(Address adr, Register reg, bool byteinst = false); | |
4759 | 571 void prefix(Address adr, XMMRegister reg); |
304 | 572 void prefixq(Address adr, Register reg); |
4759 | 573 void prefixq(Address adr, XMMRegister reg); |
304 | 574 |
575 void prefetch_prefix(Address src); | |
576 | |
4759 | 577 void rex_prefix(Address adr, XMMRegister xreg, |
578 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
579 int rex_prefix_and_encode(int dst_enc, int src_enc, | |
580 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
581 | |
582 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, | |
583 int nds_enc, VexSimdPrefix pre, VexOpcode opc, | |
584 bool vector256); | |
585 | |
586 void vex_prefix(Address adr, int nds_enc, int xreg_enc, | |
587 VexSimdPrefix pre, VexOpcode opc, | |
588 bool vex_w, bool vector256); | |
589 | |
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590 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
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591 VexSimdPrefix pre, bool vector256 = false) { |
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592 int dst_enc = dst->encoding(); |
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593 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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594 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); |
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595 } |
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596 |
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597 void vex_prefix_0F38(Register dst, Register nds, Address src) { |
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598 bool vex_w = false; |
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599 bool vector256 = false; |
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600 vex_prefix(src, nds->encoding(), dst->encoding(), |
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601 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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602 } |
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603 |
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604 void vex_prefix_0F38_q(Register dst, Register nds, Address src) { |
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605 bool vex_w = true; |
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606 bool vector256 = false; |
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607 vex_prefix(src, nds->encoding(), dst->encoding(), |
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608 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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609 } |
4759 | 610 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
611 VexSimdPrefix pre, VexOpcode opc, | |
612 bool vex_w, bool vector256); | |
613 | |
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614 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) { |
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615 bool vex_w = false; |
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616 bool vector256 = false; |
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617 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
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618 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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619 } |
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620 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) { |
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621 bool vex_w = true; |
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622 bool vector256 = false; |
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623 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
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624 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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625 } |
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626 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
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627 VexSimdPrefix pre, bool vector256 = false, |
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628 VexOpcode opc = VEX_OPCODE_0F) { |
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629 int src_enc = src->encoding(); |
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630 int dst_enc = dst->encoding(); |
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631 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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632 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); |
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633 } |
4759 | 634 |
635 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, | |
636 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
637 bool rex_w = false, bool vector256 = false); | |
638 | |
639 void simd_prefix(XMMRegister dst, Address src, | |
640 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
641 simd_prefix(dst, xnoreg, src, pre, opc); | |
642 } | |
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643 |
4759 | 644 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
645 simd_prefix(src, dst, pre); | |
646 } | |
647 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, | |
648 VexSimdPrefix pre) { | |
649 bool rex_w = true; | |
650 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); | |
651 } | |
652 | |
653 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, | |
654 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
655 bool rex_w = false, bool vector256 = false); | |
656 | |
657 // Move/convert 32-bit integer value. | |
658 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, | |
659 VexSimdPrefix pre) { | |
660 // It is OK to cast from Register to XMMRegister to pass argument here | |
661 // since only encoding is used in simd_prefix_and_encode() and number of | |
662 // Gen and Xmm registers are the same. | |
663 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); | |
664 } | |
665 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
666 return simd_prefix_and_encode(dst, xnoreg, src, pre); | |
667 } | |
668 int simd_prefix_and_encode(Register dst, XMMRegister src, | |
669 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
670 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); | |
671 } | |
672 | |
673 // Move/convert 64-bit integer value. | |
674 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, | |
675 VexSimdPrefix pre) { | |
676 bool rex_w = true; | |
677 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); | |
678 } | |
679 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
680 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); | |
681 } | |
682 int simd_prefix_and_encode_q(Register dst, XMMRegister src, | |
683 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
684 bool rex_w = true; | |
685 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); | |
686 } | |
687 | |
304 | 688 // Helper functions for groups of instructions |
689 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
690 | |
691 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
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692 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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693 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
304 | 694 void emit_arith(int op1, int op2, Register dst, Register src); |
695 | |
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696 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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697 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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698 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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699 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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700 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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701 Address src, VexSimdPrefix pre, bool vector256); |
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702 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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703 XMMRegister src, VexSimdPrefix pre, bool vector256); |
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704 |
304 | 705 void emit_operand(Register reg, |
706 Register base, Register index, Address::ScaleFactor scale, | |
707 int disp, | |
708 RelocationHolder const& rspec, | |
709 int rip_relative_correction = 0); | |
710 | |
711 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
712 | |
713 // operands that only take the original 32bit registers | |
714 void emit_operand32(Register reg, Address adr); | |
715 | |
716 void emit_operand(XMMRegister reg, | |
717 Register base, Register index, Address::ScaleFactor scale, | |
718 int disp, | |
719 RelocationHolder const& rspec); | |
720 | |
721 void emit_operand(XMMRegister reg, Address adr); | |
722 | |
723 void emit_operand(MMXRegister reg, Address adr); | |
724 | |
725 // workaround gcc (3.2.1-7) bug | |
726 void emit_operand(Address adr, MMXRegister reg); | |
727 | |
728 | |
729 // Immediate-to-memory forms | |
730 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
731 | |
732 void emit_farith(int b1, int b2, int i); | |
733 | |
734 | |
735 protected: | |
736 #ifdef ASSERT | |
737 void check_relocation(RelocationHolder const& rspec, int format); | |
738 #endif | |
739 | |
740 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
741 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
742 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
743 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
744 | |
745 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
746 | |
747 // These are all easily abused and hence protected | |
748 | |
749 // 32BIT ONLY SECTION | |
750 #ifndef _LP64 | |
751 // Make these disappear in 64bit mode since they would never be correct | |
752 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
753 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
754 | |
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755 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
304 | 756 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
757 | |
758 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
759 #else | |
760 // 64BIT ONLY SECTION | |
761 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
642
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762 |
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763 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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764 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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765 |
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766 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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767 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
304 | 768 #endif // _LP64 |
769 | |
770 // These are unique in that we are ensured by the caller that the 32bit | |
771 // relative in these instructions will always be able to reach the potentially | |
772 // 64bit address described by entry. Since they can take a 64bit address they | |
773 // don't have the 32 suffix like the other instructions in this class. | |
774 | |
775 void call_literal(address entry, RelocationHolder const& rspec); | |
776 void jmp_literal(address entry, RelocationHolder const& rspec); | |
777 | |
778 // Avoid using directly section | |
779 // Instructions in this section are actually usable by anyone without danger | |
780 // of failure but have performance issues that are addressed my enhanced | |
781 // instructions which will do the proper thing base on the particular cpu. | |
782 // We protect them because we don't trust you... | |
783 | |
784 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
785 // could cause a partial flag stall since they don't set CF flag. | |
786 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
787 // which call inc() & dec() or add() & sub() in accordance with | |
788 // the product flag UseIncDec value. | |
789 | |
790 void decl(Register dst); | |
791 void decl(Address dst); | |
792 void decq(Register dst); | |
793 void decq(Address dst); | |
794 | |
795 void incl(Register dst); | |
796 void incl(Address dst); | |
797 void incq(Register dst); | |
798 void incq(Address dst); | |
799 | |
800 // New cpus require use of movsd and movss to avoid partial register stall | |
801 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
802 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
803 | |
804 // Move Scalar Single-Precision Floating-Point Values | |
805 void movss(XMMRegister dst, Address src); | |
806 void movss(XMMRegister dst, XMMRegister src); | |
807 void movss(Address dst, XMMRegister src); | |
808 | |
809 // Move Scalar Double-Precision Floating-Point Values | |
810 void movsd(XMMRegister dst, Address src); | |
811 void movsd(XMMRegister dst, XMMRegister src); | |
812 void movsd(Address dst, XMMRegister src); | |
813 void movlpd(XMMRegister dst, Address src); | |
814 | |
815 // New cpus require use of movaps and movapd to avoid partial register stall | |
816 // when moving between registers. | |
817 void movaps(XMMRegister dst, XMMRegister src); | |
818 void movapd(XMMRegister dst, XMMRegister src); | |
819 | |
820 // End avoid using directly | |
821 | |
822 | |
823 // Instruction prefixes | |
824 void prefix(Prefix p); | |
825 | |
0 | 826 public: |
827 | |
828 // Creation | |
829 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
830 | |
831 // Decoding | |
832 static address locate_operand(address inst, WhichOperand which); | |
833 static address locate_next_instruction(address inst); | |
834 | |
304 | 835 // Utilities |
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836 static bool is_polling_page_far() NOT_LP64({ return false;}); |
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837 |
304 | 838 // Generic instructions |
839 // Does 32bit or 64bit as needed for the platform. In some sense these | |
840 // belong in macro assembler but there is no need for both varieties to exist | |
841 | |
842 void lea(Register dst, Address src); | |
843 | |
844 void mov(Register dst, Register src); | |
845 | |
846 void pusha(); | |
847 void popa(); | |
848 | |
849 void pushf(); | |
850 void popf(); | |
851 | |
852 void push(int32_t imm32); | |
853 | |
854 void push(Register src); | |
855 | |
856 void pop(Register dst); | |
857 | |
858 // These are dummies to prevent surprise implicit conversions to Register | |
859 void push(void* v); | |
860 void pop(void* v); | |
861 | |
862 // These do register sized moves/scans | |
863 void rep_mov(); | |
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864 void rep_stos(); |
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865 void rep_stosb(); |
304 | 866 void repne_scan(); |
867 #ifdef _LP64 | |
868 void repne_scanl(); | |
869 #endif | |
870 | |
871 // Vanilla instructions in lexical order | |
872 | |
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873 void adcl(Address dst, int32_t imm32); |
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874 void adcl(Address dst, Register src); |
304 | 875 void adcl(Register dst, int32_t imm32); |
0 | 876 void adcl(Register dst, Address src); |
877 void adcl(Register dst, Register src); | |
878 | |
304 | 879 void adcq(Register dst, int32_t imm32); |
880 void adcq(Register dst, Address src); | |
881 void adcq(Register dst, Register src); | |
882 | |
883 void addl(Address dst, int32_t imm32); | |
0 | 884 void addl(Address dst, Register src); |
304 | 885 void addl(Register dst, int32_t imm32); |
0 | 886 void addl(Register dst, Address src); |
887 void addl(Register dst, Register src); | |
888 | |
304 | 889 void addq(Address dst, int32_t imm32); |
890 void addq(Address dst, Register src); | |
891 void addq(Register dst, int32_t imm32); | |
892 void addq(Register dst, Address src); | |
893 void addq(Register dst, Register src); | |
894 | |
0 | 895 void addr_nop_4(); |
896 void addr_nop_5(); | |
897 void addr_nop_7(); | |
898 void addr_nop_8(); | |
899 | |
304 | 900 // Add Scalar Double-Precision Floating-Point Values |
901 void addsd(XMMRegister dst, Address src); | |
902 void addsd(XMMRegister dst, XMMRegister src); | |
903 | |
904 // Add Scalar Single-Precision Floating-Point Values | |
905 void addss(XMMRegister dst, Address src); | |
906 void addss(XMMRegister dst, XMMRegister src); | |
907 | |
6894 | 908 // AES instructions |
909 void aesdec(XMMRegister dst, Address src); | |
910 void aesdec(XMMRegister dst, XMMRegister src); | |
911 void aesdeclast(XMMRegister dst, Address src); | |
912 void aesdeclast(XMMRegister dst, XMMRegister src); | |
913 void aesenc(XMMRegister dst, Address src); | |
914 void aesenc(XMMRegister dst, XMMRegister src); | |
915 void aesenclast(XMMRegister dst, Address src); | |
916 void aesenclast(XMMRegister dst, XMMRegister src); | |
917 | |
918 | |
4759 | 919 void andl(Address dst, int32_t imm32); |
304 | 920 void andl(Register dst, int32_t imm32); |
921 void andl(Register dst, Address src); | |
922 void andl(Register dst, Register src); | |
923 | |
3457 | 924 void andq(Address dst, int32_t imm32); |
304 | 925 void andq(Register dst, int32_t imm32); |
926 void andq(Register dst, Address src); | |
927 void andq(Register dst, Register src); | |
928 | |
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929 // BMI instructions |
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930 void andnl(Register dst, Register src1, Register src2); |
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931 void andnl(Register dst, Register src1, Address src2); |
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932 void andnq(Register dst, Register src1, Register src2); |
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933 void andnq(Register dst, Register src1, Address src2); |
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934 |
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935 void blsil(Register dst, Register src); |
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936 void blsil(Register dst, Address src); |
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937 void blsiq(Register dst, Register src); |
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938 void blsiq(Register dst, Address src); |
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939 |
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940 void blsmskl(Register dst, Register src); |
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941 void blsmskl(Register dst, Address src); |
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942 void blsmskq(Register dst, Register src); |
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943 void blsmskq(Register dst, Address src); |
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944 |
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945 void blsrl(Register dst, Register src); |
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946 void blsrl(Register dst, Address src); |
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947 void blsrq(Register dst, Register src); |
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948 void blsrq(Register dst, Address src); |
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949 |
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950 void bsfl(Register dst, Register src); |
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951 void bsrl(Register dst, Register src); |
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952 |
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953 #ifdef _LP64 |
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954 void bsfq(Register dst, Register src); |
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955 void bsrq(Register dst, Register src); |
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956 #endif |
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957 |
304 | 958 void bswapl(Register reg); |
959 | |
960 void bswapq(Register reg); | |
961 | |
0 | 962 void call(Label& L, relocInfo::relocType rtype); |
963 void call(Register reg); // push pc; pc <- reg | |
964 void call(Address adr); // push pc; pc <- adr | |
965 | |
304 | 966 void cdql(); |
967 | |
968 void cdqq(); | |
969 | |
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970 void cld(); |
304 | 971 |
972 void clflush(Address adr); | |
973 | |
974 void cmovl(Condition cc, Register dst, Register src); | |
975 void cmovl(Condition cc, Register dst, Address src); | |
976 | |
977 void cmovq(Condition cc, Register dst, Register src); | |
978 void cmovq(Condition cc, Register dst, Address src); | |
979 | |
980 | |
981 void cmpb(Address dst, int imm8); | |
982 | |
983 void cmpl(Address dst, int32_t imm32); | |
984 | |
985 void cmpl(Register dst, int32_t imm32); | |
986 void cmpl(Register dst, Register src); | |
987 void cmpl(Register dst, Address src); | |
988 | |
989 void cmpq(Address dst, int32_t imm32); | |
990 void cmpq(Address dst, Register src); | |
991 | |
992 void cmpq(Register dst, int32_t imm32); | |
993 void cmpq(Register dst, Register src); | |
994 void cmpq(Register dst, Address src); | |
995 | |
996 // these are dummies used to catch attempting to convert NULL to Register | |
997 void cmpl(Register dst, void* junk); // dummy | |
998 void cmpq(Register dst, void* junk); // dummy | |
999 | |
1000 void cmpw(Address dst, int imm16); | |
1001 | |
1002 void cmpxchg8 (Address adr); | |
1003 | |
1004 void cmpxchgl(Register reg, Address adr); | |
1005 | |
1006 void cmpxchgq(Register reg, Address adr); | |
1007 | |
1008 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1009 void comisd(XMMRegister dst, Address src); | |
4759 | 1010 void comisd(XMMRegister dst, XMMRegister src); |
304 | 1011 |
1012 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
1013 void comiss(XMMRegister dst, Address src); | |
4759 | 1014 void comiss(XMMRegister dst, XMMRegister src); |
304 | 1015 |
1016 // Identify processor type and features | |
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1017 void cpuid(); |
304 | 1018 |
1019 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
1020 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
4759 | 1021 void cvtsd2ss(XMMRegister dst, Address src); |
304 | 1022 |
1023 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
1024 void cvtsi2sdl(XMMRegister dst, Register src); | |
4759 | 1025 void cvtsi2sdl(XMMRegister dst, Address src); |
304 | 1026 void cvtsi2sdq(XMMRegister dst, Register src); |
4759 | 1027 void cvtsi2sdq(XMMRegister dst, Address src); |
304 | 1028 |
1029 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
1030 void cvtsi2ssl(XMMRegister dst, Register src); | |
4759 | 1031 void cvtsi2ssl(XMMRegister dst, Address src); |
304 | 1032 void cvtsi2ssq(XMMRegister dst, Register src); |
4759 | 1033 void cvtsi2ssq(XMMRegister dst, Address src); |
304 | 1034 |
1035 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
1036 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
1037 | |
1038 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
1039 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
1040 | |
1041 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
1042 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
4759 | 1043 void cvtss2sd(XMMRegister dst, Address src); |
304 | 1044 |
1045 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
1046 void cvttsd2sil(Register dst, Address src); | |
1047 void cvttsd2sil(Register dst, XMMRegister src); | |
1048 void cvttsd2siq(Register dst, XMMRegister src); | |
1049 | |
1050 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
1051 void cvttss2sil(Register dst, XMMRegister src); | |
1052 void cvttss2siq(Register dst, XMMRegister src); | |
1053 | |
1054 // Divide Scalar Double-Precision Floating-Point Values | |
1055 void divsd(XMMRegister dst, Address src); | |
1056 void divsd(XMMRegister dst, XMMRegister src); | |
1057 | |
1058 // Divide Scalar Single-Precision Floating-Point Values | |
1059 void divss(XMMRegister dst, Address src); | |
1060 void divss(XMMRegister dst, XMMRegister src); | |
1061 | |
1062 void emms(); | |
1063 | |
1064 void fabs(); | |
1065 | |
1066 void fadd(int i); | |
1067 | |
1068 void fadd_d(Address src); | |
1069 void fadd_s(Address src); | |
1070 | |
1071 // "Alternate" versions of x87 instructions place result down in FPU | |
1072 // stack instead of on TOS | |
1073 | |
1074 void fadda(int i); // "alternate" fadd | |
1075 void faddp(int i = 1); | |
1076 | |
1077 void fchs(); | |
1078 | |
1079 void fcom(int i); | |
1080 | |
1081 void fcomp(int i = 1); | |
1082 void fcomp_d(Address src); | |
1083 void fcomp_s(Address src); | |
1084 | |
1085 void fcompp(); | |
1086 | |
1087 void fcos(); | |
1088 | |
1089 void fdecstp(); | |
1090 | |
1091 void fdiv(int i); | |
1092 void fdiv_d(Address src); | |
1093 void fdivr_s(Address src); | |
1094 void fdiva(int i); // "alternate" fdiv | |
1095 void fdivp(int i = 1); | |
1096 | |
1097 void fdivr(int i); | |
1098 void fdivr_d(Address src); | |
1099 void fdiv_s(Address src); | |
1100 | |
1101 void fdivra(int i); // "alternate" reversed fdiv | |
1102 | |
1103 void fdivrp(int i = 1); | |
1104 | |
1105 void ffree(int i = 0); | |
1106 | |
1107 void fild_d(Address adr); | |
1108 void fild_s(Address adr); | |
1109 | |
1110 void fincstp(); | |
1111 | |
1112 void finit(); | |
1113 | |
1114 void fist_s (Address adr); | |
1115 void fistp_d(Address adr); | |
1116 void fistp_s(Address adr); | |
1117 | |
1118 void fld1(); | |
1119 | |
1120 void fld_d(Address adr); | |
1121 void fld_s(Address adr); | |
1122 void fld_s(int index); | |
1123 void fld_x(Address adr); // extended-precision (80-bit) format | |
1124 | |
1125 void fldcw(Address src); | |
1126 | |
1127 void fldenv(Address src); | |
1128 | |
1129 void fldlg2(); | |
1130 | |
1131 void fldln2(); | |
1132 | |
1133 void fldz(); | |
1134 | |
1135 void flog(); | |
1136 void flog10(); | |
1137 | |
1138 void fmul(int i); | |
1139 | |
1140 void fmul_d(Address src); | |
1141 void fmul_s(Address src); | |
1142 | |
1143 void fmula(int i); // "alternate" fmul | |
1144 | |
1145 void fmulp(int i = 1); | |
1146 | |
1147 void fnsave(Address dst); | |
1148 | |
1149 void fnstcw(Address src); | |
1150 | |
1151 void fnstsw_ax(); | |
1152 | |
1153 void fprem(); | |
1154 void fprem1(); | |
1155 | |
1156 void frstor(Address src); | |
1157 | |
1158 void fsin(); | |
1159 | |
1160 void fsqrt(); | |
1161 | |
1162 void fst_d(Address adr); | |
1163 void fst_s(Address adr); | |
1164 | |
1165 void fstp_d(Address adr); | |
1166 void fstp_d(int index); | |
1167 void fstp_s(Address adr); | |
1168 void fstp_x(Address adr); // extended-precision (80-bit) format | |
1169 | |
1170 void fsub(int i); | |
1171 void fsub_d(Address src); | |
1172 void fsub_s(Address src); | |
1173 | |
1174 void fsuba(int i); // "alternate" fsub | |
1175 | |
1176 void fsubp(int i = 1); | |
1177 | |
1178 void fsubr(int i); | |
1179 void fsubr_d(Address src); | |
1180 void fsubr_s(Address src); | |
1181 | |
1182 void fsubra(int i); // "alternate" reversed fsub | |
1183 | |
1184 void fsubrp(int i = 1); | |
1185 | |
1186 void ftan(); | |
1187 | |
1188 void ftst(); | |
1189 | |
1190 void fucomi(int i = 1); | |
1191 void fucomip(int i = 1); | |
1192 | |
1193 void fwait(); | |
1194 | |
1195 void fxch(int i = 1); | |
1196 | |
1197 void fxrstor(Address src); | |
1198 | |
1199 void fxsave(Address dst); | |
1200 | |
1201 void fyl2x(); | |
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1202 void frndint(); |
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1203 void f2xm1(); |
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1204 void fldl2e(); |
304 | 1205 |
1206 void hlt(); | |
1207 | |
1208 void idivl(Register src); | |
1920 | 1209 void divl(Register src); // Unsigned division |
304 | 1210 |
1211 void idivq(Register src); | |
1212 | |
1213 void imull(Register dst, Register src); | |
1214 void imull(Register dst, Register src, int value); | |
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1215 void imull(Register dst, Address src); |
304 | 1216 |
1217 void imulq(Register dst, Register src); | |
1218 void imulq(Register dst, Register src, int value); | |
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1219 #ifdef _LP64 |
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1220 void imulq(Register dst, Address src); |
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1221 #endif |
304 | 1222 |
0 | 1223 |
1224 // jcc is the generic conditional branch generator to run- | |
1225 // time routines, jcc is used for branches to labels. jcc | |
1226 // takes a branch opcode (cc) and a label (L) and generates | |
1227 // either a backward branch or a forward branch and links it | |
1228 // to the label fixup chain. Usage: | |
1229 // | |
1230 // Label L; // unbound label | |
1231 // jcc(cc, L); // forward branch to unbound label | |
1232 // bind(L); // bind label to the current pc | |
1233 // jcc(cc, L); // backward branch to bound label | |
1234 // bind(L); // illegal: a label may be bound only once | |
1235 // | |
1236 // Note: The same Label can be used for forward and backward branches | |
1237 // but it may be bound only once. | |
1238 | |
3851 | 1239 void jcc(Condition cc, Label& L, bool maybe_short = true); |
0 | 1240 |
1241 // Conditional jump to a 8-bit offset to L. | |
1242 // WARNING: be very careful using this for forward jumps. If the label is | |
1243 // not bound within an 8-bit offset of this instruction, a run-time error | |
1244 // will occur. | |
1245 void jccb(Condition cc, Label& L); | |
1246 | |
304 | 1247 void jmp(Address entry); // pc <- entry |
1248 | |
1249 // Label operations & relative jumps (PPUM Appendix D) | |
3851 | 1250 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
304 | 1251 |
1252 void jmp(Register entry); // pc <- entry | |
1253 | |
1254 // Unconditional 8-bit offset jump to L. | |
1255 // WARNING: be very careful using this for forward jumps. If the label is | |
1256 // not bound within an 8-bit offset of this instruction, a run-time error | |
1257 // will occur. | |
1258 void jmpb(Label& L); | |
1259 | |
1260 void ldmxcsr( Address src ); | |
1261 | |
1262 void leal(Register dst, Address src); | |
1263 | |
1264 void leaq(Register dst, Address src); | |
1265 | |
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1266 void lfence(); |
304 | 1267 |
1268 void lock(); | |
1269 | |
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1270 void lzcntl(Register dst, Register src); |
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1271 |
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1272 #ifdef _LP64 |
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1273 void lzcntq(Register dst, Register src); |
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1274 #endif |
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1275 |
304 | 1276 enum Membar_mask_bits { |
1277 StoreStore = 1 << 3, | |
1278 LoadStore = 1 << 2, | |
1279 StoreLoad = 1 << 1, | |
1280 LoadLoad = 1 << 0 | |
1281 }; | |
1282 | |
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1283 // Serializes memory and blows flags |
304 | 1284 void membar(Membar_mask_bits order_constraint) { |
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1285 if (os::is_MP()) { |
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1286 // We only have to handle StoreLoad |
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1287 if (order_constraint & StoreLoad) { |
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1288 // All usable chips support "locked" instructions which suffice |
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1289 // as barriers, and are much faster than the alternative of |
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1290 // using cpuid instruction. We use here a locked add [esp],0. |
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1291 // This is conveniently otherwise a no-op except for blowing |
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1292 // flags. |
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1293 // Any change to this code may need to revisit other places in |
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1294 // the code where this idiom is used, in particular the |
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1295 // orderAccess code. |
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1296 lock(); |
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1297 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1298 } |
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1299 } |
304 | 1300 } |
1301 | |
1302 void mfence(); | |
1303 | |
1304 // Moves | |
1305 | |
1306 void mov64(Register dst, int64_t imm64); | |
1307 | |
1308 void movb(Address dst, Register src); | |
1309 void movb(Address dst, int imm8); | |
1310 void movb(Register dst, Address src); | |
1311 | |
1312 void movdl(XMMRegister dst, Register src); | |
1313 void movdl(Register dst, XMMRegister src); | |
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1314 void movdl(XMMRegister dst, Address src); |
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1315 void movdl(Address dst, XMMRegister src); |
304 | 1316 |
1317 // Move Double Quadword | |
1318 void movdq(XMMRegister dst, Register src); | |
1319 void movdq(Register dst, XMMRegister src); | |
1320 | |
1321 // Move Aligned Double Quadword | |
1322 void movdqa(XMMRegister dst, XMMRegister src); | |
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1323 void movdqa(XMMRegister dst, Address src); |
304 | 1324 |
405 | 1325 // Move Unaligned Double Quadword |
1326 void movdqu(Address dst, XMMRegister src); | |
1327 void movdqu(XMMRegister dst, Address src); | |
1328 void movdqu(XMMRegister dst, XMMRegister src); | |
1329 | |
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1330 // Move Unaligned 256bit Vector |
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1331 void vmovdqu(Address dst, XMMRegister src); |
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1332 void vmovdqu(XMMRegister dst, Address src); |
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1333 void vmovdqu(XMMRegister dst, XMMRegister src); |
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1334 |
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1335 // Move lower 64bit to high 64bit in 128bit register |
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1336 void movlhps(XMMRegister dst, XMMRegister src); |
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1337 |
304 | 1338 void movl(Register dst, int32_t imm32); |
1339 void movl(Address dst, int32_t imm32); | |
1340 void movl(Register dst, Register src); | |
1341 void movl(Register dst, Address src); | |
1342 void movl(Address dst, Register src); | |
1343 | |
1344 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
1345 // by giving the compiler two choices it can't resolve | |
1346 | |
1347 void movl(Address dst, void* junk); | |
1348 void movl(Register dst, void* junk); | |
1349 | |
1350 #ifdef _LP64 | |
1351 void movq(Register dst, Register src); | |
1352 void movq(Register dst, Address src); | |
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1353 void movq(Address dst, Register src); |
304 | 1354 #endif |
1355 | |
1356 void movq(Address dst, MMXRegister src ); | |
1357 void movq(MMXRegister dst, Address src ); | |
1358 | |
1359 #ifdef _LP64 | |
1360 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
1361 // by giving the compiler two choices it can't resolve | |
1362 | |
1363 void movq(Address dst, void* dummy); | |
1364 void movq(Register dst, void* dummy); | |
1365 #endif | |
1366 | |
1367 // Move Quadword | |
1368 void movq(Address dst, XMMRegister src); | |
1369 void movq(XMMRegister dst, Address src); | |
1370 | |
1371 void movsbl(Register dst, Address src); | |
1372 void movsbl(Register dst, Register src); | |
1373 | |
1374 #ifdef _LP64 | |
624 | 1375 void movsbq(Register dst, Address src); |
1376 void movsbq(Register dst, Register src); | |
1377 | |
304 | 1378 // Move signed 32bit immediate to 64bit extending sign |
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1379 void movslq(Address dst, int32_t imm64); |
304 | 1380 void movslq(Register dst, int32_t imm64); |
1381 | |
1382 void movslq(Register dst, Address src); | |
1383 void movslq(Register dst, Register src); | |
1384 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
1385 #endif | |
1386 | |
1387 void movswl(Register dst, Address src); | |
1388 void movswl(Register dst, Register src); | |
1389 | |
624 | 1390 #ifdef _LP64 |
1391 void movswq(Register dst, Address src); | |
1392 void movswq(Register dst, Register src); | |
1393 #endif | |
1394 | |
304 | 1395 void movw(Address dst, int imm16); |
1396 void movw(Register dst, Address src); | |
1397 void movw(Address dst, Register src); | |
1398 | |
1399 void movzbl(Register dst, Address src); | |
1400 void movzbl(Register dst, Register src); | |
1401 | |
624 | 1402 #ifdef _LP64 |
1403 void movzbq(Register dst, Address src); | |
1404 void movzbq(Register dst, Register src); | |
1405 #endif | |
1406 | |
304 | 1407 void movzwl(Register dst, Address src); |
1408 void movzwl(Register dst, Register src); | |
1409 | |
624 | 1410 #ifdef _LP64 |
1411 void movzwq(Register dst, Address src); | |
1412 void movzwq(Register dst, Register src); | |
1413 #endif | |
1414 | |
304 | 1415 void mull(Address src); |
1416 void mull(Register src); | |
1417 | |
1418 // Multiply Scalar Double-Precision Floating-Point Values | |
1419 void mulsd(XMMRegister dst, Address src); | |
1420 void mulsd(XMMRegister dst, XMMRegister src); | |
1421 | |
1422 // Multiply Scalar Single-Precision Floating-Point Values | |
1423 void mulss(XMMRegister dst, Address src); | |
1424 void mulss(XMMRegister dst, XMMRegister src); | |
1425 | |
1426 void negl(Register dst); | |
1427 | |
1428 #ifdef _LP64 | |
1429 void negq(Register dst); | |
1430 #endif | |
1431 | |
1432 void nop(int i = 1); | |
1433 | |
1434 void notl(Register dst); | |
1435 | |
1436 #ifdef _LP64 | |
1437 void notq(Register dst); | |
1438 #endif | |
1439 | |
1440 void orl(Address dst, int32_t imm32); | |
1441 void orl(Register dst, int32_t imm32); | |
1442 void orl(Register dst, Address src); | |
1443 void orl(Register dst, Register src); | |
1444 | |
1445 void orq(Address dst, int32_t imm32); | |
1446 void orq(Register dst, int32_t imm32); | |
1447 void orq(Register dst, Address src); | |
1448 void orq(Register dst, Register src); | |
1449 | |
4759 | 1450 // Pack with unsigned saturation |
1451 void packuswb(XMMRegister dst, XMMRegister src); | |
1452 void packuswb(XMMRegister dst, Address src); | |
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1453 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1454 |
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1455 // Pemutation of 64bit words |
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1456 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); |
4759 | 1457 |
17780 | 1458 void pause(); |
1459 | |
681 | 1460 // SSE4.2 string instructions |
1461 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
1462 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
1463 | |
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1464 // SSE 4.1 extract |
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1465 void pextrd(Register dst, XMMRegister src, int imm8); |
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1466 void pextrq(Register dst, XMMRegister src, int imm8); |
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1467 |
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1468 // SSE 4.1 insert |
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1469 void pinsrd(XMMRegister dst, Register src, int imm8); |
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1470 void pinsrq(XMMRegister dst, Register src, int imm8); |
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1471 |
4759 | 1472 // SSE4.1 packed move |
1473 void pmovzxbw(XMMRegister dst, XMMRegister src); | |
1474 void pmovzxbw(XMMRegister dst, Address src); | |
1475 | |
1060 | 1476 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1477 void popl(Address dst); |
1060 | 1478 #endif |
304 | 1479 |
1480 #ifdef _LP64 | |
1481 void popq(Address dst); | |
1482 #endif | |
1483 | |
643
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1484 void popcntl(Register dst, Address src); |
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1485 void popcntl(Register dst, Register src); |
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1486 |
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1487 #ifdef _LP64 |
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1488 void popcntq(Register dst, Address src); |
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1489 void popcntq(Register dst, Register src); |
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1490 #endif |
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1491 |
304 | 1492 // Prefetches (SSE, SSE2, 3DNOW only) |
1493 | |
1494 void prefetchnta(Address src); | |
1495 void prefetchr(Address src); | |
1496 void prefetcht0(Address src); | |
1497 void prefetcht1(Address src); | |
1498 void prefetcht2(Address src); | |
1499 void prefetchw(Address src); | |
1500 | |
6894 | 1501 // Shuffle Bytes |
1502 void pshufb(XMMRegister dst, XMMRegister src); | |
1503 void pshufb(XMMRegister dst, Address src); | |
1504 | |
304 | 1505 // Shuffle Packed Doublewords |
1506 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
1507 void pshufd(XMMRegister dst, Address src, int mode); | |
1508 | |
1509 // Shuffle Packed Low Words | |
1510 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
1511 void pshuflw(XMMRegister dst, Address src, int mode); | |
1512 | |
2320
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1513 // Shift Right by bytes Logical DoubleQuadword Immediate |
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1514 void psrldq(XMMRegister dst, int shift); |
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1515 |
7477
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1516 // Logical Compare 128bit |
681 | 1517 void ptest(XMMRegister dst, XMMRegister src); |
1518 void ptest(XMMRegister dst, Address src); | |
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1519 // Logical Compare 256bit |
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1520 void vptest(XMMRegister dst, XMMRegister src); |
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1521 void vptest(XMMRegister dst, Address src); |
681 | 1522 |
304 | 1523 // Interleave Low Bytes |
1524 void punpcklbw(XMMRegister dst, XMMRegister src); | |
4759 | 1525 void punpcklbw(XMMRegister dst, Address src); |
1526 | |
1527 // Interleave Low Doublewords | |
1528 void punpckldq(XMMRegister dst, XMMRegister src); | |
1529 void punpckldq(XMMRegister dst, Address src); | |
304 | 1530 |
6225 | 1531 // Interleave Low Quadwords |
1532 void punpcklqdq(XMMRegister dst, XMMRegister src); | |
1533 | |
1060 | 1534 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1535 void pushl(Address src); |
1060 | 1536 #endif |
304 | 1537 |
1538 void pushq(Address src); | |
1539 | |
1540 void rcll(Register dst, int imm8); | |
1541 | |
1542 void rclq(Register dst, int imm8); | |
1543 | |
17780 | 1544 void rdtsc(); |
1545 | |
304 | 1546 void ret(int imm16); |
0 | 1547 |
1548 void sahf(); | |
1549 | |
304 | 1550 void sarl(Register dst, int imm8); |
1551 void sarl(Register dst); | |
1552 | |
1553 void sarq(Register dst, int imm8); | |
1554 void sarq(Register dst); | |
1555 | |
1556 void sbbl(Address dst, int32_t imm32); | |
1557 void sbbl(Register dst, int32_t imm32); | |
1558 void sbbl(Register dst, Address src); | |
1559 void sbbl(Register dst, Register src); | |
1560 | |
1561 void sbbq(Address dst, int32_t imm32); | |
1562 void sbbq(Register dst, int32_t imm32); | |
1563 void sbbq(Register dst, Address src); | |
1564 void sbbq(Register dst, Register src); | |
1565 | |
1566 void setb(Condition cc, Register dst); | |
1567 | |
1568 void shldl(Register dst, Register src); | |
1569 | |
1570 void shll(Register dst, int imm8); | |
1571 void shll(Register dst); | |
1572 | |
1573 void shlq(Register dst, int imm8); | |
1574 void shlq(Register dst); | |
1575 | |
1576 void shrdl(Register dst, Register src); | |
1577 | |
1578 void shrl(Register dst, int imm8); | |
1579 void shrl(Register dst); | |
1580 | |
1581 void shrq(Register dst, int imm8); | |
1582 void shrq(Register dst); | |
1583 | |
1584 void smovl(); // QQQ generic? | |
1585 | |
1586 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
1587 void sqrtsd(XMMRegister dst, Address src); | |
1588 void sqrtsd(XMMRegister dst, XMMRegister src); | |
1589 | |
2008 | 1590 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
1591 void sqrtss(XMMRegister dst, Address src); | |
1592 void sqrtss(XMMRegister dst, XMMRegister src); | |
1593 | |
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1594 void std(); |
304 | 1595 |
1596 void stmxcsr( Address dst ); | |
1597 | |
1598 void subl(Address dst, int32_t imm32); | |
1599 void subl(Address dst, Register src); | |
1600 void subl(Register dst, int32_t imm32); | |
1601 void subl(Register dst, Address src); | |
1602 void subl(Register dst, Register src); | |
1603 | |
1604 void subq(Address dst, int32_t imm32); | |
1605 void subq(Address dst, Register src); | |
1606 void subq(Register dst, int32_t imm32); | |
1607 void subq(Register dst, Address src); | |
1608 void subq(Register dst, Register src); | |
1609 | |
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1610 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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1611 void subl_imm32(Register dst, int32_t imm32); |
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1612 void subq_imm32(Register dst, int32_t imm32); |
304 | 1613 |
1614 // Subtract Scalar Double-Precision Floating-Point Values | |
1615 void subsd(XMMRegister dst, Address src); | |
0 | 1616 void subsd(XMMRegister dst, XMMRegister src); |
1617 | |
304 | 1618 // Subtract Scalar Single-Precision Floating-Point Values |
1619 void subss(XMMRegister dst, Address src); | |
1620 void subss(XMMRegister dst, XMMRegister src); | |
1621 | |
1622 void testb(Register dst, int imm8); | |
1623 | |
1624 void testl(Register dst, int32_t imm32); | |
1625 void testl(Register dst, Register src); | |
1626 void testl(Register dst, Address src); | |
1627 | |
1628 void testq(Register dst, int32_t imm32); | |
1629 void testq(Register dst, Register src); | |
1630 | |
14693
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|
1631 // BMI - count trailing zeros |
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1632 void tzcntl(Register dst, Register src); |
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1633 void tzcntq(Register dst, Register src); |
304 | 1634 |
1635 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1636 void ucomisd(XMMRegister dst, Address src); | |
0 | 1637 void ucomisd(XMMRegister dst, XMMRegister src); |
1638 | |
304 | 1639 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1640 void ucomiss(XMMRegister dst, Address src); | |
1641 void ucomiss(XMMRegister dst, XMMRegister src); | |
1642 | |
17780 | 1643 void xabort(int8_t imm8); |
1644 | |
304 | 1645 void xaddl(Address dst, Register src); |
1646 | |
1647 void xaddq(Address dst, Register src); | |
1648 | |
17780 | 1649 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); |
1650 | |
304 | 1651 void xchgl(Register reg, Address adr); |
1652 void xchgl(Register dst, Register src); | |
1653 | |
1654 void xchgq(Register reg, Address adr); | |
1655 void xchgq(Register dst, Register src); | |
1656 | |
17780 | 1657 void xend(); |
1658 | |
4759 | 1659 // Get Value of Extended Control Register |
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1660 void xgetbv(); |
4759 | 1661 |
304 | 1662 void xorl(Register dst, int32_t imm32); |
1663 void xorl(Register dst, Address src); | |
1664 void xorl(Register dst, Register src); | |
1665 | |
1666 void xorq(Register dst, Address src); | |
1667 void xorq(Register dst, Register src); | |
1668 | |
1669 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
4759 | 1670 |
6225 | 1671 // AVX 3-operands scalar instructions (encoded with VEX prefix) |
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1672 |
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1673 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
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1674 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1675 void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
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1676 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1677 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
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1678 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1679 void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
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1680 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1681 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
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1682 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1683 void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
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1684 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1685 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
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1686 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1687 void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
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1688 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1689 |
6614
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1690 |
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1691 //====================VECTOR ARITHMETIC===================================== |
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1692 |
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1693 // Add Packed Floating-Point Values |
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1694 void addpd(XMMRegister dst, XMMRegister src); |
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1695 void addps(XMMRegister dst, XMMRegister src); |
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1696 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1697 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1698 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1699 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1700 |
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1701 // Subtract Packed Floating-Point Values |
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1702 void subpd(XMMRegister dst, XMMRegister src); |
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1703 void subps(XMMRegister dst, XMMRegister src); |
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1704 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1705 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1706 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1707 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1708 |
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1709 // Multiply Packed Floating-Point Values |
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1710 void mulpd(XMMRegister dst, XMMRegister src); |
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1711 void mulps(XMMRegister dst, XMMRegister src); |
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1712 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1713 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1714 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1715 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1716 |
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1717 // Divide Packed Floating-Point Values |
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1718 void divpd(XMMRegister dst, XMMRegister src); |
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1719 void divps(XMMRegister dst, XMMRegister src); |
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1720 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1721 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1722 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1723 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1724 |
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|
1725 // Bitwise Logical AND of Packed Floating-Point Values |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1726 void andpd(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1727 void andps(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1728 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1729 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1730 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1731 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1732 |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1733 // Bitwise Logical XOR of Packed Floating-Point Values |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1734 void xorpd(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1735 void xorps(XMMRegister dst, XMMRegister src); |
6179
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7119644: Increase superword's vector size up to 256 bits
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changeset
|
1736 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
1737 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1738 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1739 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1740 |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1741 // Add packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1742 void paddb(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1743 void paddw(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1744 void paddd(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1745 void paddq(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1746 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1747 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1748 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1749 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1750 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1751 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1752 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1753 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1754 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1755 // Sub packed integers |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1756 void psubb(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1757 void psubw(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1758 void psubd(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1759 void psubq(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1760 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1761 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1762 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1763 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1764 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1765 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1766 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1767 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1768 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1769 // Multiply packed integers (only shorts and ints) |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1770 void pmullw(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1771 void pmulld(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1772 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1773 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1774 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1775 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1776 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1777 // Shift left packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
1778 void psllw(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1779 void pslld(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1780 void psllq(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1781 void psllw(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1782 void pslld(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1783 void psllq(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1784 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1785 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1786 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1787 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1788 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1789 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1790 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1791 // Logical shift right packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1792 void psrlw(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1793 void psrld(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1794 void psrlq(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1795 void psrlw(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1796 void psrld(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1797 void psrlq(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1798 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1799 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1800 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1801 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1802 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1803 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1804 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1805 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1806 void psraw(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1807 void psrad(XMMRegister dst, int shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1808 void psraw(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1809 void psrad(XMMRegister dst, XMMRegister shift); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1810 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1811 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1812 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1813 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1814 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1815 // And packed integers |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1816 void pand(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1817 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1818 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1819 |
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6340864: Implement vectorization optimizations in hotspot-server
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|
1820 // Or packed integers |
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6340864: Implement vectorization optimizations in hotspot-server
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|
1821 void por(XMMRegister dst, XMMRegister src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1822 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1823 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1824 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1825 // Xor packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1826 void pxor(XMMRegister dst, XMMRegister src); |
6225 | 1827 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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|
1828 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1829 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1830 // Copy low 128bit into high 128bit of YMM registers. |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
1831 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
6225 | 1832 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
6179
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|
1833 |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
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changeset
|
1834 // Load/store high 128bit of YMM registers which does not destroy other half. |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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changeset
|
1835 void vinsertf128h(XMMRegister dst, Address src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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changeset
|
1836 void vinserti128h(XMMRegister dst, Address src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
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changeset
|
1837 void vextractf128h(Address dst, XMMRegister src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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changeset
|
1838 void vextracti128h(Address dst, XMMRegister src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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changeset
|
1839 |
7475
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1840 // duplicate 4-bytes integer data from src into 8 locations in dest |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
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diff
changeset
|
1841 void vpbroadcastd(XMMRegister dst, XMMRegister src); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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changeset
|
1842 |
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1843 // Carry-Less Multiplication Quadword |
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1844 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); |
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1845 |
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1846 // AVX instruction which is used to clear upper 128 bits of YMM registers and |
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1847 // to avoid transaction penalty between AVX and SSE states. There is no |
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1848 // penalty if legacy SSE instructions are encoded using VEX prefix because |
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1849 // they always clear upper 128 bits. It should be used before calling |
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1850 // runtime code and native libraries. |
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1851 void vzeroupper(); |
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1852 |
4759 | 1853 protected: |
1854 // Next instructions require address alignment 16 bytes SSE mode. | |
1855 // They should be called only from corresponding MacroAssembler instructions. | |
1856 void andpd(XMMRegister dst, Address src); | |
1857 void andps(XMMRegister dst, Address src); | |
1858 void xorpd(XMMRegister dst, Address src); | |
1859 void xorps(XMMRegister dst, Address src); | |
1860 | |
0 | 1861 }; |
1862 | |
1972 | 1863 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |