Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 1567:110501f54a99
6934104: JSR 292 needs to support SPARC C2
Summary: C2 for SPARC needs to support JSR 292.
Reviewed-by: kvn, never
author | twisti |
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date | Tue, 25 May 2010 02:38:48 -0700 |
parents | d7f654633cfe |
children | 2d127394260e |
rev | line source |
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0 | 1 // |
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f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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2 // Copyright 1998-2010 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
21 // have any questions. | |
22 // | |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
429 %} | |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
463 // Macros to extract hi & lo halves from a long pair. | |
464 // G0 is not part of any long pair, so assert on that. | |
605 | 465 // Prevents accidentally using G1 instead of G0. |
0 | 466 #define LONG_HI_REG(x) (x) |
467 #define LONG_LO_REG(x) (x) | |
468 | |
469 %} | |
470 | |
471 source %{ | |
472 #define __ _masm. | |
473 | |
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474 // Block initializing store |
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475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
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476 |
0 | 477 // tertiary op of a LoadP or StoreP encoding |
478 #define REGP_OP true | |
479 | |
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
482 static Register reg_to_register_object(int register_encoding); | |
483 | |
484 // Used by the DFA in dfa_sparc.cpp. | |
485 // Check for being able to use a V9 branch-on-register. Requires a | |
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
487 // extended. Doesn't work following an integer ADD, for example, because of | |
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
490 // replace them with zero, which could become sign-extension in a different OS | |
491 // release. There's no obvious reason why an interrupt will ever fill these | |
492 // bits with non-zero junk (the registers are reloaded with standard LD | |
493 // instructions which either zero-fill or sign-fill). | |
494 bool can_branch_register( Node *bol, Node *cmp ) { | |
495 if( !BranchOnRegister ) return false; | |
496 #ifdef _LP64 | |
497 if( cmp->Opcode() == Op_CmpP ) | |
498 return true; // No problems with pointer compares | |
499 #endif | |
500 if( cmp->Opcode() == Op_CmpL ) | |
501 return true; // No problems with long compares | |
502 | |
503 if( !SparcV9RegsHiBitsZero ) return false; | |
504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
506 return false; | |
507 | |
508 // Check for comparing against a 'safe' value. Any operation which | |
509 // clears out the high word is safe. Thus, loads and certain shifts | |
510 // are safe, as are non-negative constants. Any operation which | |
511 // preserves zero bits in the high word is safe as long as each of its | |
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
513 // inputs are safe. At present, the only important case to recognize | |
514 // seems to be loads. Constants should fold away, and shifts & | |
515 // logicals can use the 'cc' forms. | |
516 Node *x = cmp->in(1); | |
517 if( x->is_Load() ) return true; | |
518 if( x->is_Phi() ) { | |
519 for( uint i = 1; i < x->req(); i++ ) | |
520 if( !x->in(i)->is_Load() ) | |
521 return false; | |
522 return true; | |
523 } | |
524 return false; | |
525 } | |
526 | |
527 // **************************************************************************** | |
528 | |
529 // REQUIRED FUNCTIONALITY | |
530 | |
531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
532 // from the start of the call to the point where the return address | |
533 // will point. | |
534 // The "return address" is the address of the call instruction, plus 8. | |
535 | |
536 int MachCallStaticJavaNode::ret_addr_offset() { | |
1567 | 537 int offset = NativeCall::instruction_size; // call; delay slot |
538 if (_method_handle_invoke) | |
539 offset += 4; // restore SP | |
540 return offset; | |
0 | 541 } |
542 | |
543 int MachCallDynamicJavaNode::ret_addr_offset() { | |
544 int vtable_index = this->_vtable_index; | |
545 if (vtable_index < 0) { | |
546 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
548 return (NativeMovConstReg::instruction_size + | |
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
550 } else { | |
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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554 int klass_load_size; |
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555 if (UseCompressedOops) { |
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556 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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557 if (Universe::narrow_oop_base() == NULL) |
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558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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559 else |
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560 klass_load_size = 3*BytesPerInstWord; |
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561 } else { |
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562 klass_load_size = 1*BytesPerInstWord; |
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563 } |
0 | 564 if( Assembler::is_simm13(v_off) ) { |
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565 return klass_load_size + |
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566 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 567 NativeCall::instruction_size); // call; delay slot |
568 } else { | |
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569 return klass_load_size + |
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570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 571 NativeCall::instruction_size); // call; delay slot |
572 } | |
573 } | |
574 } | |
575 | |
576 int MachCallRuntimeNode::ret_addr_offset() { | |
577 #ifdef _LP64 | |
578 return NativeFarCall::instruction_size; // farcall; delay slot | |
579 #else | |
580 return NativeCall::instruction_size; // call; delay slot | |
581 #endif | |
582 } | |
583 | |
584 // Indicate if the safepoint node needs the polling page as an input. | |
585 // Since Sparc does not have absolute addressing, it does. | |
586 bool SafePointNode::needs_polling_address_input() { | |
587 return true; | |
588 } | |
589 | |
590 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
591 void emit_break(CodeBuffer &cbuf) { | |
592 MacroAssembler _masm(&cbuf); | |
593 __ breakpoint_trap(); | |
594 } | |
595 | |
596 #ifndef PRODUCT | |
597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
598 st->print("TA"); | |
599 } | |
600 #endif | |
601 | |
602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
603 emit_break(cbuf); | |
604 } | |
605 | |
606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
607 return MachNode::size(ra_); | |
608 } | |
609 | |
610 // Traceable jump | |
611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
612 MacroAssembler _masm(&cbuf); | |
613 Register rdest = reg_to_register_object(jump_target); | |
614 __ JMP(rdest, 0); | |
615 __ delayed()->nop(); | |
616 } | |
617 | |
618 // Traceable jump and set exception pc | |
619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
620 MacroAssembler _masm(&cbuf); | |
621 Register rdest = reg_to_register_object(jump_target); | |
622 __ JMP(rdest, 0); | |
623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
624 } | |
625 | |
626 void emit_nop(CodeBuffer &cbuf) { | |
627 MacroAssembler _masm(&cbuf); | |
628 __ nop(); | |
629 } | |
630 | |
631 void emit_illtrap(CodeBuffer &cbuf) { | |
632 MacroAssembler _masm(&cbuf); | |
633 __ illtrap(0); | |
634 } | |
635 | |
636 | |
637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
638 assert(n->rule() != loadUB_rule, ""); | |
639 | |
640 intptr_t offset = 0; | |
641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
642 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
644 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
645 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
646 atype = atype->add_offset(offset); | |
647 assert(disp32 == offset, "wrong disp32"); | |
648 return atype->_offset; | |
649 } | |
650 | |
651 | |
652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
653 assert(n->rule() != loadUB_rule, ""); | |
654 | |
655 intptr_t offset = 0; | |
656 Node* addr = n->in(2); | |
657 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
659 Node* a = addr->in(2/*AddPNode::Address*/); | |
660 Node* o = addr->in(3/*AddPNode::Offset*/); | |
661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
662 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
663 assert(atype->isa_oop_ptr(), "still an oop"); | |
664 } | |
665 offset = atype->is_ptr()->_offset; | |
666 if (offset != Type::OffsetBot) offset += disp32; | |
667 return offset; | |
668 } | |
669 | |
670 // Standard Sparc opcode form2 field breakdown | |
671 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
672 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
673 int op = (f30 << 30) | | |
674 (f29 << 29) | | |
675 (f25 << 25) | | |
676 (f22 << 22) | | |
677 (f20 << 20) | | |
678 (f19 << 19) | | |
679 (f0 << 0); | |
680 *((int*)(cbuf.code_end())) = op; | |
681 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
682 } | |
683 | |
684 // Standard Sparc opcode form2 field breakdown | |
685 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
686 f0 >>= 10; // Drop 10 bits | |
687 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
688 int op = (f30 << 30) | | |
689 (f25 << 25) | | |
690 (f22 << 22) | | |
691 (f0 << 0); | |
692 *((int*)(cbuf.code_end())) = op; | |
693 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
694 } | |
695 | |
696 // Standard Sparc opcode form3 field breakdown | |
697 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
698 int op = (f30 << 30) | | |
699 (f25 << 25) | | |
700 (f19 << 19) | | |
701 (f14 << 14) | | |
702 (f5 << 5) | | |
703 (f0 << 0); | |
704 *((int*)(cbuf.code_end())) = op; | |
705 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
706 } | |
707 | |
708 // Standard Sparc opcode form3 field breakdown | |
709 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
710 simm13 &= (1<<13)-1; // Mask to 13 bits | |
711 int op = (f30 << 30) | | |
712 (f25 << 25) | | |
713 (f19 << 19) | | |
714 (f14 << 14) | | |
715 (1 << 13) | // bit to indicate immediate-mode | |
716 (simm13<<0); | |
717 *((int*)(cbuf.code_end())) = op; | |
718 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
719 } | |
720 | |
721 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
722 simm10 &= (1<<10)-1; // Mask to 10 bits | |
723 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
724 } | |
725 | |
726 #ifdef ASSERT | |
727 // Helper function for VerifyOops in emit_form3_mem_reg | |
728 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
729 warning("VerifyOops encountered unexpected instruction:"); | |
730 n->dump(2); | |
731 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
732 } | |
733 #endif | |
734 | |
735 | |
736 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
737 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
738 | |
739 #ifdef ASSERT | |
740 // The following code implements the +VerifyOops feature. | |
741 // It verifies oop values which are loaded into or stored out of | |
742 // the current method activation. +VerifyOops complements techniques | |
743 // like ScavengeALot, because it eagerly inspects oops in transit, | |
744 // as they enter or leave the stack, as opposed to ScavengeALot, | |
745 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
746 // For this reason, +VerifyOops can sometimes detect bugs very close | |
747 // to their point of creation. It can also serve as a cross-check | |
748 // on the validity of oop maps, when used toegether with ScavengeALot. | |
749 | |
750 // It would be good to verify oops at other points, especially | |
751 // when an oop is used as a base pointer for a load or store. | |
752 // This is presently difficult, because it is hard to know when | |
753 // a base address is biased or not. (If we had such information, | |
754 // it would be easy and useful to make a two-argument version of | |
755 // verify_oop which unbiases the base, and performs verification.) | |
756 | |
757 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
758 bool is_verified_oop_base = false; | |
759 bool is_verified_oop_load = false; | |
760 bool is_verified_oop_store = false; | |
761 int tmp_enc = -1; | |
762 if (VerifyOops && src1_enc != R_SP_enc) { | |
763 // classify the op, mainly for an assert check | |
764 int st_op = 0, ld_op = 0; | |
765 switch (primary) { | |
766 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
767 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
768 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
769 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
770 case Assembler::std_op3: st_op = Op_StoreL; break; | |
771 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
772 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
773 | |
774 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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775 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 776 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
777 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
778 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
779 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
780 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
781 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
782 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
783 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
784 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
785 | |
786 default: ShouldNotReachHere(); | |
787 } | |
788 if (tertiary == REGP_OP) { | |
789 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
790 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
791 else ShouldNotReachHere(); | |
792 if (st_op) { | |
793 // a store | |
794 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
795 Node* n2 = n->in(3); | |
796 if (n2 != NULL) { | |
797 const Type* t = n2->bottom_type(); | |
798 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
799 } | |
800 } else { | |
801 // a load | |
802 const Type* t = n->bottom_type(); | |
803 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
804 } | |
805 } | |
806 | |
807 if (ld_op) { | |
808 // a Load | |
809 // inputs are (0:control, 1:memory, 2:address) | |
810 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
811 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
812 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
813 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
814 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
815 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
816 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
817 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
818 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
819 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
820 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
821 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
822 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
823 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
824 !(n->rule() == loadUB_rule)) { | |
825 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
826 } | |
827 } else if (st_op) { | |
828 // a Store | |
829 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
830 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
831 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
832 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
833 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
834 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
835 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { | |
836 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
837 } | |
838 } | |
839 | |
840 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
841 Node* addr = n->in(2); | |
842 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
843 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
844 if (atype != NULL) { | |
845 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
846 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
847 if (offset != offset_2) { | |
848 get_offset_from_base(n, atype, disp32); | |
849 get_offset_from_base_2(n, atype, disp32); | |
850 } | |
851 assert(offset == offset_2, "different offsets"); | |
852 if (offset == disp32) { | |
853 // we now know that src1 is a true oop pointer | |
854 is_verified_oop_base = true; | |
855 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
856 if( primary == Assembler::ldd_op3 ) { | |
857 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
858 } else { | |
859 tmp_enc = dst_enc; | |
860 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
861 assert(src1_enc != dst_enc, ""); | |
862 } | |
863 } | |
864 } | |
865 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
866 || offset == oopDesc::mark_offset_in_bytes())) { | |
867 // loading the mark should not be allowed either, but | |
868 // we don't check this since it conflicts with InlineObjectHash | |
869 // usage of LoadINode to get the mark. We could keep the | |
870 // check if we create a new LoadMarkNode | |
871 // but do not verify the object before its header is initialized | |
872 ShouldNotReachHere(); | |
873 } | |
874 } | |
875 } | |
876 } | |
877 } | |
878 #endif | |
879 | |
880 uint instr; | |
881 instr = (Assembler::ldst_op << 30) | |
882 | (dst_enc << 25) | |
883 | (primary << 19) | |
884 | (src1_enc << 14); | |
885 | |
886 uint index = src2_enc; | |
887 int disp = disp32; | |
888 | |
889 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
890 disp += STACK_BIAS; | |
891 | |
892 // We should have a compiler bailout here rather than a guarantee. | |
893 // Better yet would be some mechanism to handle variable-size matches correctly. | |
894 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
895 | |
896 if( disp == 0 ) { | |
897 // use reg-reg form | |
898 // bit 13 is already zero | |
899 instr |= index; | |
900 } else { | |
901 // use reg-imm form | |
902 instr |= 0x00002000; // set bit 13 to one | |
903 instr |= disp & 0x1FFF; | |
904 } | |
905 | |
906 uint *code = (uint*)cbuf.code_end(); | |
907 *code = instr; | |
908 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
909 | |
910 #ifdef ASSERT | |
911 { | |
912 MacroAssembler _masm(&cbuf); | |
913 if (is_verified_oop_base) { | |
914 __ verify_oop(reg_to_register_object(src1_enc)); | |
915 } | |
916 if (is_verified_oop_store) { | |
917 __ verify_oop(reg_to_register_object(dst_enc)); | |
918 } | |
919 if (tmp_enc != -1) { | |
920 __ mov(O7, reg_to_register_object(tmp_enc)); | |
921 } | |
922 if (is_verified_oop_load) { | |
923 __ verify_oop(reg_to_register_object(dst_enc)); | |
924 } | |
925 } | |
926 #endif | |
927 } | |
928 | |
929 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
930 // The method which records debug information at every safepoint | |
931 // expects the call to be the first instruction in the snippet as | |
932 // it creates a PcDesc structure which tracks the offset of a call | |
933 // from the start of the codeBlob. This offset is computed as | |
934 // code_end() - code_begin() of the code which has been emitted | |
935 // so far. | |
936 // In this particular case we have skirted around the problem by | |
937 // putting the "mov" instruction in the delay slot but the problem | |
938 // may bite us again at some other point and a cleaner/generic | |
939 // solution using relocations would be needed. | |
940 MacroAssembler _masm(&cbuf); | |
941 __ set_inst_mark(); | |
942 | |
943 // We flush the current window just so that there is a valid stack copy | |
944 // the fact that the current window becomes active again instantly is | |
945 // not a problem there is nothing live in it. | |
946 | |
947 #ifdef ASSERT | |
948 int startpos = __ offset(); | |
949 #endif /* ASSERT */ | |
950 | |
951 #ifdef _LP64 | |
952 // Calls to the runtime or native may not be reachable from compiled code, | |
953 // so we generate the far call sequence on 64 bit sparc. | |
954 // This code sequence is relocatable to any address, even on LP64. | |
955 if ( force_far_call ) { | |
956 __ relocate(rtype); | |
727 | 957 AddressLiteral dest(entry_point); |
958 __ jumpl_to(dest, O7, O7); | |
0 | 959 } |
960 else | |
961 #endif | |
962 { | |
963 __ call((address)entry_point, rtype); | |
964 } | |
965 | |
966 if (preserve_g2) __ delayed()->mov(G2, L7); | |
967 else __ delayed()->nop(); | |
968 | |
969 if (preserve_g2) __ mov(L7, G2); | |
970 | |
971 #ifdef ASSERT | |
972 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
973 #ifdef _LP64 | |
974 // Trash argument dump slots. | |
975 __ set(0xb0b8ac0db0b8ac0d, G1); | |
976 __ mov(G1, G5); | |
977 __ stx(G1, SP, STACK_BIAS + 0x80); | |
978 __ stx(G1, SP, STACK_BIAS + 0x88); | |
979 __ stx(G1, SP, STACK_BIAS + 0x90); | |
980 __ stx(G1, SP, STACK_BIAS + 0x98); | |
981 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
982 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
983 #else // _LP64 | |
984 // this is also a native call, so smash the first 7 stack locations, | |
985 // and the various registers | |
986 | |
987 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
988 // while [SP+0x44..0x58] are the argument dump slots. | |
989 __ set((intptr_t)0xbaadf00d, G1); | |
990 __ mov(G1, G5); | |
991 __ sllx(G1, 32, G1); | |
992 __ or3(G1, G5, G1); | |
993 __ mov(G1, G5); | |
994 __ stx(G1, SP, 0x40); | |
995 __ stx(G1, SP, 0x48); | |
996 __ stx(G1, SP, 0x50); | |
997 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
998 #endif // _LP64 | |
999 } | |
1000 #endif /*ASSERT*/ | |
1001 } | |
1002 | |
1003 //============================================================================= | |
1004 // REQUIRED FUNCTIONALITY for encoding | |
1005 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1006 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1007 | |
1008 | |
1009 //============================================================================= | |
1010 | |
1011 #ifndef PRODUCT | |
1012 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1013 Compile* C = ra_->C; | |
1014 | |
1015 for (int i = 0; i < OptoPrologueNops; i++) { | |
1016 st->print_cr("NOP"); st->print("\t"); | |
1017 } | |
1018 | |
1019 if( VerifyThread ) { | |
1020 st->print_cr("Verify_Thread"); st->print("\t"); | |
1021 } | |
1022 | |
1023 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1024 | |
1025 // Calls to C2R adapters often do not accept exceptional returns. | |
1026 // We require that their callers must bang for them. But be careful, because | |
1027 // some VM calls (such as call site linkage) can use several kilobytes of | |
1028 // stack. But the stack safety zone should account for that. | |
1029 // See bugs 4446381, 4468289, 4497237. | |
1030 if (C->need_stack_bang(framesize)) { | |
1031 st->print_cr("! stack bang"); st->print("\t"); | |
1032 } | |
1033 | |
1034 if (Assembler::is_simm13(-framesize)) { | |
1035 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1036 } else { | |
1037 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1038 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1039 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1040 } | |
1041 | |
1042 } | |
1043 #endif | |
1044 | |
1045 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1046 Compile* C = ra_->C; | |
1047 MacroAssembler _masm(&cbuf); | |
1048 | |
1049 for (int i = 0; i < OptoPrologueNops; i++) { | |
1050 __ nop(); | |
1051 } | |
1052 | |
1053 __ verify_thread(); | |
1054 | |
1055 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1056 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1057 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1058 | |
1059 // Calls to C2R adapters often do not accept exceptional returns. | |
1060 // We require that their callers must bang for them. But be careful, because | |
1061 // some VM calls (such as call site linkage) can use several kilobytes of | |
1062 // stack. But the stack safety zone should account for that. | |
1063 // See bugs 4446381, 4468289, 4497237. | |
1064 if (C->need_stack_bang(framesize)) { | |
1065 __ generate_stack_overflow_check(framesize); | |
1066 } | |
1067 | |
1068 if (Assembler::is_simm13(-framesize)) { | |
1069 __ save(SP, -framesize, SP); | |
1070 } else { | |
1071 __ sethi(-framesize & ~0x3ff, G3); | |
1072 __ add(G3, -framesize & 0x3ff, G3); | |
1073 __ save(SP, G3, SP); | |
1074 } | |
1075 C->set_frame_complete( __ offset() ); | |
1076 } | |
1077 | |
1078 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1079 return MachNode::size(ra_); | |
1080 } | |
1081 | |
1082 int MachPrologNode::reloc() const { | |
1083 return 10; // a large enough number | |
1084 } | |
1085 | |
1086 //============================================================================= | |
1087 #ifndef PRODUCT | |
1088 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1089 Compile* C = ra_->C; | |
1090 | |
1091 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1092 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1093 #ifdef _LP64 | |
1094 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1095 #else | |
1096 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1097 #endif | |
1098 } | |
1099 | |
1100 if( do_polling() ) | |
1101 st->print("RET\n\t"); | |
1102 | |
1103 st->print("RESTORE"); | |
1104 } | |
1105 #endif | |
1106 | |
1107 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1108 MacroAssembler _masm(&cbuf); | |
1109 Compile* C = ra_->C; | |
1110 | |
1111 __ verify_thread(); | |
1112 | |
1113 // If this does safepoint polling, then do it here | |
1114 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1115 AddressLiteral polling_page(os::get_polling_page()); |
1116 __ sethi(polling_page, L0); | |
0 | 1117 __ relocate(relocInfo::poll_return_type); |
1118 __ ld_ptr( L0, 0, G0 ); | |
1119 } | |
1120 | |
1121 // If this is a return, then stuff the restore in the delay slot | |
1122 if( do_polling() ) { | |
1123 __ ret(); | |
1124 __ delayed()->restore(); | |
1125 } else { | |
1126 __ restore(); | |
1127 } | |
1128 } | |
1129 | |
1130 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1131 return MachNode::size(ra_); | |
1132 } | |
1133 | |
1134 int MachEpilogNode::reloc() const { | |
1135 return 16; // a large enough number | |
1136 } | |
1137 | |
1138 const Pipeline * MachEpilogNode::pipeline() const { | |
1139 return MachNode::pipeline_class(); | |
1140 } | |
1141 | |
1142 int MachEpilogNode::safepoint_offset() const { | |
1143 assert( do_polling(), "no return for this epilog node"); | |
1144 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
1145 } | |
1146 | |
1147 //============================================================================= | |
1148 | |
1149 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1150 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1151 static enum RC rc_class( OptoReg::Name reg ) { | |
1152 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1153 if (OptoReg::is_stack(reg)) return rc_stack; | |
1154 VMReg r = OptoReg::as_VMReg(reg); | |
1155 if (r->is_Register()) return rc_int; | |
1156 assert(r->is_FloatRegister(), "must be"); | |
1157 return rc_float; | |
1158 } | |
1159 | |
1160 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1161 if( cbuf ) { | |
1162 // Better yet would be some mechanism to handle variable-size matches correctly | |
1163 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1164 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1165 } else { | |
1166 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1167 } | |
1168 } | |
1169 #ifndef PRODUCT | |
1170 else if( !do_size ) { | |
1171 if( size != 0 ) st->print("\n\t"); | |
1172 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1173 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1174 } | |
1175 #endif | |
1176 return size+4; | |
1177 } | |
1178 | |
1179 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1180 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1181 #ifndef PRODUCT | |
1182 else if( !do_size ) { | |
1183 if( size != 0 ) st->print("\n\t"); | |
1184 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1185 } | |
1186 #endif | |
1187 return size+4; | |
1188 } | |
1189 | |
1190 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1191 PhaseRegAlloc *ra_, | |
1192 bool do_size, | |
1193 outputStream* st ) const { | |
1194 // Get registers to move | |
1195 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1196 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1197 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1198 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1199 | |
1200 enum RC src_second_rc = rc_class(src_second); | |
1201 enum RC src_first_rc = rc_class(src_first); | |
1202 enum RC dst_second_rc = rc_class(dst_second); | |
1203 enum RC dst_first_rc = rc_class(dst_first); | |
1204 | |
1205 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1206 | |
1207 // Generate spill code! | |
1208 int size = 0; | |
1209 | |
1210 if( src_first == dst_first && src_second == dst_second ) | |
1211 return size; // Self copy, no move | |
1212 | |
1213 // -------------------------------------- | |
1214 // Check for mem-mem move. Load into unused float registers and fall into | |
1215 // the float-store case. | |
1216 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1217 int offset = ra_->reg2offset(src_first); | |
1218 // Further check for aligned-adjacent pair, so we can use a double load | |
1219 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1220 src_second = OptoReg::Name(R_F31_num); | |
1221 src_second_rc = rc_float; | |
1222 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1223 } else { | |
1224 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1225 } | |
1226 src_first = OptoReg::Name(R_F30_num); | |
1227 src_first_rc = rc_float; | |
1228 } | |
1229 | |
1230 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1231 int offset = ra_->reg2offset(src_second); | |
1232 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1233 src_second = OptoReg::Name(R_F31_num); | |
1234 src_second_rc = rc_float; | |
1235 } | |
1236 | |
1237 // -------------------------------------- | |
1238 // Check for float->int copy; requires a trip through memory | |
1239 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
1240 int offset = frame::register_save_words*wordSize; | |
1241 if( cbuf ) { | |
1242 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
1243 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1244 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1245 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1246 } | |
1247 #ifndef PRODUCT | |
1248 else if( !do_size ) { | |
1249 if( size != 0 ) st->print("\n\t"); | |
1250 st->print( "SUB R_SP,16,R_SP\n"); | |
1251 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1252 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1253 st->print("\tADD R_SP,16,R_SP\n"); | |
1254 } | |
1255 #endif | |
1256 size += 16; | |
1257 } | |
1258 | |
1259 // -------------------------------------- | |
1260 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1261 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1262 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1263 // there. Misaligned sources only come from native-long-returns (handled | |
1264 // special below). | |
1265 #ifndef _LP64 | |
1266 if( src_first_rc == rc_int && // source is already big-endian | |
1267 src_second_rc != rc_bad && // 64-bit move | |
1268 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1269 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1270 // Do the big-endian flop. | |
1271 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1272 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1273 } | |
1274 #endif | |
1275 | |
1276 // -------------------------------------- | |
1277 // Check for integer reg-reg copy | |
1278 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1279 #ifndef _LP64 | |
1280 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1281 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1282 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1283 // operand contains the least significant word of the 64-bit value and vice versa. | |
1284 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1285 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1286 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1287 if( cbuf ) { | |
1288 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1289 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1290 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1291 #ifndef PRODUCT | |
1292 } else if( !do_size ) { | |
1293 if( size != 0 ) st->print("\n\t"); | |
1294 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1295 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1296 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1297 #endif | |
1298 } | |
1299 return size+12; | |
1300 } | |
1301 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1302 // returning a long value in I0/I1 | |
1303 // a SpillCopy must be able to target a return instruction's reg_class | |
1304 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1305 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1306 // operand contains the least significant word of the 64-bit value and vice versa. | |
1307 OptoReg::Name tdest = dst_first; | |
1308 | |
1309 if (src_first == dst_first) { | |
1310 tdest = OptoReg::Name(R_O7_num); | |
1311 size += 4; | |
1312 } | |
1313 | |
1314 if( cbuf ) { | |
1315 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1316 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1317 // ShrL_reg_imm6 | |
1318 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1319 // ShrR_reg_imm6 src, 0, dst | |
1320 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1321 if (tdest != dst_first) { | |
1322 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1323 } | |
1324 } | |
1325 #ifndef PRODUCT | |
1326 else if( !do_size ) { | |
1327 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1328 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1329 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1330 if (tdest != dst_first) { | |
1331 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1332 } | |
1333 } | |
1334 #endif // PRODUCT | |
1335 return size+8; | |
1336 } | |
1337 #endif // !_LP64 | |
1338 // Else normal reg-reg copy | |
1339 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1340 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1341 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1342 // This moves an aligned adjacent pair. | |
1343 // See if we are done. | |
1344 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1345 return size; | |
1346 } | |
1347 | |
1348 // Check for integer store | |
1349 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1350 int offset = ra_->reg2offset(dst_first); | |
1351 // Further check for aligned-adjacent pair, so we can use a double store | |
1352 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1353 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1354 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1355 } | |
1356 | |
1357 // Check for integer load | |
1358 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1359 int offset = ra_->reg2offset(src_first); | |
1360 // Further check for aligned-adjacent pair, so we can use a double load | |
1361 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1362 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1363 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1364 } | |
1365 | |
1366 // Check for float reg-reg copy | |
1367 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1368 // Further check for aligned-adjacent pair, so we can use a double move | |
1369 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1370 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1371 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1372 } | |
1373 | |
1374 // Check for float store | |
1375 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1376 int offset = ra_->reg2offset(dst_first); | |
1377 // Further check for aligned-adjacent pair, so we can use a double store | |
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1381 } | |
1382 | |
1383 // Check for float load | |
1384 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1385 int offset = ra_->reg2offset(src_first); | |
1386 // Further check for aligned-adjacent pair, so we can use a double load | |
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1390 } | |
1391 | |
1392 // -------------------------------------------------------------------- | |
1393 // Check for hi bits still needing moving. Only happens for misaligned | |
1394 // arguments to native calls. | |
1395 if( src_second == dst_second ) | |
1396 return size; // Self copy; no move | |
1397 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1398 | |
1399 #ifndef _LP64 | |
1400 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1401 // pairs, so there's never any need to move the high bits separately. |
0 | 1402 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1403 // all sorts of silly alignment problems. | |
1404 | |
1405 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1406 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1407 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1408 // happened already as part of a 64-bit move) | |
1409 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1410 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1411 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1412 // Shift src_second down to dst_second's low bits. | |
1413 if( cbuf ) { | |
1414 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1415 #ifndef PRODUCT | |
1416 } else if( !do_size ) { | |
1417 if( size != 0 ) st->print("\n\t"); | |
1418 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1419 #endif | |
1420 } | |
1421 return size+4; | |
1422 } | |
1423 | |
1424 // Check for high word integer store. Must down-shift the hi bits | |
1425 // into a temp register, then fall into the case of storing int bits. | |
1426 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1427 // Shift src_second down to dst_second's low bits. | |
1428 if( cbuf ) { | |
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1430 #ifndef PRODUCT | |
1431 } else if( !do_size ) { | |
1432 if( size != 0 ) st->print("\n\t"); | |
1433 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1434 #endif | |
1435 } | |
1436 size+=4; | |
1437 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1438 } | |
1439 | |
1440 // Check for high word integer load | |
1441 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1442 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1443 | |
1444 // Check for high word integer store | |
1445 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1446 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1447 | |
1448 // Check for high word float store | |
1449 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1450 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1451 | |
1452 #endif // !_LP64 | |
1453 | |
1454 Unimplemented(); | |
1455 } | |
1456 | |
1457 #ifndef PRODUCT | |
1458 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1459 implementation( NULL, ra_, false, st ); | |
1460 } | |
1461 #endif | |
1462 | |
1463 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1464 implementation( &cbuf, ra_, false, NULL ); | |
1465 } | |
1466 | |
1467 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1468 return implementation( NULL, ra_, true, NULL ); | |
1469 } | |
1470 | |
1471 //============================================================================= | |
1472 #ifndef PRODUCT | |
1473 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1474 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1475 } | |
1476 #endif | |
1477 | |
1478 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1479 MacroAssembler _masm(&cbuf); | |
1480 for(int i = 0; i < _count; i += 1) { | |
1481 __ nop(); | |
1482 } | |
1483 } | |
1484 | |
1485 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1486 return 4 * _count; | |
1487 } | |
1488 | |
1489 | |
1490 //============================================================================= | |
1491 #ifndef PRODUCT | |
1492 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1493 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1494 int reg = ra_->get_reg_first(this); | |
1495 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1496 } | |
1497 #endif | |
1498 | |
1499 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1500 MacroAssembler _masm(&cbuf); | |
1501 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1502 int reg = ra_->get_encode(this); | |
1503 | |
1504 if (Assembler::is_simm13(offset)) { | |
1505 __ add(SP, offset, reg_to_register_object(reg)); | |
1506 } else { | |
1507 __ set(offset, O7); | |
1508 __ add(SP, O7, reg_to_register_object(reg)); | |
1509 } | |
1510 } | |
1511 | |
1512 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1513 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1514 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1515 return ra_->C->scratch_emit_size(this); | |
1516 } | |
1517 | |
1518 //============================================================================= | |
1519 | |
1520 // emit call stub, compiled java to interpretor | |
1521 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
1522 | |
1523 // Stub is fixed up when the corresponding call is converted from calling | |
1524 // compiled code to calling interpreted code. | |
1525 // set (empty), G5 | |
1526 // jmp -1 | |
1527 | |
1528 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
1529 | |
1530 MacroAssembler _masm(&cbuf); | |
1531 | |
1532 address base = | |
1533 __ start_a_stub(Compile::MAX_stubs_size); | |
1534 if (base == NULL) return; // CodeBuffer::expand failed | |
1535 | |
1536 // static stub relocation stores the instruction address of the call | |
1537 __ relocate(static_stub_Relocation::spec(mark)); | |
1538 | |
1539 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
1540 | |
1541 __ set_inst_mark(); | |
727 | 1542 AddressLiteral addrlit(-1); |
1543 __ JUMP(addrlit, G3, 0); | |
0 | 1544 |
1545 __ delayed()->nop(); | |
1546 | |
1547 // Update current stubs pointer and restore code_end. | |
1548 __ end_a_stub(); | |
1549 } | |
1550 | |
1551 // size of call stub, compiled java to interpretor | |
1552 uint size_java_to_interp() { | |
1553 // This doesn't need to be accurate but it must be larger or equal to | |
1554 // the real size of the stub. | |
1555 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
1556 NativeJump::instruction_size + // sethi; jmp; nop | |
1557 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
1558 } | |
1559 // relocation entries for call stub, compiled java to interpretor | |
1560 uint reloc_java_to_interp() { | |
1561 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
1562 } | |
1563 | |
1564 | |
1565 //============================================================================= | |
1566 #ifndef PRODUCT | |
1567 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1568 st->print_cr("\nUEP:"); | |
1569 #ifdef _LP64 | |
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1570 if (UseCompressedOops) { |
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1571 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1572 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1573 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1574 if (Universe::narrow_oop_base() != NULL) |
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1575 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1576 } else { |
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1577 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1578 } |
0 | 1579 st->print_cr("\tCMP R_G5,R_G3" ); |
1580 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1581 #else // _LP64 | |
1582 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1583 st->print_cr("\tCMP R_G5,R_G3" ); | |
1584 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1585 #endif // _LP64 | |
1586 } | |
1587 #endif | |
1588 | |
1589 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1590 MacroAssembler _masm(&cbuf); | |
1591 Label L; | |
1592 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1593 Register temp_reg = G3; | |
1594 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1595 | |
605 | 1596 // Load klass from receiver |
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1597 __ load_klass(O0, temp_reg); |
0 | 1598 // Compare against expected klass |
1599 __ cmp(temp_reg, G5_ic_reg); | |
1600 // Branch to miss code, checks xcc or icc depending | |
1601 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1602 } | |
1603 | |
1604 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1605 return MachNode::size(ra_); | |
1606 } | |
1607 | |
1608 | |
1609 //============================================================================= | |
1610 | |
1611 uint size_exception_handler() { | |
1612 if (TraceJumps) { | |
1613 return (400); // just a guess | |
1614 } | |
1615 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1616 } | |
1617 | |
1618 uint size_deopt_handler() { | |
1619 if (TraceJumps) { | |
1620 return (400); // just a guess | |
1621 } | |
1622 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1623 } | |
1624 | |
1625 // Emit exception handler code. | |
1626 int emit_exception_handler(CodeBuffer& cbuf) { | |
1627 Register temp_reg = G3; | |
727 | 1628 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); |
0 | 1629 MacroAssembler _masm(&cbuf); |
1630 | |
1631 address base = | |
1632 __ start_a_stub(size_exception_handler()); | |
1633 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1634 | |
1635 int offset = __ offset(); | |
1636 | |
727 | 1637 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1638 __ delayed()->nop(); |
1639 | |
1640 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1641 | |
1642 __ end_a_stub(); | |
1643 | |
1644 return offset; | |
1645 } | |
1646 | |
1647 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1648 // Can't use any of the current frame's registers as we may have deopted | |
1649 // at a poll and everything (including G3) can be live. | |
1650 Register temp_reg = L0; | |
727 | 1651 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1652 MacroAssembler _masm(&cbuf); |
1653 | |
1654 address base = | |
1655 __ start_a_stub(size_deopt_handler()); | |
1656 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1657 | |
1658 int offset = __ offset(); | |
1659 __ save_frame(0); | |
727 | 1660 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1661 __ delayed()->restore(); |
1662 | |
1663 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1664 | |
1665 __ end_a_stub(); | |
1666 return offset; | |
1667 | |
1668 } | |
1669 | |
1670 // Given a register encoding, produce a Integer Register object | |
1671 static Register reg_to_register_object(int register_encoding) { | |
1672 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1673 return as_Register(register_encoding); | |
1674 } | |
1675 | |
1676 // Given a register encoding, produce a single-precision Float Register object | |
1677 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1678 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1679 return as_SingleFloatRegister(register_encoding); | |
1680 } | |
1681 | |
1682 // Given a register encoding, produce a double-precision Float Register object | |
1683 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1684 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1685 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1686 return as_DoubleFloatRegister(register_encoding); | |
1687 } | |
1688 | |
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1689 const bool Matcher::match_rule_supported(int opcode) { |
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1690 if (!has_match_rule(opcode)) |
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1691 return false; |
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1692 |
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1693 switch (opcode) { |
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1694 case Op_CountLeadingZerosI: |
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1695 case Op_CountLeadingZerosL: |
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1696 case Op_CountTrailingZerosI: |
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1697 case Op_CountTrailingZerosL: |
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1698 if (!UsePopCountInstruction) |
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1699 return false; |
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1700 break; |
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1701 } |
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1702 |
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1703 return true; // Per default match rules are supported. |
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1704 } |
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1705 |
0 | 1706 int Matcher::regnum_to_fpu_offset(int regnum) { |
1707 return regnum - 32; // The FP registers are in the second chunk | |
1708 } | |
1709 | |
1710 #ifdef ASSERT | |
1711 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1712 #endif | |
1713 | |
1714 // Vector width in bytes | |
1715 const uint Matcher::vector_width_in_bytes(void) { | |
1716 return 8; | |
1717 } | |
1718 | |
1719 // Vector ideal reg | |
1720 const uint Matcher::vector_ideal_reg(void) { | |
1721 return Op_RegD; | |
1722 } | |
1723 | |
1724 // USII supports fxtof through the whole range of number, USIII doesn't | |
1725 const bool Matcher::convL2FSupported(void) { | |
1726 return VM_Version::has_fast_fxtof(); | |
1727 } | |
1728 | |
1729 // Is this branch offset short enough that a short branch can be used? | |
1730 // | |
1731 // NOTE: If the platform does not provide any short branch variants, then | |
1732 // this method should return false for offset 0. | |
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1733 bool Matcher::is_short_branch_offset(int rule, int offset) { |
0 | 1734 return false; |
1735 } | |
1736 | |
1737 const bool Matcher::isSimpleConstant64(jlong value) { | |
1738 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1739 // Depends on optimizations in MacroAssembler::setx. | |
1740 int hi = (int)(value >> 32); | |
1741 int lo = (int)(value & ~0); | |
1742 return (hi == 0) || (hi == -1) || (lo == 0); | |
1743 } | |
1744 | |
1745 // No scaling for the parameter the ClearArray node. | |
1746 const bool Matcher::init_array_count_is_in_bytes = true; | |
1747 | |
1748 // Threshold size for cleararray. | |
1749 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1750 | |
1751 // Should the Matcher clone shifts on addressing modes, expecting them to | |
1752 // be subsumed into complex addressing expressions or compute them into | |
1753 // registers? True for Intel but false for most RISCs | |
1754 const bool Matcher::clone_shift_expressions = false; | |
1755 | |
1756 // Is it better to copy float constants, or load them directly from memory? | |
1757 // Intel can load a float constant from a direct address, requiring no | |
1758 // extra registers. Most RISCs will have to materialize an address into a | |
1759 // register first, so they would do better to copy the constant from stack. | |
1760 const bool Matcher::rematerialize_float_constants = false; | |
1761 | |
1762 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1763 // needed. Else we split the double into 2 integer pieces and move it | |
1764 // piece-by-piece. Only happens when passing doubles into C code as the | |
1765 // Java calling convention forces doubles to be aligned. | |
1766 #ifdef _LP64 | |
1767 const bool Matcher::misaligned_doubles_ok = true; | |
1768 #else | |
1769 const bool Matcher::misaligned_doubles_ok = false; | |
1770 #endif | |
1771 | |
1772 // No-op on SPARC. | |
1773 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1774 } | |
1775 | |
1776 // Advertise here if the CPU requires explicit rounding operations | |
1777 // to implement the UseStrictFP mode. | |
1778 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1779 | |
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1780 // Are floats conerted to double when stored to stack during deoptimization? |
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1781 // Sparc does not handle callee-save floats. |
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1782 bool Matcher::float_in_double() { return false; } |
0 | 1783 |
1784 // Do ints take an entire long register or just half? | |
1785 // Note that we if-def off of _LP64. | |
1786 // The relevant question is how the int is callee-saved. In _LP64 | |
1787 // the whole long is written but de-opt'ing will have to extract | |
1788 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1789 #ifdef _LP64 | |
1790 const bool Matcher::int_in_long = true; | |
1791 #else | |
1792 const bool Matcher::int_in_long = false; | |
1793 #endif | |
1794 | |
1795 // Return whether or not this register is ever used as an argument. This | |
1796 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1797 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1798 // arguments in those registers not be available to the callee. | |
1799 bool Matcher::can_be_java_arg( int reg ) { | |
1800 // Standard sparc 6 args in registers | |
1801 if( reg == R_I0_num || | |
1802 reg == R_I1_num || | |
1803 reg == R_I2_num || | |
1804 reg == R_I3_num || | |
1805 reg == R_I4_num || | |
1806 reg == R_I5_num ) return true; | |
1807 #ifdef _LP64 | |
1808 // 64-bit builds can pass 64-bit pointers and longs in | |
1809 // the high I registers | |
1810 if( reg == R_I0H_num || | |
1811 reg == R_I1H_num || | |
1812 reg == R_I2H_num || | |
1813 reg == R_I3H_num || | |
1814 reg == R_I4H_num || | |
1815 reg == R_I5H_num ) return true; | |
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1816 |
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1817 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1818 return true; |
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1819 } |
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1820 |
0 | 1821 #else |
1822 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1823 // Longs cannot be passed in O regs, because O regs become I regs | |
1824 // after a 'save' and I regs get their high bits chopped off on | |
1825 // interrupt. | |
1826 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1827 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1828 #endif | |
1829 // A few float args in registers | |
1830 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1831 | |
1832 return false; | |
1833 } | |
1834 | |
1835 bool Matcher::is_spillable_arg( int reg ) { | |
1836 return can_be_java_arg(reg); | |
1837 } | |
1838 | |
1839 // Register for DIVI projection of divmodI | |
1840 RegMask Matcher::divI_proj_mask() { | |
1841 ShouldNotReachHere(); | |
1842 return RegMask(); | |
1843 } | |
1844 | |
1845 // Register for MODI projection of divmodI | |
1846 RegMask Matcher::modI_proj_mask() { | |
1847 ShouldNotReachHere(); | |
1848 return RegMask(); | |
1849 } | |
1850 | |
1851 // Register for DIVL projection of divmodL | |
1852 RegMask Matcher::divL_proj_mask() { | |
1853 ShouldNotReachHere(); | |
1854 return RegMask(); | |
1855 } | |
1856 | |
1857 // Register for MODL projection of divmodL | |
1858 RegMask Matcher::modL_proj_mask() { | |
1859 ShouldNotReachHere(); | |
1860 return RegMask(); | |
1861 } | |
1862 | |
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1863 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1567 | 1864 return L7_REGP_mask; |
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1865 } |
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1866 |
0 | 1867 %} |
1868 | |
1869 | |
1870 // The intptr_t operand types, defined by textual substitution. | |
1871 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
1872 #ifdef _LP64 | |
824 | 1873 #define immX immL |
1874 #define immX13 immL13 | |
1875 #define immX13m7 immL13m7 | |
1876 #define iRegX iRegL | |
1877 #define g1RegX g1RegL | |
0 | 1878 #else |
824 | 1879 #define immX immI |
1880 #define immX13 immI13 | |
1881 #define immX13m7 immI13m7 | |
1882 #define iRegX iRegI | |
1883 #define g1RegX g1RegI | |
0 | 1884 #endif |
1885 | |
1886 //----------ENCODING BLOCK----------------------------------------------------- | |
1887 // This block specifies the encoding classes used by the compiler to output | |
1888 // byte streams. Encoding classes are parameterized macros used by | |
1889 // Machine Instruction Nodes in order to generate the bit encoding of the | |
1890 // instruction. Operands specify their base encoding interface with the | |
1891 // interface keyword. There are currently supported four interfaces, | |
1892 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
1893 // operand to generate a function which returns its register number when | |
1894 // queried. CONST_INTER causes an operand to generate a function which | |
1895 // returns the value of the constant when queried. MEMORY_INTER causes an | |
1896 // operand to generate four functions which return the Base Register, the | |
1897 // Index Register, the Scale Value, and the Offset Value of the operand when | |
1898 // queried. COND_INTER causes an operand to generate six functions which | |
1899 // return the encoding code (ie - encoding bits for the instruction) | |
1900 // associated with each basic boolean condition for a conditional instruction. | |
1901 // | |
1902 // Instructions specify two basic values for encoding. Again, a function | |
1903 // is available to check if the constant displacement is an oop. They use the | |
1904 // ins_encode keyword to specify their encoding classes (which must be | |
1905 // a sequence of enc_class names, and their parameters, specified in | |
1906 // the encoding block), and they use the | |
1907 // opcode keyword to specify, in order, their primary, secondary, and | |
1908 // tertiary opcode. Only the opcode sections which a particular instruction | |
1909 // needs for encoding need to be specified. | |
1910 encode %{ | |
1911 enc_class enc_untested %{ | |
1912 #ifdef ASSERT | |
1913 MacroAssembler _masm(&cbuf); | |
1914 __ untested("encoding"); | |
1915 #endif | |
1916 %} | |
1917 | |
1918 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
1919 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
1920 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
1921 %} | |
1922 | |
415
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1923 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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1924 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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1925 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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1926 %} |
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1927 |
0 | 1928 enc_class form3_mem_prefetch_read( memory mem ) %{ |
415
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1929 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1930 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
1931 %} | |
1932 | |
1933 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
415
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1934 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1935 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
1936 %} | |
1937 | |
1938 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
1939 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1940 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1941 guarantee($mem$$index == R_G0_enc, "double index?"); | |
415
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1942 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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1943 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 1944 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
1945 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
1946 %} | |
1947 | |
1948 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
1949 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1950 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1951 guarantee($mem$$index == R_G0_enc, "double index?"); | |
1952 // Load long with 2 instructions | |
415
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1953 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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1954 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 1955 %} |
1956 | |
1957 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
1958 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
1959 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
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1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 1961 %} |
1962 | |
1963 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
1964 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1965 if( $rs2$$reg != $rd$$reg ) | |
1966 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
1967 %} | |
1968 | |
1969 // Target lo half of long | |
1970 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
1971 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1972 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
1973 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
1974 %} | |
1975 | |
1976 // Source lo half of long | |
1977 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
1978 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1979 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
1980 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
1981 %} | |
1982 | |
1983 // Target hi half of long | |
1984 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
1985 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
1986 %} | |
1987 | |
1988 // Source lo half of long, and leave it sign extended. | |
1989 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
1990 // Sign extend low half | |
1991 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
1992 %} | |
1993 | |
1994 // Source hi half of long, and leave it sign extended. | |
1995 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
1996 // Shift high half to low half | |
1997 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
1998 %} | |
1999 | |
2000 // Source hi half of long | |
2001 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2002 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2003 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2004 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2005 %} | |
2006 | |
2007 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2008 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2009 %} | |
2010 | |
2011 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2012 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2013 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2014 %} | |
2015 | |
2016 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2017 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2018 // clear if nothing else is happening | |
2019 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2020 // blt,a,pn done | |
2021 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2022 // mov dst,-1 in delay slot | |
2023 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2024 %} | |
2025 | |
2026 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2027 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2028 %} | |
2029 | |
2030 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2031 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2032 %} | |
2033 | |
2034 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2035 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2036 %} | |
2037 | |
2038 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2039 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2040 %} | |
2041 | |
2042 enc_class move_return_pc_to_o1() %{ | |
2043 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2044 %} | |
2045 | |
2046 #ifdef _LP64 | |
2047 /* %%% merge with enc_to_bool */ | |
2048 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2049 MacroAssembler _masm(&cbuf); | |
2050 | |
2051 Register src_reg = reg_to_register_object($src$$reg); | |
2052 Register dst_reg = reg_to_register_object($dst$$reg); | |
2053 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2054 %} | |
2055 #endif | |
2056 | |
2057 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2058 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2059 MacroAssembler _masm(&cbuf); | |
2060 | |
2061 Register p_reg = reg_to_register_object($p$$reg); | |
2062 Register q_reg = reg_to_register_object($q$$reg); | |
2063 Register y_reg = reg_to_register_object($y$$reg); | |
2064 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2065 | |
2066 __ subcc( p_reg, q_reg, p_reg ); | |
2067 __ add ( p_reg, y_reg, tmp_reg ); | |
2068 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2069 %} | |
2070 | |
2071 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2072 // fcmp %fcc0,$src,$src | |
2073 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2074 // branch %fcc0 not-nan, predict taken | |
2075 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2076 // fdtoi $src,$dst | |
2077 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2078 // fitos $dst,$dst (if nan) | |
2079 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2080 // clear $dst (if nan) | |
2081 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2082 // carry on here... | |
2083 %} | |
2084 | |
2085 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2086 // fcmp %fcc0,$src,$src check for NAN | |
2087 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2088 // branch %fcc0 not-nan, predict taken | |
2089 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2090 // fdtox $src,$dst convert in delay slot | |
2091 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2092 // fxtod $dst,$dst (if nan) | |
2093 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2094 // clear $dst (if nan) | |
2095 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2096 // carry on here... | |
2097 %} | |
2098 | |
2099 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2100 // fcmps %fcc0,$src,$src | |
2101 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2102 // branch %fcc0 not-nan, predict taken | |
2103 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2104 // fstoi $src,$dst | |
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2106 // fitos $dst,$dst (if nan) | |
2107 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2108 // clear $dst (if nan) | |
2109 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2110 // carry on here... | |
2111 %} | |
2112 | |
2113 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2114 // fcmps %fcc0,$src,$src | |
2115 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2116 // branch %fcc0 not-nan, predict taken | |
2117 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2118 // fstox $src,$dst | |
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2120 // fxtod $dst,$dst (if nan) | |
2121 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2122 // clear $dst (if nan) | |
2123 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2124 // carry on here... | |
2125 %} | |
2126 | |
2127 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2128 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2129 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2130 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2131 | |
2132 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2133 | |
2134 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2135 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2136 | |
2137 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2138 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2139 %} | |
2140 | |
2141 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2142 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2143 %} | |
2144 | |
2145 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2146 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2147 %} | |
2148 | |
2149 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2150 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2151 %} | |
2152 | |
2153 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2154 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2155 %} | |
2156 | |
2157 // Encloding class for traceable jumps | |
2158 enc_class form_jmpl(g3RegP dest) %{ | |
2159 emit_jmpl(cbuf, $dest$$reg); | |
2160 %} | |
2161 | |
2162 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2163 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2164 %} | |
2165 | |
2166 enc_class form2_nop() %{ | |
2167 emit_nop(cbuf); | |
2168 %} | |
2169 | |
2170 enc_class form2_illtrap() %{ | |
2171 emit_illtrap(cbuf); | |
2172 %} | |
2173 | |
2174 | |
2175 // Compare longs and convert into -1, 0, 1. | |
2176 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2177 // CMP $src1,$src2 | |
2178 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2179 // blt,a,pn done | |
2180 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2181 // mov dst,-1 in delay slot | |
2182 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2183 // bgt,a,pn done | |
2184 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2185 // mov dst,1 in delay slot | |
2186 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2187 // CLR $dst | |
2188 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2189 %} | |
2190 | |
2191 enc_class enc_PartialSubtypeCheck() %{ | |
2192 MacroAssembler _masm(&cbuf); | |
2193 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2194 __ delayed()->nop(); | |
2195 %} | |
2196 | |
2197 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
2198 MacroAssembler _masm(&cbuf); | |
2199 Label &L = *($labl$$label); | |
2200 Assembler::Predict predict_taken = | |
2201 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2202 | |
2203 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
2204 __ delayed()->nop(); | |
2205 %} | |
2206 | |
2207 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
2208 MacroAssembler _masm(&cbuf); | |
2209 Label &L = *($labl$$label); | |
2210 Assembler::Predict predict_taken = | |
2211 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2212 | |
2213 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
2214 __ delayed()->nop(); | |
2215 %} | |
2216 | |
2217 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
2218 MacroAssembler _masm(&cbuf); | |
2219 Label &L = *($labl$$label); | |
2220 Assembler::Predict predict_taken = | |
2221 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2222 | |
2223 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
2224 __ delayed()->nop(); | |
2225 %} | |
2226 | |
2227 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
2228 MacroAssembler _masm(&cbuf); | |
2229 Label &L = *($labl$$label); | |
2230 Assembler::Predict predict_taken = | |
2231 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2232 | |
2233 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
2234 __ delayed()->nop(); | |
2235 %} | |
2236 | |
2237 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
2238 MacroAssembler _masm(&cbuf); | |
2239 | |
2240 Register switch_reg = as_Register($switch_val$$reg); | |
2241 Register table_reg = O7; | |
2242 | |
2243 address table_base = __ address_table_constant(_index2label); | |
2244 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
2245 | |
727 | 2246 // Move table address into a register. |
2247 __ set(table_base, table_reg, rspec); | |
0 | 2248 |
2249 // Jump to base address + switch value | |
2250 __ ld_ptr(table_reg, switch_reg, table_reg); | |
2251 __ jmp(table_reg, G0); | |
2252 __ delayed()->nop(); | |
2253 | |
2254 %} | |
2255 | |
2256 enc_class enc_ba( Label labl ) %{ | |
2257 MacroAssembler _masm(&cbuf); | |
2258 Label &L = *($labl$$label); | |
2259 __ ba(false, L); | |
2260 __ delayed()->nop(); | |
2261 %} | |
2262 | |
2263 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
2264 MacroAssembler _masm(&cbuf); | |
2265 Label &L = *$labl$$label; | |
2266 Assembler::Predict predict_taken = | |
2267 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2268 | |
2269 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
2270 __ delayed()->nop(); | |
2271 %} | |
2272 | |
2273 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2274 int op = (Assembler::arith_op << 30) | | |
2275 ($dst$$reg << 25) | | |
2276 (Assembler::movcc_op3 << 19) | | |
2277 (1 << 18) | // cc2 bit for 'icc' | |
2278 ($cmp$$cmpcode << 14) | | |
2279 (0 << 13) | // select register move | |
2280 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2281 ($src$$reg << 0); | |
2282 *((int*)(cbuf.code_end())) = op; | |
2283 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2284 %} | |
2285 | |
2286 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2287 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2288 int op = (Assembler::arith_op << 30) | | |
2289 ($dst$$reg << 25) | | |
2290 (Assembler::movcc_op3 << 19) | | |
2291 (1 << 18) | // cc2 bit for 'icc' | |
2292 ($cmp$$cmpcode << 14) | | |
2293 (1 << 13) | // select immediate move | |
2294 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2295 (simm11 << 0); | |
2296 *((int*)(cbuf.code_end())) = op; | |
2297 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2298 %} | |
2299 | |
2300 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2301 int op = (Assembler::arith_op << 30) | | |
2302 ($dst$$reg << 25) | | |
2303 (Assembler::movcc_op3 << 19) | | |
2304 (0 << 18) | // cc2 bit for 'fccX' | |
2305 ($cmp$$cmpcode << 14) | | |
2306 (0 << 13) | // select register move | |
2307 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2308 ($src$$reg << 0); | |
2309 *((int*)(cbuf.code_end())) = op; | |
2310 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2311 %} | |
2312 | |
2313 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2314 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2315 int op = (Assembler::arith_op << 30) | | |
2316 ($dst$$reg << 25) | | |
2317 (Assembler::movcc_op3 << 19) | | |
2318 (0 << 18) | // cc2 bit for 'fccX' | |
2319 ($cmp$$cmpcode << 14) | | |
2320 (1 << 13) | // select immediate move | |
2321 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2322 (simm11 << 0); | |
2323 *((int*)(cbuf.code_end())) = op; | |
2324 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2325 %} | |
2326 | |
2327 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2328 int op = (Assembler::arith_op << 30) | | |
2329 ($dst$$reg << 25) | | |
2330 (Assembler::fpop2_op3 << 19) | | |
2331 (0 << 18) | | |
2332 ($cmp$$cmpcode << 14) | | |
2333 (1 << 13) | // select register move | |
2334 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2335 ($primary << 5) | // select single, double or quad | |
2336 ($src$$reg << 0); | |
2337 *((int*)(cbuf.code_end())) = op; | |
2338 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2339 %} | |
2340 | |
2341 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2342 int op = (Assembler::arith_op << 30) | | |
2343 ($dst$$reg << 25) | | |
2344 (Assembler::fpop2_op3 << 19) | | |
2345 (0 << 18) | | |
2346 ($cmp$$cmpcode << 14) | | |
2347 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2348 ($primary << 5) | // select single, double or quad | |
2349 ($src$$reg << 0); | |
2350 *((int*)(cbuf.code_end())) = op; | |
2351 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2352 %} | |
2353 | |
2354 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2355 // the condition comes from opcode-field instead of an argument. | |
2356 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2357 int op = (Assembler::arith_op << 30) | | |
2358 ($dst$$reg << 25) | | |
2359 (Assembler::movcc_op3 << 19) | | |
2360 (1 << 18) | // cc2 bit for 'icc' | |
2361 ($primary << 14) | | |
2362 (0 << 13) | // select register move | |
2363 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2364 ($src$$reg << 0); | |
2365 *((int*)(cbuf.code_end())) = op; | |
2366 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2367 %} | |
2368 | |
2369 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2370 int op = (Assembler::arith_op << 30) | | |
2371 ($dst$$reg << 25) | | |
2372 (Assembler::movcc_op3 << 19) | | |
2373 (6 << 16) | // cc2 bit for 'xcc' | |
2374 ($primary << 14) | | |
2375 (0 << 13) | // select register move | |
2376 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2377 ($src$$reg << 0); | |
2378 *((int*)(cbuf.code_end())) = op; | |
2379 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2380 %} | |
2381 | |
2382 // Utility encoding for loading a 64 bit Pointer into a register | |
2383 // The 64 bit pointer is stored in the generated code stream | |
2384 enc_class SetPtr( immP src, iRegP rd ) %{ | |
2385 Register dest = reg_to_register_object($rd$$reg); | |
727 | 2386 MacroAssembler _masm(&cbuf); |
0 | 2387 // [RGV] This next line should be generated from ADLC |
2388 if ( _opnds[1]->constant_is_oop() ) { | |
2389 intptr_t val = $src$$constant; | |
2390 __ set_oop_constant((jobject)val, dest); | |
2391 } else { // non-oop pointers, e.g. card mark base, heap top | |
727 | 2392 __ set($src$$constant, dest); |
0 | 2393 } |
2394 %} | |
2395 | |
2396 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2397 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2398 %} | |
2399 | |
2400 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2401 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2402 %} | |
2403 | |
2404 enc_class Set32( immI src, iRegI rd ) %{ | |
2405 MacroAssembler _masm(&cbuf); | |
2406 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2407 %} | |
2408 | |
2409 enc_class SetNull( iRegI rd ) %{ | |
2410 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
2411 %} | |
2412 | |
2413 enc_class call_epilog %{ | |
2414 if( VerifyStackAtCalls ) { | |
2415 MacroAssembler _masm(&cbuf); | |
2416 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2417 Register temp_reg = G3; | |
2418 __ add(SP, framesize, temp_reg); | |
2419 __ cmp(temp_reg, FP); | |
2420 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2421 } | |
2422 %} | |
2423 | |
2424 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2425 // to G1 so the register allocator will not have to deal with the misaligned register | |
2426 // pair. | |
2427 enc_class adjust_long_from_native_call %{ | |
2428 #ifndef _LP64 | |
2429 if (returns_long()) { | |
2430 // sllx O0,32,O0 | |
2431 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2432 // srl O1,0,O1 | |
2433 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2434 // or O0,O1,G1 | |
2435 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2436 } | |
2437 #endif | |
2438 %} | |
2439 | |
2440 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2441 // CALL directly to the runtime | |
2442 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2443 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
2444 /*preserve_g2=*/true, /*force far call*/true); | |
2445 %} | |
2446 | |
1567 | 2447 enc_class preserve_SP %{ |
2448 MacroAssembler _masm(&cbuf); | |
2449 __ mov(SP, L7_mh_SP_save); | |
2450 %} | |
2451 | |
2452 enc_class restore_SP %{ | |
2453 MacroAssembler _masm(&cbuf); | |
2454 __ mov(L7_mh_SP_save, SP); | |
2455 %} | |
2456 | |
0 | 2457 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2458 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2459 // who we intended to call. | |
2460 if ( !_method ) { | |
2461 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
2462 } else if (_optimized_virtual) { | |
2463 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2464 } else { | |
2465 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2466 } | |
2467 if( _method ) { // Emit stub for static call | |
2468 emit_java_to_interp(cbuf); | |
2469 } | |
2470 %} | |
2471 | |
2472 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2473 MacroAssembler _masm(&cbuf); | |
2474 __ set_inst_mark(); | |
2475 int vtable_index = this->_vtable_index; | |
2476 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2477 if (vtable_index < 0) { | |
2478 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
2479 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
2480 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2481 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2482 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
2483 // !!!!! | |
2484 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
2485 // emit_call_dynamic_prologue( cbuf ); | |
2486 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
2487 | |
2488 address virtual_call_oop_addr = __ inst_mark(); | |
2489 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2490 // who we intended to call. | |
2491 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
2492 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
2493 } else { | |
2494 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2495 // Just go thru the vtable | |
2496 // get receiver klass (receiver already checked for non-null) | |
2497 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2498 int off = __ offset(); | |
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2499 __ load_klass(O0, G3_scratch); |
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2500 int klass_load_size; |
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2501 if (UseCompressedOops) { |
642
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2502 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2503 if (Universe::narrow_oop_base() == NULL) |
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2504 klass_load_size = 2*BytesPerInstWord; |
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2505 else |
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2506 klass_load_size = 3*BytesPerInstWord; |
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2507 } else { |
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2508 klass_load_size = 1*BytesPerInstWord; |
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2509 } |
0 | 2510 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
2511 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
2512 if( __ is_simm13(v_off) ) { | |
2513 __ ld_ptr(G3, v_off, G5_method); | |
2514 } else { | |
2515 // Generate 2 instructions | |
2516 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2517 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2518 // ld_ptr, set_hi, set | |
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2519 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2520 "Unexpected instruction size(s)"); |
0 | 2521 __ ld_ptr(G3, G5_method, G5_method); |
2522 } | |
2523 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2524 // However it may very well end up in handle_wrong_method if the | |
2525 // method is abstract for the particular class. | |
2526 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
2527 // jump to target (either compiled code or c2iadapter) | |
2528 __ jmpl(G3_scratch, G0, O7); | |
2529 __ delayed()->nop(); | |
2530 } | |
2531 %} | |
2532 | |
2533 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2534 MacroAssembler _masm(&cbuf); | |
2535 | |
2536 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2537 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2538 // we might be calling a C2I adapter which needs it. | |
2539 | |
2540 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2541 // Load nmethod | |
2542 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
2543 | |
2544 // CALL to compiled java, indirect the contents of G3 | |
2545 __ set_inst_mark(); | |
2546 __ callr(temp_reg, G0); | |
2547 __ delayed()->nop(); | |
2548 %} | |
2549 | |
2550 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2551 MacroAssembler _masm(&cbuf); | |
2552 Register Rdividend = reg_to_register_object($src1$$reg); | |
2553 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2554 Register Rresult = reg_to_register_object($dst$$reg); | |
2555 | |
2556 __ sra(Rdivisor, 0, Rdivisor); | |
2557 __ sra(Rdividend, 0, Rdividend); | |
2558 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2559 %} | |
2560 | |
2561 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2562 MacroAssembler _masm(&cbuf); | |
2563 | |
2564 Register Rdividend = reg_to_register_object($src1$$reg); | |
2565 int divisor = $imm$$constant; | |
2566 Register Rresult = reg_to_register_object($dst$$reg); | |
2567 | |
2568 __ sra(Rdividend, 0, Rdividend); | |
2569 __ sdivx(Rdividend, divisor, Rresult); | |
2570 %} | |
2571 | |
2572 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2573 MacroAssembler _masm(&cbuf); | |
2574 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2575 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2576 Register Rdst = reg_to_register_object($dst$$reg); | |
2577 | |
2578 __ sra( Rsrc1, 0, Rsrc1 ); | |
2579 __ sra( Rsrc2, 0, Rsrc2 ); | |
2580 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2581 __ srlx( Rdst, 32, Rdst ); | |
2582 %} | |
2583 | |
2584 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2585 MacroAssembler _masm(&cbuf); | |
2586 Register Rdividend = reg_to_register_object($src1$$reg); | |
2587 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2588 Register Rresult = reg_to_register_object($dst$$reg); | |
2589 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2590 | |
2591 assert(Rdividend != Rscratch, ""); | |
2592 assert(Rdivisor != Rscratch, ""); | |
2593 | |
2594 __ sra(Rdividend, 0, Rdividend); | |
2595 __ sra(Rdivisor, 0, Rdivisor); | |
2596 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2597 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2598 __ sub(Rdividend, Rscratch, Rresult); | |
2599 %} | |
2600 | |
2601 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2602 MacroAssembler _masm(&cbuf); | |
2603 | |
2604 Register Rdividend = reg_to_register_object($src1$$reg); | |
2605 int divisor = $imm$$constant; | |
2606 Register Rresult = reg_to_register_object($dst$$reg); | |
2607 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2608 | |
2609 assert(Rdividend != Rscratch, ""); | |
2610 | |
2611 __ sra(Rdividend, 0, Rdividend); | |
2612 __ sdivx(Rdividend, divisor, Rscratch); | |
2613 __ mulx(Rscratch, divisor, Rscratch); | |
2614 __ sub(Rdividend, Rscratch, Rresult); | |
2615 %} | |
2616 | |
2617 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2618 MacroAssembler _masm(&cbuf); | |
2619 | |
2620 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2621 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2622 | |
2623 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2624 %} | |
2625 | |
2626 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2627 MacroAssembler _masm(&cbuf); | |
2628 | |
2629 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2630 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2631 | |
2632 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2633 %} | |
2634 | |
2635 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2636 MacroAssembler _masm(&cbuf); | |
2637 | |
2638 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2639 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2640 | |
2641 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2642 %} | |
2643 | |
2644 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2645 MacroAssembler _masm(&cbuf); | |
2646 | |
2647 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2648 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2649 | |
2650 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2651 %} | |
2652 | |
2653 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2654 MacroAssembler _masm(&cbuf); | |
2655 | |
2656 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2657 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2658 | |
2659 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2660 %} | |
2661 | |
2662 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2663 MacroAssembler _masm(&cbuf); | |
2664 | |
2665 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2666 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2667 | |
2668 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2669 %} | |
2670 | |
2671 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2672 MacroAssembler _masm(&cbuf); | |
2673 | |
2674 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2675 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2676 | |
2677 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2678 %} | |
2679 | |
2680 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2681 MacroAssembler _masm(&cbuf); | |
2682 | |
2683 Register Roop = reg_to_register_object($oop$$reg); | |
2684 Register Rbox = reg_to_register_object($box$$reg); | |
2685 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2686 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2687 | |
2688 assert(Roop != Rscratch, ""); | |
2689 assert(Roop != Rmark, ""); | |
2690 assert(Rbox != Rscratch, ""); | |
2691 assert(Rbox != Rmark, ""); | |
2692 | |
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2693 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2694 %} |
2695 | |
2696 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2697 MacroAssembler _masm(&cbuf); | |
2698 | |
2699 Register Roop = reg_to_register_object($oop$$reg); | |
2700 Register Rbox = reg_to_register_object($box$$reg); | |
2701 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2702 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2703 | |
2704 assert(Roop != Rscratch, ""); | |
2705 assert(Roop != Rmark, ""); | |
2706 assert(Rbox != Rscratch, ""); | |
2707 assert(Rbox != Rmark, ""); | |
2708 | |
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2709 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2710 %} |
2711 | |
2712 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2713 MacroAssembler _masm(&cbuf); | |
2714 Register Rmem = reg_to_register_object($mem$$reg); | |
2715 Register Rold = reg_to_register_object($old$$reg); | |
2716 Register Rnew = reg_to_register_object($new$$reg); | |
2717 | |
2718 // casx_under_lock picks 1 of 3 encodings: | |
2719 // For 32-bit pointers you get a 32-bit CAS | |
2720 // For 64-bit pointers you get a 64-bit CASX | |
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2721 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2722 __ cmp( Rold, Rnew ); |
2723 %} | |
2724 | |
2725 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2726 Register Rmem = reg_to_register_object($mem$$reg); | |
2727 Register Rold = reg_to_register_object($old$$reg); | |
2728 Register Rnew = reg_to_register_object($new$$reg); | |
2729 | |
2730 MacroAssembler _masm(&cbuf); | |
2731 __ mov(Rnew, O7); | |
2732 __ casx(Rmem, Rold, O7); | |
2733 __ cmp( Rold, O7 ); | |
2734 %} | |
2735 | |
2736 // raw int cas, used for compareAndSwap | |
2737 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2738 Register Rmem = reg_to_register_object($mem$$reg); | |
2739 Register Rold = reg_to_register_object($old$$reg); | |
2740 Register Rnew = reg_to_register_object($new$$reg); | |
2741 | |
2742 MacroAssembler _masm(&cbuf); | |
2743 __ mov(Rnew, O7); | |
2744 __ cas(Rmem, Rold, O7); | |
2745 __ cmp( Rold, O7 ); | |
2746 %} | |
2747 | |
2748 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2749 Register Rres = reg_to_register_object($res$$reg); | |
2750 | |
2751 MacroAssembler _masm(&cbuf); | |
2752 __ mov(1, Rres); | |
2753 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2754 %} | |
2755 | |
2756 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2757 Register Rres = reg_to_register_object($res$$reg); | |
2758 | |
2759 MacroAssembler _masm(&cbuf); | |
2760 __ mov(1, Rres); | |
2761 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2762 %} | |
2763 | |
2764 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2765 MacroAssembler _masm(&cbuf); | |
2766 Register Rdst = reg_to_register_object($dst$$reg); | |
2767 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2768 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2769 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2770 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2771 | |
2772 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2773 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2774 %} | |
2775 | |
2776 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
2777 MacroAssembler _masm(&cbuf); | |
2778 Register dest = reg_to_register_object($dst$$reg); | |
2779 Register temp = reg_to_register_object($tmp$$reg); | |
2780 __ set64( $src$$constant, dest, temp ); | |
2781 %} | |
2782 | |
2783 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
2784 // Load a constant replicated "count" times with width "width" | |
2785 int bit_width = $width$$constant * 8; | |
2786 jlong elt_val = $src$$constant; | |
2787 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
2788 jlong val = elt_val; | |
2789 for (int i = 0; i < $count$$constant - 1; i++) { | |
2790 val <<= bit_width; | |
2791 val |= elt_val; | |
2792 } | |
2793 jdouble dval = *(jdouble*)&val; // coerce to double type | |
727 | 2794 MacroAssembler _masm(&cbuf); |
2795 address double_address = __ double_constant(dval); | |
0 | 2796 RelocationHolder rspec = internal_word_Relocation::spec(double_address); |
727 | 2797 AddressLiteral addrlit(double_address, rspec); |
2798 | |
2799 __ sethi(addrlit, $tmp$$Register); | |
732
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2800 // XXX This is a quick fix for 6833573. |
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|
2801 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
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2802 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
0 | 2803 %} |
2804 | |
2805 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
2806 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
2807 MacroAssembler _masm(&cbuf); | |
2808 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
2809 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
2810 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
2811 | |
2812 Label loop; | |
2813 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
2814 | |
2815 // Loop and clear, walking backwards through the array. | |
2816 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
2817 __ bind(loop); | |
2818 __ deccc(nof_bytes_tmp, 8); | |
2819 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
2820 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
2821 // %%%% this mini-loop must not cross a cache boundary! | |
2822 %} | |
2823 | |
2824 | |
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2825 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2826 Label Ldone, Lloop; |
2827 MacroAssembler _masm(&cbuf); | |
2828 | |
2829 Register str1_reg = reg_to_register_object($str1$$reg); | |
2830 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2831 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2832 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2833 Register result_reg = reg_to_register_object($result$$reg); |
2834 | |
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2835 assert(result_reg != str1_reg && |
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|
2836 result_reg != str2_reg && |
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2837 result_reg != cnt1_reg && |
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|
2838 result_reg != cnt2_reg , |
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|
2839 "need different registers"); |
0 | 2840 |
2841 // Compute the minimum of the string lengths(str1_reg) and the | |
2842 // difference of the string lengths (stack) | |
2843 | |
2844 // See if the lengths are different, and calculate min in str1_reg. | |
2845 // Stash diff in O7 in case we need it for a tie-breaker. | |
2846 Label Lskip; | |
986
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2847 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2848 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2849 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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2850 // cnt2 is shorter, so use its count: |
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2851 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2852 __ bind(Lskip); |
2853 | |
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2854 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2855 // Note: limit_reg holds the string length pre-scaled by 2 |
986
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2856 Register limit_reg = cnt1_reg; |
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2857 Register chr2_reg = cnt2_reg; |
0 | 2858 Register chr1_reg = result_reg; |
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2859 // str{12} are the base pointers |
0 | 2860 |
2861 // Is the minimum length zero? | |
2862 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2863 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2864 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2865 | |
2866 // Load first characters | |
986
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2867 __ lduh(str1_reg, 0, chr1_reg); |
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2868 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2869 |
2870 // Compare first characters | |
2871 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2872 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2873 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2874 __ delayed()->nop(); | |
2875 | |
2876 { | |
2877 // Check after comparing first character to see if strings are equivalent | |
2878 Label LSkip2; | |
2879 // Check if the strings start at same location | |
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2880 __ cmp(str1_reg, str2_reg); |
0 | 2881 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2882 __ delayed()->nop(); | |
2883 | |
2884 // Check if the length difference is zero (in O7) | |
2885 __ cmp(G0, O7); | |
2886 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2887 __ delayed()->mov(G0, result_reg); // result is zero | |
2888 | |
2889 // Strings might not be equal | |
2890 __ bind(LSkip2); | |
2891 } | |
2892 | |
2893 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2894 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2895 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2896 | |
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2897 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2898 __ add(str1_reg, limit_reg, str1_reg); |
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2899 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2900 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2901 | |
2902 // Compare the rest of the characters | |
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2903 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2904 __ bind(Lloop); |
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2905 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2906 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2907 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2908 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2909 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2910 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2911 // annul LDUH if branch is not taken to prevent access past end of string | |
2912 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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2913 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2914 |
2915 // If strings are equal up to min length, return the length difference. | |
2916 __ mov(O7, result_reg); | |
2917 | |
2918 // Otherwise, return the difference between the first mismatched chars. | |
2919 __ bind(Ldone); | |
2920 %} | |
2921 | |
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|
2922 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2923 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2924 MacroAssembler _masm(&cbuf); |
2925 | |
2926 Register str1_reg = reg_to_register_object($str1$$reg); | |
2927 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2928 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2929 Register tmp1_reg = O7; |
681 | 2930 Register result_reg = reg_to_register_object($result$$reg); |
2931 | |
986
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2932 assert(result_reg != str1_reg && |
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2933 result_reg != str2_reg && |
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2934 result_reg != cnt_reg && |
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2935 result_reg != tmp1_reg , |
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2936 "need different registers"); |
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2937 |
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2938 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2939 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2940 __ delayed()->add(G0, 1, result_reg); | |
2941 | |
986
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2942 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
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2943 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2944 |
681 | 2945 //rename registers |
986
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2946 Register limit_reg = cnt_reg; |
681 | 2947 Register chr1_reg = result_reg; |
986
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2948 Register chr2_reg = tmp1_reg; |
681 | 2949 |
2950 //check for alignment and position the pointers to the ends | |
986
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2951 __ or3(str1_reg, str2_reg, chr1_reg); |
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2952 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2953 // notZero means at least one not 4-byte aligned. |
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2954 // We could optimize the case when both arrays are not aligned |
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2955 // but it is not frequent case and it requires additional checks. |
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2956 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2957 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2958 |
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2959 // Compare char[] arrays aligned to 4 bytes. |
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2960 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2961 chr1_reg, chr2_reg, Ldone); |
681 | 2962 __ ba(false,Ldone); |
2963 __ delayed()->add(G0, 1, result_reg); | |
2964 | |
986
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2965 // char by char compare |
681 | 2966 __ bind(Lchar); |
986
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2967 __ add(str1_reg, limit_reg, str1_reg); |
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2968 __ add(str2_reg, limit_reg, str2_reg); |
681 | 2969 __ neg(limit_reg); //negate count |
2970 | |
986
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2971 __ lduh(str1_reg, limit_reg, chr1_reg); |
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2972 // Lchar_loop |
681 | 2973 __ bind(Lchar_loop); |
986
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2974 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 2975 __ cmp(chr1_reg, chr2_reg); |
2976 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
2977 __ delayed()->mov(G0, result_reg); //not equal | |
2978 __ inccc(limit_reg, sizeof(jchar)); | |
2979 // annul LDUH if branch is not taken to prevent access past end of string | |
986
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2980 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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2981 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 2982 |
2983 __ add(G0, 1, result_reg); //equal | |
2984 | |
2985 __ bind(Ldone); | |
2986 %} | |
2987 | |
986
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2988 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 2989 Label Lvector, Ldone, Lloop; |
2990 MacroAssembler _masm(&cbuf); | |
2991 | |
2992 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
2993 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
2994 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
986
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2995 Register tmp2_reg = O7; |
681 | 2996 Register result_reg = reg_to_register_object($result$$reg); |
2997 | |
2998 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
2999 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3000 | |
3001 // return true if the same array | |
3002 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3003 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3004 __ delayed()->add(G0, 1, result_reg); // equal |
3005 | |
3006 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3007 __ delayed()->mov(G0, result_reg); // not equal | |
3008 | |
3009 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3010 __ delayed()->mov(G0, result_reg); // not equal | |
3011 | |
3012 //load the lengths of arrays | |
727 | 3013 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3014 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3015 |
3016 // return false if the two arrays are not equal length | |
3017 __ cmp(tmp1_reg, tmp2_reg); | |
3018 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3019 __ delayed()->mov(G0, result_reg); // not equal | |
3020 | |
986
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3021 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
681 | 3022 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3023 | |
3024 // load array addresses | |
3025 __ add(ary1_reg, base_offset, ary1_reg); | |
3026 __ add(ary2_reg, base_offset, ary2_reg); | |
3027 | |
3028 // renaming registers | |
986
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3029 Register chr1_reg = result_reg; // for characters in ary1 |
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3030 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3031 Register limit_reg = tmp1_reg; // length |
3032 | |
3033 // set byte count | |
3034 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
986
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3035 |
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3036 // Compare char[] arrays aligned to 4 bytes. |
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3037 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3038 chr1_reg, chr2_reg, Ldone); |
681 | 3039 __ add(G0, 1, result_reg); // equals |
3040 | |
3041 __ bind(Ldone); | |
3042 %} | |
3043 | |
0 | 3044 enc_class enc_rethrow() %{ |
3045 cbuf.set_inst_mark(); | |
3046 Register temp_reg = G3; | |
727 | 3047 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3048 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3049 MacroAssembler _masm(&cbuf); | |
3050 #ifdef ASSERT | |
3051 __ save_frame(0); | |
727 | 3052 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3053 __ sethi(last_rethrow_addrlit, L1); | |
3054 Address addr(L1, last_rethrow_addrlit.low10()); | |
0 | 3055 __ get_pc(L2); |
3056 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
727 | 3057 __ st_ptr(L2, addr); |
0 | 3058 __ restore(); |
3059 #endif | |
727 | 3060 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3061 __ delayed()->nop(); |
3062 %} | |
3063 | |
3064 enc_class emit_mem_nop() %{ | |
3065 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
3066 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3067 *code = (unsigned int)0xc0839040; | |
3068 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3069 %} | |
3070 | |
3071 enc_class emit_fadd_nop() %{ | |
3072 // Generates the instruction FMOVS f31,f31 | |
3073 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3074 *code = (unsigned int)0xbfa0003f; | |
3075 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3076 %} | |
3077 | |
3078 enc_class emit_br_nop() %{ | |
3079 // Generates the instruction BPN,PN . | |
3080 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3081 *code = (unsigned int)0x00400000; | |
3082 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3083 %} | |
3084 | |
3085 enc_class enc_membar_acquire %{ | |
3086 MacroAssembler _masm(&cbuf); | |
3087 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3088 %} | |
3089 | |
3090 enc_class enc_membar_release %{ | |
3091 MacroAssembler _masm(&cbuf); | |
3092 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3093 %} | |
3094 | |
3095 enc_class enc_membar_volatile %{ | |
3096 MacroAssembler _masm(&cbuf); | |
3097 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3098 %} | |
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3099 |
0 | 3100 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
3101 MacroAssembler _masm(&cbuf); | |
3102 Register src_reg = reg_to_register_object($src$$reg); | |
3103 Register dst_reg = reg_to_register_object($dst$$reg); | |
3104 __ sllx(src_reg, 56, dst_reg); | |
3105 __ srlx(dst_reg, 8, O7); | |
3106 __ or3 (dst_reg, O7, dst_reg); | |
3107 __ srlx(dst_reg, 16, O7); | |
3108 __ or3 (dst_reg, O7, dst_reg); | |
3109 __ srlx(dst_reg, 32, O7); | |
3110 __ or3 (dst_reg, O7, dst_reg); | |
3111 %} | |
3112 | |
3113 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
3114 MacroAssembler _masm(&cbuf); | |
3115 Register src_reg = reg_to_register_object($src$$reg); | |
3116 Register dst_reg = reg_to_register_object($dst$$reg); | |
3117 __ sll(src_reg, 24, dst_reg); | |
3118 __ srl(dst_reg, 8, O7); | |
3119 __ or3(dst_reg, O7, dst_reg); | |
3120 __ srl(dst_reg, 16, O7); | |
3121 __ or3(dst_reg, O7, dst_reg); | |
3122 %} | |
3123 | |
3124 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
3125 MacroAssembler _masm(&cbuf); | |
3126 Register src_reg = reg_to_register_object($src$$reg); | |
3127 Register dst_reg = reg_to_register_object($dst$$reg); | |
3128 __ sllx(src_reg, 48, dst_reg); | |
3129 __ srlx(dst_reg, 16, O7); | |
3130 __ or3 (dst_reg, O7, dst_reg); | |
3131 __ srlx(dst_reg, 32, O7); | |
3132 __ or3 (dst_reg, O7, dst_reg); | |
3133 %} | |
3134 | |
3135 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
3136 MacroAssembler _masm(&cbuf); | |
3137 Register src_reg = reg_to_register_object($src$$reg); | |
3138 Register dst_reg = reg_to_register_object($dst$$reg); | |
3139 __ sllx(src_reg, 32, dst_reg); | |
3140 __ srlx(dst_reg, 32, O7); | |
3141 __ or3 (dst_reg, O7, dst_reg); | |
3142 %} | |
3143 | |
3144 %} | |
3145 | |
3146 //----------FRAME-------------------------------------------------------------- | |
3147 // Definition of frame structure and management information. | |
3148 // | |
3149 // S T A C K L A Y O U T Allocators stack-slot number | |
3150 // | (to get allocators register number | |
3151 // G Owned by | | v add VMRegImpl::stack0) | |
3152 // r CALLER | | | |
3153 // o | +--------+ pad to even-align allocators stack-slot | |
3154 // w V | pad0 | numbers; owned by CALLER | |
3155 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3156 // h ^ | in | 5 | |
3157 // | | args | 4 Holes in incoming args owned by SELF | |
3158 // | | | | 3 | |
3159 // | | +--------+ | |
3160 // V | | old out| Empty on Intel, window on Sparc | |
3161 // | old |preserve| Must be even aligned. | |
3162 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3163 // | | in | 3 area for Intel ret address | |
3164 // Owned by |preserve| Empty on Sparc. | |
3165 // SELF +--------+ | |
3166 // | | pad2 | 2 pad to align old SP | |
3167 // | +--------+ 1 | |
3168 // | | locks | 0 | |
3169 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3170 // | | pad1 | 11 pad to align new SP | |
3171 // | +--------+ | |
3172 // | | | 10 | |
3173 // | | spills | 9 spills | |
3174 // V | | 8 (pad0 slot for callee) | |
3175 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3176 // ^ | out | 7 | |
3177 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3178 // Owned by +--------+ | |
3179 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3180 // | new |preserve| Must be even-aligned. | |
3181 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3182 // | | | | |
3183 // | |
3184 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3185 // known from SELF's arguments and the Java calling convention. | |
3186 // Region 6-7 is determined per call site. | |
3187 // Note 2: If the calling convention leaves holes in the incoming argument | |
3188 // area, those holes are owned by SELF. Holes in the outgoing area | |
3189 // are owned by the CALLEE. Holes should not be nessecary in the | |
3190 // incoming area, as the Java calling convention is completely under | |
3191 // the control of the AD file. Doubles can be sorted and packed to | |
3192 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3193 // varargs C calling conventions. | |
3194 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3195 // even aligned with pad0 as needed. | |
3196 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3197 // region 6-11 is even aligned; it may be padded out more so that | |
3198 // the region from SP to FP meets the minimum stack alignment. | |
3199 | |
3200 frame %{ | |
3201 // What direction does stack grow in (assumed to be same for native & Java) | |
3202 stack_direction(TOWARDS_LOW); | |
3203 | |
3204 // These two registers define part of the calling convention | |
3205 // between compiled code and the interpreter. | |
3206 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
3207 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
3208 | |
3209 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3210 cisc_spilling_operand_name(indOffset); | |
3211 | |
3212 // Number of stack slots consumed by a Monitor enter | |
3213 #ifdef _LP64 | |
3214 sync_stack_slots(2); | |
3215 #else | |
3216 sync_stack_slots(1); | |
3217 #endif | |
3218 | |
3219 // Compiled code's Frame Pointer | |
3220 frame_pointer(R_SP); | |
3221 | |
3222 // Stack alignment requirement | |
3223 stack_alignment(StackAlignmentInBytes); | |
3224 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3225 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3226 | |
3227 // Number of stack slots between incoming argument block and the start of | |
3228 // a new frame. The PROLOG must add this many slots to the stack. The | |
3229 // EPILOG must remove this many slots. | |
3230 in_preserve_stack_slots(0); | |
3231 | |
3232 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3233 // for calls to C. Supports the var-args backing area for register parms. | |
3234 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3235 #ifdef _LP64 | |
3236 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3237 varargs_C_out_slots_killed(12); | |
3238 #else | |
3239 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3240 varargs_C_out_slots_killed( 7); | |
3241 #endif | |
3242 | |
3243 // The after-PROLOG location of the return address. Location of | |
3244 // return address specifies a type (REG or STACK) and a number | |
3245 // representing the register number (i.e. - use a register name) or | |
3246 // stack slot. | |
3247 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3248 | |
3249 // Body of function which returns an OptoRegs array locating | |
3250 // arguments either in registers or in stack slots for calling | |
3251 // java | |
3252 calling_convention %{ | |
3253 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3254 | |
3255 %} | |
3256 | |
3257 // Body of function which returns an OptoRegs array locating | |
3258 // arguments either in registers or in stack slots for callin | |
3259 // C. | |
3260 c_calling_convention %{ | |
3261 // This is obviously always outgoing | |
3262 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3263 %} | |
3264 | |
3265 // Location of native (C/C++) and interpreter return values. This is specified to | |
3266 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3267 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3268 // to and from the register pairs is done by the appropriate call and epilog | |
3269 // opcodes. This simplifies the register allocator. | |
3270 c_return_value %{ | |
3271 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3272 #ifdef _LP64 | |
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3273 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3274 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3275 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3276 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3277 #else // !_LP64 |
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3278 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3279 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3280 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3281 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3282 #endif |
3283 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3284 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3285 %} | |
3286 | |
3287 // Location of compiled Java return values. Same as C | |
3288 return_value %{ | |
3289 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3290 #ifdef _LP64 | |
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3291 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3292 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3293 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3294 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3295 #else // !_LP64 |
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3296 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3297 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3298 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3299 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3300 #endif |
3301 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3302 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3303 %} | |
3304 | |
3305 %} | |
3306 | |
3307 | |
3308 //----------ATTRIBUTES--------------------------------------------------------- | |
3309 //----------Operand Attributes------------------------------------------------- | |
3310 op_attrib op_cost(1); // Required cost attribute | |
3311 | |
3312 //----------Instruction Attributes--------------------------------------------- | |
3313 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3314 ins_attrib ins_size(32); // Required size attribute (in bits) | |
3315 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
3316 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
3317 // non-matching short branch variant of some | |
3318 // long branch? | |
3319 | |
3320 //----------OPERANDS----------------------------------------------------------- | |
3321 // Operand definitions must precede instruction definitions for correct parsing | |
3322 // in the ADLC because operands constitute user defined types which are used in | |
3323 // instruction definitions. | |
3324 | |
3325 //----------Simple Operands---------------------------------------------------- | |
3326 // Immediate Operands | |
3327 // Integer Immediate: 32-bit | |
3328 operand immI() %{ | |
3329 match(ConI); | |
3330 | |
3331 op_cost(0); | |
3332 // formats are generated automatically for constants and base registers | |
3333 format %{ %} | |
3334 interface(CONST_INTER); | |
3335 %} | |
3336 | |
824 | 3337 // Integer Immediate: 8-bit |
3338 operand immI8() %{ | |
3339 predicate(Assembler::is_simm(n->get_int(), 8)); | |
3340 match(ConI); | |
3341 op_cost(0); | |
3342 format %{ %} | |
3343 interface(CONST_INTER); | |
3344 %} | |
3345 | |
0 | 3346 // Integer Immediate: 13-bit |
3347 operand immI13() %{ | |
3348 predicate(Assembler::is_simm13(n->get_int())); | |
3349 match(ConI); | |
3350 op_cost(0); | |
3351 | |
3352 format %{ %} | |
3353 interface(CONST_INTER); | |
3354 %} | |
3355 | |
785 | 3356 // Integer Immediate: 13-bit minus 7 |
3357 operand immI13m7() %{ | |
3358 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3359 match(ConI); | |
3360 op_cost(0); | |
3361 | |
3362 format %{ %} | |
3363 interface(CONST_INTER); | |
3364 %} | |
3365 | |
824 | 3366 // Integer Immediate: 16-bit |
3367 operand immI16() %{ | |
3368 predicate(Assembler::is_simm(n->get_int(), 16)); | |
3369 match(ConI); | |
3370 op_cost(0); | |
3371 format %{ %} | |
3372 interface(CONST_INTER); | |
3373 %} | |
3374 | |
0 | 3375 // Unsigned (positive) Integer Immediate: 13-bit |
3376 operand immU13() %{ | |
3377 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3378 match(ConI); | |
3379 op_cost(0); | |
3380 | |
3381 format %{ %} | |
3382 interface(CONST_INTER); | |
3383 %} | |
3384 | |
3385 // Integer Immediate: 6-bit | |
3386 operand immU6() %{ | |
3387 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3388 match(ConI); | |
3389 op_cost(0); | |
3390 format %{ %} | |
3391 interface(CONST_INTER); | |
3392 %} | |
3393 | |
3394 // Integer Immediate: 11-bit | |
3395 operand immI11() %{ | |
3396 predicate(Assembler::is_simm(n->get_int(),11)); | |
3397 match(ConI); | |
3398 op_cost(0); | |
3399 format %{ %} | |
3400 interface(CONST_INTER); | |
3401 %} | |
3402 | |
3403 // Integer Immediate: 0-bit | |
3404 operand immI0() %{ | |
3405 predicate(n->get_int() == 0); | |
3406 match(ConI); | |
3407 op_cost(0); | |
3408 | |
3409 format %{ %} | |
3410 interface(CONST_INTER); | |
3411 %} | |
3412 | |
3413 // Integer Immediate: the value 10 | |
3414 operand immI10() %{ | |
3415 predicate(n->get_int() == 10); | |
3416 match(ConI); | |
3417 op_cost(0); | |
3418 | |
3419 format %{ %} | |
3420 interface(CONST_INTER); | |
3421 %} | |
3422 | |
3423 // Integer Immediate: the values 0-31 | |
3424 operand immU5() %{ | |
3425 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3426 match(ConI); | |
3427 op_cost(0); | |
3428 | |
3429 format %{ %} | |
3430 interface(CONST_INTER); | |
3431 %} | |
3432 | |
3433 // Integer Immediate: the values 1-31 | |
3434 operand immI_1_31() %{ | |
3435 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3436 match(ConI); | |
3437 op_cost(0); | |
3438 | |
3439 format %{ %} | |
3440 interface(CONST_INTER); | |
3441 %} | |
3442 | |
3443 // Integer Immediate: the values 32-63 | |
3444 operand immI_32_63() %{ | |
3445 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3446 match(ConI); | |
3447 op_cost(0); | |
3448 | |
3449 format %{ %} | |
3450 interface(CONST_INTER); | |
3451 %} | |
3452 | |
785 | 3453 // Immediates for special shifts (sign extend) |
3454 | |
3455 // Integer Immediate: the value 16 | |
3456 operand immI_16() %{ | |
3457 predicate(n->get_int() == 16); | |
3458 match(ConI); | |
3459 op_cost(0); | |
3460 | |
3461 format %{ %} | |
3462 interface(CONST_INTER); | |
3463 %} | |
3464 | |
3465 // Integer Immediate: the value 24 | |
3466 operand immI_24() %{ | |
3467 predicate(n->get_int() == 24); | |
3468 match(ConI); | |
3469 op_cost(0); | |
3470 | |
3471 format %{ %} | |
3472 interface(CONST_INTER); | |
3473 %} | |
3474 | |
0 | 3475 // Integer Immediate: the value 255 |
3476 operand immI_255() %{ | |
3477 predicate( n->get_int() == 255 ); | |
3478 match(ConI); | |
3479 op_cost(0); | |
3480 | |
3481 format %{ %} | |
3482 interface(CONST_INTER); | |
3483 %} | |
3484 | |
785 | 3485 // Integer Immediate: the value 65535 |
3486 operand immI_65535() %{ | |
3487 predicate(n->get_int() == 65535); | |
3488 match(ConI); | |
3489 op_cost(0); | |
3490 | |
3491 format %{ %} | |
3492 interface(CONST_INTER); | |
3493 %} | |
3494 | |
0 | 3495 // Long Immediate: the value FF |
3496 operand immL_FF() %{ | |
3497 predicate( n->get_long() == 0xFFL ); | |
3498 match(ConL); | |
3499 op_cost(0); | |
3500 | |
3501 format %{ %} | |
3502 interface(CONST_INTER); | |
3503 %} | |
3504 | |
3505 // Long Immediate: the value FFFF | |
3506 operand immL_FFFF() %{ | |
3507 predicate( n->get_long() == 0xFFFFL ); | |
3508 match(ConL); | |
3509 op_cost(0); | |
3510 | |
3511 format %{ %} | |
3512 interface(CONST_INTER); | |
3513 %} | |
3514 | |
3515 // Pointer Immediate: 32 or 64-bit | |
3516 operand immP() %{ | |
3517 match(ConP); | |
3518 | |
3519 op_cost(5); | |
3520 // formats are generated automatically for constants and base registers | |
3521 format %{ %} | |
3522 interface(CONST_INTER); | |
3523 %} | |
3524 | |
3525 operand immP13() %{ | |
3526 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3527 match(ConP); | |
3528 op_cost(0); | |
3529 | |
3530 format %{ %} | |
3531 interface(CONST_INTER); | |
3532 %} | |
3533 | |
3534 operand immP0() %{ | |
3535 predicate(n->get_ptr() == 0); | |
3536 match(ConP); | |
3537 op_cost(0); | |
3538 | |
3539 format %{ %} | |
3540 interface(CONST_INTER); | |
3541 %} | |
3542 | |
3543 operand immP_poll() %{ | |
3544 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3545 match(ConP); | |
3546 | |
3547 // formats are generated automatically for constants and base registers | |
3548 format %{ %} | |
3549 interface(CONST_INTER); | |
3550 %} | |
3551 | |
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3552 // Pointer Immediate |
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3553 operand immN() |
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3554 %{ |
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3555 match(ConN); |
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3556 |
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3557 op_cost(10); |
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3558 format %{ %} |
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3559 interface(CONST_INTER); |
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3560 %} |
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3561 |
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3562 // NULL Pointer Immediate |
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3563 operand immN0() |
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3564 %{ |
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3565 predicate(n->get_narrowcon() == 0); |
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3566 match(ConN); |
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3567 |
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3568 op_cost(0); |
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3569 format %{ %} |
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3570 interface(CONST_INTER); |
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3571 %} |
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3572 |
0 | 3573 operand immL() %{ |
3574 match(ConL); | |
3575 op_cost(40); | |
3576 // formats are generated automatically for constants and base registers | |
3577 format %{ %} | |
3578 interface(CONST_INTER); | |
3579 %} | |
3580 | |
3581 operand immL0() %{ | |
3582 predicate(n->get_long() == 0L); | |
3583 match(ConL); | |
3584 op_cost(0); | |
3585 // formats are generated automatically for constants and base registers | |
3586 format %{ %} | |
3587 interface(CONST_INTER); | |
3588 %} | |
3589 | |
3590 // Long Immediate: 13-bit | |
3591 operand immL13() %{ | |
3592 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3593 match(ConL); | |
3594 op_cost(0); | |
3595 | |
3596 format %{ %} | |
3597 interface(CONST_INTER); | |
3598 %} | |
3599 | |
785 | 3600 // Long Immediate: 13-bit minus 7 |
3601 operand immL13m7() %{ | |
3602 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3603 match(ConL); | |
3604 op_cost(0); | |
3605 | |
3606 format %{ %} | |
3607 interface(CONST_INTER); | |
3608 %} | |
3609 | |
0 | 3610 // Long Immediate: low 32-bit mask |
3611 operand immL_32bits() %{ | |
3612 predicate(n->get_long() == 0xFFFFFFFFL); | |
3613 match(ConL); | |
3614 op_cost(0); | |
3615 | |
3616 format %{ %} | |
3617 interface(CONST_INTER); | |
3618 %} | |
3619 | |
3620 // Double Immediate | |
3621 operand immD() %{ | |
3622 match(ConD); | |
3623 | |
3624 op_cost(40); | |
3625 format %{ %} | |
3626 interface(CONST_INTER); | |
3627 %} | |
3628 | |
3629 operand immD0() %{ | |
3630 #ifdef _LP64 | |
3631 // on 64-bit architectures this comparision is faster | |
3632 predicate(jlong_cast(n->getd()) == 0); | |
3633 #else | |
3634 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3635 #endif | |
3636 match(ConD); | |
3637 | |
3638 op_cost(0); | |
3639 format %{ %} | |
3640 interface(CONST_INTER); | |
3641 %} | |
3642 | |
3643 // Float Immediate | |
3644 operand immF() %{ | |
3645 match(ConF); | |
3646 | |
3647 op_cost(20); | |
3648 format %{ %} | |
3649 interface(CONST_INTER); | |
3650 %} | |
3651 | |
3652 // Float Immediate: 0 | |
3653 operand immF0() %{ | |
3654 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3655 match(ConF); | |
3656 | |
3657 op_cost(0); | |
3658 format %{ %} | |
3659 interface(CONST_INTER); | |
3660 %} | |
3661 | |
3662 // Integer Register Operands | |
3663 // Integer Register | |
3664 operand iRegI() %{ | |
3665 constraint(ALLOC_IN_RC(int_reg)); | |
3666 match(RegI); | |
3667 | |
3668 match(notemp_iRegI); | |
3669 match(g1RegI); | |
3670 match(o0RegI); | |
3671 match(iRegIsafe); | |
3672 | |
3673 format %{ %} | |
3674 interface(REG_INTER); | |
3675 %} | |
3676 | |
3677 operand notemp_iRegI() %{ | |
3678 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3679 match(RegI); | |
3680 | |
3681 match(o0RegI); | |
3682 | |
3683 format %{ %} | |
3684 interface(REG_INTER); | |
3685 %} | |
3686 | |
3687 operand o0RegI() %{ | |
3688 constraint(ALLOC_IN_RC(o0_regI)); | |
3689 match(iRegI); | |
3690 | |
3691 format %{ %} | |
3692 interface(REG_INTER); | |
3693 %} | |
3694 | |
3695 // Pointer Register | |
3696 operand iRegP() %{ | |
3697 constraint(ALLOC_IN_RC(ptr_reg)); | |
3698 match(RegP); | |
3699 | |
3700 match(lock_ptr_RegP); | |
3701 match(g1RegP); | |
3702 match(g2RegP); | |
3703 match(g3RegP); | |
3704 match(g4RegP); | |
3705 match(i0RegP); | |
3706 match(o0RegP); | |
3707 match(o1RegP); | |
3708 match(l7RegP); | |
3709 | |
3710 format %{ %} | |
3711 interface(REG_INTER); | |
3712 %} | |
3713 | |
3714 operand sp_ptr_RegP() %{ | |
3715 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3716 match(RegP); | |
3717 match(iRegP); | |
3718 | |
3719 format %{ %} | |
3720 interface(REG_INTER); | |
3721 %} | |
3722 | |
3723 operand lock_ptr_RegP() %{ | |
3724 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3725 match(RegP); | |
3726 match(i0RegP); | |
3727 match(o0RegP); | |
3728 match(o1RegP); | |
3729 match(l7RegP); | |
3730 | |
3731 format %{ %} | |
3732 interface(REG_INTER); | |
3733 %} | |
3734 | |
3735 operand g1RegP() %{ | |
3736 constraint(ALLOC_IN_RC(g1_regP)); | |
3737 match(iRegP); | |
3738 | |
3739 format %{ %} | |
3740 interface(REG_INTER); | |
3741 %} | |
3742 | |
3743 operand g2RegP() %{ | |
3744 constraint(ALLOC_IN_RC(g2_regP)); | |
3745 match(iRegP); | |
3746 | |
3747 format %{ %} | |
3748 interface(REG_INTER); | |
3749 %} | |
3750 | |
3751 operand g3RegP() %{ | |
3752 constraint(ALLOC_IN_RC(g3_regP)); | |
3753 match(iRegP); | |
3754 | |
3755 format %{ %} | |
3756 interface(REG_INTER); | |
3757 %} | |
3758 | |
3759 operand g1RegI() %{ | |
3760 constraint(ALLOC_IN_RC(g1_regI)); | |
3761 match(iRegI); | |
3762 | |
3763 format %{ %} | |
3764 interface(REG_INTER); | |
3765 %} | |
3766 | |
3767 operand g3RegI() %{ | |
3768 constraint(ALLOC_IN_RC(g3_regI)); | |
3769 match(iRegI); | |
3770 | |
3771 format %{ %} | |
3772 interface(REG_INTER); | |
3773 %} | |
3774 | |
3775 operand g4RegI() %{ | |
3776 constraint(ALLOC_IN_RC(g4_regI)); | |
3777 match(iRegI); | |
3778 | |
3779 format %{ %} | |
3780 interface(REG_INTER); | |
3781 %} | |
3782 | |
3783 operand g4RegP() %{ | |
3784 constraint(ALLOC_IN_RC(g4_regP)); | |
3785 match(iRegP); | |
3786 | |
3787 format %{ %} | |
3788 interface(REG_INTER); | |
3789 %} | |
3790 | |
3791 operand i0RegP() %{ | |
3792 constraint(ALLOC_IN_RC(i0_regP)); | |
3793 match(iRegP); | |
3794 | |
3795 format %{ %} | |
3796 interface(REG_INTER); | |
3797 %} | |
3798 | |
3799 operand o0RegP() %{ | |
3800 constraint(ALLOC_IN_RC(o0_regP)); | |
3801 match(iRegP); | |
3802 | |
3803 format %{ %} | |
3804 interface(REG_INTER); | |
3805 %} | |
3806 | |
3807 operand o1RegP() %{ | |
3808 constraint(ALLOC_IN_RC(o1_regP)); | |
3809 match(iRegP); | |
3810 | |
3811 format %{ %} | |
3812 interface(REG_INTER); | |
3813 %} | |
3814 | |
3815 operand o2RegP() %{ | |
3816 constraint(ALLOC_IN_RC(o2_regP)); | |
3817 match(iRegP); | |
3818 | |
3819 format %{ %} | |
3820 interface(REG_INTER); | |
3821 %} | |
3822 | |
3823 operand o7RegP() %{ | |
3824 constraint(ALLOC_IN_RC(o7_regP)); | |
3825 match(iRegP); | |
3826 | |
3827 format %{ %} | |
3828 interface(REG_INTER); | |
3829 %} | |
3830 | |
3831 operand l7RegP() %{ | |
3832 constraint(ALLOC_IN_RC(l7_regP)); | |
3833 match(iRegP); | |
3834 | |
3835 format %{ %} | |
3836 interface(REG_INTER); | |
3837 %} | |
3838 | |
3839 operand o7RegI() %{ | |
3840 constraint(ALLOC_IN_RC(o7_regI)); | |
3841 match(iRegI); | |
3842 | |
3843 format %{ %} | |
3844 interface(REG_INTER); | |
3845 %} | |
3846 | |
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3847 operand iRegN() %{ |
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3848 constraint(ALLOC_IN_RC(int_reg)); |
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3849 match(RegN); |
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3850 |
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3851 format %{ %} |
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3852 interface(REG_INTER); |
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3853 %} |
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3854 |
0 | 3855 // Long Register |
3856 operand iRegL() %{ | |
3857 constraint(ALLOC_IN_RC(long_reg)); | |
3858 match(RegL); | |
3859 | |
3860 format %{ %} | |
3861 interface(REG_INTER); | |
3862 %} | |
3863 | |
3864 operand o2RegL() %{ | |
3865 constraint(ALLOC_IN_RC(o2_regL)); | |
3866 match(iRegL); | |
3867 | |
3868 format %{ %} | |
3869 interface(REG_INTER); | |
3870 %} | |
3871 | |
3872 operand o7RegL() %{ | |
3873 constraint(ALLOC_IN_RC(o7_regL)); | |
3874 match(iRegL); | |
3875 | |
3876 format %{ %} | |
3877 interface(REG_INTER); | |
3878 %} | |
3879 | |
3880 operand g1RegL() %{ | |
3881 constraint(ALLOC_IN_RC(g1_regL)); | |
3882 match(iRegL); | |
3883 | |
3884 format %{ %} | |
3885 interface(REG_INTER); | |
3886 %} | |
3887 | |
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3888 operand g3RegL() %{ |
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3889 constraint(ALLOC_IN_RC(g3_regL)); |
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3890 match(iRegL); |
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3891 |
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3892 format %{ %} |
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3893 interface(REG_INTER); |
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3894 %} |
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3895 |
0 | 3896 // Int Register safe |
3897 // This is 64bit safe | |
3898 operand iRegIsafe() %{ | |
3899 constraint(ALLOC_IN_RC(long_reg)); | |
3900 | |
3901 match(iRegI); | |
3902 | |
3903 format %{ %} | |
3904 interface(REG_INTER); | |
3905 %} | |
3906 | |
3907 // Condition Code Flag Register | |
3908 operand flagsReg() %{ | |
3909 constraint(ALLOC_IN_RC(int_flags)); | |
3910 match(RegFlags); | |
3911 | |
3912 format %{ "ccr" %} // both ICC and XCC | |
3913 interface(REG_INTER); | |
3914 %} | |
3915 | |
3916 // Condition Code Register, unsigned comparisons. | |
3917 operand flagsRegU() %{ | |
3918 constraint(ALLOC_IN_RC(int_flags)); | |
3919 match(RegFlags); | |
3920 | |
3921 format %{ "icc_U" %} | |
3922 interface(REG_INTER); | |
3923 %} | |
3924 | |
3925 // Condition Code Register, pointer comparisons. | |
3926 operand flagsRegP() %{ | |
3927 constraint(ALLOC_IN_RC(int_flags)); | |
3928 match(RegFlags); | |
3929 | |
3930 #ifdef _LP64 | |
3931 format %{ "xcc_P" %} | |
3932 #else | |
3933 format %{ "icc_P" %} | |
3934 #endif | |
3935 interface(REG_INTER); | |
3936 %} | |
3937 | |
3938 // Condition Code Register, long comparisons. | |
3939 operand flagsRegL() %{ | |
3940 constraint(ALLOC_IN_RC(int_flags)); | |
3941 match(RegFlags); | |
3942 | |
3943 format %{ "xcc_L" %} | |
3944 interface(REG_INTER); | |
3945 %} | |
3946 | |
3947 // Condition Code Register, floating comparisons, unordered same as "less". | |
3948 operand flagsRegF() %{ | |
3949 constraint(ALLOC_IN_RC(float_flags)); | |
3950 match(RegFlags); | |
3951 match(flagsRegF0); | |
3952 | |
3953 format %{ %} | |
3954 interface(REG_INTER); | |
3955 %} | |
3956 | |
3957 operand flagsRegF0() %{ | |
3958 constraint(ALLOC_IN_RC(float_flag0)); | |
3959 match(RegFlags); | |
3960 | |
3961 format %{ %} | |
3962 interface(REG_INTER); | |
3963 %} | |
3964 | |
3965 | |
3966 // Condition Code Flag Register used by long compare | |
3967 operand flagsReg_long_LTGE() %{ | |
3968 constraint(ALLOC_IN_RC(int_flags)); | |
3969 match(RegFlags); | |
3970 format %{ "icc_LTGE" %} | |
3971 interface(REG_INTER); | |
3972 %} | |
3973 operand flagsReg_long_EQNE() %{ | |
3974 constraint(ALLOC_IN_RC(int_flags)); | |
3975 match(RegFlags); | |
3976 format %{ "icc_EQNE" %} | |
3977 interface(REG_INTER); | |
3978 %} | |
3979 operand flagsReg_long_LEGT() %{ | |
3980 constraint(ALLOC_IN_RC(int_flags)); | |
3981 match(RegFlags); | |
3982 format %{ "icc_LEGT" %} | |
3983 interface(REG_INTER); | |
3984 %} | |
3985 | |
3986 | |
3987 operand regD() %{ | |
3988 constraint(ALLOC_IN_RC(dflt_reg)); | |
3989 match(RegD); | |
3990 | |
551 | 3991 match(regD_low); |
3992 | |
0 | 3993 format %{ %} |
3994 interface(REG_INTER); | |
3995 %} | |
3996 | |
3997 operand regF() %{ | |
3998 constraint(ALLOC_IN_RC(sflt_reg)); | |
3999 match(RegF); | |
4000 | |
4001 format %{ %} | |
4002 interface(REG_INTER); | |
4003 %} | |
4004 | |
4005 operand regD_low() %{ | |
4006 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4007 match(regD); |
0 | 4008 |
4009 format %{ %} | |
4010 interface(REG_INTER); | |
4011 %} | |
4012 | |
4013 // Special Registers | |
4014 | |
4015 // Method Register | |
4016 operand inline_cache_regP(iRegP reg) %{ | |
4017 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4018 match(reg); | |
4019 format %{ %} | |
4020 interface(REG_INTER); | |
4021 %} | |
4022 | |
4023 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4024 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4025 match(reg); | |
4026 format %{ %} | |
4027 interface(REG_INTER); | |
4028 %} | |
4029 | |
4030 | |
4031 //----------Complex Operands--------------------------------------------------- | |
4032 // Indirect Memory Reference | |
4033 operand indirect(sp_ptr_RegP reg) %{ | |
4034 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4035 match(reg); | |
4036 | |
4037 op_cost(100); | |
4038 format %{ "[$reg]" %} | |
4039 interface(MEMORY_INTER) %{ | |
4040 base($reg); | |
4041 index(0x0); | |
4042 scale(0x0); | |
4043 disp(0x0); | |
4044 %} | |
4045 %} | |
4046 | |
785 | 4047 // Indirect with simm13 Offset |
0 | 4048 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4049 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4050 match(AddP reg offset); | |
4051 | |
4052 op_cost(100); | |
4053 format %{ "[$reg + $offset]" %} | |
4054 interface(MEMORY_INTER) %{ | |
4055 base($reg); | |
4056 index(0x0); | |
4057 scale(0x0); | |
4058 disp($offset); | |
4059 %} | |
4060 %} | |
4061 | |
785 | 4062 // Indirect with simm13 Offset minus 7 |
4063 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4064 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4065 match(AddP reg offset); | |
4066 | |
4067 op_cost(100); | |
4068 format %{ "[$reg + $offset]" %} | |
4069 interface(MEMORY_INTER) %{ | |
4070 base($reg); | |
4071 index(0x0); | |
4072 scale(0x0); | |
4073 disp($offset); | |
4074 %} | |
4075 %} | |
4076 | |
0 | 4077 // Note: Intel has a swapped version also, like this: |
4078 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4079 // constraint(ALLOC_IN_RC(int_reg)); | |
4080 // match(AddP offset reg); | |
4081 // | |
4082 // op_cost(100); | |
4083 // format %{ "[$reg + $offset]" %} | |
4084 // interface(MEMORY_INTER) %{ | |
4085 // base($reg); | |
4086 // index(0x0); | |
4087 // scale(0x0); | |
4088 // disp($offset); | |
4089 // %} | |
4090 //%} | |
4091 //// However, it doesn't make sense for SPARC, since | |
4092 // we have no particularly good way to embed oops in | |
4093 // single instructions. | |
4094 | |
4095 // Indirect with Register Index | |
4096 operand indIndex(iRegP addr, iRegX index) %{ | |
4097 constraint(ALLOC_IN_RC(ptr_reg)); | |
4098 match(AddP addr index); | |
4099 | |
4100 op_cost(100); | |
4101 format %{ "[$addr + $index]" %} | |
4102 interface(MEMORY_INTER) %{ | |
4103 base($addr); | |
4104 index($index); | |
4105 scale(0x0); | |
4106 disp(0x0); | |
4107 %} | |
4108 %} | |
4109 | |
4110 //----------Special Memory Operands-------------------------------------------- | |
4111 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4112 // values on the stack where a match requires a value to | |
4113 // flow through memory. | |
4114 operand stackSlotI(sRegI reg) %{ | |
4115 constraint(ALLOC_IN_RC(stack_slots)); | |
4116 op_cost(100); | |
4117 //match(RegI); | |
4118 format %{ "[$reg]" %} | |
4119 interface(MEMORY_INTER) %{ | |
4120 base(0xE); // R_SP | |
4121 index(0x0); | |
4122 scale(0x0); | |
4123 disp($reg); // Stack Offset | |
4124 %} | |
4125 %} | |
4126 | |
4127 operand stackSlotP(sRegP reg) %{ | |
4128 constraint(ALLOC_IN_RC(stack_slots)); | |
4129 op_cost(100); | |
4130 //match(RegP); | |
4131 format %{ "[$reg]" %} | |
4132 interface(MEMORY_INTER) %{ | |
4133 base(0xE); // R_SP | |
4134 index(0x0); | |
4135 scale(0x0); | |
4136 disp($reg); // Stack Offset | |
4137 %} | |
4138 %} | |
4139 | |
4140 operand stackSlotF(sRegF reg) %{ | |
4141 constraint(ALLOC_IN_RC(stack_slots)); | |
4142 op_cost(100); | |
4143 //match(RegF); | |
4144 format %{ "[$reg]" %} | |
4145 interface(MEMORY_INTER) %{ | |
4146 base(0xE); // R_SP | |
4147 index(0x0); | |
4148 scale(0x0); | |
4149 disp($reg); // Stack Offset | |
4150 %} | |
4151 %} | |
4152 operand stackSlotD(sRegD reg) %{ | |
4153 constraint(ALLOC_IN_RC(stack_slots)); | |
4154 op_cost(100); | |
4155 //match(RegD); | |
4156 format %{ "[$reg]" %} | |
4157 interface(MEMORY_INTER) %{ | |
4158 base(0xE); // R_SP | |
4159 index(0x0); | |
4160 scale(0x0); | |
4161 disp($reg); // Stack Offset | |
4162 %} | |
4163 %} | |
4164 operand stackSlotL(sRegL reg) %{ | |
4165 constraint(ALLOC_IN_RC(stack_slots)); | |
4166 op_cost(100); | |
4167 //match(RegL); | |
4168 format %{ "[$reg]" %} | |
4169 interface(MEMORY_INTER) %{ | |
4170 base(0xE); // R_SP | |
4171 index(0x0); | |
4172 scale(0x0); | |
4173 disp($reg); // Stack Offset | |
4174 %} | |
4175 %} | |
4176 | |
4177 // Operands for expressing Control Flow | |
4178 // NOTE: Label is a predefined operand which should not be redefined in | |
4179 // the AD file. It is generically handled within the ADLC. | |
4180 | |
4181 //----------Conditional Branch Operands---------------------------------------- | |
4182 // Comparison Op - This is the operation of the comparison, and is limited to | |
4183 // the following set of codes: | |
4184 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4185 // | |
4186 // Other attributes of the comparison, such as unsignedness, are specified | |
4187 // by the comparison instruction that sets a condition code flags register. | |
4188 // That result is represented by a flags operand whose subtype is appropriate | |
4189 // to the unsignedness (etc.) of the comparison. | |
4190 // | |
4191 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4192 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4193 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4194 | |
4195 operand cmpOp() %{ | |
4196 match(Bool); | |
4197 | |
4198 format %{ "" %} | |
4199 interface(COND_INTER) %{ | |
4200 equal(0x1); | |
4201 not_equal(0x9); | |
4202 less(0x3); | |
4203 greater_equal(0xB); | |
4204 less_equal(0x2); | |
4205 greater(0xA); | |
4206 %} | |
4207 %} | |
4208 | |
4209 // Comparison Op, unsigned | |
4210 operand cmpOpU() %{ | |
4211 match(Bool); | |
4212 | |
4213 format %{ "u" %} | |
4214 interface(COND_INTER) %{ | |
4215 equal(0x1); | |
4216 not_equal(0x9); | |
4217 less(0x5); | |
4218 greater_equal(0xD); | |
4219 less_equal(0x4); | |
4220 greater(0xC); | |
4221 %} | |
4222 %} | |
4223 | |
4224 // Comparison Op, pointer (same as unsigned) | |
4225 operand cmpOpP() %{ | |
4226 match(Bool); | |
4227 | |
4228 format %{ "p" %} | |
4229 interface(COND_INTER) %{ | |
4230 equal(0x1); | |
4231 not_equal(0x9); | |
4232 less(0x5); | |
4233 greater_equal(0xD); | |
4234 less_equal(0x4); | |
4235 greater(0xC); | |
4236 %} | |
4237 %} | |
4238 | |
4239 // Comparison Op, branch-register encoding | |
4240 operand cmpOp_reg() %{ | |
4241 match(Bool); | |
4242 | |
4243 format %{ "" %} | |
4244 interface(COND_INTER) %{ | |
4245 equal (0x1); | |
4246 not_equal (0x5); | |
4247 less (0x3); | |
4248 greater_equal(0x7); | |
4249 less_equal (0x2); | |
4250 greater (0x6); | |
4251 %} | |
4252 %} | |
4253 | |
4254 // Comparison Code, floating, unordered same as less | |
4255 operand cmpOpF() %{ | |
4256 match(Bool); | |
4257 | |
4258 format %{ "fl" %} | |
4259 interface(COND_INTER) %{ | |
4260 equal(0x9); | |
4261 not_equal(0x1); | |
4262 less(0x3); | |
4263 greater_equal(0xB); | |
4264 less_equal(0xE); | |
4265 greater(0x6); | |
4266 %} | |
4267 %} | |
4268 | |
4269 // Used by long compare | |
4270 operand cmpOp_commute() %{ | |
4271 match(Bool); | |
4272 | |
4273 format %{ "" %} | |
4274 interface(COND_INTER) %{ | |
4275 equal(0x1); | |
4276 not_equal(0x9); | |
4277 less(0xA); | |
4278 greater_equal(0x2); | |
4279 less_equal(0xB); | |
4280 greater(0x3); | |
4281 %} | |
4282 %} | |
4283 | |
4284 //----------OPERAND CLASSES---------------------------------------------------- | |
4285 // Operand Classes are groups of operands that are used to simplify | |
605 | 4286 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4287 // instructions for every form of operand when the instruction accepts |
4288 // multiple operand types with the same basic encoding and format. The classic | |
4289 // case of this is memory operands. | |
4290 opclass memory( indirect, indOffset13, indIndex ); | |
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4291 opclass indIndexMemory( indIndex ); |
0 | 4292 |
4293 //----------PIPELINE----------------------------------------------------------- | |
4294 pipeline %{ | |
4295 | |
4296 //----------ATTRIBUTES--------------------------------------------------------- | |
4297 attributes %{ | |
4298 fixed_size_instructions; // Fixed size instructions | |
4299 branch_has_delay_slot; // Branch has delay slot following | |
4300 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4301 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4302 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4303 instruction_fetch_units = 1; // of 16 bytes | |
4304 | |
4305 // List of nop instructions | |
4306 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4307 %} | |
4308 | |
4309 //----------RESOURCES---------------------------------------------------------- | |
4310 // Resources are the functional units available to the machine | |
4311 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4312 | |
4313 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4314 // Pipeline Description specifies the stages in the machine's pipeline | |
4315 | |
4316 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4317 | |
4318 //----------PIPELINE CLASSES--------------------------------------------------- | |
4319 // Pipeline Classes describe the stages in which input and output are | |
4320 // referenced by the hardware pipeline. | |
4321 | |
4322 // Integer ALU reg-reg operation | |
4323 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4324 single_instruction; | |
4325 dst : E(write); | |
4326 src1 : R(read); | |
4327 src2 : R(read); | |
4328 IALU : R; | |
4329 %} | |
4330 | |
4331 // Integer ALU reg-reg long operation | |
4332 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4333 instruction_count(2); | |
4334 dst : E(write); | |
4335 src1 : R(read); | |
4336 src2 : R(read); | |
4337 IALU : R; | |
4338 IALU : R; | |
4339 %} | |
4340 | |
4341 // Integer ALU reg-reg long dependent operation | |
4342 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4343 instruction_count(1); multiple_bundles; | |
4344 dst : E(write); | |
4345 src1 : R(read); | |
4346 src2 : R(read); | |
4347 cr : E(write); | |
4348 IALU : R(2); | |
4349 %} | |
4350 | |
4351 // Integer ALU reg-imm operaion | |
4352 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4353 single_instruction; | |
4354 dst : E(write); | |
4355 src1 : R(read); | |
4356 IALU : R; | |
4357 %} | |
4358 | |
4359 // Integer ALU reg-reg operation with condition code | |
4360 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4361 single_instruction; | |
4362 dst : E(write); | |
4363 cr : E(write); | |
4364 src1 : R(read); | |
4365 src2 : R(read); | |
4366 IALU : R; | |
4367 %} | |
4368 | |
4369 // Integer ALU reg-imm operation with condition code | |
4370 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4371 single_instruction; | |
4372 dst : E(write); | |
4373 cr : E(write); | |
4374 src1 : R(read); | |
4375 IALU : R; | |
4376 %} | |
4377 | |
4378 // Integer ALU zero-reg operation | |
4379 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4380 single_instruction; | |
4381 dst : E(write); | |
4382 src2 : R(read); | |
4383 IALU : R; | |
4384 %} | |
4385 | |
4386 // Integer ALU zero-reg operation with condition code only | |
4387 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4388 single_instruction; | |
4389 cr : E(write); | |
4390 src : R(read); | |
4391 IALU : R; | |
4392 %} | |
4393 | |
4394 // Integer ALU reg-reg operation with condition code only | |
4395 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4396 single_instruction; | |
4397 cr : E(write); | |
4398 src1 : R(read); | |
4399 src2 : R(read); | |
4400 IALU : R; | |
4401 %} | |
4402 | |
4403 // Integer ALU reg-imm operation with condition code only | |
4404 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4405 single_instruction; | |
4406 cr : E(write); | |
4407 src1 : R(read); | |
4408 IALU : R; | |
4409 %} | |
4410 | |
4411 // Integer ALU reg-reg-zero operation with condition code only | |
4412 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4413 single_instruction; | |
4414 cr : E(write); | |
4415 src1 : R(read); | |
4416 src2 : R(read); | |
4417 IALU : R; | |
4418 %} | |
4419 | |
4420 // Integer ALU reg-imm-zero operation with condition code only | |
4421 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4422 single_instruction; | |
4423 cr : E(write); | |
4424 src1 : R(read); | |
4425 IALU : R; | |
4426 %} | |
4427 | |
4428 // Integer ALU reg-reg operation with condition code, src1 modified | |
4429 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4430 single_instruction; | |
4431 cr : E(write); | |
4432 src1 : E(write); | |
4433 src1 : R(read); | |
4434 src2 : R(read); | |
4435 IALU : R; | |
4436 %} | |
4437 | |
4438 // Integer ALU reg-imm operation with condition code, src1 modified | |
4439 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4440 single_instruction; | |
4441 cr : E(write); | |
4442 src1 : E(write); | |
4443 src1 : R(read); | |
4444 IALU : R; | |
4445 %} | |
4446 | |
4447 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4448 multiple_bundles; | |
4449 dst : E(write)+4; | |
4450 cr : E(write); | |
4451 src1 : R(read); | |
4452 src2 : R(read); | |
4453 IALU : R(3); | |
4454 BR : R(2); | |
4455 %} | |
4456 | |
4457 // Integer ALU operation | |
4458 pipe_class ialu_none(iRegI dst) %{ | |
4459 single_instruction; | |
4460 dst : E(write); | |
4461 IALU : R; | |
4462 %} | |
4463 | |
4464 // Integer ALU reg operation | |
4465 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4466 single_instruction; may_have_no_code; | |
4467 dst : E(write); | |
4468 src : R(read); | |
4469 IALU : R; | |
4470 %} | |
4471 | |
4472 // Integer ALU reg conditional operation | |
4473 // This instruction has a 1 cycle stall, and cannot execute | |
4474 // in the same cycle as the instruction setting the condition | |
4475 // code. We kludge this by pretending to read the condition code | |
4476 // 1 cycle earlier, and by marking the functional units as busy | |
4477 // for 2 cycles with the result available 1 cycle later than | |
4478 // is really the case. | |
4479 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4480 single_instruction; | |
4481 op2_out : C(write); | |
4482 op1 : R(read); | |
4483 cr : R(read); // This is really E, with a 1 cycle stall | |
4484 BR : R(2); | |
4485 MS : R(2); | |
4486 %} | |
4487 | |
4488 #ifdef _LP64 | |
4489 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4490 instruction_count(1); multiple_bundles; | |
4491 dst : C(write)+1; | |
4492 src : R(read)+1; | |
4493 IALU : R(1); | |
4494 BR : E(2); | |
4495 MS : E(2); | |
4496 %} | |
4497 #endif | |
4498 | |
4499 // Integer ALU reg operation | |
4500 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4501 single_instruction; may_have_no_code; | |
4502 dst : E(write); | |
4503 src : R(read); | |
4504 IALU : R; | |
4505 %} | |
4506 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4507 single_instruction; may_have_no_code; | |
4508 dst : E(write); | |
4509 src : R(read); | |
4510 IALU : R; | |
4511 %} | |
4512 | |
4513 // Two integer ALU reg operations | |
4514 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4515 instruction_count(2); | |
4516 dst : E(write); | |
4517 src : R(read); | |
4518 A0 : R; | |
4519 A1 : R; | |
4520 %} | |
4521 | |
4522 // Two integer ALU reg operations | |
4523 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4524 instruction_count(2); may_have_no_code; | |
4525 dst : E(write); | |
4526 src : R(read); | |
4527 A0 : R; | |
4528 A1 : R; | |
4529 %} | |
4530 | |
4531 // Integer ALU imm operation | |
4532 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4533 single_instruction; | |
4534 dst : E(write); | |
4535 IALU : R; | |
4536 %} | |
4537 | |
4538 // Integer ALU reg-reg with carry operation | |
4539 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4540 single_instruction; | |
4541 dst : E(write); | |
4542 src1 : R(read); | |
4543 src2 : R(read); | |
4544 IALU : R; | |
4545 %} | |
4546 | |
4547 // Integer ALU cc operation | |
4548 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4549 single_instruction; | |
4550 dst : E(write); | |
4551 cc : R(read); | |
4552 IALU : R; | |
4553 %} | |
4554 | |
4555 // Integer ALU cc / second IALU operation | |
4556 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4557 instruction_count(1); multiple_bundles; | |
4558 dst : E(write)+1; | |
4559 src : R(read); | |
4560 IALU : R; | |
4561 %} | |
4562 | |
4563 // Integer ALU cc / second IALU operation | |
4564 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4565 instruction_count(1); multiple_bundles; | |
4566 dst : E(write)+1; | |
4567 p : R(read); | |
4568 q : R(read); | |
4569 IALU : R; | |
4570 %} | |
4571 | |
4572 // Integer ALU hi-lo-reg operation | |
4573 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4574 instruction_count(1); multiple_bundles; | |
4575 dst : E(write)+1; | |
4576 IALU : R(2); | |
4577 %} | |
4578 | |
4579 // Float ALU hi-lo-reg operation (with temp) | |
4580 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4581 instruction_count(1); multiple_bundles; | |
4582 dst : E(write)+1; | |
4583 IALU : R(2); | |
4584 %} | |
4585 | |
4586 // Long Constant | |
4587 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4588 instruction_count(2); multiple_bundles; | |
4589 dst : E(write)+1; | |
4590 IALU : R(2); | |
4591 IALU : R(2); | |
4592 %} | |
4593 | |
4594 // Pointer Constant | |
4595 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4596 instruction_count(0); multiple_bundles; | |
4597 fixed_latency(6); | |
4598 %} | |
4599 | |
4600 // Polling Address | |
4601 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4602 #ifdef _LP64 | |
4603 instruction_count(0); multiple_bundles; | |
4604 fixed_latency(6); | |
4605 #else | |
4606 dst : E(write); | |
4607 IALU : R; | |
4608 #endif | |
4609 %} | |
4610 | |
4611 // Long Constant small | |
4612 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4613 instruction_count(2); | |
4614 dst : E(write); | |
4615 IALU : R; | |
4616 IALU : R; | |
4617 %} | |
4618 | |
4619 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4620 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4621 instruction_count(1); multiple_bundles; | |
4622 src : R(read); | |
4623 dst : M(write)+1; | |
4624 IALU : R; | |
4625 MS : E; | |
4626 %} | |
4627 | |
4628 // Integer ALU nop operation | |
4629 pipe_class ialu_nop() %{ | |
4630 single_instruction; | |
4631 IALU : R; | |
4632 %} | |
4633 | |
4634 // Integer ALU nop operation | |
4635 pipe_class ialu_nop_A0() %{ | |
4636 single_instruction; | |
4637 A0 : R; | |
4638 %} | |
4639 | |
4640 // Integer ALU nop operation | |
4641 pipe_class ialu_nop_A1() %{ | |
4642 single_instruction; | |
4643 A1 : R; | |
4644 %} | |
4645 | |
4646 // Integer Multiply reg-reg operation | |
4647 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4648 single_instruction; | |
4649 dst : E(write); | |
4650 src1 : R(read); | |
4651 src2 : R(read); | |
4652 MS : R(5); | |
4653 %} | |
4654 | |
4655 // Integer Multiply reg-imm operation | |
4656 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4657 single_instruction; | |
4658 dst : E(write); | |
4659 src1 : R(read); | |
4660 MS : R(5); | |
4661 %} | |
4662 | |
4663 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4664 single_instruction; | |
4665 dst : E(write)+4; | |
4666 src1 : R(read); | |
4667 src2 : R(read); | |
4668 MS : R(6); | |
4669 %} | |
4670 | |
4671 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4672 single_instruction; | |
4673 dst : E(write)+4; | |
4674 src1 : R(read); | |
4675 MS : R(6); | |
4676 %} | |
4677 | |
4678 // Integer Divide reg-reg | |
4679 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4680 instruction_count(1); multiple_bundles; | |
4681 dst : E(write); | |
4682 temp : E(write); | |
4683 src1 : R(read); | |
4684 src2 : R(read); | |
4685 temp : R(read); | |
4686 MS : R(38); | |
4687 %} | |
4688 | |
4689 // Integer Divide reg-imm | |
4690 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4691 instruction_count(1); multiple_bundles; | |
4692 dst : E(write); | |
4693 temp : E(write); | |
4694 src1 : R(read); | |
4695 temp : R(read); | |
4696 MS : R(38); | |
4697 %} | |
4698 | |
4699 // Long Divide | |
4700 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4701 dst : E(write)+71; | |
4702 src1 : R(read); | |
4703 src2 : R(read)+1; | |
4704 MS : R(70); | |
4705 %} | |
4706 | |
4707 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4708 dst : E(write)+71; | |
4709 src1 : R(read); | |
4710 MS : R(70); | |
4711 %} | |
4712 | |
4713 // Floating Point Add Float | |
4714 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4715 single_instruction; | |
4716 dst : X(write); | |
4717 src1 : E(read); | |
4718 src2 : E(read); | |
4719 FA : R; | |
4720 %} | |
4721 | |
4722 // Floating Point Add Double | |
4723 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4724 single_instruction; | |
4725 dst : X(write); | |
4726 src1 : E(read); | |
4727 src2 : E(read); | |
4728 FA : R; | |
4729 %} | |
4730 | |
4731 // Floating Point Conditional Move based on integer flags | |
4732 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4733 single_instruction; | |
4734 dst : X(write); | |
4735 src : E(read); | |
4736 cr : R(read); | |
4737 FA : R(2); | |
4738 BR : R(2); | |
4739 %} | |
4740 | |
4741 // Floating Point Conditional Move based on integer flags | |
4742 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4743 single_instruction; | |
4744 dst : X(write); | |
4745 src : E(read); | |
4746 cr : R(read); | |
4747 FA : R(2); | |
4748 BR : R(2); | |
4749 %} | |
4750 | |
4751 // Floating Point Multiply Float | |
4752 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4753 single_instruction; | |
4754 dst : X(write); | |
4755 src1 : E(read); | |
4756 src2 : E(read); | |
4757 FM : R; | |
4758 %} | |
4759 | |
4760 // Floating Point Multiply Double | |
4761 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4762 single_instruction; | |
4763 dst : X(write); | |
4764 src1 : E(read); | |
4765 src2 : E(read); | |
4766 FM : R; | |
4767 %} | |
4768 | |
4769 // Floating Point Divide Float | |
4770 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4771 single_instruction; | |
4772 dst : X(write); | |
4773 src1 : E(read); | |
4774 src2 : E(read); | |
4775 FM : R; | |
4776 FDIV : C(14); | |
4777 %} | |
4778 | |
4779 // Floating Point Divide Double | |
4780 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4781 single_instruction; | |
4782 dst : X(write); | |
4783 src1 : E(read); | |
4784 src2 : E(read); | |
4785 FM : R; | |
4786 FDIV : C(17); | |
4787 %} | |
4788 | |
4789 // Floating Point Move/Negate/Abs Float | |
4790 pipe_class faddF_reg(regF dst, regF src) %{ | |
4791 single_instruction; | |
4792 dst : W(write); | |
4793 src : E(read); | |
4794 FA : R(1); | |
4795 %} | |
4796 | |
4797 // Floating Point Move/Negate/Abs Double | |
4798 pipe_class faddD_reg(regD dst, regD src) %{ | |
4799 single_instruction; | |
4800 dst : W(write); | |
4801 src : E(read); | |
4802 FA : R; | |
4803 %} | |
4804 | |
4805 // Floating Point Convert F->D | |
4806 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4807 single_instruction; | |
4808 dst : X(write); | |
4809 src : E(read); | |
4810 FA : R; | |
4811 %} | |
4812 | |
4813 // Floating Point Convert I->D | |
4814 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4815 single_instruction; | |
4816 dst : X(write); | |
4817 src : E(read); | |
4818 FA : R; | |
4819 %} | |
4820 | |
4821 // Floating Point Convert LHi->D | |
4822 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4823 single_instruction; | |
4824 dst : X(write); | |
4825 src : E(read); | |
4826 FA : R; | |
4827 %} | |
4828 | |
4829 // Floating Point Convert L->D | |
4830 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4831 single_instruction; | |
4832 dst : X(write); | |
4833 src : E(read); | |
4834 FA : R; | |
4835 %} | |
4836 | |
4837 // Floating Point Convert L->F | |
4838 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4839 single_instruction; | |
4840 dst : X(write); | |
4841 src : E(read); | |
4842 FA : R; | |
4843 %} | |
4844 | |
4845 // Floating Point Convert D->F | |
4846 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4847 single_instruction; | |
4848 dst : X(write); | |
4849 src : E(read); | |
4850 FA : R; | |
4851 %} | |
4852 | |
4853 // Floating Point Convert I->L | |
4854 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4855 single_instruction; | |
4856 dst : X(write); | |
4857 src : E(read); | |
4858 FA : R; | |
4859 %} | |
4860 | |
4861 // Floating Point Convert D->F | |
4862 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4863 instruction_count(1); multiple_bundles; | |
4864 dst : X(write)+6; | |
4865 src : E(read); | |
4866 FA : R; | |
4867 %} | |
4868 | |
4869 // Floating Point Convert D->L | |
4870 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4871 instruction_count(1); multiple_bundles; | |
4872 dst : X(write)+6; | |
4873 src : E(read); | |
4874 FA : R; | |
4875 %} | |
4876 | |
4877 // Floating Point Convert F->I | |
4878 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4879 instruction_count(1); multiple_bundles; | |
4880 dst : X(write)+6; | |
4881 src : E(read); | |
4882 FA : R; | |
4883 %} | |
4884 | |
4885 // Floating Point Convert F->L | |
4886 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4887 instruction_count(1); multiple_bundles; | |
4888 dst : X(write)+6; | |
4889 src : E(read); | |
4890 FA : R; | |
4891 %} | |
4892 | |
4893 // Floating Point Convert I->F | |
4894 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4895 single_instruction; | |
4896 dst : X(write); | |
4897 src : E(read); | |
4898 FA : R; | |
4899 %} | |
4900 | |
4901 // Floating Point Compare | |
4902 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4903 single_instruction; | |
4904 cr : X(write); | |
4905 src1 : E(read); | |
4906 src2 : E(read); | |
4907 FA : R; | |
4908 %} | |
4909 | |
4910 // Floating Point Compare | |
4911 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4912 single_instruction; | |
4913 cr : X(write); | |
4914 src1 : E(read); | |
4915 src2 : E(read); | |
4916 FA : R; | |
4917 %} | |
4918 | |
4919 // Floating Add Nop | |
4920 pipe_class fadd_nop() %{ | |
4921 single_instruction; | |
4922 FA : R; | |
4923 %} | |
4924 | |
4925 // Integer Store to Memory | |
4926 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
4927 single_instruction; | |
4928 mem : R(read); | |
4929 src : C(read); | |
4930 MS : R; | |
4931 %} | |
4932 | |
4933 // Integer Store to Memory | |
4934 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
4935 single_instruction; | |
4936 mem : R(read); | |
4937 src : C(read); | |
4938 MS : R; | |
4939 %} | |
4940 | |
4941 // Integer Store Zero to Memory | |
4942 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
4943 single_instruction; | |
4944 mem : R(read); | |
4945 MS : R; | |
4946 %} | |
4947 | |
4948 // Special Stack Slot Store | |
4949 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
4950 single_instruction; | |
4951 stkSlot : R(read); | |
4952 src : C(read); | |
4953 MS : R; | |
4954 %} | |
4955 | |
4956 // Special Stack Slot Store | |
4957 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
4958 instruction_count(2); multiple_bundles; | |
4959 stkSlot : R(read); | |
4960 src : C(read); | |
4961 MS : R(2); | |
4962 %} | |
4963 | |
4964 // Float Store | |
4965 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
4966 single_instruction; | |
4967 mem : R(read); | |
4968 src : C(read); | |
4969 MS : R; | |
4970 %} | |
4971 | |
4972 // Float Store | |
4973 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
4974 single_instruction; | |
4975 mem : R(read); | |
4976 MS : R; | |
4977 %} | |
4978 | |
4979 // Double Store | |
4980 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
4981 instruction_count(1); | |
4982 mem : R(read); | |
4983 src : C(read); | |
4984 MS : R; | |
4985 %} | |
4986 | |
4987 // Double Store | |
4988 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
4989 single_instruction; | |
4990 mem : R(read); | |
4991 MS : R; | |
4992 %} | |
4993 | |
4994 // Special Stack Slot Float Store | |
4995 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
4996 single_instruction; | |
4997 stkSlot : R(read); | |
4998 src : C(read); | |
4999 MS : R; | |
5000 %} | |
5001 | |
5002 // Special Stack Slot Double Store | |
5003 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5004 single_instruction; | |
5005 stkSlot : R(read); | |
5006 src : C(read); | |
5007 MS : R; | |
5008 %} | |
5009 | |
5010 // Integer Load (when sign bit propagation not needed) | |
5011 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5012 single_instruction; | |
5013 mem : R(read); | |
5014 dst : C(write); | |
5015 MS : R; | |
5016 %} | |
5017 | |
5018 // Integer Load from stack operand | |
5019 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5020 single_instruction; | |
5021 mem : R(read); | |
5022 dst : C(write); | |
5023 MS : R; | |
5024 %} | |
5025 | |
5026 // Integer Load (when sign bit propagation or masking is needed) | |
5027 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5028 single_instruction; | |
5029 mem : R(read); | |
5030 dst : M(write); | |
5031 MS : R; | |
5032 %} | |
5033 | |
5034 // Float Load | |
5035 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5036 single_instruction; | |
5037 mem : R(read); | |
5038 dst : M(write); | |
5039 MS : R; | |
5040 %} | |
5041 | |
5042 // Float Load | |
5043 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5044 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5045 mem : R(read); | |
5046 dst : M(write); | |
5047 MS : R; | |
5048 %} | |
5049 | |
5050 // Float Load | |
5051 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5052 single_instruction; | |
5053 stkSlot : R(read); | |
5054 dst : M(write); | |
5055 MS : R; | |
5056 %} | |
5057 | |
5058 // Float Load | |
5059 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5060 single_instruction; | |
5061 stkSlot : R(read); | |
5062 dst : M(write); | |
5063 MS : R; | |
5064 %} | |
5065 | |
5066 // Memory Nop | |
5067 pipe_class mem_nop() %{ | |
5068 single_instruction; | |
5069 MS : R; | |
5070 %} | |
5071 | |
5072 pipe_class sethi(iRegP dst, immI src) %{ | |
5073 single_instruction; | |
5074 dst : E(write); | |
5075 IALU : R; | |
5076 %} | |
5077 | |
5078 pipe_class loadPollP(iRegP poll) %{ | |
5079 single_instruction; | |
5080 poll : R(read); | |
5081 MS : R; | |
5082 %} | |
5083 | |
5084 pipe_class br(Universe br, label labl) %{ | |
5085 single_instruction_with_delay_slot; | |
5086 BR : R; | |
5087 %} | |
5088 | |
5089 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5090 single_instruction_with_delay_slot; | |
5091 cr : E(read); | |
5092 BR : R; | |
5093 %} | |
5094 | |
5095 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5096 single_instruction_with_delay_slot; | |
5097 op1 : E(read); | |
5098 BR : R; | |
5099 MS : R; | |
5100 %} | |
5101 | |
5102 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
5103 single_instruction_with_delay_slot; | |
5104 cr : E(read); | |
5105 BR : R; | |
5106 %} | |
5107 | |
5108 pipe_class br_nop() %{ | |
5109 single_instruction; | |
5110 BR : R; | |
5111 %} | |
5112 | |
5113 pipe_class simple_call(method meth) %{ | |
5114 instruction_count(2); multiple_bundles; force_serialization; | |
5115 fixed_latency(100); | |
5116 BR : R(1); | |
5117 MS : R(1); | |
5118 A0 : R(1); | |
5119 %} | |
5120 | |
5121 pipe_class compiled_call(method meth) %{ | |
5122 instruction_count(1); multiple_bundles; force_serialization; | |
5123 fixed_latency(100); | |
5124 MS : R(1); | |
5125 %} | |
5126 | |
5127 pipe_class call(method meth) %{ | |
5128 instruction_count(0); multiple_bundles; force_serialization; | |
5129 fixed_latency(100); | |
5130 %} | |
5131 | |
5132 pipe_class tail_call(Universe ignore, label labl) %{ | |
5133 single_instruction; has_delay_slot; | |
5134 fixed_latency(100); | |
5135 BR : R(1); | |
5136 MS : R(1); | |
5137 %} | |
5138 | |
5139 pipe_class ret(Universe ignore) %{ | |
5140 single_instruction; has_delay_slot; | |
5141 BR : R(1); | |
5142 MS : R(1); | |
5143 %} | |
5144 | |
5145 pipe_class ret_poll(g3RegP poll) %{ | |
5146 instruction_count(3); has_delay_slot; | |
5147 poll : E(read); | |
5148 MS : R; | |
5149 %} | |
5150 | |
5151 // The real do-nothing guy | |
5152 pipe_class empty( ) %{ | |
5153 instruction_count(0); | |
5154 %} | |
5155 | |
5156 pipe_class long_memory_op() %{ | |
5157 instruction_count(0); multiple_bundles; force_serialization; | |
5158 fixed_latency(25); | |
5159 MS : R(1); | |
5160 %} | |
5161 | |
5162 // Check-cast | |
5163 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5164 array : R(read); | |
5165 match : R(read); | |
5166 IALU : R(2); | |
5167 BR : R(2); | |
5168 MS : R; | |
5169 %} | |
5170 | |
5171 // Convert FPU flags into +1,0,-1 | |
5172 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5173 src1 : E(read); | |
5174 src2 : E(read); | |
5175 dst : E(write); | |
5176 FA : R; | |
5177 MS : R(2); | |
5178 BR : R(2); | |
5179 %} | |
5180 | |
5181 // Compare for p < q, and conditionally add y | |
5182 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5183 p : E(read); | |
5184 q : E(read); | |
5185 y : E(read); | |
5186 IALU : R(3) | |
5187 %} | |
5188 | |
5189 // Perform a compare, then move conditionally in a branch delay slot. | |
5190 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5191 src2 : E(read); | |
5192 srcdst : E(read); | |
5193 IALU : R; | |
5194 BR : R; | |
5195 %} | |
5196 | |
5197 // Define the class for the Nop node | |
5198 define %{ | |
5199 MachNop = ialu_nop; | |
5200 %} | |
5201 | |
5202 %} | |
5203 | |
5204 //----------INSTRUCTIONS------------------------------------------------------- | |
5205 | |
5206 //------------Special Stack Slot instructions - no match rules----------------- | |
5207 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5208 // No match rule to avoid chain rule match. | |
5209 effect(DEF dst, USE src); | |
5210 ins_cost(MEMORY_REF_COST); | |
5211 size(4); | |
5212 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5213 opcode(Assembler::ldf_op3); | |
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5214 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5215 ins_pipe(floadF_stk); |
5216 %} | |
5217 | |
5218 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5219 // No match rule to avoid chain rule match. | |
5220 effect(DEF dst, USE src); | |
5221 ins_cost(MEMORY_REF_COST); | |
5222 size(4); | |
5223 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5224 opcode(Assembler::lddf_op3); | |
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5225 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5226 ins_pipe(floadD_stk); |
5227 %} | |
5228 | |
5229 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5230 // No match rule to avoid chain rule match. | |
5231 effect(DEF dst, USE src); | |
5232 ins_cost(MEMORY_REF_COST); | |
5233 size(4); | |
5234 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5235 opcode(Assembler::stf_op3); | |
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5236 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5237 ins_pipe(fstoreF_stk_reg); |
5238 %} | |
5239 | |
5240 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5241 // No match rule to avoid chain rule match. | |
5242 effect(DEF dst, USE src); | |
5243 ins_cost(MEMORY_REF_COST); | |
5244 size(4); | |
5245 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5246 opcode(Assembler::stdf_op3); | |
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5247 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5248 ins_pipe(fstoreD_stk_reg); |
5249 %} | |
5250 | |
5251 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5252 effect(DEF dst, USE src); | |
5253 ins_cost(MEMORY_REF_COST*2); | |
5254 size(8); | |
5255 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5256 "STW R_G0,$dst.lo" %} | |
5257 opcode(Assembler::stw_op3); | |
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5258 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5259 ins_pipe(lstoreI_stk_reg); |
5260 %} | |
5261 | |
5262 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5263 // No match rule to avoid chain rule match. | |
5264 effect(DEF dst, USE src); | |
5265 ins_cost(MEMORY_REF_COST); | |
5266 size(4); | |
5267 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5268 opcode(Assembler::stx_op3); | |
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5269 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5270 ins_pipe(istore_stk_reg); |
5271 %} | |
5272 | |
5273 //---------- Chain stack slots between similar types -------- | |
5274 | |
5275 // Load integer from stack slot | |
5276 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5277 match(Set dst src); | |
5278 ins_cost(MEMORY_REF_COST); | |
5279 | |
5280 size(4); | |
5281 format %{ "LDUW $src,$dst\t!stk" %} | |
5282 opcode(Assembler::lduw_op3); | |
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5283 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5284 ins_pipe(iload_mem); |
5285 %} | |
5286 | |
5287 // Store integer to stack slot | |
5288 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5289 match(Set dst src); | |
5290 ins_cost(MEMORY_REF_COST); | |
5291 | |
5292 size(4); | |
5293 format %{ "STW $src,$dst\t!stk" %} | |
5294 opcode(Assembler::stw_op3); | |
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5295 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5296 ins_pipe(istore_mem_reg); |
5297 %} | |
5298 | |
5299 // Load long from stack slot | |
5300 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5301 match(Set dst src); | |
5302 | |
5303 ins_cost(MEMORY_REF_COST); | |
5304 size(4); | |
5305 format %{ "LDX $src,$dst\t! long" %} | |
5306 opcode(Assembler::ldx_op3); | |
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5307 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5308 ins_pipe(iload_mem); |
5309 %} | |
5310 | |
5311 // Store long to stack slot | |
5312 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5313 match(Set dst src); | |
5314 | |
5315 ins_cost(MEMORY_REF_COST); | |
5316 size(4); | |
5317 format %{ "STX $src,$dst\t! long" %} | |
5318 opcode(Assembler::stx_op3); | |
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5319 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5320 ins_pipe(istore_mem_reg); |
5321 %} | |
5322 | |
5323 #ifdef _LP64 | |
5324 // Load pointer from stack slot, 64-bit encoding | |
5325 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5326 match(Set dst src); | |
5327 ins_cost(MEMORY_REF_COST); | |
5328 size(4); | |
5329 format %{ "LDX $src,$dst\t!ptr" %} | |
5330 opcode(Assembler::ldx_op3); | |
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5331 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5332 ins_pipe(iload_mem); |
5333 %} | |
5334 | |
5335 // Store pointer to stack slot | |
5336 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5337 match(Set dst src); | |
5338 ins_cost(MEMORY_REF_COST); | |
5339 size(4); | |
5340 format %{ "STX $src,$dst\t!ptr" %} | |
5341 opcode(Assembler::stx_op3); | |
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5342 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5343 ins_pipe(istore_mem_reg); |
5344 %} | |
5345 #else // _LP64 | |
5346 // Load pointer from stack slot, 32-bit encoding | |
5347 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5348 match(Set dst src); | |
5349 ins_cost(MEMORY_REF_COST); | |
5350 format %{ "LDUW $src,$dst\t!ptr" %} | |
5351 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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5352 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5353 ins_pipe(iload_mem); |
5354 %} | |
5355 | |
5356 // Store pointer to stack slot | |
5357 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5358 match(Set dst src); | |
5359 ins_cost(MEMORY_REF_COST); | |
5360 format %{ "STW $src,$dst\t!ptr" %} | |
5361 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5362 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5363 ins_pipe(istore_mem_reg); |
5364 %} | |
5365 #endif // _LP64 | |
5366 | |
5367 //------------Special Nop instructions for bundling - no match rules----------- | |
5368 // Nop using the A0 functional unit | |
5369 instruct Nop_A0() %{ | |
5370 ins_cost(0); | |
5371 | |
5372 format %{ "NOP ! Alu Pipeline" %} | |
5373 opcode(Assembler::or_op3, Assembler::arith_op); | |
5374 ins_encode( form2_nop() ); | |
5375 ins_pipe(ialu_nop_A0); | |
5376 %} | |
5377 | |
5378 // Nop using the A1 functional unit | |
5379 instruct Nop_A1( ) %{ | |
5380 ins_cost(0); | |
5381 | |
5382 format %{ "NOP ! Alu Pipeline" %} | |
5383 opcode(Assembler::or_op3, Assembler::arith_op); | |
5384 ins_encode( form2_nop() ); | |
5385 ins_pipe(ialu_nop_A1); | |
5386 %} | |
5387 | |
5388 // Nop using the memory functional unit | |
5389 instruct Nop_MS( ) %{ | |
5390 ins_cost(0); | |
5391 | |
5392 format %{ "NOP ! Memory Pipeline" %} | |
5393 ins_encode( emit_mem_nop ); | |
5394 ins_pipe(mem_nop); | |
5395 %} | |
5396 | |
5397 // Nop using the floating add functional unit | |
5398 instruct Nop_FA( ) %{ | |
5399 ins_cost(0); | |
5400 | |
5401 format %{ "NOP ! Floating Add Pipeline" %} | |
5402 ins_encode( emit_fadd_nop ); | |
5403 ins_pipe(fadd_nop); | |
5404 %} | |
5405 | |
5406 // Nop using the branch functional unit | |
5407 instruct Nop_BR( ) %{ | |
5408 ins_cost(0); | |
5409 | |
5410 format %{ "NOP ! Branch Pipeline" %} | |
5411 ins_encode( emit_br_nop ); | |
5412 ins_pipe(br_nop); | |
5413 %} | |
5414 | |
5415 //----------Load/Store/Move Instructions--------------------------------------- | |
5416 //----------Load Instructions-------------------------------------------------- | |
5417 // Load Byte (8bit signed) | |
5418 instruct loadB(iRegI dst, memory mem) %{ | |
5419 match(Set dst (LoadB mem)); | |
5420 ins_cost(MEMORY_REF_COST); | |
5421 | |
5422 size(4); | |
624 | 5423 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5424 ins_encode %{ |
5425 __ ldsb($mem$$Address, $dst$$Register); | |
5426 %} | |
624 | 5427 ins_pipe(iload_mask_mem); |
5428 %} | |
5429 | |
5430 // Load Byte (8bit signed) into a Long Register | |
5431 instruct loadB2L(iRegL dst, memory mem) %{ | |
5432 match(Set dst (ConvI2L (LoadB mem))); | |
5433 ins_cost(MEMORY_REF_COST); | |
5434 | |
5435 size(4); | |
5436 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5437 ins_encode %{ |
5438 __ ldsb($mem$$Address, $dst$$Register); | |
5439 %} | |
0 | 5440 ins_pipe(iload_mask_mem); |
5441 %} | |
5442 | |
624 | 5443 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5444 instruct loadUB(iRegI dst, memory mem) %{ | |
5445 match(Set dst (LoadUB mem)); | |
0 | 5446 ins_cost(MEMORY_REF_COST); |
5447 | |
5448 size(4); | |
624 | 5449 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5450 ins_encode %{ |
5451 __ ldub($mem$$Address, $dst$$Register); | |
5452 %} | |
824 | 5453 ins_pipe(iload_mem); |
624 | 5454 %} |
5455 | |
5456 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5457 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5458 match(Set dst (ConvI2L (LoadUB mem))); | |
5459 ins_cost(MEMORY_REF_COST); | |
5460 | |
5461 size(4); | |
5462 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5463 ins_encode %{ |
5464 __ ldub($mem$$Address, $dst$$Register); | |
5465 %} | |
824 | 5466 ins_pipe(iload_mem); |
5467 %} | |
5468 | |
5469 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5470 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5471 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5472 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5473 | |
5474 size(2*4); | |
5475 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5476 "AND $dst,$mask,$dst" %} | |
5477 ins_encode %{ | |
5478 __ ldub($mem$$Address, $dst$$Register); | |
5479 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5480 %} | |
5481 ins_pipe(iload_mem); | |
0 | 5482 %} |
5483 | |
624 | 5484 // Load Short (16bit signed) |
5485 instruct loadS(iRegI dst, memory mem) %{ | |
5486 match(Set dst (LoadS mem)); | |
5487 ins_cost(MEMORY_REF_COST); | |
5488 | |
5489 size(4); | |
5490 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5491 ins_encode %{ |
5492 __ ldsh($mem$$Address, $dst$$Register); | |
5493 %} | |
624 | 5494 ins_pipe(iload_mask_mem); |
5495 %} | |
5496 | |
785 | 5497 // Load Short (16 bit signed) to Byte (8 bit signed) |
5498 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5499 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5500 ins_cost(MEMORY_REF_COST); | |
5501 | |
5502 size(4); | |
5503 | |
5504 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5505 ins_encode %{ | |
5506 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5507 %} | |
5508 ins_pipe(iload_mask_mem); | |
5509 %} | |
5510 | |
624 | 5511 // Load Short (16bit signed) into a Long Register |
5512 instruct loadS2L(iRegL dst, memory mem) %{ | |
5513 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5514 ins_cost(MEMORY_REF_COST); |
5515 | |
5516 size(4); | |
624 | 5517 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5518 ins_encode %{ |
5519 __ ldsh($mem$$Address, $dst$$Register); | |
5520 %} | |
624 | 5521 ins_pipe(iload_mask_mem); |
5522 %} | |
5523 | |
5524 // Load Unsigned Short/Char (16bit UNsigned) | |
5525 instruct loadUS(iRegI dst, memory mem) %{ | |
5526 match(Set dst (LoadUS mem)); | |
5527 ins_cost(MEMORY_REF_COST); | |
5528 | |
5529 size(4); | |
5530 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5531 ins_encode %{ |
5532 __ lduh($mem$$Address, $dst$$Register); | |
5533 %} | |
824 | 5534 ins_pipe(iload_mem); |
0 | 5535 %} |
5536 | |
785 | 5537 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5538 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5539 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5540 ins_cost(MEMORY_REF_COST); | |
5541 | |
5542 size(4); | |
5543 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5544 ins_encode %{ | |
5545 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5546 %} | |
5547 ins_pipe(iload_mask_mem); | |
5548 %} | |
5549 | |
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diff
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|
5550 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5551 instruct loadUS2L(iRegL dst, memory mem) %{ |
5552 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5553 ins_cost(MEMORY_REF_COST); |
5554 | |
5555 size(4); | |
624 | 5556 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5557 ins_encode %{ |
5558 __ lduh($mem$$Address, $dst$$Register); | |
5559 %} | |
824 | 5560 ins_pipe(iload_mem); |
5561 %} | |
5562 | |
5563 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5564 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5565 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5566 ins_cost(MEMORY_REF_COST); | |
5567 | |
5568 size(4); | |
5569 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5570 ins_encode %{ | |
5571 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5572 %} | |
5573 ins_pipe(iload_mem); | |
5574 %} | |
5575 | |
5576 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5577 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5578 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5579 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5580 | |
5581 size(2*4); | |
5582 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5583 "AND $dst,$mask,$dst" %} | |
5584 ins_encode %{ | |
5585 Register Rdst = $dst$$Register; | |
5586 __ lduh($mem$$Address, Rdst); | |
5587 __ and3(Rdst, $mask$$constant, Rdst); | |
5588 %} | |
5589 ins_pipe(iload_mem); | |
5590 %} | |
5591 | |
5592 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5593 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5594 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5595 effect(TEMP dst, TEMP tmp); | |
5596 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5597 | |
951
1fbd5d696bf4
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|
5598 size((3+1)*4); // set may use two instructions. |
824 | 5599 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5600 "SET $mask,$tmp\n\t" | |
5601 "AND $dst,$tmp,$dst" %} | |
5602 ins_encode %{ | |
5603 Register Rdst = $dst$$Register; | |
5604 Register Rtmp = $tmp$$Register; | |
5605 __ lduh($mem$$Address, Rdst); | |
5606 __ set($mask$$constant, Rtmp); | |
5607 __ and3(Rdst, Rtmp, Rdst); | |
5608 %} | |
5609 ins_pipe(iload_mem); | |
0 | 5610 %} |
5611 | |
5612 // Load Integer | |
5613 instruct loadI(iRegI dst, memory mem) %{ | |
5614 match(Set dst (LoadI mem)); | |
5615 ins_cost(MEMORY_REF_COST); | |
624 | 5616 |
5617 size(4); | |
5618 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5619 ins_encode %{ |
5620 __ lduw($mem$$Address, $dst$$Register); | |
5621 %} | |
624 | 5622 ins_pipe(iload_mem); |
5623 %} | |
5624 | |
785 | 5625 // Load Integer to Byte (8 bit signed) |
5626 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5627 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5628 ins_cost(MEMORY_REF_COST); | |
5629 | |
5630 size(4); | |
5631 | |
5632 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5633 ins_encode %{ | |
5634 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5635 %} | |
5636 ins_pipe(iload_mask_mem); | |
5637 %} | |
5638 | |
5639 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5640 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5641 match(Set dst (AndI (LoadI mem) mask)); | |
5642 ins_cost(MEMORY_REF_COST); | |
5643 | |
5644 size(4); | |
5645 | |
5646 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5647 ins_encode %{ | |
5648 __ ldub($mem$$Address, $dst$$Register, 3); | |
5649 %} | |
5650 ins_pipe(iload_mask_mem); | |
5651 %} | |
5652 | |
5653 // Load Integer to Short (16 bit signed) | |
5654 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5655 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5656 ins_cost(MEMORY_REF_COST); | |
5657 | |
5658 size(4); | |
5659 | |
5660 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5661 ins_encode %{ | |
5662 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5663 %} | |
5664 ins_pipe(iload_mask_mem); | |
5665 %} | |
5666 | |
5667 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5668 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5669 match(Set dst (AndI (LoadI mem) mask)); | |
5670 ins_cost(MEMORY_REF_COST); | |
5671 | |
5672 size(4); | |
5673 | |
5674 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5675 ins_encode %{ | |
5676 __ lduh($mem$$Address, $dst$$Register, 2); | |
5677 %} | |
5678 ins_pipe(iload_mask_mem); | |
5679 %} | |
5680 | |
624 | 5681 // Load Integer into a Long Register |
5682 instruct loadI2L(iRegL dst, memory mem) %{ | |
5683 match(Set dst (ConvI2L (LoadI mem))); | |
5684 ins_cost(MEMORY_REF_COST); | |
5685 | |
5686 size(4); | |
5687 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5688 ins_encode %{ |
5689 __ ldsw($mem$$Address, $dst$$Register); | |
5690 %} | |
824 | 5691 ins_pipe(iload_mask_mem); |
5692 %} | |
5693 | |
5694 // Load Integer with mask 0xFF into a Long Register | |
5695 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5696 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5697 ins_cost(MEMORY_REF_COST); | |
5698 | |
5699 size(4); | |
5700 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5701 ins_encode %{ | |
5702 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5703 %} | |
5704 ins_pipe(iload_mem); | |
5705 %} | |
5706 | |
5707 // Load Integer with mask 0xFFFF into a Long Register | |
5708 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5709 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5710 ins_cost(MEMORY_REF_COST); | |
5711 | |
5712 size(4); | |
5713 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5714 ins_encode %{ | |
5715 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5716 %} | |
5717 ins_pipe(iload_mem); | |
5718 %} | |
5719 | |
5720 // Load Integer with a 13-bit mask into a Long Register | |
5721 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5722 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5723 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5724 | |
5725 size(2*4); | |
5726 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
5727 "AND $dst,$mask,$dst" %} | |
5728 ins_encode %{ | |
5729 Register Rdst = $dst$$Register; | |
5730 __ lduw($mem$$Address, Rdst); | |
5731 __ and3(Rdst, $mask$$constant, Rdst); | |
5732 %} | |
5733 ins_pipe(iload_mem); | |
5734 %} | |
5735 | |
5736 // Load Integer with a 32-bit mask into a Long Register | |
5737 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
5738 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5739 effect(TEMP dst, TEMP tmp); | |
5740 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5741 | |
951
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|
5742 size((3+1)*4); // set may use two instructions. |
824 | 5743 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
5744 "SET $mask,$tmp\n\t" | |
5745 "AND $dst,$tmp,$dst" %} | |
5746 ins_encode %{ | |
5747 Register Rdst = $dst$$Register; | |
5748 Register Rtmp = $tmp$$Register; | |
5749 __ lduw($mem$$Address, Rdst); | |
5750 __ set($mask$$constant, Rtmp); | |
5751 __ and3(Rdst, Rtmp, Rdst); | |
5752 %} | |
624 | 5753 ins_pipe(iload_mem); |
5754 %} | |
5755 | |
5756 // Load Unsigned Integer into a Long Register | |
5757 instruct loadUI2L(iRegL dst, memory mem) %{ | |
5758 match(Set dst (LoadUI2L mem)); | |
5759 ins_cost(MEMORY_REF_COST); | |
5760 | |
5761 size(4); | |
5762 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5763 ins_encode %{ |
5764 __ lduw($mem$$Address, $dst$$Register); | |
5765 %} | |
0 | 5766 ins_pipe(iload_mem); |
5767 %} | |
5768 | |
5769 // Load Long - aligned | |
5770 instruct loadL(iRegL dst, memory mem ) %{ | |
5771 match(Set dst (LoadL mem)); | |
5772 ins_cost(MEMORY_REF_COST); | |
624 | 5773 |
0 | 5774 size(4); |
5775 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5776 ins_encode %{ |
5777 __ ldx($mem$$Address, $dst$$Register); | |
5778 %} | |
0 | 5779 ins_pipe(iload_mem); |
5780 %} | |
5781 | |
5782 // Load Long - UNaligned | |
5783 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5784 match(Set dst (LoadL_unaligned mem)); | |
5785 effect(KILL tmp); | |
5786 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5787 size(16); | |
5788 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5789 "\tLDUW $mem ,$dst\n" | |
5790 "\tSLLX #32, $dst, $dst\n" | |
5791 "\tOR $dst, R_O7, $dst" %} | |
5792 opcode(Assembler::lduw_op3); | |
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|
5793 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5794 ins_pipe(iload_mem); |
5795 %} | |
5796 | |
5797 // Load Aligned Packed Byte into a Double Register | |
5798 instruct loadA8B(regD dst, memory mem) %{ | |
5799 match(Set dst (Load8B mem)); | |
5800 ins_cost(MEMORY_REF_COST); | |
5801 size(4); | |
5802 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
5803 opcode(Assembler::lddf_op3); | |
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|
5804 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5805 ins_pipe(floadD_mem); |
5806 %} | |
5807 | |
5808 // Load Aligned Packed Char into a Double Register | |
5809 instruct loadA4C(regD dst, memory mem) %{ | |
5810 match(Set dst (Load4C mem)); | |
5811 ins_cost(MEMORY_REF_COST); | |
5812 size(4); | |
5813 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
5814 opcode(Assembler::lddf_op3); | |
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5815 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5816 ins_pipe(floadD_mem); |
5817 %} | |
5818 | |
5819 // Load Aligned Packed Short into a Double Register | |
5820 instruct loadA4S(regD dst, memory mem) %{ | |
5821 match(Set dst (Load4S mem)); | |
5822 ins_cost(MEMORY_REF_COST); | |
5823 size(4); | |
5824 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
5825 opcode(Assembler::lddf_op3); | |
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|
5826 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5827 ins_pipe(floadD_mem); |
5828 %} | |
5829 | |
5830 // Load Aligned Packed Int into a Double Register | |
5831 instruct loadA2I(regD dst, memory mem) %{ | |
5832 match(Set dst (Load2I mem)); | |
5833 ins_cost(MEMORY_REF_COST); | |
5834 size(4); | |
5835 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
5836 opcode(Assembler::lddf_op3); | |
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235
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|
5837 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5838 ins_pipe(floadD_mem); |
5839 %} | |
5840 | |
5841 // Load Range | |
5842 instruct loadRange(iRegI dst, memory mem) %{ | |
5843 match(Set dst (LoadRange mem)); | |
5844 ins_cost(MEMORY_REF_COST); | |
5845 | |
5846 size(4); | |
5847 format %{ "LDUW $mem,$dst\t! range" %} | |
5848 opcode(Assembler::lduw_op3); | |
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|
5849 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5850 ins_pipe(iload_mem); |
5851 %} | |
5852 | |
5853 // Load Integer into %f register (for fitos/fitod) | |
5854 instruct loadI_freg(regF dst, memory mem) %{ | |
5855 match(Set dst (LoadI mem)); | |
5856 ins_cost(MEMORY_REF_COST); | |
5857 size(4); | |
5858 | |
5859 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5860 opcode(Assembler::ldf_op3); | |
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|
5861 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5862 ins_pipe(floadF_mem); |
5863 %} | |
5864 | |
5865 // Load Pointer | |
5866 instruct loadP(iRegP dst, memory mem) %{ | |
5867 match(Set dst (LoadP mem)); | |
5868 ins_cost(MEMORY_REF_COST); | |
5869 size(4); | |
5870 | |
5871 #ifndef _LP64 | |
5872 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5873 ins_encode %{ |
5874 __ lduw($mem$$Address, $dst$$Register); | |
5875 %} | |
0 | 5876 #else |
5877 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5878 ins_encode %{ |
5879 __ ldx($mem$$Address, $dst$$Register); | |
5880 %} | |
0 | 5881 #endif |
5882 ins_pipe(iload_mem); | |
5883 %} | |
5884 | |
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5885 // Load Compressed Pointer |
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5886 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5887 match(Set dst (LoadN mem)); |
5888 ins_cost(MEMORY_REF_COST); | |
5889 size(4); | |
5890 | |
5891 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5892 ins_encode %{ | |
5893 __ lduw($mem$$Address, $dst$$Register); | |
5894 %} | |
5895 ins_pipe(iload_mem); | |
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5896 %} |
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5897 |
0 | 5898 // Load Klass Pointer |
5899 instruct loadKlass(iRegP dst, memory mem) %{ | |
5900 match(Set dst (LoadKlass mem)); | |
5901 ins_cost(MEMORY_REF_COST); | |
5902 size(4); | |
5903 | |
5904 #ifndef _LP64 | |
5905 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5906 ins_encode %{ |
5907 __ lduw($mem$$Address, $dst$$Register); | |
5908 %} | |
0 | 5909 #else |
5910 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5911 ins_encode %{ |
5912 __ ldx($mem$$Address, $dst$$Register); | |
5913 %} | |
0 | 5914 #endif |
5915 ins_pipe(iload_mem); | |
5916 %} | |
5917 | |
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5918 // Load narrow Klass Pointer |
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5919 instruct loadNKlass(iRegN dst, memory mem) %{ |
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5920 match(Set dst (LoadNKlass mem)); |
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5921 ins_cost(MEMORY_REF_COST); |
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5922 size(4); |
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5923 |
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5924 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5925 ins_encode %{ |
727 | 5926 __ lduw($mem$$Address, $dst$$Register); |
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5927 %} |
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|
5928 ins_pipe(iload_mem); |
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5929 %} |
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5930 |
0 | 5931 // Load Double |
5932 instruct loadD(regD dst, memory mem) %{ | |
5933 match(Set dst (LoadD mem)); | |
5934 ins_cost(MEMORY_REF_COST); | |
5935 | |
5936 size(4); | |
5937 format %{ "LDDF $mem,$dst" %} | |
5938 opcode(Assembler::lddf_op3); | |
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5939 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5940 ins_pipe(floadD_mem); |
5941 %} | |
5942 | |
5943 // Load Double - UNaligned | |
5944 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
5945 match(Set dst (LoadD_unaligned mem)); | |
5946 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5947 size(8); | |
5948 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
5949 "\tLDF $mem+4,$dst.lo\t!" %} | |
5950 opcode(Assembler::ldf_op3); | |
5951 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
5952 ins_pipe(iload_mem); | |
5953 %} | |
5954 | |
5955 // Load Float | |
5956 instruct loadF(regF dst, memory mem) %{ | |
5957 match(Set dst (LoadF mem)); | |
5958 ins_cost(MEMORY_REF_COST); | |
5959 | |
5960 size(4); | |
5961 format %{ "LDF $mem,$dst" %} | |
5962 opcode(Assembler::ldf_op3); | |
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5963 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5964 ins_pipe(floadF_mem); |
5965 %} | |
5966 | |
5967 // Load Constant | |
5968 instruct loadConI( iRegI dst, immI src ) %{ | |
5969 match(Set dst src); | |
5970 ins_cost(DEFAULT_COST * 3/2); | |
5971 format %{ "SET $src,$dst" %} | |
5972 ins_encode( Set32(src, dst) ); | |
5973 ins_pipe(ialu_hi_lo_reg); | |
5974 %} | |
5975 | |
5976 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
5977 match(Set dst src); | |
5978 | |
5979 size(4); | |
5980 format %{ "MOV $src,$dst" %} | |
5981 ins_encode( Set13( src, dst ) ); | |
5982 ins_pipe(ialu_imm); | |
5983 %} | |
5984 | |
5985 instruct loadConP(iRegP dst, immP src) %{ | |
5986 match(Set dst src); | |
5987 ins_cost(DEFAULT_COST * 3/2); | |
5988 format %{ "SET $src,$dst\t!ptr" %} | |
5989 // This rule does not use "expand" unlike loadConI because then | |
5990 // the result type is not known to be an Oop. An ADLC | |
5991 // enhancement will be needed to make that work - not worth it! | |
5992 | |
5993 ins_encode( SetPtr( src, dst ) ); | |
5994 ins_pipe(loadConP); | |
5995 | |
5996 %} | |
5997 | |
5998 instruct loadConP0(iRegP dst, immP0 src) %{ | |
5999 match(Set dst src); | |
6000 | |
6001 size(4); | |
6002 format %{ "CLR $dst\t!ptr" %} | |
6003 ins_encode( SetNull( dst ) ); | |
6004 ins_pipe(ialu_imm); | |
6005 %} | |
6006 | |
6007 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6008 match(Set dst src); | |
6009 ins_cost(DEFAULT_COST); | |
6010 format %{ "SET $src,$dst\t!ptr" %} | |
6011 ins_encode %{ | |
727 | 6012 AddressLiteral polling_page(os::get_polling_page()); |
6013 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6014 %} |
6015 ins_pipe(loadConP_poll); | |
6016 %} | |
6017 | |
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6018 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6019 match(Set dst src); |
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6020 |
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6021 size(4); |
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6022 format %{ "CLR $dst\t! compressed NULL ptr" %} |
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6023 ins_encode( SetNull( dst ) ); |
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6024 ins_pipe(ialu_imm); |
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6025 %} |
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6026 |
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6027 instruct loadConN(iRegN dst, immN src) %{ |
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6028 match(Set dst src); |
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6029 ins_cost(DEFAULT_COST * 3/2); |
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6030 format %{ "SET $src,$dst\t! compressed ptr" %} |
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6031 ins_encode %{ |
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6032 Register dst = $dst$$Register; |
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6033 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6034 %} |
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6035 ins_pipe(ialu_hi_lo_reg); |
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6036 %} |
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6037 |
0 | 6038 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
6039 // %%% maybe this should work like loadConD | |
6040 match(Set dst src); | |
6041 effect(KILL tmp); | |
6042 ins_cost(DEFAULT_COST * 4); | |
6043 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
6044 ins_encode( LdImmL(src, dst, tmp) ); | |
6045 ins_pipe(loadConL); | |
6046 %} | |
6047 | |
6048 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6049 match(Set dst src); | |
6050 ins_cost(DEFAULT_COST); | |
6051 size(4); | |
6052 format %{ "CLR $dst\t! long" %} | |
6053 ins_encode( Set13( src, dst ) ); | |
6054 ins_pipe(ialu_imm); | |
6055 %} | |
6056 | |
6057 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6058 match(Set dst src); | |
6059 ins_cost(DEFAULT_COST * 2); | |
6060 | |
6061 size(4); | |
6062 format %{ "MOV $src,$dst\t! long" %} | |
6063 ins_encode( Set13( src, dst ) ); | |
6064 ins_pipe(ialu_imm); | |
6065 %} | |
6066 | |
6067 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
6068 match(Set dst src); | |
6069 effect(KILL tmp); | |
6070 | |
6071 #ifdef _LP64 | |
727 | 6072 size(8*4); |
0 | 6073 #else |
727 | 6074 size(2*4); |
0 | 6075 #endif |
6076 | |
6077 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
6078 "LDF [$tmp+lo(&$src)],$dst" %} | |
727 | 6079 ins_encode %{ |
6080 address float_address = __ float_constant($src$$constant); | |
6081 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
6082 AddressLiteral addrlit(float_address, rspec); | |
6083 | |
6084 __ sethi(addrlit, $tmp$$Register); | |
6085 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); | |
6086 %} | |
0 | 6087 ins_pipe(loadConFD); |
6088 %} | |
6089 | |
6090 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
6091 match(Set dst src); | |
6092 effect(KILL tmp); | |
6093 | |
6094 #ifdef _LP64 | |
727 | 6095 size(8*4); |
0 | 6096 #else |
727 | 6097 size(2*4); |
0 | 6098 #endif |
6099 | |
6100 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
6101 "LDDF [$tmp+lo(&$src)],$dst" %} | |
727 | 6102 ins_encode %{ |
6103 address double_address = __ double_constant($src$$constant); | |
6104 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
6105 AddressLiteral addrlit(double_address, rspec); | |
6106 | |
6107 __ sethi(addrlit, $tmp$$Register); | |
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6108 // XXX This is a quick fix for 6833573. |
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6109 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
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6110 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
727 | 6111 %} |
0 | 6112 ins_pipe(loadConFD); |
6113 %} | |
6114 | |
6115 // Prefetch instructions. | |
6116 // Must be safe to execute with invalid address (cannot fault). | |
6117 | |
6118 instruct prefetchr( memory mem ) %{ | |
6119 match( PrefetchRead mem ); | |
6120 ins_cost(MEMORY_REF_COST); | |
6121 | |
6122 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6123 opcode(Assembler::prefetch_op3); | |
6124 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6125 ins_pipe(iload_mem); | |
6126 %} | |
6127 | |
6128 instruct prefetchw( memory mem ) %{ | |
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6129 predicate(AllocatePrefetchStyle != 3 ); |
0 | 6130 match( PrefetchWrite mem ); |
6131 ins_cost(MEMORY_REF_COST); | |
6132 | |
6133 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6134 opcode(Assembler::prefetch_op3); | |
6135 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6136 ins_pipe(iload_mem); | |
6137 %} | |
6138 | |
1367
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6139 // Use BIS instruction to prefetch. |
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6140 instruct prefetchw_bis( memory mem ) %{ |
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6141 predicate(AllocatePrefetchStyle == 3); |
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6142 match( PrefetchWrite mem ); |
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6143 ins_cost(MEMORY_REF_COST); |
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6144 |
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6145 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
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6146 ins_encode %{ |
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6147 Register base = as_Register($mem$$base); |
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6148 int disp = $mem$$disp; |
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6149 if (disp != 0) { |
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6150 __ add(base, AllocatePrefetchStepSize, base); |
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6151 } |
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6152 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
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6153 %} |
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6154 ins_pipe(istore_mem_reg); |
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6155 %} |
0 | 6156 |
6157 //----------Store Instructions------------------------------------------------- | |
6158 // Store Byte | |
6159 instruct storeB(memory mem, iRegI src) %{ | |
6160 match(Set mem (StoreB mem src)); | |
6161 ins_cost(MEMORY_REF_COST); | |
6162 | |
6163 size(4); | |
6164 format %{ "STB $src,$mem\t! byte" %} | |
6165 opcode(Assembler::stb_op3); | |
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6166 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6167 ins_pipe(istore_mem_reg); |
6168 %} | |
6169 | |
6170 instruct storeB0(memory mem, immI0 src) %{ | |
6171 match(Set mem (StoreB mem src)); | |
6172 ins_cost(MEMORY_REF_COST); | |
6173 | |
6174 size(4); | |
6175 format %{ "STB $src,$mem\t! byte" %} | |
6176 opcode(Assembler::stb_op3); | |
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6177 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6178 ins_pipe(istore_mem_zero); |
6179 %} | |
6180 | |
6181 instruct storeCM0(memory mem, immI0 src) %{ | |
6182 match(Set mem (StoreCM mem src)); | |
6183 ins_cost(MEMORY_REF_COST); | |
6184 | |
6185 size(4); | |
6186 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6187 opcode(Assembler::stb_op3); | |
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6188 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6189 ins_pipe(istore_mem_zero); |
6190 %} | |
6191 | |
6192 // Store Char/Short | |
6193 instruct storeC(memory mem, iRegI src) %{ | |
6194 match(Set mem (StoreC mem src)); | |
6195 ins_cost(MEMORY_REF_COST); | |
6196 | |
6197 size(4); | |
6198 format %{ "STH $src,$mem\t! short" %} | |
6199 opcode(Assembler::sth_op3); | |
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6200 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6201 ins_pipe(istore_mem_reg); |
6202 %} | |
6203 | |
6204 instruct storeC0(memory mem, immI0 src) %{ | |
6205 match(Set mem (StoreC mem src)); | |
6206 ins_cost(MEMORY_REF_COST); | |
6207 | |
6208 size(4); | |
6209 format %{ "STH $src,$mem\t! short" %} | |
6210 opcode(Assembler::sth_op3); | |
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6211 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6212 ins_pipe(istore_mem_zero); |
6213 %} | |
6214 | |
6215 // Store Integer | |
6216 instruct storeI(memory mem, iRegI src) %{ | |
6217 match(Set mem (StoreI mem src)); | |
6218 ins_cost(MEMORY_REF_COST); | |
6219 | |
6220 size(4); | |
6221 format %{ "STW $src,$mem" %} | |
6222 opcode(Assembler::stw_op3); | |
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6223 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6224 ins_pipe(istore_mem_reg); |
6225 %} | |
6226 | |
6227 // Store Long | |
6228 instruct storeL(memory mem, iRegL src) %{ | |
6229 match(Set mem (StoreL mem src)); | |
6230 ins_cost(MEMORY_REF_COST); | |
6231 size(4); | |
6232 format %{ "STX $src,$mem\t! long" %} | |
6233 opcode(Assembler::stx_op3); | |
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6234 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6235 ins_pipe(istore_mem_reg); |
6236 %} | |
6237 | |
6238 instruct storeI0(memory mem, immI0 src) %{ | |
6239 match(Set mem (StoreI mem src)); | |
6240 ins_cost(MEMORY_REF_COST); | |
6241 | |
6242 size(4); | |
6243 format %{ "STW $src,$mem" %} | |
6244 opcode(Assembler::stw_op3); | |
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6245 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6246 ins_pipe(istore_mem_zero); |
6247 %} | |
6248 | |
6249 instruct storeL0(memory mem, immL0 src) %{ | |
6250 match(Set mem (StoreL mem src)); | |
6251 ins_cost(MEMORY_REF_COST); | |
6252 | |
6253 size(4); | |
6254 format %{ "STX $src,$mem" %} | |
6255 opcode(Assembler::stx_op3); | |
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6256 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6257 ins_pipe(istore_mem_zero); |
6258 %} | |
6259 | |
6260 // Store Integer from float register (used after fstoi) | |
6261 instruct storeI_Freg(memory mem, regF src) %{ | |
6262 match(Set mem (StoreI mem src)); | |
6263 ins_cost(MEMORY_REF_COST); | |
6264 | |
6265 size(4); | |
6266 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6267 opcode(Assembler::stf_op3); | |
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6268 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6269 ins_pipe(fstoreF_mem_reg); |
6270 %} | |
6271 | |
6272 // Store Pointer | |
6273 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6274 match(Set dst (StoreP dst src)); | |
6275 ins_cost(MEMORY_REF_COST); | |
6276 size(4); | |
6277 | |
6278 #ifndef _LP64 | |
6279 format %{ "STW $src,$dst\t! ptr" %} | |
6280 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6281 #else | |
6282 format %{ "STX $src,$dst\t! ptr" %} | |
6283 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6284 #endif | |
6285 ins_encode( form3_mem_reg( dst, src ) ); | |
6286 ins_pipe(istore_mem_spORreg); | |
6287 %} | |
6288 | |
6289 instruct storeP0(memory dst, immP0 src) %{ | |
6290 match(Set dst (StoreP dst src)); | |
6291 ins_cost(MEMORY_REF_COST); | |
6292 size(4); | |
6293 | |
6294 #ifndef _LP64 | |
6295 format %{ "STW $src,$dst\t! ptr" %} | |
6296 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6297 #else | |
6298 format %{ "STX $src,$dst\t! ptr" %} | |
6299 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6300 #endif | |
6301 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6302 ins_pipe(istore_mem_zero); | |
6303 %} | |
6304 | |
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6305 // Store Compressed Pointer |
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6306 instruct storeN(memory dst, iRegN src) %{ |
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6307 match(Set dst (StoreN dst src)); |
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6308 ins_cost(MEMORY_REF_COST); |
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6309 size(4); |
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6310 |
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6311 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6312 ins_encode %{ |
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6313 Register base = as_Register($dst$$base); |
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6314 Register index = as_Register($dst$$index); |
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6315 Register src = $src$$Register; |
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6316 if (index != G0) { |
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6317 __ stw(src, base, index); |
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6318 } else { |
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6319 __ stw(src, base, $dst$$disp); |
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6320 } |
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6321 %} |
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6322 ins_pipe(istore_mem_spORreg); |
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6323 %} |
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6324 |
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6325 instruct storeN0(memory dst, immN0 src) %{ |
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6326 match(Set dst (StoreN dst src)); |
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6327 ins_cost(MEMORY_REF_COST); |
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6328 size(4); |
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6329 |
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6330 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6331 ins_encode %{ |
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6332 Register base = as_Register($dst$$base); |
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6333 Register index = as_Register($dst$$index); |
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6334 if (index != G0) { |
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6335 __ stw(0, base, index); |
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6336 } else { |
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6337 __ stw(0, base, $dst$$disp); |
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6338 } |
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6339 %} |
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6340 ins_pipe(istore_mem_zero); |
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6341 %} |
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6342 |
0 | 6343 // Store Double |
6344 instruct storeD( memory mem, regD src) %{ | |
6345 match(Set mem (StoreD mem src)); | |
6346 ins_cost(MEMORY_REF_COST); | |
6347 | |
6348 size(4); | |
6349 format %{ "STDF $src,$mem" %} | |
6350 opcode(Assembler::stdf_op3); | |
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6351 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6352 ins_pipe(fstoreD_mem_reg); |
6353 %} | |
6354 | |
6355 instruct storeD0( memory mem, immD0 src) %{ | |
6356 match(Set mem (StoreD mem src)); | |
6357 ins_cost(MEMORY_REF_COST); | |
6358 | |
6359 size(4); | |
6360 format %{ "STX $src,$mem" %} | |
6361 opcode(Assembler::stx_op3); | |
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6362 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6363 ins_pipe(fstoreD_mem_zero); |
6364 %} | |
6365 | |
6366 // Store Float | |
6367 instruct storeF( memory mem, regF src) %{ | |
6368 match(Set mem (StoreF mem src)); | |
6369 ins_cost(MEMORY_REF_COST); | |
6370 | |
6371 size(4); | |
6372 format %{ "STF $src,$mem" %} | |
6373 opcode(Assembler::stf_op3); | |
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6374 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6375 ins_pipe(fstoreF_mem_reg); |
6376 %} | |
6377 | |
6378 instruct storeF0( memory mem, immF0 src) %{ | |
6379 match(Set mem (StoreF mem src)); | |
6380 ins_cost(MEMORY_REF_COST); | |
6381 | |
6382 size(4); | |
6383 format %{ "STW $src,$mem\t! storeF0" %} | |
6384 opcode(Assembler::stw_op3); | |
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6385 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6386 ins_pipe(fstoreF_mem_zero); |
6387 %} | |
6388 | |
6389 // Store Aligned Packed Bytes in Double register to memory | |
6390 instruct storeA8B(memory mem, regD src) %{ | |
6391 match(Set mem (Store8B mem src)); | |
6392 ins_cost(MEMORY_REF_COST); | |
6393 size(4); | |
6394 format %{ "STDF $src,$mem\t! packed8B" %} | |
6395 opcode(Assembler::stdf_op3); | |
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6396 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6397 ins_pipe(fstoreD_mem_reg); |
6398 %} | |
6399 | |
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6400 // Convert oop pointer into compressed form |
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6401 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
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6402 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
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6403 match(Set dst (EncodeP src)); |
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6404 format %{ "encode_heap_oop $src, $dst" %} |
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6405 ins_encode %{ |
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6406 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6407 %} |
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6408 ins_pipe(ialu_reg); |
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6409 %} |
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6410 |
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6411 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
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6412 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
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6413 match(Set dst (EncodeP src)); |
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6414 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6415 ins_encode %{ |
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6416 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6417 %} |
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|
6418 ins_pipe(ialu_reg); |
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|
6419 %} |
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|
6420 |
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6421 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
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6422 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6423 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
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6424 match(Set dst (DecodeN src)); |
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6425 format %{ "decode_heap_oop $src, $dst" %} |
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6426 ins_encode %{ |
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6427 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6428 %} |
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6429 ins_pipe(ialu_reg); |
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6430 %} |
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6431 |
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6432 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
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6433 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
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6434 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
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|
6435 match(Set dst (DecodeN src)); |
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6436 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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6437 ins_encode %{ |
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|
6438 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6439 %} |
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|
6440 ins_pipe(ialu_reg); |
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|
6441 %} |
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|
6442 |
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6443 |
0 | 6444 // Store Zero into Aligned Packed Bytes |
6445 instruct storeA8B0(memory mem, immI0 zero) %{ | |
6446 match(Set mem (Store8B mem zero)); | |
6447 ins_cost(MEMORY_REF_COST); | |
6448 size(4); | |
6449 format %{ "STX $zero,$mem\t! packed8B" %} | |
6450 opcode(Assembler::stx_op3); | |
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6451 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6452 ins_pipe(fstoreD_mem_zero); |
6453 %} | |
6454 | |
6455 // Store Aligned Packed Chars/Shorts in Double register to memory | |
6456 instruct storeA4C(memory mem, regD src) %{ | |
6457 match(Set mem (Store4C mem src)); | |
6458 ins_cost(MEMORY_REF_COST); | |
6459 size(4); | |
6460 format %{ "STDF $src,$mem\t! packed4C" %} | |
6461 opcode(Assembler::stdf_op3); | |
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6462 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6463 ins_pipe(fstoreD_mem_reg); |
6464 %} | |
6465 | |
6466 // Store Zero into Aligned Packed Chars/Shorts | |
6467 instruct storeA4C0(memory mem, immI0 zero) %{ | |
6468 match(Set mem (Store4C mem (Replicate4C zero))); | |
6469 ins_cost(MEMORY_REF_COST); | |
6470 size(4); | |
6471 format %{ "STX $zero,$mem\t! packed4C" %} | |
6472 opcode(Assembler::stx_op3); | |
415
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6473 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6474 ins_pipe(fstoreD_mem_zero); |
6475 %} | |
6476 | |
6477 // Store Aligned Packed Ints in Double register to memory | |
6478 instruct storeA2I(memory mem, regD src) %{ | |
6479 match(Set mem (Store2I mem src)); | |
6480 ins_cost(MEMORY_REF_COST); | |
6481 size(4); | |
6482 format %{ "STDF $src,$mem\t! packed2I" %} | |
6483 opcode(Assembler::stdf_op3); | |
415
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6484 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6485 ins_pipe(fstoreD_mem_reg); |
6486 %} | |
6487 | |
6488 // Store Zero into Aligned Packed Ints | |
6489 instruct storeA2I0(memory mem, immI0 zero) %{ | |
6490 match(Set mem (Store2I mem zero)); | |
6491 ins_cost(MEMORY_REF_COST); | |
6492 size(4); | |
6493 format %{ "STX $zero,$mem\t! packed2I" %} | |
6494 opcode(Assembler::stx_op3); | |
415
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changeset
|
6495 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6496 ins_pipe(fstoreD_mem_zero); |
6497 %} | |
6498 | |
6499 | |
6500 //----------MemBar Instructions----------------------------------------------- | |
6501 // Memory barrier flavors | |
6502 | |
6503 instruct membar_acquire() %{ | |
6504 match(MemBarAcquire); | |
6505 ins_cost(4*MEMORY_REF_COST); | |
6506 | |
6507 size(0); | |
6508 format %{ "MEMBAR-acquire" %} | |
6509 ins_encode( enc_membar_acquire ); | |
6510 ins_pipe(long_memory_op); | |
6511 %} | |
6512 | |
6513 instruct membar_acquire_lock() %{ | |
6514 match(MemBarAcquire); | |
6515 predicate(Matcher::prior_fast_lock(n)); | |
6516 ins_cost(0); | |
6517 | |
6518 size(0); | |
6519 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6520 ins_encode( ); | |
6521 ins_pipe(empty); | |
6522 %} | |
6523 | |
6524 instruct membar_release() %{ | |
6525 match(MemBarRelease); | |
6526 ins_cost(4*MEMORY_REF_COST); | |
6527 | |
6528 size(0); | |
6529 format %{ "MEMBAR-release" %} | |
6530 ins_encode( enc_membar_release ); | |
6531 ins_pipe(long_memory_op); | |
6532 %} | |
6533 | |
6534 instruct membar_release_lock() %{ | |
6535 match(MemBarRelease); | |
6536 predicate(Matcher::post_fast_unlock(n)); | |
6537 ins_cost(0); | |
6538 | |
6539 size(0); | |
6540 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6541 ins_encode( ); | |
6542 ins_pipe(empty); | |
6543 %} | |
6544 | |
6545 instruct membar_volatile() %{ | |
6546 match(MemBarVolatile); | |
6547 ins_cost(4*MEMORY_REF_COST); | |
6548 | |
6549 size(4); | |
6550 format %{ "MEMBAR-volatile" %} | |
6551 ins_encode( enc_membar_volatile ); | |
6552 ins_pipe(long_memory_op); | |
6553 %} | |
6554 | |
6555 instruct unnecessary_membar_volatile() %{ | |
6556 match(MemBarVolatile); | |
6557 predicate(Matcher::post_store_load_barrier(n)); | |
6558 ins_cost(0); | |
6559 | |
6560 size(0); | |
6561 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6562 ins_encode( ); | |
6563 ins_pipe(empty); | |
6564 %} | |
6565 | |
6566 //----------Register Move Instructions----------------------------------------- | |
6567 instruct roundDouble_nop(regD dst) %{ | |
6568 match(Set dst (RoundDouble dst)); | |
6569 ins_cost(0); | |
6570 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6571 ins_encode( ); | |
6572 ins_pipe(empty); | |
6573 %} | |
6574 | |
6575 | |
6576 instruct roundFloat_nop(regF dst) %{ | |
6577 match(Set dst (RoundFloat dst)); | |
6578 ins_cost(0); | |
6579 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6580 ins_encode( ); | |
6581 ins_pipe(empty); | |
6582 %} | |
6583 | |
6584 | |
6585 // Cast Index to Pointer for unsafe natives | |
6586 instruct castX2P(iRegX src, iRegP dst) %{ | |
6587 match(Set dst (CastX2P src)); | |
6588 | |
6589 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6590 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6591 ins_pipe(ialu_reg); | |
6592 %} | |
6593 | |
6594 // Cast Pointer to Index for unsafe natives | |
6595 instruct castP2X(iRegP src, iRegX dst) %{ | |
6596 match(Set dst (CastP2X src)); | |
6597 | |
6598 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6599 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6600 ins_pipe(ialu_reg); | |
6601 %} | |
6602 | |
6603 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6604 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6605 match(Set stkSlot src); // chain rule | |
6606 ins_cost(MEMORY_REF_COST); | |
6607 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6608 opcode(Assembler::stdf_op3); | |
415
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|
6609 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6610 ins_pipe(fstoreD_stk_reg); |
6611 %} | |
6612 | |
6613 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6614 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6615 match(Set dst stkSlot); // chain rule | |
6616 ins_cost(MEMORY_REF_COST); | |
6617 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6618 opcode(Assembler::lddf_op3); | |
415
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diff
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|
6619 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6620 ins_pipe(floadD_stk); |
6621 %} | |
6622 | |
6623 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6624 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6625 match(Set stkSlot src); // chain rule | |
6626 ins_cost(MEMORY_REF_COST); | |
6627 format %{ "STF $src,$stkSlot\t!stk" %} | |
6628 opcode(Assembler::stf_op3); | |
415
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|
6629 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6630 ins_pipe(fstoreF_stk_reg); |
6631 %} | |
6632 | |
6633 //----------Conditional Move--------------------------------------------------- | |
6634 // Conditional move | |
6635 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6636 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6637 ins_cost(150); | |
6638 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6639 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6640 ins_pipe(ialu_reg); | |
6641 %} | |
6642 | |
6643 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6644 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6645 ins_cost(140); | |
6646 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6647 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6648 ins_pipe(ialu_imm); | |
6649 %} | |
6650 | |
6651 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6652 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6653 ins_cost(150); | |
6654 size(4); | |
6655 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6656 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6657 ins_pipe(ialu_reg); | |
6658 %} | |
6659 | |
6660 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6661 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6662 ins_cost(140); | |
6663 size(4); | |
6664 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6665 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6666 ins_pipe(ialu_imm); | |
6667 %} | |
6668 | |
1160
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|
6669 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6670 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6671 ins_cost(150); | |
6672 size(4); | |
6673 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6674 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6675 ins_pipe(ialu_reg); | |
6676 %} | |
6677 | |
1160
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diff
changeset
|
6678 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6679 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6680 ins_cost(140); | |
6681 size(4); | |
6682 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6683 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6684 ins_pipe(ialu_imm); | |
6685 %} | |
6686 | |
6687 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6688 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6689 ins_cost(150); | |
6690 size(4); | |
6691 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6692 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6693 ins_pipe(ialu_reg); | |
6694 %} | |
6695 | |
6696 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6697 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6698 ins_cost(140); | |
6699 size(4); | |
6700 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6701 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6702 ins_pipe(ialu_imm); | |
6703 %} | |
6704 | |
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|
6705 // Conditional move for RegN. Only cmov(reg,reg). |
c436414a719e
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diff
changeset
|
6706 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
c436414a719e
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diff
changeset
|
6707 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
c436414a719e
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parents:
163
diff
changeset
|
6708 ins_cost(150); |
c436414a719e
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parents:
163
diff
changeset
|
6709 format %{ "MOV$cmp $pcc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6710 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6711 ins_pipe(ialu_reg); |
c436414a719e
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parents:
163
diff
changeset
|
6712 %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6713 |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6714 // This instruction also works with CmpN so we don't need cmovNN_reg. |
c436414a719e
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kvn
parents:
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diff
changeset
|
6715 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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163
diff
changeset
|
6716 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6717 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6718 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6719 format %{ "MOV$cmp $icc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6720 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6721 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6722 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6723 |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6724 // This instruction also works with CmpN so we don't need cmovNN_reg. |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6725 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6726 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6727 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6728 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6729 format %{ "MOV$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6730 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6731 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6732 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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diff
changeset
|
6733 |
164
c436414a719e
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kvn
parents:
163
diff
changeset
|
6734 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
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163
diff
changeset
|
6735 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
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kvn
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163
diff
changeset
|
6736 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6737 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
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163
diff
changeset
|
6738 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
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parents:
163
diff
changeset
|
6739 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
c436414a719e
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163
diff
changeset
|
6740 ins_pipe(ialu_reg); |
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|
6741 %} |
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|
6742 |
0 | 6743 // Conditional move |
6744 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6745 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6746 ins_cost(150); | |
6747 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6748 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6749 ins_pipe(ialu_reg); | |
6750 %} | |
6751 | |
6752 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6753 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6754 ins_cost(140); | |
6755 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6756 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6757 ins_pipe(ialu_imm); | |
6758 %} | |
6759 | |
164
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|
6760 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6761 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6762 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6763 ins_cost(150); | |
6764 | |
6765 size(4); | |
6766 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6767 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6768 ins_pipe(ialu_reg); | |
6769 %} | |
6770 | |
1160
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1137
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changeset
|
6771 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6772 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
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1137
diff
changeset
|
6773 ins_cost(150); |
f24201449cac
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1137
diff
changeset
|
6774 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6775 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6776 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
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diff
changeset
|
6777 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6778 ins_pipe(ialu_reg); |
f24201449cac
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diff
changeset
|
6779 %} |
f24201449cac
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1137
diff
changeset
|
6780 |
0 | 6781 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
6782 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6783 ins_cost(140); | |
6784 | |
6785 size(4); | |
6786 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6787 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6788 ins_pipe(ialu_imm); | |
6789 %} | |
6790 | |
1160
f24201449cac
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1137
diff
changeset
|
6791 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
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changeset
|
6792 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6793 ins_cost(140); |
f24201449cac
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1137
diff
changeset
|
6794 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6795 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6796 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
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diff
changeset
|
6797 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
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diff
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|
6798 ins_pipe(ialu_imm); |
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diff
changeset
|
6799 %} |
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diff
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|
6800 |
0 | 6801 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
6802 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6803 ins_cost(150); | |
6804 size(4); | |
6805 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6806 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6807 ins_pipe(ialu_imm); | |
6808 %} | |
6809 | |
6810 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6811 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6812 ins_cost(140); | |
6813 size(4); | |
6814 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6815 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6816 ins_pipe(ialu_imm); | |
6817 %} | |
6818 | |
6819 // Conditional move | |
6820 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6821 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6822 ins_cost(150); | |
6823 opcode(0x101); | |
6824 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6825 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6826 ins_pipe(int_conditional_float_move); | |
6827 %} | |
6828 | |
6829 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6830 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6831 ins_cost(150); | |
6832 | |
6833 size(4); | |
6834 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6835 opcode(0x101); | |
6836 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6837 ins_pipe(int_conditional_float_move); | |
6838 %} | |
6839 | |
1160
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changeset
|
6840 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6841 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6842 ins_cost(150); |
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diff
changeset
|
6843 |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6844 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6845 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6846 opcode(0x101); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6847 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
6848 ins_pipe(int_conditional_float_move); |
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changeset
|
6849 %} |
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changeset
|
6850 |
0 | 6851 // Conditional move, |
6852 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6853 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6854 ins_cost(150); | |
6855 size(4); | |
6856 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6857 opcode(0x1); | |
6858 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6859 ins_pipe(int_conditional_double_move); | |
6860 %} | |
6861 | |
6862 // Conditional move | |
6863 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6864 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
6865 ins_cost(150); | |
6866 size(4); | |
6867 opcode(0x102); | |
6868 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6869 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6870 ins_pipe(int_conditional_double_move); | |
6871 %} | |
6872 | |
6873 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
6874 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
6875 ins_cost(150); | |
6876 | |
6877 size(4); | |
6878 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
6879 opcode(0x102); | |
6880 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6881 ins_pipe(int_conditional_double_move); | |
6882 %} | |
6883 | |
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6884 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6885 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
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changeset
|
6886 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6887 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6888 size(4); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6889 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
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changeset
|
6890 opcode(0x102); |
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changeset
|
6891 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
6892 ins_pipe(int_conditional_double_move); |
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changeset
|
6893 %} |
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changeset
|
6894 |
0 | 6895 // Conditional move, |
6896 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
6897 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
6898 ins_cost(150); | |
6899 size(4); | |
6900 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
6901 opcode(0x2); | |
6902 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6903 ins_pipe(int_conditional_double_move); | |
6904 %} | |
6905 | |
6906 // Conditional move | |
6907 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
6908 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6909 ins_cost(150); | |
6910 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6911 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6912 ins_pipe(ialu_reg); | |
6913 %} | |
6914 | |
6915 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
6916 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6917 ins_cost(140); | |
6918 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6919 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6920 ins_pipe(ialu_imm); | |
6921 %} | |
6922 | |
6923 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
6924 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
6925 ins_cost(150); | |
6926 | |
6927 size(4); | |
6928 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
6929 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6930 ins_pipe(ialu_reg); | |
6931 %} | |
6932 | |
6933 | |
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6934 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6935 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
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changeset
|
6936 ins_cost(150); |
f24201449cac
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diff
changeset
|
6937 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6938 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6939 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
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changeset
|
6940 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6941 ins_pipe(ialu_reg); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6942 %} |
f24201449cac
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changeset
|
6943 |
f24201449cac
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changeset
|
6944 |
0 | 6945 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
6946 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
6947 ins_cost(150); | |
6948 | |
6949 size(4); | |
6950 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
6951 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6952 ins_pipe(ialu_reg); | |
6953 %} | |
6954 | |
6955 | |
6956 | |
6957 //----------OS and Locking Instructions---------------------------------------- | |
6958 | |
6959 // This name is KNOWN by the ADLC and cannot be changed. | |
6960 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
6961 // for this guy. | |
6962 instruct tlsLoadP(g2RegP dst) %{ | |
6963 match(Set dst (ThreadLocal)); | |
6964 | |
6965 size(0); | |
6966 ins_cost(0); | |
6967 format %{ "# TLS is in G2" %} | |
6968 ins_encode( /*empty encoding*/ ); | |
6969 ins_pipe(ialu_none); | |
6970 %} | |
6971 | |
6972 instruct checkCastPP( iRegP dst ) %{ | |
6973 match(Set dst (CheckCastPP dst)); | |
6974 | |
6975 size(0); | |
6976 format %{ "# checkcastPP of $dst" %} | |
6977 ins_encode( /*empty encoding*/ ); | |
6978 ins_pipe(empty); | |
6979 %} | |
6980 | |
6981 | |
6982 instruct castPP( iRegP dst ) %{ | |
6983 match(Set dst (CastPP dst)); | |
6984 format %{ "# castPP of $dst" %} | |
6985 ins_encode( /*empty encoding*/ ); | |
6986 ins_pipe(empty); | |
6987 %} | |
6988 | |
6989 instruct castII( iRegI dst ) %{ | |
6990 match(Set dst (CastII dst)); | |
6991 format %{ "# castII of $dst" %} | |
6992 ins_encode( /*empty encoding*/ ); | |
6993 ins_cost(0); | |
6994 ins_pipe(empty); | |
6995 %} | |
6996 | |
6997 //----------Arithmetic Instructions-------------------------------------------- | |
6998 // Addition Instructions | |
6999 // Register Addition | |
7000 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7001 match(Set dst (AddI src1 src2)); | |
7002 | |
7003 size(4); | |
7004 format %{ "ADD $src1,$src2,$dst" %} | |
7005 ins_encode %{ | |
7006 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7007 %} | |
7008 ins_pipe(ialu_reg_reg); | |
7009 %} | |
7010 | |
7011 // Immediate Addition | |
7012 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7013 match(Set dst (AddI src1 src2)); | |
7014 | |
7015 size(4); | |
7016 format %{ "ADD $src1,$src2,$dst" %} | |
7017 opcode(Assembler::add_op3, Assembler::arith_op); | |
7018 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7019 ins_pipe(ialu_reg_imm); | |
7020 %} | |
7021 | |
7022 // Pointer Register Addition | |
7023 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7024 match(Set dst (AddP src1 src2)); | |
7025 | |
7026 size(4); | |
7027 format %{ "ADD $src1,$src2,$dst" %} | |
7028 opcode(Assembler::add_op3, Assembler::arith_op); | |
7029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7030 ins_pipe(ialu_reg_reg); | |
7031 %} | |
7032 | |
7033 // Pointer Immediate Addition | |
7034 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7035 match(Set dst (AddP src1 src2)); | |
7036 | |
7037 size(4); | |
7038 format %{ "ADD $src1,$src2,$dst" %} | |
7039 opcode(Assembler::add_op3, Assembler::arith_op); | |
7040 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7041 ins_pipe(ialu_reg_imm); | |
7042 %} | |
7043 | |
7044 // Long Addition | |
7045 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7046 match(Set dst (AddL src1 src2)); | |
7047 | |
7048 size(4); | |
7049 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7050 opcode(Assembler::add_op3, Assembler::arith_op); | |
7051 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7052 ins_pipe(ialu_reg_reg); | |
7053 %} | |
7054 | |
7055 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7056 match(Set dst (AddL src1 con)); | |
7057 | |
7058 size(4); | |
7059 format %{ "ADD $src1,$con,$dst" %} | |
7060 opcode(Assembler::add_op3, Assembler::arith_op); | |
7061 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7062 ins_pipe(ialu_reg_imm); | |
7063 %} | |
7064 | |
7065 //----------Conditional_store-------------------------------------------------- | |
7066 // Conditional-store of the updated heap-top. | |
7067 // Used during allocation of the shared heap. | |
7068 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7069 | |
7070 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7071 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7072 match(Set dst (LoadPLocked mem)); | |
7073 ins_cost(MEMORY_REF_COST); | |
7074 | |
7075 #ifndef _LP64 | |
7076 size(4); | |
7077 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7078 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7079 #else | |
7080 format %{ "LDX $mem,$dst\t! ptr" %} | |
7081 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7082 #endif | |
7083 ins_encode( form3_mem_reg( mem, dst ) ); | |
7084 ins_pipe(iload_mem); | |
7085 %} | |
7086 | |
7087 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
7088 instruct loadLLocked(iRegL dst, memory mem) %{ | |
7089 match(Set dst (LoadLLocked mem)); | |
7090 ins_cost(MEMORY_REF_COST); | |
7091 size(4); | |
7092 format %{ "LDX $mem,$dst\t! long" %} | |
7093 opcode(Assembler::ldx_op3); | |
415
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|
7094 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 7095 ins_pipe(iload_mem); |
7096 %} | |
7097 | |
7098 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7099 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7100 effect( KILL newval ); | |
7101 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7102 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7103 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7104 ins_pipe( long_memory_op ); | |
7105 %} | |
7106 | |
420
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|
7107 // Conditional-store of an int value. |
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diff
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|
7108 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7109 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
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diff
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|
7110 effect( KILL newval ); |
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changeset
|
7111 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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|
7112 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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|
7113 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7114 ins_pipe( long_memory_op ); |
7115 %} | |
7116 | |
420
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|
7117 // Conditional-store of a long value. |
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7118 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
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changeset
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7119 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
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diff
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|
7120 effect( KILL newval ); |
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|
7121 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7122 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7123 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7124 ins_pipe( long_memory_op ); |
7125 %} | |
7126 | |
7127 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7128 | |
7129 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7130 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
7131 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7132 format %{ | |
7133 "MOV $newval,O7\n\t" | |
7134 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7135 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7136 "MOV 1,$res\n\t" | |
7137 "MOVne xcc,R_G0,$res" | |
7138 %} | |
7139 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7140 enc_lflags_ne_to_boolean(res) ); | |
7141 ins_pipe( long_memory_op ); | |
7142 %} | |
7143 | |
7144 | |
7145 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7146 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7147 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7148 format %{ | |
7149 "MOV $newval,O7\n\t" | |
7150 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7151 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7152 "MOV 1,$res\n\t" | |
7153 "MOVne icc,R_G0,$res" | |
7154 %} | |
7155 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7156 enc_iflags_ne_to_boolean(res) ); | |
7157 ins_pipe( long_memory_op ); | |
7158 %} | |
7159 | |
7160 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7161 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
7162 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7163 format %{ | |
7164 "MOV $newval,O7\n\t" | |
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7165 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7166 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7167 "MOV 1,$res\n\t" | |
7168 "MOVne xcc,R_G0,$res" | |
7169 %} | |
113
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7170 #ifdef _LP64 |
0 | 7171 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7172 enc_lflags_ne_to_boolean(res) ); | |
7173 #else | |
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7174 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7175 enc_iflags_ne_to_boolean(res) ); |
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7176 #endif |
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7177 ins_pipe( long_memory_op ); |
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7178 %} |
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7179 |
181
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7180 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
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7181 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7182 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7183 format %{ |
7184 "MOV $newval,O7\n\t" | |
7185 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7186 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7187 "MOV 1,$res\n\t" | |
7188 "MOVne icc,R_G0,$res" | |
7189 %} | |
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7190 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7191 enc_iflags_ne_to_boolean(res) ); |
0 | 7192 ins_pipe( long_memory_op ); |
7193 %} | |
7194 | |
7195 //--------------------- | |
7196 // Subtraction Instructions | |
7197 // Register Subtraction | |
7198 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7199 match(Set dst (SubI src1 src2)); | |
7200 | |
7201 size(4); | |
7202 format %{ "SUB $src1,$src2,$dst" %} | |
7203 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7204 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7205 ins_pipe(ialu_reg_reg); | |
7206 %} | |
7207 | |
7208 // Immediate Subtraction | |
7209 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7210 match(Set dst (SubI src1 src2)); | |
7211 | |
7212 size(4); | |
7213 format %{ "SUB $src1,$src2,$dst" %} | |
7214 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7215 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7216 ins_pipe(ialu_reg_imm); | |
7217 %} | |
7218 | |
7219 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7220 match(Set dst (SubI zero src2)); | |
7221 | |
7222 size(4); | |
7223 format %{ "NEG $src2,$dst" %} | |
7224 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7225 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7226 ins_pipe(ialu_zero_reg); | |
7227 %} | |
7228 | |
7229 // Long subtraction | |
7230 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7231 match(Set dst (SubL src1 src2)); | |
7232 | |
7233 size(4); | |
7234 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7235 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7236 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7237 ins_pipe(ialu_reg_reg); | |
7238 %} | |
7239 | |
7240 // Immediate Subtraction | |
7241 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7242 match(Set dst (SubL src1 con)); | |
7243 | |
7244 size(4); | |
7245 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7246 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7247 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7248 ins_pipe(ialu_reg_imm); | |
7249 %} | |
7250 | |
7251 // Long negation | |
7252 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7253 match(Set dst (SubL zero src2)); | |
7254 | |
7255 size(4); | |
7256 format %{ "NEG $src2,$dst\t! long" %} | |
7257 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7258 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7259 ins_pipe(ialu_zero_reg); | |
7260 %} | |
7261 | |
7262 // Multiplication Instructions | |
7263 // Integer Multiplication | |
7264 // Register Multiplication | |
7265 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7266 match(Set dst (MulI src1 src2)); | |
7267 | |
7268 size(4); | |
7269 format %{ "MULX $src1,$src2,$dst" %} | |
7270 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7271 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7272 ins_pipe(imul_reg_reg); | |
7273 %} | |
7274 | |
7275 // Immediate Multiplication | |
7276 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7277 match(Set dst (MulI src1 src2)); | |
7278 | |
7279 size(4); | |
7280 format %{ "MULX $src1,$src2,$dst" %} | |
7281 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7282 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7283 ins_pipe(imul_reg_imm); | |
7284 %} | |
7285 | |
7286 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7287 match(Set dst (MulL src1 src2)); | |
7288 ins_cost(DEFAULT_COST * 5); | |
7289 size(4); | |
7290 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7291 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7292 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7293 ins_pipe(mulL_reg_reg); | |
7294 %} | |
7295 | |
7296 // Immediate Multiplication | |
7297 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7298 match(Set dst (MulL src1 src2)); | |
7299 ins_cost(DEFAULT_COST * 5); | |
7300 size(4); | |
7301 format %{ "MULX $src1,$src2,$dst" %} | |
7302 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7303 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7304 ins_pipe(mulL_reg_imm); | |
7305 %} | |
7306 | |
7307 // Integer Division | |
7308 // Register Division | |
7309 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7310 match(Set dst (DivI src1 src2)); | |
7311 ins_cost((2+71)*DEFAULT_COST); | |
7312 | |
7313 format %{ "SRA $src2,0,$src2\n\t" | |
7314 "SRA $src1,0,$src1\n\t" | |
7315 "SDIVX $src1,$src2,$dst" %} | |
7316 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7317 ins_pipe(sdiv_reg_reg); | |
7318 %} | |
7319 | |
7320 // Immediate Division | |
7321 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7322 match(Set dst (DivI src1 src2)); | |
7323 ins_cost((2+71)*DEFAULT_COST); | |
7324 | |
7325 format %{ "SRA $src1,0,$src1\n\t" | |
7326 "SDIVX $src1,$src2,$dst" %} | |
7327 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7328 ins_pipe(sdiv_reg_imm); | |
7329 %} | |
7330 | |
7331 //----------Div-By-10-Expansion------------------------------------------------ | |
7332 // Extract hi bits of a 32x32->64 bit multiply. | |
7333 // Expand rule only, not matched | |
7334 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7335 effect( DEF dst, USE src1, USE src2 ); | |
7336 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7337 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7338 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7339 ins_pipe(sdiv_reg_reg); | |
7340 %} | |
7341 | |
605 | 7342 // Magic constant, reciprocal of 10 |
0 | 7343 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7344 effect( DEF dst ); | |
7345 | |
7346 size(8); | |
7347 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7348 ins_encode( Set32(0x66666667, dst) ); | |
7349 ins_pipe(ialu_hi_lo_reg); | |
7350 %} | |
7351 | |
605 | 7352 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7353 instruct sra_31( iRegI dst, iRegI src ) %{ |
7354 effect( DEF dst, USE src ); | |
7355 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7356 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7357 ins_pipe(ialu_reg_reg); | |
7358 %} | |
7359 | |
7360 // Arithmetic Shift Right by 8-bit immediate | |
7361 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7362 effect( DEF dst, USE src ); | |
7363 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7364 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7365 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7366 ins_pipe(ialu_reg_imm); | |
7367 %} | |
7368 | |
7369 // Integer DIV with 10 | |
7370 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7371 match(Set dst (DivI src div)); | |
7372 ins_cost((6+6)*DEFAULT_COST); | |
7373 expand %{ | |
7374 iRegIsafe tmp1; // Killed temps; | |
7375 iRegIsafe tmp2; // Killed temps; | |
7376 iRegI tmp3; // Killed temps; | |
7377 iRegI tmp4; // Killed temps; | |
7378 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7379 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7380 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7381 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7382 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7383 %} | |
7384 %} | |
7385 | |
7386 // Register Long Division | |
7387 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7388 match(Set dst (DivL src1 src2)); | |
7389 ins_cost(DEFAULT_COST*71); | |
7390 size(4); | |
7391 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7392 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7393 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7394 ins_pipe(divL_reg_reg); | |
7395 %} | |
7396 | |
7397 // Register Long Division | |
7398 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7399 match(Set dst (DivL src1 src2)); | |
7400 ins_cost(DEFAULT_COST*71); | |
7401 size(4); | |
7402 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7403 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7404 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7405 ins_pipe(divL_reg_imm); | |
7406 %} | |
7407 | |
7408 // Integer Remainder | |
7409 // Register Remainder | |
7410 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7411 match(Set dst (ModI src1 src2)); | |
7412 effect( KILL ccr, KILL temp); | |
7413 | |
7414 format %{ "SREM $src1,$src2,$dst" %} | |
7415 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7416 ins_pipe(sdiv_reg_reg); | |
7417 %} | |
7418 | |
7419 // Immediate Remainder | |
7420 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7421 match(Set dst (ModI src1 src2)); | |
7422 effect( KILL ccr, KILL temp); | |
7423 | |
7424 format %{ "SREM $src1,$src2,$dst" %} | |
7425 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7426 ins_pipe(sdiv_reg_imm); | |
7427 %} | |
7428 | |
7429 // Register Long Remainder | |
7430 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7431 effect(DEF dst, USE src1, USE src2); | |
7432 size(4); | |
7433 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7434 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7435 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7436 ins_pipe(divL_reg_reg); | |
7437 %} | |
7438 | |
7439 // Register Long Division | |
7440 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7441 effect(DEF dst, USE src1, USE src2); | |
7442 size(4); | |
7443 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7444 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7445 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7446 ins_pipe(divL_reg_imm); | |
7447 %} | |
7448 | |
7449 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7450 effect(DEF dst, USE src1, USE src2); | |
7451 size(4); | |
7452 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7453 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7454 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7455 ins_pipe(mulL_reg_reg); | |
7456 %} | |
7457 | |
7458 // Immediate Multiplication | |
7459 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7460 effect(DEF dst, USE src1, USE src2); | |
7461 size(4); | |
7462 format %{ "MULX $src1,$src2,$dst" %} | |
7463 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7464 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7465 ins_pipe(mulL_reg_imm); | |
7466 %} | |
7467 | |
7468 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7469 effect(DEF dst, USE src1, USE src2); | |
7470 size(4); | |
7471 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7472 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7473 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7474 ins_pipe(ialu_reg_reg); | |
7475 %} | |
7476 | |
7477 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7478 effect(DEF dst, USE src1, USE src2); | |
7479 size(4); | |
7480 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7481 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7482 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7483 ins_pipe(ialu_reg_reg); | |
7484 %} | |
7485 | |
7486 // Register Long Remainder | |
7487 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7488 match(Set dst (ModL src1 src2)); | |
7489 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7490 expand %{ | |
7491 iRegL tmp1; | |
7492 iRegL tmp2; | |
7493 divL_reg_reg_1(tmp1, src1, src2); | |
7494 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7495 subL_reg_reg_1(dst, src1, tmp2); | |
7496 %} | |
7497 %} | |
7498 | |
7499 // Register Long Remainder | |
7500 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7501 match(Set dst (ModL src1 src2)); | |
7502 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7503 expand %{ | |
7504 iRegL tmp1; | |
7505 iRegL tmp2; | |
7506 divL_reg_imm13_1(tmp1, src1, src2); | |
7507 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7508 subL_reg_reg_2 (dst, src1, tmp2); | |
7509 %} | |
7510 %} | |
7511 | |
7512 // Integer Shift Instructions | |
7513 // Register Shift Left | |
7514 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7515 match(Set dst (LShiftI src1 src2)); | |
7516 | |
7517 size(4); | |
7518 format %{ "SLL $src1,$src2,$dst" %} | |
7519 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7520 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7521 ins_pipe(ialu_reg_reg); | |
7522 %} | |
7523 | |
7524 // Register Shift Left Immediate | |
7525 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7526 match(Set dst (LShiftI src1 src2)); | |
7527 | |
7528 size(4); | |
7529 format %{ "SLL $src1,$src2,$dst" %} | |
7530 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7531 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7532 ins_pipe(ialu_reg_imm); | |
7533 %} | |
7534 | |
7535 // Register Shift Left | |
7536 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7537 match(Set dst (LShiftL src1 src2)); | |
7538 | |
7539 size(4); | |
7540 format %{ "SLLX $src1,$src2,$dst" %} | |
7541 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7542 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7543 ins_pipe(ialu_reg_reg); | |
7544 %} | |
7545 | |
7546 // Register Shift Left Immediate | |
7547 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7548 match(Set dst (LShiftL src1 src2)); | |
7549 | |
7550 size(4); | |
7551 format %{ "SLLX $src1,$src2,$dst" %} | |
7552 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7553 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7554 ins_pipe(ialu_reg_imm); | |
7555 %} | |
7556 | |
7557 // Register Arithmetic Shift Right | |
7558 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7559 match(Set dst (RShiftI src1 src2)); | |
7560 size(4); | |
7561 format %{ "SRA $src1,$src2,$dst" %} | |
7562 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7563 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7564 ins_pipe(ialu_reg_reg); | |
7565 %} | |
7566 | |
7567 // Register Arithmetic Shift Right Immediate | |
7568 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7569 match(Set dst (RShiftI src1 src2)); | |
7570 | |
7571 size(4); | |
7572 format %{ "SRA $src1,$src2,$dst" %} | |
7573 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7574 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7575 ins_pipe(ialu_reg_imm); | |
7576 %} | |
7577 | |
7578 // Register Shift Right Arithmatic Long | |
7579 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7580 match(Set dst (RShiftL src1 src2)); | |
7581 | |
7582 size(4); | |
7583 format %{ "SRAX $src1,$src2,$dst" %} | |
7584 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7585 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7586 ins_pipe(ialu_reg_reg); | |
7587 %} | |
7588 | |
7589 // Register Shift Left Immediate | |
7590 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7591 match(Set dst (RShiftL src1 src2)); | |
7592 | |
7593 size(4); | |
7594 format %{ "SRAX $src1,$src2,$dst" %} | |
7595 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7596 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7597 ins_pipe(ialu_reg_imm); | |
7598 %} | |
7599 | |
7600 // Register Shift Right | |
7601 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7602 match(Set dst (URShiftI src1 src2)); | |
7603 | |
7604 size(4); | |
7605 format %{ "SRL $src1,$src2,$dst" %} | |
7606 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7607 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7608 ins_pipe(ialu_reg_reg); | |
7609 %} | |
7610 | |
7611 // Register Shift Right Immediate | |
7612 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7613 match(Set dst (URShiftI src1 src2)); | |
7614 | |
7615 size(4); | |
7616 format %{ "SRL $src1,$src2,$dst" %} | |
7617 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7618 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7619 ins_pipe(ialu_reg_imm); | |
7620 %} | |
7621 | |
7622 // Register Shift Right | |
7623 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7624 match(Set dst (URShiftL src1 src2)); | |
7625 | |
7626 size(4); | |
7627 format %{ "SRLX $src1,$src2,$dst" %} | |
7628 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7629 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7630 ins_pipe(ialu_reg_reg); | |
7631 %} | |
7632 | |
7633 // Register Shift Right Immediate | |
7634 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7635 match(Set dst (URShiftL src1 src2)); | |
7636 | |
7637 size(4); | |
7638 format %{ "SRLX $src1,$src2,$dst" %} | |
7639 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7640 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7641 ins_pipe(ialu_reg_imm); | |
7642 %} | |
7643 | |
7644 // Register Shift Right Immediate with a CastP2X | |
7645 #ifdef _LP64 | |
7646 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7647 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7648 size(4); | |
7649 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7650 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7651 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7652 ins_pipe(ialu_reg_imm); | |
7653 %} | |
7654 #else | |
7655 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7656 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7657 size(4); | |
7658 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7659 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7660 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7661 ins_pipe(ialu_reg_imm); | |
7662 %} | |
7663 #endif | |
7664 | |
7665 | |
7666 //----------Floating Point Arithmetic Instructions----------------------------- | |
7667 | |
7668 // Add float single precision | |
7669 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7670 match(Set dst (AddF src1 src2)); | |
7671 | |
7672 size(4); | |
7673 format %{ "FADDS $src1,$src2,$dst" %} | |
7674 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7675 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7676 ins_pipe(faddF_reg_reg); | |
7677 %} | |
7678 | |
7679 // Add float double precision | |
7680 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7681 match(Set dst (AddD src1 src2)); | |
7682 | |
7683 size(4); | |
7684 format %{ "FADDD $src1,$src2,$dst" %} | |
7685 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7686 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7687 ins_pipe(faddD_reg_reg); | |
7688 %} | |
7689 | |
7690 // Sub float single precision | |
7691 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7692 match(Set dst (SubF src1 src2)); | |
7693 | |
7694 size(4); | |
7695 format %{ "FSUBS $src1,$src2,$dst" %} | |
7696 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7697 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7698 ins_pipe(faddF_reg_reg); | |
7699 %} | |
7700 | |
7701 // Sub float double precision | |
7702 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7703 match(Set dst (SubD src1 src2)); | |
7704 | |
7705 size(4); | |
7706 format %{ "FSUBD $src1,$src2,$dst" %} | |
7707 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7708 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7709 ins_pipe(faddD_reg_reg); | |
7710 %} | |
7711 | |
7712 // Mul float single precision | |
7713 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7714 match(Set dst (MulF src1 src2)); | |
7715 | |
7716 size(4); | |
7717 format %{ "FMULS $src1,$src2,$dst" %} | |
7718 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7719 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7720 ins_pipe(fmulF_reg_reg); | |
7721 %} | |
7722 | |
7723 // Mul float double precision | |
7724 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7725 match(Set dst (MulD src1 src2)); | |
7726 | |
7727 size(4); | |
7728 format %{ "FMULD $src1,$src2,$dst" %} | |
7729 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7730 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7731 ins_pipe(fmulD_reg_reg); | |
7732 %} | |
7733 | |
7734 // Div float single precision | |
7735 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7736 match(Set dst (DivF src1 src2)); | |
7737 | |
7738 size(4); | |
7739 format %{ "FDIVS $src1,$src2,$dst" %} | |
7740 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7741 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7742 ins_pipe(fdivF_reg_reg); | |
7743 %} | |
7744 | |
7745 // Div float double precision | |
7746 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7747 match(Set dst (DivD src1 src2)); | |
7748 | |
7749 size(4); | |
7750 format %{ "FDIVD $src1,$src2,$dst" %} | |
7751 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7752 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7753 ins_pipe(fdivD_reg_reg); | |
7754 %} | |
7755 | |
7756 // Absolute float double precision | |
7757 instruct absD_reg(regD dst, regD src) %{ | |
7758 match(Set dst (AbsD src)); | |
7759 | |
7760 format %{ "FABSd $src,$dst" %} | |
7761 ins_encode(fabsd(dst, src)); | |
7762 ins_pipe(faddD_reg); | |
7763 %} | |
7764 | |
7765 // Absolute float single precision | |
7766 instruct absF_reg(regF dst, regF src) %{ | |
7767 match(Set dst (AbsF src)); | |
7768 | |
7769 format %{ "FABSs $src,$dst" %} | |
7770 ins_encode(fabss(dst, src)); | |
7771 ins_pipe(faddF_reg); | |
7772 %} | |
7773 | |
7774 instruct negF_reg(regF dst, regF src) %{ | |
7775 match(Set dst (NegF src)); | |
7776 | |
7777 size(4); | |
7778 format %{ "FNEGs $src,$dst" %} | |
7779 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7780 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7781 ins_pipe(faddF_reg); | |
7782 %} | |
7783 | |
7784 instruct negD_reg(regD dst, regD src) %{ | |
7785 match(Set dst (NegD src)); | |
7786 | |
7787 format %{ "FNEGd $src,$dst" %} | |
7788 ins_encode(fnegd(dst, src)); | |
7789 ins_pipe(faddD_reg); | |
7790 %} | |
7791 | |
7792 // Sqrt float double precision | |
7793 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7794 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7795 | |
7796 size(4); | |
7797 format %{ "FSQRTS $src,$dst" %} | |
7798 ins_encode(fsqrts(dst, src)); | |
7799 ins_pipe(fdivF_reg_reg); | |
7800 %} | |
7801 | |
7802 // Sqrt float double precision | |
7803 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7804 match(Set dst (SqrtD src)); | |
7805 | |
7806 size(4); | |
7807 format %{ "FSQRTD $src,$dst" %} | |
7808 ins_encode(fsqrtd(dst, src)); | |
7809 ins_pipe(fdivD_reg_reg); | |
7810 %} | |
7811 | |
7812 //----------Logical Instructions----------------------------------------------- | |
7813 // And Instructions | |
7814 // Register And | |
7815 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7816 match(Set dst (AndI src1 src2)); | |
7817 | |
7818 size(4); | |
7819 format %{ "AND $src1,$src2,$dst" %} | |
7820 opcode(Assembler::and_op3, Assembler::arith_op); | |
7821 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7822 ins_pipe(ialu_reg_reg); | |
7823 %} | |
7824 | |
7825 // Immediate And | |
7826 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7827 match(Set dst (AndI src1 src2)); | |
7828 | |
7829 size(4); | |
7830 format %{ "AND $src1,$src2,$dst" %} | |
7831 opcode(Assembler::and_op3, Assembler::arith_op); | |
7832 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7833 ins_pipe(ialu_reg_imm); | |
7834 %} | |
7835 | |
7836 // Register And Long | |
7837 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7838 match(Set dst (AndL src1 src2)); | |
7839 | |
7840 ins_cost(DEFAULT_COST); | |
7841 size(4); | |
7842 format %{ "AND $src1,$src2,$dst\t! long" %} | |
7843 opcode(Assembler::and_op3, Assembler::arith_op); | |
7844 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7845 ins_pipe(ialu_reg_reg); | |
7846 %} | |
7847 | |
7848 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7849 match(Set dst (AndL src1 con)); | |
7850 | |
7851 ins_cost(DEFAULT_COST); | |
7852 size(4); | |
7853 format %{ "AND $src1,$con,$dst\t! long" %} | |
7854 opcode(Assembler::and_op3, Assembler::arith_op); | |
7855 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7856 ins_pipe(ialu_reg_imm); | |
7857 %} | |
7858 | |
7859 // Or Instructions | |
7860 // Register Or | |
7861 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7862 match(Set dst (OrI src1 src2)); | |
7863 | |
7864 size(4); | |
7865 format %{ "OR $src1,$src2,$dst" %} | |
7866 opcode(Assembler::or_op3, Assembler::arith_op); | |
7867 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7868 ins_pipe(ialu_reg_reg); | |
7869 %} | |
7870 | |
7871 // Immediate Or | |
7872 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7873 match(Set dst (OrI src1 src2)); | |
7874 | |
7875 size(4); | |
7876 format %{ "OR $src1,$src2,$dst" %} | |
7877 opcode(Assembler::or_op3, Assembler::arith_op); | |
7878 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7879 ins_pipe(ialu_reg_imm); | |
7880 %} | |
7881 | |
7882 // Register Or Long | |
7883 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7884 match(Set dst (OrL src1 src2)); | |
7885 | |
7886 ins_cost(DEFAULT_COST); | |
7887 size(4); | |
7888 format %{ "OR $src1,$src2,$dst\t! long" %} | |
7889 opcode(Assembler::or_op3, Assembler::arith_op); | |
7890 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7891 ins_pipe(ialu_reg_reg); | |
7892 %} | |
7893 | |
7894 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7895 match(Set dst (OrL src1 con)); | |
7896 ins_cost(DEFAULT_COST*2); | |
7897 | |
7898 ins_cost(DEFAULT_COST); | |
7899 size(4); | |
7900 format %{ "OR $src1,$con,$dst\t! long" %} | |
7901 opcode(Assembler::or_op3, Assembler::arith_op); | |
7902 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7903 ins_pipe(ialu_reg_imm); | |
7904 %} | |
7905 | |
420
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7906 #ifndef _LP64 |
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7907 |
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7908 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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7909 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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7910 match(Set dst (OrI src1 (CastP2X src2))); |
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7911 |
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7912 size(4); |
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7913 format %{ "OR $src1,$src2,$dst" %} |
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7914 opcode(Assembler::or_op3, Assembler::arith_op); |
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7915 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7916 ins_pipe(ialu_reg_reg); |
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7917 %} |
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7918 |
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7919 #else |
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7920 |
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7921 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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7922 match(Set dst (OrL src1 (CastP2X src2))); |
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7923 |
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7924 ins_cost(DEFAULT_COST); |
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7925 size(4); |
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7926 format %{ "OR $src1,$src2,$dst\t! long" %} |
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7927 opcode(Assembler::or_op3, Assembler::arith_op); |
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7928 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7929 ins_pipe(ialu_reg_reg); |
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7930 %} |
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7931 |
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7932 #endif |
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7933 |
0 | 7934 // Xor Instructions |
7935 // Register Xor | |
7936 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7937 match(Set dst (XorI src1 src2)); | |
7938 | |
7939 size(4); | |
7940 format %{ "XOR $src1,$src2,$dst" %} | |
7941 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7942 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7943 ins_pipe(ialu_reg_reg); | |
7944 %} | |
7945 | |
7946 // Immediate Xor | |
7947 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7948 match(Set dst (XorI src1 src2)); | |
7949 | |
7950 size(4); | |
7951 format %{ "XOR $src1,$src2,$dst" %} | |
7952 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7953 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7954 ins_pipe(ialu_reg_imm); | |
7955 %} | |
7956 | |
7957 // Register Xor Long | |
7958 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7959 match(Set dst (XorL src1 src2)); | |
7960 | |
7961 ins_cost(DEFAULT_COST); | |
7962 size(4); | |
7963 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
7964 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7965 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7966 ins_pipe(ialu_reg_reg); | |
7967 %} | |
7968 | |
7969 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7970 match(Set dst (XorL src1 con)); | |
7971 | |
7972 ins_cost(DEFAULT_COST); | |
7973 size(4); | |
7974 format %{ "XOR $src1,$con,$dst\t! long" %} | |
7975 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7976 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7977 ins_pipe(ialu_reg_imm); | |
7978 %} | |
7979 | |
7980 //----------Convert to Boolean------------------------------------------------- | |
7981 // Nice hack for 32-bit tests but doesn't work for | |
7982 // 64-bit pointers. | |
7983 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
7984 match(Set dst (Conv2B src)); | |
7985 effect( KILL ccr ); | |
7986 ins_cost(DEFAULT_COST*2); | |
7987 format %{ "CMP R_G0,$src\n\t" | |
7988 "ADDX R_G0,0,$dst" %} | |
7989 ins_encode( enc_to_bool( src, dst ) ); | |
7990 ins_pipe(ialu_reg_ialu); | |
7991 %} | |
7992 | |
7993 #ifndef _LP64 | |
7994 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
7995 match(Set dst (Conv2B src)); | |
7996 effect( KILL ccr ); | |
7997 ins_cost(DEFAULT_COST*2); | |
7998 format %{ "CMP R_G0,$src\n\t" | |
7999 "ADDX R_G0,0,$dst" %} | |
8000 ins_encode( enc_to_bool( src, dst ) ); | |
8001 ins_pipe(ialu_reg_ialu); | |
8002 %} | |
8003 #else | |
8004 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8005 match(Set dst (Conv2B src)); | |
8006 ins_cost(DEFAULT_COST*2); | |
8007 format %{ "MOV $src,$dst\n\t" | |
8008 "MOVRNZ $src,1,$dst" %} | |
8009 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8010 ins_pipe(ialu_clr_and_mover); | |
8011 %} | |
8012 #endif | |
8013 | |
8014 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
8015 match(Set dst (CmpLTMask p q)); | |
8016 effect( KILL ccr ); | |
8017 ins_cost(DEFAULT_COST*4); | |
8018 format %{ "CMP $p,$q\n\t" | |
8019 "MOV #0,$dst\n\t" | |
8020 "BLT,a .+8\n\t" | |
8021 "MOV #-1,$dst" %} | |
8022 ins_encode( enc_ltmask(p,q,dst) ); | |
8023 ins_pipe(ialu_reg_reg_ialu); | |
8024 %} | |
8025 | |
8026 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8027 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8028 effect(KILL ccr, TEMP tmp); | |
8029 ins_cost(DEFAULT_COST*3); | |
8030 | |
8031 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8032 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
8033 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
8034 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
8035 ins_pipe( cadd_cmpltmask ); | |
8036 %} | |
8037 | |
8038 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8039 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
8040 effect( KILL ccr, TEMP tmp); | |
8041 ins_cost(DEFAULT_COST*3); | |
8042 | |
8043 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8044 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
8045 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
8046 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
8047 ins_pipe( cadd_cmpltmask ); | |
8048 %} | |
8049 | |
8050 //----------Arithmetic Conversion Instructions--------------------------------- | |
8051 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8052 | |
8053 instruct convD2F_reg(regF dst, regD src) %{ | |
8054 match(Set dst (ConvD2F src)); | |
8055 size(4); | |
8056 format %{ "FDTOS $src,$dst" %} | |
8057 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8058 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8059 ins_pipe(fcvtD2F); | |
8060 %} | |
8061 | |
8062 | |
8063 // Convert a double to an int in a float register. | |
8064 // If the double is a NAN, stuff a zero in instead. | |
8065 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8066 effect(DEF dst, USE src, KILL fcc0); | |
8067 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8068 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8069 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8070 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8071 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8072 "skip:" %} | |
8073 ins_encode(form_d2i_helper(src,dst)); | |
8074 ins_pipe(fcvtD2I); | |
8075 %} | |
8076 | |
8077 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
8078 match(Set dst (ConvD2I src)); | |
8079 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8080 expand %{ | |
8081 regF tmp; | |
8082 convD2I_helper(tmp, src); | |
8083 regF_to_stkI(dst, tmp); | |
8084 %} | |
8085 %} | |
8086 | |
8087 // Convert a double to a long in a double register. | |
8088 // If the double is a NAN, stuff a zero in instead. | |
8089 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8090 effect(DEF dst, USE src, KILL fcc0); | |
8091 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8092 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8093 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8094 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8095 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8096 "skip:" %} | |
8097 ins_encode(form_d2l_helper(src,dst)); | |
8098 ins_pipe(fcvtD2L); | |
8099 %} | |
8100 | |
8101 | |
8102 // Double to Long conversion | |
8103 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
8104 match(Set dst (ConvD2L src)); | |
8105 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8106 expand %{ | |
8107 regD tmp; | |
8108 convD2L_helper(tmp, src); | |
8109 regD_to_stkL(dst, tmp); | |
8110 %} | |
8111 %} | |
8112 | |
8113 | |
8114 instruct convF2D_reg(regD dst, regF src) %{ | |
8115 match(Set dst (ConvF2D src)); | |
8116 format %{ "FSTOD $src,$dst" %} | |
8117 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8118 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8119 ins_pipe(fcvtF2D); | |
8120 %} | |
8121 | |
8122 | |
8123 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8124 effect(DEF dst, USE src, KILL fcc0); | |
8125 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8126 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8127 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8128 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8129 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8130 "skip:" %} | |
8131 ins_encode(form_f2i_helper(src,dst)); | |
8132 ins_pipe(fcvtF2I); | |
8133 %} | |
8134 | |
8135 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
8136 match(Set dst (ConvF2I src)); | |
8137 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8138 expand %{ | |
8139 regF tmp; | |
8140 convF2I_helper(tmp, src); | |
8141 regF_to_stkI(dst, tmp); | |
8142 %} | |
8143 %} | |
8144 | |
8145 | |
8146 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8147 effect(DEF dst, USE src, KILL fcc0); | |
8148 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8149 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8150 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8151 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8152 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8153 "skip:" %} | |
8154 ins_encode(form_f2l_helper(src,dst)); | |
8155 ins_pipe(fcvtF2L); | |
8156 %} | |
8157 | |
8158 // Float to Long conversion | |
8159 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
8160 match(Set dst (ConvF2L src)); | |
8161 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8162 expand %{ | |
8163 regD tmp; | |
8164 convF2L_helper(tmp, src); | |
8165 regD_to_stkL(dst, tmp); | |
8166 %} | |
8167 %} | |
8168 | |
8169 | |
8170 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8171 effect(USE tmp, DEF dst); | |
8172 format %{ "FITOD $tmp,$dst" %} | |
8173 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8174 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8175 ins_pipe(fcvtI2D); | |
8176 %} | |
8177 | |
8178 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
8179 match(Set dst (ConvI2D src)); | |
8180 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8181 expand %{ | |
8182 regF tmp; | |
8183 stkI_to_regF( tmp, src); | |
8184 convI2D_helper( dst, tmp); | |
8185 %} | |
8186 %} | |
8187 | |
8188 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
8189 match(Set dst (ConvI2D (LoadI mem))); | |
8190 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8191 size(8); | |
8192 format %{ "LDF $mem,$dst\n\t" | |
8193 "FITOD $dst,$dst" %} | |
8194 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
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8195 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8196 ins_pipe(floadF_mem); |
8197 %} | |
8198 | |
8199 | |
8200 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8201 effect(DEF dst, USE tmp); | |
8202 format %{ "FITOS $tmp,$dst" %} | |
8203 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8204 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8205 ins_pipe(fcvtI2F); | |
8206 %} | |
8207 | |
8208 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
8209 match(Set dst (ConvI2F src)); | |
8210 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8211 expand %{ | |
8212 regF tmp; | |
8213 stkI_to_regF(tmp,src); | |
8214 convI2F_helper(dst, tmp); | |
8215 %} | |
8216 %} | |
8217 | |
8218 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8219 match(Set dst (ConvI2F (LoadI mem))); | |
8220 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8221 size(8); | |
8222 format %{ "LDF $mem,$dst\n\t" | |
8223 "FITOS $dst,$dst" %} | |
8224 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
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8225 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8226 ins_pipe(floadF_mem); |
8227 %} | |
8228 | |
8229 | |
8230 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8231 match(Set dst (ConvI2L src)); | |
8232 size(4); | |
8233 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8234 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8235 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8236 ins_pipe(ialu_reg_reg); | |
8237 %} | |
8238 | |
8239 // Zero-extend convert int to long | |
8240 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8241 match(Set dst (AndL (ConvI2L src) mask) ); | |
8242 size(4); | |
8243 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8244 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8245 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8246 ins_pipe(ialu_reg_reg); | |
8247 %} | |
8248 | |
8249 // Zero-extend long | |
8250 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8251 match(Set dst (AndL src mask) ); | |
8252 size(4); | |
8253 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8254 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8255 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8256 ins_pipe(ialu_reg_reg); | |
8257 %} | |
8258 | |
8259 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
8260 match(Set dst (MoveF2I src)); | |
8261 effect(DEF dst, USE src); | |
8262 ins_cost(MEMORY_REF_COST); | |
8263 | |
8264 size(4); | |
8265 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8266 opcode(Assembler::lduw_op3); | |
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8267 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8268 ins_pipe(iload_mem); |
8269 %} | |
8270 | |
8271 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8272 match(Set dst (MoveI2F src)); | |
8273 effect(DEF dst, USE src); | |
8274 ins_cost(MEMORY_REF_COST); | |
8275 | |
8276 size(4); | |
8277 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8278 opcode(Assembler::ldf_op3); | |
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8279 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8280 ins_pipe(floadF_stk); |
8281 %} | |
8282 | |
8283 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8284 match(Set dst (MoveD2L src)); | |
8285 effect(DEF dst, USE src); | |
8286 ins_cost(MEMORY_REF_COST); | |
8287 | |
8288 size(4); | |
8289 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8290 opcode(Assembler::ldx_op3); | |
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8291 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8292 ins_pipe(iload_mem); |
8293 %} | |
8294 | |
8295 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8296 match(Set dst (MoveL2D src)); | |
8297 effect(DEF dst, USE src); | |
8298 ins_cost(MEMORY_REF_COST); | |
8299 | |
8300 size(4); | |
8301 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8302 opcode(Assembler::lddf_op3); | |
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8303 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8304 ins_pipe(floadD_stk); |
8305 %} | |
8306 | |
8307 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8308 match(Set dst (MoveF2I src)); | |
8309 effect(DEF dst, USE src); | |
8310 ins_cost(MEMORY_REF_COST); | |
8311 | |
8312 size(4); | |
8313 format %{ "STF $src,$dst\t!MoveF2I" %} | |
8314 opcode(Assembler::stf_op3); | |
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8315 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8316 ins_pipe(fstoreF_stk_reg); |
8317 %} | |
8318 | |
8319 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8320 match(Set dst (MoveI2F src)); | |
8321 effect(DEF dst, USE src); | |
8322 ins_cost(MEMORY_REF_COST); | |
8323 | |
8324 size(4); | |
8325 format %{ "STW $src,$dst\t!MoveI2F" %} | |
8326 opcode(Assembler::stw_op3); | |
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8327 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8328 ins_pipe(istore_mem_reg); |
8329 %} | |
8330 | |
8331 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8332 match(Set dst (MoveD2L src)); | |
8333 effect(DEF dst, USE src); | |
8334 ins_cost(MEMORY_REF_COST); | |
8335 | |
8336 size(4); | |
8337 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
8338 opcode(Assembler::stdf_op3); | |
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8339 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8340 ins_pipe(fstoreD_stk_reg); |
8341 %} | |
8342 | |
8343 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8344 match(Set dst (MoveL2D src)); | |
8345 effect(DEF dst, USE src); | |
8346 ins_cost(MEMORY_REF_COST); | |
8347 | |
8348 size(4); | |
8349 format %{ "STX $src,$dst\t!MoveL2D" %} | |
8350 opcode(Assembler::stx_op3); | |
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8351 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8352 ins_pipe(istore_mem_reg); |
8353 %} | |
8354 | |
8355 | |
8356 //----------- | |
8357 // Long to Double conversion using V8 opcodes. | |
8358 // Still useful because cheetah traps and becomes | |
8359 // amazingly slow for some common numbers. | |
8360 | |
8361 // Magic constant, 0x43300000 | |
8362 instruct loadConI_x43300000(iRegI dst) %{ | |
8363 effect(DEF dst); | |
8364 size(4); | |
8365 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8366 ins_encode(SetHi22(0x43300000, dst)); | |
8367 ins_pipe(ialu_none); | |
8368 %} | |
8369 | |
8370 // Magic constant, 0x41f00000 | |
8371 instruct loadConI_x41f00000(iRegI dst) %{ | |
8372 effect(DEF dst); | |
8373 size(4); | |
8374 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8375 ins_encode(SetHi22(0x41f00000, dst)); | |
8376 ins_pipe(ialu_none); | |
8377 %} | |
8378 | |
8379 // Construct a double from two float halves | |
8380 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8381 effect(DEF dst, USE src1, USE src2); | |
8382 size(8); | |
8383 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8384 "FMOVS $src2.lo,$dst.lo" %} | |
8385 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8386 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8387 ins_pipe(faddD_reg_reg); | |
8388 %} | |
8389 | |
8390 // Convert integer in high half of a double register (in the lower half of | |
8391 // the double register file) to double | |
8392 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8393 effect(DEF dst, USE src); | |
8394 size(4); | |
8395 format %{ "FITOD $src,$dst" %} | |
8396 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8397 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8398 ins_pipe(fcvtLHi2D); | |
8399 %} | |
8400 | |
8401 // Add float double precision | |
8402 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8403 effect(DEF dst, USE src1, USE src2); | |
8404 size(4); | |
8405 format %{ "FADDD $src1,$src2,$dst" %} | |
8406 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8407 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8408 ins_pipe(faddD_reg_reg); | |
8409 %} | |
8410 | |
8411 // Sub float double precision | |
8412 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8413 effect(DEF dst, USE src1, USE src2); | |
8414 size(4); | |
8415 format %{ "FSUBD $src1,$src2,$dst" %} | |
8416 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8417 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8418 ins_pipe(faddD_reg_reg); | |
8419 %} | |
8420 | |
8421 // Mul float double precision | |
8422 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8423 effect(DEF dst, USE src1, USE src2); | |
8424 size(4); | |
8425 format %{ "FMULD $src1,$src2,$dst" %} | |
8426 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8427 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8428 ins_pipe(fmulD_reg_reg); | |
8429 %} | |
8430 | |
8431 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8432 match(Set dst (ConvL2D src)); | |
8433 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8434 | |
8435 expand %{ | |
8436 regD_low tmpsrc; | |
8437 iRegI ix43300000; | |
8438 iRegI ix41f00000; | |
8439 stackSlotL lx43300000; | |
8440 stackSlotL lx41f00000; | |
8441 regD_low dx43300000; | |
8442 regD dx41f00000; | |
8443 regD tmp1; | |
8444 regD_low tmp2; | |
8445 regD tmp3; | |
8446 regD tmp4; | |
8447 | |
8448 stkL_to_regD(tmpsrc, src); | |
8449 | |
8450 loadConI_x43300000(ix43300000); | |
8451 loadConI_x41f00000(ix41f00000); | |
8452 regI_to_stkLHi(lx43300000, ix43300000); | |
8453 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8454 stkL_to_regD(dx43300000, lx43300000); | |
8455 stkL_to_regD(dx41f00000, lx41f00000); | |
8456 | |
8457 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8458 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8459 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8460 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8461 addD_regD_regD(dst, tmp3, tmp4); | |
8462 %} | |
8463 %} | |
8464 | |
8465 // Long to Double conversion using fast fxtof | |
8466 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8467 effect(DEF dst, USE tmp); | |
8468 size(4); | |
8469 format %{ "FXTOD $tmp,$dst" %} | |
8470 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8471 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8472 ins_pipe(fcvtL2D); | |
8473 %} | |
8474 | |
8475 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
8476 predicate(VM_Version::has_fast_fxtof()); | |
8477 match(Set dst (ConvL2D src)); | |
8478 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8479 expand %{ | |
8480 regD tmp; | |
8481 stkL_to_regD(tmp, src); | |
8482 convL2D_helper(dst, tmp); | |
8483 %} | |
8484 %} | |
8485 | |
8486 //----------- | |
8487 // Long to Float conversion using V8 opcodes. | |
8488 // Still useful because cheetah traps and becomes | |
8489 // amazingly slow for some common numbers. | |
8490 | |
8491 // Long to Float conversion using fast fxtof | |
8492 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8493 effect(DEF dst, USE tmp); | |
8494 size(4); | |
8495 format %{ "FXTOS $tmp,$dst" %} | |
8496 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8497 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8498 ins_pipe(fcvtL2F); | |
8499 %} | |
8500 | |
8501 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
8502 match(Set dst (ConvL2F src)); | |
8503 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8504 expand %{ | |
8505 regD tmp; | |
8506 stkL_to_regD(tmp, src); | |
8507 convL2F_helper(dst, tmp); | |
8508 %} | |
8509 %} | |
8510 //----------- | |
8511 | |
8512 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8513 match(Set dst (ConvL2I src)); | |
8514 #ifndef _LP64 | |
8515 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8516 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8517 ins_pipe(ialu_move_reg_I_to_L); | |
8518 #else | |
8519 size(4); | |
8520 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8521 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8522 ins_pipe(ialu_reg); | |
8523 #endif | |
8524 %} | |
8525 | |
8526 // Register Shift Right Immediate | |
8527 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8528 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8529 | |
8530 size(4); | |
8531 format %{ "SRAX $src,$cnt,$dst" %} | |
8532 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8533 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8534 ins_pipe(ialu_reg_imm); | |
8535 %} | |
8536 | |
8537 // Replicate scalar to packed byte values in Double register | |
8538 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
8539 effect(DEF dst, USE src); | |
8540 format %{ "SLLX $src,56,$dst\n\t" | |
8541 "SRLX $dst, 8,O7\n\t" | |
8542 "OR $dst,O7,$dst\n\t" | |
8543 "SRLX $dst,16,O7\n\t" | |
8544 "OR $dst,O7,$dst\n\t" | |
8545 "SRLX $dst,32,O7\n\t" | |
8546 "OR $dst,O7,$dst\t! replicate8B" %} | |
8547 ins_encode( enc_repl8b(src, dst)); | |
8548 ins_pipe(ialu_reg); | |
8549 %} | |
8550 | |
8551 // Replicate scalar to packed byte values in Double register | |
8552 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
8553 match(Set dst (Replicate8B src)); | |
8554 expand %{ | |
8555 iRegL tmp; | |
8556 Repl8B_reg_helper(tmp, src); | |
8557 regL_to_stkD(dst, tmp); | |
8558 %} | |
8559 %} | |
8560 | |
8561 // Replicate scalar constant to packed byte values in Double register | |
8562 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
8563 match(Set dst (Replicate8B src)); | |
8564 #ifdef _LP64 | |
8565 size(36); | |
8566 #else | |
8567 size(8); | |
8568 #endif | |
8569 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
8570 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
8571 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
8572 ins_pipe(loadConFD); | |
8573 %} | |
8574 | |
8575 // Replicate scalar to packed char values into stack slot | |
8576 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
8577 effect(DEF dst, USE src); | |
8578 format %{ "SLLX $src,48,$dst\n\t" | |
8579 "SRLX $dst,16,O7\n\t" | |
8580 "OR $dst,O7,$dst\n\t" | |
8581 "SRLX $dst,32,O7\n\t" | |
8582 "OR $dst,O7,$dst\t! replicate4C" %} | |
8583 ins_encode( enc_repl4s(src, dst) ); | |
8584 ins_pipe(ialu_reg); | |
8585 %} | |
8586 | |
8587 // Replicate scalar to packed char values into stack slot | |
8588 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
8589 match(Set dst (Replicate4C src)); | |
8590 expand %{ | |
8591 iRegL tmp; | |
8592 Repl4C_reg_helper(tmp, src); | |
8593 regL_to_stkD(dst, tmp); | |
8594 %} | |
8595 %} | |
8596 | |
8597 // Replicate scalar constant to packed char values in Double register | |
8598 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
8599 match(Set dst (Replicate4C src)); | |
8600 #ifdef _LP64 | |
8601 size(36); | |
8602 #else | |
8603 size(8); | |
8604 #endif | |
8605 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
8606 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8607 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8608 ins_pipe(loadConFD); | |
8609 %} | |
8610 | |
8611 // Replicate scalar to packed short values into stack slot | |
8612 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
8613 effect(DEF dst, USE src); | |
8614 format %{ "SLLX $src,48,$dst\n\t" | |
8615 "SRLX $dst,16,O7\n\t" | |
8616 "OR $dst,O7,$dst\n\t" | |
8617 "SRLX $dst,32,O7\n\t" | |
8618 "OR $dst,O7,$dst\t! replicate4S" %} | |
8619 ins_encode( enc_repl4s(src, dst) ); | |
8620 ins_pipe(ialu_reg); | |
8621 %} | |
8622 | |
8623 // Replicate scalar to packed short values into stack slot | |
8624 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
8625 match(Set dst (Replicate4S src)); | |
8626 expand %{ | |
8627 iRegL tmp; | |
8628 Repl4S_reg_helper(tmp, src); | |
8629 regL_to_stkD(dst, tmp); | |
8630 %} | |
8631 %} | |
8632 | |
8633 // Replicate scalar constant to packed short values in Double register | |
8634 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
8635 match(Set dst (Replicate4S src)); | |
8636 #ifdef _LP64 | |
8637 size(36); | |
8638 #else | |
8639 size(8); | |
8640 #endif | |
8641 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
8642 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8643 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8644 ins_pipe(loadConFD); | |
8645 %} | |
8646 | |
8647 // Replicate scalar to packed int values in Double register | |
8648 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
8649 effect(DEF dst, USE src); | |
8650 format %{ "SLLX $src,32,$dst\n\t" | |
8651 "SRLX $dst,32,O7\n\t" | |
8652 "OR $dst,O7,$dst\t! replicate2I" %} | |
8653 ins_encode( enc_repl2i(src, dst)); | |
8654 ins_pipe(ialu_reg); | |
8655 %} | |
8656 | |
8657 // Replicate scalar to packed int values in Double register | |
8658 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
8659 match(Set dst (Replicate2I src)); | |
8660 expand %{ | |
8661 iRegL tmp; | |
8662 Repl2I_reg_helper(tmp, src); | |
8663 regL_to_stkD(dst, tmp); | |
8664 %} | |
8665 %} | |
8666 | |
8667 // Replicate scalar zero constant to packed int values in Double register | |
8668 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
8669 match(Set dst (Replicate2I src)); | |
8670 #ifdef _LP64 | |
8671 size(36); | |
8672 #else | |
8673 size(8); | |
8674 #endif | |
8675 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
8676 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
8677 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
8678 ins_pipe(loadConFD); | |
8679 %} | |
8680 | |
8681 //----------Control Flow Instructions------------------------------------------ | |
8682 // Compare Instructions | |
8683 // Compare Integers | |
8684 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8685 match(Set icc (CmpI op1 op2)); | |
8686 effect( DEF icc, USE op1, USE op2 ); | |
8687 | |
8688 size(4); | |
8689 format %{ "CMP $op1,$op2" %} | |
8690 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8691 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8692 ins_pipe(ialu_cconly_reg_reg); | |
8693 %} | |
8694 | |
8695 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8696 match(Set icc (CmpU op1 op2)); | |
8697 | |
8698 size(4); | |
8699 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8700 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8701 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8702 ins_pipe(ialu_cconly_reg_reg); | |
8703 %} | |
8704 | |
8705 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8706 match(Set icc (CmpI op1 op2)); | |
8707 effect( DEF icc, USE op1 ); | |
8708 | |
8709 size(4); | |
8710 format %{ "CMP $op1,$op2" %} | |
8711 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8712 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8713 ins_pipe(ialu_cconly_reg_imm); | |
8714 %} | |
8715 | |
8716 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8717 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8718 | |
8719 size(4); | |
8720 format %{ "BTST $op2,$op1" %} | |
8721 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8722 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8723 ins_pipe(ialu_cconly_reg_reg_zero); | |
8724 %} | |
8725 | |
8726 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8727 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8728 | |
8729 size(4); | |
8730 format %{ "BTST $op2,$op1" %} | |
8731 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8732 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8733 ins_pipe(ialu_cconly_reg_imm_zero); | |
8734 %} | |
8735 | |
8736 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8737 match(Set xcc (CmpL op1 op2)); | |
8738 effect( DEF xcc, USE op1, USE op2 ); | |
8739 | |
8740 size(4); | |
8741 format %{ "CMP $op1,$op2\t\t! long" %} | |
8742 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8743 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8744 ins_pipe(ialu_cconly_reg_reg); | |
8745 %} | |
8746 | |
8747 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8748 match(Set xcc (CmpL op1 con)); | |
8749 effect( DEF xcc, USE op1, USE con ); | |
8750 | |
8751 size(4); | |
8752 format %{ "CMP $op1,$con\t\t! long" %} | |
8753 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8754 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8755 ins_pipe(ialu_cconly_reg_reg); | |
8756 %} | |
8757 | |
8758 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8759 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8760 effect( DEF xcc, USE op1, USE op2 ); | |
8761 | |
8762 size(4); | |
8763 format %{ "BTST $op1,$op2\t\t! long" %} | |
8764 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8765 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8766 ins_pipe(ialu_cconly_reg_reg); | |
8767 %} | |
8768 | |
8769 // useful for checking the alignment of a pointer: | |
8770 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8771 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8772 effect( DEF xcc, USE op1, USE con ); | |
8773 | |
8774 size(4); | |
8775 format %{ "BTST $op1,$con\t\t! long" %} | |
8776 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8777 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8778 ins_pipe(ialu_cconly_reg_reg); | |
8779 %} | |
8780 | |
8781 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8782 match(Set icc (CmpU op1 op2)); | |
8783 | |
8784 size(4); | |
8785 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8786 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8787 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8788 ins_pipe(ialu_cconly_reg_imm); | |
8789 %} | |
8790 | |
8791 // Compare Pointers | |
8792 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8793 match(Set pcc (CmpP op1 op2)); | |
8794 | |
8795 size(4); | |
8796 format %{ "CMP $op1,$op2\t! ptr" %} | |
8797 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8798 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8799 ins_pipe(ialu_cconly_reg_reg); | |
8800 %} | |
8801 | |
8802 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8803 match(Set pcc (CmpP op1 op2)); | |
8804 | |
8805 size(4); | |
8806 format %{ "CMP $op1,$op2\t! ptr" %} | |
8807 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8808 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8809 ins_pipe(ialu_cconly_reg_imm); | |
8810 %} | |
8811 | |
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8812 // Compare Narrow oops |
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8813 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8814 match(Set icc (CmpN op1 op2)); |
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8815 |
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8816 size(4); |
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8817 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8818 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8819 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8820 ins_pipe(ialu_cconly_reg_reg); |
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8821 %} |
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8822 |
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8823 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8824 match(Set icc (CmpN op1 op2)); |
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8825 |
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8826 size(4); |
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8827 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8828 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8829 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8830 ins_pipe(ialu_cconly_reg_imm); |
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8831 %} |
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8832 |
0 | 8833 //----------Max and Min-------------------------------------------------------- |
8834 // Min Instructions | |
8835 // Conditional move for min | |
8836 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8837 effect( USE_DEF op2, USE op1, USE icc ); | |
8838 | |
8839 size(4); | |
8840 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
8841 opcode(Assembler::less); | |
8842 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8843 ins_pipe(ialu_reg_flags); | |
8844 %} | |
8845 | |
8846 // Min Register with Register. | |
8847 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
8848 match(Set op2 (MinI op1 op2)); | |
8849 ins_cost(DEFAULT_COST*2); | |
8850 expand %{ | |
8851 flagsReg icc; | |
8852 compI_iReg(icc,op1,op2); | |
8853 cmovI_reg_lt(op2,op1,icc); | |
8854 %} | |
8855 %} | |
8856 | |
8857 // Max Instructions | |
8858 // Conditional move for max | |
8859 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8860 effect( USE_DEF op2, USE op1, USE icc ); | |
8861 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
8862 opcode(Assembler::greater); | |
8863 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8864 ins_pipe(ialu_reg_flags); | |
8865 %} | |
8866 | |
8867 // Max Register with Register | |
8868 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
8869 match(Set op2 (MaxI op1 op2)); | |
8870 ins_cost(DEFAULT_COST*2); | |
8871 expand %{ | |
8872 flagsReg icc; | |
8873 compI_iReg(icc,op1,op2); | |
8874 cmovI_reg_gt(op2,op1,icc); | |
8875 %} | |
8876 %} | |
8877 | |
8878 | |
8879 //----------Float Compares---------------------------------------------------- | |
8880 // Compare floating, generate condition code | |
8881 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
8882 match(Set fcc (CmpF src1 src2)); | |
8883 | |
8884 size(4); | |
8885 format %{ "FCMPs $fcc,$src1,$src2" %} | |
8886 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
8887 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
8888 ins_pipe(faddF_fcc_reg_reg_zero); | |
8889 %} | |
8890 | |
8891 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
8892 match(Set fcc (CmpD src1 src2)); | |
8893 | |
8894 size(4); | |
8895 format %{ "FCMPd $fcc,$src1,$src2" %} | |
8896 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
8897 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
8898 ins_pipe(faddD_fcc_reg_reg_zero); | |
8899 %} | |
8900 | |
8901 | |
8902 // Compare floating, generate -1,0,1 | |
8903 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
8904 match(Set dst (CmpF3 src1 src2)); | |
8905 effect(KILL fcc0); | |
8906 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8907 format %{ "fcmpl $dst,$src1,$src2" %} | |
8908 // Primary = float | |
8909 opcode( true ); | |
8910 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8911 ins_pipe( floating_cmp ); | |
8912 %} | |
8913 | |
8914 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
8915 match(Set dst (CmpD3 src1 src2)); | |
8916 effect(KILL fcc0); | |
8917 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8918 format %{ "dcmpl $dst,$src1,$src2" %} | |
8919 // Primary = double (not float) | |
8920 opcode( false ); | |
8921 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8922 ins_pipe( floating_cmp ); | |
8923 %} | |
8924 | |
8925 //----------Branches--------------------------------------------------------- | |
8926 // Jump | |
8927 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
8928 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
8929 match(Jump switch_val); | |
8930 | |
8931 ins_cost(350); | |
8932 | |
8933 format %{ "SETHI [hi(table_base)],O7\n\t" | |
8934 "ADD O7, lo(table_base), O7\n\t" | |
8935 "LD [O7+$switch_val], O7\n\t" | |
8936 "JUMP O7" | |
8937 %} | |
8938 ins_encode( jump_enc( switch_val, table) ); | |
8939 ins_pc_relative(1); | |
8940 ins_pipe(ialu_reg_reg); | |
8941 %} | |
8942 | |
8943 // Direct Branch. Use V8 version with longer range. | |
8944 instruct branch(label labl) %{ | |
8945 match(Goto); | |
8946 effect(USE labl); | |
8947 | |
8948 size(8); | |
8949 ins_cost(BRANCH_COST); | |
8950 format %{ "BA $labl" %} | |
8951 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
8952 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
8953 ins_encode( enc_ba( labl ) ); | |
8954 ins_pc_relative(1); | |
8955 ins_pipe(br); | |
8956 %} | |
8957 | |
8958 // Conditional Direct Branch | |
8959 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
8960 match(If cmp icc); | |
8961 effect(USE labl); | |
8962 | |
8963 size(8); | |
8964 ins_cost(BRANCH_COST); | |
8965 format %{ "BP$cmp $icc,$labl" %} | |
8966 // Prim = bits 24-22, Secnd = bits 31-30 | |
8967 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8968 ins_pc_relative(1); | |
8969 ins_pipe(br_cc); | |
8970 %} | |
8971 | |
8972 // Branch-on-register tests all 64 bits. We assume that values | |
8973 // in 64-bit registers always remains zero or sign extended | |
8974 // unless our code munges the high bits. Interrupts can chop | |
8975 // the high order bits to zero or sign at any time. | |
8976 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
8977 match(If cmp (CmpI op1 zero)); | |
8978 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8979 effect(USE labl); | |
8980 | |
8981 size(8); | |
8982 ins_cost(BRANCH_COST); | |
8983 format %{ "BR$cmp $op1,$labl" %} | |
8984 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8985 ins_pc_relative(1); | |
8986 ins_pipe(br_reg); | |
8987 %} | |
8988 | |
8989 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
8990 match(If cmp (CmpP op1 null)); | |
8991 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8992 effect(USE labl); | |
8993 | |
8994 size(8); | |
8995 ins_cost(BRANCH_COST); | |
8996 format %{ "BR$cmp $op1,$labl" %} | |
8997 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8998 ins_pc_relative(1); | |
8999 ins_pipe(br_reg); | |
9000 %} | |
9001 | |
9002 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9003 match(If cmp (CmpL op1 zero)); | |
9004 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9005 effect(USE labl); | |
9006 | |
9007 size(8); | |
9008 ins_cost(BRANCH_COST); | |
9009 format %{ "BR$cmp $op1,$labl" %} | |
9010 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9011 ins_pc_relative(1); | |
9012 ins_pipe(br_reg); | |
9013 %} | |
9014 | |
9015 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9016 match(If cmp icc); | |
9017 effect(USE labl); | |
9018 | |
9019 format %{ "BP$cmp $icc,$labl" %} | |
9020 // Prim = bits 24-22, Secnd = bits 31-30 | |
9021 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9022 ins_pc_relative(1); | |
9023 ins_pipe(br_cc); | |
9024 %} | |
9025 | |
9026 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9027 match(If cmp pcc); | |
9028 effect(USE labl); | |
9029 | |
9030 size(8); | |
9031 ins_cost(BRANCH_COST); | |
9032 format %{ "BP$cmp $pcc,$labl" %} | |
9033 // Prim = bits 24-22, Secnd = bits 31-30 | |
9034 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
9035 ins_pc_relative(1); | |
9036 ins_pipe(br_cc); | |
9037 %} | |
9038 | |
9039 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9040 match(If cmp fcc); | |
9041 effect(USE labl); | |
9042 | |
9043 size(8); | |
9044 ins_cost(BRANCH_COST); | |
9045 format %{ "FBP$cmp $fcc,$labl" %} | |
9046 // Prim = bits 24-22, Secnd = bits 31-30 | |
9047 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
9048 ins_pc_relative(1); | |
9049 ins_pipe(br_fcc); | |
9050 %} | |
9051 | |
9052 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9053 match(CountedLoopEnd cmp icc); | |
9054 effect(USE labl); | |
9055 | |
9056 size(8); | |
9057 ins_cost(BRANCH_COST); | |
9058 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9059 // Prim = bits 24-22, Secnd = bits 31-30 | |
9060 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9061 ins_pc_relative(1); | |
9062 ins_pipe(br_cc); | |
9063 %} | |
9064 | |
9065 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9066 match(CountedLoopEnd cmp icc); | |
9067 effect(USE labl); | |
9068 | |
9069 size(8); | |
9070 ins_cost(BRANCH_COST); | |
9071 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9072 // Prim = bits 24-22, Secnd = bits 31-30 | |
9073 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9074 ins_pc_relative(1); | |
9075 ins_pipe(br_cc); | |
9076 %} | |
9077 | |
9078 // ============================================================================ | |
9079 // Long Compare | |
9080 // | |
9081 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9082 // is tricky. The flavor of compare used depends on whether we are testing | |
9083 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9084 // The GE test is the negated LT test. The LE test can be had by commuting | |
9085 // the operands (yielding a GE test) and then negating; negate again for the | |
9086 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9087 // NE test is negated from that. | |
9088 | |
9089 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9090 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9091 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9092 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9093 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9094 // foo match ends up with the wrong leaf. One fix is to not match both | |
9095 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9096 // both forms beat the trinary form of long-compare and both are very useful | |
9097 // on Intel which has so few registers. | |
9098 | |
9099 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9100 match(If cmp xcc); | |
9101 effect(USE labl); | |
9102 | |
9103 size(8); | |
9104 ins_cost(BRANCH_COST); | |
9105 format %{ "BP$cmp $xcc,$labl" %} | |
9106 // Prim = bits 24-22, Secnd = bits 31-30 | |
9107 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
9108 ins_pc_relative(1); | |
9109 ins_pipe(br_cc); | |
9110 %} | |
9111 | |
9112 // Manifest a CmpL3 result in an integer register. Very painful. | |
9113 // This is the test to avoid. | |
9114 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9115 match(Set dst (CmpL3 src1 src2) ); | |
9116 effect( KILL ccr ); | |
9117 ins_cost(6*DEFAULT_COST); | |
9118 size(24); | |
9119 format %{ "CMP $src1,$src2\t\t! long\n" | |
9120 "\tBLT,a,pn done\n" | |
9121 "\tMOV -1,$dst\t! delay slot\n" | |
9122 "\tBGT,a,pn done\n" | |
9123 "\tMOV 1,$dst\t! delay slot\n" | |
9124 "\tCLR $dst\n" | |
9125 "done:" %} | |
9126 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9127 ins_pipe(cmpL_reg); | |
9128 %} | |
9129 | |
9130 // Conditional move | |
9131 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9132 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9133 ins_cost(150); | |
9134 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9135 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9136 ins_pipe(ialu_reg); | |
9137 %} | |
9138 | |
9139 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9140 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9141 ins_cost(140); | |
9142 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9143 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9144 ins_pipe(ialu_imm); | |
9145 %} | |
9146 | |
9147 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9148 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9149 ins_cost(150); | |
9150 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9151 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9152 ins_pipe(ialu_reg); | |
9153 %} | |
9154 | |
9155 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9156 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9157 ins_cost(140); | |
9158 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9159 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9160 ins_pipe(ialu_imm); | |
9161 %} | |
9162 | |
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9163 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9164 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9165 ins_cost(150); |
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9166 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9167 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9168 ins_pipe(ialu_reg); |
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9169 %} |
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9170 |
0 | 9171 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9172 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9173 ins_cost(150); | |
9174 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9175 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9176 ins_pipe(ialu_reg); | |
9177 %} | |
9178 | |
9179 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9180 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9181 ins_cost(140); | |
9182 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9183 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9184 ins_pipe(ialu_imm); | |
9185 %} | |
9186 | |
9187 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9188 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9189 ins_cost(150); | |
9190 opcode(0x101); | |
9191 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9192 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9193 ins_pipe(int_conditional_float_move); | |
9194 %} | |
9195 | |
9196 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9197 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9198 ins_cost(150); | |
9199 opcode(0x102); | |
9200 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9201 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9202 ins_pipe(int_conditional_float_move); | |
9203 %} | |
9204 | |
9205 // ============================================================================ | |
9206 // Safepoint Instruction | |
9207 instruct safePoint_poll(iRegP poll) %{ | |
9208 match(SafePoint poll); | |
9209 effect(USE poll); | |
9210 | |
9211 size(4); | |
9212 #ifdef _LP64 | |
9213 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9214 #else | |
9215 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9216 #endif | |
9217 ins_encode %{ | |
9218 __ relocate(relocInfo::poll_type); | |
9219 __ ld_ptr($poll$$Register, 0, G0); | |
9220 %} | |
9221 ins_pipe(loadPollP); | |
9222 %} | |
9223 | |
9224 // ============================================================================ | |
9225 // Call Instructions | |
9226 // Call Java Static Instruction | |
9227 instruct CallStaticJavaDirect( method meth ) %{ | |
9228 match(CallStaticJava); | |
1567 | 9229 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
0 | 9230 effect(USE meth); |
9231 | |
9232 size(8); | |
9233 ins_cost(CALL_COST); | |
9234 format %{ "CALL,static ; NOP ==> " %} | |
9235 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9236 ins_pc_relative(1); | |
9237 ins_pipe(simple_call); | |
9238 %} | |
9239 | |
1567 | 9240 // Call Java Static Instruction (method handle version) |
9241 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
9242 match(CallStaticJava); | |
9243 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
9244 effect(USE meth, KILL l7_mh_SP_save); | |
9245 | |
9246 size(8); | |
9247 ins_cost(CALL_COST); | |
9248 format %{ "CALL,static/MethodHandle" %} | |
9249 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
9250 ins_pc_relative(1); | |
9251 ins_pipe(simple_call); | |
9252 %} | |
9253 | |
0 | 9254 // Call Java Dynamic Instruction |
9255 instruct CallDynamicJavaDirect( method meth ) %{ | |
9256 match(CallDynamicJava); | |
9257 effect(USE meth); | |
9258 | |
9259 ins_cost(CALL_COST); | |
9260 format %{ "SET (empty),R_G5\n\t" | |
9261 "CALL,dynamic ; NOP ==> " %} | |
9262 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9263 ins_pc_relative(1); | |
9264 ins_pipe(call); | |
9265 %} | |
9266 | |
9267 // Call Runtime Instruction | |
9268 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9269 match(CallRuntime); | |
9270 effect(USE meth, KILL l7); | |
9271 ins_cost(CALL_COST); | |
9272 format %{ "CALL,runtime" %} | |
9273 ins_encode( Java_To_Runtime( meth ), | |
9274 call_epilog, adjust_long_from_native_call ); | |
9275 ins_pc_relative(1); | |
9276 ins_pipe(simple_call); | |
9277 %} | |
9278 | |
9279 // Call runtime without safepoint - same as CallRuntime | |
9280 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9281 match(CallLeaf); | |
9282 effect(USE meth, KILL l7); | |
9283 ins_cost(CALL_COST); | |
9284 format %{ "CALL,runtime leaf" %} | |
9285 ins_encode( Java_To_Runtime( meth ), | |
9286 call_epilog, | |
9287 adjust_long_from_native_call ); | |
9288 ins_pc_relative(1); | |
9289 ins_pipe(simple_call); | |
9290 %} | |
9291 | |
9292 // Call runtime without safepoint - same as CallLeaf | |
9293 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9294 match(CallLeafNoFP); | |
9295 effect(USE meth, KILL l7); | |
9296 ins_cost(CALL_COST); | |
9297 format %{ "CALL,runtime leaf nofp" %} | |
9298 ins_encode( Java_To_Runtime( meth ), | |
9299 call_epilog, | |
9300 adjust_long_from_native_call ); | |
9301 ins_pc_relative(1); | |
9302 ins_pipe(simple_call); | |
9303 %} | |
9304 | |
9305 // Tail Call; Jump from runtime stub to Java code. | |
9306 // Also known as an 'interprocedural jump'. | |
9307 // Target of jump will eventually return to caller. | |
9308 // TailJump below removes the return address. | |
9309 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9310 match(TailCall jump_target method_oop ); | |
9311 | |
9312 ins_cost(CALL_COST); | |
9313 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9314 ins_encode(form_jmpl(jump_target)); | |
9315 ins_pipe(tail_call); | |
9316 %} | |
9317 | |
9318 | |
9319 // Return Instruction | |
9320 instruct Ret() %{ | |
9321 match(Return); | |
9322 | |
9323 // The epilogue node did the ret already. | |
9324 size(0); | |
9325 format %{ "! return" %} | |
9326 ins_encode(); | |
9327 ins_pipe(empty); | |
9328 %} | |
9329 | |
9330 | |
9331 // Tail Jump; remove the return address; jump to target. | |
9332 // TailCall above leaves the return address around. | |
9333 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
9334 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
9335 // "restore" before this instruction (in Epilogue), we need to materialize it | |
9336 // in %i0. | |
9337 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
9338 match( TailJump jump_target ex_oop ); | |
9339 ins_cost(CALL_COST); | |
9340 format %{ "! discard R_O7\n\t" | |
9341 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
9342 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
9343 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
9344 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
9345 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
9346 ins_pipe(tail_call); | |
9347 %} | |
9348 | |
9349 // Create exception oop: created by stack-crawling runtime code. | |
9350 // Created exception is now available to this handler, and is setup | |
9351 // just prior to jumping to this handler. No code emitted. | |
9352 instruct CreateException( o0RegP ex_oop ) | |
9353 %{ | |
9354 match(Set ex_oop (CreateEx)); | |
9355 ins_cost(0); | |
9356 | |
9357 size(0); | |
9358 // use the following format syntax | |
9359 format %{ "! exception oop is in R_O0; no code emitted" %} | |
9360 ins_encode(); | |
9361 ins_pipe(empty); | |
9362 %} | |
9363 | |
9364 | |
9365 // Rethrow exception: | |
9366 // The exception oop will come in the first argument position. | |
9367 // Then JUMP (not call) to the rethrow stub code. | |
9368 instruct RethrowException() | |
9369 %{ | |
9370 match(Rethrow); | |
9371 ins_cost(CALL_COST); | |
9372 | |
9373 // use the following format syntax | |
9374 format %{ "Jmp rethrow_stub" %} | |
9375 ins_encode(enc_rethrow); | |
9376 ins_pipe(tail_call); | |
9377 %} | |
9378 | |
9379 | |
9380 // Die now | |
9381 instruct ShouldNotReachHere( ) | |
9382 %{ | |
9383 match(Halt); | |
9384 ins_cost(CALL_COST); | |
9385 | |
9386 size(4); | |
9387 // Use the following format syntax | |
9388 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
9389 ins_encode( form2_illtrap() ); | |
9390 ins_pipe(tail_call); | |
9391 %} | |
9392 | |
9393 // ============================================================================ | |
9394 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
9395 // array for an instance of the superklass. Set a hidden internal cache on a | |
9396 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
9397 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
9398 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
9399 match(Set index (PartialSubtypeCheck sub super)); | |
9400 effect( KILL pcc, KILL o7 ); | |
9401 ins_cost(DEFAULT_COST*10); | |
9402 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
9403 ins_encode( enc_PartialSubtypeCheck() ); | |
9404 ins_pipe(partial_subtype_check_pipe); | |
9405 %} | |
9406 | |
9407 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
9408 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
9409 effect( KILL idx, KILL o7 ); | |
9410 ins_cost(DEFAULT_COST*10); | |
9411 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
9412 ins_encode( enc_PartialSubtypeCheck() ); | |
9413 ins_pipe(partial_subtype_check_pipe); | |
9414 %} | |
9415 | |
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9416 |
0 | 9417 // ============================================================================ |
9418 // inlined locking and unlocking | |
9419 | |
9420 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9421 match(Set pcc (FastLock object box)); | |
9422 | |
9423 effect(KILL scratch, TEMP scratch2); | |
9424 ins_cost(100); | |
9425 | |
9426 size(4*112); // conservative overestimation ... | |
9427 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9428 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
9429 ins_pipe(long_memory_op); | |
9430 %} | |
9431 | |
9432 | |
9433 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9434 match(Set pcc (FastUnlock object box)); | |
9435 effect(KILL scratch, TEMP scratch2); | |
9436 ins_cost(100); | |
9437 | |
9438 size(4*120); // conservative overestimation ... | |
9439 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9440 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
9441 ins_pipe(long_memory_op); | |
9442 %} | |
9443 | |
9444 // Count and Base registers are fixed because the allocator cannot | |
9445 // kill unknown registers. The encodings are generic. | |
9446 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
9447 match(Set dummy (ClearArray cnt base)); | |
9448 effect(TEMP temp, KILL ccr); | |
9449 ins_cost(300); | |
9450 format %{ "MOV $cnt,$temp\n" | |
9451 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
9452 " BRge loop\t\t! Clearing loop\n" | |
9453 " STX G0,[$base+$temp]\t! delay slot" %} | |
9454 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
9455 ins_pipe(long_memory_op); | |
9456 %} | |
9457 | |
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9458 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
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9459 o7RegI tmp, flagsReg ccr) %{ |
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9460 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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9461 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 9462 ins_cost(300); |
986
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9463 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
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9464 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 9465 ins_pipe(long_memory_op); |
9466 %} | |
9467 | |
986
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9468 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
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9469 o7RegI tmp, flagsReg ccr) %{ |
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9470 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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9471 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 9472 ins_cost(300); |
986
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9473 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
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9474 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 9475 ins_pipe(long_memory_op); |
9476 %} | |
9477 | |
986
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9478 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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9479 o7RegI tmp2, flagsReg ccr) %{ |
681 | 9480 match(Set result (AryEq ary1 ary2)); |
9481 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
9482 ins_cost(300); | |
986
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9483 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
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9484 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 9485 ins_pipe(long_memory_op); |
9486 %} | |
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9487 |
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9488 |
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9489 //---------- Zeros Count Instructions ------------------------------------------ |
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9490 |
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9491 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
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9492 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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9493 match(Set dst (CountLeadingZerosI src)); |
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9494 effect(TEMP dst, TEMP tmp, KILL cr); |
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9495 |
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9496 // x |= (x >> 1); |
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9497 // x |= (x >> 2); |
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9498 // x |= (x >> 4); |
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9499 // x |= (x >> 8); |
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9500 // x |= (x >> 16); |
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9501 // return (WORDBITS - popc(x)); |
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9502 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
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9503 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
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9504 "OR $dst,$tmp,$dst\n\t" |
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9505 "SRL $dst,2,$tmp\n\t" |
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9506 "OR $dst,$tmp,$dst\n\t" |
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9507 "SRL $dst,4,$tmp\n\t" |
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9508 "OR $dst,$tmp,$dst\n\t" |
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9509 "SRL $dst,8,$tmp\n\t" |
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9510 "OR $dst,$tmp,$dst\n\t" |
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9511 "SRL $dst,16,$tmp\n\t" |
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9512 "OR $dst,$tmp,$dst\n\t" |
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9513 "POPC $dst,$dst\n\t" |
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9514 "MOV 32,$tmp\n\t" |
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9515 "SUB $tmp,$dst,$dst" %} |
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9516 ins_encode %{ |
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9517 Register Rdst = $dst$$Register; |
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9518 Register Rsrc = $src$$Register; |
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9519 Register Rtmp = $tmp$$Register; |
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9520 __ srl(Rsrc, 1, Rtmp); |
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9521 __ srl(Rsrc, 0, Rdst); |
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9522 __ or3(Rdst, Rtmp, Rdst); |
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9523 __ srl(Rdst, 2, Rtmp); |
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9524 __ or3(Rdst, Rtmp, Rdst); |
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9525 __ srl(Rdst, 4, Rtmp); |
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9526 __ or3(Rdst, Rtmp, Rdst); |
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9527 __ srl(Rdst, 8, Rtmp); |
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9528 __ or3(Rdst, Rtmp, Rdst); |
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9529 __ srl(Rdst, 16, Rtmp); |
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9530 __ or3(Rdst, Rtmp, Rdst); |
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9531 __ popc(Rdst, Rdst); |
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changeset
|
9532 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9533 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9534 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9535 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9536 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9537 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9538 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9539 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9540 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9541 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9542 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9543 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9544 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9545 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9546 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9547 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9548 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9549 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9550 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9551 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9552 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9553 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9554 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9555 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9556 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9557 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9558 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9559 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9560 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9561 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9562 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9563 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9564 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9565 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9566 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9567 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9568 Register Rtmp = $tmp$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9569 __ srlx(Rsrc, 1, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9570 __ or3(Rsrc, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9571 __ srlx(Rdst, 2, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9572 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9573 __ srlx(Rdst, 4, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9574 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9575 __ srlx(Rdst, 8, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9576 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9577 __ srlx(Rdst, 16, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9578 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9579 __ srlx(Rdst, 32, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9580 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9581 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9582 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9583 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9584 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9585 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9586 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9587 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9588 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9589 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9590 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9591 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9592 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9593 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9594 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9595 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9596 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9597 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9598 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9599 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9600 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9601 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9602 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9603 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9604 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9605 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9606 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9607 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9608 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9609 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9610 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9611 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9612 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9613 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9614 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9615 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9616 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9617 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9618 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9619 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9620 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9621 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9622 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9623 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9624 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9625 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9626 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9627 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9628 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9629 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9630 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9631 instruct popCountI(iRegI dst, iRegI src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9632 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9633 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9634 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9635 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9636 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9637 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9638 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9639 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9640 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9641 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9642 // Note: Long.bitCount(long) returns an int. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9643 instruct popCountL(iRegI dst, iRegL src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9644 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9645 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9646 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9647 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9648 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9649 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9650 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9651 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9652 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9653 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9654 |
0 | 9655 // ============================================================================ |
9656 //------------Bytes reverse-------------------------------------------------- | |
9657 | |
9658 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
9659 match(Set dst (ReverseBytesI src)); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9660 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9661 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9662 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9663 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9664 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9665 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9666 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9667 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9668 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9669 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9670 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9671 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9672 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9673 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9674 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9675 match(Set dst (ReverseBytesL src)); |
0 | 9676 |
9677 // Op cost is artificially doubled to make sure that load or store | |
9678 // instructions are preferred over this one which requires a spill | |
9679 // onto a stack slot. | |
9680 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9681 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9682 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9683 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9684 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9685 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9686 %} |
0 | 9687 ins_pipe( iload_mem ); |
9688 %} | |
9689 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9690 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9691 match(Set dst (ReverseBytesUS src)); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9692 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9693 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9694 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9695 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9696 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9697 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9698 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9699 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9700 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9701 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9702 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9703 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9704 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9705 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9706 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9707 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9708 match(Set dst (ReverseBytesS src)); |
0 | 9709 |
9710 // Op cost is artificially doubled to make sure that load or store | |
9711 // instructions are preferred over this one which requires a spill | |
9712 // onto a stack slot. | |
9713 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9714 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9715 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9716 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9717 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9718 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9719 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9720 %} |
0 | 9721 ins_pipe( iload_mem ); |
9722 %} | |
9723 | |
9724 // Load Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9725 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
0 | 9726 match(Set dst (ReverseBytesI (LoadI src))); |
9727 | |
9728 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9729 size(4); |
0 | 9730 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
9731 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9732 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9733 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9734 %} |
0 | 9735 ins_pipe(iload_mem); |
9736 %} | |
9737 | |
9738 // Load Long - aligned and reversed | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9739 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
0 | 9740 match(Set dst (ReverseBytesL (LoadL src))); |
9741 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9742 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9743 size(4); |
0 | 9744 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
9745 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9746 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9747 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9748 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9749 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9750 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9751 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9752 // Load unsigned short / char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9753 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9754 match(Set dst (ReverseBytesUS (LoadUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9755 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9756 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9757 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9758 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9759 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9760 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9761 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9762 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9763 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9764 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9765 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9766 // Load short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9767 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9768 match(Set dst (ReverseBytesS (LoadS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9769 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9770 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9771 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9772 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9773 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9774 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9775 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9776 %} |
0 | 9777 ins_pipe(iload_mem); |
9778 %} | |
9779 | |
9780 // Store Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9781 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
0 | 9782 match(Set dst (StoreI dst (ReverseBytesI src))); |
9783 | |
9784 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9785 size(4); |
0 | 9786 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
9787 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9788 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9789 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9790 %} |
0 | 9791 ins_pipe(istore_mem_reg); |
9792 %} | |
9793 | |
9794 // Store Long reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9795 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
0 | 9796 match(Set dst (StoreL dst (ReverseBytesL src))); |
9797 | |
9798 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9799 size(4); |
0 | 9800 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
9801 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9802 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9803 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9804 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9805 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9806 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9807 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9808 // Store unsighed short/char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9809 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9810 match(Set dst (StoreC dst (ReverseBytesUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9811 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9812 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9813 size(4); |
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9814 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
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9815 |
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9816 ins_encode %{ |
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9817 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
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9818 %} |
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9819 ins_pipe(istore_mem_reg); |
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9820 %} |
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9821 |
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9822 // Store short reversed byte order |
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9823 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
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9824 match(Set dst (StoreC dst (ReverseBytesS src))); |
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diff
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|
9825 |
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9826 ins_cost(MEMORY_REF_COST); |
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|
9827 size(4); |
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9828 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
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diff
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|
9829 |
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|
9830 ins_encode %{ |
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9831 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
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9832 %} |
0 | 9833 ins_pipe(istore_mem_reg); |
9834 %} | |
9835 | |
9836 //----------PEEPHOLE RULES----------------------------------------------------- | |
9837 // These must follow all instruction definitions as they use the names | |
9838 // defined in the instructions definitions. | |
9839 // | |
605 | 9840 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 9841 // |
9842 // peepconstraint %{ | |
9843 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
9844 // [, ...] ); | |
9845 // // instruction numbers are zero-based using left to right order in peepmatch | |
9846 // | |
9847 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
9848 // // provide an instruction_number.operand_name for each operand that appears | |
9849 // // in the replacement instruction's match rule | |
9850 // | |
9851 // ---------VM FLAGS--------------------------------------------------------- | |
9852 // | |
9853 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
9854 // | |
9855 // Each peephole rule is given an identifying number starting with zero and | |
9856 // increasing by one in the order seen by the parser. An individual peephole | |
9857 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
9858 // on the command-line. | |
9859 // | |
9860 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
9861 // | |
9862 // Only match adjacent instructions in same basic block | |
9863 // Only equality constraints | |
9864 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
9865 // Only one replacement instruction | |
9866 // | |
9867 // ---------EXAMPLE---------------------------------------------------------- | |
9868 // | |
9869 // // pertinent parts of existing instructions in architecture description | |
9870 // instruct movI(eRegI dst, eRegI src) %{ | |
9871 // match(Set dst (CopyI src)); | |
9872 // %} | |
9873 // | |
9874 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
9875 // match(Set dst (AddI dst src)); | |
9876 // effect(KILL cr); | |
9877 // %} | |
9878 // | |
9879 // // Change (inc mov) to lea | |
9880 // peephole %{ | |
9881 // // increment preceeded by register-register move | |
9882 // peepmatch ( incI_eReg movI ); | |
9883 // // require that the destination register of the increment | |
9884 // // match the destination register of the move | |
9885 // peepconstraint ( 0.dst == 1.dst ); | |
9886 // // construct a replacement instruction that sets | |
9887 // // the destination to ( move's source register + one ) | |
9888 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
9889 // %} | |
9890 // | |
9891 | |
9892 // // Change load of spilled value to only a spill | |
9893 // instruct storeI(memory mem, eRegI src) %{ | |
9894 // match(Set mem (StoreI mem src)); | |
9895 // %} | |
9896 // | |
9897 // instruct loadI(eRegI dst, memory mem) %{ | |
9898 // match(Set dst (LoadI mem)); | |
9899 // %} | |
9900 // | |
9901 // peephole %{ | |
9902 // peepmatch ( loadI storeI ); | |
9903 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
9904 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
9905 // %} | |
9906 | |
9907 //----------SMARTSPILL RULES--------------------------------------------------- | |
9908 // These must follow all instruction definitions as they use the names | |
9909 // defined in the instructions definitions. | |
9910 // | |
9911 // SPARC will probably not have any of these rules due to RISC instruction set. | |
9912 | |
9913 //----------PIPELINE----------------------------------------------------------- | |
9914 // Rules which define the behavior of the target architectures pipeline. |