annotate src/cpu/sparc/vm/sparc.ad @ 775:93c14e5562c4

6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents fb4c18a2ec66
children 2056494941db
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1 //
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337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
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2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 // CA 95054 USA or visit www.sun.com if you need additional information or
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21 // have any questions.
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22 //
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23 //
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24
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25 // SPARC Architecture Description File
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26
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27 //----------REGISTER DEFINITION BLOCK------------------------------------------
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28 // This information is used by the matcher and the register allocator to
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29 // describe individual registers and classes of registers within the target
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30 // archtecture.
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31 register %{
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32 //----------Architecture Description Register Definitions----------------------
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33 // General Registers
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34 // "reg_def" name ( register save type, C convention save type,
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35 // ideal register type, encoding, vm name );
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36 // Register Save Types:
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37 //
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38 // NS = No-Save: The register allocator assumes that these registers
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39 // can be used without saving upon entry to the method, &
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40 // that they do not need to be saved at call sites.
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41 //
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42 // SOC = Save-On-Call: The register allocator assumes that these registers
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43 // can be used without saving upon entry to the method,
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44 // but that they must be saved at call sites.
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45 //
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46 // SOE = Save-On-Entry: The register allocator assumes that these registers
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47 // must be saved before using them upon entry to the
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48 // method, but they do not need to be saved at call
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49 // sites.
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50 //
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51 // AS = Always-Save: The register allocator assumes that these registers
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52 // must be saved before using them upon entry to the
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53 // method, & that they must be saved at call sites.
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54 //
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55 // Ideal Register Type is used to determine how to save & restore a
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56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
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57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
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58 //
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59 // The encoding number is the actual bit-pattern placed into the opcodes.
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60
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61
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62 // ----------------------------
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63 // Integer/Long Registers
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64 // ----------------------------
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65
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66 // Need to expose the hi/lo aspect of 64-bit registers
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67 // This register set is used for both the 64-bit build and
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68 // the 32-bit build with 1-register longs.
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69
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70 // Global Registers 0-7
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71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
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72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
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73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
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74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
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75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
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76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
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77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
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78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
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79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
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80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
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81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
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82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
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83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
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84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
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85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
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86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
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87
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88 // Output Registers 0-7
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89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
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90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
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91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
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92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
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93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
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94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
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95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
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96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
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97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
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98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
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99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
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100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
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101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
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102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
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103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
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104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
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105
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106 // Local Registers 0-7
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107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
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108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
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109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
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110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
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111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
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112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
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113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
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114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
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115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
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116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
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117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
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118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
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119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
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120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
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121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
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122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
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123
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124 // Input Registers 0-7
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125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
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126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
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127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
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128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
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129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
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130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
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131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
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132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
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133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
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134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
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135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
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136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
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137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
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138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
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139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
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140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
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141
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142 // ----------------------------
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143 // Float/Double Registers
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144 // ----------------------------
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145
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146 // Float Registers
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147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
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148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
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149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
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150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
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151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
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152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
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153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
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154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
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155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
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156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
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157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
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158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
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159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
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160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
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161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
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162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
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163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
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164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
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165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
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166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
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167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
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168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
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169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
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170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
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171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
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172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
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173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
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174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
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175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
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176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
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177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
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178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
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179
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180 // Double Registers
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181 // The rules of ADL require that double registers be defined in pairs.
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182 // Each pair must be two 32-bit values, but not necessarily a pair of
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183 // single float registers. In each pair, ADLC-assigned register numbers
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184 // must be adjacent, with the lower number even. Finally, when the
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185 // CPU stores such a register pair to memory, the word associated with
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186 // the lower ADLC-assigned number must be stored to the lower address.
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187
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188 // These definitions specify the actual bit encodings of the sparc
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189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
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190 // wants 0-63, so we have to convert every time we want to use fp regs
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191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
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98cb887364d3 6810672: Comment typos
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192 // 255 is a flag meaning "don't go here".
0
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193 // I believe we can't handle callee-save doubles D32 and up until
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194 // the place in the sparc stack crawler that asserts on the 255 is
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195 // fixed up.
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196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
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197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
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198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
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199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
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200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
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201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
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202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
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203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
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204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
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205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
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206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
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207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
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208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
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209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
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210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
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211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
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212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
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213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
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214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
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215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
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216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
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217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
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218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
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219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
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220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
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221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
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222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
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223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
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224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
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225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
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226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
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227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
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228
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229
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230 // ----------------------------
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231 // Special Registers
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232 // Condition Codes Flag Registers
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233 // I tried to break out ICC and XCC but it's not very pretty.
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234 // Every Sparc instruction which defs/kills one also kills the other.
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235 // Hence every compare instruction which defs one kind of flags ends
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236 // up needing a kill of the other.
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237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
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238
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239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
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240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
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241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
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242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
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243
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244 // ----------------------------
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245 // Specify the enum values for the registers. These enums are only used by the
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246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
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247 // for visibility to the rest of the vm. The order of this enum influences the
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248 // register allocator so having the freedom to set this order and not be stuck
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249 // with the order that is natural for the rest of the vm is worth it.
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250 alloc_class chunk0(
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251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
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252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
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253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
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254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
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255
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256 // Note that a register is not allocatable unless it is also mentioned
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257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
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258
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259 alloc_class chunk1(
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260 // The first registers listed here are those most likely to be used
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261 // as temporaries. We move F0..F7 away from the front of the list,
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262 // to reduce the likelihood of interferences with parameters and
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263 // return values. Likewise, we avoid using F0/F1 for parameters,
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264 // since they are used for return values.
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265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
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266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
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267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
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268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
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269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
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270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
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271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
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272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
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273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
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274
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275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
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276
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277 //----------Architecture Description Register Classes--------------------------
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278 // Several register classes are automatically defined based upon information in
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279 // this architecture description.
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280 // 1) reg_class inline_cache_reg ( as defined in frame section )
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281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
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282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
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283 //
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284
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285 // G0 is not included in integer class since it has special meaning.
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286 reg_class g0_reg(R_G0);
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287
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288 // ----------------------------
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289 // Integer Register Classes
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290 // ----------------------------
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291 // Exclusions from i_reg:
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292 // R_G0: hardwired zero
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293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
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294 // R_G6: reserved by Solaris ABI to tools
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295 // R_G7: reserved by Solaris ABI to libthread
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296 // R_O7: Used as a temp in many encodings
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297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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298
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299 // Class for all integer registers, except the G registers. This is used for
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300 // encodings which use G registers as temps. The regular inputs to such
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301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
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302 // will not put an input into a temp register.
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303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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304
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305 reg_class g1_regI(R_G1);
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306 reg_class g3_regI(R_G3);
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307 reg_class g4_regI(R_G4);
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308 reg_class o0_regI(R_O0);
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309 reg_class o7_regI(R_O7);
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310
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311 // ----------------------------
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312 // Pointer Register Classes
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313 // ----------------------------
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314 #ifdef _LP64
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315 // 64-bit build means 64-bit pointers means hi/lo pairs
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316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
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317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
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318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
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319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
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320 // Lock encodings use G3 and G4 internally
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321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
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322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
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323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
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324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
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325 // Special class for storeP instructions, which can store SP or RPC to TLS.
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326 // It is also used for memory addressing, allowing direct TLS addressing.
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327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
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328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
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329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
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330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
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331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
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332 // We use it to save R_G2 across calls out of Java.
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333 reg_class l7_regP(R_L7H,R_L7);
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334
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335 // Other special pointer regs
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parents:
diff changeset
336 reg_class g1_regP(R_G1H,R_G1);
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parents:
diff changeset
337 reg_class g2_regP(R_G2H,R_G2);
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parents:
diff changeset
338 reg_class g3_regP(R_G3H,R_G3);
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parents:
diff changeset
339 reg_class g4_regP(R_G4H,R_G4);
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parents:
diff changeset
340 reg_class g5_regP(R_G5H,R_G5);
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parents:
diff changeset
341 reg_class i0_regP(R_I0H,R_I0);
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parents:
diff changeset
342 reg_class o0_regP(R_O0H,R_O0);
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parents:
diff changeset
343 reg_class o1_regP(R_O1H,R_O1);
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parents:
diff changeset
344 reg_class o2_regP(R_O2H,R_O2);
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parents:
diff changeset
345 reg_class o7_regP(R_O7H,R_O7);
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parents:
diff changeset
346
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parents:
diff changeset
347 #else // _LP64
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parents:
diff changeset
348 // 32-bit build means 32-bit pointers means 1 register.
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parents:
diff changeset
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
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parents:
diff changeset
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
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parents:
diff changeset
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
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parents:
diff changeset
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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parents:
diff changeset
353 // Lock encodings use G3 and G4 internally
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parents:
diff changeset
354 reg_class lock_ptr_reg(R_G1, R_G5,
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parents:
diff changeset
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
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parents:
diff changeset
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
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parents:
diff changeset
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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parents:
diff changeset
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
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parents:
diff changeset
359 // It is also used for memory addressing, allowing direct TLS addressing.
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parents:
diff changeset
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
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parents:
diff changeset
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
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parents:
diff changeset
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
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parents:
diff changeset
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
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parents:
diff changeset
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
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parents:
diff changeset
365 // We use it to save R_G2 across calls out of Java.
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parents:
diff changeset
366 reg_class l7_regP(R_L7);
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parents:
diff changeset
367
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parents:
diff changeset
368 // Other special pointer regs
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parents:
diff changeset
369 reg_class g1_regP(R_G1);
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parents:
diff changeset
370 reg_class g2_regP(R_G2);
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parents:
diff changeset
371 reg_class g3_regP(R_G3);
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parents:
diff changeset
372 reg_class g4_regP(R_G4);
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parents:
diff changeset
373 reg_class g5_regP(R_G5);
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parents:
diff changeset
374 reg_class i0_regP(R_I0);
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parents:
diff changeset
375 reg_class o0_regP(R_O0);
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parents:
diff changeset
376 reg_class o1_regP(R_O1);
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parents:
diff changeset
377 reg_class o2_regP(R_O2);
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parents:
diff changeset
378 reg_class o7_regP(R_O7);
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parents:
diff changeset
379 #endif // _LP64
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parents:
diff changeset
380
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parents:
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381
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parents:
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382 // ----------------------------
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parents:
diff changeset
383 // Long Register Classes
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parents:
diff changeset
384 // ----------------------------
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parents:
diff changeset
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
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parents:
diff changeset
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
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parents:
diff changeset
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
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parents:
diff changeset
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
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parents:
diff changeset
389 #ifdef _LP64
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parents:
diff changeset
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
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parents:
diff changeset
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
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parents:
diff changeset
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
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parents:
diff changeset
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
a61af66fc99e Initial load
duke
parents:
diff changeset
394 #endif // _LP64
a61af66fc99e Initial load
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parents:
diff changeset
395 );
a61af66fc99e Initial load
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parents:
diff changeset
396
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parents:
diff changeset
397 reg_class g1_regL(R_G1H,R_G1);
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
398 reg_class g3_regL(R_G3H,R_G3);
0
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parents:
diff changeset
399 reg_class o2_regL(R_O2H,R_O2);
a61af66fc99e Initial load
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parents:
diff changeset
400 reg_class o7_regL(R_O7H,R_O7);
a61af66fc99e Initial load
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parents:
diff changeset
401
a61af66fc99e Initial load
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parents:
diff changeset
402 // ----------------------------
a61af66fc99e Initial load
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parents:
diff changeset
403 // Special Class for Condition Code Flags Register
a61af66fc99e Initial load
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parents:
diff changeset
404 reg_class int_flags(CCR);
a61af66fc99e Initial load
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parents:
diff changeset
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
a61af66fc99e Initial load
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parents:
diff changeset
406 reg_class float_flag0(FCC0);
a61af66fc99e Initial load
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parents:
diff changeset
407
a61af66fc99e Initial load
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parents:
diff changeset
408
a61af66fc99e Initial load
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parents:
diff changeset
409 // ----------------------------
a61af66fc99e Initial load
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parents:
diff changeset
410 // Float Point Register Classes
a61af66fc99e Initial load
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parents:
diff changeset
411 // ----------------------------
a61af66fc99e Initial load
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parents:
diff changeset
412 // Skip F30/F31, they are reserved for mem-mem copies
a61af66fc99e Initial load
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parents:
diff changeset
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
a61af66fc99e Initial load
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parents:
diff changeset
414
a61af66fc99e Initial load
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parents:
diff changeset
415 // Paired floating point registers--they show up in the same order as the floats,
a61af66fc99e Initial load
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parents:
diff changeset
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
a61af66fc99e Initial load
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parents:
diff changeset
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
a61af66fc99e Initial load
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parents:
diff changeset
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
a61af66fc99e Initial load
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parents:
diff changeset
419 /* Use extra V9 double registers; this AD file does not support V8 */
a61af66fc99e Initial load
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parents:
diff changeset
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
a61af66fc99e Initial load
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parents:
diff changeset
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
a61af66fc99e Initial load
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parents:
diff changeset
422 );
a61af66fc99e Initial load
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parents:
diff changeset
423
a61af66fc99e Initial load
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parents:
diff changeset
424 // Paired floating point registers--they show up in the same order as the floats,
a61af66fc99e Initial load
duke
parents:
diff changeset
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
a61af66fc99e Initial load
duke
parents:
diff changeset
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
a61af66fc99e Initial load
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parents:
diff changeset
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
a61af66fc99e Initial load
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parents:
diff changeset
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
a61af66fc99e Initial load
duke
parents:
diff changeset
429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
430
a61af66fc99e Initial load
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parents:
diff changeset
431 //----------DEFINITION BLOCK---------------------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
432 // Define name --> value mappings to inform the ADLC of an integer valued name
a61af66fc99e Initial load
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parents:
diff changeset
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
a61af66fc99e Initial load
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parents:
diff changeset
434 // Format:
a61af66fc99e Initial load
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parents:
diff changeset
435 // int_def <name> ( <int_value>, <expression>);
a61af66fc99e Initial load
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parents:
diff changeset
436 // Generated Code in ad_<arch>.hpp
a61af66fc99e Initial load
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parents:
diff changeset
437 // #define <name> (<expression>)
a61af66fc99e Initial load
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parents:
diff changeset
438 // // value == <int_value>
a61af66fc99e Initial load
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parents:
diff changeset
439 // Generated code in ad_<arch>.cpp adlc_verification()
a61af66fc99e Initial load
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parents:
diff changeset
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
a61af66fc99e Initial load
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parents:
diff changeset
441 //
a61af66fc99e Initial load
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parents:
diff changeset
442 definitions %{
a61af66fc99e Initial load
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parents:
diff changeset
443 // The default cost (of an ALU instruction).
a61af66fc99e Initial load
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parents:
diff changeset
444 int_def DEFAULT_COST ( 100, 100);
a61af66fc99e Initial load
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parents:
diff changeset
445 int_def HUGE_COST (1000000, 1000000);
a61af66fc99e Initial load
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parents:
diff changeset
446
a61af66fc99e Initial load
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parents:
diff changeset
447 // Memory refs are twice as expensive as run-of-the-mill.
a61af66fc99e Initial load
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parents:
diff changeset
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
a61af66fc99e Initial load
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parents:
diff changeset
449
a61af66fc99e Initial load
duke
parents:
diff changeset
450 // Branches are even more expensive.
a61af66fc99e Initial load
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parents:
diff changeset
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
a61af66fc99e Initial load
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parents:
diff changeset
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
a61af66fc99e Initial load
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parents:
diff changeset
453 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
454
a61af66fc99e Initial load
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parents:
diff changeset
455
a61af66fc99e Initial load
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parents:
diff changeset
456 //----------SOURCE BLOCK-------------------------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
457 // This is a block of C++ code which provides values, functions, and
a61af66fc99e Initial load
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parents:
diff changeset
458 // definitions necessary in the rest of the architecture description
a61af66fc99e Initial load
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parents:
diff changeset
459 source_hpp %{
a61af66fc99e Initial load
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parents:
diff changeset
460 // Must be visible to the DFA in dfa_sparc.cpp
a61af66fc99e Initial load
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parents:
diff changeset
461 extern bool can_branch_register( Node *bol, Node *cmp );
a61af66fc99e Initial load
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parents:
diff changeset
462
a61af66fc99e Initial load
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parents:
diff changeset
463 // Macros to extract hi & lo halves from a long pair.
a61af66fc99e Initial load
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parents:
diff changeset
464 // G0 is not part of any long pair, so assert on that.
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
465 // Prevents accidentally using G1 instead of G0.
0
a61af66fc99e Initial load
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parents:
diff changeset
466 #define LONG_HI_REG(x) (x)
a61af66fc99e Initial load
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parents:
diff changeset
467 #define LONG_LO_REG(x) (x)
a61af66fc99e Initial load
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parents:
diff changeset
468
a61af66fc99e Initial load
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parents:
diff changeset
469 %}
a61af66fc99e Initial load
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parents:
diff changeset
470
a61af66fc99e Initial load
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parents:
diff changeset
471 source %{
a61af66fc99e Initial load
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parents:
diff changeset
472 #define __ _masm.
a61af66fc99e Initial load
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parents:
diff changeset
473
a61af66fc99e Initial load
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parents:
diff changeset
474 // tertiary op of a LoadP or StoreP encoding
a61af66fc99e Initial load
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parents:
diff changeset
475 #define REGP_OP true
a61af66fc99e Initial load
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parents:
diff changeset
476
a61af66fc99e Initial load
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parents:
diff changeset
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
a61af66fc99e Initial load
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parents:
diff changeset
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
a61af66fc99e Initial load
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parents:
diff changeset
479 static Register reg_to_register_object(int register_encoding);
a61af66fc99e Initial load
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parents:
diff changeset
480
a61af66fc99e Initial load
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parents:
diff changeset
481 // Used by the DFA in dfa_sparc.cpp.
a61af66fc99e Initial load
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parents:
diff changeset
482 // Check for being able to use a V9 branch-on-register. Requires a
a61af66fc99e Initial load
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parents:
diff changeset
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
a61af66fc99e Initial load
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parents:
diff changeset
484 // extended. Doesn't work following an integer ADD, for example, because of
a61af66fc99e Initial load
duke
parents:
diff changeset
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
a61af66fc99e Initial load
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parents:
diff changeset
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
a61af66fc99e Initial load
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parents:
diff changeset
487 // replace them with zero, which could become sign-extension in a different OS
a61af66fc99e Initial load
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parents:
diff changeset
488 // release. There's no obvious reason why an interrupt will ever fill these
a61af66fc99e Initial load
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parents:
diff changeset
489 // bits with non-zero junk (the registers are reloaded with standard LD
a61af66fc99e Initial load
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parents:
diff changeset
490 // instructions which either zero-fill or sign-fill).
a61af66fc99e Initial load
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parents:
diff changeset
491 bool can_branch_register( Node *bol, Node *cmp ) {
a61af66fc99e Initial load
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parents:
diff changeset
492 if( !BranchOnRegister ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
493 #ifdef _LP64
a61af66fc99e Initial load
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parents:
diff changeset
494 if( cmp->Opcode() == Op_CmpP )
a61af66fc99e Initial load
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parents:
diff changeset
495 return true; // No problems with pointer compares
a61af66fc99e Initial load
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parents:
diff changeset
496 #endif
a61af66fc99e Initial load
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parents:
diff changeset
497 if( cmp->Opcode() == Op_CmpL )
a61af66fc99e Initial load
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parents:
diff changeset
498 return true; // No problems with long compares
a61af66fc99e Initial load
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parents:
diff changeset
499
a61af66fc99e Initial load
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parents:
diff changeset
500 if( !SparcV9RegsHiBitsZero ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
a61af66fc99e Initial load
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parents:
diff changeset
502 bol->as_Bool()->_test._test != BoolTest::eq )
a61af66fc99e Initial load
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parents:
diff changeset
503 return false;
a61af66fc99e Initial load
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parents:
diff changeset
504
a61af66fc99e Initial load
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parents:
diff changeset
505 // Check for comparing against a 'safe' value. Any operation which
a61af66fc99e Initial load
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parents:
diff changeset
506 // clears out the high word is safe. Thus, loads and certain shifts
a61af66fc99e Initial load
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parents:
diff changeset
507 // are safe, as are non-negative constants. Any operation which
a61af66fc99e Initial load
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parents:
diff changeset
508 // preserves zero bits in the high word is safe as long as each of its
a61af66fc99e Initial load
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parents:
diff changeset
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
a61af66fc99e Initial load
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parents:
diff changeset
510 // inputs are safe. At present, the only important case to recognize
a61af66fc99e Initial load
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parents:
diff changeset
511 // seems to be loads. Constants should fold away, and shifts &
a61af66fc99e Initial load
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parents:
diff changeset
512 // logicals can use the 'cc' forms.
a61af66fc99e Initial load
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parents:
diff changeset
513 Node *x = cmp->in(1);
a61af66fc99e Initial load
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parents:
diff changeset
514 if( x->is_Load() ) return true;
a61af66fc99e Initial load
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parents:
diff changeset
515 if( x->is_Phi() ) {
a61af66fc99e Initial load
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parents:
diff changeset
516 for( uint i = 1; i < x->req(); i++ )
a61af66fc99e Initial load
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parents:
diff changeset
517 if( !x->in(i)->is_Load() )
a61af66fc99e Initial load
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parents:
diff changeset
518 return false;
a61af66fc99e Initial load
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parents:
diff changeset
519 return true;
a61af66fc99e Initial load
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parents:
diff changeset
520 }
a61af66fc99e Initial load
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parents:
diff changeset
521 return false;
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parents:
diff changeset
522 }
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parents:
diff changeset
523
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parents:
diff changeset
524 // ****************************************************************************
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parents:
diff changeset
525
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parents:
diff changeset
526 // REQUIRED FUNCTIONALITY
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parents:
diff changeset
527
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parents:
diff changeset
528 // !!!!! Special hack to get all type of calls to specify the byte offset
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parents:
diff changeset
529 // from the start of the call to the point where the return address
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parents:
diff changeset
530 // will point.
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parents:
diff changeset
531 // The "return address" is the address of the call instruction, plus 8.
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parents:
diff changeset
532
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parents:
diff changeset
533 int MachCallStaticJavaNode::ret_addr_offset() {
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parents:
diff changeset
534 return NativeCall::instruction_size; // call; delay slot
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parents:
diff changeset
535 }
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parents:
diff changeset
536
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parents:
diff changeset
537 int MachCallDynamicJavaNode::ret_addr_offset() {
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parents:
diff changeset
538 int vtable_index = this->_vtable_index;
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parents:
diff changeset
539 if (vtable_index < 0) {
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parents:
diff changeset
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
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parents:
diff changeset
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
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parents:
diff changeset
542 return (NativeMovConstReg::instruction_size +
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parents:
diff changeset
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
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parents:
diff changeset
544 } else {
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parents:
diff changeset
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
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parents:
diff changeset
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
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parents:
diff changeset
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
113
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parents: 81
diff changeset
548 int klass_load_size;
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coleenp
parents: 81
diff changeset
549 if (UseCompressedOops) {
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
550 assert(Universe::heap() != NULL, "java heap should be initialized");
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
551 if (Universe::narrow_oop_base() == NULL)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
553 else
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
554 klass_load_size = 3*BytesPerInstWord;
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
555 } else {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
556 klass_load_size = 1*BytesPerInstWord;
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coleenp
parents: 81
diff changeset
557 }
0
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parents:
diff changeset
558 if( Assembler::is_simm13(v_off) ) {
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
559 return klass_load_size +
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
0
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parents:
diff changeset
561 NativeCall::instruction_size); // call; delay slot
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parents:
diff changeset
562 } else {
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
563 return klass_load_size +
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
0
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parents:
diff changeset
565 NativeCall::instruction_size); // call; delay slot
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parents:
diff changeset
566 }
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parents:
diff changeset
567 }
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parents:
diff changeset
568 }
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parents:
diff changeset
569
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parents:
diff changeset
570 int MachCallRuntimeNode::ret_addr_offset() {
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parents:
diff changeset
571 #ifdef _LP64
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parents:
diff changeset
572 return NativeFarCall::instruction_size; // farcall; delay slot
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parents:
diff changeset
573 #else
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parents:
diff changeset
574 return NativeCall::instruction_size; // call; delay slot
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parents:
diff changeset
575 #endif
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parents:
diff changeset
576 }
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parents:
diff changeset
577
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parents:
diff changeset
578 // Indicate if the safepoint node needs the polling page as an input.
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parents:
diff changeset
579 // Since Sparc does not have absolute addressing, it does.
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parents:
diff changeset
580 bool SafePointNode::needs_polling_address_input() {
a61af66fc99e Initial load
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parents:
diff changeset
581 return true;
a61af66fc99e Initial load
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parents:
diff changeset
582 }
a61af66fc99e Initial load
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parents:
diff changeset
583
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parents:
diff changeset
584 // emit an interrupt that is caught by the debugger (for debugging compiler)
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parents:
diff changeset
585 void emit_break(CodeBuffer &cbuf) {
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parents:
diff changeset
586 MacroAssembler _masm(&cbuf);
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parents:
diff changeset
587 __ breakpoint_trap();
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parents:
diff changeset
588 }
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parents:
diff changeset
589
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parents:
diff changeset
590 #ifndef PRODUCT
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parents:
diff changeset
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
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parents:
diff changeset
592 st->print("TA");
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parents:
diff changeset
593 }
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parents:
diff changeset
594 #endif
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parents:
diff changeset
595
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parents:
diff changeset
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
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parents:
diff changeset
597 emit_break(cbuf);
a61af66fc99e Initial load
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parents:
diff changeset
598 }
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parents:
diff changeset
599
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parents:
diff changeset
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
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parents:
diff changeset
601 return MachNode::size(ra_);
a61af66fc99e Initial load
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parents:
diff changeset
602 }
a61af66fc99e Initial load
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parents:
diff changeset
603
a61af66fc99e Initial load
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parents:
diff changeset
604 // Traceable jump
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parents:
diff changeset
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
a61af66fc99e Initial load
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parents:
diff changeset
606 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
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parents:
diff changeset
607 Register rdest = reg_to_register_object(jump_target);
a61af66fc99e Initial load
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parents:
diff changeset
608 __ JMP(rdest, 0);
a61af66fc99e Initial load
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parents:
diff changeset
609 __ delayed()->nop();
a61af66fc99e Initial load
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parents:
diff changeset
610 }
a61af66fc99e Initial load
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parents:
diff changeset
611
a61af66fc99e Initial load
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parents:
diff changeset
612 // Traceable jump and set exception pc
a61af66fc99e Initial load
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parents:
diff changeset
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
a61af66fc99e Initial load
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parents:
diff changeset
614 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
615 Register rdest = reg_to_register_object(jump_target);
a61af66fc99e Initial load
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parents:
diff changeset
616 __ JMP(rdest, 0);
a61af66fc99e Initial load
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parents:
diff changeset
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
a61af66fc99e Initial load
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parents:
diff changeset
618 }
a61af66fc99e Initial load
duke
parents:
diff changeset
619
a61af66fc99e Initial load
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parents:
diff changeset
620 void emit_nop(CodeBuffer &cbuf) {
a61af66fc99e Initial load
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parents:
diff changeset
621 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
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parents:
diff changeset
622 __ nop();
a61af66fc99e Initial load
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parents:
diff changeset
623 }
a61af66fc99e Initial load
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parents:
diff changeset
624
a61af66fc99e Initial load
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parents:
diff changeset
625 void emit_illtrap(CodeBuffer &cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
626 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
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parents:
diff changeset
627 __ illtrap(0);
a61af66fc99e Initial load
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parents:
diff changeset
628 }
a61af66fc99e Initial load
duke
parents:
diff changeset
629
a61af66fc99e Initial load
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parents:
diff changeset
630
a61af66fc99e Initial load
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parents:
diff changeset
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
a61af66fc99e Initial load
duke
parents:
diff changeset
632 assert(n->rule() != loadUB_rule, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
633
a61af66fc99e Initial load
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parents:
diff changeset
634 intptr_t offset = 0;
a61af66fc99e Initial load
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parents:
diff changeset
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
a61af66fc99e Initial load
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parents:
diff changeset
636 const Node* addr = n->get_base_and_disp(offset, adr_type);
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parents:
diff changeset
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
a61af66fc99e Initial load
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parents:
diff changeset
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
a61af66fc99e Initial load
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parents:
diff changeset
639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
a61af66fc99e Initial load
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parents:
diff changeset
640 atype = atype->add_offset(offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
641 assert(disp32 == offset, "wrong disp32");
a61af66fc99e Initial load
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parents:
diff changeset
642 return atype->_offset;
a61af66fc99e Initial load
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parents:
diff changeset
643 }
a61af66fc99e Initial load
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parents:
diff changeset
644
a61af66fc99e Initial load
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parents:
diff changeset
645
a61af66fc99e Initial load
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parents:
diff changeset
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
a61af66fc99e Initial load
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parents:
diff changeset
647 assert(n->rule() != loadUB_rule, "");
a61af66fc99e Initial load
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parents:
diff changeset
648
a61af66fc99e Initial load
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parents:
diff changeset
649 intptr_t offset = 0;
a61af66fc99e Initial load
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parents:
diff changeset
650 Node* addr = n->in(2);
a61af66fc99e Initial load
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parents:
diff changeset
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
a61af66fc99e Initial load
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parents:
diff changeset
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
a61af66fc99e Initial load
duke
parents:
diff changeset
653 Node* a = addr->in(2/*AddPNode::Address*/);
a61af66fc99e Initial load
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parents:
diff changeset
654 Node* o = addr->in(3/*AddPNode::Offset*/);
a61af66fc99e Initial load
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parents:
diff changeset
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
a61af66fc99e Initial load
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parents:
diff changeset
656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
a61af66fc99e Initial load
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parents:
diff changeset
657 assert(atype->isa_oop_ptr(), "still an oop");
a61af66fc99e Initial load
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parents:
diff changeset
658 }
a61af66fc99e Initial load
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parents:
diff changeset
659 offset = atype->is_ptr()->_offset;
a61af66fc99e Initial load
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parents:
diff changeset
660 if (offset != Type::OffsetBot) offset += disp32;
a61af66fc99e Initial load
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parents:
diff changeset
661 return offset;
a61af66fc99e Initial load
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parents:
diff changeset
662 }
a61af66fc99e Initial load
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parents:
diff changeset
663
a61af66fc99e Initial load
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parents:
diff changeset
664 // Standard Sparc opcode form2 field breakdown
a61af66fc99e Initial load
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parents:
diff changeset
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
a61af66fc99e Initial load
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parents:
diff changeset
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
a61af66fc99e Initial load
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parents:
diff changeset
667 int op = (f30 << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
668 (f29 << 29) |
a61af66fc99e Initial load
duke
parents:
diff changeset
669 (f25 << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
670 (f22 << 22) |
a61af66fc99e Initial load
duke
parents:
diff changeset
671 (f20 << 20) |
a61af66fc99e Initial load
duke
parents:
diff changeset
672 (f19 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
673 (f0 << 0);
a61af66fc99e Initial load
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parents:
diff changeset
674 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
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parents:
diff changeset
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
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parents:
diff changeset
676 }
a61af66fc99e Initial load
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parents:
diff changeset
677
a61af66fc99e Initial load
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parents:
diff changeset
678 // Standard Sparc opcode form2 field breakdown
a61af66fc99e Initial load
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parents:
diff changeset
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
a61af66fc99e Initial load
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parents:
diff changeset
680 f0 >>= 10; // Drop 10 bits
a61af66fc99e Initial load
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parents:
diff changeset
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
a61af66fc99e Initial load
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parents:
diff changeset
682 int op = (f30 << 30) |
a61af66fc99e Initial load
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parents:
diff changeset
683 (f25 << 25) |
a61af66fc99e Initial load
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parents:
diff changeset
684 (f22 << 22) |
a61af66fc99e Initial load
duke
parents:
diff changeset
685 (f0 << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
686 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
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parents:
diff changeset
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
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parents:
diff changeset
688 }
a61af66fc99e Initial load
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parents:
diff changeset
689
a61af66fc99e Initial load
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parents:
diff changeset
690 // Standard Sparc opcode form3 field breakdown
a61af66fc99e Initial load
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parents:
diff changeset
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
692 int op = (f30 << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
693 (f25 << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
694 (f19 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
695 (f14 << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
696 (f5 << 5) |
a61af66fc99e Initial load
duke
parents:
diff changeset
697 (f0 << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
698 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
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parents:
diff changeset
700 }
a61af66fc99e Initial load
duke
parents:
diff changeset
701
a61af66fc99e Initial load
duke
parents:
diff changeset
702 // Standard Sparc opcode form3 field breakdown
a61af66fc99e Initial load
duke
parents:
diff changeset
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
704 simm13 &= (1<<13)-1; // Mask to 13 bits
a61af66fc99e Initial load
duke
parents:
diff changeset
705 int op = (f30 << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
706 (f25 << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
707 (f19 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
708 (f14 << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
709 (1 << 13) | // bit to indicate immediate-mode
a61af66fc99e Initial load
duke
parents:
diff changeset
710 (simm13<<0);
a61af66fc99e Initial load
duke
parents:
diff changeset
711 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
713 }
a61af66fc99e Initial load
duke
parents:
diff changeset
714
a61af66fc99e Initial load
duke
parents:
diff changeset
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
716 simm10 &= (1<<10)-1; // Mask to 10 bits
a61af66fc99e Initial load
duke
parents:
diff changeset
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
a61af66fc99e Initial load
duke
parents:
diff changeset
718 }
a61af66fc99e Initial load
duke
parents:
diff changeset
719
a61af66fc99e Initial load
duke
parents:
diff changeset
720 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
721 // Helper function for VerifyOops in emit_form3_mem_reg
a61af66fc99e Initial load
duke
parents:
diff changeset
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
a61af66fc99e Initial load
duke
parents:
diff changeset
723 warning("VerifyOops encountered unexpected instruction:");
a61af66fc99e Initial load
duke
parents:
diff changeset
724 n->dump(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
a61af66fc99e Initial load
duke
parents:
diff changeset
726 }
a61af66fc99e Initial load
duke
parents:
diff changeset
727 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
728
a61af66fc99e Initial load
duke
parents:
diff changeset
729
a61af66fc99e Initial load
duke
parents:
diff changeset
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
a61af66fc99e Initial load
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parents:
diff changeset
731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
a61af66fc99e Initial load
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parents:
diff changeset
732
a61af66fc99e Initial load
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parents:
diff changeset
733 #ifdef ASSERT
a61af66fc99e Initial load
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parents:
diff changeset
734 // The following code implements the +VerifyOops feature.
a61af66fc99e Initial load
duke
parents:
diff changeset
735 // It verifies oop values which are loaded into or stored out of
a61af66fc99e Initial load
duke
parents:
diff changeset
736 // the current method activation. +VerifyOops complements techniques
a61af66fc99e Initial load
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parents:
diff changeset
737 // like ScavengeALot, because it eagerly inspects oops in transit,
a61af66fc99e Initial load
duke
parents:
diff changeset
738 // as they enter or leave the stack, as opposed to ScavengeALot,
a61af66fc99e Initial load
duke
parents:
diff changeset
739 // which inspects oops "at rest", in the stack or heap, at safepoints.
a61af66fc99e Initial load
duke
parents:
diff changeset
740 // For this reason, +VerifyOops can sometimes detect bugs very close
a61af66fc99e Initial load
duke
parents:
diff changeset
741 // to their point of creation. It can also serve as a cross-check
a61af66fc99e Initial load
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parents:
diff changeset
742 // on the validity of oop maps, when used toegether with ScavengeALot.
a61af66fc99e Initial load
duke
parents:
diff changeset
743
a61af66fc99e Initial load
duke
parents:
diff changeset
744 // It would be good to verify oops at other points, especially
a61af66fc99e Initial load
duke
parents:
diff changeset
745 // when an oop is used as a base pointer for a load or store.
a61af66fc99e Initial load
duke
parents:
diff changeset
746 // This is presently difficult, because it is hard to know when
a61af66fc99e Initial load
duke
parents:
diff changeset
747 // a base address is biased or not. (If we had such information,
a61af66fc99e Initial load
duke
parents:
diff changeset
748 // it would be easy and useful to make a two-argument version of
a61af66fc99e Initial load
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parents:
diff changeset
749 // verify_oop which unbiases the base, and performs verification.)
a61af66fc99e Initial load
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parents:
diff changeset
750
a61af66fc99e Initial load
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parents:
diff changeset
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
a61af66fc99e Initial load
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parents:
diff changeset
752 bool is_verified_oop_base = false;
a61af66fc99e Initial load
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parents:
diff changeset
753 bool is_verified_oop_load = false;
a61af66fc99e Initial load
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parents:
diff changeset
754 bool is_verified_oop_store = false;
a61af66fc99e Initial load
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parents:
diff changeset
755 int tmp_enc = -1;
a61af66fc99e Initial load
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parents:
diff changeset
756 if (VerifyOops && src1_enc != R_SP_enc) {
a61af66fc99e Initial load
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parents:
diff changeset
757 // classify the op, mainly for an assert check
a61af66fc99e Initial load
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parents:
diff changeset
758 int st_op = 0, ld_op = 0;
a61af66fc99e Initial load
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parents:
diff changeset
759 switch (primary) {
a61af66fc99e Initial load
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parents:
diff changeset
760 case Assembler::stb_op3: st_op = Op_StoreB; break;
a61af66fc99e Initial load
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parents:
diff changeset
761 case Assembler::sth_op3: st_op = Op_StoreC; break;
a61af66fc99e Initial load
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parents:
diff changeset
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
a61af66fc99e Initial load
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parents:
diff changeset
763 case Assembler::stw_op3: st_op = Op_StoreI; break;
a61af66fc99e Initial load
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parents:
diff changeset
764 case Assembler::std_op3: st_op = Op_StoreL; break;
a61af66fc99e Initial load
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parents:
diff changeset
765 case Assembler::stf_op3: st_op = Op_StoreF; break;
a61af66fc99e Initial load
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parents:
diff changeset
766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
a61af66fc99e Initial load
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parents:
diff changeset
767
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parents:
diff changeset
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 551
diff changeset
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
0
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parents:
diff changeset
770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
a61af66fc99e Initial load
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parents:
diff changeset
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
a61af66fc99e Initial load
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parents:
diff changeset
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
a61af66fc99e Initial load
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parents:
diff changeset
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
a61af66fc99e Initial load
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parents:
diff changeset
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
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parents:
diff changeset
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
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parents:
diff changeset
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
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parents:
diff changeset
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
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parents:
diff changeset
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
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parents:
diff changeset
779
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parents:
diff changeset
780 default: ShouldNotReachHere();
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parents:
diff changeset
781 }
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duke
parents:
diff changeset
782 if (tertiary == REGP_OP) {
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parents:
diff changeset
783 if (st_op == Op_StoreI) st_op = Op_StoreP;
a61af66fc99e Initial load
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parents:
diff changeset
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
a61af66fc99e Initial load
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parents:
diff changeset
785 else ShouldNotReachHere();
a61af66fc99e Initial load
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parents:
diff changeset
786 if (st_op) {
a61af66fc99e Initial load
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parents:
diff changeset
787 // a store
a61af66fc99e Initial load
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parents:
diff changeset
788 // inputs are (0:control, 1:memory, 2:address, 3:value)
a61af66fc99e Initial load
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parents:
diff changeset
789 Node* n2 = n->in(3);
a61af66fc99e Initial load
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parents:
diff changeset
790 if (n2 != NULL) {
a61af66fc99e Initial load
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parents:
diff changeset
791 const Type* t = n2->bottom_type();
a61af66fc99e Initial load
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parents:
diff changeset
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
a61af66fc99e Initial load
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parents:
diff changeset
793 }
a61af66fc99e Initial load
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parents:
diff changeset
794 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
795 // a load
a61af66fc99e Initial load
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parents:
diff changeset
796 const Type* t = n->bottom_type();
a61af66fc99e Initial load
duke
parents:
diff changeset
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
a61af66fc99e Initial load
duke
parents:
diff changeset
798 }
a61af66fc99e Initial load
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parents:
diff changeset
799 }
a61af66fc99e Initial load
duke
parents:
diff changeset
800
a61af66fc99e Initial load
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parents:
diff changeset
801 if (ld_op) {
a61af66fc99e Initial load
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parents:
diff changeset
802 // a Load
a61af66fc99e Initial load
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parents:
diff changeset
803 // inputs are (0:control, 1:memory, 2:address)
a61af66fc99e Initial load
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parents:
diff changeset
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
a61af66fc99e Initial load
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parents:
diff changeset
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
a61af66fc99e Initial load
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parents:
diff changeset
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
a61af66fc99e Initial load
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parents:
diff changeset
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
a61af66fc99e Initial load
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parents:
diff changeset
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
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parents:
diff changeset
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
818 !(n->rule() == loadUB_rule)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
820 }
a61af66fc99e Initial load
duke
parents:
diff changeset
821 } else if (st_op) {
a61af66fc99e Initial load
duke
parents:
diff changeset
822 // a Store
a61af66fc99e Initial load
duke
parents:
diff changeset
823 // inputs are (0:control, 1:memory, 2:address, 3:value)
a61af66fc99e Initial load
duke
parents:
diff changeset
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
a61af66fc99e Initial load
duke
parents:
diff changeset
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
831 }
a61af66fc99e Initial load
duke
parents:
diff changeset
832 }
a61af66fc99e Initial load
duke
parents:
diff changeset
833
a61af66fc99e Initial load
duke
parents:
diff changeset
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
835 Node* addr = n->in(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
a61af66fc99e Initial load
duke
parents:
diff changeset
838 if (atype != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
839 intptr_t offset = get_offset_from_base(n, atype, disp32);
a61af66fc99e Initial load
duke
parents:
diff changeset
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
a61af66fc99e Initial load
duke
parents:
diff changeset
841 if (offset != offset_2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
842 get_offset_from_base(n, atype, disp32);
a61af66fc99e Initial load
duke
parents:
diff changeset
843 get_offset_from_base_2(n, atype, disp32);
a61af66fc99e Initial load
duke
parents:
diff changeset
844 }
a61af66fc99e Initial load
duke
parents:
diff changeset
845 assert(offset == offset_2, "different offsets");
a61af66fc99e Initial load
duke
parents:
diff changeset
846 if (offset == disp32) {
a61af66fc99e Initial load
duke
parents:
diff changeset
847 // we now know that src1 is a true oop pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
848 is_verified_oop_base = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
a61af66fc99e Initial load
duke
parents:
diff changeset
850 if( primary == Assembler::ldd_op3 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
851 is_verified_oop_base = false; // Cannot 'ldd' into O7
a61af66fc99e Initial load
duke
parents:
diff changeset
852 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
853 tmp_enc = dst_enc;
a61af66fc99e Initial load
duke
parents:
diff changeset
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
a61af66fc99e Initial load
duke
parents:
diff changeset
855 assert(src1_enc != dst_enc, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
856 }
a61af66fc99e Initial load
duke
parents:
diff changeset
857 }
a61af66fc99e Initial load
duke
parents:
diff changeset
858 }
a61af66fc99e Initial load
duke
parents:
diff changeset
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
a61af66fc99e Initial load
duke
parents:
diff changeset
860 || offset == oopDesc::mark_offset_in_bytes())) {
a61af66fc99e Initial load
duke
parents:
diff changeset
861 // loading the mark should not be allowed either, but
a61af66fc99e Initial load
duke
parents:
diff changeset
862 // we don't check this since it conflicts with InlineObjectHash
a61af66fc99e Initial load
duke
parents:
diff changeset
863 // usage of LoadINode to get the mark. We could keep the
a61af66fc99e Initial load
duke
parents:
diff changeset
864 // check if we create a new LoadMarkNode
a61af66fc99e Initial load
duke
parents:
diff changeset
865 // but do not verify the object before its header is initialized
a61af66fc99e Initial load
duke
parents:
diff changeset
866 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
867 }
a61af66fc99e Initial load
duke
parents:
diff changeset
868 }
a61af66fc99e Initial load
duke
parents:
diff changeset
869 }
a61af66fc99e Initial load
duke
parents:
diff changeset
870 }
a61af66fc99e Initial load
duke
parents:
diff changeset
871 }
a61af66fc99e Initial load
duke
parents:
diff changeset
872 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
873
a61af66fc99e Initial load
duke
parents:
diff changeset
874 uint instr;
a61af66fc99e Initial load
duke
parents:
diff changeset
875 instr = (Assembler::ldst_op << 30)
a61af66fc99e Initial load
duke
parents:
diff changeset
876 | (dst_enc << 25)
a61af66fc99e Initial load
duke
parents:
diff changeset
877 | (primary << 19)
a61af66fc99e Initial load
duke
parents:
diff changeset
878 | (src1_enc << 14);
a61af66fc99e Initial load
duke
parents:
diff changeset
879
a61af66fc99e Initial load
duke
parents:
diff changeset
880 uint index = src2_enc;
a61af66fc99e Initial load
duke
parents:
diff changeset
881 int disp = disp32;
a61af66fc99e Initial load
duke
parents:
diff changeset
882
a61af66fc99e Initial load
duke
parents:
diff changeset
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
a61af66fc99e Initial load
duke
parents:
diff changeset
884 disp += STACK_BIAS;
a61af66fc99e Initial load
duke
parents:
diff changeset
885
a61af66fc99e Initial load
duke
parents:
diff changeset
886 // We should have a compiler bailout here rather than a guarantee.
a61af66fc99e Initial load
duke
parents:
diff changeset
887 // Better yet would be some mechanism to handle variable-size matches correctly.
a61af66fc99e Initial load
duke
parents:
diff changeset
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
a61af66fc99e Initial load
duke
parents:
diff changeset
889
a61af66fc99e Initial load
duke
parents:
diff changeset
890 if( disp == 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
891 // use reg-reg form
a61af66fc99e Initial load
duke
parents:
diff changeset
892 // bit 13 is already zero
a61af66fc99e Initial load
duke
parents:
diff changeset
893 instr |= index;
a61af66fc99e Initial load
duke
parents:
diff changeset
894 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
895 // use reg-imm form
a61af66fc99e Initial load
duke
parents:
diff changeset
896 instr |= 0x00002000; // set bit 13 to one
a61af66fc99e Initial load
duke
parents:
diff changeset
897 instr |= disp & 0x1FFF;
a61af66fc99e Initial load
duke
parents:
diff changeset
898 }
a61af66fc99e Initial load
duke
parents:
diff changeset
899
a61af66fc99e Initial load
duke
parents:
diff changeset
900 uint *code = (uint*)cbuf.code_end();
a61af66fc99e Initial load
duke
parents:
diff changeset
901 *code = instr;
a61af66fc99e Initial load
duke
parents:
diff changeset
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
903
a61af66fc99e Initial load
duke
parents:
diff changeset
904 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
905 {
a61af66fc99e Initial load
duke
parents:
diff changeset
906 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
907 if (is_verified_oop_base) {
a61af66fc99e Initial load
duke
parents:
diff changeset
908 __ verify_oop(reg_to_register_object(src1_enc));
a61af66fc99e Initial load
duke
parents:
diff changeset
909 }
a61af66fc99e Initial load
duke
parents:
diff changeset
910 if (is_verified_oop_store) {
a61af66fc99e Initial load
duke
parents:
diff changeset
911 __ verify_oop(reg_to_register_object(dst_enc));
a61af66fc99e Initial load
duke
parents:
diff changeset
912 }
a61af66fc99e Initial load
duke
parents:
diff changeset
913 if (tmp_enc != -1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
914 __ mov(O7, reg_to_register_object(tmp_enc));
a61af66fc99e Initial load
duke
parents:
diff changeset
915 }
a61af66fc99e Initial load
duke
parents:
diff changeset
916 if (is_verified_oop_load) {
a61af66fc99e Initial load
duke
parents:
diff changeset
917 __ verify_oop(reg_to_register_object(dst_enc));
a61af66fc99e Initial load
duke
parents:
diff changeset
918 }
a61af66fc99e Initial load
duke
parents:
diff changeset
919 }
a61af66fc99e Initial load
duke
parents:
diff changeset
920 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
921 }
a61af66fc99e Initial load
duke
parents:
diff changeset
922
a61af66fc99e Initial load
duke
parents:
diff changeset
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
a61af66fc99e Initial load
duke
parents:
diff changeset
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
a61af66fc99e Initial load
duke
parents:
diff changeset
925
a61af66fc99e Initial load
duke
parents:
diff changeset
926 uint instr;
a61af66fc99e Initial load
duke
parents:
diff changeset
927 instr = (Assembler::ldst_op << 30)
a61af66fc99e Initial load
duke
parents:
diff changeset
928 | (dst_enc << 25)
a61af66fc99e Initial load
duke
parents:
diff changeset
929 | (primary << 19)
a61af66fc99e Initial load
duke
parents:
diff changeset
930 | (src1_enc << 14);
a61af66fc99e Initial load
duke
parents:
diff changeset
931
a61af66fc99e Initial load
duke
parents:
diff changeset
932 int disp = disp32;
a61af66fc99e Initial load
duke
parents:
diff changeset
933 int index = src2_enc;
a61af66fc99e Initial load
duke
parents:
diff changeset
934
a61af66fc99e Initial load
duke
parents:
diff changeset
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
a61af66fc99e Initial load
duke
parents:
diff changeset
936 disp += STACK_BIAS;
a61af66fc99e Initial load
duke
parents:
diff changeset
937
a61af66fc99e Initial load
duke
parents:
diff changeset
938 // We should have a compiler bailout here rather than a guarantee.
a61af66fc99e Initial load
duke
parents:
diff changeset
939 // Better yet would be some mechanism to handle variable-size matches correctly.
a61af66fc99e Initial load
duke
parents:
diff changeset
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
a61af66fc99e Initial load
duke
parents:
diff changeset
941
a61af66fc99e Initial load
duke
parents:
diff changeset
942 if( disp != 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
943 // use reg-reg form
a61af66fc99e Initial load
duke
parents:
diff changeset
944 // set src2=R_O7 contains offset
a61af66fc99e Initial load
duke
parents:
diff changeset
945 index = R_O7_enc;
a61af66fc99e Initial load
duke
parents:
diff changeset
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
947 }
a61af66fc99e Initial load
duke
parents:
diff changeset
948 instr |= (asi << 5);
a61af66fc99e Initial load
duke
parents:
diff changeset
949 instr |= index;
a61af66fc99e Initial load
duke
parents:
diff changeset
950 uint *code = (uint*)cbuf.code_end();
a61af66fc99e Initial load
duke
parents:
diff changeset
951 *code = instr;
a61af66fc99e Initial load
duke
parents:
diff changeset
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
953 }
a61af66fc99e Initial load
duke
parents:
diff changeset
954
a61af66fc99e Initial load
duke
parents:
diff changeset
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
a61af66fc99e Initial load
duke
parents:
diff changeset
956 // The method which records debug information at every safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
957 // expects the call to be the first instruction in the snippet as
a61af66fc99e Initial load
duke
parents:
diff changeset
958 // it creates a PcDesc structure which tracks the offset of a call
a61af66fc99e Initial load
duke
parents:
diff changeset
959 // from the start of the codeBlob. This offset is computed as
a61af66fc99e Initial load
duke
parents:
diff changeset
960 // code_end() - code_begin() of the code which has been emitted
a61af66fc99e Initial load
duke
parents:
diff changeset
961 // so far.
a61af66fc99e Initial load
duke
parents:
diff changeset
962 // In this particular case we have skirted around the problem by
a61af66fc99e Initial load
duke
parents:
diff changeset
963 // putting the "mov" instruction in the delay slot but the problem
a61af66fc99e Initial load
duke
parents:
diff changeset
964 // may bite us again at some other point and a cleaner/generic
a61af66fc99e Initial load
duke
parents:
diff changeset
965 // solution using relocations would be needed.
a61af66fc99e Initial load
duke
parents:
diff changeset
966 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
967 __ set_inst_mark();
a61af66fc99e Initial load
duke
parents:
diff changeset
968
a61af66fc99e Initial load
duke
parents:
diff changeset
969 // We flush the current window just so that there is a valid stack copy
a61af66fc99e Initial load
duke
parents:
diff changeset
970 // the fact that the current window becomes active again instantly is
a61af66fc99e Initial load
duke
parents:
diff changeset
971 // not a problem there is nothing live in it.
a61af66fc99e Initial load
duke
parents:
diff changeset
972
a61af66fc99e Initial load
duke
parents:
diff changeset
973 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
974 int startpos = __ offset();
a61af66fc99e Initial load
duke
parents:
diff changeset
975 #endif /* ASSERT */
a61af66fc99e Initial load
duke
parents:
diff changeset
976
a61af66fc99e Initial load
duke
parents:
diff changeset
977 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
978 // Calls to the runtime or native may not be reachable from compiled code,
a61af66fc99e Initial load
duke
parents:
diff changeset
979 // so we generate the far call sequence on 64 bit sparc.
a61af66fc99e Initial load
duke
parents:
diff changeset
980 // This code sequence is relocatable to any address, even on LP64.
a61af66fc99e Initial load
duke
parents:
diff changeset
981 if ( force_far_call ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
982 __ relocate(rtype);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
983 AddressLiteral dest(entry_point);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
984 __ jumpl_to(dest, O7, O7);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
985 }
a61af66fc99e Initial load
duke
parents:
diff changeset
986 else
a61af66fc99e Initial load
duke
parents:
diff changeset
987 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
988 {
a61af66fc99e Initial load
duke
parents:
diff changeset
989 __ call((address)entry_point, rtype);
a61af66fc99e Initial load
duke
parents:
diff changeset
990 }
a61af66fc99e Initial load
duke
parents:
diff changeset
991
a61af66fc99e Initial load
duke
parents:
diff changeset
992 if (preserve_g2) __ delayed()->mov(G2, L7);
a61af66fc99e Initial load
duke
parents:
diff changeset
993 else __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
994
a61af66fc99e Initial load
duke
parents:
diff changeset
995 if (preserve_g2) __ mov(L7, G2);
a61af66fc99e Initial load
duke
parents:
diff changeset
996
a61af66fc99e Initial load
duke
parents:
diff changeset
997 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
999 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1000 // Trash argument dump slots.
a61af66fc99e Initial load
duke
parents:
diff changeset
1001 __ set(0xb0b8ac0db0b8ac0d, G1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1002 __ mov(G1, G5);
a61af66fc99e Initial load
duke
parents:
diff changeset
1003 __ stx(G1, SP, STACK_BIAS + 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
1004 __ stx(G1, SP, STACK_BIAS + 0x88);
a61af66fc99e Initial load
duke
parents:
diff changeset
1005 __ stx(G1, SP, STACK_BIAS + 0x90);
a61af66fc99e Initial load
duke
parents:
diff changeset
1006 __ stx(G1, SP, STACK_BIAS + 0x98);
a61af66fc99e Initial load
duke
parents:
diff changeset
1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
a61af66fc99e Initial load
duke
parents:
diff changeset
1009 #else // _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1010 // this is also a native call, so smash the first 7 stack locations,
a61af66fc99e Initial load
duke
parents:
diff changeset
1011 // and the various registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1012
a61af66fc99e Initial load
duke
parents:
diff changeset
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
a61af66fc99e Initial load
duke
parents:
diff changeset
1014 // while [SP+0x44..0x58] are the argument dump slots.
a61af66fc99e Initial load
duke
parents:
diff changeset
1015 __ set((intptr_t)0xbaadf00d, G1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1016 __ mov(G1, G5);
a61af66fc99e Initial load
duke
parents:
diff changeset
1017 __ sllx(G1, 32, G1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1018 __ or3(G1, G5, G1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1019 __ mov(G1, G5);
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 __ stx(G1, SP, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
1021 __ stx(G1, SP, 0x48);
a61af66fc99e Initial load
duke
parents:
diff changeset
1022 __ stx(G1, SP, 0x50);
a61af66fc99e Initial load
duke
parents:
diff changeset
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
a61af66fc99e Initial load
duke
parents:
diff changeset
1024 #endif // _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1025 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1026 #endif /*ASSERT*/
a61af66fc99e Initial load
duke
parents:
diff changeset
1027 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1028
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1030 // REQUIRED FUNCTIONALITY for encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
1031 void emit_lo(CodeBuffer &cbuf, int val) { }
a61af66fc99e Initial load
duke
parents:
diff changeset
1032 void emit_hi(CodeBuffer &cbuf, int val) { }
a61af66fc99e Initial load
duke
parents:
diff changeset
1033
a61af66fc99e Initial load
duke
parents:
diff changeset
1034
a61af66fc99e Initial load
duke
parents:
diff changeset
1035 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1036
a61af66fc99e Initial load
duke
parents:
diff changeset
1037 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1039 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
1040
a61af66fc99e Initial load
duke
parents:
diff changeset
1041 for (int i = 0; i < OptoPrologueNops; i++) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1042 st->print_cr("NOP"); st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1043 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1044
a61af66fc99e Initial load
duke
parents:
diff changeset
1045 if( VerifyThread ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1046 st->print_cr("Verify_Thread"); st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1047 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1048
a61af66fc99e Initial load
duke
parents:
diff changeset
1049 size_t framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
1050
a61af66fc99e Initial load
duke
parents:
diff changeset
1051 // Calls to C2R adapters often do not accept exceptional returns.
a61af66fc99e Initial load
duke
parents:
diff changeset
1052 // We require that their callers must bang for them. But be careful, because
a61af66fc99e Initial load
duke
parents:
diff changeset
1053 // some VM calls (such as call site linkage) can use several kilobytes of
a61af66fc99e Initial load
duke
parents:
diff changeset
1054 // stack. But the stack safety zone should account for that.
a61af66fc99e Initial load
duke
parents:
diff changeset
1055 // See bugs 4446381, 4468289, 4497237.
a61af66fc99e Initial load
duke
parents:
diff changeset
1056 if (C->need_stack_bang(framesize)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1057 st->print_cr("! stack bang"); st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1058 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1059
a61af66fc99e Initial load
duke
parents:
diff changeset
1060 if (Assembler::is_simm13(-framesize)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
1062 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1065 st->print ("SAVE R_SP,R_G3,R_SP");
a61af66fc99e Initial load
duke
parents:
diff changeset
1066 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1067
a61af66fc99e Initial load
duke
parents:
diff changeset
1068 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1069 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1070
a61af66fc99e Initial load
duke
parents:
diff changeset
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1072 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
1073 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1074
a61af66fc99e Initial load
duke
parents:
diff changeset
1075 for (int i = 0; i < OptoPrologueNops; i++) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 __ nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1078
a61af66fc99e Initial load
duke
parents:
diff changeset
1079 __ verify_thread();
a61af66fc99e Initial load
duke
parents:
diff changeset
1080
a61af66fc99e Initial load
duke
parents:
diff changeset
1081 size_t framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area");
a61af66fc99e Initial load
duke
parents:
diff changeset
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
a61af66fc99e Initial load
duke
parents:
diff changeset
1084
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 // Calls to C2R adapters often do not accept exceptional returns.
a61af66fc99e Initial load
duke
parents:
diff changeset
1086 // We require that their callers must bang for them. But be careful, because
a61af66fc99e Initial load
duke
parents:
diff changeset
1087 // some VM calls (such as call site linkage) can use several kilobytes of
a61af66fc99e Initial load
duke
parents:
diff changeset
1088 // stack. But the stack safety zone should account for that.
a61af66fc99e Initial load
duke
parents:
diff changeset
1089 // See bugs 4446381, 4468289, 4497237.
a61af66fc99e Initial load
duke
parents:
diff changeset
1090 if (C->need_stack_bang(framesize)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1091 __ generate_stack_overflow_check(framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
1092 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1093
a61af66fc99e Initial load
duke
parents:
diff changeset
1094 if (Assembler::is_simm13(-framesize)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1095 __ save(SP, -framesize, SP);
a61af66fc99e Initial load
duke
parents:
diff changeset
1096 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1097 __ sethi(-framesize & ~0x3ff, G3);
a61af66fc99e Initial load
duke
parents:
diff changeset
1098 __ add(G3, -framesize & 0x3ff, G3);
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 __ save(SP, G3, SP);
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 C->set_frame_complete( __ offset() );
a61af66fc99e Initial load
duke
parents:
diff changeset
1102 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1103
a61af66fc99e Initial load
duke
parents:
diff changeset
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1105 return MachNode::size(ra_);
a61af66fc99e Initial load
duke
parents:
diff changeset
1106 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1107
a61af66fc99e Initial load
duke
parents:
diff changeset
1108 int MachPrologNode::reloc() const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1109 return 10; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
1110 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1111
a61af66fc99e Initial load
duke
parents:
diff changeset
1112 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1113 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1115 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
1116
a61af66fc99e Initial load
duke
parents:
diff changeset
1117 if( do_polling() && ra_->C->is_method_compilation() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1119 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1121 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1123 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1125
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 if( do_polling() )
a61af66fc99e Initial load
duke
parents:
diff changeset
1127 st->print("RET\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1128
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 st->print("RESTORE");
a61af66fc99e Initial load
duke
parents:
diff changeset
1130 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1131 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1132
a61af66fc99e Initial load
duke
parents:
diff changeset
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
1136
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 __ verify_thread();
a61af66fc99e Initial load
duke
parents:
diff changeset
1138
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 // If this does safepoint polling, then do it here
a61af66fc99e Initial load
duke
parents:
diff changeset
1140 if( do_polling() && ra_->C->is_method_compilation() ) {
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1141 AddressLiteral polling_page(os::get_polling_page());
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1142 __ sethi(polling_page, L0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1143 __ relocate(relocInfo::poll_return_type);
a61af66fc99e Initial load
duke
parents:
diff changeset
1144 __ ld_ptr( L0, 0, G0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1146
a61af66fc99e Initial load
duke
parents:
diff changeset
1147 // If this is a return, then stuff the restore in the delay slot
a61af66fc99e Initial load
duke
parents:
diff changeset
1148 if( do_polling() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1149 __ ret();
a61af66fc99e Initial load
duke
parents:
diff changeset
1150 __ delayed()->restore();
a61af66fc99e Initial load
duke
parents:
diff changeset
1151 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1152 __ restore();
a61af66fc99e Initial load
duke
parents:
diff changeset
1153 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1154 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1155
a61af66fc99e Initial load
duke
parents:
diff changeset
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1157 return MachNode::size(ra_);
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1159
a61af66fc99e Initial load
duke
parents:
diff changeset
1160 int MachEpilogNode::reloc() const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1161 return 16; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1163
a61af66fc99e Initial load
duke
parents:
diff changeset
1164 const Pipeline * MachEpilogNode::pipeline() const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1165 return MachNode::pipeline_class();
a61af66fc99e Initial load
duke
parents:
diff changeset
1166 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1167
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 int MachEpilogNode::safepoint_offset() const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 assert( do_polling(), "no return for this epilog node");
a61af66fc99e Initial load
duke
parents:
diff changeset
1170 return MacroAssembler::size_of_sethi(os::get_polling_page());
a61af66fc99e Initial load
duke
parents:
diff changeset
1171 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1172
a61af66fc99e Initial load
duke
parents:
diff changeset
1173 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1174
a61af66fc99e Initial load
duke
parents:
diff changeset
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
a61af66fc99e Initial load
duke
parents:
diff changeset
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack };
a61af66fc99e Initial load
duke
parents:
diff changeset
1177 static enum RC rc_class( OptoReg::Name reg ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1178 if( !OptoReg::is_valid(reg) ) return rc_bad;
a61af66fc99e Initial load
duke
parents:
diff changeset
1179 if (OptoReg::is_stack(reg)) return rc_stack;
a61af66fc99e Initial load
duke
parents:
diff changeset
1180 VMReg r = OptoReg::as_VMReg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1181 if (r->is_Register()) return rc_int;
a61af66fc99e Initial load
duke
parents:
diff changeset
1182 assert(r->is_FloatRegister(), "must be");
a61af66fc99e Initial load
duke
parents:
diff changeset
1183 return rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
1184 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1185
a61af66fc99e Initial load
duke
parents:
diff changeset
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1187 if( cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1188 // Better yet would be some mechanism to handle variable-size matches correctly
a61af66fc99e Initial load
duke
parents:
diff changeset
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
a61af66fc99e Initial load
duke
parents:
diff changeset
1191 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1193 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1195 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1196 else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1202 return size+4;
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1204
a61af66fc99e Initial load
duke
parents:
diff changeset
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
a61af66fc99e Initial load
duke
parents:
diff changeset
1207 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1208 else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1212 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 return size+4;
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1215
a61af66fc99e Initial load
duke
parents:
diff changeset
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1217 PhaseRegAlloc *ra_,
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 bool do_size,
a61af66fc99e Initial load
duke
parents:
diff changeset
1219 outputStream* st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1220 // Get registers to move
a61af66fc99e Initial load
duke
parents:
diff changeset
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 OptoReg::Name dst_second = ra_->get_reg_second(this );
a61af66fc99e Initial load
duke
parents:
diff changeset
1224 OptoReg::Name dst_first = ra_->get_reg_first(this );
a61af66fc99e Initial load
duke
parents:
diff changeset
1225
a61af66fc99e Initial load
duke
parents:
diff changeset
1226 enum RC src_second_rc = rc_class(src_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
1227 enum RC src_first_rc = rc_class(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1228 enum RC dst_second_rc = rc_class(dst_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 enum RC dst_first_rc = rc_class(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1230
a61af66fc99e Initial load
duke
parents:
diff changeset
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1232
a61af66fc99e Initial load
duke
parents:
diff changeset
1233 // Generate spill code!
a61af66fc99e Initial load
duke
parents:
diff changeset
1234 int size = 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
1235
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 if( src_first == dst_first && src_second == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1237 return size; // Self copy, no move
a61af66fc99e Initial load
duke
parents:
diff changeset
1238
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 // --------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 // Check for mem-mem move. Load into unused float registers and fall into
a61af66fc99e Initial load
duke
parents:
diff changeset
1241 // the float-store case.
a61af66fc99e Initial load
duke
parents:
diff changeset
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1243 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1244 // Further check for aligned-adjacent pair, so we can use a double load
a61af66fc99e Initial load
duke
parents:
diff changeset
1245 if( (src_first&1)==0 && src_first+1 == src_second ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1246 src_second = OptoReg::Name(R_F31_num);
a61af66fc99e Initial load
duke
parents:
diff changeset
1247 src_second_rc = rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1249 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1251 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1252 src_first = OptoReg::Name(R_F30_num);
a61af66fc99e Initial load
duke
parents:
diff changeset
1253 src_first_rc = rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
1254 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1255
a61af66fc99e Initial load
duke
parents:
diff changeset
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1257 int offset = ra_->reg2offset(src_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1259 src_second = OptoReg::Name(R_F31_num);
a61af66fc99e Initial load
duke
parents:
diff changeset
1260 src_second_rc = rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
1261 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1262
a61af66fc99e Initial load
duke
parents:
diff changeset
1263 // --------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1264 // Check for float->int copy; requires a trip through memory
a61af66fc99e Initial load
duke
parents:
diff changeset
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1266 int offset = frame::register_save_words*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
1267 if( cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1272 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1273 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1274 else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1275 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1276 st->print( "SUB R_SP,16,R_SP\n");
a61af66fc99e Initial load
duke
parents:
diff changeset
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1279 st->print("\tADD R_SP,16,R_SP\n");
a61af66fc99e Initial load
duke
parents:
diff changeset
1280 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1281 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1282 size += 16;
a61af66fc99e Initial load
duke
parents:
diff changeset
1283 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1284
a61af66fc99e Initial load
duke
parents:
diff changeset
1285 // --------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
a61af66fc99e Initial load
duke
parents:
diff changeset
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the
a61af66fc99e Initial load
duke
parents:
diff changeset
1288 // hardware does the flop for me. Doubles are always aligned, so no problem
a61af66fc99e Initial load
duke
parents:
diff changeset
1289 // there. Misaligned sources only come from native-long-returns (handled
a61af66fc99e Initial load
duke
parents:
diff changeset
1290 // special below).
a61af66fc99e Initial load
duke
parents:
diff changeset
1291 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1292 if( src_first_rc == rc_int && // source is already big-endian
a61af66fc99e Initial load
duke
parents:
diff changeset
1293 src_second_rc != rc_bad && // 64-bit move
a61af66fc99e Initial load
duke
parents:
diff changeset
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
a61af66fc99e Initial load
duke
parents:
diff changeset
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1296 // Do the big-endian flop.
a61af66fc99e Initial load
duke
parents:
diff changeset
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
a61af66fc99e Initial load
duke
parents:
diff changeset
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
a61af66fc99e Initial load
duke
parents:
diff changeset
1299 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1300 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1301
a61af66fc99e Initial load
duke
parents:
diff changeset
1302 // --------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1303 // Check for integer reg-reg copy
a61af66fc99e Initial load
duke
parents:
diff changeset
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1305 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
a61af66fc99e Initial load
duke
parents:
diff changeset
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
a61af66fc99e Initial load
duke
parents:
diff changeset
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
a61af66fc99e Initial load
duke
parents:
diff changeset
1309 // operand contains the least significant word of the 64-bit value and vice versa.
a61af66fc99e Initial load
duke
parents:
diff changeset
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
a61af66fc99e Initial load
duke
parents:
diff changeset
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
a61af66fc99e Initial load
duke
parents:
diff changeset
1313 if( cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
a61af66fc99e Initial load
duke
parents:
diff changeset
1317 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1318 } else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1319 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
a61af66fc99e Initial load
duke
parents:
diff changeset
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
a61af66fc99e Initial load
duke
parents:
diff changeset
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
a61af66fc99e Initial load
duke
parents:
diff changeset
1323 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1324 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1325 return size+12;
a61af66fc99e Initial load
duke
parents:
diff changeset
1326 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1328 // returning a long value in I0/I1
a61af66fc99e Initial load
duke
parents:
diff changeset
1329 // a SpillCopy must be able to target a return instruction's reg_class
a61af66fc99e Initial load
duke
parents:
diff changeset
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
a61af66fc99e Initial load
duke
parents:
diff changeset
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
a61af66fc99e Initial load
duke
parents:
diff changeset
1332 // operand contains the least significant word of the 64-bit value and vice versa.
a61af66fc99e Initial load
duke
parents:
diff changeset
1333 OptoReg::Name tdest = dst_first;
a61af66fc99e Initial load
duke
parents:
diff changeset
1334
a61af66fc99e Initial load
duke
parents:
diff changeset
1335 if (src_first == dst_first) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1336 tdest = OptoReg::Name(R_O7_num);
a61af66fc99e Initial load
duke
parents:
diff changeset
1337 size += 4;
a61af66fc99e Initial load
duke
parents:
diff changeset
1338 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1339
a61af66fc99e Initial load
duke
parents:
diff changeset
1340 if( cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
a61af66fc99e Initial load
duke
parents:
diff changeset
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
a61af66fc99e Initial load
duke
parents:
diff changeset
1343 // ShrL_reg_imm6
a61af66fc99e Initial load
duke
parents:
diff changeset
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1345 // ShrR_reg_imm6 src, 0, dst
a61af66fc99e Initial load
duke
parents:
diff changeset
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1347 if (tdest != dst_first) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
a61af66fc99e Initial load
duke
parents:
diff changeset
1349 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1350 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1351 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1352 else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
a61af66fc99e Initial load
duke
parents:
diff changeset
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
a61af66fc99e Initial load
duke
parents:
diff changeset
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
a61af66fc99e Initial load
duke
parents:
diff changeset
1356 if (tdest != dst_first) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
a61af66fc99e Initial load
duke
parents:
diff changeset
1358 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1359 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1360 #endif // PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1361 return size+8;
a61af66fc99e Initial load
duke
parents:
diff changeset
1362 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1363 #endif // !_LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1364 // Else normal reg-reg copy
a61af66fc99e Initial load
duke
parents:
diff changeset
1365 assert( src_second != dst_first, "smashed second before evacuating it" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1368 // This moves an aligned adjacent pair.
a61af66fc99e Initial load
duke
parents:
diff changeset
1369 // See if we are done.
a61af66fc99e Initial load
duke
parents:
diff changeset
1370 if( src_first+1 == src_second && dst_first+1 == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1371 return size;
a61af66fc99e Initial load
duke
parents:
diff changeset
1372 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1373
a61af66fc99e Initial load
duke
parents:
diff changeset
1374 // Check for integer store
a61af66fc99e Initial load
duke
parents:
diff changeset
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1376 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1377 // Further check for aligned-adjacent pair, so we can use a double store
a61af66fc99e Initial load
duke
parents:
diff changeset
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1381 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1382
a61af66fc99e Initial load
duke
parents:
diff changeset
1383 // Check for integer load
a61af66fc99e Initial load
duke
parents:
diff changeset
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1385 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1386 // Further check for aligned-adjacent pair, so we can use a double load
a61af66fc99e Initial load
duke
parents:
diff changeset
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1390 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1391
a61af66fc99e Initial load
duke
parents:
diff changeset
1392 // Check for float reg-reg copy
a61af66fc99e Initial load
duke
parents:
diff changeset
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1394 // Further check for aligned-adjacent pair, so we can use a double move
a61af66fc99e Initial load
duke
parents:
diff changeset
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1398 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1399
a61af66fc99e Initial load
duke
parents:
diff changeset
1400 // Check for float store
a61af66fc99e Initial load
duke
parents:
diff changeset
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1402 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1403 // Further check for aligned-adjacent pair, so we can use a double store
a61af66fc99e Initial load
duke
parents:
diff changeset
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1407 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1408
a61af66fc99e Initial load
duke
parents:
diff changeset
1409 // Check for float load
a61af66fc99e Initial load
duke
parents:
diff changeset
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1411 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1412 // Further check for aligned-adjacent pair, so we can use a double load
a61af66fc99e Initial load
duke
parents:
diff changeset
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1416 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1417
a61af66fc99e Initial load
duke
parents:
diff changeset
1418 // --------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1419 // Check for hi bits still needing moving. Only happens for misaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
1420 // arguments to native calls.
a61af66fc99e Initial load
duke
parents:
diff changeset
1421 if( src_second == dst_second )
a61af66fc99e Initial load
duke
parents:
diff changeset
1422 return size; // Self copy; no move
a61af66fc99e Initial load
duke
parents:
diff changeset
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1424
a61af66fc99e Initial load
duke
parents:
diff changeset
1425 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1426 // In the LP64 build, all registers can be moved as aligned/adjacent
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
1427 // pairs, so there's never any need to move the high bits separately.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1428 // The 32-bit builds have to deal with the 32-bit ABI which can force
a61af66fc99e Initial load
duke
parents:
diff changeset
1429 // all sorts of silly alignment problems.
a61af66fc99e Initial load
duke
parents:
diff changeset
1430
a61af66fc99e Initial load
duke
parents:
diff changeset
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top
a61af66fc99e Initial load
duke
parents:
diff changeset
1432 // 32-bits of a 64-bit register, but are needed in low bits of another
a61af66fc99e Initial load
duke
parents:
diff changeset
1433 // register (else it's a hi-bits-to-hi-bits copy which should have
a61af66fc99e Initial load
duke
parents:
diff changeset
1434 // happened already as part of a 64-bit move)
a61af66fc99e Initial load
duke
parents:
diff changeset
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1438 // Shift src_second down to dst_second's low bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
1439 if( cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1441 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1442 } else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1443 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
a61af66fc99e Initial load
duke
parents:
diff changeset
1445 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1446 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1447 return size+4;
a61af66fc99e Initial load
duke
parents:
diff changeset
1448 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1449
a61af66fc99e Initial load
duke
parents:
diff changeset
1450 // Check for high word integer store. Must down-shift the hi bits
a61af66fc99e Initial load
duke
parents:
diff changeset
1451 // into a temp register, then fall into the case of storing int bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1453 // Shift src_second down to dst_second's low bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
1454 if( cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1456 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1457 } else if( !do_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1458 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
a61af66fc99e Initial load
duke
parents:
diff changeset
1460 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1461 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1462 size+=4;
a61af66fc99e Initial load
duke
parents:
diff changeset
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
a61af66fc99e Initial load
duke
parents:
diff changeset
1464 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1465
a61af66fc99e Initial load
duke
parents:
diff changeset
1466 // Check for high word integer load
a61af66fc99e Initial load
duke
parents:
diff changeset
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
a61af66fc99e Initial load
duke
parents:
diff changeset
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1469
a61af66fc99e Initial load
duke
parents:
diff changeset
1470 // Check for high word integer store
a61af66fc99e Initial load
duke
parents:
diff changeset
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
a61af66fc99e Initial load
duke
parents:
diff changeset
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1473
a61af66fc99e Initial load
duke
parents:
diff changeset
1474 // Check for high word float store
a61af66fc99e Initial load
duke
parents:
diff changeset
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
a61af66fc99e Initial load
duke
parents:
diff changeset
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1477
a61af66fc99e Initial load
duke
parents:
diff changeset
1478 #endif // !_LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1479
a61af66fc99e Initial load
duke
parents:
diff changeset
1480 Unimplemented();
a61af66fc99e Initial load
duke
parents:
diff changeset
1481 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1482
a61af66fc99e Initial load
duke
parents:
diff changeset
1483 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1485 implementation( NULL, ra_, false, st );
a61af66fc99e Initial load
duke
parents:
diff changeset
1486 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1487 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1488
a61af66fc99e Initial load
duke
parents:
diff changeset
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1490 implementation( &cbuf, ra_, false, NULL );
a61af66fc99e Initial load
duke
parents:
diff changeset
1491 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1492
a61af66fc99e Initial load
duke
parents:
diff changeset
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1494 return implementation( NULL, ra_, true, NULL );
a61af66fc99e Initial load
duke
parents:
diff changeset
1495 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1496
a61af66fc99e Initial load
duke
parents:
diff changeset
1497 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1498 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1501 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1502 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1503
a61af66fc99e Initial load
duke
parents:
diff changeset
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1505 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1506 for(int i = 0; i < _count; i += 1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1507 __ nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
1508 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1509 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1510
a61af66fc99e Initial load
duke
parents:
diff changeset
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1512 return 4 * _count;
a61af66fc99e Initial load
duke
parents:
diff changeset
1513 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1514
a61af66fc99e Initial load
duke
parents:
diff changeset
1515
a61af66fc99e Initial load
duke
parents:
diff changeset
1516 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1517 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1520 int reg = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1522 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1523 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1524
a61af66fc99e Initial load
duke
parents:
diff changeset
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1526 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
a61af66fc99e Initial load
duke
parents:
diff changeset
1528 int reg = ra_->get_encode(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1529
a61af66fc99e Initial load
duke
parents:
diff changeset
1530 if (Assembler::is_simm13(offset)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1531 __ add(SP, offset, reg_to_register_object(reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
1532 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1533 __ set(offset, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1534 __ add(SP, O7, reg_to_register_object(reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
1535 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1536 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1537
a61af66fc99e Initial load
duke
parents:
diff changeset
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
a61af66fc99e Initial load
duke
parents:
diff changeset
1540 assert(ra_ == ra_->C->regalloc(), "sanity");
a61af66fc99e Initial load
duke
parents:
diff changeset
1541 return ra_->C->scratch_emit_size(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1542 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1543
a61af66fc99e Initial load
duke
parents:
diff changeset
1544 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1545
a61af66fc99e Initial load
duke
parents:
diff changeset
1546 // emit call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1547 void emit_java_to_interp(CodeBuffer &cbuf ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1548
a61af66fc99e Initial load
duke
parents:
diff changeset
1549 // Stub is fixed up when the corresponding call is converted from calling
a61af66fc99e Initial load
duke
parents:
diff changeset
1550 // compiled code to calling interpreted code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1551 // set (empty), G5
a61af66fc99e Initial load
duke
parents:
diff changeset
1552 // jmp -1
a61af66fc99e Initial load
duke
parents:
diff changeset
1553
a61af66fc99e Initial load
duke
parents:
diff changeset
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section
a61af66fc99e Initial load
duke
parents:
diff changeset
1555
a61af66fc99e Initial load
duke
parents:
diff changeset
1556 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1557
a61af66fc99e Initial load
duke
parents:
diff changeset
1558 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1559 __ start_a_stub(Compile::MAX_stubs_size);
a61af66fc99e Initial load
duke
parents:
diff changeset
1560 if (base == NULL) return; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1561
a61af66fc99e Initial load
duke
parents:
diff changeset
1562 // static stub relocation stores the instruction address of the call
a61af66fc99e Initial load
duke
parents:
diff changeset
1563 __ relocate(static_stub_Relocation::spec(mark));
a61af66fc99e Initial load
duke
parents:
diff changeset
1564
a61af66fc99e Initial load
duke
parents:
diff changeset
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1566
a61af66fc99e Initial load
duke
parents:
diff changeset
1567 __ set_inst_mark();
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1568 AddressLiteral addrlit(-1);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1569 __ JUMP(addrlit, G3, 0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1570
a61af66fc99e Initial load
duke
parents:
diff changeset
1571 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
1572
a61af66fc99e Initial load
duke
parents:
diff changeset
1573 // Update current stubs pointer and restore code_end.
a61af66fc99e Initial load
duke
parents:
diff changeset
1574 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1575 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1576
a61af66fc99e Initial load
duke
parents:
diff changeset
1577 // size of call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1578 uint size_java_to_interp() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1579 // This doesn't need to be accurate but it must be larger or equal to
a61af66fc99e Initial load
duke
parents:
diff changeset
1580 // the real size of the stub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo;
a61af66fc99e Initial load
duke
parents:
diff changeset
1582 NativeJump::instruction_size + // sethi; jmp; nop
a61af66fc99e Initial load
duke
parents:
diff changeset
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1584 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1585 // relocation entries for call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1586 uint reloc_java_to_interp() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
a61af66fc99e Initial load
duke
parents:
diff changeset
1588 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1589
a61af66fc99e Initial load
duke
parents:
diff changeset
1590
a61af66fc99e Initial load
duke
parents:
diff changeset
1591 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1592 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1594 st->print_cr("\nUEP:");
a61af66fc99e Initial load
duke
parents:
diff changeset
1595 #ifdef _LP64
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1596 if (UseCompressedOops) {
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
1597 assert(Universe::heap() != NULL, "java heap should be initialized");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1599 st->print_cr("\tSLL R_G5,3,R_G5");
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
1600 if (Universe::narrow_oop_base() != NULL)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1602 } else {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1604 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1605 st->print_cr("\tCMP R_G5,R_G3" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
a61af66fc99e Initial load
duke
parents:
diff changeset
1607 #else // _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
a61af66fc99e Initial load
duke
parents:
diff changeset
1609 st->print_cr("\tCMP R_G5,R_G3" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
a61af66fc99e Initial load
duke
parents:
diff changeset
1611 #endif // _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1612 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1613 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1614
a61af66fc99e Initial load
duke
parents:
diff changeset
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1616 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1617 Label L;
a61af66fc99e Initial load
duke
parents:
diff changeset
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
a61af66fc99e Initial load
duke
parents:
diff changeset
1619 Register temp_reg = G3;
a61af66fc99e Initial load
duke
parents:
diff changeset
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1621
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
1622 // Load klass from receiver
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1623 __ load_klass(O0, temp_reg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1624 // Compare against expected klass
a61af66fc99e Initial load
duke
parents:
diff changeset
1625 __ cmp(temp_reg, G5_ic_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1626 // Branch to miss code, checks xcc or icc depending
a61af66fc99e Initial load
duke
parents:
diff changeset
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1628 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1629
a61af66fc99e Initial load
duke
parents:
diff changeset
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1631 return MachNode::size(ra_);
a61af66fc99e Initial load
duke
parents:
diff changeset
1632 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1633
a61af66fc99e Initial load
duke
parents:
diff changeset
1634
a61af66fc99e Initial load
duke
parents:
diff changeset
1635 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1636
a61af66fc99e Initial load
duke
parents:
diff changeset
1637 uint size_exception_handler() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1638 if (TraceJumps) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1639 return (400); // just a guess
a61af66fc99e Initial load
duke
parents:
diff changeset
1640 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop
a61af66fc99e Initial load
duke
parents:
diff changeset
1642 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1643
a61af66fc99e Initial load
duke
parents:
diff changeset
1644 uint size_deopt_handler() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1645 if (TraceJumps) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1646 return (400); // just a guess
a61af66fc99e Initial load
duke
parents:
diff changeset
1647 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
a61af66fc99e Initial load
duke
parents:
diff changeset
1649 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1650
a61af66fc99e Initial load
duke
parents:
diff changeset
1651 // Emit exception handler code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1652 int emit_exception_handler(CodeBuffer& cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1653 Register temp_reg = G3;
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1655 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1656
a61af66fc99e Initial load
duke
parents:
diff changeset
1657 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1658 __ start_a_stub(size_exception_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1659 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1660
a61af66fc99e Initial load
duke
parents:
diff changeset
1661 int offset = __ offset();
a61af66fc99e Initial load
duke
parents:
diff changeset
1662
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1664 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
1665
a61af66fc99e Initial load
duke
parents:
diff changeset
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1667
a61af66fc99e Initial load
duke
parents:
diff changeset
1668 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1669
a61af66fc99e Initial load
duke
parents:
diff changeset
1670 return offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
1671 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1672
a61af66fc99e Initial load
duke
parents:
diff changeset
1673 int emit_deopt_handler(CodeBuffer& cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1674 // Can't use any of the current frame's registers as we may have deopted
a61af66fc99e Initial load
duke
parents:
diff changeset
1675 // at a poll and everything (including G3) can be live.
a61af66fc99e Initial load
duke
parents:
diff changeset
1676 Register temp_reg = L0;
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1678 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1679
a61af66fc99e Initial load
duke
parents:
diff changeset
1680 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1681 __ start_a_stub(size_deopt_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1682 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1683
a61af66fc99e Initial load
duke
parents:
diff changeset
1684 int offset = __ offset();
a61af66fc99e Initial load
duke
parents:
diff changeset
1685 __ save_frame(0);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1687 __ delayed()->restore();
a61af66fc99e Initial load
duke
parents:
diff changeset
1688
a61af66fc99e Initial load
duke
parents:
diff changeset
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1690
a61af66fc99e Initial load
duke
parents:
diff changeset
1691 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1692 return offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
1693
a61af66fc99e Initial load
duke
parents:
diff changeset
1694 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1695
a61af66fc99e Initial load
duke
parents:
diff changeset
1696 // Given a register encoding, produce a Integer Register object
a61af66fc99e Initial load
duke
parents:
diff changeset
1697 static Register reg_to_register_object(int register_encoding) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
a61af66fc99e Initial load
duke
parents:
diff changeset
1699 return as_Register(register_encoding);
a61af66fc99e Initial load
duke
parents:
diff changeset
1700 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1701
a61af66fc99e Initial load
duke
parents:
diff changeset
1702 // Given a register encoding, produce a single-precision Float Register object
a61af66fc99e Initial load
duke
parents:
diff changeset
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
a61af66fc99e Initial load
duke
parents:
diff changeset
1705 return as_SingleFloatRegister(register_encoding);
a61af66fc99e Initial load
duke
parents:
diff changeset
1706 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1707
a61af66fc99e Initial load
duke
parents:
diff changeset
1708 // Given a register encoding, produce a double-precision Float Register object
a61af66fc99e Initial load
duke
parents:
diff changeset
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
a61af66fc99e Initial load
duke
parents:
diff changeset
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
a61af66fc99e Initial load
duke
parents:
diff changeset
1712 return as_DoubleFloatRegister(register_encoding);
a61af66fc99e Initial load
duke
parents:
diff changeset
1713 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1714
775
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1715 const bool Matcher::match_rule_supported(int opcode) {
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1716 if (!has_match_rule(opcode))
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1717 return false;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1718
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1719 switch (opcode) {
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1720 case Op_CountLeadingZerosI:
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1721 case Op_CountLeadingZerosL:
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1722 case Op_CountTrailingZerosI:
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1723 case Op_CountTrailingZerosL:
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1724 if (!UsePopCountInstruction)
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1725 return false;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1726 break;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1727 }
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1728
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1729 return true; // Per default match rules are supported.
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1730 }
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
1731
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1732 int Matcher::regnum_to_fpu_offset(int regnum) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1733 return regnum - 32; // The FP registers are in the second chunk
a61af66fc99e Initial load
duke
parents:
diff changeset
1734 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1735
a61af66fc99e Initial load
duke
parents:
diff changeset
1736 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
1738 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1739
a61af66fc99e Initial load
duke
parents:
diff changeset
1740 // Vector width in bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
1741 const uint Matcher::vector_width_in_bytes(void) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1742 return 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
1743 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1744
a61af66fc99e Initial load
duke
parents:
diff changeset
1745 // Vector ideal reg
a61af66fc99e Initial load
duke
parents:
diff changeset
1746 const uint Matcher::vector_ideal_reg(void) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1747 return Op_RegD;
a61af66fc99e Initial load
duke
parents:
diff changeset
1748 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1749
a61af66fc99e Initial load
duke
parents:
diff changeset
1750 // USII supports fxtof through the whole range of number, USIII doesn't
a61af66fc99e Initial load
duke
parents:
diff changeset
1751 const bool Matcher::convL2FSupported(void) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1752 return VM_Version::has_fast_fxtof();
a61af66fc99e Initial load
duke
parents:
diff changeset
1753 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1754
a61af66fc99e Initial load
duke
parents:
diff changeset
1755 // Is this branch offset short enough that a short branch can be used?
a61af66fc99e Initial load
duke
parents:
diff changeset
1756 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1757 // NOTE: If the platform does not provide any short branch variants, then
a61af66fc99e Initial load
duke
parents:
diff changeset
1758 // this method should return false for offset 0.
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1759 bool Matcher::is_short_branch_offset(int rule, int offset) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1760 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1761 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1762
a61af66fc99e Initial load
duke
parents:
diff changeset
1763 const bool Matcher::isSimpleConstant64(jlong value) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
a61af66fc99e Initial load
duke
parents:
diff changeset
1765 // Depends on optimizations in MacroAssembler::setx.
a61af66fc99e Initial load
duke
parents:
diff changeset
1766 int hi = (int)(value >> 32);
a61af66fc99e Initial load
duke
parents:
diff changeset
1767 int lo = (int)(value & ~0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1768 return (hi == 0) || (hi == -1) || (lo == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1769 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1770
a61af66fc99e Initial load
duke
parents:
diff changeset
1771 // No scaling for the parameter the ClearArray node.
a61af66fc99e Initial load
duke
parents:
diff changeset
1772 const bool Matcher::init_array_count_is_in_bytes = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1773
a61af66fc99e Initial load
duke
parents:
diff changeset
1774 // Threshold size for cleararray.
a61af66fc99e Initial load
duke
parents:
diff changeset
1775 const int Matcher::init_array_short_size = 8 * BytesPerLong;
a61af66fc99e Initial load
duke
parents:
diff changeset
1776
a61af66fc99e Initial load
duke
parents:
diff changeset
1777 // Should the Matcher clone shifts on addressing modes, expecting them to
a61af66fc99e Initial load
duke
parents:
diff changeset
1778 // be subsumed into complex addressing expressions or compute them into
a61af66fc99e Initial load
duke
parents:
diff changeset
1779 // registers? True for Intel but false for most RISCs
a61af66fc99e Initial load
duke
parents:
diff changeset
1780 const bool Matcher::clone_shift_expressions = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1781
a61af66fc99e Initial load
duke
parents:
diff changeset
1782 // Is it better to copy float constants, or load them directly from memory?
a61af66fc99e Initial load
duke
parents:
diff changeset
1783 // Intel can load a float constant from a direct address, requiring no
a61af66fc99e Initial load
duke
parents:
diff changeset
1784 // extra registers. Most RISCs will have to materialize an address into a
a61af66fc99e Initial load
duke
parents:
diff changeset
1785 // register first, so they would do better to copy the constant from stack.
a61af66fc99e Initial load
duke
parents:
diff changeset
1786 const bool Matcher::rematerialize_float_constants = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1787
a61af66fc99e Initial load
duke
parents:
diff changeset
1788 // If CPU can load and store mis-aligned doubles directly then no fixup is
a61af66fc99e Initial load
duke
parents:
diff changeset
1789 // needed. Else we split the double into 2 integer pieces and move it
a61af66fc99e Initial load
duke
parents:
diff changeset
1790 // piece-by-piece. Only happens when passing doubles into C code as the
a61af66fc99e Initial load
duke
parents:
diff changeset
1791 // Java calling convention forces doubles to be aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
1792 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1793 const bool Matcher::misaligned_doubles_ok = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1794 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
1795 const bool Matcher::misaligned_doubles_ok = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1796 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1797
a61af66fc99e Initial load
duke
parents:
diff changeset
1798 // No-op on SPARC.
a61af66fc99e Initial load
duke
parents:
diff changeset
1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1800 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1801
a61af66fc99e Initial load
duke
parents:
diff changeset
1802 // Advertise here if the CPU requires explicit rounding operations
a61af66fc99e Initial load
duke
parents:
diff changeset
1803 // to implement the UseStrictFP mode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1804 const bool Matcher::strict_fp_requires_explicit_rounding = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1805
a61af66fc99e Initial load
duke
parents:
diff changeset
1806 // Do floats take an entire double register or just half?
a61af66fc99e Initial load
duke
parents:
diff changeset
1807 const bool Matcher::float_in_double = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1808
a61af66fc99e Initial load
duke
parents:
diff changeset
1809 // Do ints take an entire long register or just half?
a61af66fc99e Initial load
duke
parents:
diff changeset
1810 // Note that we if-def off of _LP64.
a61af66fc99e Initial load
duke
parents:
diff changeset
1811 // The relevant question is how the int is callee-saved. In _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1812 // the whole long is written but de-opt'ing will have to extract
a61af66fc99e Initial load
duke
parents:
diff changeset
1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
a61af66fc99e Initial load
duke
parents:
diff changeset
1814 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1815 const bool Matcher::int_in_long = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1816 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
1817 const bool Matcher::int_in_long = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1818 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1819
a61af66fc99e Initial load
duke
parents:
diff changeset
1820 // Return whether or not this register is ever used as an argument. This
a61af66fc99e Initial load
duke
parents:
diff changeset
1821 // function is used on startup to build the trampoline stubs in generateOptoStub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1822 // Registers not mentioned will be killed by the VM call in the trampoline, and
a61af66fc99e Initial load
duke
parents:
diff changeset
1823 // arguments in those registers not be available to the callee.
a61af66fc99e Initial load
duke
parents:
diff changeset
1824 bool Matcher::can_be_java_arg( int reg ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1825 // Standard sparc 6 args in registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1826 if( reg == R_I0_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1827 reg == R_I1_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1828 reg == R_I2_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1829 reg == R_I3_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1830 reg == R_I4_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1831 reg == R_I5_num ) return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1832 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1833 // 64-bit builds can pass 64-bit pointers and longs in
a61af66fc99e Initial load
duke
parents:
diff changeset
1834 // the high I registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1835 if( reg == R_I0H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1836 reg == R_I1H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1837 reg == R_I2H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1838 reg == R_I3H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1839 reg == R_I4H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
1840 reg == R_I5H_num ) return true;
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1841
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1843 return true;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1844 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
1845
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1846 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
a61af66fc99e Initial load
duke
parents:
diff changeset
1848 // Longs cannot be passed in O regs, because O regs become I regs
a61af66fc99e Initial load
duke
parents:
diff changeset
1849 // after a 'save' and I regs get their high bits chopped off on
a61af66fc99e Initial load
duke
parents:
diff changeset
1850 // interrupt.
a61af66fc99e Initial load
duke
parents:
diff changeset
1851 if( reg == R_G1H_num || reg == R_G1_num ) return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1852 if( reg == R_G4H_num || reg == R_G4_num ) return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1853 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1854 // A few float args in registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1856
a61af66fc99e Initial load
duke
parents:
diff changeset
1857 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1858 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1859
a61af66fc99e Initial load
duke
parents:
diff changeset
1860 bool Matcher::is_spillable_arg( int reg ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1861 return can_be_java_arg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1862 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1863
a61af66fc99e Initial load
duke
parents:
diff changeset
1864 // Register for DIVI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
1865 RegMask Matcher::divI_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1866 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
1867 return RegMask();
a61af66fc99e Initial load
duke
parents:
diff changeset
1868 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1869
a61af66fc99e Initial load
duke
parents:
diff changeset
1870 // Register for MODI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
1871 RegMask Matcher::modI_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1872 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
1873 return RegMask();
a61af66fc99e Initial load
duke
parents:
diff changeset
1874 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1875
a61af66fc99e Initial load
duke
parents:
diff changeset
1876 // Register for DIVL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
1877 RegMask Matcher::divL_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1878 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
1879 return RegMask();
a61af66fc99e Initial load
duke
parents:
diff changeset
1880 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1881
a61af66fc99e Initial load
duke
parents:
diff changeset
1882 // Register for MODL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
1883 RegMask Matcher::modL_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1884 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
1885 return RegMask();
a61af66fc99e Initial load
duke
parents:
diff changeset
1886 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1887
a61af66fc99e Initial load
duke
parents:
diff changeset
1888 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1889
a61af66fc99e Initial load
duke
parents:
diff changeset
1890
a61af66fc99e Initial load
duke
parents:
diff changeset
1891 // The intptr_t operand types, defined by textual substitution.
a61af66fc99e Initial load
duke
parents:
diff changeset
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1893 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
1894 #define immX immL
a61af66fc99e Initial load
duke
parents:
diff changeset
1895 #define immX13 immL13
a61af66fc99e Initial load
duke
parents:
diff changeset
1896 #define iRegX iRegL
a61af66fc99e Initial load
duke
parents:
diff changeset
1897 #define g1RegX g1RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
1898 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
1899 #define immX immI
a61af66fc99e Initial load
duke
parents:
diff changeset
1900 #define immX13 immI13
a61af66fc99e Initial load
duke
parents:
diff changeset
1901 #define iRegX iRegI
a61af66fc99e Initial load
duke
parents:
diff changeset
1902 #define g1RegX g1RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
1903 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1904
a61af66fc99e Initial load
duke
parents:
diff changeset
1905 //----------ENCODING BLOCK-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1906 // This block specifies the encoding classes used by the compiler to output
a61af66fc99e Initial load
duke
parents:
diff changeset
1907 // byte streams. Encoding classes are parameterized macros used by
a61af66fc99e Initial load
duke
parents:
diff changeset
1908 // Machine Instruction Nodes in order to generate the bit encoding of the
a61af66fc99e Initial load
duke
parents:
diff changeset
1909 // instruction. Operands specify their base encoding interface with the
a61af66fc99e Initial load
duke
parents:
diff changeset
1910 // interface keyword. There are currently supported four interfaces,
a61af66fc99e Initial load
duke
parents:
diff changeset
1911 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
a61af66fc99e Initial load
duke
parents:
diff changeset
1912 // operand to generate a function which returns its register number when
a61af66fc99e Initial load
duke
parents:
diff changeset
1913 // queried. CONST_INTER causes an operand to generate a function which
a61af66fc99e Initial load
duke
parents:
diff changeset
1914 // returns the value of the constant when queried. MEMORY_INTER causes an
a61af66fc99e Initial load
duke
parents:
diff changeset
1915 // operand to generate four functions which return the Base Register, the
a61af66fc99e Initial load
duke
parents:
diff changeset
1916 // Index Register, the Scale Value, and the Offset Value of the operand when
a61af66fc99e Initial load
duke
parents:
diff changeset
1917 // queried. COND_INTER causes an operand to generate six functions which
a61af66fc99e Initial load
duke
parents:
diff changeset
1918 // return the encoding code (ie - encoding bits for the instruction)
a61af66fc99e Initial load
duke
parents:
diff changeset
1919 // associated with each basic boolean condition for a conditional instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
1920 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1921 // Instructions specify two basic values for encoding. Again, a function
a61af66fc99e Initial load
duke
parents:
diff changeset
1922 // is available to check if the constant displacement is an oop. They use the
a61af66fc99e Initial load
duke
parents:
diff changeset
1923 // ins_encode keyword to specify their encoding classes (which must be
a61af66fc99e Initial load
duke
parents:
diff changeset
1924 // a sequence of enc_class names, and their parameters, specified in
a61af66fc99e Initial load
duke
parents:
diff changeset
1925 // the encoding block), and they use the
a61af66fc99e Initial load
duke
parents:
diff changeset
1926 // opcode keyword to specify, in order, their primary, secondary, and
a61af66fc99e Initial load
duke
parents:
diff changeset
1927 // tertiary opcode. Only the opcode sections which a particular instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
1928 // needs for encoding need to be specified.
a61af66fc99e Initial load
duke
parents:
diff changeset
1929 encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1930 enc_class enc_untested %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1931 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1932 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1933 __ untested("encoding");
a61af66fc99e Initial load
duke
parents:
diff changeset
1934 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1935 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1936
a61af66fc99e Initial load
duke
parents:
diff changeset
1937 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1938 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
a61af66fc99e Initial load
duke
parents:
diff changeset
1939 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1940 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1941
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1942 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1943 emit_form3_mem_reg(cbuf, this, $primary, -1,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1944 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1945 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1946
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1947 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1948 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1949 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
a61af66fc99e Initial load
duke
parents:
diff changeset
1950 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1951
a61af66fc99e Initial load
duke
parents:
diff changeset
1952 enc_class form3_mem_prefetch_read( memory mem ) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1953 emit_form3_mem_reg(cbuf, this, $primary, -1,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1954 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
a61af66fc99e Initial load
duke
parents:
diff changeset
1955 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1956
a61af66fc99e Initial load
duke
parents:
diff changeset
1957 enc_class form3_mem_prefetch_write( memory mem ) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1958 emit_form3_mem_reg(cbuf, this, $primary, -1,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1959 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
a61af66fc99e Initial load
duke
parents:
diff changeset
1960 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1961
a61af66fc99e Initial load
duke
parents:
diff changeset
1962 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1963 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1964 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1965 guarantee($mem$$index == R_G0_enc, "double index?");
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1966 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1968 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
a61af66fc99e Initial load
duke
parents:
diff changeset
1969 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
a61af66fc99e Initial load
duke
parents:
diff changeset
1970 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1971
a61af66fc99e Initial load
duke
parents:
diff changeset
1972 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1973 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1974 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1975 guarantee($mem$$index == R_G0_enc, "double index?");
a61af66fc99e Initial load
duke
parents:
diff changeset
1976 // Load long with 2 instructions
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1977 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1978 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1979 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1980
a61af66fc99e Initial load
duke
parents:
diff changeset
1981 //%%% form3_mem_plus_4_reg is a hack--get rid of it
a61af66fc99e Initial load
duke
parents:
diff changeset
1982 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1983 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
1984 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1985 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1986
a61af66fc99e Initial load
duke
parents:
diff changeset
1987 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1988 // Encode a reg-reg copy. If it is useless, then empty encoding.
a61af66fc99e Initial load
duke
parents:
diff changeset
1989 if( $rs2$$reg != $rd$$reg )
a61af66fc99e Initial load
duke
parents:
diff changeset
1990 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
1991 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1992
a61af66fc99e Initial load
duke
parents:
diff changeset
1993 // Target lo half of long
a61af66fc99e Initial load
duke
parents:
diff changeset
1994 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
a61af66fc99e Initial load
duke
parents:
diff changeset
1996 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
a61af66fc99e Initial load
duke
parents:
diff changeset
1997 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
1998 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1999
a61af66fc99e Initial load
duke
parents:
diff changeset
2000 // Source lo half of long
a61af66fc99e Initial load
duke
parents:
diff changeset
2001 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2002 // Encode a reg-reg copy. If it is useless, then empty encoding.
a61af66fc99e Initial load
duke
parents:
diff changeset
2003 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
a61af66fc99e Initial load
duke
parents:
diff changeset
2004 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
a61af66fc99e Initial load
duke
parents:
diff changeset
2005 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2006
a61af66fc99e Initial load
duke
parents:
diff changeset
2007 // Target hi half of long
a61af66fc99e Initial load
duke
parents:
diff changeset
2008 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2009 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2010 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2011
a61af66fc99e Initial load
duke
parents:
diff changeset
2012 // Source lo half of long, and leave it sign extended.
a61af66fc99e Initial load
duke
parents:
diff changeset
2013 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2014 // Sign extend low half
a61af66fc99e Initial load
duke
parents:
diff changeset
2015 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2016 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2017
a61af66fc99e Initial load
duke
parents:
diff changeset
2018 // Source hi half of long, and leave it sign extended.
a61af66fc99e Initial load
duke
parents:
diff changeset
2019 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2020 // Shift high half to low half
a61af66fc99e Initial load
duke
parents:
diff changeset
2021 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2022 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2023
a61af66fc99e Initial load
duke
parents:
diff changeset
2024 // Source hi half of long
a61af66fc99e Initial load
duke
parents:
diff changeset
2025 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2026 // Encode a reg-reg copy. If it is useless, then empty encoding.
a61af66fc99e Initial load
duke
parents:
diff changeset
2027 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
a61af66fc99e Initial load
duke
parents:
diff changeset
2028 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
a61af66fc99e Initial load
duke
parents:
diff changeset
2029 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2030
a61af66fc99e Initial load
duke
parents:
diff changeset
2031 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2032 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2033 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2034
a61af66fc99e Initial load
duke
parents:
diff changeset
2035 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2036 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2037 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2038 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2039
a61af66fc99e Initial load
duke
parents:
diff changeset
2040 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2041 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2042 // clear if nothing else is happening
a61af66fc99e Initial load
duke
parents:
diff changeset
2043 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2044 // blt,a,pn done
a61af66fc99e Initial load
duke
parents:
diff changeset
2045 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2046 // mov dst,-1 in delay slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2047 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2048 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2049
a61af66fc99e Initial load
duke
parents:
diff changeset
2050 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2051 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
a61af66fc99e Initial load
duke
parents:
diff changeset
2052 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2053
a61af66fc99e Initial load
duke
parents:
diff changeset
2054 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2055 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2056 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2057
a61af66fc99e Initial load
duke
parents:
diff changeset
2058 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2059 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2060 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2061
a61af66fc99e Initial load
duke
parents:
diff changeset
2062 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2063 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
a61af66fc99e Initial load
duke
parents:
diff changeset
2064 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2065
a61af66fc99e Initial load
duke
parents:
diff changeset
2066 enc_class move_return_pc_to_o1() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2067 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
a61af66fc99e Initial load
duke
parents:
diff changeset
2068 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2069
a61af66fc99e Initial load
duke
parents:
diff changeset
2070 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
2071 /* %%% merge with enc_to_bool */
a61af66fc99e Initial load
duke
parents:
diff changeset
2072 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2073 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2074
a61af66fc99e Initial load
duke
parents:
diff changeset
2075 Register src_reg = reg_to_register_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2076 Register dst_reg = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2077 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2078 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2079 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
2080
a61af66fc99e Initial load
duke
parents:
diff changeset
2081 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2082 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
a61af66fc99e Initial load
duke
parents:
diff changeset
2083 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2084
a61af66fc99e Initial load
duke
parents:
diff changeset
2085 Register p_reg = reg_to_register_object($p$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2086 Register q_reg = reg_to_register_object($q$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2087 Register y_reg = reg_to_register_object($y$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2088 Register tmp_reg = reg_to_register_object($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2089
a61af66fc99e Initial load
duke
parents:
diff changeset
2090 __ subcc( p_reg, q_reg, p_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2091 __ add ( p_reg, y_reg, tmp_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2092 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2093 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2094
a61af66fc99e Initial load
duke
parents:
diff changeset
2095 enc_class form_d2i_helper(regD src, regF dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2096 // fcmp %fcc0,$src,$src
a61af66fc99e Initial load
duke
parents:
diff changeset
2097 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2098 // branch %fcc0 not-nan, predict taken
a61af66fc99e Initial load
duke
parents:
diff changeset
2099 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2100 // fdtoi $src,$dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2101 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2102 // fitos $dst,$dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2104 // clear $dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2106 // carry on here...
a61af66fc99e Initial load
duke
parents:
diff changeset
2107 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2108
a61af66fc99e Initial load
duke
parents:
diff changeset
2109 enc_class form_d2l_helper(regD src, regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2110 // fcmp %fcc0,$src,$src check for NAN
a61af66fc99e Initial load
duke
parents:
diff changeset
2111 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2112 // branch %fcc0 not-nan, predict taken
a61af66fc99e Initial load
duke
parents:
diff changeset
2113 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2114 // fdtox $src,$dst convert in delay slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2116 // fxtod $dst,$dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2118 // clear $dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2120 // carry on here...
a61af66fc99e Initial load
duke
parents:
diff changeset
2121 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2122
a61af66fc99e Initial load
duke
parents:
diff changeset
2123 enc_class form_f2i_helper(regF src, regF dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2124 // fcmps %fcc0,$src,$src
a61af66fc99e Initial load
duke
parents:
diff changeset
2125 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2126 // branch %fcc0 not-nan, predict taken
a61af66fc99e Initial load
duke
parents:
diff changeset
2127 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2128 // fstoi $src,$dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2130 // fitos $dst,$dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2132 // clear $dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2134 // carry on here...
a61af66fc99e Initial load
duke
parents:
diff changeset
2135 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2136
a61af66fc99e Initial load
duke
parents:
diff changeset
2137 enc_class form_f2l_helper(regF src, regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2138 // fcmps %fcc0,$src,$src
a61af66fc99e Initial load
duke
parents:
diff changeset
2139 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2140 // branch %fcc0 not-nan, predict taken
a61af66fc99e Initial load
duke
parents:
diff changeset
2141 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2142 // fstox $src,$dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2143 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2144 // fxtod $dst,$dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2146 // clear $dst (if nan)
a61af66fc99e Initial load
duke
parents:
diff changeset
2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2148 // carry on here...
a61af66fc99e Initial load
duke
parents:
diff changeset
2149 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2150
a61af66fc99e Initial load
duke
parents:
diff changeset
2151 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2152 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2153 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2154 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2155
a61af66fc99e Initial load
duke
parents:
diff changeset
2156 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2157
a61af66fc99e Initial load
duke
parents:
diff changeset
2158 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2159 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2160
a61af66fc99e Initial load
duke
parents:
diff changeset
2161 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2163 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2164
a61af66fc99e Initial load
duke
parents:
diff changeset
2165 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2166 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2167 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2168
a61af66fc99e Initial load
duke
parents:
diff changeset
2169 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2170 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2171 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2172
a61af66fc99e Initial load
duke
parents:
diff changeset
2173 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2174 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2175 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2176
a61af66fc99e Initial load
duke
parents:
diff changeset
2177 enc_class form3_convI2F(regF rs2, regF rd) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2178 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2180
a61af66fc99e Initial load
duke
parents:
diff changeset
2181 // Encloding class for traceable jumps
a61af66fc99e Initial load
duke
parents:
diff changeset
2182 enc_class form_jmpl(g3RegP dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2183 emit_jmpl(cbuf, $dest$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2184 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2185
a61af66fc99e Initial load
duke
parents:
diff changeset
2186 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2187 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2188 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2189
a61af66fc99e Initial load
duke
parents:
diff changeset
2190 enc_class form2_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2191 emit_nop(cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2192 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2193
a61af66fc99e Initial load
duke
parents:
diff changeset
2194 enc_class form2_illtrap() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2195 emit_illtrap(cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2196 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2197
a61af66fc99e Initial load
duke
parents:
diff changeset
2198
a61af66fc99e Initial load
duke
parents:
diff changeset
2199 // Compare longs and convert into -1, 0, 1.
a61af66fc99e Initial load
duke
parents:
diff changeset
2200 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2201 // CMP $src1,$src2
a61af66fc99e Initial load
duke
parents:
diff changeset
2202 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2203 // blt,a,pn done
a61af66fc99e Initial load
duke
parents:
diff changeset
2204 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2205 // mov dst,-1 in delay slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2206 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2207 // bgt,a,pn done
a61af66fc99e Initial load
duke
parents:
diff changeset
2208 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2209 // mov dst,1 in delay slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2210 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2211 // CLR $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2212 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2213 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2214
a61af66fc99e Initial load
duke
parents:
diff changeset
2215 enc_class enc_PartialSubtypeCheck() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2216 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2217 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
a61af66fc99e Initial load
duke
parents:
diff changeset
2218 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2219 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2220
a61af66fc99e Initial load
duke
parents:
diff changeset
2221 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2222 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2223 Label &L = *($labl$$label);
a61af66fc99e Initial load
duke
parents:
diff changeset
2224 Assembler::Predict predict_taken =
a61af66fc99e Initial load
duke
parents:
diff changeset
2225 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
a61af66fc99e Initial load
duke
parents:
diff changeset
2226
a61af66fc99e Initial load
duke
parents:
diff changeset
2227 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2228 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2229 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2230
a61af66fc99e Initial load
duke
parents:
diff changeset
2231 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2232 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2233 Label &L = *($labl$$label);
a61af66fc99e Initial load
duke
parents:
diff changeset
2234 Assembler::Predict predict_taken =
a61af66fc99e Initial load
duke
parents:
diff changeset
2235 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
a61af66fc99e Initial load
duke
parents:
diff changeset
2236
a61af66fc99e Initial load
duke
parents:
diff changeset
2237 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2238 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2239 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2240
a61af66fc99e Initial load
duke
parents:
diff changeset
2241 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2242 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2243 Label &L = *($labl$$label);
a61af66fc99e Initial load
duke
parents:
diff changeset
2244 Assembler::Predict predict_taken =
a61af66fc99e Initial load
duke
parents:
diff changeset
2245 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
a61af66fc99e Initial load
duke
parents:
diff changeset
2246
a61af66fc99e Initial load
duke
parents:
diff changeset
2247 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2248 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2249 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2250
a61af66fc99e Initial load
duke
parents:
diff changeset
2251 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2252 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2253 Label &L = *($labl$$label);
a61af66fc99e Initial load
duke
parents:
diff changeset
2254 Assembler::Predict predict_taken =
a61af66fc99e Initial load
duke
parents:
diff changeset
2255 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
a61af66fc99e Initial load
duke
parents:
diff changeset
2256
a61af66fc99e Initial load
duke
parents:
diff changeset
2257 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2258 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2259 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2260
a61af66fc99e Initial load
duke
parents:
diff changeset
2261 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2262 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2263
a61af66fc99e Initial load
duke
parents:
diff changeset
2264 Register switch_reg = as_Register($switch_val$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2265 Register table_reg = O7;
a61af66fc99e Initial load
duke
parents:
diff changeset
2266
a61af66fc99e Initial load
duke
parents:
diff changeset
2267 address table_base = __ address_table_constant(_index2label);
a61af66fc99e Initial load
duke
parents:
diff changeset
2268 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
a61af66fc99e Initial load
duke
parents:
diff changeset
2269
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2270 // Move table address into a register.
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2271 __ set(table_base, table_reg, rspec);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2272
a61af66fc99e Initial load
duke
parents:
diff changeset
2273 // Jump to base address + switch value
a61af66fc99e Initial load
duke
parents:
diff changeset
2274 __ ld_ptr(table_reg, switch_reg, table_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2275 __ jmp(table_reg, G0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2276 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2277
a61af66fc99e Initial load
duke
parents:
diff changeset
2278 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2279
a61af66fc99e Initial load
duke
parents:
diff changeset
2280 enc_class enc_ba( Label labl ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2281 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2282 Label &L = *($labl$$label);
a61af66fc99e Initial load
duke
parents:
diff changeset
2283 __ ba(false, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2284 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2285 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2286
a61af66fc99e Initial load
duke
parents:
diff changeset
2287 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2288 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2289 Label &L = *$labl$$label;
a61af66fc99e Initial load
duke
parents:
diff changeset
2290 Assembler::Predict predict_taken =
a61af66fc99e Initial load
duke
parents:
diff changeset
2291 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
a61af66fc99e Initial load
duke
parents:
diff changeset
2292
a61af66fc99e Initial load
duke
parents:
diff changeset
2293 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2294 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2295 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2296
a61af66fc99e Initial load
duke
parents:
diff changeset
2297 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2298 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2299 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2300 (Assembler::movcc_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2301 (1 << 18) | // cc2 bit for 'icc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2302 ($cmp$$cmpcode << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2303 (0 << 13) | // select register move
a61af66fc99e Initial load
duke
parents:
diff changeset
2304 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2305 ($src$$reg << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2306 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2307 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2308 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2309
a61af66fc99e Initial load
duke
parents:
diff changeset
2310 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2311 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
a61af66fc99e Initial load
duke
parents:
diff changeset
2312 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2313 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2314 (Assembler::movcc_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2315 (1 << 18) | // cc2 bit for 'icc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2316 ($cmp$$cmpcode << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2317 (1 << 13) | // select immediate move
a61af66fc99e Initial load
duke
parents:
diff changeset
2318 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2319 (simm11 << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2320 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2321 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2322 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2323
a61af66fc99e Initial load
duke
parents:
diff changeset
2324 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2325 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2326 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2327 (Assembler::movcc_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2328 (0 << 18) | // cc2 bit for 'fccX'
a61af66fc99e Initial load
duke
parents:
diff changeset
2329 ($cmp$$cmpcode << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2330 (0 << 13) | // select register move
a61af66fc99e Initial load
duke
parents:
diff changeset
2331 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
a61af66fc99e Initial load
duke
parents:
diff changeset
2332 ($src$$reg << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2333 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2334 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2335 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2336
a61af66fc99e Initial load
duke
parents:
diff changeset
2337 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2338 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
a61af66fc99e Initial load
duke
parents:
diff changeset
2339 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2340 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2341 (Assembler::movcc_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2342 (0 << 18) | // cc2 bit for 'fccX'
a61af66fc99e Initial load
duke
parents:
diff changeset
2343 ($cmp$$cmpcode << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2344 (1 << 13) | // select immediate move
a61af66fc99e Initial load
duke
parents:
diff changeset
2345 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
a61af66fc99e Initial load
duke
parents:
diff changeset
2346 (simm11 << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2347 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2348 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2349 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2350
a61af66fc99e Initial load
duke
parents:
diff changeset
2351 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2352 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2353 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2354 (Assembler::fpop2_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2355 (0 << 18) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2356 ($cmp$$cmpcode << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2357 (1 << 13) | // select register move
a61af66fc99e Initial load
duke
parents:
diff changeset
2358 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2359 ($primary << 5) | // select single, double or quad
a61af66fc99e Initial load
duke
parents:
diff changeset
2360 ($src$$reg << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2361 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2362 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2363 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2364
a61af66fc99e Initial load
duke
parents:
diff changeset
2365 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2366 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2367 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2368 (Assembler::fpop2_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2369 (0 << 18) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2370 ($cmp$$cmpcode << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2371 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
a61af66fc99e Initial load
duke
parents:
diff changeset
2372 ($primary << 5) | // select single, double or quad
a61af66fc99e Initial load
duke
parents:
diff changeset
2373 ($src$$reg << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2374 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2375 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2376 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2377
a61af66fc99e Initial load
duke
parents:
diff changeset
2378 // Used by the MIN/MAX encodings. Same as a CMOV, but
a61af66fc99e Initial load
duke
parents:
diff changeset
2379 // the condition comes from opcode-field instead of an argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
2380 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2381 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2382 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2383 (Assembler::movcc_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2384 (1 << 18) | // cc2 bit for 'icc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2385 ($primary << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2386 (0 << 13) | // select register move
a61af66fc99e Initial load
duke
parents:
diff changeset
2387 (0 << 11) | // cc1, cc0 bits for 'icc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2388 ($src$$reg << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2389 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2390 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2391 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2392
a61af66fc99e Initial load
duke
parents:
diff changeset
2393 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2394 int op = (Assembler::arith_op << 30) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2395 ($dst$$reg << 25) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2396 (Assembler::movcc_op3 << 19) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2397 (6 << 16) | // cc2 bit for 'xcc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2398 ($primary << 14) |
a61af66fc99e Initial load
duke
parents:
diff changeset
2399 (0 << 13) | // select register move
a61af66fc99e Initial load
duke
parents:
diff changeset
2400 (0 << 11) | // cc1, cc0 bits for 'icc'
a61af66fc99e Initial load
duke
parents:
diff changeset
2401 ($src$$reg << 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2402 *((int*)(cbuf.code_end())) = op;
a61af66fc99e Initial load
duke
parents:
diff changeset
2403 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
2404 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2405
a61af66fc99e Initial load
duke
parents:
diff changeset
2406 // Utility encoding for loading a 64 bit Pointer into a register
a61af66fc99e Initial load
duke
parents:
diff changeset
2407 // The 64 bit pointer is stored in the generated code stream
a61af66fc99e Initial load
duke
parents:
diff changeset
2408 enc_class SetPtr( immP src, iRegP rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2409 Register dest = reg_to_register_object($rd$$reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2410 MacroAssembler _masm(&cbuf);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2411 // [RGV] This next line should be generated from ADLC
a61af66fc99e Initial load
duke
parents:
diff changeset
2412 if ( _opnds[1]->constant_is_oop() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2413 intptr_t val = $src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2414 __ set_oop_constant((jobject)val, dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
2415 } else { // non-oop pointers, e.g. card mark base, heap top
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2416 __ set($src$$constant, dest);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2417 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2418 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2419
a61af66fc99e Initial load
duke
parents:
diff changeset
2420 enc_class Set13( immI13 src, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2421 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
a61af66fc99e Initial load
duke
parents:
diff changeset
2422 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2423
a61af66fc99e Initial load
duke
parents:
diff changeset
2424 enc_class SetHi22( immI src, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2425 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
a61af66fc99e Initial load
duke
parents:
diff changeset
2426 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2427
a61af66fc99e Initial load
duke
parents:
diff changeset
2428 enc_class Set32( immI src, iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2429 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2430 __ set($src$$constant, reg_to_register_object($rd$$reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
2431 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2432
a61af66fc99e Initial load
duke
parents:
diff changeset
2433 enc_class SetNull( iRegI rd ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2434 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2435 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2436
a61af66fc99e Initial load
duke
parents:
diff changeset
2437 enc_class call_epilog %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2438 if( VerifyStackAtCalls ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2439 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2440 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
2441 Register temp_reg = G3;
a61af66fc99e Initial load
duke
parents:
diff changeset
2442 __ add(SP, framesize, temp_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2443 __ cmp(temp_reg, FP);
a61af66fc99e Initial load
duke
parents:
diff changeset
2444 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2445 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2446 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2447
a61af66fc99e Initial load
duke
parents:
diff changeset
2448 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
a61af66fc99e Initial load
duke
parents:
diff changeset
2449 // to G1 so the register allocator will not have to deal with the misaligned register
a61af66fc99e Initial load
duke
parents:
diff changeset
2450 // pair.
a61af66fc99e Initial load
duke
parents:
diff changeset
2451 enc_class adjust_long_from_native_call %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2452 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
2453 if (returns_long()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2454 // sllx O0,32,O0
a61af66fc99e Initial load
duke
parents:
diff changeset
2455 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2456 // srl O1,0,O1
a61af66fc99e Initial load
duke
parents:
diff changeset
2457 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2458 // or O0,O1,G1
a61af66fc99e Initial load
duke
parents:
diff changeset
2459 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
a61af66fc99e Initial load
duke
parents:
diff changeset
2460 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2461 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
2462 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2463
a61af66fc99e Initial load
duke
parents:
diff changeset
2464 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
a61af66fc99e Initial load
duke
parents:
diff changeset
2465 // CALL directly to the runtime
a61af66fc99e Initial load
duke
parents:
diff changeset
2466 // The user of this is responsible for ensuring that R_L7 is empty (killed).
a61af66fc99e Initial load
duke
parents:
diff changeset
2467 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
a61af66fc99e Initial load
duke
parents:
diff changeset
2468 /*preserve_g2=*/true, /*force far call*/true);
a61af66fc99e Initial load
duke
parents:
diff changeset
2469 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2470
a61af66fc99e Initial load
duke
parents:
diff changeset
2471 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2472 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
a61af66fc99e Initial load
duke
parents:
diff changeset
2473 // who we intended to call.
a61af66fc99e Initial load
duke
parents:
diff changeset
2474 if ( !_method ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2475 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
a61af66fc99e Initial load
duke
parents:
diff changeset
2476 } else if (_optimized_virtual) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
a61af66fc99e Initial load
duke
parents:
diff changeset
2478 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
a61af66fc99e Initial load
duke
parents:
diff changeset
2480 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2481 if( _method ) { // Emit stub for static call
a61af66fc99e Initial load
duke
parents:
diff changeset
2482 emit_java_to_interp(cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2483 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2484 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2485
a61af66fc99e Initial load
duke
parents:
diff changeset
2486 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2487 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2488 __ set_inst_mark();
a61af66fc99e Initial load
duke
parents:
diff changeset
2489 int vtable_index = this->_vtable_index;
a61af66fc99e Initial load
duke
parents:
diff changeset
2490 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
a61af66fc99e Initial load
duke
parents:
diff changeset
2491 if (vtable_index < 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2492 // must be invalid_vtable_index, not nonvirtual_vtable_index
a61af66fc99e Initial load
duke
parents:
diff changeset
2493 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
a61af66fc99e Initial load
duke
parents:
diff changeset
2494 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
a61af66fc99e Initial load
duke
parents:
diff changeset
2495 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
a61af66fc99e Initial load
duke
parents:
diff changeset
2496 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
a61af66fc99e Initial load
duke
parents:
diff changeset
2497 // !!!!!
a61af66fc99e Initial load
duke
parents:
diff changeset
2498 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
a61af66fc99e Initial load
duke
parents:
diff changeset
2499 // emit_call_dynamic_prologue( cbuf );
a61af66fc99e Initial load
duke
parents:
diff changeset
2500 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2501
a61af66fc99e Initial load
duke
parents:
diff changeset
2502 address virtual_call_oop_addr = __ inst_mark();
a61af66fc99e Initial load
duke
parents:
diff changeset
2503 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
a61af66fc99e Initial load
duke
parents:
diff changeset
2504 // who we intended to call.
a61af66fc99e Initial load
duke
parents:
diff changeset
2505 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
a61af66fc99e Initial load
duke
parents:
diff changeset
2506 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
a61af66fc99e Initial load
duke
parents:
diff changeset
2507 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2508 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
a61af66fc99e Initial load
duke
parents:
diff changeset
2509 // Just go thru the vtable
a61af66fc99e Initial load
duke
parents:
diff changeset
2510 // get receiver klass (receiver already checked for non-null)
a61af66fc99e Initial load
duke
parents:
diff changeset
2511 // If we end up going thru a c2i adapter interpreter expects method in G5
a61af66fc99e Initial load
duke
parents:
diff changeset
2512 int off = __ offset();
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2513 __ load_klass(O0, G3_scratch);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2514 int klass_load_size;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2515 if (UseCompressedOops) {
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
2516 assert(Universe::heap() != NULL, "java heap should be initialized");
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
2517 if (Universe::narrow_oop_base() == NULL)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
2518 klass_load_size = 2*BytesPerInstWord;
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
2519 else
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
2520 klass_load_size = 3*BytesPerInstWord;
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2521 } else {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2522 klass_load_size = 1*BytesPerInstWord;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2523 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2524 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
a61af66fc99e Initial load
duke
parents:
diff changeset
2525 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
a61af66fc99e Initial load
duke
parents:
diff changeset
2526 if( __ is_simm13(v_off) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2527 __ ld_ptr(G3, v_off, G5_method);
a61af66fc99e Initial load
duke
parents:
diff changeset
2528 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2529 // Generate 2 instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
2530 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
a61af66fc99e Initial load
duke
parents:
diff changeset
2531 __ or3(G5_method, v_off & 0x3ff, G5_method);
a61af66fc99e Initial load
duke
parents:
diff changeset
2532 // ld_ptr, set_hi, set
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2533 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
2534 "Unexpected instruction size(s)");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2535 __ ld_ptr(G3, G5_method, G5_method);
a61af66fc99e Initial load
duke
parents:
diff changeset
2536 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2537 // NOTE: for vtable dispatches, the vtable entry will never be null.
a61af66fc99e Initial load
duke
parents:
diff changeset
2538 // However it may very well end up in handle_wrong_method if the
a61af66fc99e Initial load
duke
parents:
diff changeset
2539 // method is abstract for the particular class.
a61af66fc99e Initial load
duke
parents:
diff changeset
2540 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
a61af66fc99e Initial load
duke
parents:
diff changeset
2541 // jump to target (either compiled code or c2iadapter)
a61af66fc99e Initial load
duke
parents:
diff changeset
2542 __ jmpl(G3_scratch, G0, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2543 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2544 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2545 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2546
a61af66fc99e Initial load
duke
parents:
diff changeset
2547 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2548 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2549
a61af66fc99e Initial load
duke
parents:
diff changeset
2550 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
a61af66fc99e Initial load
duke
parents:
diff changeset
2551 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
a61af66fc99e Initial load
duke
parents:
diff changeset
2552 // we might be calling a C2I adapter which needs it.
a61af66fc99e Initial load
duke
parents:
diff changeset
2553
a61af66fc99e Initial load
duke
parents:
diff changeset
2554 assert(temp_reg != G5_ic_reg, "conflicting registers");
a61af66fc99e Initial load
duke
parents:
diff changeset
2555 // Load nmethod
a61af66fc99e Initial load
duke
parents:
diff changeset
2556 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2557
a61af66fc99e Initial load
duke
parents:
diff changeset
2558 // CALL to compiled java, indirect the contents of G3
a61af66fc99e Initial load
duke
parents:
diff changeset
2559 __ set_inst_mark();
a61af66fc99e Initial load
duke
parents:
diff changeset
2560 __ callr(temp_reg, G0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2561 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2562 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2563
a61af66fc99e Initial load
duke
parents:
diff changeset
2564 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2565 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2566 Register Rdividend = reg_to_register_object($src1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2567 Register Rdivisor = reg_to_register_object($src2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2568 Register Rresult = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2569
a61af66fc99e Initial load
duke
parents:
diff changeset
2570 __ sra(Rdivisor, 0, Rdivisor);
a61af66fc99e Initial load
duke
parents:
diff changeset
2571 __ sra(Rdividend, 0, Rdividend);
a61af66fc99e Initial load
duke
parents:
diff changeset
2572 __ sdivx(Rdividend, Rdivisor, Rresult);
a61af66fc99e Initial load
duke
parents:
diff changeset
2573 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2574
a61af66fc99e Initial load
duke
parents:
diff changeset
2575 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2576 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2577
a61af66fc99e Initial load
duke
parents:
diff changeset
2578 Register Rdividend = reg_to_register_object($src1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2579 int divisor = $imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2580 Register Rresult = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2581
a61af66fc99e Initial load
duke
parents:
diff changeset
2582 __ sra(Rdividend, 0, Rdividend);
a61af66fc99e Initial load
duke
parents:
diff changeset
2583 __ sdivx(Rdividend, divisor, Rresult);
a61af66fc99e Initial load
duke
parents:
diff changeset
2584 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2585
a61af66fc99e Initial load
duke
parents:
diff changeset
2586 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2587 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2588 Register Rsrc1 = reg_to_register_object($src1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2589 Register Rsrc2 = reg_to_register_object($src2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2590 Register Rdst = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2591
a61af66fc99e Initial load
duke
parents:
diff changeset
2592 __ sra( Rsrc1, 0, Rsrc1 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2593 __ sra( Rsrc2, 0, Rsrc2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2594 __ mulx( Rsrc1, Rsrc2, Rdst );
a61af66fc99e Initial load
duke
parents:
diff changeset
2595 __ srlx( Rdst, 32, Rdst );
a61af66fc99e Initial load
duke
parents:
diff changeset
2596 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2597
a61af66fc99e Initial load
duke
parents:
diff changeset
2598 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2599 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2600 Register Rdividend = reg_to_register_object($src1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2601 Register Rdivisor = reg_to_register_object($src2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2602 Register Rresult = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2603 Register Rscratch = reg_to_register_object($scratch$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2604
a61af66fc99e Initial load
duke
parents:
diff changeset
2605 assert(Rdividend != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2606 assert(Rdivisor != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2607
a61af66fc99e Initial load
duke
parents:
diff changeset
2608 __ sra(Rdividend, 0, Rdividend);
a61af66fc99e Initial load
duke
parents:
diff changeset
2609 __ sra(Rdivisor, 0, Rdivisor);
a61af66fc99e Initial load
duke
parents:
diff changeset
2610 __ sdivx(Rdividend, Rdivisor, Rscratch);
a61af66fc99e Initial load
duke
parents:
diff changeset
2611 __ mulx(Rscratch, Rdivisor, Rscratch);
a61af66fc99e Initial load
duke
parents:
diff changeset
2612 __ sub(Rdividend, Rscratch, Rresult);
a61af66fc99e Initial load
duke
parents:
diff changeset
2613 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2614
a61af66fc99e Initial load
duke
parents:
diff changeset
2615 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2616 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2617
a61af66fc99e Initial load
duke
parents:
diff changeset
2618 Register Rdividend = reg_to_register_object($src1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2619 int divisor = $imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2620 Register Rresult = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2621 Register Rscratch = reg_to_register_object($scratch$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2622
a61af66fc99e Initial load
duke
parents:
diff changeset
2623 assert(Rdividend != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2624
a61af66fc99e Initial load
duke
parents:
diff changeset
2625 __ sra(Rdividend, 0, Rdividend);
a61af66fc99e Initial load
duke
parents:
diff changeset
2626 __ sdivx(Rdividend, divisor, Rscratch);
a61af66fc99e Initial load
duke
parents:
diff changeset
2627 __ mulx(Rscratch, divisor, Rscratch);
a61af66fc99e Initial load
duke
parents:
diff changeset
2628 __ sub(Rdividend, Rscratch, Rresult);
a61af66fc99e Initial load
duke
parents:
diff changeset
2629 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2630
a61af66fc99e Initial load
duke
parents:
diff changeset
2631 enc_class fabss (sflt_reg dst, sflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2632 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2633
a61af66fc99e Initial load
duke
parents:
diff changeset
2634 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2635 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2636
a61af66fc99e Initial load
duke
parents:
diff changeset
2637 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2638 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2639
a61af66fc99e Initial load
duke
parents:
diff changeset
2640 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2641 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2642
a61af66fc99e Initial load
duke
parents:
diff changeset
2643 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2644 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2645
a61af66fc99e Initial load
duke
parents:
diff changeset
2646 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2647 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2648
a61af66fc99e Initial load
duke
parents:
diff changeset
2649 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2650 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2651
a61af66fc99e Initial load
duke
parents:
diff changeset
2652 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2653 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2654
a61af66fc99e Initial load
duke
parents:
diff changeset
2655 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2656 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2657
a61af66fc99e Initial load
duke
parents:
diff changeset
2658 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2659 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2660
a61af66fc99e Initial load
duke
parents:
diff changeset
2661 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2662 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2663
a61af66fc99e Initial load
duke
parents:
diff changeset
2664 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2665 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2666
a61af66fc99e Initial load
duke
parents:
diff changeset
2667 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2668 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2669
a61af66fc99e Initial load
duke
parents:
diff changeset
2670 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2671 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2672
a61af66fc99e Initial load
duke
parents:
diff changeset
2673 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2674 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2675
a61af66fc99e Initial load
duke
parents:
diff changeset
2676 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2677 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2678
a61af66fc99e Initial load
duke
parents:
diff changeset
2679 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2680 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2681
a61af66fc99e Initial load
duke
parents:
diff changeset
2682 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2683 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2684
a61af66fc99e Initial load
duke
parents:
diff changeset
2685 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2686 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2687
a61af66fc99e Initial load
duke
parents:
diff changeset
2688 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2689 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2690
a61af66fc99e Initial load
duke
parents:
diff changeset
2691 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2692 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2693
a61af66fc99e Initial load
duke
parents:
diff changeset
2694 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2695 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2696
a61af66fc99e Initial load
duke
parents:
diff changeset
2697 Register Roop = reg_to_register_object($oop$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2698 Register Rbox = reg_to_register_object($box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2699 Register Rscratch = reg_to_register_object($scratch$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2700 Register Rmark = reg_to_register_object($scratch2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2701
a61af66fc99e Initial load
duke
parents:
diff changeset
2702 assert(Roop != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2703 assert(Roop != Rmark, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2704 assert(Rbox != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2705 assert(Rbox != Rmark, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2706
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2707 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2708 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2709
a61af66fc99e Initial load
duke
parents:
diff changeset
2710 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2711 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2712
a61af66fc99e Initial load
duke
parents:
diff changeset
2713 Register Roop = reg_to_register_object($oop$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2714 Register Rbox = reg_to_register_object($box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2715 Register Rscratch = reg_to_register_object($scratch$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2716 Register Rmark = reg_to_register_object($scratch2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2717
a61af66fc99e Initial load
duke
parents:
diff changeset
2718 assert(Roop != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2719 assert(Roop != Rmark, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2720 assert(Rbox != Rscratch, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2721 assert(Rbox != Rmark, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
2722
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2723 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2724 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2725
a61af66fc99e Initial load
duke
parents:
diff changeset
2726 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2727 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2728 Register Rmem = reg_to_register_object($mem$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2729 Register Rold = reg_to_register_object($old$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2730 Register Rnew = reg_to_register_object($new$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2731
a61af66fc99e Initial load
duke
parents:
diff changeset
2732 // casx_under_lock picks 1 of 3 encodings:
a61af66fc99e Initial load
duke
parents:
diff changeset
2733 // For 32-bit pointers you get a 32-bit CAS
a61af66fc99e Initial load
duke
parents:
diff changeset
2734 // For 64-bit pointers you get a 64-bit CASX
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2735 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2736 __ cmp( Rold, Rnew );
a61af66fc99e Initial load
duke
parents:
diff changeset
2737 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2738
a61af66fc99e Initial load
duke
parents:
diff changeset
2739 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2740 Register Rmem = reg_to_register_object($mem$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2741 Register Rold = reg_to_register_object($old$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2742 Register Rnew = reg_to_register_object($new$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2743
a61af66fc99e Initial load
duke
parents:
diff changeset
2744 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2745 __ mov(Rnew, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2746 __ casx(Rmem, Rold, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2747 __ cmp( Rold, O7 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2748 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2749
a61af66fc99e Initial load
duke
parents:
diff changeset
2750 // raw int cas, used for compareAndSwap
a61af66fc99e Initial load
duke
parents:
diff changeset
2751 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2752 Register Rmem = reg_to_register_object($mem$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2753 Register Rold = reg_to_register_object($old$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2754 Register Rnew = reg_to_register_object($new$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2755
a61af66fc99e Initial load
duke
parents:
diff changeset
2756 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2757 __ mov(Rnew, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2758 __ cas(Rmem, Rold, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2759 __ cmp( Rold, O7 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2760 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2761
a61af66fc99e Initial load
duke
parents:
diff changeset
2762 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2763 Register Rres = reg_to_register_object($res$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2764
a61af66fc99e Initial load
duke
parents:
diff changeset
2765 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2766 __ mov(1, Rres);
a61af66fc99e Initial load
duke
parents:
diff changeset
2767 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
a61af66fc99e Initial load
duke
parents:
diff changeset
2768 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2769
a61af66fc99e Initial load
duke
parents:
diff changeset
2770 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2771 Register Rres = reg_to_register_object($res$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2772
a61af66fc99e Initial load
duke
parents:
diff changeset
2773 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2774 __ mov(1, Rres);
a61af66fc99e Initial load
duke
parents:
diff changeset
2775 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
a61af66fc99e Initial load
duke
parents:
diff changeset
2776 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2777
a61af66fc99e Initial load
duke
parents:
diff changeset
2778 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2779 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2780 Register Rdst = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2781 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2782 : reg_to_DoubleFloatRegister_object($src1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2783 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2784 : reg_to_DoubleFloatRegister_object($src2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2785
a61af66fc99e Initial load
duke
parents:
diff changeset
2786 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
a61af66fc99e Initial load
duke
parents:
diff changeset
2787 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
a61af66fc99e Initial load
duke
parents:
diff changeset
2788 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2789
a61af66fc99e Initial load
duke
parents:
diff changeset
2790 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2791 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2792 Register dest = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2793 Register temp = reg_to_register_object($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2794 __ set64( $src$$constant, dest, temp );
a61af66fc99e Initial load
duke
parents:
diff changeset
2795 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2796
a61af66fc99e Initial load
duke
parents:
diff changeset
2797 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2798 // Load a constant replicated "count" times with width "width"
a61af66fc99e Initial load
duke
parents:
diff changeset
2799 int bit_width = $width$$constant * 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2800 jlong elt_val = $src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2801 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
a61af66fc99e Initial load
duke
parents:
diff changeset
2802 jlong val = elt_val;
a61af66fc99e Initial load
duke
parents:
diff changeset
2803 for (int i = 0; i < $count$$constant - 1; i++) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2804 val <<= bit_width;
a61af66fc99e Initial load
duke
parents:
diff changeset
2805 val |= elt_val;
a61af66fc99e Initial load
duke
parents:
diff changeset
2806 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2807 jdouble dval = *(jdouble*)&val; // coerce to double type
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2808 MacroAssembler _masm(&cbuf);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2809 address double_address = __ double_constant(dval);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2810 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2811 AddressLiteral addrlit(double_address, rspec);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2812
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2813 __ sethi(addrlit, $tmp$$Register);
732
fb4c18a2ec66 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 727
diff changeset
2814 // XXX This is a quick fix for 6833573.
fb4c18a2ec66 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 727
diff changeset
2815 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
fb4c18a2ec66 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 727
diff changeset
2816 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2817 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2818
a61af66fc99e Initial load
duke
parents:
diff changeset
2819 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
a61af66fc99e Initial load
duke
parents:
diff changeset
2820 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2821 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2822 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2823 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2824 Register base_pointer_arg = reg_to_register_object($base$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2825
a61af66fc99e Initial load
duke
parents:
diff changeset
2826 Label loop;
a61af66fc99e Initial load
duke
parents:
diff changeset
2827 __ mov(nof_bytes_arg, nof_bytes_tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
2828
a61af66fc99e Initial load
duke
parents:
diff changeset
2829 // Loop and clear, walking backwards through the array.
a61af66fc99e Initial load
duke
parents:
diff changeset
2830 // nof_bytes_tmp (if >0) is always the number of bytes to zero
a61af66fc99e Initial load
duke
parents:
diff changeset
2831 __ bind(loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2832 __ deccc(nof_bytes_tmp, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
2833 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2834 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
2835 // %%%% this mini-loop must not cross a cache boundary!
a61af66fc99e Initial load
duke
parents:
diff changeset
2836 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2837
a61af66fc99e Initial load
duke
parents:
diff changeset
2838
a61af66fc99e Initial load
duke
parents:
diff changeset
2839 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2840 Label Ldone, Lloop;
a61af66fc99e Initial load
duke
parents:
diff changeset
2841 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2842
a61af66fc99e Initial load
duke
parents:
diff changeset
2843 Register str1_reg = reg_to_register_object($str1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2844 Register str2_reg = reg_to_register_object($str2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2845 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2846 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2847 Register result_reg = reg_to_register_object($result$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2848
a61af66fc99e Initial load
duke
parents:
diff changeset
2849 // Get the first character position in both strings
a61af66fc99e Initial load
duke
parents:
diff changeset
2850 // [8] char array, [12] offset, [16] count
a61af66fc99e Initial load
duke
parents:
diff changeset
2851 int value_offset = java_lang_String:: value_offset_in_bytes();
a61af66fc99e Initial load
duke
parents:
diff changeset
2852 int offset_offset = java_lang_String::offset_offset_in_bytes();
a61af66fc99e Initial load
duke
parents:
diff changeset
2853 int count_offset = java_lang_String:: count_offset_in_bytes();
a61af66fc99e Initial load
duke
parents:
diff changeset
2854
a61af66fc99e Initial load
duke
parents:
diff changeset
2855 // load str1 (jchar*) base address into tmp1_reg
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2856 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2857 __ ld(str1_reg, offset_offset, result_reg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2858 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2859 __ ld(str1_reg, count_offset, str1_reg); // hoisted
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2860 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2861 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2862 __ add(result_reg, tmp1_reg, tmp1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2863
a61af66fc99e Initial load
duke
parents:
diff changeset
2864 // load str2 (jchar*) base address into tmp2_reg
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2865 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2866 __ ld(str2_reg, offset_offset, result_reg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2867 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2868 __ ld(str2_reg, count_offset, str2_reg); // hoisted
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2869 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2870 __ subcc(str1_reg, str2_reg, O7); // hoisted
a61af66fc99e Initial load
duke
parents:
diff changeset
2871 __ add(result_reg, tmp2_reg, tmp2_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2872
a61af66fc99e Initial load
duke
parents:
diff changeset
2873 // Compute the minimum of the string lengths(str1_reg) and the
a61af66fc99e Initial load
duke
parents:
diff changeset
2874 // difference of the string lengths (stack)
a61af66fc99e Initial load
duke
parents:
diff changeset
2875
a61af66fc99e Initial load
duke
parents:
diff changeset
2876 // discard string base pointers, after loading up the lengths
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2877 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2878 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2879
a61af66fc99e Initial load
duke
parents:
diff changeset
2880 // See if the lengths are different, and calculate min in str1_reg.
a61af66fc99e Initial load
duke
parents:
diff changeset
2881 // Stash diff in O7 in case we need it for a tie-breaker.
a61af66fc99e Initial load
duke
parents:
diff changeset
2882 Label Lskip;
a61af66fc99e Initial load
duke
parents:
diff changeset
2883 // __ subcc(str1_reg, str2_reg, O7); // hoisted
a61af66fc99e Initial load
duke
parents:
diff changeset
2884 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
a61af66fc99e Initial load
duke
parents:
diff changeset
2885 __ br(Assembler::greater, true, Assembler::pt, Lskip);
a61af66fc99e Initial load
duke
parents:
diff changeset
2886 // str2 is shorter, so use its count:
a61af66fc99e Initial load
duke
parents:
diff changeset
2887 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
a61af66fc99e Initial load
duke
parents:
diff changeset
2888 __ bind(Lskip);
a61af66fc99e Initial load
duke
parents:
diff changeset
2889
a61af66fc99e Initial load
duke
parents:
diff changeset
2890 // reallocate str1_reg, str2_reg, result_reg
a61af66fc99e Initial load
duke
parents:
diff changeset
2891 // Note: limit_reg holds the string length pre-scaled by 2
a61af66fc99e Initial load
duke
parents:
diff changeset
2892 Register limit_reg = str1_reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2893 Register chr2_reg = str2_reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2894 Register chr1_reg = result_reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2895 // tmp{12} are the base pointers
a61af66fc99e Initial load
duke
parents:
diff changeset
2896
a61af66fc99e Initial load
duke
parents:
diff changeset
2897 // Is the minimum length zero?
a61af66fc99e Initial load
duke
parents:
diff changeset
2898 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
a61af66fc99e Initial load
duke
parents:
diff changeset
2899 __ br(Assembler::equal, true, Assembler::pn, Ldone);
a61af66fc99e Initial load
duke
parents:
diff changeset
2900 __ delayed()->mov(O7, result_reg); // result is difference in lengths
a61af66fc99e Initial load
duke
parents:
diff changeset
2901
a61af66fc99e Initial load
duke
parents:
diff changeset
2902 // Load first characters
a61af66fc99e Initial load
duke
parents:
diff changeset
2903 __ lduh(tmp1_reg, 0, chr1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2904 __ lduh(tmp2_reg, 0, chr2_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2905
a61af66fc99e Initial load
duke
parents:
diff changeset
2906 // Compare first characters
a61af66fc99e Initial load
duke
parents:
diff changeset
2907 __ subcc(chr1_reg, chr2_reg, chr1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2908 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
a61af66fc99e Initial load
duke
parents:
diff changeset
2909 assert(chr1_reg == result_reg, "result must be pre-placed");
a61af66fc99e Initial load
duke
parents:
diff changeset
2910 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2911
a61af66fc99e Initial load
duke
parents:
diff changeset
2912 {
a61af66fc99e Initial load
duke
parents:
diff changeset
2913 // Check after comparing first character to see if strings are equivalent
a61af66fc99e Initial load
duke
parents:
diff changeset
2914 Label LSkip2;
a61af66fc99e Initial load
duke
parents:
diff changeset
2915 // Check if the strings start at same location
a61af66fc99e Initial load
duke
parents:
diff changeset
2916 __ cmp(tmp1_reg, tmp2_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2917 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2918 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2919
a61af66fc99e Initial load
duke
parents:
diff changeset
2920 // Check if the length difference is zero (in O7)
a61af66fc99e Initial load
duke
parents:
diff changeset
2921 __ cmp(G0, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2922 __ br(Assembler::equal, true, Assembler::pn, Ldone);
a61af66fc99e Initial load
duke
parents:
diff changeset
2923 __ delayed()->mov(G0, result_reg); // result is zero
a61af66fc99e Initial load
duke
parents:
diff changeset
2924
a61af66fc99e Initial load
duke
parents:
diff changeset
2925 // Strings might not be equal
a61af66fc99e Initial load
duke
parents:
diff changeset
2926 __ bind(LSkip2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2927 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2928
a61af66fc99e Initial load
duke
parents:
diff changeset
2929 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2930 __ br(Assembler::equal, true, Assembler::pn, Ldone);
a61af66fc99e Initial load
duke
parents:
diff changeset
2931 __ delayed()->mov(O7, result_reg); // result is difference in lengths
a61af66fc99e Initial load
duke
parents:
diff changeset
2932
a61af66fc99e Initial load
duke
parents:
diff changeset
2933 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
a61af66fc99e Initial load
duke
parents:
diff changeset
2934 __ add(tmp1_reg, limit_reg, tmp1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2935 __ add(tmp2_reg, limit_reg, tmp2_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2936 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
a61af66fc99e Initial load
duke
parents:
diff changeset
2937
a61af66fc99e Initial load
duke
parents:
diff changeset
2938 // Compare the rest of the characters
a61af66fc99e Initial load
duke
parents:
diff changeset
2939 __ lduh(tmp1_reg, limit_reg, chr1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2940 __ bind(Lloop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2941 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
a61af66fc99e Initial load
duke
parents:
diff changeset
2942 __ lduh(tmp2_reg, limit_reg, chr2_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2943 __ subcc(chr1_reg, chr2_reg, chr1_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2944 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
a61af66fc99e Initial load
duke
parents:
diff changeset
2945 assert(chr1_reg == result_reg, "result must be pre-placed");
a61af66fc99e Initial load
duke
parents:
diff changeset
2946 __ delayed()->inccc(limit_reg, sizeof(jchar));
a61af66fc99e Initial load
duke
parents:
diff changeset
2947 // annul LDUH if branch is not taken to prevent access past end of string
a61af66fc99e Initial load
duke
parents:
diff changeset
2948 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2949 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
a61af66fc99e Initial load
duke
parents:
diff changeset
2950
a61af66fc99e Initial load
duke
parents:
diff changeset
2951 // If strings are equal up to min length, return the length difference.
a61af66fc99e Initial load
duke
parents:
diff changeset
2952 __ mov(O7, result_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2953
a61af66fc99e Initial load
duke
parents:
diff changeset
2954 // Otherwise, return the difference between the first mismatched chars.
a61af66fc99e Initial load
duke
parents:
diff changeset
2955 __ bind(Ldone);
a61af66fc99e Initial load
duke
parents:
diff changeset
2956 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2957
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2958 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2959 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2960 MacroAssembler _masm(&cbuf);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2961
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2962 Register str1_reg = reg_to_register_object($str1$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2963 Register str2_reg = reg_to_register_object($str2$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2964 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2965 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2966 Register result_reg = reg_to_register_object($result$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2967
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2968 // Get the first character position in both strings
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2969 // [8] char array, [12] offset, [16] count
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2970 int value_offset = java_lang_String:: value_offset_in_bytes();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2971 int offset_offset = java_lang_String::offset_offset_in_bytes();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2972 int count_offset = java_lang_String:: count_offset_in_bytes();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2973
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2974 // load str1 (jchar*) base address into tmp1_reg
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2975 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2976 __ ld(Address(str1_reg, offset_offset), result_reg);
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2977 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2978 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2979 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2980 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2981 __ add(result_reg, tmp1_reg, tmp1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2982
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2983 // load str2 (jchar*) base address into tmp2_reg
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2984 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2985 __ ld(Address(str2_reg, offset_offset), result_reg);
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2986 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
2987 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2988 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2989 __ cmp(str1_reg, str2_reg); // hoisted
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2990 __ add(result_reg, tmp2_reg, tmp2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2991
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2992 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2993 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2994 __ delayed()->mov(G0, result_reg); // not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2995
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2996 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2997 __ delayed()->add(G0, 1, result_reg); //equals
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2998
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
2999 __ cmp(tmp1_reg, tmp2_reg); //same string ?
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3000 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3001 __ delayed()->add(G0, 1, result_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3002
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3003 //rename registers
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3004 Register limit_reg = str1_reg;
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3005 Register chr2_reg = str2_reg;
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3006 Register chr1_reg = result_reg;
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3007 // tmp{12} are the base pointers
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3008
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3009 //check for alignment and position the pointers to the ends
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3010 __ or3(tmp1_reg, tmp2_reg, chr1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3011 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3012 __ br(Assembler::notZero, false, Assembler::pn, Lchar);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3013 __ delayed()->nop();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3014
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3015 __ bind(Lword);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3016 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3017 __ andn(limit_reg, 0x3, limit_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3018 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3019 __ delayed()->nop();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3020
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3021 __ add(tmp1_reg, limit_reg, tmp1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3022 __ add(tmp2_reg, limit_reg, tmp2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3023 __ neg(limit_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3024
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3025 __ lduw(tmp1_reg, limit_reg, chr1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3026 __ bind(Lword_loop);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3027 __ lduw(tmp2_reg, limit_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3028 __ cmp(chr1_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3029 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3030 __ delayed()->mov(G0, result_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3031 __ inccc(limit_reg, 2*sizeof(jchar));
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3032 // annul LDUW if branch i s not taken to prevent access past end of string
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3033 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3034 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3035
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3036 __ bind(Lpost_word);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3037 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3038 __ delayed()->add(G0, 1, result_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3039
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3040 __ lduh(tmp1_reg, 0, chr1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3041 __ lduh(tmp2_reg, 0, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3042 __ cmp (chr1_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3043 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3044 __ delayed()->mov(G0, result_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3045 __ ba(false,Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3046 __ delayed()->add(G0, 1, result_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3047
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3048 __ bind(Lchar);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3049 __ add(tmp1_reg, limit_reg, tmp1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3050 __ add(tmp2_reg, limit_reg, tmp2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3051 __ neg(limit_reg); //negate count
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3052
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3053 __ lduh(tmp1_reg, limit_reg, chr1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3054 __ bind(Lchar_loop);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3055 __ lduh(tmp2_reg, limit_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3056 __ cmp(chr1_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3057 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3058 __ delayed()->mov(G0, result_reg); //not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3059 __ inccc(limit_reg, sizeof(jchar));
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3060 // annul LDUH if branch is not taken to prevent access past end of string
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3061 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3062 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3063
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3064 __ add(G0, 1, result_reg); //equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3065
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3066 __ bind(Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3067 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3068
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3069 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3070 Label Lvector, Ldone, Lloop;
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3071 MacroAssembler _masm(&cbuf);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3072
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3073 Register ary1_reg = reg_to_register_object($ary1$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3074 Register ary2_reg = reg_to_register_object($ary2$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3075 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3076 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3077 Register result_reg = reg_to_register_object($result$$reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3078
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3079 int length_offset = arrayOopDesc::length_offset_in_bytes();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3080 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3081
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3082 // return true if the same array
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3083 __ cmp(ary1_reg, ary2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3084 __ br(Assembler::equal, true, Assembler::pn, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3085 __ delayed()->add(G0, 1, result_reg); // equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3086
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3087 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3088 __ delayed()->mov(G0, result_reg); // not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3089
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3090 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3091 __ delayed()->mov(G0, result_reg); // not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3092
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3093 //load the lengths of arrays
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3094 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3095 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3096
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3097 // return false if the two arrays are not equal length
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3098 __ cmp(tmp1_reg, tmp2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3099 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3100 __ delayed()->mov(G0, result_reg); // not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3101
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3102 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3103 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3104
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3105 // load array addresses
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3106 __ add(ary1_reg, base_offset, ary1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3107 __ add(ary2_reg, base_offset, ary2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3108
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3109 // renaming registers
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3110 Register chr1_reg = tmp2_reg; // for characters in ary1
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3111 Register chr2_reg = result_reg; // for characters in ary2
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3112 Register limit_reg = tmp1_reg; // length
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3113
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3114 // set byte count
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3115 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3116 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3117 __ br(Assembler::zero, false, Assembler::pt, Lvector);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3118 __ delayed()->nop();
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3119
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3120 //compare the trailing char
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3121 __ sub(limit_reg, sizeof(jchar), limit_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3122 __ lduh(ary1_reg, limit_reg, chr1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3123 __ lduh(ary2_reg, limit_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3124 __ cmp(chr1_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3125 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3126 __ delayed()->mov(G0, result_reg); // not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3127
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3128 // only one char ?
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3129 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3130 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3131
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3132 __ bind(Lvector);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3133 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3134 __ add(ary1_reg, limit_reg, ary1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3135 __ add(ary2_reg, limit_reg, ary2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3136 __ neg(limit_reg, limit_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3137
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3138 __ lduw(ary1_reg, limit_reg, chr1_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3139 __ bind(Lloop);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3140 __ lduw(ary2_reg, limit_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3141 __ cmp(chr1_reg, chr2_reg);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3142 __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3143 __ delayed()->mov(G0, result_reg); // not equal
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3144 __ inccc(limit_reg, 2*sizeof(jchar));
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3145 // annul LDUW if branch is not taken to prevent access past end of string
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3146 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3147 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3148
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3149 __ add(G0, 1, result_reg); // equals
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3150
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3151 __ bind(Ldone);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3152 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
3153
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3154 enc_class enc_rethrow() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3155 cbuf.set_inst_mark();
a61af66fc99e Initial load
duke
parents:
diff changeset
3156 Register temp_reg = G3;
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3157 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3158 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
a61af66fc99e Initial load
duke
parents:
diff changeset
3159 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3160 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
3161 __ save_frame(0);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3162 AddressLiteral last_rethrow_addrlit(&last_rethrow);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3163 __ sethi(last_rethrow_addrlit, L1);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3164 Address addr(L1, last_rethrow_addrlit.low10());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3165 __ get_pc(L2);
a61af66fc99e Initial load
duke
parents:
diff changeset
3166 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3167 __ st_ptr(L2, addr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3168 __ restore();
a61af66fc99e Initial load
duke
parents:
diff changeset
3169 #endif
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
3170 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3171 __ delayed()->nop();
a61af66fc99e Initial load
duke
parents:
diff changeset
3172 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3173
a61af66fc99e Initial load
duke
parents:
diff changeset
3174 enc_class emit_mem_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3175 // Generates the instruction LDUXA [o6,g0],#0x82,g0
a61af66fc99e Initial load
duke
parents:
diff changeset
3176 unsigned int *code = (unsigned int*)cbuf.code_end();
a61af66fc99e Initial load
duke
parents:
diff changeset
3177 *code = (unsigned int)0xc0839040;
a61af66fc99e Initial load
duke
parents:
diff changeset
3178 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
3179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3180
a61af66fc99e Initial load
duke
parents:
diff changeset
3181 enc_class emit_fadd_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3182 // Generates the instruction FMOVS f31,f31
a61af66fc99e Initial load
duke
parents:
diff changeset
3183 unsigned int *code = (unsigned int*)cbuf.code_end();
a61af66fc99e Initial load
duke
parents:
diff changeset
3184 *code = (unsigned int)0xbfa0003f;
a61af66fc99e Initial load
duke
parents:
diff changeset
3185 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
3186 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3187
a61af66fc99e Initial load
duke
parents:
diff changeset
3188 enc_class emit_br_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3189 // Generates the instruction BPN,PN .
a61af66fc99e Initial load
duke
parents:
diff changeset
3190 unsigned int *code = (unsigned int*)cbuf.code_end();
a61af66fc99e Initial load
duke
parents:
diff changeset
3191 *code = (unsigned int)0x00400000;
a61af66fc99e Initial load
duke
parents:
diff changeset
3192 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
3193 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3194
a61af66fc99e Initial load
duke
parents:
diff changeset
3195 enc_class enc_membar_acquire %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3196 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3197 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
a61af66fc99e Initial load
duke
parents:
diff changeset
3198 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3199
a61af66fc99e Initial load
duke
parents:
diff changeset
3200 enc_class enc_membar_release %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3201 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3202 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
a61af66fc99e Initial load
duke
parents:
diff changeset
3203 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3204
a61af66fc99e Initial load
duke
parents:
diff changeset
3205 enc_class enc_membar_volatile %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3206 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3207 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
a61af66fc99e Initial load
duke
parents:
diff changeset
3208 %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3209
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3210 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3211 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3212 Register src_reg = reg_to_register_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3213 Register dst_reg = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3214 __ sllx(src_reg, 56, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3215 __ srlx(dst_reg, 8, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3216 __ or3 (dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3217 __ srlx(dst_reg, 16, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3218 __ or3 (dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3219 __ srlx(dst_reg, 32, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3220 __ or3 (dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3221 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3222
a61af66fc99e Initial load
duke
parents:
diff changeset
3223 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3224 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3225 Register src_reg = reg_to_register_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3226 Register dst_reg = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3227 __ sll(src_reg, 24, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3228 __ srl(dst_reg, 8, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3229 __ or3(dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3230 __ srl(dst_reg, 16, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3231 __ or3(dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3232 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3233
a61af66fc99e Initial load
duke
parents:
diff changeset
3234 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3235 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3236 Register src_reg = reg_to_register_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3237 Register dst_reg = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3238 __ sllx(src_reg, 48, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3239 __ srlx(dst_reg, 16, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3240 __ or3 (dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3241 __ srlx(dst_reg, 32, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3242 __ or3 (dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3243 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3244
a61af66fc99e Initial load
duke
parents:
diff changeset
3245 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3246 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3247 Register src_reg = reg_to_register_object($src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3248 Register dst_reg = reg_to_register_object($dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3249 __ sllx(src_reg, 32, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3250 __ srlx(dst_reg, 32, O7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3251 __ or3 (dst_reg, O7, dst_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3252 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3253
a61af66fc99e Initial load
duke
parents:
diff changeset
3254 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3255
a61af66fc99e Initial load
duke
parents:
diff changeset
3256 //----------FRAME--------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3257 // Definition of frame structure and management information.
a61af66fc99e Initial load
duke
parents:
diff changeset
3258 //
a61af66fc99e Initial load
duke
parents:
diff changeset
3259 // S T A C K L A Y O U T Allocators stack-slot number
a61af66fc99e Initial load
duke
parents:
diff changeset
3260 // | (to get allocators register number
a61af66fc99e Initial load
duke
parents:
diff changeset
3261 // G Owned by | | v add VMRegImpl::stack0)
a61af66fc99e Initial load
duke
parents:
diff changeset
3262 // r CALLER | |
a61af66fc99e Initial load
duke
parents:
diff changeset
3263 // o | +--------+ pad to even-align allocators stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
3264 // w V | pad0 | numbers; owned by CALLER
a61af66fc99e Initial load
duke
parents:
diff changeset
3265 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3266 // h ^ | in | 5
a61af66fc99e Initial load
duke
parents:
diff changeset
3267 // | | args | 4 Holes in incoming args owned by SELF
a61af66fc99e Initial load
duke
parents:
diff changeset
3268 // | | | | 3
a61af66fc99e Initial load
duke
parents:
diff changeset
3269 // | | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3270 // V | | old out| Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
3271 // | old |preserve| Must be even aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
3272 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3273 // | | in | 3 area for Intel ret address
a61af66fc99e Initial load
duke
parents:
diff changeset
3274 // Owned by |preserve| Empty on Sparc.
a61af66fc99e Initial load
duke
parents:
diff changeset
3275 // SELF +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3276 // | | pad2 | 2 pad to align old SP
a61af66fc99e Initial load
duke
parents:
diff changeset
3277 // | +--------+ 1
a61af66fc99e Initial load
duke
parents:
diff changeset
3278 // | | locks | 0
a61af66fc99e Initial load
duke
parents:
diff changeset
3279 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3280 // | | pad1 | 11 pad to align new SP
a61af66fc99e Initial load
duke
parents:
diff changeset
3281 // | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3282 // | | | 10
a61af66fc99e Initial load
duke
parents:
diff changeset
3283 // | | spills | 9 spills
a61af66fc99e Initial load
duke
parents:
diff changeset
3284 // V | | 8 (pad0 slot for callee)
a61af66fc99e Initial load
duke
parents:
diff changeset
3285 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3286 // ^ | out | 7
a61af66fc99e Initial load
duke
parents:
diff changeset
3287 // | | args | 6 Holes in outgoing args owned by CALLEE
a61af66fc99e Initial load
duke
parents:
diff changeset
3288 // Owned by +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3289 // CALLEE | new out| 6 Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
3290 // | new |preserve| Must be even-aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
3291 // | SP-+--------+----> Matcher::_new_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3292 // | | |
a61af66fc99e Initial load
duke
parents:
diff changeset
3293 //
a61af66fc99e Initial load
duke
parents:
diff changeset
3294 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
3295 // known from SELF's arguments and the Java calling convention.
a61af66fc99e Initial load
duke
parents:
diff changeset
3296 // Region 6-7 is determined per call site.
a61af66fc99e Initial load
duke
parents:
diff changeset
3297 // Note 2: If the calling convention leaves holes in the incoming argument
a61af66fc99e Initial load
duke
parents:
diff changeset
3298 // area, those holes are owned by SELF. Holes in the outgoing area
a61af66fc99e Initial load
duke
parents:
diff changeset
3299 // are owned by the CALLEE. Holes should not be nessecary in the
a61af66fc99e Initial load
duke
parents:
diff changeset
3300 // incoming area, as the Java calling convention is completely under
a61af66fc99e Initial load
duke
parents:
diff changeset
3301 // the control of the AD file. Doubles can be sorted and packed to
a61af66fc99e Initial load
duke
parents:
diff changeset
3302 // avoid holes. Holes in the outgoing arguments may be nessecary for
a61af66fc99e Initial load
duke
parents:
diff changeset
3303 // varargs C calling conventions.
a61af66fc99e Initial load
duke
parents:
diff changeset
3304 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
3305 // even aligned with pad0 as needed.
a61af66fc99e Initial load
duke
parents:
diff changeset
3306 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
a61af66fc99e Initial load
duke
parents:
diff changeset
3307 // region 6-11 is even aligned; it may be padded out more so that
a61af66fc99e Initial load
duke
parents:
diff changeset
3308 // the region from SP to FP meets the minimum stack alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
3309
a61af66fc99e Initial load
duke
parents:
diff changeset
3310 frame %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3311 // What direction does stack grow in (assumed to be same for native & Java)
a61af66fc99e Initial load
duke
parents:
diff changeset
3312 stack_direction(TOWARDS_LOW);
a61af66fc99e Initial load
duke
parents:
diff changeset
3313
a61af66fc99e Initial load
duke
parents:
diff changeset
3314 // These two registers define part of the calling convention
a61af66fc99e Initial load
duke
parents:
diff changeset
3315 // between compiled code and the interpreter.
a61af66fc99e Initial load
duke
parents:
diff changeset
3316 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
a61af66fc99e Initial load
duke
parents:
diff changeset
3317 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
3318
a61af66fc99e Initial load
duke
parents:
diff changeset
3319 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
3320 cisc_spilling_operand_name(indOffset);
a61af66fc99e Initial load
duke
parents:
diff changeset
3321
a61af66fc99e Initial load
duke
parents:
diff changeset
3322 // Number of stack slots consumed by a Monitor enter
a61af66fc99e Initial load
duke
parents:
diff changeset
3323 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
3324 sync_stack_slots(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
3325 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
3326 sync_stack_slots(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3327 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
3328
a61af66fc99e Initial load
duke
parents:
diff changeset
3329 // Compiled code's Frame Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
3330 frame_pointer(R_SP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3331
a61af66fc99e Initial load
duke
parents:
diff changeset
3332 // Stack alignment requirement
a61af66fc99e Initial load
duke
parents:
diff changeset
3333 stack_alignment(StackAlignmentInBytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
3334 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
a61af66fc99e Initial load
duke
parents:
diff changeset
3335 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
a61af66fc99e Initial load
duke
parents:
diff changeset
3336
a61af66fc99e Initial load
duke
parents:
diff changeset
3337 // Number of stack slots between incoming argument block and the start of
a61af66fc99e Initial load
duke
parents:
diff changeset
3338 // a new frame. The PROLOG must add this many slots to the stack. The
a61af66fc99e Initial load
duke
parents:
diff changeset
3339 // EPILOG must remove this many slots.
a61af66fc99e Initial load
duke
parents:
diff changeset
3340 in_preserve_stack_slots(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3341
a61af66fc99e Initial load
duke
parents:
diff changeset
3342 // Number of outgoing stack slots killed above the out_preserve_stack_slots
a61af66fc99e Initial load
duke
parents:
diff changeset
3343 // for calls to C. Supports the var-args backing area for register parms.
a61af66fc99e Initial load
duke
parents:
diff changeset
3344 // ADLC doesn't support parsing expressions, so I folded the math by hand.
a61af66fc99e Initial load
duke
parents:
diff changeset
3345 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
3346 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
a61af66fc99e Initial load
duke
parents:
diff changeset
3347 varargs_C_out_slots_killed(12);
a61af66fc99e Initial load
duke
parents:
diff changeset
3348 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
3349 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
a61af66fc99e Initial load
duke
parents:
diff changeset
3350 varargs_C_out_slots_killed( 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3351 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
3352
a61af66fc99e Initial load
duke
parents:
diff changeset
3353 // The after-PROLOG location of the return address. Location of
a61af66fc99e Initial load
duke
parents:
diff changeset
3354 // return address specifies a type (REG or STACK) and a number
a61af66fc99e Initial load
duke
parents:
diff changeset
3355 // representing the register number (i.e. - use a register name) or
a61af66fc99e Initial load
duke
parents:
diff changeset
3356 // stack slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
3357 return_addr(REG R_I7); // Ret Addr is in register I7
a61af66fc99e Initial load
duke
parents:
diff changeset
3358
a61af66fc99e Initial load
duke
parents:
diff changeset
3359 // Body of function which returns an OptoRegs array locating
a61af66fc99e Initial load
duke
parents:
diff changeset
3360 // arguments either in registers or in stack slots for calling
a61af66fc99e Initial load
duke
parents:
diff changeset
3361 // java
a61af66fc99e Initial load
duke
parents:
diff changeset
3362 calling_convention %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3363 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
a61af66fc99e Initial load
duke
parents:
diff changeset
3364
a61af66fc99e Initial load
duke
parents:
diff changeset
3365 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3366
a61af66fc99e Initial load
duke
parents:
diff changeset
3367 // Body of function which returns an OptoRegs array locating
a61af66fc99e Initial load
duke
parents:
diff changeset
3368 // arguments either in registers or in stack slots for callin
a61af66fc99e Initial load
duke
parents:
diff changeset
3369 // C.
a61af66fc99e Initial load
duke
parents:
diff changeset
3370 c_calling_convention %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3371 // This is obviously always outgoing
a61af66fc99e Initial load
duke
parents:
diff changeset
3372 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
a61af66fc99e Initial load
duke
parents:
diff changeset
3373 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3374
a61af66fc99e Initial load
duke
parents:
diff changeset
3375 // Location of native (C/C++) and interpreter return values. This is specified to
a61af66fc99e Initial load
duke
parents:
diff changeset
3376 // be the same as Java. In the 32-bit VM, long values are actually returned from
a61af66fc99e Initial load
duke
parents:
diff changeset
3377 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
a61af66fc99e Initial load
duke
parents:
diff changeset
3378 // to and from the register pairs is done by the appropriate call and epilog
a61af66fc99e Initial load
duke
parents:
diff changeset
3379 // opcodes. This simplifies the register allocator.
a61af66fc99e Initial load
duke
parents:
diff changeset
3380 c_return_value %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3381 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
a61af66fc99e Initial load
duke
parents:
diff changeset
3382 #ifdef _LP64
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3383 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3384 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3385 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3386 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3387 #else // !_LP64
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3388 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3389 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3390 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3391 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3392 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
3393 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
a61af66fc99e Initial load
duke
parents:
diff changeset
3394 (is_outgoing?lo_out:lo_in)[ideal_reg] );
a61af66fc99e Initial load
duke
parents:
diff changeset
3395 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3396
a61af66fc99e Initial load
duke
parents:
diff changeset
3397 // Location of compiled Java return values. Same as C
a61af66fc99e Initial load
duke
parents:
diff changeset
3398 return_value %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3399 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
a61af66fc99e Initial load
duke
parents:
diff changeset
3400 #ifdef _LP64
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3401 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3402 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3403 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3404 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3405 #else // !_LP64
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3406 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3407 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3408 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3409 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3410 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
3411 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
a61af66fc99e Initial load
duke
parents:
diff changeset
3412 (is_outgoing?lo_out:lo_in)[ideal_reg] );
a61af66fc99e Initial load
duke
parents:
diff changeset
3413 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3414
a61af66fc99e Initial load
duke
parents:
diff changeset
3415 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3416
a61af66fc99e Initial load
duke
parents:
diff changeset
3417
a61af66fc99e Initial load
duke
parents:
diff changeset
3418 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
3419 //----------Operand Attributes-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3420 op_attrib op_cost(1); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
3421
a61af66fc99e Initial load
duke
parents:
diff changeset
3422 //----------Instruction Attributes---------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3423 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
3424 ins_attrib ins_size(32); // Required size attribute (in bits)
a61af66fc99e Initial load
duke
parents:
diff changeset
3425 ins_attrib ins_pc_relative(0); // Required PC Relative flag
a61af66fc99e Initial load
duke
parents:
diff changeset
3426 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
a61af66fc99e Initial load
duke
parents:
diff changeset
3427 // non-matching short branch variant of some
a61af66fc99e Initial load
duke
parents:
diff changeset
3428 // long branch?
a61af66fc99e Initial load
duke
parents:
diff changeset
3429
a61af66fc99e Initial load
duke
parents:
diff changeset
3430 //----------OPERANDS-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3431 // Operand definitions must precede instruction definitions for correct parsing
a61af66fc99e Initial load
duke
parents:
diff changeset
3432 // in the ADLC because operands constitute user defined types which are used in
a61af66fc99e Initial load
duke
parents:
diff changeset
3433 // instruction definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
3434
a61af66fc99e Initial load
duke
parents:
diff changeset
3435 //----------Simple Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3436 // Immediate Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3437 // Integer Immediate: 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3438 operand immI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3439 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3440
a61af66fc99e Initial load
duke
parents:
diff changeset
3441 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3442 // formats are generated automatically for constants and base registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3443 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3444 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3445 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3446
a61af66fc99e Initial load
duke
parents:
diff changeset
3447 // Integer Immediate: 13-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3448 operand immI13() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3449 predicate(Assembler::is_simm13(n->get_int()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3450 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3451 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3452
a61af66fc99e Initial load
duke
parents:
diff changeset
3453 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3454 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3455 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3456
a61af66fc99e Initial load
duke
parents:
diff changeset
3457 // Unsigned (positive) Integer Immediate: 13-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3458 operand immU13() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3459 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3460 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3461 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3462
a61af66fc99e Initial load
duke
parents:
diff changeset
3463 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3464 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3465 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3466
a61af66fc99e Initial load
duke
parents:
diff changeset
3467 // Integer Immediate: 6-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3468 operand immU6() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3469 predicate(n->get_int() >= 0 && n->get_int() <= 63);
a61af66fc99e Initial load
duke
parents:
diff changeset
3470 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3471 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3472 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3473 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3474 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3475
a61af66fc99e Initial load
duke
parents:
diff changeset
3476 // Integer Immediate: 11-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3477 operand immI11() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3478 predicate(Assembler::is_simm(n->get_int(),11));
a61af66fc99e Initial load
duke
parents:
diff changeset
3479 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3480 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3481 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3482 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3483 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3484
a61af66fc99e Initial load
duke
parents:
diff changeset
3485 // Integer Immediate: 0-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3486 operand immI0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3487 predicate(n->get_int() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3488 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3489 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3490
a61af66fc99e Initial load
duke
parents:
diff changeset
3491 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3492 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3493 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3494
a61af66fc99e Initial load
duke
parents:
diff changeset
3495 // Integer Immediate: the value 10
a61af66fc99e Initial load
duke
parents:
diff changeset
3496 operand immI10() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3497 predicate(n->get_int() == 10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3498 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3499 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3500
a61af66fc99e Initial load
duke
parents:
diff changeset
3501 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3502 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3503 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3504
a61af66fc99e Initial load
duke
parents:
diff changeset
3505 // Integer Immediate: the values 0-31
a61af66fc99e Initial load
duke
parents:
diff changeset
3506 operand immU5() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3507 predicate(n->get_int() >= 0 && n->get_int() <= 31);
a61af66fc99e Initial load
duke
parents:
diff changeset
3508 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3509 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3510
a61af66fc99e Initial load
duke
parents:
diff changeset
3511 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3512 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3513 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3514
a61af66fc99e Initial load
duke
parents:
diff changeset
3515 // Integer Immediate: the values 1-31
a61af66fc99e Initial load
duke
parents:
diff changeset
3516 operand immI_1_31() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3517 predicate(n->get_int() >= 1 && n->get_int() <= 31);
a61af66fc99e Initial load
duke
parents:
diff changeset
3518 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3519 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3520
a61af66fc99e Initial load
duke
parents:
diff changeset
3521 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3522 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3523 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3524
a61af66fc99e Initial load
duke
parents:
diff changeset
3525 // Integer Immediate: the values 32-63
a61af66fc99e Initial load
duke
parents:
diff changeset
3526 operand immI_32_63() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3527 predicate(n->get_int() >= 32 && n->get_int() <= 63);
a61af66fc99e Initial load
duke
parents:
diff changeset
3528 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3529 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3530
a61af66fc99e Initial load
duke
parents:
diff changeset
3531 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3532 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3533 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3534
a61af66fc99e Initial load
duke
parents:
diff changeset
3535 // Integer Immediate: the value 255
a61af66fc99e Initial load
duke
parents:
diff changeset
3536 operand immI_255() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3537 predicate( n->get_int() == 255 );
a61af66fc99e Initial load
duke
parents:
diff changeset
3538 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3539 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3540
a61af66fc99e Initial load
duke
parents:
diff changeset
3541 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3542 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3543 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3544
a61af66fc99e Initial load
duke
parents:
diff changeset
3545 // Long Immediate: the value FF
a61af66fc99e Initial load
duke
parents:
diff changeset
3546 operand immL_FF() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3547 predicate( n->get_long() == 0xFFL );
a61af66fc99e Initial load
duke
parents:
diff changeset
3548 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3549 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3550
a61af66fc99e Initial load
duke
parents:
diff changeset
3551 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3552 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3553 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3554
a61af66fc99e Initial load
duke
parents:
diff changeset
3555 // Long Immediate: the value FFFF
a61af66fc99e Initial load
duke
parents:
diff changeset
3556 operand immL_FFFF() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3557 predicate( n->get_long() == 0xFFFFL );
a61af66fc99e Initial load
duke
parents:
diff changeset
3558 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3559 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3560
a61af66fc99e Initial load
duke
parents:
diff changeset
3561 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3562 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3563 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3564
a61af66fc99e Initial load
duke
parents:
diff changeset
3565 // Pointer Immediate: 32 or 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3566 operand immP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3567 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3568
a61af66fc99e Initial load
duke
parents:
diff changeset
3569 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3570 // formats are generated automatically for constants and base registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3571 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3572 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3573 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3574
a61af66fc99e Initial load
duke
parents:
diff changeset
3575 operand immP13() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3576 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
a61af66fc99e Initial load
duke
parents:
diff changeset
3577 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3578 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3579
a61af66fc99e Initial load
duke
parents:
diff changeset
3580 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3581 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3582 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3583
a61af66fc99e Initial load
duke
parents:
diff changeset
3584 operand immP0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3585 predicate(n->get_ptr() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3586 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3587 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3588
a61af66fc99e Initial load
duke
parents:
diff changeset
3589 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3590 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3591 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3592
a61af66fc99e Initial load
duke
parents:
diff changeset
3593 operand immP_poll() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3594 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
a61af66fc99e Initial load
duke
parents:
diff changeset
3595 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3596
a61af66fc99e Initial load
duke
parents:
diff changeset
3597 // formats are generated automatically for constants and base registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3598 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3599 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3600 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3601
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3602 // Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3603 operand immN()
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3604 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3605 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3606
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3607 op_cost(10);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3608 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3609 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3610 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3611
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3612 // NULL Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3613 operand immN0()
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3614 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3615 predicate(n->get_narrowcon() == 0);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3616 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3617
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3618 op_cost(0);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3619 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3620 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3621 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3622
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3623 operand immL() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3624 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3625 op_cost(40);
a61af66fc99e Initial load
duke
parents:
diff changeset
3626 // formats are generated automatically for constants and base registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3627 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3628 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3629 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3630
a61af66fc99e Initial load
duke
parents:
diff changeset
3631 operand immL0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3632 predicate(n->get_long() == 0L);
a61af66fc99e Initial load
duke
parents:
diff changeset
3633 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3634 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3635 // formats are generated automatically for constants and base registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3636 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3637 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3638 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3639
a61af66fc99e Initial load
duke
parents:
diff changeset
3640 // Long Immediate: 13-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3641 operand immL13() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3642 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
a61af66fc99e Initial load
duke
parents:
diff changeset
3643 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3644 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3645
a61af66fc99e Initial load
duke
parents:
diff changeset
3646 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3647 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3648 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3649
a61af66fc99e Initial load
duke
parents:
diff changeset
3650 // Long Immediate: low 32-bit mask
a61af66fc99e Initial load
duke
parents:
diff changeset
3651 operand immL_32bits() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3652 predicate(n->get_long() == 0xFFFFFFFFL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3653 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3654 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3655
a61af66fc99e Initial load
duke
parents:
diff changeset
3656 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3657 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3658 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3659
a61af66fc99e Initial load
duke
parents:
diff changeset
3660 // Double Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3661 operand immD() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3662 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3663
a61af66fc99e Initial load
duke
parents:
diff changeset
3664 op_cost(40);
a61af66fc99e Initial load
duke
parents:
diff changeset
3665 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3666 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3668
a61af66fc99e Initial load
duke
parents:
diff changeset
3669 operand immD0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3670 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
3671 // on 64-bit architectures this comparision is faster
a61af66fc99e Initial load
duke
parents:
diff changeset
3672 predicate(jlong_cast(n->getd()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3673 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
3674 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
a61af66fc99e Initial load
duke
parents:
diff changeset
3675 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
3676 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3677
a61af66fc99e Initial load
duke
parents:
diff changeset
3678 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3679 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3680 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3681 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3682
a61af66fc99e Initial load
duke
parents:
diff changeset
3683 // Float Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3684 operand immF() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3685 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3686
a61af66fc99e Initial load
duke
parents:
diff changeset
3687 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
3688 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3689 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3690 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3691
a61af66fc99e Initial load
duke
parents:
diff changeset
3692 // Float Immediate: 0
a61af66fc99e Initial load
duke
parents:
diff changeset
3693 operand immF0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3694 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
a61af66fc99e Initial load
duke
parents:
diff changeset
3695 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3696
a61af66fc99e Initial load
duke
parents:
diff changeset
3697 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3698 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3699 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3700 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3701
a61af66fc99e Initial load
duke
parents:
diff changeset
3702 // Integer Register Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3703 // Integer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3704 operand iRegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3705 constraint(ALLOC_IN_RC(int_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3706 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3707
a61af66fc99e Initial load
duke
parents:
diff changeset
3708 match(notemp_iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3709 match(g1RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3710 match(o0RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3711 match(iRegIsafe);
a61af66fc99e Initial load
duke
parents:
diff changeset
3712
a61af66fc99e Initial load
duke
parents:
diff changeset
3713 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3714 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3715 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3716
a61af66fc99e Initial load
duke
parents:
diff changeset
3717 operand notemp_iRegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3718 constraint(ALLOC_IN_RC(notemp_int_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3719 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3720
a61af66fc99e Initial load
duke
parents:
diff changeset
3721 match(o0RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3722
a61af66fc99e Initial load
duke
parents:
diff changeset
3723 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3724 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3725 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3726
a61af66fc99e Initial load
duke
parents:
diff changeset
3727 operand o0RegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3728 constraint(ALLOC_IN_RC(o0_regI));
a61af66fc99e Initial load
duke
parents:
diff changeset
3729 match(iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3730
a61af66fc99e Initial load
duke
parents:
diff changeset
3731 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3732 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3733 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3734
a61af66fc99e Initial load
duke
parents:
diff changeset
3735 // Pointer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3736 operand iRegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3737 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3738 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3739
a61af66fc99e Initial load
duke
parents:
diff changeset
3740 match(lock_ptr_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3741 match(g1RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3742 match(g2RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3743 match(g3RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3744 match(g4RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3745 match(i0RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3746 match(o0RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3747 match(o1RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3748 match(l7RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3749
a61af66fc99e Initial load
duke
parents:
diff changeset
3750 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3751 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3752 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3753
a61af66fc99e Initial load
duke
parents:
diff changeset
3754 operand sp_ptr_RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3755 constraint(ALLOC_IN_RC(sp_ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3756 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3757 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3758
a61af66fc99e Initial load
duke
parents:
diff changeset
3759 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3760 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3761 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3762
a61af66fc99e Initial load
duke
parents:
diff changeset
3763 operand lock_ptr_RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3764 constraint(ALLOC_IN_RC(lock_ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3765 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3766 match(i0RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3767 match(o0RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3768 match(o1RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3769 match(l7RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3770
a61af66fc99e Initial load
duke
parents:
diff changeset
3771 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3772 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3773 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3774
a61af66fc99e Initial load
duke
parents:
diff changeset
3775 operand g1RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3776 constraint(ALLOC_IN_RC(g1_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3777 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3778
a61af66fc99e Initial load
duke
parents:
diff changeset
3779 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3780 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3781 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3782
a61af66fc99e Initial load
duke
parents:
diff changeset
3783 operand g2RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3784 constraint(ALLOC_IN_RC(g2_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3785 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3786
a61af66fc99e Initial load
duke
parents:
diff changeset
3787 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3788 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3789 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3790
a61af66fc99e Initial load
duke
parents:
diff changeset
3791 operand g3RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3792 constraint(ALLOC_IN_RC(g3_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3793 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3794
a61af66fc99e Initial load
duke
parents:
diff changeset
3795 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3796 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3797 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3798
a61af66fc99e Initial load
duke
parents:
diff changeset
3799 operand g1RegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3800 constraint(ALLOC_IN_RC(g1_regI));
a61af66fc99e Initial load
duke
parents:
diff changeset
3801 match(iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3802
a61af66fc99e Initial load
duke
parents:
diff changeset
3803 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3804 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3805 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3806
a61af66fc99e Initial load
duke
parents:
diff changeset
3807 operand g3RegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3808 constraint(ALLOC_IN_RC(g3_regI));
a61af66fc99e Initial load
duke
parents:
diff changeset
3809 match(iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3810
a61af66fc99e Initial load
duke
parents:
diff changeset
3811 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3812 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3813 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3814
a61af66fc99e Initial load
duke
parents:
diff changeset
3815 operand g4RegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3816 constraint(ALLOC_IN_RC(g4_regI));
a61af66fc99e Initial load
duke
parents:
diff changeset
3817 match(iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3818
a61af66fc99e Initial load
duke
parents:
diff changeset
3819 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3820 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3821 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3822
a61af66fc99e Initial load
duke
parents:
diff changeset
3823 operand g4RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3824 constraint(ALLOC_IN_RC(g4_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3825 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3826
a61af66fc99e Initial load
duke
parents:
diff changeset
3827 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3828 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3829 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3830
a61af66fc99e Initial load
duke
parents:
diff changeset
3831 operand i0RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3832 constraint(ALLOC_IN_RC(i0_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3833 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3834
a61af66fc99e Initial load
duke
parents:
diff changeset
3835 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3836 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3837 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3838
a61af66fc99e Initial load
duke
parents:
diff changeset
3839 operand o0RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3840 constraint(ALLOC_IN_RC(o0_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3841 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3842
a61af66fc99e Initial load
duke
parents:
diff changeset
3843 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3844 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3845 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3846
a61af66fc99e Initial load
duke
parents:
diff changeset
3847 operand o1RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3848 constraint(ALLOC_IN_RC(o1_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3849 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3850
a61af66fc99e Initial load
duke
parents:
diff changeset
3851 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3852 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3853 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3854
a61af66fc99e Initial load
duke
parents:
diff changeset
3855 operand o2RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3856 constraint(ALLOC_IN_RC(o2_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3857 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3858
a61af66fc99e Initial load
duke
parents:
diff changeset
3859 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3860 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3861 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3862
a61af66fc99e Initial load
duke
parents:
diff changeset
3863 operand o7RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3864 constraint(ALLOC_IN_RC(o7_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3865 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3866
a61af66fc99e Initial load
duke
parents:
diff changeset
3867 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3868 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3869 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3870
a61af66fc99e Initial load
duke
parents:
diff changeset
3871 operand l7RegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3872 constraint(ALLOC_IN_RC(l7_regP));
a61af66fc99e Initial load
duke
parents:
diff changeset
3873 match(iRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3874
a61af66fc99e Initial load
duke
parents:
diff changeset
3875 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3876 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3877 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3878
a61af66fc99e Initial load
duke
parents:
diff changeset
3879 operand o7RegI() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3880 constraint(ALLOC_IN_RC(o7_regI));
a61af66fc99e Initial load
duke
parents:
diff changeset
3881 match(iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3882
a61af66fc99e Initial load
duke
parents:
diff changeset
3883 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3884 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3885 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3886
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3887 operand iRegN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3888 constraint(ALLOC_IN_RC(int_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3889 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3890
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3891 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3892 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3893 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
3894
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3895 // Long Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3896 operand iRegL() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3897 constraint(ALLOC_IN_RC(long_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3898 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3899
a61af66fc99e Initial load
duke
parents:
diff changeset
3900 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3901 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3902 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3903
a61af66fc99e Initial load
duke
parents:
diff changeset
3904 operand o2RegL() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3905 constraint(ALLOC_IN_RC(o2_regL));
a61af66fc99e Initial load
duke
parents:
diff changeset
3906 match(iRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3907
a61af66fc99e Initial load
duke
parents:
diff changeset
3908 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3909 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3910 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3911
a61af66fc99e Initial load
duke
parents:
diff changeset
3912 operand o7RegL() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3913 constraint(ALLOC_IN_RC(o7_regL));
a61af66fc99e Initial load
duke
parents:
diff changeset
3914 match(iRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3915
a61af66fc99e Initial load
duke
parents:
diff changeset
3916 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3917 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3918 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3919
a61af66fc99e Initial load
duke
parents:
diff changeset
3920 operand g1RegL() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3921 constraint(ALLOC_IN_RC(g1_regL));
a61af66fc99e Initial load
duke
parents:
diff changeset
3922 match(iRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3923
a61af66fc99e Initial load
duke
parents:
diff changeset
3924 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3925 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3926 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3927
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3928 operand g3RegL() %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3929 constraint(ALLOC_IN_RC(g3_regL));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3930 match(iRegL);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3931
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3932 format %{ %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3933 interface(REG_INTER);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3934 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3935
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3936 // Int Register safe
a61af66fc99e Initial load
duke
parents:
diff changeset
3937 // This is 64bit safe
a61af66fc99e Initial load
duke
parents:
diff changeset
3938 operand iRegIsafe() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3939 constraint(ALLOC_IN_RC(long_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3940
a61af66fc99e Initial load
duke
parents:
diff changeset
3941 match(iRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3942
a61af66fc99e Initial load
duke
parents:
diff changeset
3943 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3944 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3945 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3946
a61af66fc99e Initial load
duke
parents:
diff changeset
3947 // Condition Code Flag Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3948 operand flagsReg() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3949 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3950 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3951
a61af66fc99e Initial load
duke
parents:
diff changeset
3952 format %{ "ccr" %} // both ICC and XCC
a61af66fc99e Initial load
duke
parents:
diff changeset
3953 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3954 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3955
a61af66fc99e Initial load
duke
parents:
diff changeset
3956 // Condition Code Register, unsigned comparisons.
a61af66fc99e Initial load
duke
parents:
diff changeset
3957 operand flagsRegU() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3958 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3959 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3960
a61af66fc99e Initial load
duke
parents:
diff changeset
3961 format %{ "icc_U" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3962 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3963 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3964
a61af66fc99e Initial load
duke
parents:
diff changeset
3965 // Condition Code Register, pointer comparisons.
a61af66fc99e Initial load
duke
parents:
diff changeset
3966 operand flagsRegP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3967 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3968 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3969
a61af66fc99e Initial load
duke
parents:
diff changeset
3970 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
3971 format %{ "xcc_P" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3972 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
3973 format %{ "icc_P" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3974 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
3975 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3976 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3977
a61af66fc99e Initial load
duke
parents:
diff changeset
3978 // Condition Code Register, long comparisons.
a61af66fc99e Initial load
duke
parents:
diff changeset
3979 operand flagsRegL() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3980 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3981 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3982
a61af66fc99e Initial load
duke
parents:
diff changeset
3983 format %{ "xcc_L" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3984 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3985 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3986
a61af66fc99e Initial load
duke
parents:
diff changeset
3987 // Condition Code Register, floating comparisons, unordered same as "less".
a61af66fc99e Initial load
duke
parents:
diff changeset
3988 operand flagsRegF() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3989 constraint(ALLOC_IN_RC(float_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3990 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3991 match(flagsRegF0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3992
a61af66fc99e Initial load
duke
parents:
diff changeset
3993 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3994 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3995 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3996
a61af66fc99e Initial load
duke
parents:
diff changeset
3997 operand flagsRegF0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3998 constraint(ALLOC_IN_RC(float_flag0));
a61af66fc99e Initial load
duke
parents:
diff changeset
3999 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
4000
a61af66fc99e Initial load
duke
parents:
diff changeset
4001 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4002 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4003 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4004
a61af66fc99e Initial load
duke
parents:
diff changeset
4005
a61af66fc99e Initial load
duke
parents:
diff changeset
4006 // Condition Code Flag Register used by long compare
a61af66fc99e Initial load
duke
parents:
diff changeset
4007 operand flagsReg_long_LTGE() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4008 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
4009 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
4010 format %{ "icc_LTGE" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4011 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4012 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4013 operand flagsReg_long_EQNE() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4014 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
4015 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
4016 format %{ "icc_EQNE" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4017 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4018 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4019 operand flagsReg_long_LEGT() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4020 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
4021 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
4022 format %{ "icc_LEGT" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4023 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4024 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4025
a61af66fc99e Initial load
duke
parents:
diff changeset
4026
a61af66fc99e Initial load
duke
parents:
diff changeset
4027 operand regD() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4028 constraint(ALLOC_IN_RC(dflt_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4029 match(RegD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4030
551
6c4cda924d2e 6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents: 420
diff changeset
4031 match(regD_low);
6c4cda924d2e 6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents: 420
diff changeset
4032
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4033 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4034 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4035 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4036
a61af66fc99e Initial load
duke
parents:
diff changeset
4037 operand regF() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4038 constraint(ALLOC_IN_RC(sflt_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4039 match(RegF);
a61af66fc99e Initial load
duke
parents:
diff changeset
4040
a61af66fc99e Initial load
duke
parents:
diff changeset
4041 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4042 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4043 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4044
a61af66fc99e Initial load
duke
parents:
diff changeset
4045 operand regD_low() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4046 constraint(ALLOC_IN_RC(dflt_low_reg));
551
6c4cda924d2e 6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents: 420
diff changeset
4047 match(regD);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4048
a61af66fc99e Initial load
duke
parents:
diff changeset
4049 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4050 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4051 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4052
a61af66fc99e Initial load
duke
parents:
diff changeset
4053 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
4054
a61af66fc99e Initial load
duke
parents:
diff changeset
4055 // Method Register
a61af66fc99e Initial load
duke
parents:
diff changeset
4056 operand inline_cache_regP(iRegP reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4057 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
a61af66fc99e Initial load
duke
parents:
diff changeset
4058 match(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4059 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4060 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4061 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4062
a61af66fc99e Initial load
duke
parents:
diff changeset
4063 operand interpreter_method_oop_regP(iRegP reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4064 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
a61af66fc99e Initial load
duke
parents:
diff changeset
4065 match(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4066 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4067 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4068 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4069
a61af66fc99e Initial load
duke
parents:
diff changeset
4070
a61af66fc99e Initial load
duke
parents:
diff changeset
4071 //----------Complex Operands---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4072 // Indirect Memory Reference
a61af66fc99e Initial load
duke
parents:
diff changeset
4073 operand indirect(sp_ptr_RegP reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4074 constraint(ALLOC_IN_RC(sp_ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4075 match(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4076
a61af66fc99e Initial load
duke
parents:
diff changeset
4077 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4078 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4079 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4080 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4081 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4082 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4083 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4084 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4085 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4086
a61af66fc99e Initial load
duke
parents:
diff changeset
4087 // Indirect with Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4088 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4089 constraint(ALLOC_IN_RC(sp_ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4090 match(AddP reg offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
4091
a61af66fc99e Initial load
duke
parents:
diff changeset
4092 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4093 format %{ "[$reg + $offset]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4094 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4095 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4096 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4097 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4098 disp($offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
4099 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4100 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4101
a61af66fc99e Initial load
duke
parents:
diff changeset
4102 // Note: Intel has a swapped version also, like this:
a61af66fc99e Initial load
duke
parents:
diff changeset
4103 //operand indOffsetX(iRegI reg, immP offset) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4104 // constraint(ALLOC_IN_RC(int_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4105 // match(AddP offset reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4106 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4107 // op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4108 // format %{ "[$reg + $offset]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4109 // interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4110 // base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4111 // index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4112 // scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4113 // disp($offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
4114 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4115 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
4116 //// However, it doesn't make sense for SPARC, since
a61af66fc99e Initial load
duke
parents:
diff changeset
4117 // we have no particularly good way to embed oops in
a61af66fc99e Initial load
duke
parents:
diff changeset
4118 // single instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
4119
a61af66fc99e Initial load
duke
parents:
diff changeset
4120 // Indirect with Register Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4121 operand indIndex(iRegP addr, iRegX index) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4122 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4123 match(AddP addr index);
a61af66fc99e Initial load
duke
parents:
diff changeset
4124
a61af66fc99e Initial load
duke
parents:
diff changeset
4125 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4126 format %{ "[$addr + $index]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4127 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4128 base($addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
4129 index($index);
a61af66fc99e Initial load
duke
parents:
diff changeset
4130 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4131 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4132 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4133 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4134
a61af66fc99e Initial load
duke
parents:
diff changeset
4135 //----------Special Memory Operands--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4136 // Stack Slot Operand - This operand is used for loading and storing temporary
a61af66fc99e Initial load
duke
parents:
diff changeset
4137 // values on the stack where a match requires a value to
a61af66fc99e Initial load
duke
parents:
diff changeset
4138 // flow through memory.
a61af66fc99e Initial load
duke
parents:
diff changeset
4139 operand stackSlotI(sRegI reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4140 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4141 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4142 //match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4143 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4144 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4145 base(0xE); // R_SP
a61af66fc99e Initial load
duke
parents:
diff changeset
4146 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4147 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4148 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4149 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4150 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4151
a61af66fc99e Initial load
duke
parents:
diff changeset
4152 operand stackSlotP(sRegP reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4153 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4154 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4155 //match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4156 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4157 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4158 base(0xE); // R_SP
a61af66fc99e Initial load
duke
parents:
diff changeset
4159 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4160 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4161 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4162 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4163 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4164
a61af66fc99e Initial load
duke
parents:
diff changeset
4165 operand stackSlotF(sRegF reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4166 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4167 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4168 //match(RegF);
a61af66fc99e Initial load
duke
parents:
diff changeset
4169 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4170 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4171 base(0xE); // R_SP
a61af66fc99e Initial load
duke
parents:
diff changeset
4172 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4173 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4174 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4175 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4176 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4177 operand stackSlotD(sRegD reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4178 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4179 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4180 //match(RegD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4181 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4182 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4183 base(0xE); // R_SP
a61af66fc99e Initial load
duke
parents:
diff changeset
4184 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4185 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4186 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4187 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4188 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4189 operand stackSlotL(sRegL reg) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4190 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4191 op_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4192 //match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4193 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4194 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4195 base(0xE); // R_SP
a61af66fc99e Initial load
duke
parents:
diff changeset
4196 index(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4197 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4198 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4199 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4200 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4201
a61af66fc99e Initial load
duke
parents:
diff changeset
4202 // Operands for expressing Control Flow
a61af66fc99e Initial load
duke
parents:
diff changeset
4203 // NOTE: Label is a predefined operand which should not be redefined in
a61af66fc99e Initial load
duke
parents:
diff changeset
4204 // the AD file. It is generically handled within the ADLC.
a61af66fc99e Initial load
duke
parents:
diff changeset
4205
a61af66fc99e Initial load
duke
parents:
diff changeset
4206 //----------Conditional Branch Operands----------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4207 // Comparison Op - This is the operation of the comparison, and is limited to
a61af66fc99e Initial load
duke
parents:
diff changeset
4208 // the following set of codes:
a61af66fc99e Initial load
duke
parents:
diff changeset
4209 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
a61af66fc99e Initial load
duke
parents:
diff changeset
4210 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4211 // Other attributes of the comparison, such as unsignedness, are specified
a61af66fc99e Initial load
duke
parents:
diff changeset
4212 // by the comparison instruction that sets a condition code flags register.
a61af66fc99e Initial load
duke
parents:
diff changeset
4213 // That result is represented by a flags operand whose subtype is appropriate
a61af66fc99e Initial load
duke
parents:
diff changeset
4214 // to the unsignedness (etc.) of the comparison.
a61af66fc99e Initial load
duke
parents:
diff changeset
4215 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4216 // Later, the instruction which matches both the Comparison Op (a Bool) and
a61af66fc99e Initial load
duke
parents:
diff changeset
4217 // the flags (produced by the Cmp) specifies the coding of the comparison op
a61af66fc99e Initial load
duke
parents:
diff changeset
4218 // by matching a specific subtype of Bool operand below, such as cmpOpU.
a61af66fc99e Initial load
duke
parents:
diff changeset
4219
a61af66fc99e Initial load
duke
parents:
diff changeset
4220 operand cmpOp() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4221 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4222
a61af66fc99e Initial load
duke
parents:
diff changeset
4223 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4224 interface(COND_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4225 equal(0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4226 not_equal(0x9);
a61af66fc99e Initial load
duke
parents:
diff changeset
4227 less(0x3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4228 greater_equal(0xB);
a61af66fc99e Initial load
duke
parents:
diff changeset
4229 less_equal(0x2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4230 greater(0xA);
a61af66fc99e Initial load
duke
parents:
diff changeset
4231 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4232 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4233
a61af66fc99e Initial load
duke
parents:
diff changeset
4234 // Comparison Op, unsigned
a61af66fc99e Initial load
duke
parents:
diff changeset
4235 operand cmpOpU() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4236 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4237
a61af66fc99e Initial load
duke
parents:
diff changeset
4238 format %{ "u" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4239 interface(COND_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4240 equal(0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4241 not_equal(0x9);
a61af66fc99e Initial load
duke
parents:
diff changeset
4242 less(0x5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4243 greater_equal(0xD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4244 less_equal(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4245 greater(0xC);
a61af66fc99e Initial load
duke
parents:
diff changeset
4246 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4247 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4248
a61af66fc99e Initial load
duke
parents:
diff changeset
4249 // Comparison Op, pointer (same as unsigned)
a61af66fc99e Initial load
duke
parents:
diff changeset
4250 operand cmpOpP() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4251 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4252
a61af66fc99e Initial load
duke
parents:
diff changeset
4253 format %{ "p" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4254 interface(COND_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4255 equal(0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4256 not_equal(0x9);
a61af66fc99e Initial load
duke
parents:
diff changeset
4257 less(0x5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4258 greater_equal(0xD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4259 less_equal(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4260 greater(0xC);
a61af66fc99e Initial load
duke
parents:
diff changeset
4261 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4262 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4263
a61af66fc99e Initial load
duke
parents:
diff changeset
4264 // Comparison Op, branch-register encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
4265 operand cmpOp_reg() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4266 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4267
a61af66fc99e Initial load
duke
parents:
diff changeset
4268 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4269 interface(COND_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4270 equal (0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4271 not_equal (0x5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4272 less (0x3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4273 greater_equal(0x7);
a61af66fc99e Initial load
duke
parents:
diff changeset
4274 less_equal (0x2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4275 greater (0x6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4276 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4277 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4278
a61af66fc99e Initial load
duke
parents:
diff changeset
4279 // Comparison Code, floating, unordered same as less
a61af66fc99e Initial load
duke
parents:
diff changeset
4280 operand cmpOpF() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4281 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4282
a61af66fc99e Initial load
duke
parents:
diff changeset
4283 format %{ "fl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4284 interface(COND_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4285 equal(0x9);
a61af66fc99e Initial load
duke
parents:
diff changeset
4286 not_equal(0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4287 less(0x3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4288 greater_equal(0xB);
a61af66fc99e Initial load
duke
parents:
diff changeset
4289 less_equal(0xE);
a61af66fc99e Initial load
duke
parents:
diff changeset
4290 greater(0x6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4291 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4292 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4293
a61af66fc99e Initial load
duke
parents:
diff changeset
4294 // Used by long compare
a61af66fc99e Initial load
duke
parents:
diff changeset
4295 operand cmpOp_commute() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4296 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4297
a61af66fc99e Initial load
duke
parents:
diff changeset
4298 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4299 interface(COND_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4300 equal(0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4301 not_equal(0x9);
a61af66fc99e Initial load
duke
parents:
diff changeset
4302 less(0xA);
a61af66fc99e Initial load
duke
parents:
diff changeset
4303 greater_equal(0x2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4304 less_equal(0xB);
a61af66fc99e Initial load
duke
parents:
diff changeset
4305 greater(0x3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4306 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4307 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4308
a61af66fc99e Initial load
duke
parents:
diff changeset
4309 //----------OPERAND CLASSES----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4310 // Operand Classes are groups of operands that are used to simplify
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
4311 // instruction definitions by not requiring the AD writer to specify separate
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4312 // instructions for every form of operand when the instruction accepts
a61af66fc99e Initial load
duke
parents:
diff changeset
4313 // multiple operand types with the same basic encoding and format. The classic
a61af66fc99e Initial load
duke
parents:
diff changeset
4314 // case of this is memory operands.
a61af66fc99e Initial load
duke
parents:
diff changeset
4315 // Indirect is not included since its use is limited to Compare & Swap
a61af66fc99e Initial load
duke
parents:
diff changeset
4316 opclass memory( indirect, indOffset13, indIndex );
a61af66fc99e Initial load
duke
parents:
diff changeset
4317
a61af66fc99e Initial load
duke
parents:
diff changeset
4318 //----------PIPELINE-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4319 pipeline %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4320
a61af66fc99e Initial load
duke
parents:
diff changeset
4321 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4322 attributes %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4323 fixed_size_instructions; // Fixed size instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4324 branch_has_delay_slot; // Branch has delay slot following
a61af66fc99e Initial load
duke
parents:
diff changeset
4325 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
a61af66fc99e Initial load
duke
parents:
diff changeset
4326 instruction_unit_size = 4; // An instruction is 4 bytes long
a61af66fc99e Initial load
duke
parents:
diff changeset
4327 instruction_fetch_unit_size = 16; // The processor fetches one line
a61af66fc99e Initial load
duke
parents:
diff changeset
4328 instruction_fetch_units = 1; // of 16 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
4329
a61af66fc99e Initial load
duke
parents:
diff changeset
4330 // List of nop instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4331 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
a61af66fc99e Initial load
duke
parents:
diff changeset
4332 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4333
a61af66fc99e Initial load
duke
parents:
diff changeset
4334 //----------RESOURCES----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4335 // Resources are the functional units available to the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
4336 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4337
a61af66fc99e Initial load
duke
parents:
diff changeset
4338 //----------PIPELINE DESCRIPTION-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4339 // Pipeline Description specifies the stages in the machine's pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4340
a61af66fc99e Initial load
duke
parents:
diff changeset
4341 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
a61af66fc99e Initial load
duke
parents:
diff changeset
4342
a61af66fc99e Initial load
duke
parents:
diff changeset
4343 //----------PIPELINE CLASSES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4344 // Pipeline Classes describe the stages in which input and output are
a61af66fc99e Initial load
duke
parents:
diff changeset
4345 // referenced by the hardware pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
4346
a61af66fc99e Initial load
duke
parents:
diff changeset
4347 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4348 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4349 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4350 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4351 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4352 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4353 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4354 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4355
a61af66fc99e Initial load
duke
parents:
diff changeset
4356 // Integer ALU reg-reg long operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4357 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4358 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4359 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4360 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4361 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4362 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4363 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4364 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4365
a61af66fc99e Initial load
duke
parents:
diff changeset
4366 // Integer ALU reg-reg long dependent operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4367 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4368 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4369 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4370 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4371 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4372 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4373 IALU : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4374 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4375
a61af66fc99e Initial load
duke
parents:
diff changeset
4376 // Integer ALU reg-imm operaion
a61af66fc99e Initial load
duke
parents:
diff changeset
4377 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4378 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4379 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4380 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4381 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4382 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4383
a61af66fc99e Initial load
duke
parents:
diff changeset
4384 // Integer ALU reg-reg operation with condition code
a61af66fc99e Initial load
duke
parents:
diff changeset
4385 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4386 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4387 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4388 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4389 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4390 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4391 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4392 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4393
a61af66fc99e Initial load
duke
parents:
diff changeset
4394 // Integer ALU reg-imm operation with condition code
a61af66fc99e Initial load
duke
parents:
diff changeset
4395 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4396 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4397 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4398 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4399 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4400 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4401 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4402
a61af66fc99e Initial load
duke
parents:
diff changeset
4403 // Integer ALU zero-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4404 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4405 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4406 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4407 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4408 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4409 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4410
a61af66fc99e Initial load
duke
parents:
diff changeset
4411 // Integer ALU zero-reg operation with condition code only
a61af66fc99e Initial load
duke
parents:
diff changeset
4412 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4413 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4414 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4415 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4416 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4417 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4418
a61af66fc99e Initial load
duke
parents:
diff changeset
4419 // Integer ALU reg-reg operation with condition code only
a61af66fc99e Initial load
duke
parents:
diff changeset
4420 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4421 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4422 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4423 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4424 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4425 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4426 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4427
a61af66fc99e Initial load
duke
parents:
diff changeset
4428 // Integer ALU reg-imm operation with condition code only
a61af66fc99e Initial load
duke
parents:
diff changeset
4429 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4430 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4431 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4432 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4433 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4434 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4435
a61af66fc99e Initial load
duke
parents:
diff changeset
4436 // Integer ALU reg-reg-zero operation with condition code only
a61af66fc99e Initial load
duke
parents:
diff changeset
4437 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4438 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4439 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4440 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4441 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4442 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4443 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4444
a61af66fc99e Initial load
duke
parents:
diff changeset
4445 // Integer ALU reg-imm-zero operation with condition code only
a61af66fc99e Initial load
duke
parents:
diff changeset
4446 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4447 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4448 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4449 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4450 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4451 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4452
a61af66fc99e Initial load
duke
parents:
diff changeset
4453 // Integer ALU reg-reg operation with condition code, src1 modified
a61af66fc99e Initial load
duke
parents:
diff changeset
4454 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4455 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4456 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4457 src1 : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4458 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4459 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4460 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4461 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4462
a61af66fc99e Initial load
duke
parents:
diff changeset
4463 // Integer ALU reg-imm operation with condition code, src1 modified
a61af66fc99e Initial load
duke
parents:
diff changeset
4464 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4465 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4466 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4467 src1 : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4468 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4469 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4470 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4471
a61af66fc99e Initial load
duke
parents:
diff changeset
4472 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4473 multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4474 dst : E(write)+4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4475 cr : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4476 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4477 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4478 IALU : R(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4479 BR : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4480 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4481
a61af66fc99e Initial load
duke
parents:
diff changeset
4482 // Integer ALU operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4483 pipe_class ialu_none(iRegI dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4484 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4485 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4486 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4487 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4488
a61af66fc99e Initial load
duke
parents:
diff changeset
4489 // Integer ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4490 pipe_class ialu_reg(iRegI dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4491 single_instruction; may_have_no_code;
a61af66fc99e Initial load
duke
parents:
diff changeset
4492 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4493 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4494 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4495 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4496
a61af66fc99e Initial load
duke
parents:
diff changeset
4497 // Integer ALU reg conditional operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4498 // This instruction has a 1 cycle stall, and cannot execute
a61af66fc99e Initial load
duke
parents:
diff changeset
4499 // in the same cycle as the instruction setting the condition
a61af66fc99e Initial load
duke
parents:
diff changeset
4500 // code. We kludge this by pretending to read the condition code
a61af66fc99e Initial load
duke
parents:
diff changeset
4501 // 1 cycle earlier, and by marking the functional units as busy
a61af66fc99e Initial load
duke
parents:
diff changeset
4502 // for 2 cycles with the result available 1 cycle later than
a61af66fc99e Initial load
duke
parents:
diff changeset
4503 // is really the case.
a61af66fc99e Initial load
duke
parents:
diff changeset
4504 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4505 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4506 op2_out : C(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4507 op1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4508 cr : R(read); // This is really E, with a 1 cycle stall
a61af66fc99e Initial load
duke
parents:
diff changeset
4509 BR : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4510 MS : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4511 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4512
a61af66fc99e Initial load
duke
parents:
diff changeset
4513 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
4514 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4515 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4516 dst : C(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4517 src : R(read)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4518 IALU : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4519 BR : E(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4520 MS : E(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4521 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4522 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
4523
a61af66fc99e Initial load
duke
parents:
diff changeset
4524 // Integer ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4525 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4526 single_instruction; may_have_no_code;
a61af66fc99e Initial load
duke
parents:
diff changeset
4527 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4528 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4529 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4530 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4531 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4532 single_instruction; may_have_no_code;
a61af66fc99e Initial load
duke
parents:
diff changeset
4533 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4534 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4535 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4536 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4537
a61af66fc99e Initial load
duke
parents:
diff changeset
4538 // Two integer ALU reg operations
a61af66fc99e Initial load
duke
parents:
diff changeset
4539 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4540 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4541 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4542 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4543 A0 : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4544 A1 : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4545 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4546
a61af66fc99e Initial load
duke
parents:
diff changeset
4547 // Two integer ALU reg operations
a61af66fc99e Initial load
duke
parents:
diff changeset
4548 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4549 instruction_count(2); may_have_no_code;
a61af66fc99e Initial load
duke
parents:
diff changeset
4550 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4551 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4552 A0 : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4553 A1 : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4554 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4555
a61af66fc99e Initial load
duke
parents:
diff changeset
4556 // Integer ALU imm operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4557 pipe_class ialu_imm(iRegI dst, immI13 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4558 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4559 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4560 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4561 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4562
a61af66fc99e Initial load
duke
parents:
diff changeset
4563 // Integer ALU reg-reg with carry operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4564 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4565 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4566 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4567 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4568 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4569 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4570 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4571
a61af66fc99e Initial load
duke
parents:
diff changeset
4572 // Integer ALU cc operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4573 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4574 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4575 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4576 cc : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4577 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4578 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4579
a61af66fc99e Initial load
duke
parents:
diff changeset
4580 // Integer ALU cc / second IALU operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4581 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4582 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4583 dst : E(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4584 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4585 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4586 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4587
a61af66fc99e Initial load
duke
parents:
diff changeset
4588 // Integer ALU cc / second IALU operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4589 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4590 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4591 dst : E(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4592 p : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4593 q : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4594 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4595 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4596
a61af66fc99e Initial load
duke
parents:
diff changeset
4597 // Integer ALU hi-lo-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4598 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4599 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4600 dst : E(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4601 IALU : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4602 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4603
a61af66fc99e Initial load
duke
parents:
diff changeset
4604 // Float ALU hi-lo-reg operation (with temp)
a61af66fc99e Initial load
duke
parents:
diff changeset
4605 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4606 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4607 dst : E(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4608 IALU : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4609 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4610
a61af66fc99e Initial load
duke
parents:
diff changeset
4611 // Long Constant
a61af66fc99e Initial load
duke
parents:
diff changeset
4612 pipe_class loadConL( iRegL dst, immL src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4613 instruction_count(2); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4614 dst : E(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4615 IALU : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4616 IALU : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4617 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4618
a61af66fc99e Initial load
duke
parents:
diff changeset
4619 // Pointer Constant
a61af66fc99e Initial load
duke
parents:
diff changeset
4620 pipe_class loadConP( iRegP dst, immP src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4621 instruction_count(0); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4622 fixed_latency(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4623 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4624
a61af66fc99e Initial load
duke
parents:
diff changeset
4625 // Polling Address
a61af66fc99e Initial load
duke
parents:
diff changeset
4626 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4627 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
4628 instruction_count(0); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4629 fixed_latency(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4630 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
4631 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4632 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4633 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
4634 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4635
a61af66fc99e Initial load
duke
parents:
diff changeset
4636 // Long Constant small
a61af66fc99e Initial load
duke
parents:
diff changeset
4637 pipe_class loadConLlo( iRegL dst, immL src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4638 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4639 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4640 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4641 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4642 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4643
a61af66fc99e Initial load
duke
parents:
diff changeset
4644 // [PHH] This is wrong for 64-bit. See LdImmF/D.
a61af66fc99e Initial load
duke
parents:
diff changeset
4645 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4646 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4647 src : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4648 dst : M(write)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4649 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4650 MS : E;
a61af66fc99e Initial load
duke
parents:
diff changeset
4651 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4652
a61af66fc99e Initial load
duke
parents:
diff changeset
4653 // Integer ALU nop operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4654 pipe_class ialu_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4655 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4656 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4657 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4658
a61af66fc99e Initial load
duke
parents:
diff changeset
4659 // Integer ALU nop operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4660 pipe_class ialu_nop_A0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4661 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4662 A0 : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4663 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4664
a61af66fc99e Initial load
duke
parents:
diff changeset
4665 // Integer ALU nop operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4666 pipe_class ialu_nop_A1() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4667 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4668 A1 : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4669 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4670
a61af66fc99e Initial load
duke
parents:
diff changeset
4671 // Integer Multiply reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4672 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4673 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4674 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4675 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4676 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4677 MS : R(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4678 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4679
a61af66fc99e Initial load
duke
parents:
diff changeset
4680 // Integer Multiply reg-imm operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4681 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4682 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4683 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4684 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4685 MS : R(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4686 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4687
a61af66fc99e Initial load
duke
parents:
diff changeset
4688 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4689 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4690 dst : E(write)+4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4691 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4692 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4693 MS : R(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4694 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4695
a61af66fc99e Initial load
duke
parents:
diff changeset
4696 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4697 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4698 dst : E(write)+4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4699 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4700 MS : R(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4701 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4702
a61af66fc99e Initial load
duke
parents:
diff changeset
4703 // Integer Divide reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4704 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4705 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4706 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4707 temp : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4708 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4709 src2 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4710 temp : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4711 MS : R(38);
a61af66fc99e Initial load
duke
parents:
diff changeset
4712 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4713
a61af66fc99e Initial load
duke
parents:
diff changeset
4714 // Integer Divide reg-imm
a61af66fc99e Initial load
duke
parents:
diff changeset
4715 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4716 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4717 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4718 temp : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4719 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4720 temp : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4721 MS : R(38);
a61af66fc99e Initial load
duke
parents:
diff changeset
4722 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4723
a61af66fc99e Initial load
duke
parents:
diff changeset
4724 // Long Divide
a61af66fc99e Initial load
duke
parents:
diff changeset
4725 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4726 dst : E(write)+71;
a61af66fc99e Initial load
duke
parents:
diff changeset
4727 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4728 src2 : R(read)+1;
a61af66fc99e Initial load
duke
parents:
diff changeset
4729 MS : R(70);
a61af66fc99e Initial load
duke
parents:
diff changeset
4730 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4731
a61af66fc99e Initial load
duke
parents:
diff changeset
4732 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4733 dst : E(write)+71;
a61af66fc99e Initial load
duke
parents:
diff changeset
4734 src1 : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4735 MS : R(70);
a61af66fc99e Initial load
duke
parents:
diff changeset
4736 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4737
a61af66fc99e Initial load
duke
parents:
diff changeset
4738 // Floating Point Add Float
a61af66fc99e Initial load
duke
parents:
diff changeset
4739 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4740 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4741 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4742 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4743 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4744 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4745 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4746
a61af66fc99e Initial load
duke
parents:
diff changeset
4747 // Floating Point Add Double
a61af66fc99e Initial load
duke
parents:
diff changeset
4748 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4749 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4750 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4751 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4752 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4753 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4754 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4755
a61af66fc99e Initial load
duke
parents:
diff changeset
4756 // Floating Point Conditional Move based on integer flags
a61af66fc99e Initial load
duke
parents:
diff changeset
4757 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4758 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4759 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4760 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4761 cr : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4762 FA : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4763 BR : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4764 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4765
a61af66fc99e Initial load
duke
parents:
diff changeset
4766 // Floating Point Conditional Move based on integer flags
a61af66fc99e Initial load
duke
parents:
diff changeset
4767 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4768 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4769 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4770 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4771 cr : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4772 FA : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4773 BR : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4774 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4775
a61af66fc99e Initial load
duke
parents:
diff changeset
4776 // Floating Point Multiply Float
a61af66fc99e Initial load
duke
parents:
diff changeset
4777 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4778 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4779 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4780 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4781 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4782 FM : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4783 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4784
a61af66fc99e Initial load
duke
parents:
diff changeset
4785 // Floating Point Multiply Double
a61af66fc99e Initial load
duke
parents:
diff changeset
4786 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4787 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4788 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4789 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4790 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4791 FM : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4792 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4793
a61af66fc99e Initial load
duke
parents:
diff changeset
4794 // Floating Point Divide Float
a61af66fc99e Initial load
duke
parents:
diff changeset
4795 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4796 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4797 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4798 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4799 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4800 FM : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4801 FDIV : C(14);
a61af66fc99e Initial load
duke
parents:
diff changeset
4802 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4803
a61af66fc99e Initial load
duke
parents:
diff changeset
4804 // Floating Point Divide Double
a61af66fc99e Initial load
duke
parents:
diff changeset
4805 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4806 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4807 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4808 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4809 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4810 FM : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4811 FDIV : C(17);
a61af66fc99e Initial load
duke
parents:
diff changeset
4812 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4813
a61af66fc99e Initial load
duke
parents:
diff changeset
4814 // Floating Point Move/Negate/Abs Float
a61af66fc99e Initial load
duke
parents:
diff changeset
4815 pipe_class faddF_reg(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4816 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4817 dst : W(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4818 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4819 FA : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4820 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4821
a61af66fc99e Initial load
duke
parents:
diff changeset
4822 // Floating Point Move/Negate/Abs Double
a61af66fc99e Initial load
duke
parents:
diff changeset
4823 pipe_class faddD_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4824 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4825 dst : W(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4826 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4827 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4828 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4829
a61af66fc99e Initial load
duke
parents:
diff changeset
4830 // Floating Point Convert F->D
a61af66fc99e Initial load
duke
parents:
diff changeset
4831 pipe_class fcvtF2D(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4832 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4833 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4834 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4835 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4836 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4837
a61af66fc99e Initial load
duke
parents:
diff changeset
4838 // Floating Point Convert I->D
a61af66fc99e Initial load
duke
parents:
diff changeset
4839 pipe_class fcvtI2D(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4840 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4841 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4842 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4843 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4844 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4845
a61af66fc99e Initial load
duke
parents:
diff changeset
4846 // Floating Point Convert LHi->D
a61af66fc99e Initial load
duke
parents:
diff changeset
4847 pipe_class fcvtLHi2D(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4848 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4849 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4850 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4851 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4852 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4853
a61af66fc99e Initial load
duke
parents:
diff changeset
4854 // Floating Point Convert L->D
a61af66fc99e Initial load
duke
parents:
diff changeset
4855 pipe_class fcvtL2D(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4856 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4857 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4858 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4859 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4860 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4861
a61af66fc99e Initial load
duke
parents:
diff changeset
4862 // Floating Point Convert L->F
a61af66fc99e Initial load
duke
parents:
diff changeset
4863 pipe_class fcvtL2F(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4864 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4865 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4866 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4867 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4868 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4869
a61af66fc99e Initial load
duke
parents:
diff changeset
4870 // Floating Point Convert D->F
a61af66fc99e Initial load
duke
parents:
diff changeset
4871 pipe_class fcvtD2F(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4872 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4873 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4874 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4875 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4876 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4877
a61af66fc99e Initial load
duke
parents:
diff changeset
4878 // Floating Point Convert I->L
a61af66fc99e Initial load
duke
parents:
diff changeset
4879 pipe_class fcvtI2L(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4880 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4881 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4882 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4883 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4884 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4885
a61af66fc99e Initial load
duke
parents:
diff changeset
4886 // Floating Point Convert D->F
a61af66fc99e Initial load
duke
parents:
diff changeset
4887 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4888 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4889 dst : X(write)+6;
a61af66fc99e Initial load
duke
parents:
diff changeset
4890 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4891 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4892 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4893
a61af66fc99e Initial load
duke
parents:
diff changeset
4894 // Floating Point Convert D->L
a61af66fc99e Initial load
duke
parents:
diff changeset
4895 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4896 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4897 dst : X(write)+6;
a61af66fc99e Initial load
duke
parents:
diff changeset
4898 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4899 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4900 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4901
a61af66fc99e Initial load
duke
parents:
diff changeset
4902 // Floating Point Convert F->I
a61af66fc99e Initial load
duke
parents:
diff changeset
4903 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4904 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4905 dst : X(write)+6;
a61af66fc99e Initial load
duke
parents:
diff changeset
4906 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4907 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4908 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4909
a61af66fc99e Initial load
duke
parents:
diff changeset
4910 // Floating Point Convert F->L
a61af66fc99e Initial load
duke
parents:
diff changeset
4911 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4912 instruction_count(1); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4913 dst : X(write)+6;
a61af66fc99e Initial load
duke
parents:
diff changeset
4914 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4915 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4916 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4917
a61af66fc99e Initial load
duke
parents:
diff changeset
4918 // Floating Point Convert I->F
a61af66fc99e Initial load
duke
parents:
diff changeset
4919 pipe_class fcvtI2F(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4920 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4921 dst : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4922 src : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4923 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4924 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4925
a61af66fc99e Initial load
duke
parents:
diff changeset
4926 // Floating Point Compare
a61af66fc99e Initial load
duke
parents:
diff changeset
4927 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4928 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4929 cr : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4930 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4931 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4932 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4933 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4934
a61af66fc99e Initial load
duke
parents:
diff changeset
4935 // Floating Point Compare
a61af66fc99e Initial load
duke
parents:
diff changeset
4936 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4937 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4938 cr : X(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4939 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4940 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4941 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4942 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4943
a61af66fc99e Initial load
duke
parents:
diff changeset
4944 // Floating Add Nop
a61af66fc99e Initial load
duke
parents:
diff changeset
4945 pipe_class fadd_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4946 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4947 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4948 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4949
a61af66fc99e Initial load
duke
parents:
diff changeset
4950 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4951 pipe_class istore_mem_reg(memory mem, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4952 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4953 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4954 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4955 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4956 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4957
a61af66fc99e Initial load
duke
parents:
diff changeset
4958 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4959 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4960 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4961 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4962 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4963 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4964 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4965
a61af66fc99e Initial load
duke
parents:
diff changeset
4966 // Integer Store Zero to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4967 pipe_class istore_mem_zero(memory mem, immI0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4968 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4969 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4970 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4971 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4972
a61af66fc99e Initial load
duke
parents:
diff changeset
4973 // Special Stack Slot Store
a61af66fc99e Initial load
duke
parents:
diff changeset
4974 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4975 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4976 stkSlot : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4977 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4978 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4979 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4980
a61af66fc99e Initial load
duke
parents:
diff changeset
4981 // Special Stack Slot Store
a61af66fc99e Initial load
duke
parents:
diff changeset
4982 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4983 instruction_count(2); multiple_bundles;
a61af66fc99e Initial load
duke
parents:
diff changeset
4984 stkSlot : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4985 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4986 MS : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4987 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4988
a61af66fc99e Initial load
duke
parents:
diff changeset
4989 // Float Store
a61af66fc99e Initial load
duke
parents:
diff changeset
4990 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4991 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4992 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4993 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4994 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
4995 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4996
a61af66fc99e Initial load
duke
parents:
diff changeset
4997 // Float Store
a61af66fc99e Initial load
duke
parents:
diff changeset
4998 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4999 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5000 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5001 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5002 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5003
a61af66fc99e Initial load
duke
parents:
diff changeset
5004 // Double Store
a61af66fc99e Initial load
duke
parents:
diff changeset
5005 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5006 instruction_count(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5007 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5008 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5009 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5010 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5011
a61af66fc99e Initial load
duke
parents:
diff changeset
5012 // Double Store
a61af66fc99e Initial load
duke
parents:
diff changeset
5013 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5014 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5015 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5016 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5017 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5018
a61af66fc99e Initial load
duke
parents:
diff changeset
5019 // Special Stack Slot Float Store
a61af66fc99e Initial load
duke
parents:
diff changeset
5020 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5021 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5022 stkSlot : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5023 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5024 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5025 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5026
a61af66fc99e Initial load
duke
parents:
diff changeset
5027 // Special Stack Slot Double Store
a61af66fc99e Initial load
duke
parents:
diff changeset
5028 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5029 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5030 stkSlot : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5031 src : C(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5032 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5033 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5034
a61af66fc99e Initial load
duke
parents:
diff changeset
5035 // Integer Load (when sign bit propagation not needed)
a61af66fc99e Initial load
duke
parents:
diff changeset
5036 pipe_class iload_mem(iRegI dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5037 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5038 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5039 dst : C(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5040 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5041 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5042
a61af66fc99e Initial load
duke
parents:
diff changeset
5043 // Integer Load from stack operand
a61af66fc99e Initial load
duke
parents:
diff changeset
5044 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5045 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5046 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5047 dst : C(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5048 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5049 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5050
a61af66fc99e Initial load
duke
parents:
diff changeset
5051 // Integer Load (when sign bit propagation or masking is needed)
a61af66fc99e Initial load
duke
parents:
diff changeset
5052 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5053 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5054 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5055 dst : M(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5056 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5057 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5058
a61af66fc99e Initial load
duke
parents:
diff changeset
5059 // Float Load
a61af66fc99e Initial load
duke
parents:
diff changeset
5060 pipe_class floadF_mem(regF dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5061 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5062 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5063 dst : M(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5064 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5065 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5066
a61af66fc99e Initial load
duke
parents:
diff changeset
5067 // Float Load
a61af66fc99e Initial load
duke
parents:
diff changeset
5068 pipe_class floadD_mem(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5069 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
a61af66fc99e Initial load
duke
parents:
diff changeset
5070 mem : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5071 dst : M(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5072 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5073 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5074
a61af66fc99e Initial load
duke
parents:
diff changeset
5075 // Float Load
a61af66fc99e Initial load
duke
parents:
diff changeset
5076 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5077 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5078 stkSlot : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5079 dst : M(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5080 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5081 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5082
a61af66fc99e Initial load
duke
parents:
diff changeset
5083 // Float Load
a61af66fc99e Initial load
duke
parents:
diff changeset
5084 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5085 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5086 stkSlot : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5087 dst : M(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5088 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5089 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5090
a61af66fc99e Initial load
duke
parents:
diff changeset
5091 // Memory Nop
a61af66fc99e Initial load
duke
parents:
diff changeset
5092 pipe_class mem_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5093 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5094 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5095 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5096
a61af66fc99e Initial load
duke
parents:
diff changeset
5097 pipe_class sethi(iRegP dst, immI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5098 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5099 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5100 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5101 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5102
a61af66fc99e Initial load
duke
parents:
diff changeset
5103 pipe_class loadPollP(iRegP poll) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5104 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5105 poll : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5106 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5107 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5108
a61af66fc99e Initial load
duke
parents:
diff changeset
5109 pipe_class br(Universe br, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5110 single_instruction_with_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5111 BR : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5112 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5113
a61af66fc99e Initial load
duke
parents:
diff changeset
5114 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5115 single_instruction_with_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5116 cr : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5117 BR : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5118 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5119
a61af66fc99e Initial load
duke
parents:
diff changeset
5120 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5121 single_instruction_with_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5122 op1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5123 BR : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5124 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5125 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5126
a61af66fc99e Initial load
duke
parents:
diff changeset
5127 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5128 single_instruction_with_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5129 cr : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5130 BR : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5131 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5132
a61af66fc99e Initial load
duke
parents:
diff changeset
5133 pipe_class br_nop() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5134 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5135 BR : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5136 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5137
a61af66fc99e Initial load
duke
parents:
diff changeset
5138 pipe_class simple_call(method meth) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5139 instruction_count(2); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
5140 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5141 BR : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5142 MS : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5143 A0 : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5144 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5145
a61af66fc99e Initial load
duke
parents:
diff changeset
5146 pipe_class compiled_call(method meth) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5147 instruction_count(1); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
5148 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5149 MS : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5150 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5151
a61af66fc99e Initial load
duke
parents:
diff changeset
5152 pipe_class call(method meth) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5153 instruction_count(0); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
5154 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5155 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5156
a61af66fc99e Initial load
duke
parents:
diff changeset
5157 pipe_class tail_call(Universe ignore, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5158 single_instruction; has_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5159 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5160 BR : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5161 MS : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5162 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5163
a61af66fc99e Initial load
duke
parents:
diff changeset
5164 pipe_class ret(Universe ignore) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5165 single_instruction; has_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5166 BR : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5167 MS : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5169
a61af66fc99e Initial load
duke
parents:
diff changeset
5170 pipe_class ret_poll(g3RegP poll) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5171 instruction_count(3); has_delay_slot;
a61af66fc99e Initial load
duke
parents:
diff changeset
5172 poll : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5173 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5174 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5175
a61af66fc99e Initial load
duke
parents:
diff changeset
5176 // The real do-nothing guy
a61af66fc99e Initial load
duke
parents:
diff changeset
5177 pipe_class empty( ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5178 instruction_count(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5180
a61af66fc99e Initial load
duke
parents:
diff changeset
5181 pipe_class long_memory_op() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5182 instruction_count(0); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
5183 fixed_latency(25);
a61af66fc99e Initial load
duke
parents:
diff changeset
5184 MS : R(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5185 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5186
a61af66fc99e Initial load
duke
parents:
diff changeset
5187 // Check-cast
a61af66fc99e Initial load
duke
parents:
diff changeset
5188 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5189 array : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5190 match : R(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5191 IALU : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5192 BR : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5193 MS : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5194 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5195
a61af66fc99e Initial load
duke
parents:
diff changeset
5196 // Convert FPU flags into +1,0,-1
a61af66fc99e Initial load
duke
parents:
diff changeset
5197 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5198 src1 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5199 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5200 dst : E(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5201 FA : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5202 MS : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5203 BR : R(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5204 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5205
a61af66fc99e Initial load
duke
parents:
diff changeset
5206 // Compare for p < q, and conditionally add y
a61af66fc99e Initial load
duke
parents:
diff changeset
5207 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5208 p : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5209 q : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5210 y : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5211 IALU : R(3)
a61af66fc99e Initial load
duke
parents:
diff changeset
5212 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5213
a61af66fc99e Initial load
duke
parents:
diff changeset
5214 // Perform a compare, then move conditionally in a branch delay slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
5215 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5216 src2 : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5217 srcdst : E(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5218 IALU : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5219 BR : R;
a61af66fc99e Initial load
duke
parents:
diff changeset
5220 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5221
a61af66fc99e Initial load
duke
parents:
diff changeset
5222 // Define the class for the Nop node
a61af66fc99e Initial load
duke
parents:
diff changeset
5223 define %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5224 MachNop = ialu_nop;
a61af66fc99e Initial load
duke
parents:
diff changeset
5225 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5226
a61af66fc99e Initial load
duke
parents:
diff changeset
5227 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5228
a61af66fc99e Initial load
duke
parents:
diff changeset
5229 //----------INSTRUCTIONS-------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5230
a61af66fc99e Initial load
duke
parents:
diff changeset
5231 //------------Special Stack Slot instructions - no match rules-----------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5232 instruct stkI_to_regF(regF dst, stackSlotI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5233 // No match rule to avoid chain rule match.
a61af66fc99e Initial load
duke
parents:
diff changeset
5234 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5235 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5236 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5237 format %{ "LDF $src,$dst\t! stkI to regF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5238 opcode(Assembler::ldf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5239 ins_encode(simple_form3_mem_reg(src, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5240 ins_pipe(floadF_stk);
a61af66fc99e Initial load
duke
parents:
diff changeset
5241 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5242
a61af66fc99e Initial load
duke
parents:
diff changeset
5243 instruct stkL_to_regD(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5244 // No match rule to avoid chain rule match.
a61af66fc99e Initial load
duke
parents:
diff changeset
5245 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5246 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5247 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5248 format %{ "LDDF $src,$dst\t! stkL to regD" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5249 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5250 ins_encode(simple_form3_mem_reg(src, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5251 ins_pipe(floadD_stk);
a61af66fc99e Initial load
duke
parents:
diff changeset
5252 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5253
a61af66fc99e Initial load
duke
parents:
diff changeset
5254 instruct regF_to_stkI(stackSlotI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5255 // No match rule to avoid chain rule match.
a61af66fc99e Initial load
duke
parents:
diff changeset
5256 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5257 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5258 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5259 format %{ "STF $src,$dst\t! regF to stkI" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5260 opcode(Assembler::stf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5261 ins_encode(simple_form3_mem_reg(dst, src));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5262 ins_pipe(fstoreF_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5263 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5264
a61af66fc99e Initial load
duke
parents:
diff changeset
5265 instruct regD_to_stkL(stackSlotL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5266 // No match rule to avoid chain rule match.
a61af66fc99e Initial load
duke
parents:
diff changeset
5267 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5268 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5269 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5270 format %{ "STDF $src,$dst\t! regD to stkL" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5271 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5272 ins_encode(simple_form3_mem_reg(dst, src));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5273 ins_pipe(fstoreD_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5274 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5275
a61af66fc99e Initial load
duke
parents:
diff changeset
5276 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5277 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5278 ins_cost(MEMORY_REF_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5279 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
5280 format %{ "STW $src,$dst.hi\t! long\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
5281 "STW R_G0,$dst.lo" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5282 opcode(Assembler::stw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5283 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5284 ins_pipe(lstoreI_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5285 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5286
a61af66fc99e Initial load
duke
parents:
diff changeset
5287 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5288 // No match rule to avoid chain rule match.
a61af66fc99e Initial load
duke
parents:
diff changeset
5289 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5290 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5291 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5292 format %{ "STX $src,$dst\t! regL to stkD" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5293 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5294 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5295 ins_pipe(istore_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5296 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5297
a61af66fc99e Initial load
duke
parents:
diff changeset
5298 //---------- Chain stack slots between similar types --------
a61af66fc99e Initial load
duke
parents:
diff changeset
5299
a61af66fc99e Initial load
duke
parents:
diff changeset
5300 // Load integer from stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
5301 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5302 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5303 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5304
a61af66fc99e Initial load
duke
parents:
diff changeset
5305 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5306 format %{ "LDUW $src,$dst\t!stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5307 opcode(Assembler::lduw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5308 ins_encode(simple_form3_mem_reg( src, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5309 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5310 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5311
a61af66fc99e Initial load
duke
parents:
diff changeset
5312 // Store integer to stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
5313 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5314 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5315 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5316
a61af66fc99e Initial load
duke
parents:
diff changeset
5317 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5318 format %{ "STW $src,$dst\t!stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5319 opcode(Assembler::stw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5320 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5321 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5322 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5323
a61af66fc99e Initial load
duke
parents:
diff changeset
5324 // Load long from stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
5325 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5326 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5327
a61af66fc99e Initial load
duke
parents:
diff changeset
5328 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5329 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5330 format %{ "LDX $src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5331 opcode(Assembler::ldx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5332 ins_encode(simple_form3_mem_reg( src, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5333 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5334 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5335
a61af66fc99e Initial load
duke
parents:
diff changeset
5336 // Store long to stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
5337 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5338 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5339
a61af66fc99e Initial load
duke
parents:
diff changeset
5340 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5341 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5342 format %{ "STX $src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5343 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5344 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5345 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5346 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5347
a61af66fc99e Initial load
duke
parents:
diff changeset
5348 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
5349 // Load pointer from stack slot, 64-bit encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
5350 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5351 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5352 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5353 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5354 format %{ "LDX $src,$dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5355 opcode(Assembler::ldx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5356 ins_encode(simple_form3_mem_reg( src, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5357 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5358 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5359
a61af66fc99e Initial load
duke
parents:
diff changeset
5360 // Store pointer to stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
5361 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5362 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5363 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5364 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5365 format %{ "STX $src,$dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5366 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5367 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5368 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5369 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5370 #else // _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
5371 // Load pointer from stack slot, 32-bit encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
5372 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5373 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5374 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5375 format %{ "LDUW $src,$dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5376 opcode(Assembler::lduw_op3, Assembler::ldst_op);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5377 ins_encode(simple_form3_mem_reg( src, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5378 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5379 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5380
a61af66fc99e Initial load
duke
parents:
diff changeset
5381 // Store pointer to stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
5382 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5383 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5384 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5385 format %{ "STW $src,$dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5386 opcode(Assembler::stw_op3, Assembler::ldst_op);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5387 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5388 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5389 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5390 #endif // _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
5391
a61af66fc99e Initial load
duke
parents:
diff changeset
5392 //------------Special Nop instructions for bundling - no match rules-----------
a61af66fc99e Initial load
duke
parents:
diff changeset
5393 // Nop using the A0 functional unit
a61af66fc99e Initial load
duke
parents:
diff changeset
5394 instruct Nop_A0() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5395 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5396
a61af66fc99e Initial load
duke
parents:
diff changeset
5397 format %{ "NOP ! Alu Pipeline" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5398 opcode(Assembler::or_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
5399 ins_encode( form2_nop() );
a61af66fc99e Initial load
duke
parents:
diff changeset
5400 ins_pipe(ialu_nop_A0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5401 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5402
a61af66fc99e Initial load
duke
parents:
diff changeset
5403 // Nop using the A1 functional unit
a61af66fc99e Initial load
duke
parents:
diff changeset
5404 instruct Nop_A1( ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5405 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5406
a61af66fc99e Initial load
duke
parents:
diff changeset
5407 format %{ "NOP ! Alu Pipeline" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5408 opcode(Assembler::or_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
5409 ins_encode( form2_nop() );
a61af66fc99e Initial load
duke
parents:
diff changeset
5410 ins_pipe(ialu_nop_A1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5411 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5412
a61af66fc99e Initial load
duke
parents:
diff changeset
5413 // Nop using the memory functional unit
a61af66fc99e Initial load
duke
parents:
diff changeset
5414 instruct Nop_MS( ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5415 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5416
a61af66fc99e Initial load
duke
parents:
diff changeset
5417 format %{ "NOP ! Memory Pipeline" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5418 ins_encode( emit_mem_nop );
a61af66fc99e Initial load
duke
parents:
diff changeset
5419 ins_pipe(mem_nop);
a61af66fc99e Initial load
duke
parents:
diff changeset
5420 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5421
a61af66fc99e Initial load
duke
parents:
diff changeset
5422 // Nop using the floating add functional unit
a61af66fc99e Initial load
duke
parents:
diff changeset
5423 instruct Nop_FA( ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5424 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5425
a61af66fc99e Initial load
duke
parents:
diff changeset
5426 format %{ "NOP ! Floating Add Pipeline" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5427 ins_encode( emit_fadd_nop );
a61af66fc99e Initial load
duke
parents:
diff changeset
5428 ins_pipe(fadd_nop);
a61af66fc99e Initial load
duke
parents:
diff changeset
5429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5430
a61af66fc99e Initial load
duke
parents:
diff changeset
5431 // Nop using the branch functional unit
a61af66fc99e Initial load
duke
parents:
diff changeset
5432 instruct Nop_BR( ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5433 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5434
a61af66fc99e Initial load
duke
parents:
diff changeset
5435 format %{ "NOP ! Branch Pipeline" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5436 ins_encode( emit_br_nop );
a61af66fc99e Initial load
duke
parents:
diff changeset
5437 ins_pipe(br_nop);
a61af66fc99e Initial load
duke
parents:
diff changeset
5438 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5439
a61af66fc99e Initial load
duke
parents:
diff changeset
5440 //----------Load/Store/Move Instructions---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5441 //----------Load Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5442 // Load Byte (8bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
5443 instruct loadB(iRegI dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5444 match(Set dst (LoadB mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5445 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5446
a61af66fc99e Initial load
duke
parents:
diff changeset
5447 size(4);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5448 format %{ "LDSB $mem,$dst\t! byte" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5449 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5450 __ ldsb($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5451 %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5452 ins_pipe(iload_mask_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5453 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5454
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5455 // Load Byte (8bit signed) into a Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5456 instruct loadB2L(iRegL dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5457 match(Set dst (ConvI2L (LoadB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5458 ins_cost(MEMORY_REF_COST);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5459
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5460 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5461 format %{ "LDSB $mem,$dst\t! byte -> long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5462 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5463 __ ldsb($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5464 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5465 ins_pipe(iload_mask_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5466 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5467
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5468 // Load Unsigned Byte (8bit UNsigned) into an int reg
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5469 instruct loadUB(iRegI dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5470 match(Set dst (LoadUB mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5471 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5472
a61af66fc99e Initial load
duke
parents:
diff changeset
5473 size(4);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5474 format %{ "LDUB $mem,$dst\t! ubyte" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5475 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5476 __ ldub($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5477 %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5478 ins_pipe(iload_mask_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5479 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5480
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5481 // Load Unsigned Byte (8bit UNsigned) into a Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5482 instruct loadUB2L(iRegL dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5483 match(Set dst (ConvI2L (LoadUB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5484 ins_cost(MEMORY_REF_COST);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5485
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5486 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5487 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5488 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5489 __ ldub($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5490 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5491 ins_pipe(iload_mask_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5492 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5493
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5494 // Load Short (16bit signed)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5495 instruct loadS(iRegI dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5496 match(Set dst (LoadS mem));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5497 ins_cost(MEMORY_REF_COST);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5498
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5499 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5500 format %{ "LDSH $mem,$dst\t! short" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5501 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5502 __ ldsh($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5503 %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5504 ins_pipe(iload_mask_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5505 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5506
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5507 // Load Short (16bit signed) into a Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5508 instruct loadS2L(iRegL dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5509 match(Set dst (ConvI2L (LoadS mem)));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5510 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5511
a61af66fc99e Initial load
duke
parents:
diff changeset
5512 size(4);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5513 format %{ "LDSH $mem,$dst\t! short -> long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5514 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5515 __ ldsh($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5516 %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5517 ins_pipe(iload_mask_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5518 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5519
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5520 // Load Unsigned Short/Char (16bit UNsigned)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5521 instruct loadUS(iRegI dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5522 match(Set dst (LoadUS mem));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5523 ins_cost(MEMORY_REF_COST);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5524
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5525 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5526 format %{ "LDUH $mem,$dst\t! ushort/char" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5527 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5528 __ lduh($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5529 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5530 ins_pipe(iload_mask_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5531 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5532
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 551
diff changeset
5533 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5534 instruct loadUS2L(iRegL dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5535 match(Set dst (ConvI2L (LoadUS mem)));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5536 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5537
a61af66fc99e Initial load
duke
parents:
diff changeset
5538 size(4);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5539 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5540 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5541 __ lduh($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5542 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5543 ins_pipe(iload_mask_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5545
a61af66fc99e Initial load
duke
parents:
diff changeset
5546 // Load Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
5547 instruct loadI(iRegI dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5548 match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5549 ins_cost(MEMORY_REF_COST);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5550
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5551 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5552 format %{ "LDUW $mem,$dst\t! int" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5553 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5554 __ lduw($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5555 %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5556 ins_pipe(iload_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5557 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5558
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5559 // Load Integer into a Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5560 instruct loadI2L(iRegL dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5561 match(Set dst (ConvI2L (LoadI mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5562 ins_cost(MEMORY_REF_COST);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5563
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5564 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5565 format %{ "LDSW $mem,$dst\t! int -> long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5566 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5567 __ ldsw($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5568 %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5569 ins_pipe(iload_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5570 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5571
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5572 // Load Unsigned Integer into a Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5573 instruct loadUI2L(iRegL dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5574 match(Set dst (LoadUI2L mem));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5575 ins_cost(MEMORY_REF_COST);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5576
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5577 size(4);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5578 format %{ "LDUW $mem,$dst\t! uint -> long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5579 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5580 __ lduw($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5581 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5582 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5583 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5584
a61af66fc99e Initial load
duke
parents:
diff changeset
5585 // Load Long - aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
5586 instruct loadL(iRegL dst, memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5587 match(Set dst (LoadL mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5588 ins_cost(MEMORY_REF_COST);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 605
diff changeset
5589
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5590 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5591 format %{ "LDX $mem,$dst\t! long" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5592 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5593 __ ldx($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5594 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5595 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5596 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5597
a61af66fc99e Initial load
duke
parents:
diff changeset
5598 // Load Long - UNaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
5599 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5600 match(Set dst (LoadL_unaligned mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5601 effect(KILL tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
5602 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5603 size(16);
a61af66fc99e Initial load
duke
parents:
diff changeset
5604 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
5605 "\tLDUW $mem ,$dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
5606 "\tSLLX #32, $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
5607 "\tOR $dst, R_O7, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5608 opcode(Assembler::lduw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5609 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5610 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5611 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5612
a61af66fc99e Initial load
duke
parents:
diff changeset
5613 // Load Aligned Packed Byte into a Double Register
a61af66fc99e Initial load
duke
parents:
diff changeset
5614 instruct loadA8B(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5615 match(Set dst (Load8B mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5616 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5617 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5618 format %{ "LDDF $mem,$dst\t! packed8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5619 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5620 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5621 ins_pipe(floadD_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5622 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5623
a61af66fc99e Initial load
duke
parents:
diff changeset
5624 // Load Aligned Packed Char into a Double Register
a61af66fc99e Initial load
duke
parents:
diff changeset
5625 instruct loadA4C(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5626 match(Set dst (Load4C mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5627 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5628 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5629 format %{ "LDDF $mem,$dst\t! packed4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5630 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5631 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5632 ins_pipe(floadD_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5633 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5634
a61af66fc99e Initial load
duke
parents:
diff changeset
5635 // Load Aligned Packed Short into a Double Register
a61af66fc99e Initial load
duke
parents:
diff changeset
5636 instruct loadA4S(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5637 match(Set dst (Load4S mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5638 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5639 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5640 format %{ "LDDF $mem,$dst\t! packed4S" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5641 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5642 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5643 ins_pipe(floadD_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5644 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5645
a61af66fc99e Initial load
duke
parents:
diff changeset
5646 // Load Aligned Packed Int into a Double Register
a61af66fc99e Initial load
duke
parents:
diff changeset
5647 instruct loadA2I(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5648 match(Set dst (Load2I mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5649 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5650 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5651 format %{ "LDDF $mem,$dst\t! packed2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5652 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5653 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5654 ins_pipe(floadD_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5655 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5656
a61af66fc99e Initial load
duke
parents:
diff changeset
5657 // Load Range
a61af66fc99e Initial load
duke
parents:
diff changeset
5658 instruct loadRange(iRegI dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5659 match(Set dst (LoadRange mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5660 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5661
a61af66fc99e Initial load
duke
parents:
diff changeset
5662 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5663 format %{ "LDUW $mem,$dst\t! range" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5664 opcode(Assembler::lduw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5665 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5666 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5668
a61af66fc99e Initial load
duke
parents:
diff changeset
5669 // Load Integer into %f register (for fitos/fitod)
a61af66fc99e Initial load
duke
parents:
diff changeset
5670 instruct loadI_freg(regF dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5671 match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5672 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5673 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5674
a61af66fc99e Initial load
duke
parents:
diff changeset
5675 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5676 opcode(Assembler::ldf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5677 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5678 ins_pipe(floadF_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5679 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5680
a61af66fc99e Initial load
duke
parents:
diff changeset
5681 // Load Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5682 instruct loadP(iRegP dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5683 match(Set dst (LoadP mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5684 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5685 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5686
a61af66fc99e Initial load
duke
parents:
diff changeset
5687 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
5688 format %{ "LDUW $mem,$dst\t! ptr" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5689 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5690 __ lduw($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5691 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5692 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
5693 format %{ "LDX $mem,$dst\t! ptr" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5694 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5695 __ ldx($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5696 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5697 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
5698 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5699 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5700
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5701 // Load Compressed Pointer
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5702 instruct loadN(iRegN dst, memory mem) %{
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5703 match(Set dst (LoadN mem));
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5704 ins_cost(MEMORY_REF_COST);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5705 size(4);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5706
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5707 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5708 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5709 __ lduw($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5710 %}
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5711 ins_pipe(iload_mem);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5712 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5713
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5714 // Load Klass Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5715 instruct loadKlass(iRegP dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5716 match(Set dst (LoadKlass mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5717 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5718 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5719
a61af66fc99e Initial load
duke
parents:
diff changeset
5720 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
5721 format %{ "LDUW $mem,$dst\t! klass ptr" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5722 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5723 __ lduw($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5724 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5725 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
5726 format %{ "LDX $mem,$dst\t! klass ptr" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5727 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5728 __ ldx($mem$$Address, $dst$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5729 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5730 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
5731 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5732 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5733
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5734 // Load narrow Klass Pointer
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5735 instruct loadNKlass(iRegN dst, memory mem) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5736 match(Set dst (LoadNKlass mem));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5737 ins_cost(MEMORY_REF_COST);
165
437d03ea40b1 6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents: 164
diff changeset
5738 size(4);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5739
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5740 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5741 ins_encode %{
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5742 __ lduw($mem$$Address, $dst$$Register);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5743 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5744 ins_pipe(iload_mem);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5745 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5746
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5747 // Load Double
a61af66fc99e Initial load
duke
parents:
diff changeset
5748 instruct loadD(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5749 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5750 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5751
a61af66fc99e Initial load
duke
parents:
diff changeset
5752 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5753 format %{ "LDDF $mem,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5754 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5755 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5756 ins_pipe(floadD_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5757 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5758
a61af66fc99e Initial load
duke
parents:
diff changeset
5759 // Load Double - UNaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
5760 instruct loadD_unaligned(regD_low dst, memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5761 match(Set dst (LoadD_unaligned mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5762 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5763 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
5764 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
5765 "\tLDF $mem+4,$dst.lo\t!" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5766 opcode(Assembler::ldf_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5767 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
a61af66fc99e Initial load
duke
parents:
diff changeset
5768 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5769 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5770
a61af66fc99e Initial load
duke
parents:
diff changeset
5771 // Load Float
a61af66fc99e Initial load
duke
parents:
diff changeset
5772 instruct loadF(regF dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5773 match(Set dst (LoadF mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5774 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5775
a61af66fc99e Initial load
duke
parents:
diff changeset
5776 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5777 format %{ "LDF $mem,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5778 opcode(Assembler::ldf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5779 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5780 ins_pipe(floadF_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5781 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5782
a61af66fc99e Initial load
duke
parents:
diff changeset
5783 // Load Constant
a61af66fc99e Initial load
duke
parents:
diff changeset
5784 instruct loadConI( iRegI dst, immI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5785 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5786 ins_cost(DEFAULT_COST * 3/2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5787 format %{ "SET $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5788 ins_encode( Set32(src, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5789 ins_pipe(ialu_hi_lo_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5790 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5791
a61af66fc99e Initial load
duke
parents:
diff changeset
5792 instruct loadConI13( iRegI dst, immI13 src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5793 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5794
a61af66fc99e Initial load
duke
parents:
diff changeset
5795 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5796 format %{ "MOV $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5797 ins_encode( Set13( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5798 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5799 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5800
a61af66fc99e Initial load
duke
parents:
diff changeset
5801 instruct loadConP(iRegP dst, immP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5802 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5803 ins_cost(DEFAULT_COST * 3/2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5804 format %{ "SET $src,$dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5805 // This rule does not use "expand" unlike loadConI because then
a61af66fc99e Initial load
duke
parents:
diff changeset
5806 // the result type is not known to be an Oop. An ADLC
a61af66fc99e Initial load
duke
parents:
diff changeset
5807 // enhancement will be needed to make that work - not worth it!
a61af66fc99e Initial load
duke
parents:
diff changeset
5808
a61af66fc99e Initial load
duke
parents:
diff changeset
5809 ins_encode( SetPtr( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5810 ins_pipe(loadConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
5811
a61af66fc99e Initial load
duke
parents:
diff changeset
5812 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5813
a61af66fc99e Initial load
duke
parents:
diff changeset
5814 instruct loadConP0(iRegP dst, immP0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5815 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5816
a61af66fc99e Initial load
duke
parents:
diff changeset
5817 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5818 format %{ "CLR $dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5819 ins_encode( SetNull( dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5820 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5821 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5822
a61af66fc99e Initial load
duke
parents:
diff changeset
5823 instruct loadConP_poll(iRegP dst, immP_poll src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5824 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5825 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5826 format %{ "SET $src,$dst\t!ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5827 ins_encode %{
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5828 AddressLiteral polling_page(os::get_polling_page());
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5829 __ sethi(polling_page, reg_to_register_object($dst$$reg));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5830 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5831 ins_pipe(loadConP_poll);
a61af66fc99e Initial load
duke
parents:
diff changeset
5832 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5833
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5834 instruct loadConN0(iRegN dst, immN0 src) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5835 match(Set dst src);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5836
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5837 size(4);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5838 format %{ "CLR $dst\t! compressed NULL ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5839 ins_encode( SetNull( dst ) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5840 ins_pipe(ialu_imm);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5841 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5842
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5843 instruct loadConN(iRegN dst, immN src) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5844 match(Set dst src);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5845 ins_cost(DEFAULT_COST * 3/2);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5846 format %{ "SET $src,$dst\t! compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5847 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5848 Register dst = $dst$$Register;
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5849 __ set_narrow_oop((jobject)$src$$constant, dst);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5850 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5851 ins_pipe(ialu_hi_lo_reg);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5852 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
5853
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5854 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5855 // %%% maybe this should work like loadConD
a61af66fc99e Initial load
duke
parents:
diff changeset
5856 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5857 effect(KILL tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
5858 ins_cost(DEFAULT_COST * 4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5859 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5860 ins_encode( LdImmL(src, dst, tmp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5861 ins_pipe(loadConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
5862 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5863
a61af66fc99e Initial load
duke
parents:
diff changeset
5864 instruct loadConL0( iRegL dst, immL0 src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5865 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5866 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5867 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5868 format %{ "CLR $dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5869 ins_encode( Set13( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5870 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5871 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5872
a61af66fc99e Initial load
duke
parents:
diff changeset
5873 instruct loadConL13( iRegL dst, immL13 src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5874 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5875 ins_cost(DEFAULT_COST * 2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5876
a61af66fc99e Initial load
duke
parents:
diff changeset
5877 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5878 format %{ "MOV $src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5879 ins_encode( Set13( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5880 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5881 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5882
a61af66fc99e Initial load
duke
parents:
diff changeset
5883 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5884 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5885 effect(KILL tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
5886
a61af66fc99e Initial load
duke
parents:
diff changeset
5887 #ifdef _LP64
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5888 size(8*4);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5889 #else
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5890 size(2*4);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5891 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
5892
a61af66fc99e Initial load
duke
parents:
diff changeset
5893 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
5894 "LDF [$tmp+lo(&$src)],$dst" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5895 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5896 address float_address = __ float_constant($src$$constant);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5897 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5898 AddressLiteral addrlit(float_address, rspec);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5899
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5900 __ sethi(addrlit, $tmp$$Register);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5901 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5902 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5903 ins_pipe(loadConFD);
a61af66fc99e Initial load
duke
parents:
diff changeset
5904 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5905
a61af66fc99e Initial load
duke
parents:
diff changeset
5906 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5907 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5908 effect(KILL tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
5909
a61af66fc99e Initial load
duke
parents:
diff changeset
5910 #ifdef _LP64
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5911 size(8*4);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5912 #else
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5913 size(2*4);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5914 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
5915
a61af66fc99e Initial load
duke
parents:
diff changeset
5916 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
5917 "LDDF [$tmp+lo(&$src)],$dst" %}
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5918 ins_encode %{
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5919 address double_address = __ double_constant($src$$constant);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5920 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5921 AddressLiteral addrlit(double_address, rspec);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5922
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5923 __ sethi(addrlit, $tmp$$Register);
732
fb4c18a2ec66 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 727
diff changeset
5924 // XXX This is a quick fix for 6833573.
fb4c18a2ec66 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 727
diff changeset
5925 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
fb4c18a2ec66 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 727
diff changeset
5926 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
727
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC
twisti
parents: 681
diff changeset
5927 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5928 ins_pipe(loadConFD);
a61af66fc99e Initial load
duke
parents:
diff changeset
5929 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5930
a61af66fc99e Initial load
duke
parents:
diff changeset
5931 // Prefetch instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
5932 // Must be safe to execute with invalid address (cannot fault).
a61af66fc99e Initial load
duke
parents:
diff changeset
5933
a61af66fc99e Initial load
duke
parents:
diff changeset
5934 instruct prefetchr( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5935 match( PrefetchRead mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
5936 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5937
a61af66fc99e Initial load
duke
parents:
diff changeset
5938 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5939 opcode(Assembler::prefetch_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5940 ins_encode( form3_mem_prefetch_read( mem ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5941 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5942 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5943
a61af66fc99e Initial load
duke
parents:
diff changeset
5944 instruct prefetchw( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5945 match( PrefetchWrite mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
5946 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5947
a61af66fc99e Initial load
duke
parents:
diff changeset
5948 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5949 opcode(Assembler::prefetch_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5950 ins_encode( form3_mem_prefetch_write( mem ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
5951 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5952 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5953
a61af66fc99e Initial load
duke
parents:
diff changeset
5954
a61af66fc99e Initial load
duke
parents:
diff changeset
5955 //----------Store Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5956 // Store Byte
a61af66fc99e Initial load
duke
parents:
diff changeset
5957 instruct storeB(memory mem, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5958 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5959 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5960
a61af66fc99e Initial load
duke
parents:
diff changeset
5961 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5962 format %{ "STB $src,$mem\t! byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5963 opcode(Assembler::stb_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5964 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5965 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5966 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5967
a61af66fc99e Initial load
duke
parents:
diff changeset
5968 instruct storeB0(memory mem, immI0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5969 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5970 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5971
a61af66fc99e Initial load
duke
parents:
diff changeset
5972 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5973 format %{ "STB $src,$mem\t! byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5974 opcode(Assembler::stb_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5975 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5976 ins_pipe(istore_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
5977 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5978
a61af66fc99e Initial load
duke
parents:
diff changeset
5979 instruct storeCM0(memory mem, immI0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5980 match(Set mem (StoreCM mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5981 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5982
a61af66fc99e Initial load
duke
parents:
diff changeset
5983 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5984 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5985 opcode(Assembler::stb_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5986 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5987 ins_pipe(istore_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
5988 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5989
a61af66fc99e Initial load
duke
parents:
diff changeset
5990 // Store Char/Short
a61af66fc99e Initial load
duke
parents:
diff changeset
5991 instruct storeC(memory mem, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5992 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5993 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
5994
a61af66fc99e Initial load
duke
parents:
diff changeset
5995 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5996 format %{ "STH $src,$mem\t! short" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5997 opcode(Assembler::sth_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
5998 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5999 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6000 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6001
a61af66fc99e Initial load
duke
parents:
diff changeset
6002 instruct storeC0(memory mem, immI0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6003 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6004 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6005
a61af66fc99e Initial load
duke
parents:
diff changeset
6006 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6007 format %{ "STH $src,$mem\t! short" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6008 opcode(Assembler::sth_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6009 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6010 ins_pipe(istore_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6011 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6012
a61af66fc99e Initial load
duke
parents:
diff changeset
6013 // Store Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
6014 instruct storeI(memory mem, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6015 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6016 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6017
a61af66fc99e Initial load
duke
parents:
diff changeset
6018 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6019 format %{ "STW $src,$mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6020 opcode(Assembler::stw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6021 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6022 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6023 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6024
a61af66fc99e Initial load
duke
parents:
diff changeset
6025 // Store Long
a61af66fc99e Initial load
duke
parents:
diff changeset
6026 instruct storeL(memory mem, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6027 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6028 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6029 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6030 format %{ "STX $src,$mem\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6031 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6032 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6033 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6034 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6035
a61af66fc99e Initial load
duke
parents:
diff changeset
6036 instruct storeI0(memory mem, immI0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6037 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6038 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6039
a61af66fc99e Initial load
duke
parents:
diff changeset
6040 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6041 format %{ "STW $src,$mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6042 opcode(Assembler::stw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6043 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6044 ins_pipe(istore_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6045 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6046
a61af66fc99e Initial load
duke
parents:
diff changeset
6047 instruct storeL0(memory mem, immL0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6048 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6049 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6050
a61af66fc99e Initial load
duke
parents:
diff changeset
6051 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6052 format %{ "STX $src,$mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6053 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6054 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6055 ins_pipe(istore_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6056 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6057
a61af66fc99e Initial load
duke
parents:
diff changeset
6058 // Store Integer from float register (used after fstoi)
a61af66fc99e Initial load
duke
parents:
diff changeset
6059 instruct storeI_Freg(memory mem, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6060 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6061 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6062
a61af66fc99e Initial load
duke
parents:
diff changeset
6063 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6064 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6065 opcode(Assembler::stf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6066 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6067 ins_pipe(fstoreF_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6068 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6069
a61af66fc99e Initial load
duke
parents:
diff changeset
6070 // Store Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
6071 instruct storeP(memory dst, sp_ptr_RegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6072 match(Set dst (StoreP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6073 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6074 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6075
a61af66fc99e Initial load
duke
parents:
diff changeset
6076 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
6077 format %{ "STW $src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6078 opcode(Assembler::stw_op3, 0, REGP_OP);
a61af66fc99e Initial load
duke
parents:
diff changeset
6079 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
6080 format %{ "STX $src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6081 opcode(Assembler::stx_op3, 0, REGP_OP);
a61af66fc99e Initial load
duke
parents:
diff changeset
6082 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
6083 ins_encode( form3_mem_reg( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6084 ins_pipe(istore_mem_spORreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6085 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6086
a61af66fc99e Initial load
duke
parents:
diff changeset
6087 instruct storeP0(memory dst, immP0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6088 match(Set dst (StoreP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6089 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6090 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6091
a61af66fc99e Initial load
duke
parents:
diff changeset
6092 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
6093 format %{ "STW $src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6094 opcode(Assembler::stw_op3, 0, REGP_OP);
a61af66fc99e Initial load
duke
parents:
diff changeset
6095 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
6096 format %{ "STX $src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6097 opcode(Assembler::stx_op3, 0, REGP_OP);
a61af66fc99e Initial load
duke
parents:
diff changeset
6098 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
6099 ins_encode( form3_mem_reg( dst, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6100 ins_pipe(istore_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6101 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6102
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6103 // Store Compressed Pointer
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6104 instruct storeN(memory dst, iRegN src) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6105 match(Set dst (StoreN dst src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6106 ins_cost(MEMORY_REF_COST);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6107 size(4);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6108
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6109 format %{ "STW $src,$dst\t! compressed ptr" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6110 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6111 Register base = as_Register($dst$$base);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6112 Register index = as_Register($dst$$index);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6113 Register src = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6114 if (index != G0) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6115 __ stw(src, base, index);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6116 } else {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6117 __ stw(src, base, $dst$$disp);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6118 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6119 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6120 ins_pipe(istore_mem_spORreg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6121 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6122
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6123 instruct storeN0(memory dst, immN0 src) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6124 match(Set dst (StoreN dst src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6125 ins_cost(MEMORY_REF_COST);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6126 size(4);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6127
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6128 format %{ "STW $src,$dst\t! compressed ptr" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6129 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6130 Register base = as_Register($dst$$base);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6131 Register index = as_Register($dst$$index);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6132 if (index != G0) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6133 __ stw(0, base, index);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6134 } else {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6135 __ stw(0, base, $dst$$disp);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6136 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6137 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6138 ins_pipe(istore_mem_zero);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6139 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6140
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6141 // Store Double
a61af66fc99e Initial load
duke
parents:
diff changeset
6142 instruct storeD( memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6143 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6144 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6145
a61af66fc99e Initial load
duke
parents:
diff changeset
6146 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6147 format %{ "STDF $src,$mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6148 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6149 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6150 ins_pipe(fstoreD_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6151 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6152
a61af66fc99e Initial load
duke
parents:
diff changeset
6153 instruct storeD0( memory mem, immD0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6154 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6155 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6156
a61af66fc99e Initial load
duke
parents:
diff changeset
6157 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6158 format %{ "STX $src,$mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6159 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6160 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6161 ins_pipe(fstoreD_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6162 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6163
a61af66fc99e Initial load
duke
parents:
diff changeset
6164 // Store Float
a61af66fc99e Initial load
duke
parents:
diff changeset
6165 instruct storeF( memory mem, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6166 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6167 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6168
a61af66fc99e Initial load
duke
parents:
diff changeset
6169 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6170 format %{ "STF $src,$mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6171 opcode(Assembler::stf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6172 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6173 ins_pipe(fstoreF_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6174 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6175
a61af66fc99e Initial load
duke
parents:
diff changeset
6176 instruct storeF0( memory mem, immF0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6177 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6178 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6179
a61af66fc99e Initial load
duke
parents:
diff changeset
6180 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6181 format %{ "STW $src,$mem\t! storeF0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6182 opcode(Assembler::stw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6183 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6184 ins_pipe(fstoreF_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6185 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6186
a61af66fc99e Initial load
duke
parents:
diff changeset
6187 // Store Aligned Packed Bytes in Double register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
6188 instruct storeA8B(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6189 match(Set mem (Store8B mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6190 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6191 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6192 format %{ "STDF $src,$mem\t! packed8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6193 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6194 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6195 ins_pipe(fstoreD_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6196 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6197
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6198 // Convert oop pointer into compressed form
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6199 instruct encodeHeapOop(iRegN dst, iRegP src) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
6200 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6201 match(Set dst (EncodeP src));
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6202 format %{ "encode_heap_oop $src, $dst" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6203 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6204 __ encode_heap_oop($src$$Register, $dst$$Register);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6205 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6206 ins_pipe(ialu_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6207 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6208
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6209 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
6210 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6211 match(Set dst (EncodeP src));
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6212 format %{ "encode_heap_oop_not_null $src, $dst" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6213 ins_encode %{
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6214 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6215 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6216 ins_pipe(ialu_reg);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6217 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6218
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6219 instruct decodeHeapOop(iRegP dst, iRegN src) %{
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 181
diff changeset
6220 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 181
diff changeset
6221 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6222 match(Set dst (DecodeN src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6223 format %{ "decode_heap_oop $src, $dst" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6224 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6225 __ decode_heap_oop($src$$Register, $dst$$Register);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6226 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6227 ins_pipe(ialu_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6228 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6229
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6230 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 181
diff changeset
6231 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 181
diff changeset
6232 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6233 match(Set dst (DecodeN src));
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6234 format %{ "decode_heap_oop_not_null $src, $dst" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6235 ins_encode %{
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6236 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6237 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6238 ins_pipe(ialu_reg);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6239 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6240
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6241
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6242 // Store Zero into Aligned Packed Bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
6243 instruct storeA8B0(memory mem, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6244 match(Set mem (Store8B mem zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
6245 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6246 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6247 format %{ "STX $zero,$mem\t! packed8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6248 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6249 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6250 ins_pipe(fstoreD_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6251 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6252
a61af66fc99e Initial load
duke
parents:
diff changeset
6253 // Store Aligned Packed Chars/Shorts in Double register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
6254 instruct storeA4C(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6255 match(Set mem (Store4C mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6256 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6257 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6258 format %{ "STDF $src,$mem\t! packed4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6259 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6260 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6261 ins_pipe(fstoreD_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6262 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6263
a61af66fc99e Initial load
duke
parents:
diff changeset
6264 // Store Zero into Aligned Packed Chars/Shorts
a61af66fc99e Initial load
duke
parents:
diff changeset
6265 instruct storeA4C0(memory mem, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6266 match(Set mem (Store4C mem (Replicate4C zero)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6267 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6268 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6269 format %{ "STX $zero,$mem\t! packed4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6270 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6272 ins_pipe(fstoreD_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6273 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6274
a61af66fc99e Initial load
duke
parents:
diff changeset
6275 // Store Aligned Packed Ints in Double register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
6276 instruct storeA2I(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6277 match(Set mem (Store2I mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6278 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6279 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6280 format %{ "STDF $src,$mem\t! packed2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6281 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6282 ins_encode(simple_form3_mem_reg( mem, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6283 ins_pipe(fstoreD_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6284 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6285
a61af66fc99e Initial load
duke
parents:
diff changeset
6286 // Store Zero into Aligned Packed Ints
a61af66fc99e Initial load
duke
parents:
diff changeset
6287 instruct storeA2I0(memory mem, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6288 match(Set mem (Store2I mem zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
6289 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6290 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6291 format %{ "STX $zero,$mem\t! packed2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6292 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6293 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6294 ins_pipe(fstoreD_mem_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
6295 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6296
a61af66fc99e Initial load
duke
parents:
diff changeset
6297
a61af66fc99e Initial load
duke
parents:
diff changeset
6298 //----------MemBar Instructions-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6299 // Memory barrier flavors
a61af66fc99e Initial load
duke
parents:
diff changeset
6300
a61af66fc99e Initial load
duke
parents:
diff changeset
6301 instruct membar_acquire() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6302 match(MemBarAcquire);
a61af66fc99e Initial load
duke
parents:
diff changeset
6303 ins_cost(4*MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6304
a61af66fc99e Initial load
duke
parents:
diff changeset
6305 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6306 format %{ "MEMBAR-acquire" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6307 ins_encode( enc_membar_acquire );
a61af66fc99e Initial load
duke
parents:
diff changeset
6308 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6309 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6310
a61af66fc99e Initial load
duke
parents:
diff changeset
6311 instruct membar_acquire_lock() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6312 match(MemBarAcquire);
a61af66fc99e Initial load
duke
parents:
diff changeset
6313 predicate(Matcher::prior_fast_lock(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
6314 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6315
a61af66fc99e Initial load
duke
parents:
diff changeset
6316 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6317 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6318 ins_encode( );
a61af66fc99e Initial load
duke
parents:
diff changeset
6319 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6320 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6321
a61af66fc99e Initial load
duke
parents:
diff changeset
6322 instruct membar_release() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6323 match(MemBarRelease);
a61af66fc99e Initial load
duke
parents:
diff changeset
6324 ins_cost(4*MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6325
a61af66fc99e Initial load
duke
parents:
diff changeset
6326 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6327 format %{ "MEMBAR-release" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6328 ins_encode( enc_membar_release );
a61af66fc99e Initial load
duke
parents:
diff changeset
6329 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6330 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6331
a61af66fc99e Initial load
duke
parents:
diff changeset
6332 instruct membar_release_lock() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6333 match(MemBarRelease);
a61af66fc99e Initial load
duke
parents:
diff changeset
6334 predicate(Matcher::post_fast_unlock(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
6335 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6336
a61af66fc99e Initial load
duke
parents:
diff changeset
6337 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6338 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6339 ins_encode( );
a61af66fc99e Initial load
duke
parents:
diff changeset
6340 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6341 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6342
a61af66fc99e Initial load
duke
parents:
diff changeset
6343 instruct membar_volatile() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6344 match(MemBarVolatile);
a61af66fc99e Initial load
duke
parents:
diff changeset
6345 ins_cost(4*MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6346
a61af66fc99e Initial load
duke
parents:
diff changeset
6347 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6348 format %{ "MEMBAR-volatile" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6349 ins_encode( enc_membar_volatile );
a61af66fc99e Initial load
duke
parents:
diff changeset
6350 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6351 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6352
a61af66fc99e Initial load
duke
parents:
diff changeset
6353 instruct unnecessary_membar_volatile() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6354 match(MemBarVolatile);
a61af66fc99e Initial load
duke
parents:
diff changeset
6355 predicate(Matcher::post_store_load_barrier(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
6356 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6357
a61af66fc99e Initial load
duke
parents:
diff changeset
6358 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6359 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6360 ins_encode( );
a61af66fc99e Initial load
duke
parents:
diff changeset
6361 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6362 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6363
a61af66fc99e Initial load
duke
parents:
diff changeset
6364 //----------Register Move Instructions-----------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6365 instruct roundDouble_nop(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6366 match(Set dst (RoundDouble dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6367 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6368 // SPARC results are already "rounded" (i.e., normal-format IEEE)
a61af66fc99e Initial load
duke
parents:
diff changeset
6369 ins_encode( );
a61af66fc99e Initial load
duke
parents:
diff changeset
6370 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6371 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6372
a61af66fc99e Initial load
duke
parents:
diff changeset
6373
a61af66fc99e Initial load
duke
parents:
diff changeset
6374 instruct roundFloat_nop(regF dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6375 match(Set dst (RoundFloat dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6376 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6377 // SPARC results are already "rounded" (i.e., normal-format IEEE)
a61af66fc99e Initial load
duke
parents:
diff changeset
6378 ins_encode( );
a61af66fc99e Initial load
duke
parents:
diff changeset
6379 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6380 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6381
a61af66fc99e Initial load
duke
parents:
diff changeset
6382
a61af66fc99e Initial load
duke
parents:
diff changeset
6383 // Cast Index to Pointer for unsafe natives
a61af66fc99e Initial load
duke
parents:
diff changeset
6384 instruct castX2P(iRegX src, iRegP dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6385 match(Set dst (CastX2P src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6386
a61af66fc99e Initial load
duke
parents:
diff changeset
6387 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6388 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6389 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6390 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6391
a61af66fc99e Initial load
duke
parents:
diff changeset
6392 // Cast Pointer to Index for unsafe natives
a61af66fc99e Initial load
duke
parents:
diff changeset
6393 instruct castP2X(iRegP src, iRegX dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6394 match(Set dst (CastP2X src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6395
a61af66fc99e Initial load
duke
parents:
diff changeset
6396 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6397 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6398 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6399 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6400
a61af66fc99e Initial load
duke
parents:
diff changeset
6401 instruct stfSSD(stackSlotD stkSlot, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6402 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
a61af66fc99e Initial load
duke
parents:
diff changeset
6403 match(Set stkSlot src); // chain rule
a61af66fc99e Initial load
duke
parents:
diff changeset
6404 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6405 format %{ "STDF $src,$stkSlot\t!stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6406 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6407 ins_encode(simple_form3_mem_reg(stkSlot, src));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6408 ins_pipe(fstoreD_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6409 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6410
a61af66fc99e Initial load
duke
parents:
diff changeset
6411 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6412 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
a61af66fc99e Initial load
duke
parents:
diff changeset
6413 match(Set dst stkSlot); // chain rule
a61af66fc99e Initial load
duke
parents:
diff changeset
6414 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6415 format %{ "LDDF $stkSlot,$dst\t!stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6416 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6417 ins_encode(simple_form3_mem_reg(stkSlot, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6418 ins_pipe(floadD_stk);
a61af66fc99e Initial load
duke
parents:
diff changeset
6419 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6420
a61af66fc99e Initial load
duke
parents:
diff changeset
6421 instruct stfSSF(stackSlotF stkSlot, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6422 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
a61af66fc99e Initial load
duke
parents:
diff changeset
6423 match(Set stkSlot src); // chain rule
a61af66fc99e Initial load
duke
parents:
diff changeset
6424 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6425 format %{ "STF $src,$stkSlot\t!stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6426 opcode(Assembler::stf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6427 ins_encode(simple_form3_mem_reg(stkSlot, src));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6428 ins_pipe(fstoreF_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6430
a61af66fc99e Initial load
duke
parents:
diff changeset
6431 //----------Conditional Move---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6432 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6433 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6434 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6435 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6436 format %{ "MOV$cmp $pcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6437 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6438 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6439 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6440
a61af66fc99e Initial load
duke
parents:
diff changeset
6441 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6442 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6443 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6444 format %{ "MOV$cmp $pcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6445 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6446 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6447 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6448
a61af66fc99e Initial load
duke
parents:
diff changeset
6449 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6450 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6451 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6452 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6453 format %{ "MOV$cmp $icc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6454 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6455 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6456 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6457
a61af66fc99e Initial load
duke
parents:
diff changeset
6458 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6459 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6460 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6461 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6462 format %{ "MOV$cmp $icc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6463 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6464 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6465 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6466
81
dee7a3f3dc9d 6636352: Unit tests for supplementary character support fail with -XX:+AggressiveOpts
never
parents: 0
diff changeset
6467 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6468 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6469 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6470 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6471 format %{ "MOV$cmp $icc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6472 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6473 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6474 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6475
81
dee7a3f3dc9d 6636352: Unit tests for supplementary character support fail with -XX:+AggressiveOpts
never
parents: 0
diff changeset
6476 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6477 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6478 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6479 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6480 format %{ "MOV$cmp $icc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6481 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6482 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6483 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6484
a61af66fc99e Initial load
duke
parents:
diff changeset
6485 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6486 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6487 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6488 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6489 format %{ "MOV$cmp $fcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6490 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6491 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6492 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6493
a61af66fc99e Initial load
duke
parents:
diff changeset
6494 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6495 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6496 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6497 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6498 format %{ "MOV$cmp $fcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6499 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6500 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6501 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6502
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6503 // Conditional move for RegN. Only cmov(reg,reg).
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6504 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6505 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6506 ins_cost(150);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6507 format %{ "MOV$cmp $pcc,$src,$dst" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6508 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6509 ins_pipe(ialu_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6510 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6511
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6512 // This instruction also works with CmpN so we don't need cmovNN_reg.
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6513 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6514 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6515 ins_cost(150);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6516 size(4);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6517 format %{ "MOV$cmp $icc,$src,$dst" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6518 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6519 ins_pipe(ialu_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6520 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6521
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6522 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6523 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6524 ins_cost(150);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6525 size(4);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6526 format %{ "MOV$cmp $fcc,$src,$dst" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6527 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6528 ins_pipe(ialu_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6529 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6530
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6531 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6532 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6533 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6534 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6535 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6536 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6537 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6538 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6539
a61af66fc99e Initial load
duke
parents:
diff changeset
6540 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6541 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6542 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6543 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6544 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6545 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6546 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6547
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6548 // This instruction also works with CmpN so we don't need cmovPN_reg.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6549 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6550 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6551 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6552
a61af66fc99e Initial load
duke
parents:
diff changeset
6553 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6554 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6555 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6556 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6557 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6558
a61af66fc99e Initial load
duke
parents:
diff changeset
6559 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6560 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6561 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6562
a61af66fc99e Initial load
duke
parents:
diff changeset
6563 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6564 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6565 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6566 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6567 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6568
a61af66fc99e Initial load
duke
parents:
diff changeset
6569 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6570 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6571 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6572 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6573 format %{ "MOV$cmp $fcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6574 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6575 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6576 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6577
a61af66fc99e Initial load
duke
parents:
diff changeset
6578 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6579 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6580 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6581 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6582 format %{ "MOV$cmp $fcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6583 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6584 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6585 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6586
a61af66fc99e Initial load
duke
parents:
diff changeset
6587 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6588 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6589 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6590 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6591 opcode(0x101);
a61af66fc99e Initial load
duke
parents:
diff changeset
6592 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6593 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6594 ins_pipe(int_conditional_float_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
6595 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6596
a61af66fc99e Initial load
duke
parents:
diff changeset
6597 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6598 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6599 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6600
a61af66fc99e Initial load
duke
parents:
diff changeset
6601 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6602 format %{ "FMOVS$cmp $icc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6603 opcode(0x101);
a61af66fc99e Initial load
duke
parents:
diff changeset
6604 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6605 ins_pipe(int_conditional_float_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
6606 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6607
a61af66fc99e Initial load
duke
parents:
diff changeset
6608 // Conditional move,
a61af66fc99e Initial load
duke
parents:
diff changeset
6609 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6610 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6611 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6612 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6613 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6614 opcode(0x1);
a61af66fc99e Initial load
duke
parents:
diff changeset
6615 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6616 ins_pipe(int_conditional_double_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
6617 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6618
a61af66fc99e Initial load
duke
parents:
diff changeset
6619 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6620 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6621 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6622 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6623 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6624 opcode(0x102);
a61af66fc99e Initial load
duke
parents:
diff changeset
6625 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6626 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6627 ins_pipe(int_conditional_double_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
6628 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6629
a61af66fc99e Initial load
duke
parents:
diff changeset
6630 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6631 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6632 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6633
a61af66fc99e Initial load
duke
parents:
diff changeset
6634 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6635 format %{ "FMOVD$cmp $icc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6636 opcode(0x102);
a61af66fc99e Initial load
duke
parents:
diff changeset
6637 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6638 ins_pipe(int_conditional_double_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
6639 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6640
a61af66fc99e Initial load
duke
parents:
diff changeset
6641 // Conditional move,
a61af66fc99e Initial load
duke
parents:
diff changeset
6642 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6643 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6644 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6645 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6646 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6647 opcode(0x2);
a61af66fc99e Initial load
duke
parents:
diff changeset
6648 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6649 ins_pipe(int_conditional_double_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
6650 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6651
a61af66fc99e Initial load
duke
parents:
diff changeset
6652 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6653 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6654 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6655 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6656 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6657 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6658 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6659 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6660
a61af66fc99e Initial load
duke
parents:
diff changeset
6661 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6662 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6663 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
6664 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6665 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6666 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6668
a61af66fc99e Initial load
duke
parents:
diff changeset
6669 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6670 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6671 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6672
a61af66fc99e Initial load
duke
parents:
diff changeset
6673 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6674 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6675 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6676 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6677 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6678
a61af66fc99e Initial load
duke
parents:
diff changeset
6679
a61af66fc99e Initial load
duke
parents:
diff changeset
6680 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6681 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6682 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6683
a61af66fc99e Initial load
duke
parents:
diff changeset
6684 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6685 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6686 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6687 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6688 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6689
a61af66fc99e Initial load
duke
parents:
diff changeset
6690
a61af66fc99e Initial load
duke
parents:
diff changeset
6691
a61af66fc99e Initial load
duke
parents:
diff changeset
6692 //----------OS and Locking Instructions----------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6693
a61af66fc99e Initial load
duke
parents:
diff changeset
6694 // This name is KNOWN by the ADLC and cannot be changed.
a61af66fc99e Initial load
duke
parents:
diff changeset
6695 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
a61af66fc99e Initial load
duke
parents:
diff changeset
6696 // for this guy.
a61af66fc99e Initial load
duke
parents:
diff changeset
6697 instruct tlsLoadP(g2RegP dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6698 match(Set dst (ThreadLocal));
a61af66fc99e Initial load
duke
parents:
diff changeset
6699
a61af66fc99e Initial load
duke
parents:
diff changeset
6700 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6701 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6702 format %{ "# TLS is in G2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6703 ins_encode( /*empty encoding*/ );
a61af66fc99e Initial load
duke
parents:
diff changeset
6704 ins_pipe(ialu_none);
a61af66fc99e Initial load
duke
parents:
diff changeset
6705 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6706
a61af66fc99e Initial load
duke
parents:
diff changeset
6707 instruct checkCastPP( iRegP dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6708 match(Set dst (CheckCastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6709
a61af66fc99e Initial load
duke
parents:
diff changeset
6710 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6711 format %{ "# checkcastPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6712 ins_encode( /*empty encoding*/ );
a61af66fc99e Initial load
duke
parents:
diff changeset
6713 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6714 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6715
a61af66fc99e Initial load
duke
parents:
diff changeset
6716
a61af66fc99e Initial load
duke
parents:
diff changeset
6717 instruct castPP( iRegP dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6718 match(Set dst (CastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6719 format %{ "# castPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6720 ins_encode( /*empty encoding*/ );
a61af66fc99e Initial load
duke
parents:
diff changeset
6721 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6722 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6723
a61af66fc99e Initial load
duke
parents:
diff changeset
6724 instruct castII( iRegI dst ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6725 match(Set dst (CastII dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6726 format %{ "# castII of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6727 ins_encode( /*empty encoding*/ );
a61af66fc99e Initial load
duke
parents:
diff changeset
6728 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6729 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6730 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6731
a61af66fc99e Initial load
duke
parents:
diff changeset
6732 //----------Arithmetic Instructions--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6733 // Addition Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
6734 // Register Addition
a61af66fc99e Initial load
duke
parents:
diff changeset
6735 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6736 match(Set dst (AddI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6737
a61af66fc99e Initial load
duke
parents:
diff changeset
6738 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6739 format %{ "ADD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6740 ins_encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6741 __ add($src1$$Register, $src2$$Register, $dst$$Register);
a61af66fc99e Initial load
duke
parents:
diff changeset
6742 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6743 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6744 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6745
a61af66fc99e Initial load
duke
parents:
diff changeset
6746 // Immediate Addition
a61af66fc99e Initial load
duke
parents:
diff changeset
6747 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6748 match(Set dst (AddI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6749
a61af66fc99e Initial load
duke
parents:
diff changeset
6750 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6751 format %{ "ADD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6752 opcode(Assembler::add_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6753 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6754 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6755 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6756
a61af66fc99e Initial load
duke
parents:
diff changeset
6757 // Pointer Register Addition
a61af66fc99e Initial load
duke
parents:
diff changeset
6758 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6759 match(Set dst (AddP src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6760
a61af66fc99e Initial load
duke
parents:
diff changeset
6761 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6762 format %{ "ADD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6763 opcode(Assembler::add_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6764 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6765 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6766 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6767
a61af66fc99e Initial load
duke
parents:
diff changeset
6768 // Pointer Immediate Addition
a61af66fc99e Initial load
duke
parents:
diff changeset
6769 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6770 match(Set dst (AddP src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6771
a61af66fc99e Initial load
duke
parents:
diff changeset
6772 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6773 format %{ "ADD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6774 opcode(Assembler::add_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6775 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6776 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6777 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6778
a61af66fc99e Initial load
duke
parents:
diff changeset
6779 // Long Addition
a61af66fc99e Initial load
duke
parents:
diff changeset
6780 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6781 match(Set dst (AddL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6782
a61af66fc99e Initial load
duke
parents:
diff changeset
6783 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6784 format %{ "ADD $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6785 opcode(Assembler::add_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6786 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6787 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6788 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6789
a61af66fc99e Initial load
duke
parents:
diff changeset
6790 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6791 match(Set dst (AddL src1 con));
a61af66fc99e Initial load
duke
parents:
diff changeset
6792
a61af66fc99e Initial load
duke
parents:
diff changeset
6793 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6794 format %{ "ADD $src1,$con,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6795 opcode(Assembler::add_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6796 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6797 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6798 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6799
a61af66fc99e Initial load
duke
parents:
diff changeset
6800 //----------Conditional_store--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6801 // Conditional-store of the updated heap-top.
a61af66fc99e Initial load
duke
parents:
diff changeset
6802 // Used during allocation of the shared heap.
a61af66fc99e Initial load
duke
parents:
diff changeset
6803 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
a61af66fc99e Initial load
duke
parents:
diff changeset
6804
a61af66fc99e Initial load
duke
parents:
diff changeset
6805 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
a61af66fc99e Initial load
duke
parents:
diff changeset
6806 instruct loadPLocked(iRegP dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6807 match(Set dst (LoadPLocked mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6808 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6809
a61af66fc99e Initial load
duke
parents:
diff changeset
6810 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
6811 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6812 format %{ "LDUW $mem,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6813 opcode(Assembler::lduw_op3, 0, REGP_OP);
a61af66fc99e Initial load
duke
parents:
diff changeset
6814 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
6815 format %{ "LDX $mem,$dst\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6816 opcode(Assembler::ldx_op3, 0, REGP_OP);
a61af66fc99e Initial load
duke
parents:
diff changeset
6817 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
6818 ins_encode( form3_mem_reg( mem, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6819 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6820 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6821
a61af66fc99e Initial load
duke
parents:
diff changeset
6822 // LoadL-locked. Same as a regular long load when used with a compare-swap
a61af66fc99e Initial load
duke
parents:
diff changeset
6823 instruct loadLLocked(iRegL dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6824 match(Set dst (LoadLLocked mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6825 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
6826 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6827 format %{ "LDX $mem,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6828 opcode(Assembler::ldx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
6829 ins_encode(simple_form3_mem_reg( mem, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6830 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6831 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6832
a61af66fc99e Initial load
duke
parents:
diff changeset
6833 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6834 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6835 effect( KILL newval );
a61af66fc99e Initial load
duke
parents:
diff changeset
6836 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6837 "CMP R_G3,$oldval\t\t! See if we made progress" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6838 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6839 ins_pipe( long_memory_op );
a61af66fc99e Initial load
duke
parents:
diff changeset
6840 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6841
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6842 // Conditional-store of an int value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6843 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6844 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6845 effect( KILL newval );
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6846 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6847 "CMP $oldval,$newval\t\t! See if we made progress" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6848 ins_encode( enc_cas(mem_ptr,oldval,newval) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6849 ins_pipe( long_memory_op );
a61af66fc99e Initial load
duke
parents:
diff changeset
6850 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6851
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6852 // Conditional-store of a long value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6853 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6854 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6855 effect( KILL newval );
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6856 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6857 "CMP $oldval,$newval\t\t! See if we made progress" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
6858 ins_encode( enc_cas(mem_ptr,oldval,newval) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6859 ins_pipe( long_memory_op );
a61af66fc99e Initial load
duke
parents:
diff changeset
6860 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6861
a61af66fc99e Initial load
duke
parents:
diff changeset
6862 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
a61af66fc99e Initial load
duke
parents:
diff changeset
6863
a61af66fc99e Initial load
duke
parents:
diff changeset
6864 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6865 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6866 effect( USE mem_ptr, KILL ccr, KILL tmp1);
a61af66fc99e Initial load
duke
parents:
diff changeset
6867 format %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6868 "MOV $newval,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6869 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6870 "CMP $oldval,O7\t\t! See if we made progress\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6871 "MOV 1,$res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6872 "MOVne xcc,R_G0,$res"
a61af66fc99e Initial load
duke
parents:
diff changeset
6873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6874 ins_encode( enc_casx(mem_ptr, oldval, newval),
a61af66fc99e Initial load
duke
parents:
diff changeset
6875 enc_lflags_ne_to_boolean(res) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6876 ins_pipe( long_memory_op );
a61af66fc99e Initial load
duke
parents:
diff changeset
6877 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6878
a61af66fc99e Initial load
duke
parents:
diff changeset
6879
a61af66fc99e Initial load
duke
parents:
diff changeset
6880 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6881 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6882 effect( USE mem_ptr, KILL ccr, KILL tmp1);
a61af66fc99e Initial load
duke
parents:
diff changeset
6883 format %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6884 "MOV $newval,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6885 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6886 "CMP $oldval,O7\t\t! See if we made progress\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6887 "MOV 1,$res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6888 "MOVne icc,R_G0,$res"
a61af66fc99e Initial load
duke
parents:
diff changeset
6889 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6890 ins_encode( enc_casi(mem_ptr, oldval, newval),
a61af66fc99e Initial load
duke
parents:
diff changeset
6891 enc_iflags_ne_to_boolean(res) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6892 ins_pipe( long_memory_op );
a61af66fc99e Initial load
duke
parents:
diff changeset
6893 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6894
a61af66fc99e Initial load
duke
parents:
diff changeset
6895 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6896 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6897 effect( USE mem_ptr, KILL ccr, KILL tmp1);
a61af66fc99e Initial load
duke
parents:
diff changeset
6898 format %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6899 "MOV $newval,O7\n\t"
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6900 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6901 "CMP $oldval,O7\t\t! See if we made progress\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6902 "MOV 1,$res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6903 "MOVne xcc,R_G0,$res"
a61af66fc99e Initial load
duke
parents:
diff changeset
6904 %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6905 #ifdef _LP64
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6906 ins_encode( enc_casx(mem_ptr, oldval, newval),
a61af66fc99e Initial load
duke
parents:
diff changeset
6907 enc_lflags_ne_to_boolean(res) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6908 #else
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6909 ins_encode( enc_casi(mem_ptr, oldval, newval),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6910 enc_iflags_ne_to_boolean(res) );
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6911 #endif
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6912 ins_pipe( long_memory_op );
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6913 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6914
181
823298b11afc 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 165
diff changeset
6915 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
6916 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
181
823298b11afc 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 165
diff changeset
6917 effect( USE mem_ptr, KILL ccr, KILL tmp1);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6918 format %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6919 "MOV $newval,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6920 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6921 "CMP $oldval,O7\t\t! See if we made progress\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6922 "MOV 1,$res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6923 "MOVne icc,R_G0,$res"
a61af66fc99e Initial load
duke
parents:
diff changeset
6924 %}
181
823298b11afc 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 165
diff changeset
6925 ins_encode( enc_casi(mem_ptr, oldval, newval),
823298b11afc 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 165
diff changeset
6926 enc_iflags_ne_to_boolean(res) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6927 ins_pipe( long_memory_op );
a61af66fc99e Initial load
duke
parents:
diff changeset
6928 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6929
a61af66fc99e Initial load
duke
parents:
diff changeset
6930 //---------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6931 // Subtraction Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
6932 // Register Subtraction
a61af66fc99e Initial load
duke
parents:
diff changeset
6933 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6934 match(Set dst (SubI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6935
a61af66fc99e Initial load
duke
parents:
diff changeset
6936 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6937 format %{ "SUB $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6938 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6939 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6940 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6941 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6942
a61af66fc99e Initial load
duke
parents:
diff changeset
6943 // Immediate Subtraction
a61af66fc99e Initial load
duke
parents:
diff changeset
6944 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6945 match(Set dst (SubI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6946
a61af66fc99e Initial load
duke
parents:
diff changeset
6947 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6948 format %{ "SUB $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6949 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6950 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6951 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6952 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6953
a61af66fc99e Initial load
duke
parents:
diff changeset
6954 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6955 match(Set dst (SubI zero src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6956
a61af66fc99e Initial load
duke
parents:
diff changeset
6957 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6958 format %{ "NEG $src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6959 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6960 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6961 ins_pipe(ialu_zero_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6962 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6963
a61af66fc99e Initial load
duke
parents:
diff changeset
6964 // Long subtraction
a61af66fc99e Initial load
duke
parents:
diff changeset
6965 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6966 match(Set dst (SubL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6967
a61af66fc99e Initial load
duke
parents:
diff changeset
6968 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6969 format %{ "SUB $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6970 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6971 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6972 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6973 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6974
a61af66fc99e Initial load
duke
parents:
diff changeset
6975 // Immediate Subtraction
a61af66fc99e Initial load
duke
parents:
diff changeset
6976 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6977 match(Set dst (SubL src1 con));
a61af66fc99e Initial load
duke
parents:
diff changeset
6978
a61af66fc99e Initial load
duke
parents:
diff changeset
6979 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6980 format %{ "SUB $src1,$con,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6981 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6982 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6983 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6984 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6985
a61af66fc99e Initial load
duke
parents:
diff changeset
6986 // Long negation
a61af66fc99e Initial load
duke
parents:
diff changeset
6987 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6988 match(Set dst (SubL zero src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
6989
a61af66fc99e Initial load
duke
parents:
diff changeset
6990 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
6991 format %{ "NEG $src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6992 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
6993 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6994 ins_pipe(ialu_zero_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6995 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6996
a61af66fc99e Initial load
duke
parents:
diff changeset
6997 // Multiplication Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
6998 // Integer Multiplication
a61af66fc99e Initial load
duke
parents:
diff changeset
6999 // Register Multiplication
a61af66fc99e Initial load
duke
parents:
diff changeset
7000 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7001 match(Set dst (MulI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7002
a61af66fc99e Initial load
duke
parents:
diff changeset
7003 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7004 format %{ "MULX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7005 opcode(Assembler::mulx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7006 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7007 ins_pipe(imul_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7008 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7009
a61af66fc99e Initial load
duke
parents:
diff changeset
7010 // Immediate Multiplication
a61af66fc99e Initial load
duke
parents:
diff changeset
7011 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7012 match(Set dst (MulI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7013
a61af66fc99e Initial load
duke
parents:
diff changeset
7014 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7015 format %{ "MULX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7016 opcode(Assembler::mulx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7018 ins_pipe(imul_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7019 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7020
a61af66fc99e Initial load
duke
parents:
diff changeset
7021 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7022 match(Set dst (MulL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7023 ins_cost(DEFAULT_COST * 5);
a61af66fc99e Initial load
duke
parents:
diff changeset
7024 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7025 format %{ "MULX $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7026 opcode(Assembler::mulx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7027 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7028 ins_pipe(mulL_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7029 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7030
a61af66fc99e Initial load
duke
parents:
diff changeset
7031 // Immediate Multiplication
a61af66fc99e Initial load
duke
parents:
diff changeset
7032 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7033 match(Set dst (MulL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7034 ins_cost(DEFAULT_COST * 5);
a61af66fc99e Initial load
duke
parents:
diff changeset
7035 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7036 format %{ "MULX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7037 opcode(Assembler::mulx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7038 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7039 ins_pipe(mulL_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7040 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7041
a61af66fc99e Initial load
duke
parents:
diff changeset
7042 // Integer Division
a61af66fc99e Initial load
duke
parents:
diff changeset
7043 // Register Division
a61af66fc99e Initial load
duke
parents:
diff changeset
7044 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7045 match(Set dst (DivI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7046 ins_cost((2+71)*DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7047
a61af66fc99e Initial load
duke
parents:
diff changeset
7048 format %{ "SRA $src2,0,$src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7049 "SRA $src1,0,$src1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7050 "SDIVX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7051 ins_encode( idiv_reg( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7052 ins_pipe(sdiv_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7053 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7054
a61af66fc99e Initial load
duke
parents:
diff changeset
7055 // Immediate Division
a61af66fc99e Initial load
duke
parents:
diff changeset
7056 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7057 match(Set dst (DivI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7058 ins_cost((2+71)*DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7059
a61af66fc99e Initial load
duke
parents:
diff changeset
7060 format %{ "SRA $src1,0,$src1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7061 "SDIVX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7062 ins_encode( idiv_imm( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7063 ins_pipe(sdiv_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7064 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7065
a61af66fc99e Initial load
duke
parents:
diff changeset
7066 //----------Div-By-10-Expansion------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7067 // Extract hi bits of a 32x32->64 bit multiply.
a61af66fc99e Initial load
duke
parents:
diff changeset
7068 // Expand rule only, not matched
a61af66fc99e Initial load
duke
parents:
diff changeset
7069 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7070 effect( DEF dst, USE src1, USE src2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
7071 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7072 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7073 ins_encode( enc_mul_hi(dst,src1,src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7074 ins_pipe(sdiv_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7075 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7076
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
7077 // Magic constant, reciprocal of 10
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7078 instruct loadConI_x66666667(iRegIsafe dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7079 effect( DEF dst );
a61af66fc99e Initial load
duke
parents:
diff changeset
7080
a61af66fc99e Initial load
duke
parents:
diff changeset
7081 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
7082 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7083 ins_encode( Set32(0x66666667, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7084 ins_pipe(ialu_hi_lo_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7085 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7086
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
7087 // Register Shift Right Arithmetic Long by 32-63
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7088 instruct sra_31( iRegI dst, iRegI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7089 effect( DEF dst, USE src );
a61af66fc99e Initial load
duke
parents:
diff changeset
7090 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7091 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7092 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7093 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7094
a61af66fc99e Initial load
duke
parents:
diff changeset
7095 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7096 instruct sra_reg_2( iRegI dst, iRegI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7097 effect( DEF dst, USE src );
a61af66fc99e Initial load
duke
parents:
diff changeset
7098 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7099 opcode(Assembler::sra_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7100 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7101 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7102 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7103
a61af66fc99e Initial load
duke
parents:
diff changeset
7104 // Integer DIV with 10
a61af66fc99e Initial load
duke
parents:
diff changeset
7105 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7106 match(Set dst (DivI src div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7107 ins_cost((6+6)*DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7108 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7109 iRegIsafe tmp1; // Killed temps;
a61af66fc99e Initial load
duke
parents:
diff changeset
7110 iRegIsafe tmp2; // Killed temps;
a61af66fc99e Initial load
duke
parents:
diff changeset
7111 iRegI tmp3; // Killed temps;
a61af66fc99e Initial load
duke
parents:
diff changeset
7112 iRegI tmp4; // Killed temps;
a61af66fc99e Initial load
duke
parents:
diff changeset
7113 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
a61af66fc99e Initial load
duke
parents:
diff changeset
7114 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
a61af66fc99e Initial load
duke
parents:
diff changeset
7115 sra_31( tmp3, src ); // SRA src,31 -> tmp3
a61af66fc99e Initial load
duke
parents:
diff changeset
7116 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
a61af66fc99e Initial load
duke
parents:
diff changeset
7117 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
a61af66fc99e Initial load
duke
parents:
diff changeset
7118 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7119 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7120
a61af66fc99e Initial load
duke
parents:
diff changeset
7121 // Register Long Division
a61af66fc99e Initial load
duke
parents:
diff changeset
7122 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7123 match(Set dst (DivL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7124 ins_cost(DEFAULT_COST*71);
a61af66fc99e Initial load
duke
parents:
diff changeset
7125 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7126 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7127 opcode(Assembler::sdivx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7128 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7129 ins_pipe(divL_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7130 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7131
a61af66fc99e Initial load
duke
parents:
diff changeset
7132 // Register Long Division
a61af66fc99e Initial load
duke
parents:
diff changeset
7133 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7134 match(Set dst (DivL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7135 ins_cost(DEFAULT_COST*71);
a61af66fc99e Initial load
duke
parents:
diff changeset
7136 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7137 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7138 opcode(Assembler::sdivx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7139 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7140 ins_pipe(divL_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7141 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7142
a61af66fc99e Initial load
duke
parents:
diff changeset
7143 // Integer Remainder
a61af66fc99e Initial load
duke
parents:
diff changeset
7144 // Register Remainder
a61af66fc99e Initial load
duke
parents:
diff changeset
7145 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7146 match(Set dst (ModI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7147 effect( KILL ccr, KILL temp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7148
a61af66fc99e Initial load
duke
parents:
diff changeset
7149 format %{ "SREM $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7150 ins_encode( irem_reg(src1, src2, dst, temp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7151 ins_pipe(sdiv_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7152 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7153
a61af66fc99e Initial load
duke
parents:
diff changeset
7154 // Immediate Remainder
a61af66fc99e Initial load
duke
parents:
diff changeset
7155 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7156 match(Set dst (ModI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7157 effect( KILL ccr, KILL temp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7158
a61af66fc99e Initial load
duke
parents:
diff changeset
7159 format %{ "SREM $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7160 ins_encode( irem_imm(src1, src2, dst, temp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7161 ins_pipe(sdiv_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7162 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7163
a61af66fc99e Initial load
duke
parents:
diff changeset
7164 // Register Long Remainder
a61af66fc99e Initial load
duke
parents:
diff changeset
7165 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7166 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7167 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7168 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7169 opcode(Assembler::sdivx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7170 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7171 ins_pipe(divL_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7172 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7173
a61af66fc99e Initial load
duke
parents:
diff changeset
7174 // Register Long Division
a61af66fc99e Initial load
duke
parents:
diff changeset
7175 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7176 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7177 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7178 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7179 opcode(Assembler::sdivx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7180 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7181 ins_pipe(divL_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7182 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7183
a61af66fc99e Initial load
duke
parents:
diff changeset
7184 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7185 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7186 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7187 format %{ "MULX $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7188 opcode(Assembler::mulx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7189 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7190 ins_pipe(mulL_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7191 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7192
a61af66fc99e Initial load
duke
parents:
diff changeset
7193 // Immediate Multiplication
a61af66fc99e Initial load
duke
parents:
diff changeset
7194 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7195 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7196 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7197 format %{ "MULX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7198 opcode(Assembler::mulx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7199 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7200 ins_pipe(mulL_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7201 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7202
a61af66fc99e Initial load
duke
parents:
diff changeset
7203 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7204 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7205 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7206 format %{ "SUB $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7207 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7208 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7209 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7210 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7211
a61af66fc99e Initial load
duke
parents:
diff changeset
7212 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7213 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7214 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7215 format %{ "SUB $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7216 opcode(Assembler::sub_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7217 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7218 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7219 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7220
a61af66fc99e Initial load
duke
parents:
diff changeset
7221 // Register Long Remainder
a61af66fc99e Initial load
duke
parents:
diff changeset
7222 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7223 match(Set dst (ModL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7224 ins_cost(DEFAULT_COST*(71 + 6 + 1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7225 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7226 iRegL tmp1;
a61af66fc99e Initial load
duke
parents:
diff changeset
7227 iRegL tmp2;
a61af66fc99e Initial load
duke
parents:
diff changeset
7228 divL_reg_reg_1(tmp1, src1, src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7229 mulL_reg_reg_1(tmp2, tmp1, src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7230 subL_reg_reg_1(dst, src1, tmp2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7231 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7232 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7233
a61af66fc99e Initial load
duke
parents:
diff changeset
7234 // Register Long Remainder
a61af66fc99e Initial load
duke
parents:
diff changeset
7235 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7236 match(Set dst (ModL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7237 ins_cost(DEFAULT_COST*(71 + 6 + 1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7238 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7239 iRegL tmp1;
a61af66fc99e Initial load
duke
parents:
diff changeset
7240 iRegL tmp2;
a61af66fc99e Initial load
duke
parents:
diff changeset
7241 divL_reg_imm13_1(tmp1, src1, src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7242 mulL_reg_imm13_1(tmp2, tmp1, src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7243 subL_reg_reg_2 (dst, src1, tmp2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7244 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7245 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7246
a61af66fc99e Initial load
duke
parents:
diff changeset
7247 // Integer Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7248 // Register Shift Left
a61af66fc99e Initial load
duke
parents:
diff changeset
7249 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7250 match(Set dst (LShiftI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7251
a61af66fc99e Initial load
duke
parents:
diff changeset
7252 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7253 format %{ "SLL $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7254 opcode(Assembler::sll_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7255 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7256 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7257 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7258
a61af66fc99e Initial load
duke
parents:
diff changeset
7259 // Register Shift Left Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7260 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7261 match(Set dst (LShiftI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7262
a61af66fc99e Initial load
duke
parents:
diff changeset
7263 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7264 format %{ "SLL $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7265 opcode(Assembler::sll_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7266 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7267 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7268 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7269
a61af66fc99e Initial load
duke
parents:
diff changeset
7270 // Register Shift Left
a61af66fc99e Initial load
duke
parents:
diff changeset
7271 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7272 match(Set dst (LShiftL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7273
a61af66fc99e Initial load
duke
parents:
diff changeset
7274 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7275 format %{ "SLLX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7276 opcode(Assembler::sllx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7277 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7278 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7279 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7280
a61af66fc99e Initial load
duke
parents:
diff changeset
7281 // Register Shift Left Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7282 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7283 match(Set dst (LShiftL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7284
a61af66fc99e Initial load
duke
parents:
diff changeset
7285 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7286 format %{ "SLLX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7287 opcode(Assembler::sllx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7288 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7289 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7290 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7291
a61af66fc99e Initial load
duke
parents:
diff changeset
7292 // Register Arithmetic Shift Right
a61af66fc99e Initial load
duke
parents:
diff changeset
7293 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7294 match(Set dst (RShiftI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7295 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7296 format %{ "SRA $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7297 opcode(Assembler::sra_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7298 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7299 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7300 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7301
a61af66fc99e Initial load
duke
parents:
diff changeset
7302 // Register Arithmetic Shift Right Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7303 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7304 match(Set dst (RShiftI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7305
a61af66fc99e Initial load
duke
parents:
diff changeset
7306 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7307 format %{ "SRA $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7308 opcode(Assembler::sra_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7309 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7310 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7311 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7312
a61af66fc99e Initial load
duke
parents:
diff changeset
7313 // Register Shift Right Arithmatic Long
a61af66fc99e Initial load
duke
parents:
diff changeset
7314 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7315 match(Set dst (RShiftL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7316
a61af66fc99e Initial load
duke
parents:
diff changeset
7317 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7318 format %{ "SRAX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7319 opcode(Assembler::srax_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7320 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7321 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7322 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7323
a61af66fc99e Initial load
duke
parents:
diff changeset
7324 // Register Shift Left Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7325 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7326 match(Set dst (RShiftL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7327
a61af66fc99e Initial load
duke
parents:
diff changeset
7328 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7329 format %{ "SRAX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7330 opcode(Assembler::srax_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7331 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7332 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7333 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7334
a61af66fc99e Initial load
duke
parents:
diff changeset
7335 // Register Shift Right
a61af66fc99e Initial load
duke
parents:
diff changeset
7336 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7337 match(Set dst (URShiftI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7338
a61af66fc99e Initial load
duke
parents:
diff changeset
7339 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7340 format %{ "SRL $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7341 opcode(Assembler::srl_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7342 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7343 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7344 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7345
a61af66fc99e Initial load
duke
parents:
diff changeset
7346 // Register Shift Right Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7347 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7348 match(Set dst (URShiftI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7349
a61af66fc99e Initial load
duke
parents:
diff changeset
7350 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7351 format %{ "SRL $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7352 opcode(Assembler::srl_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7353 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7354 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7355 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7356
a61af66fc99e Initial load
duke
parents:
diff changeset
7357 // Register Shift Right
a61af66fc99e Initial load
duke
parents:
diff changeset
7358 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7359 match(Set dst (URShiftL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7360
a61af66fc99e Initial load
duke
parents:
diff changeset
7361 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7362 format %{ "SRLX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7363 opcode(Assembler::srlx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7364 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7365 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7366 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7367
a61af66fc99e Initial load
duke
parents:
diff changeset
7368 // Register Shift Right Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7369 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7370 match(Set dst (URShiftL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7371
a61af66fc99e Initial load
duke
parents:
diff changeset
7372 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7373 format %{ "SRLX $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7374 opcode(Assembler::srlx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7375 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7376 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7377 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7378
a61af66fc99e Initial load
duke
parents:
diff changeset
7379 // Register Shift Right Immediate with a CastP2X
a61af66fc99e Initial load
duke
parents:
diff changeset
7380 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
7381 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7382 match(Set dst (URShiftL (CastP2X src1) src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7383 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7384 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7385 opcode(Assembler::srlx_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7386 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7387 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7388 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7389 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
7390 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7391 match(Set dst (URShiftI (CastP2X src1) src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7392 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7393 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7394 opcode(Assembler::srl_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7395 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7396 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7397 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7398 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
7399
a61af66fc99e Initial load
duke
parents:
diff changeset
7400
a61af66fc99e Initial load
duke
parents:
diff changeset
7401 //----------Floating Point Arithmetic Instructions-----------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7402
a61af66fc99e Initial load
duke
parents:
diff changeset
7403 // Add float single precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7404 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7405 match(Set dst (AddF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7406
a61af66fc99e Initial load
duke
parents:
diff changeset
7407 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7408 format %{ "FADDS $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7410 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7411 ins_pipe(faddF_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7412 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7413
a61af66fc99e Initial load
duke
parents:
diff changeset
7414 // Add float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7415 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7416 match(Set dst (AddD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7417
a61af66fc99e Initial load
duke
parents:
diff changeset
7418 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7419 format %{ "FADDD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7420 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7421 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7422 ins_pipe(faddD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7423 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7424
a61af66fc99e Initial load
duke
parents:
diff changeset
7425 // Sub float single precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7426 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7427 match(Set dst (SubF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7428
a61af66fc99e Initial load
duke
parents:
diff changeset
7429 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7430 format %{ "FSUBS $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7431 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7432 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7433 ins_pipe(faddF_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7434 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7435
a61af66fc99e Initial load
duke
parents:
diff changeset
7436 // Sub float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7437 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7438 match(Set dst (SubD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7439
a61af66fc99e Initial load
duke
parents:
diff changeset
7440 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7441 format %{ "FSUBD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7442 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7443 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7444 ins_pipe(faddD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7445 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7446
a61af66fc99e Initial load
duke
parents:
diff changeset
7447 // Mul float single precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7448 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7449 match(Set dst (MulF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7450
a61af66fc99e Initial load
duke
parents:
diff changeset
7451 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7452 format %{ "FMULS $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7453 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7454 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7455 ins_pipe(fmulF_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7456 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7457
a61af66fc99e Initial load
duke
parents:
diff changeset
7458 // Mul float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7459 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7460 match(Set dst (MulD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7461
a61af66fc99e Initial load
duke
parents:
diff changeset
7462 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7463 format %{ "FMULD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7464 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7465 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7466 ins_pipe(fmulD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7467 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7468
a61af66fc99e Initial load
duke
parents:
diff changeset
7469 // Div float single precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7470 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7471 match(Set dst (DivF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7472
a61af66fc99e Initial load
duke
parents:
diff changeset
7473 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7474 format %{ "FDIVS $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7475 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7476 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7477 ins_pipe(fdivF_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7478 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7479
a61af66fc99e Initial load
duke
parents:
diff changeset
7480 // Div float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7481 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7482 match(Set dst (DivD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7483
a61af66fc99e Initial load
duke
parents:
diff changeset
7484 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7485 format %{ "FDIVD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7486 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7487 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7488 ins_pipe(fdivD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7489 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7490
a61af66fc99e Initial load
duke
parents:
diff changeset
7491 // Absolute float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7492 instruct absD_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7493 match(Set dst (AbsD src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7494
a61af66fc99e Initial load
duke
parents:
diff changeset
7495 format %{ "FABSd $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7496 ins_encode(fabsd(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7497 ins_pipe(faddD_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7498 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7499
a61af66fc99e Initial load
duke
parents:
diff changeset
7500 // Absolute float single precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7501 instruct absF_reg(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7502 match(Set dst (AbsF src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7503
a61af66fc99e Initial load
duke
parents:
diff changeset
7504 format %{ "FABSs $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7505 ins_encode(fabss(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7506 ins_pipe(faddF_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7507 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7508
a61af66fc99e Initial load
duke
parents:
diff changeset
7509 instruct negF_reg(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7510 match(Set dst (NegF src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7511
a61af66fc99e Initial load
duke
parents:
diff changeset
7512 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7513 format %{ "FNEGs $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7514 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7515 ins_encode(form3_opf_rs2F_rdF(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7516 ins_pipe(faddF_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7517 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7518
a61af66fc99e Initial load
duke
parents:
diff changeset
7519 instruct negD_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7520 match(Set dst (NegD src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7521
a61af66fc99e Initial load
duke
parents:
diff changeset
7522 format %{ "FNEGd $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7523 ins_encode(fnegd(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7524 ins_pipe(faddD_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7525 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7526
a61af66fc99e Initial load
duke
parents:
diff changeset
7527 // Sqrt float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7528 instruct sqrtF_reg_reg(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7529 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7530
a61af66fc99e Initial load
duke
parents:
diff changeset
7531 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7532 format %{ "FSQRTS $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7533 ins_encode(fsqrts(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7534 ins_pipe(fdivF_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7535 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7536
a61af66fc99e Initial load
duke
parents:
diff changeset
7537 // Sqrt float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
7538 instruct sqrtD_reg_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7539 match(Set dst (SqrtD src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7540
a61af66fc99e Initial load
duke
parents:
diff changeset
7541 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7542 format %{ "FSQRTD $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7543 ins_encode(fsqrtd(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7544 ins_pipe(fdivD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7545 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7546
a61af66fc99e Initial load
duke
parents:
diff changeset
7547 //----------Logical Instructions-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7548 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7549 // Register And
a61af66fc99e Initial load
duke
parents:
diff changeset
7550 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7551 match(Set dst (AndI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7552
a61af66fc99e Initial load
duke
parents:
diff changeset
7553 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7554 format %{ "AND $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7555 opcode(Assembler::and_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7556 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7557 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7558 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7559
a61af66fc99e Initial load
duke
parents:
diff changeset
7560 // Immediate And
a61af66fc99e Initial load
duke
parents:
diff changeset
7561 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7562 match(Set dst (AndI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7563
a61af66fc99e Initial load
duke
parents:
diff changeset
7564 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7565 format %{ "AND $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7566 opcode(Assembler::and_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7567 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7568 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7569 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7570
a61af66fc99e Initial load
duke
parents:
diff changeset
7571 // Register And Long
a61af66fc99e Initial load
duke
parents:
diff changeset
7572 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7573 match(Set dst (AndL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7574
a61af66fc99e Initial load
duke
parents:
diff changeset
7575 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7576 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7577 format %{ "AND $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7578 opcode(Assembler::and_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7579 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7580 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7581 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7582
a61af66fc99e Initial load
duke
parents:
diff changeset
7583 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7584 match(Set dst (AndL src1 con));
a61af66fc99e Initial load
duke
parents:
diff changeset
7585
a61af66fc99e Initial load
duke
parents:
diff changeset
7586 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7587 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7588 format %{ "AND $src1,$con,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7589 opcode(Assembler::and_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7590 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7591 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7592 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7593
a61af66fc99e Initial load
duke
parents:
diff changeset
7594 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7595 // Register Or
a61af66fc99e Initial load
duke
parents:
diff changeset
7596 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7597 match(Set dst (OrI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7598
a61af66fc99e Initial load
duke
parents:
diff changeset
7599 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7600 format %{ "OR $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7601 opcode(Assembler::or_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7602 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7603 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7604 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7605
a61af66fc99e Initial load
duke
parents:
diff changeset
7606 // Immediate Or
a61af66fc99e Initial load
duke
parents:
diff changeset
7607 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7608 match(Set dst (OrI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7609
a61af66fc99e Initial load
duke
parents:
diff changeset
7610 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7611 format %{ "OR $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7612 opcode(Assembler::or_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7613 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7614 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7615 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7616
a61af66fc99e Initial load
duke
parents:
diff changeset
7617 // Register Or Long
a61af66fc99e Initial load
duke
parents:
diff changeset
7618 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7619 match(Set dst (OrL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7620
a61af66fc99e Initial load
duke
parents:
diff changeset
7621 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7622 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7623 format %{ "OR $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7624 opcode(Assembler::or_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7625 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7626 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7627 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7628
a61af66fc99e Initial load
duke
parents:
diff changeset
7629 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7630 match(Set dst (OrL src1 con));
a61af66fc99e Initial load
duke
parents:
diff changeset
7631 ins_cost(DEFAULT_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7632
a61af66fc99e Initial load
duke
parents:
diff changeset
7633 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7634 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7635 format %{ "OR $src1,$con,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7636 opcode(Assembler::or_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7637 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7638 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7639 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7640
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7641 #ifndef _LP64
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7642
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7643 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7644 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7645 match(Set dst (OrI src1 (CastP2X src2)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7646
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7647 size(4);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7648 format %{ "OR $src1,$src2,$dst" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7649 opcode(Assembler::or_op3, Assembler::arith_op);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7650 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7651 ins_pipe(ialu_reg_reg);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7652 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7653
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7654 #else
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7655
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7656 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7657 match(Set dst (OrL src1 (CastP2X src2)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7658
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7659 ins_cost(DEFAULT_COST);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7660 size(4);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7661 format %{ "OR $src1,$src2,$dst\t! long" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7662 opcode(Assembler::or_op3, Assembler::arith_op);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7663 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7664 ins_pipe(ialu_reg_reg);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7665 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7666
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7667 #endif
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7668
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7669 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7670 // Register Xor
a61af66fc99e Initial load
duke
parents:
diff changeset
7671 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7672 match(Set dst (XorI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7673
a61af66fc99e Initial load
duke
parents:
diff changeset
7674 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7675 format %{ "XOR $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7676 opcode(Assembler::xor_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7677 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7678 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7679 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7680
a61af66fc99e Initial load
duke
parents:
diff changeset
7681 // Immediate Xor
a61af66fc99e Initial load
duke
parents:
diff changeset
7682 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7683 match(Set dst (XorI src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7684
a61af66fc99e Initial load
duke
parents:
diff changeset
7685 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7686 format %{ "XOR $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7687 opcode(Assembler::xor_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7688 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7689 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7690 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7691
a61af66fc99e Initial load
duke
parents:
diff changeset
7692 // Register Xor Long
a61af66fc99e Initial load
duke
parents:
diff changeset
7693 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7694 match(Set dst (XorL src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7695
a61af66fc99e Initial load
duke
parents:
diff changeset
7696 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7697 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7698 format %{ "XOR $src1,$src2,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7699 opcode(Assembler::xor_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7700 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7701 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7702 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7703
a61af66fc99e Initial load
duke
parents:
diff changeset
7704 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7705 match(Set dst (XorL src1 con));
a61af66fc99e Initial load
duke
parents:
diff changeset
7706
a61af66fc99e Initial load
duke
parents:
diff changeset
7707 ins_cost(DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7708 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7709 format %{ "XOR $src1,$con,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7710 opcode(Assembler::xor_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7711 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7712 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7713 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7714
a61af66fc99e Initial load
duke
parents:
diff changeset
7715 //----------Convert to Boolean-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7716 // Nice hack for 32-bit tests but doesn't work for
a61af66fc99e Initial load
duke
parents:
diff changeset
7717 // 64-bit pointers.
a61af66fc99e Initial load
duke
parents:
diff changeset
7718 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7719 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7720 effect( KILL ccr );
a61af66fc99e Initial load
duke
parents:
diff changeset
7721 ins_cost(DEFAULT_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7722 format %{ "CMP R_G0,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7723 "ADDX R_G0,0,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7724 ins_encode( enc_to_bool( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7725 ins_pipe(ialu_reg_ialu);
a61af66fc99e Initial load
duke
parents:
diff changeset
7726 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7727
a61af66fc99e Initial load
duke
parents:
diff changeset
7728 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
7729 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7730 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7731 effect( KILL ccr );
a61af66fc99e Initial load
duke
parents:
diff changeset
7732 ins_cost(DEFAULT_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7733 format %{ "CMP R_G0,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7734 "ADDX R_G0,0,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7735 ins_encode( enc_to_bool( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7736 ins_pipe(ialu_reg_ialu);
a61af66fc99e Initial load
duke
parents:
diff changeset
7737 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7738 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
7739 instruct convP2B( iRegI dst, iRegP src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7740 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7741 ins_cost(DEFAULT_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
7742 format %{ "MOV $src,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7743 "MOVRNZ $src,1,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7744 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7745 ins_pipe(ialu_clr_and_mover);
a61af66fc99e Initial load
duke
parents:
diff changeset
7746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7747 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
7748
a61af66fc99e Initial load
duke
parents:
diff changeset
7749 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7750 match(Set dst (CmpLTMask p q));
a61af66fc99e Initial load
duke
parents:
diff changeset
7751 effect( KILL ccr );
a61af66fc99e Initial load
duke
parents:
diff changeset
7752 ins_cost(DEFAULT_COST*4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7753 format %{ "CMP $p,$q\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7754 "MOV #0,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7755 "BLT,a .+8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7756 "MOV #-1,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7757 ins_encode( enc_ltmask(p,q,dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7758 ins_pipe(ialu_reg_reg_ialu);
a61af66fc99e Initial load
duke
parents:
diff changeset
7759 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7760
a61af66fc99e Initial load
duke
parents:
diff changeset
7761 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7762 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7763 effect(KILL ccr, TEMP tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7764 ins_cost(DEFAULT_COST*3);
a61af66fc99e Initial load
duke
parents:
diff changeset
7765
a61af66fc99e Initial load
duke
parents:
diff changeset
7766 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7767 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7768 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7769 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7770 ins_pipe( cadd_cmpltmask );
a61af66fc99e Initial load
duke
parents:
diff changeset
7771 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7772
a61af66fc99e Initial load
duke
parents:
diff changeset
7773 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7774 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7775 effect( KILL ccr, TEMP tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7776 ins_cost(DEFAULT_COST*3);
a61af66fc99e Initial load
duke
parents:
diff changeset
7777
a61af66fc99e Initial load
duke
parents:
diff changeset
7778 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7779 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7780 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7781 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7782 ins_pipe( cadd_cmpltmask );
a61af66fc99e Initial load
duke
parents:
diff changeset
7783 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7784
a61af66fc99e Initial load
duke
parents:
diff changeset
7785 //----------Arithmetic Conversion Instructions---------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7786 // The conversions operations are all Alpha sorted. Please keep it that way!
a61af66fc99e Initial load
duke
parents:
diff changeset
7787
a61af66fc99e Initial load
duke
parents:
diff changeset
7788 instruct convD2F_reg(regF dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7789 match(Set dst (ConvD2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7790 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7791 format %{ "FDTOS $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7792 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7793 ins_encode(form3_opf_rs2D_rdF(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7794 ins_pipe(fcvtD2F);
a61af66fc99e Initial load
duke
parents:
diff changeset
7795 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7796
a61af66fc99e Initial load
duke
parents:
diff changeset
7797
a61af66fc99e Initial load
duke
parents:
diff changeset
7798 // Convert a double to an int in a float register.
a61af66fc99e Initial load
duke
parents:
diff changeset
7799 // If the double is a NAN, stuff a zero in instead.
a61af66fc99e Initial load
duke
parents:
diff changeset
7800 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7801 effect(DEF dst, USE src, KILL fcc0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7802 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7803 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7804 "FDTOI $src,$dst\t! convert in delay slot\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7805 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7806 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7807 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7808 ins_encode(form_d2i_helper(src,dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7809 ins_pipe(fcvtD2I);
a61af66fc99e Initial load
duke
parents:
diff changeset
7810 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7811
a61af66fc99e Initial load
duke
parents:
diff changeset
7812 instruct convD2I_reg(stackSlotI dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7813 match(Set dst (ConvD2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7814 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7815 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7816 regF tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
7817 convD2I_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7818 regF_to_stkI(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7819 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7820 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7821
a61af66fc99e Initial load
duke
parents:
diff changeset
7822 // Convert a double to a long in a double register.
a61af66fc99e Initial load
duke
parents:
diff changeset
7823 // If the double is a NAN, stuff a zero in instead.
a61af66fc99e Initial load
duke
parents:
diff changeset
7824 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7825 effect(DEF dst, USE src, KILL fcc0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7826 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7827 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7828 "FDTOX $src,$dst\t! convert in delay slot\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7829 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7830 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7831 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7832 ins_encode(form_d2l_helper(src,dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7833 ins_pipe(fcvtD2L);
a61af66fc99e Initial load
duke
parents:
diff changeset
7834 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7835
a61af66fc99e Initial load
duke
parents:
diff changeset
7836
a61af66fc99e Initial load
duke
parents:
diff changeset
7837 // Double to Long conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
7838 instruct convD2L_reg(stackSlotL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7839 match(Set dst (ConvD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7840 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7841 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7842 regD tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
7843 convD2L_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7844 regD_to_stkL(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7845 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7846 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7847
a61af66fc99e Initial load
duke
parents:
diff changeset
7848
a61af66fc99e Initial load
duke
parents:
diff changeset
7849 instruct convF2D_reg(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7850 match(Set dst (ConvF2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7851 format %{ "FSTOD $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7852 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7853 ins_encode(form3_opf_rs2F_rdD(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7854 ins_pipe(fcvtF2D);
a61af66fc99e Initial load
duke
parents:
diff changeset
7855 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7856
a61af66fc99e Initial load
duke
parents:
diff changeset
7857
a61af66fc99e Initial load
duke
parents:
diff changeset
7858 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7859 effect(DEF dst, USE src, KILL fcc0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7860 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7861 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7862 "FSTOI $src,$dst\t! convert in delay slot\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7863 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7864 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7865 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7866 ins_encode(form_f2i_helper(src,dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7867 ins_pipe(fcvtF2I);
a61af66fc99e Initial load
duke
parents:
diff changeset
7868 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7869
a61af66fc99e Initial load
duke
parents:
diff changeset
7870 instruct convF2I_reg(stackSlotI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7871 match(Set dst (ConvF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7872 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7873 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7874 regF tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
7875 convF2I_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7876 regF_to_stkI(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7877 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7878 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7879
a61af66fc99e Initial load
duke
parents:
diff changeset
7880
a61af66fc99e Initial load
duke
parents:
diff changeset
7881 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7882 effect(DEF dst, USE src, KILL fcc0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7883 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7884 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7885 "FSTOX $src,$dst\t! convert in delay slot\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7886 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7887 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7888 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7889 ins_encode(form_f2l_helper(src,dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7890 ins_pipe(fcvtF2L);
a61af66fc99e Initial load
duke
parents:
diff changeset
7891 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7892
a61af66fc99e Initial load
duke
parents:
diff changeset
7893 // Float to Long conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
7894 instruct convF2L_reg(stackSlotL dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7895 match(Set dst (ConvF2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7896 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7897 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7898 regD tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
7899 convF2L_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7900 regD_to_stkL(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7901 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7902 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7903
a61af66fc99e Initial load
duke
parents:
diff changeset
7904
a61af66fc99e Initial load
duke
parents:
diff changeset
7905 instruct convI2D_helper(regD dst, regF tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7906 effect(USE tmp, DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
7907 format %{ "FITOD $tmp,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7908 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7909 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7910 ins_pipe(fcvtI2D);
a61af66fc99e Initial load
duke
parents:
diff changeset
7911 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7912
a61af66fc99e Initial load
duke
parents:
diff changeset
7913 instruct convI2D_reg(stackSlotI src, regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7914 match(Set dst (ConvI2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7915 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7916 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7917 regF tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
7918 stkI_to_regF( tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7919 convI2D_helper( dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7920 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7921 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7922
a61af66fc99e Initial load
duke
parents:
diff changeset
7923 instruct convI2D_mem( regD_low dst, memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7924 match(Set dst (ConvI2D (LoadI mem)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7925 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7926 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
7927 format %{ "LDF $mem,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7928 "FITOD $dst,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7929 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
7930 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7931 ins_pipe(floadF_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7932 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7933
a61af66fc99e Initial load
duke
parents:
diff changeset
7934
a61af66fc99e Initial load
duke
parents:
diff changeset
7935 instruct convI2F_helper(regF dst, regF tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7936 effect(DEF dst, USE tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7937 format %{ "FITOS $tmp,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7938 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
7939 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7940 ins_pipe(fcvtI2F);
a61af66fc99e Initial load
duke
parents:
diff changeset
7941 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7942
a61af66fc99e Initial load
duke
parents:
diff changeset
7943 instruct convI2F_reg( regF dst, stackSlotI src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7944 match(Set dst (ConvI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7945 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7946 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7947 regF tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
7948 stkI_to_regF(tmp,src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7949 convI2F_helper(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7950 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7951 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7952
a61af66fc99e Initial load
duke
parents:
diff changeset
7953 instruct convI2F_mem( regF dst, memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7954 match(Set dst (ConvI2F (LoadI mem)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7955 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7956 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
7957 format %{ "LDF $mem,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7958 "FITOS $dst,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7959 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
7960 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7961 ins_pipe(floadF_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7962 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7963
a61af66fc99e Initial load
duke
parents:
diff changeset
7964
a61af66fc99e Initial load
duke
parents:
diff changeset
7965 instruct convI2L_reg(iRegL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7966 match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7967 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7968 format %{ "SRA $src,0,$dst\t! int->long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7969 opcode(Assembler::sra_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7970 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7971 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7972 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7973
a61af66fc99e Initial load
duke
parents:
diff changeset
7974 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
7975 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7976 match(Set dst (AndL (ConvI2L src) mask) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7977 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7978 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7979 opcode(Assembler::srl_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7980 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7981 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7982 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7983
a61af66fc99e Initial load
duke
parents:
diff changeset
7984 // Zero-extend long
a61af66fc99e Initial load
duke
parents:
diff changeset
7985 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7986 match(Set dst (AndL src mask) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7987 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
7988 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7989 opcode(Assembler::srl_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
7990 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7991 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7992 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7993
a61af66fc99e Initial load
duke
parents:
diff changeset
7994 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7995 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7996 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7997 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
7998
a61af66fc99e Initial load
duke
parents:
diff changeset
7999 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8000 format %{ "LDUW $src,$dst\t! MoveF2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8001 opcode(Assembler::lduw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8002 ins_encode(simple_form3_mem_reg( src, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8003 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8004 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8005
a61af66fc99e Initial load
duke
parents:
diff changeset
8006 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8007 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8008 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8009 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8010
a61af66fc99e Initial load
duke
parents:
diff changeset
8011 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8012 format %{ "LDF $src,$dst\t! MoveI2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8013 opcode(Assembler::ldf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8014 ins_encode(simple_form3_mem_reg(src, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8015 ins_pipe(floadF_stk);
a61af66fc99e Initial load
duke
parents:
diff changeset
8016 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8017
a61af66fc99e Initial load
duke
parents:
diff changeset
8018 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8019 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8020 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8021 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8022
a61af66fc99e Initial load
duke
parents:
diff changeset
8023 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8024 format %{ "LDX $src,$dst\t! MoveD2L" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8025 opcode(Assembler::ldx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8026 ins_encode(simple_form3_mem_reg( src, dst ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8027 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8028 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8029
a61af66fc99e Initial load
duke
parents:
diff changeset
8030 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8031 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8032 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8033 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8034
a61af66fc99e Initial load
duke
parents:
diff changeset
8035 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8036 format %{ "LDDF $src,$dst\t! MoveL2D" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8037 opcode(Assembler::lddf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8038 ins_encode(simple_form3_mem_reg(src, dst));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8039 ins_pipe(floadD_stk);
a61af66fc99e Initial load
duke
parents:
diff changeset
8040 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8041
a61af66fc99e Initial load
duke
parents:
diff changeset
8042 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8043 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8044 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8045 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8046
a61af66fc99e Initial load
duke
parents:
diff changeset
8047 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8048 format %{ "STF $src,$dst\t!MoveF2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8049 opcode(Assembler::stf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8050 ins_encode(simple_form3_mem_reg(dst, src));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8051 ins_pipe(fstoreF_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8052 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8053
a61af66fc99e Initial load
duke
parents:
diff changeset
8054 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8055 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8056 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8057 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8058
a61af66fc99e Initial load
duke
parents:
diff changeset
8059 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8060 format %{ "STW $src,$dst\t!MoveI2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8061 opcode(Assembler::stw_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8062 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8063 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8064 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8065
a61af66fc99e Initial load
duke
parents:
diff changeset
8066 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8067 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8068 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8069 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8070
a61af66fc99e Initial load
duke
parents:
diff changeset
8071 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8072 format %{ "STDF $src,$dst\t!MoveD2L" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8073 opcode(Assembler::stdf_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8074 ins_encode(simple_form3_mem_reg(dst, src));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8075 ins_pipe(fstoreD_stk_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8076 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8077
a61af66fc99e Initial load
duke
parents:
diff changeset
8078 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8079 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8080 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8081 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8082
a61af66fc99e Initial load
duke
parents:
diff changeset
8083 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8084 format %{ "STX $src,$dst\t!MoveL2D" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8085 opcode(Assembler::stx_op3);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 235
diff changeset
8086 ins_encode(simple_form3_mem_reg( dst, src ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8087 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8088 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8089
a61af66fc99e Initial load
duke
parents:
diff changeset
8090
a61af66fc99e Initial load
duke
parents:
diff changeset
8091 //-----------
a61af66fc99e Initial load
duke
parents:
diff changeset
8092 // Long to Double conversion using V8 opcodes.
a61af66fc99e Initial load
duke
parents:
diff changeset
8093 // Still useful because cheetah traps and becomes
a61af66fc99e Initial load
duke
parents:
diff changeset
8094 // amazingly slow for some common numbers.
a61af66fc99e Initial load
duke
parents:
diff changeset
8095
a61af66fc99e Initial load
duke
parents:
diff changeset
8096 // Magic constant, 0x43300000
a61af66fc99e Initial load
duke
parents:
diff changeset
8097 instruct loadConI_x43300000(iRegI dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8098 effect(DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
8099 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8100 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8101 ins_encode(SetHi22(0x43300000, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8102 ins_pipe(ialu_none);
a61af66fc99e Initial load
duke
parents:
diff changeset
8103 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8104
a61af66fc99e Initial load
duke
parents:
diff changeset
8105 // Magic constant, 0x41f00000
a61af66fc99e Initial load
duke
parents:
diff changeset
8106 instruct loadConI_x41f00000(iRegI dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8107 effect(DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
8108 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8109 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8110 ins_encode(SetHi22(0x41f00000, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8111 ins_pipe(ialu_none);
a61af66fc99e Initial load
duke
parents:
diff changeset
8112 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8113
a61af66fc99e Initial load
duke
parents:
diff changeset
8114 // Construct a double from two float halves
a61af66fc99e Initial load
duke
parents:
diff changeset
8115 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8116 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8117 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8118 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8119 "FMOVS $src2.lo,$dst.lo" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8120 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8121 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8122 ins_pipe(faddD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8123 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8124
a61af66fc99e Initial load
duke
parents:
diff changeset
8125 // Convert integer in high half of a double register (in the lower half of
a61af66fc99e Initial load
duke
parents:
diff changeset
8126 // the double register file) to double
a61af66fc99e Initial load
duke
parents:
diff changeset
8127 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8128 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8129 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8130 format %{ "FITOD $src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8131 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8132 ins_encode(form3_opf_rs2D_rdD(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8133 ins_pipe(fcvtLHi2D);
a61af66fc99e Initial load
duke
parents:
diff changeset
8134 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8135
a61af66fc99e Initial load
duke
parents:
diff changeset
8136 // Add float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
8137 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8138 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8139 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8140 format %{ "FADDD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8141 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8142 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8143 ins_pipe(faddD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8144 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8145
a61af66fc99e Initial load
duke
parents:
diff changeset
8146 // Sub float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
8147 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8148 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8149 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8150 format %{ "FSUBD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8151 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8152 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8153 ins_pipe(faddD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8154 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8155
a61af66fc99e Initial load
duke
parents:
diff changeset
8156 // Mul float double precision
a61af66fc99e Initial load
duke
parents:
diff changeset
8157 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8158 effect(DEF dst, USE src1, USE src2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8159 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8160 format %{ "FMULD $src1,$src2,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8161 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8162 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8163 ins_pipe(fmulD_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8164 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8165
a61af66fc99e Initial load
duke
parents:
diff changeset
8166 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8167 match(Set dst (ConvL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8168 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
a61af66fc99e Initial load
duke
parents:
diff changeset
8169
a61af66fc99e Initial load
duke
parents:
diff changeset
8170 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8171 regD_low tmpsrc;
a61af66fc99e Initial load
duke
parents:
diff changeset
8172 iRegI ix43300000;
a61af66fc99e Initial load
duke
parents:
diff changeset
8173 iRegI ix41f00000;
a61af66fc99e Initial load
duke
parents:
diff changeset
8174 stackSlotL lx43300000;
a61af66fc99e Initial load
duke
parents:
diff changeset
8175 stackSlotL lx41f00000;
a61af66fc99e Initial load
duke
parents:
diff changeset
8176 regD_low dx43300000;
a61af66fc99e Initial load
duke
parents:
diff changeset
8177 regD dx41f00000;
a61af66fc99e Initial load
duke
parents:
diff changeset
8178 regD tmp1;
a61af66fc99e Initial load
duke
parents:
diff changeset
8179 regD_low tmp2;
a61af66fc99e Initial load
duke
parents:
diff changeset
8180 regD tmp3;
a61af66fc99e Initial load
duke
parents:
diff changeset
8181 regD tmp4;
a61af66fc99e Initial load
duke
parents:
diff changeset
8182
a61af66fc99e Initial load
duke
parents:
diff changeset
8183 stkL_to_regD(tmpsrc, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8184
a61af66fc99e Initial load
duke
parents:
diff changeset
8185 loadConI_x43300000(ix43300000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8186 loadConI_x41f00000(ix41f00000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8187 regI_to_stkLHi(lx43300000, ix43300000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8188 regI_to_stkLHi(lx41f00000, ix41f00000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8189 stkL_to_regD(dx43300000, lx43300000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8190 stkL_to_regD(dx41f00000, lx41f00000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8191
a61af66fc99e Initial load
duke
parents:
diff changeset
8192 convI2D_regDHi_regD(tmp1, tmpsrc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8193 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8194 subD_regD_regD(tmp3, tmp2, dx43300000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8195 mulD_regD_regD(tmp4, tmp1, dx41f00000);
a61af66fc99e Initial load
duke
parents:
diff changeset
8196 addD_regD_regD(dst, tmp3, tmp4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8197 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8198 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8199
a61af66fc99e Initial load
duke
parents:
diff changeset
8200 // Long to Double conversion using fast fxtof
a61af66fc99e Initial load
duke
parents:
diff changeset
8201 instruct convL2D_helper(regD dst, regD tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8202 effect(DEF dst, USE tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8203 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8204 format %{ "FXTOD $tmp,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8205 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8206 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8207 ins_pipe(fcvtL2D);
a61af66fc99e Initial load
duke
parents:
diff changeset
8208 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8209
a61af66fc99e Initial load
duke
parents:
diff changeset
8210 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8211 predicate(VM_Version::has_fast_fxtof());
a61af66fc99e Initial load
duke
parents:
diff changeset
8212 match(Set dst (ConvL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8213 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8214 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8215 regD tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
8216 stkL_to_regD(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8217 convL2D_helper(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8218 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8219 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8220
a61af66fc99e Initial load
duke
parents:
diff changeset
8221 //-----------
a61af66fc99e Initial load
duke
parents:
diff changeset
8222 // Long to Float conversion using V8 opcodes.
a61af66fc99e Initial load
duke
parents:
diff changeset
8223 // Still useful because cheetah traps and becomes
a61af66fc99e Initial load
duke
parents:
diff changeset
8224 // amazingly slow for some common numbers.
a61af66fc99e Initial load
duke
parents:
diff changeset
8225
a61af66fc99e Initial load
duke
parents:
diff changeset
8226 // Long to Float conversion using fast fxtof
a61af66fc99e Initial load
duke
parents:
diff changeset
8227 instruct convL2F_helper(regF dst, regD tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8228 effect(DEF dst, USE tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8229 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8230 format %{ "FXTOS $tmp,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8231 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8232 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8233 ins_pipe(fcvtL2F);
a61af66fc99e Initial load
duke
parents:
diff changeset
8234 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8235
a61af66fc99e Initial load
duke
parents:
diff changeset
8236 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8237 match(Set dst (ConvL2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8238 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8239 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8240 regD tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
8241 stkL_to_regD(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8242 convL2F_helper(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8243 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8244 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8245 //-----------
a61af66fc99e Initial load
duke
parents:
diff changeset
8246
a61af66fc99e Initial load
duke
parents:
diff changeset
8247 instruct convL2I_reg(iRegI dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8248 match(Set dst (ConvL2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8249 #ifndef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
8250 format %{ "MOV $src.lo,$dst\t! long->int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8251 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8252 ins_pipe(ialu_move_reg_I_to_L);
a61af66fc99e Initial load
duke
parents:
diff changeset
8253 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
8254 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8255 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8256 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8257 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8258 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
8259 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8260
a61af66fc99e Initial load
duke
parents:
diff changeset
8261 // Register Shift Right Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8262 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8263 match(Set dst (ConvL2I (RShiftL src cnt)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8264
a61af66fc99e Initial load
duke
parents:
diff changeset
8265 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8266 format %{ "SRAX $src,$cnt,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8267 opcode(Assembler::srax_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8268 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8269 ins_pipe(ialu_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8270 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8271
a61af66fc99e Initial load
duke
parents:
diff changeset
8272 // Replicate scalar to packed byte values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8273 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8274 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8275 format %{ "SLLX $src,56,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8276 "SRLX $dst, 8,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8277 "OR $dst,O7,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8278 "SRLX $dst,16,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8279 "OR $dst,O7,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8280 "SRLX $dst,32,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8281 "OR $dst,O7,$dst\t! replicate8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8282 ins_encode( enc_repl8b(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8283 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8284 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8285
a61af66fc99e Initial load
duke
parents:
diff changeset
8286 // Replicate scalar to packed byte values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8287 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8288 match(Set dst (Replicate8B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8289 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8290 iRegL tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
8291 Repl8B_reg_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8292 regL_to_stkD(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8293 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8294 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8295
a61af66fc99e Initial load
duke
parents:
diff changeset
8296 // Replicate scalar constant to packed byte values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8297 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8298 match(Set dst (Replicate8B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8299 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
8300 size(36);
a61af66fc99e Initial load
duke
parents:
diff changeset
8301 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
8302 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8303 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
8304 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8305 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8306 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8307 ins_pipe(loadConFD);
a61af66fc99e Initial load
duke
parents:
diff changeset
8308 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8309
a61af66fc99e Initial load
duke
parents:
diff changeset
8310 // Replicate scalar to packed char values into stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
8311 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8312 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8313 format %{ "SLLX $src,48,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8314 "SRLX $dst,16,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8315 "OR $dst,O7,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8316 "SRLX $dst,32,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8317 "OR $dst,O7,$dst\t! replicate4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8318 ins_encode( enc_repl4s(src, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8319 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8320 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8321
a61af66fc99e Initial load
duke
parents:
diff changeset
8322 // Replicate scalar to packed char values into stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
8323 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8324 match(Set dst (Replicate4C src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8325 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8326 iRegL tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
8327 Repl4C_reg_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8328 regL_to_stkD(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8329 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8330 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8331
a61af66fc99e Initial load
duke
parents:
diff changeset
8332 // Replicate scalar constant to packed char values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8333 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8334 match(Set dst (Replicate4C src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8335 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
8336 size(36);
a61af66fc99e Initial load
duke
parents:
diff changeset
8337 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
8338 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8339 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
8340 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8341 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8342 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8343 ins_pipe(loadConFD);
a61af66fc99e Initial load
duke
parents:
diff changeset
8344 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8345
a61af66fc99e Initial load
duke
parents:
diff changeset
8346 // Replicate scalar to packed short values into stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
8347 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8348 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8349 format %{ "SLLX $src,48,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8350 "SRLX $dst,16,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8351 "OR $dst,O7,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8352 "SRLX $dst,32,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8353 "OR $dst,O7,$dst\t! replicate4S" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8354 ins_encode( enc_repl4s(src, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8355 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8356 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8357
a61af66fc99e Initial load
duke
parents:
diff changeset
8358 // Replicate scalar to packed short values into stack slot
a61af66fc99e Initial load
duke
parents:
diff changeset
8359 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8360 match(Set dst (Replicate4S src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8361 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8362 iRegL tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
8363 Repl4S_reg_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8364 regL_to_stkD(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8365 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8366 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8367
a61af66fc99e Initial load
duke
parents:
diff changeset
8368 // Replicate scalar constant to packed short values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8369 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8370 match(Set dst (Replicate4S src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8371 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
8372 size(36);
a61af66fc99e Initial load
duke
parents:
diff changeset
8373 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
8374 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8375 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
8376 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8377 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8378 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8379 ins_pipe(loadConFD);
a61af66fc99e Initial load
duke
parents:
diff changeset
8380 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8381
a61af66fc99e Initial load
duke
parents:
diff changeset
8382 // Replicate scalar to packed int values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8383 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8384 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8385 format %{ "SLLX $src,32,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8386 "SRLX $dst,32,O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8387 "OR $dst,O7,$dst\t! replicate2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8388 ins_encode( enc_repl2i(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8389 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8390 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8391
a61af66fc99e Initial load
duke
parents:
diff changeset
8392 // Replicate scalar to packed int values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8393 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8394 match(Set dst (Replicate2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8395 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8396 iRegL tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
8397 Repl2I_reg_helper(tmp, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
8398 regL_to_stkD(dst, tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
8399 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8400 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8401
a61af66fc99e Initial load
duke
parents:
diff changeset
8402 // Replicate scalar zero constant to packed int values in Double register
a61af66fc99e Initial load
duke
parents:
diff changeset
8403 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8404 match(Set dst (Replicate2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8405 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
8406 size(36);
a61af66fc99e Initial load
duke
parents:
diff changeset
8407 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
8408 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8409 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
8410 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8411 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8412 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8413 ins_pipe(loadConFD);
a61af66fc99e Initial load
duke
parents:
diff changeset
8414 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8415
a61af66fc99e Initial load
duke
parents:
diff changeset
8416 //----------Control Flow Instructions------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8417 // Compare Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8418 // Compare Integers
a61af66fc99e Initial load
duke
parents:
diff changeset
8419 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8420 match(Set icc (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8421 effect( DEF icc, USE op1, USE op2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
8422
a61af66fc99e Initial load
duke
parents:
diff changeset
8423 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8424 format %{ "CMP $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8425 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8426 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8427 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8428 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8429
a61af66fc99e Initial load
duke
parents:
diff changeset
8430 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8431 match(Set icc (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8432
a61af66fc99e Initial load
duke
parents:
diff changeset
8433 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8434 format %{ "CMP $op1,$op2\t! unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8435 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8436 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8437 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8438 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8439
a61af66fc99e Initial load
duke
parents:
diff changeset
8440 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8441 match(Set icc (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8442 effect( DEF icc, USE op1 );
a61af66fc99e Initial load
duke
parents:
diff changeset
8443
a61af66fc99e Initial load
duke
parents:
diff changeset
8444 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8445 format %{ "CMP $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8446 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8447 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8448 ins_pipe(ialu_cconly_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8449 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8450
a61af66fc99e Initial load
duke
parents:
diff changeset
8451 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8452 match(Set icc (CmpI (AndI op1 op2) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
8453
a61af66fc99e Initial load
duke
parents:
diff changeset
8454 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8455 format %{ "BTST $op2,$op1" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8456 opcode(Assembler::andcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8457 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8458 ins_pipe(ialu_cconly_reg_reg_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
8459 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8460
a61af66fc99e Initial load
duke
parents:
diff changeset
8461 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8462 match(Set icc (CmpI (AndI op1 op2) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
8463
a61af66fc99e Initial load
duke
parents:
diff changeset
8464 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8465 format %{ "BTST $op2,$op1" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8466 opcode(Assembler::andcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8467 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8468 ins_pipe(ialu_cconly_reg_imm_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
8469 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8470
a61af66fc99e Initial load
duke
parents:
diff changeset
8471 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8472 match(Set xcc (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8473 effect( DEF xcc, USE op1, USE op2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
8474
a61af66fc99e Initial load
duke
parents:
diff changeset
8475 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8476 format %{ "CMP $op1,$op2\t\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8477 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8478 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8479 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8480 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8481
a61af66fc99e Initial load
duke
parents:
diff changeset
8482 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8483 match(Set xcc (CmpL op1 con));
a61af66fc99e Initial load
duke
parents:
diff changeset
8484 effect( DEF xcc, USE op1, USE con );
a61af66fc99e Initial load
duke
parents:
diff changeset
8485
a61af66fc99e Initial load
duke
parents:
diff changeset
8486 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8487 format %{ "CMP $op1,$con\t\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8488 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8489 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8490 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8491 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8492
a61af66fc99e Initial load
duke
parents:
diff changeset
8493 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8494 match(Set xcc (CmpL (AndL op1 op2) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
8495 effect( DEF xcc, USE op1, USE op2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
8496
a61af66fc99e Initial load
duke
parents:
diff changeset
8497 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8498 format %{ "BTST $op1,$op2\t\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8499 opcode(Assembler::andcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8500 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8501 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8502 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8503
a61af66fc99e Initial load
duke
parents:
diff changeset
8504 // useful for checking the alignment of a pointer:
a61af66fc99e Initial load
duke
parents:
diff changeset
8505 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8506 match(Set xcc (CmpL (AndL op1 con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
8507 effect( DEF xcc, USE op1, USE con );
a61af66fc99e Initial load
duke
parents:
diff changeset
8508
a61af66fc99e Initial load
duke
parents:
diff changeset
8509 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8510 format %{ "BTST $op1,$con\t\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8511 opcode(Assembler::andcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8512 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8513 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8514 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8515
a61af66fc99e Initial load
duke
parents:
diff changeset
8516 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8517 match(Set icc (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8518
a61af66fc99e Initial load
duke
parents:
diff changeset
8519 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8520 format %{ "CMP $op1,$op2\t! unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8521 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8522 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8523 ins_pipe(ialu_cconly_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8524 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8525
a61af66fc99e Initial load
duke
parents:
diff changeset
8526 // Compare Pointers
a61af66fc99e Initial load
duke
parents:
diff changeset
8527 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8528 match(Set pcc (CmpP op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8529
a61af66fc99e Initial load
duke
parents:
diff changeset
8530 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8531 format %{ "CMP $op1,$op2\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8532 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8533 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8534 ins_pipe(ialu_cconly_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8535 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8536
a61af66fc99e Initial load
duke
parents:
diff changeset
8537 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8538 match(Set pcc (CmpP op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8539
a61af66fc99e Initial load
duke
parents:
diff changeset
8540 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8541 format %{ "CMP $op1,$op2\t! ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8542 opcode(Assembler::subcc_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
8543 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8544 ins_pipe(ialu_cconly_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8545 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8546
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8547 // Compare Narrow oops
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8548 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8549 match(Set icc (CmpN op1 op2));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8550
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8551 size(4);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8552 format %{ "CMP $op1,$op2\t! compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8553 opcode(Assembler::subcc_op3, Assembler::arith_op);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8554 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8555 ins_pipe(ialu_cconly_reg_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8556 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8557
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8558 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8559 match(Set icc (CmpN op1 op2));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8560
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8561 size(4);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8562 format %{ "CMP $op1,$op2\t! compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8563 opcode(Assembler::subcc_op3, Assembler::arith_op);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8564 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8565 ins_pipe(ialu_cconly_reg_imm);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8566 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8567
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8568 //----------Max and Min--------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8569 // Min Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8570 // Conditional move for min
a61af66fc99e Initial load
duke
parents:
diff changeset
8571 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8572 effect( USE_DEF op2, USE op1, USE icc );
a61af66fc99e Initial load
duke
parents:
diff changeset
8573
a61af66fc99e Initial load
duke
parents:
diff changeset
8574 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8575 format %{ "MOVlt icc,$op1,$op2\t! min" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8576 opcode(Assembler::less);
a61af66fc99e Initial load
duke
parents:
diff changeset
8577 ins_encode( enc_cmov_reg_minmax(op2,op1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8578 ins_pipe(ialu_reg_flags);
a61af66fc99e Initial load
duke
parents:
diff changeset
8579 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8580
a61af66fc99e Initial load
duke
parents:
diff changeset
8581 // Min Register with Register.
a61af66fc99e Initial load
duke
parents:
diff changeset
8582 instruct minI_eReg(iRegI op1, iRegI op2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8583 match(Set op2 (MinI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8584 ins_cost(DEFAULT_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8585 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8586 flagsReg icc;
a61af66fc99e Initial load
duke
parents:
diff changeset
8587 compI_iReg(icc,op1,op2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8588 cmovI_reg_lt(op2,op1,icc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8589 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8590 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8591
a61af66fc99e Initial load
duke
parents:
diff changeset
8592 // Max Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8593 // Conditional move for max
a61af66fc99e Initial load
duke
parents:
diff changeset
8594 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8595 effect( USE_DEF op2, USE op1, USE icc );
a61af66fc99e Initial load
duke
parents:
diff changeset
8596 format %{ "MOVgt icc,$op1,$op2\t! max" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8597 opcode(Assembler::greater);
a61af66fc99e Initial load
duke
parents:
diff changeset
8598 ins_encode( enc_cmov_reg_minmax(op2,op1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8599 ins_pipe(ialu_reg_flags);
a61af66fc99e Initial load
duke
parents:
diff changeset
8600 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8601
a61af66fc99e Initial load
duke
parents:
diff changeset
8602 // Max Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8603 instruct maxI_eReg(iRegI op1, iRegI op2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8604 match(Set op2 (MaxI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8605 ins_cost(DEFAULT_COST*2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8606 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8607 flagsReg icc;
a61af66fc99e Initial load
duke
parents:
diff changeset
8608 compI_iReg(icc,op1,op2);
a61af66fc99e Initial load
duke
parents:
diff changeset
8609 cmovI_reg_gt(op2,op1,icc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8610 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8611 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8612
a61af66fc99e Initial load
duke
parents:
diff changeset
8613
a61af66fc99e Initial load
duke
parents:
diff changeset
8614 //----------Float Compares----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8615 // Compare floating, generate condition code
a61af66fc99e Initial load
duke
parents:
diff changeset
8616 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8617 match(Set fcc (CmpF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8618
a61af66fc99e Initial load
duke
parents:
diff changeset
8619 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8620 format %{ "FCMPs $fcc,$src1,$src2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8621 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8622 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8623 ins_pipe(faddF_fcc_reg_reg_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
8624 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8625
a61af66fc99e Initial load
duke
parents:
diff changeset
8626 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8627 match(Set fcc (CmpD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8628
a61af66fc99e Initial load
duke
parents:
diff changeset
8629 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8630 format %{ "FCMPd $fcc,$src1,$src2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8631 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
a61af66fc99e Initial load
duke
parents:
diff changeset
8632 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8633 ins_pipe(faddD_fcc_reg_reg_zero);
a61af66fc99e Initial load
duke
parents:
diff changeset
8634 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8635
a61af66fc99e Initial load
duke
parents:
diff changeset
8636
a61af66fc99e Initial load
duke
parents:
diff changeset
8637 // Compare floating, generate -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
8638 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8639 match(Set dst (CmpF3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8640 effect(KILL fcc0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8641 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
a61af66fc99e Initial load
duke
parents:
diff changeset
8642 format %{ "fcmpl $dst,$src1,$src2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8643 // Primary = float
a61af66fc99e Initial load
duke
parents:
diff changeset
8644 opcode( true );
a61af66fc99e Initial load
duke
parents:
diff changeset
8645 ins_encode( floating_cmp( dst, src1, src2 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8646 ins_pipe( floating_cmp );
a61af66fc99e Initial load
duke
parents:
diff changeset
8647 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8648
a61af66fc99e Initial load
duke
parents:
diff changeset
8649 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8650 match(Set dst (CmpD3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8651 effect(KILL fcc0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8652 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
a61af66fc99e Initial load
duke
parents:
diff changeset
8653 format %{ "dcmpl $dst,$src1,$src2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8654 // Primary = double (not float)
a61af66fc99e Initial load
duke
parents:
diff changeset
8655 opcode( false );
a61af66fc99e Initial load
duke
parents:
diff changeset
8656 ins_encode( floating_cmp( dst, src1, src2 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8657 ins_pipe( floating_cmp );
a61af66fc99e Initial load
duke
parents:
diff changeset
8658 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8659
a61af66fc99e Initial load
duke
parents:
diff changeset
8660 //----------Branches---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8661 // Jump
a61af66fc99e Initial load
duke
parents:
diff changeset
8662 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
a61af66fc99e Initial load
duke
parents:
diff changeset
8663 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8664 match(Jump switch_val);
a61af66fc99e Initial load
duke
parents:
diff changeset
8665
a61af66fc99e Initial load
duke
parents:
diff changeset
8666 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
8667
a61af66fc99e Initial load
duke
parents:
diff changeset
8668 format %{ "SETHI [hi(table_base)],O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8669 "ADD O7, lo(table_base), O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8670 "LD [O7+$switch_val], O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8671 "JUMP O7"
a61af66fc99e Initial load
duke
parents:
diff changeset
8672 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8673 ins_encode( jump_enc( switch_val, table) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8674 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8675 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8676 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8677
a61af66fc99e Initial load
duke
parents:
diff changeset
8678 // Direct Branch. Use V8 version with longer range.
a61af66fc99e Initial load
duke
parents:
diff changeset
8679 instruct branch(label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8680 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
8681 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8682
a61af66fc99e Initial load
duke
parents:
diff changeset
8683 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8684 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8685 format %{ "BA $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8686 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
a61af66fc99e Initial load
duke
parents:
diff changeset
8687 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
a61af66fc99e Initial load
duke
parents:
diff changeset
8688 ins_encode( enc_ba( labl ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8689 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8690 ins_pipe(br);
a61af66fc99e Initial load
duke
parents:
diff changeset
8691 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8692
a61af66fc99e Initial load
duke
parents:
diff changeset
8693 // Conditional Direct Branch
a61af66fc99e Initial load
duke
parents:
diff changeset
8694 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8695 match(If cmp icc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8696 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8697
a61af66fc99e Initial load
duke
parents:
diff changeset
8698 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8699 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8700 format %{ "BP$cmp $icc,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8701 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8702 ins_encode( enc_bp( labl, cmp, icc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8703 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8704 ins_pipe(br_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8705 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8706
a61af66fc99e Initial load
duke
parents:
diff changeset
8707 // Branch-on-register tests all 64 bits. We assume that values
a61af66fc99e Initial load
duke
parents:
diff changeset
8708 // in 64-bit registers always remains zero or sign extended
a61af66fc99e Initial load
duke
parents:
diff changeset
8709 // unless our code munges the high bits. Interrupts can chop
a61af66fc99e Initial load
duke
parents:
diff changeset
8710 // the high order bits to zero or sign at any time.
a61af66fc99e Initial load
duke
parents:
diff changeset
8711 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8712 match(If cmp (CmpI op1 zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
8713 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
a61af66fc99e Initial load
duke
parents:
diff changeset
8714 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8715
a61af66fc99e Initial load
duke
parents:
diff changeset
8716 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8717 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8718 format %{ "BR$cmp $op1,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8719 ins_encode( enc_bpr( labl, cmp, op1 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8720 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8721 ins_pipe(br_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8722 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8723
a61af66fc99e Initial load
duke
parents:
diff changeset
8724 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8725 match(If cmp (CmpP op1 null));
a61af66fc99e Initial load
duke
parents:
diff changeset
8726 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
a61af66fc99e Initial load
duke
parents:
diff changeset
8727 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8728
a61af66fc99e Initial load
duke
parents:
diff changeset
8729 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8730 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8731 format %{ "BR$cmp $op1,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8732 ins_encode( enc_bpr( labl, cmp, op1 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8733 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8734 ins_pipe(br_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8735 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8736
a61af66fc99e Initial load
duke
parents:
diff changeset
8737 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8738 match(If cmp (CmpL op1 zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
8739 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
a61af66fc99e Initial load
duke
parents:
diff changeset
8740 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8741
a61af66fc99e Initial load
duke
parents:
diff changeset
8742 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8743 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8744 format %{ "BR$cmp $op1,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8745 ins_encode( enc_bpr( labl, cmp, op1 ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8746 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8747 ins_pipe(br_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8748 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8749
a61af66fc99e Initial load
duke
parents:
diff changeset
8750 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8751 match(If cmp icc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8752 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8753
a61af66fc99e Initial load
duke
parents:
diff changeset
8754 format %{ "BP$cmp $icc,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8755 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8756 ins_encode( enc_bp( labl, cmp, icc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8757 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8758 ins_pipe(br_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8759 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8760
a61af66fc99e Initial load
duke
parents:
diff changeset
8761 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8762 match(If cmp pcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8763 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8764
a61af66fc99e Initial load
duke
parents:
diff changeset
8765 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8766 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8767 format %{ "BP$cmp $pcc,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8768 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8769 ins_encode( enc_bpx( labl, cmp, pcc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8770 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8771 ins_pipe(br_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8772 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8773
a61af66fc99e Initial load
duke
parents:
diff changeset
8774 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8775 match(If cmp fcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8776 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8777
a61af66fc99e Initial load
duke
parents:
diff changeset
8778 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8779 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8780 format %{ "FBP$cmp $fcc,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8781 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8782 ins_encode( enc_fbp( labl, cmp, fcc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8783 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8784 ins_pipe(br_fcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8785 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8786
a61af66fc99e Initial load
duke
parents:
diff changeset
8787 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8788 match(CountedLoopEnd cmp icc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8789 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8790
a61af66fc99e Initial load
duke
parents:
diff changeset
8791 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8792 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8793 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8794 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8795 ins_encode( enc_bp( labl, cmp, icc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8796 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8797 ins_pipe(br_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8798 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8799
a61af66fc99e Initial load
duke
parents:
diff changeset
8800 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8801 match(CountedLoopEnd cmp icc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8802 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8803
a61af66fc99e Initial load
duke
parents:
diff changeset
8804 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8805 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8806 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8807 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8808 ins_encode( enc_bp( labl, cmp, icc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8809 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8810 ins_pipe(br_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8811 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8812
a61af66fc99e Initial load
duke
parents:
diff changeset
8813 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
8814 // Long Compare
a61af66fc99e Initial load
duke
parents:
diff changeset
8815 //
a61af66fc99e Initial load
duke
parents:
diff changeset
8816 // Currently we hold longs in 2 registers. Comparing such values efficiently
a61af66fc99e Initial load
duke
parents:
diff changeset
8817 // is tricky. The flavor of compare used depends on whether we are testing
a61af66fc99e Initial load
duke
parents:
diff changeset
8818 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
a61af66fc99e Initial load
duke
parents:
diff changeset
8819 // The GE test is the negated LT test. The LE test can be had by commuting
a61af66fc99e Initial load
duke
parents:
diff changeset
8820 // the operands (yielding a GE test) and then negating; negate again for the
a61af66fc99e Initial load
duke
parents:
diff changeset
8821 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
a61af66fc99e Initial load
duke
parents:
diff changeset
8822 // NE test is negated from that.
a61af66fc99e Initial load
duke
parents:
diff changeset
8823
a61af66fc99e Initial load
duke
parents:
diff changeset
8824 // Due to a shortcoming in the ADLC, it mixes up expressions like:
a61af66fc99e Initial load
duke
parents:
diff changeset
8825 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
a61af66fc99e Initial load
duke
parents:
diff changeset
8826 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
a61af66fc99e Initial load
duke
parents:
diff changeset
8827 // are collapsed internally in the ADLC's dfa-gen code. The match for
a61af66fc99e Initial load
duke
parents:
diff changeset
8828 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
a61af66fc99e Initial load
duke
parents:
diff changeset
8829 // foo match ends up with the wrong leaf. One fix is to not match both
a61af66fc99e Initial load
duke
parents:
diff changeset
8830 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
a61af66fc99e Initial load
duke
parents:
diff changeset
8831 // both forms beat the trinary form of long-compare and both are very useful
a61af66fc99e Initial load
duke
parents:
diff changeset
8832 // on Intel which has so few registers.
a61af66fc99e Initial load
duke
parents:
diff changeset
8833
a61af66fc99e Initial load
duke
parents:
diff changeset
8834 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8835 match(If cmp xcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8836 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
8837
a61af66fc99e Initial load
duke
parents:
diff changeset
8838 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8839 ins_cost(BRANCH_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8840 format %{ "BP$cmp $xcc,$labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8841 // Prim = bits 24-22, Secnd = bits 31-30
a61af66fc99e Initial load
duke
parents:
diff changeset
8842 ins_encode( enc_bpl( labl, cmp, xcc ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8843 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8844 ins_pipe(br_cc);
a61af66fc99e Initial load
duke
parents:
diff changeset
8845 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8846
a61af66fc99e Initial load
duke
parents:
diff changeset
8847 // Manifest a CmpL3 result in an integer register. Very painful.
a61af66fc99e Initial load
duke
parents:
diff changeset
8848 // This is the test to avoid.
a61af66fc99e Initial load
duke
parents:
diff changeset
8849 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8850 match(Set dst (CmpL3 src1 src2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8851 effect( KILL ccr );
a61af66fc99e Initial load
duke
parents:
diff changeset
8852 ins_cost(6*DEFAULT_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8853 size(24);
a61af66fc99e Initial load
duke
parents:
diff changeset
8854 format %{ "CMP $src1,$src2\t\t! long\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8855 "\tBLT,a,pn done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8856 "\tMOV -1,$dst\t! delay slot\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8857 "\tBGT,a,pn done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8858 "\tMOV 1,$dst\t! delay slot\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8859 "\tCLR $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8860 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8861 ins_encode( cmpl_flag(src1,src2,dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8862 ins_pipe(cmpL_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8863 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8864
a61af66fc99e Initial load
duke
parents:
diff changeset
8865 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
8866 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8867 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8868 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8869 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8871 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8872 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8873
a61af66fc99e Initial load
duke
parents:
diff changeset
8874 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8875 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8876 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
8877 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8878 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8879 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8880 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8881
a61af66fc99e Initial load
duke
parents:
diff changeset
8882 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8883 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8884 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8885 format %{ "MOV$cmp $xcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8886 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8887 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8888 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8889
a61af66fc99e Initial load
duke
parents:
diff changeset
8890 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8891 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8892 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
8893 format %{ "MOV$cmp $xcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8894 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8895 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8896 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8897
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8898 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8899 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8900 ins_cost(150);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8901 format %{ "MOV$cmp $xcc,$src,$dst" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8902 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8903 ins_pipe(ialu_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8904 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
8905
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8906 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8907 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8908 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8909 format %{ "MOV$cmp $xcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8911 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8912 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8913
a61af66fc99e Initial load
duke
parents:
diff changeset
8914 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8915 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8916 ins_cost(140);
a61af66fc99e Initial load
duke
parents:
diff changeset
8917 format %{ "MOV$cmp $xcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8918 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8919 ins_pipe(ialu_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8920 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8921
a61af66fc99e Initial load
duke
parents:
diff changeset
8922 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8923 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8924 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8925 opcode(0x101);
a61af66fc99e Initial load
duke
parents:
diff changeset
8926 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8927 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8928 ins_pipe(int_conditional_float_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
8929 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8930
a61af66fc99e Initial load
duke
parents:
diff changeset
8931 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8932 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8933 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8934 opcode(0x102);
a61af66fc99e Initial load
duke
parents:
diff changeset
8935 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8936 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8937 ins_pipe(int_conditional_float_move);
a61af66fc99e Initial load
duke
parents:
diff changeset
8938 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8939
a61af66fc99e Initial load
duke
parents:
diff changeset
8940 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
8941 // Safepoint Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
8942 instruct safePoint_poll(iRegP poll) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8943 match(SafePoint poll);
a61af66fc99e Initial load
duke
parents:
diff changeset
8944 effect(USE poll);
a61af66fc99e Initial load
duke
parents:
diff changeset
8945
a61af66fc99e Initial load
duke
parents:
diff changeset
8946 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
8947 #ifdef _LP64
a61af66fc99e Initial load
duke
parents:
diff changeset
8948 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8949 #else
a61af66fc99e Initial load
duke
parents:
diff changeset
8950 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8951 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
8952 ins_encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8953 __ relocate(relocInfo::poll_type);
a61af66fc99e Initial load
duke
parents:
diff changeset
8954 __ ld_ptr($poll$$Register, 0, G0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8955 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8956 ins_pipe(loadPollP);
a61af66fc99e Initial load
duke
parents:
diff changeset
8957 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8958
a61af66fc99e Initial load
duke
parents:
diff changeset
8959 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
8960 // Call Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8961 // Call Java Static Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
8962 instruct CallStaticJavaDirect( method meth ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8963 match(CallStaticJava);
a61af66fc99e Initial load
duke
parents:
diff changeset
8964 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
8965
a61af66fc99e Initial load
duke
parents:
diff changeset
8966 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
8967 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8968 format %{ "CALL,static ; NOP ==> " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8969 ins_encode( Java_Static_Call( meth ), call_epilog );
a61af66fc99e Initial load
duke
parents:
diff changeset
8970 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8971 ins_pipe(simple_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
8972 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8973
a61af66fc99e Initial load
duke
parents:
diff changeset
8974 // Call Java Dynamic Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
8975 instruct CallDynamicJavaDirect( method meth ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8976 match(CallDynamicJava);
a61af66fc99e Initial load
duke
parents:
diff changeset
8977 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
8978
a61af66fc99e Initial load
duke
parents:
diff changeset
8979 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8980 format %{ "SET (empty),R_G5\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8981 "CALL,dynamic ; NOP ==> " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8982 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
a61af66fc99e Initial load
duke
parents:
diff changeset
8983 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8984 ins_pipe(call);
a61af66fc99e Initial load
duke
parents:
diff changeset
8985 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8986
a61af66fc99e Initial load
duke
parents:
diff changeset
8987 // Call Runtime Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
8988 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8989 match(CallRuntime);
a61af66fc99e Initial load
duke
parents:
diff changeset
8990 effect(USE meth, KILL l7);
a61af66fc99e Initial load
duke
parents:
diff changeset
8991 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
8992 format %{ "CALL,runtime" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8993 ins_encode( Java_To_Runtime( meth ),
a61af66fc99e Initial load
duke
parents:
diff changeset
8994 call_epilog, adjust_long_from_native_call );
a61af66fc99e Initial load
duke
parents:
diff changeset
8995 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8996 ins_pipe(simple_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
8997 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8998
a61af66fc99e Initial load
duke
parents:
diff changeset
8999 // Call runtime without safepoint - same as CallRuntime
a61af66fc99e Initial load
duke
parents:
diff changeset
9000 instruct CallLeafDirect(method meth, l7RegP l7) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9001 match(CallLeaf);
a61af66fc99e Initial load
duke
parents:
diff changeset
9002 effect(USE meth, KILL l7);
a61af66fc99e Initial load
duke
parents:
diff changeset
9003 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9004 format %{ "CALL,runtime leaf" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9005 ins_encode( Java_To_Runtime( meth ),
a61af66fc99e Initial load
duke
parents:
diff changeset
9006 call_epilog,
a61af66fc99e Initial load
duke
parents:
diff changeset
9007 adjust_long_from_native_call );
a61af66fc99e Initial load
duke
parents:
diff changeset
9008 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
9009 ins_pipe(simple_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
9010 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9011
a61af66fc99e Initial load
duke
parents:
diff changeset
9012 // Call runtime without safepoint - same as CallLeaf
a61af66fc99e Initial load
duke
parents:
diff changeset
9013 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9014 match(CallLeafNoFP);
a61af66fc99e Initial load
duke
parents:
diff changeset
9015 effect(USE meth, KILL l7);
a61af66fc99e Initial load
duke
parents:
diff changeset
9016 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9017 format %{ "CALL,runtime leaf nofp" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9018 ins_encode( Java_To_Runtime( meth ),
a61af66fc99e Initial load
duke
parents:
diff changeset
9019 call_epilog,
a61af66fc99e Initial load
duke
parents:
diff changeset
9020 adjust_long_from_native_call );
a61af66fc99e Initial load
duke
parents:
diff changeset
9021 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
9022 ins_pipe(simple_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
9023 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9024
a61af66fc99e Initial load
duke
parents:
diff changeset
9025 // Tail Call; Jump from runtime stub to Java code.
a61af66fc99e Initial load
duke
parents:
diff changeset
9026 // Also known as an 'interprocedural jump'.
a61af66fc99e Initial load
duke
parents:
diff changeset
9027 // Target of jump will eventually return to caller.
a61af66fc99e Initial load
duke
parents:
diff changeset
9028 // TailJump below removes the return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
9029 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9030 match(TailCall jump_target method_oop );
a61af66fc99e Initial load
duke
parents:
diff changeset
9031
a61af66fc99e Initial load
duke
parents:
diff changeset
9032 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9033 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9034 ins_encode(form_jmpl(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
9035 ins_pipe(tail_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
9036 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9037
a61af66fc99e Initial load
duke
parents:
diff changeset
9038
a61af66fc99e Initial load
duke
parents:
diff changeset
9039 // Return Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
9040 instruct Ret() %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9041 match(Return);
a61af66fc99e Initial load
duke
parents:
diff changeset
9042
a61af66fc99e Initial load
duke
parents:
diff changeset
9043 // The epilogue node did the ret already.
a61af66fc99e Initial load
duke
parents:
diff changeset
9044 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9045 format %{ "! return" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9046 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
9047 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
9048 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9049
a61af66fc99e Initial load
duke
parents:
diff changeset
9050
a61af66fc99e Initial load
duke
parents:
diff changeset
9051 // Tail Jump; remove the return address; jump to target.
a61af66fc99e Initial load
duke
parents:
diff changeset
9052 // TailCall above leaves the return address around.
a61af66fc99e Initial load
duke
parents:
diff changeset
9053 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
a61af66fc99e Initial load
duke
parents:
diff changeset
9054 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
a61af66fc99e Initial load
duke
parents:
diff changeset
9055 // "restore" before this instruction (in Epilogue), we need to materialize it
a61af66fc99e Initial load
duke
parents:
diff changeset
9056 // in %i0.
a61af66fc99e Initial load
duke
parents:
diff changeset
9057 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9058 match( TailJump jump_target ex_oop );
a61af66fc99e Initial load
duke
parents:
diff changeset
9059 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9060 format %{ "! discard R_O7\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9061 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9062 ins_encode(form_jmpl_set_exception_pc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
9063 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
9064 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
a61af66fc99e Initial load
duke
parents:
diff changeset
9065 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
a61af66fc99e Initial load
duke
parents:
diff changeset
9066 ins_pipe(tail_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
9067 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9068
a61af66fc99e Initial load
duke
parents:
diff changeset
9069 // Create exception oop: created by stack-crawling runtime code.
a61af66fc99e Initial load
duke
parents:
diff changeset
9070 // Created exception is now available to this handler, and is setup
a61af66fc99e Initial load
duke
parents:
diff changeset
9071 // just prior to jumping to this handler. No code emitted.
a61af66fc99e Initial load
duke
parents:
diff changeset
9072 instruct CreateException( o0RegP ex_oop )
a61af66fc99e Initial load
duke
parents:
diff changeset
9073 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9074 match(Set ex_oop (CreateEx));
a61af66fc99e Initial load
duke
parents:
diff changeset
9075 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9076
a61af66fc99e Initial load
duke
parents:
diff changeset
9077 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9078 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
9079 format %{ "! exception oop is in R_O0; no code emitted" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9080 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
9081 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
9082 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9083
a61af66fc99e Initial load
duke
parents:
diff changeset
9084
a61af66fc99e Initial load
duke
parents:
diff changeset
9085 // Rethrow exception:
a61af66fc99e Initial load
duke
parents:
diff changeset
9086 // The exception oop will come in the first argument position.
a61af66fc99e Initial load
duke
parents:
diff changeset
9087 // Then JUMP (not call) to the rethrow stub code.
a61af66fc99e Initial load
duke
parents:
diff changeset
9088 instruct RethrowException()
a61af66fc99e Initial load
duke
parents:
diff changeset
9089 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9090 match(Rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9091 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9092
a61af66fc99e Initial load
duke
parents:
diff changeset
9093 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
9094 format %{ "Jmp rethrow_stub" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9095 ins_encode(enc_rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9096 ins_pipe(tail_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
9097 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9098
a61af66fc99e Initial load
duke
parents:
diff changeset
9099
a61af66fc99e Initial load
duke
parents:
diff changeset
9100 // Die now
a61af66fc99e Initial load
duke
parents:
diff changeset
9101 instruct ShouldNotReachHere( )
a61af66fc99e Initial load
duke
parents:
diff changeset
9102 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9103 match(Halt);
a61af66fc99e Initial load
duke
parents:
diff changeset
9104 ins_cost(CALL_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9105
a61af66fc99e Initial load
duke
parents:
diff changeset
9106 size(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
9107 // Use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
9108 format %{ "ILLTRAP ; ShouldNotReachHere" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9109 ins_encode( form2_illtrap() );
a61af66fc99e Initial load
duke
parents:
diff changeset
9110 ins_pipe(tail_call);
a61af66fc99e Initial load
duke
parents:
diff changeset
9111 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9112
a61af66fc99e Initial load
duke
parents:
diff changeset
9113 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
9114 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
a61af66fc99e Initial load
duke
parents:
diff changeset
9115 // array for an instance of the superklass. Set a hidden internal cache on a
a61af66fc99e Initial load
duke
parents:
diff changeset
9116 // hit (cache is checked with exposed code in gen_subtype_check()). Return
a61af66fc99e Initial load
duke
parents:
diff changeset
9117 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
9118 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9119 match(Set index (PartialSubtypeCheck sub super));
a61af66fc99e Initial load
duke
parents:
diff changeset
9120 effect( KILL pcc, KILL o7 );
a61af66fc99e Initial load
duke
parents:
diff changeset
9121 ins_cost(DEFAULT_COST*10);
a61af66fc99e Initial load
duke
parents:
diff changeset
9122 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9123 ins_encode( enc_PartialSubtypeCheck() );
a61af66fc99e Initial load
duke
parents:
diff changeset
9124 ins_pipe(partial_subtype_check_pipe);
a61af66fc99e Initial load
duke
parents:
diff changeset
9125 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9126
a61af66fc99e Initial load
duke
parents:
diff changeset
9127 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9128 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
9129 effect( KILL idx, KILL o7 );
a61af66fc99e Initial load
duke
parents:
diff changeset
9130 ins_cost(DEFAULT_COST*10);
a61af66fc99e Initial load
duke
parents:
diff changeset
9131 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9132 ins_encode( enc_PartialSubtypeCheck() );
a61af66fc99e Initial load
duke
parents:
diff changeset
9133 ins_pipe(partial_subtype_check_pipe);
a61af66fc99e Initial load
duke
parents:
diff changeset
9134 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9135
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
9136
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9137 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
9138 // inlined locking and unlocking
a61af66fc99e Initial load
duke
parents:
diff changeset
9139
a61af66fc99e Initial load
duke
parents:
diff changeset
9140 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9141 match(Set pcc (FastLock object box));
a61af66fc99e Initial load
duke
parents:
diff changeset
9142
a61af66fc99e Initial load
duke
parents:
diff changeset
9143 effect(KILL scratch, TEMP scratch2);
a61af66fc99e Initial load
duke
parents:
diff changeset
9144 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
9145
a61af66fc99e Initial load
duke
parents:
diff changeset
9146 size(4*112); // conservative overestimation ...
a61af66fc99e Initial load
duke
parents:
diff changeset
9147 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9148 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9149 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
9150 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9151
a61af66fc99e Initial load
duke
parents:
diff changeset
9152
a61af66fc99e Initial load
duke
parents:
diff changeset
9153 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9154 match(Set pcc (FastUnlock object box));
a61af66fc99e Initial load
duke
parents:
diff changeset
9155 effect(KILL scratch, TEMP scratch2);
a61af66fc99e Initial load
duke
parents:
diff changeset
9156 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
9157
a61af66fc99e Initial load
duke
parents:
diff changeset
9158 size(4*120); // conservative overestimation ...
a61af66fc99e Initial load
duke
parents:
diff changeset
9159 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9160 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9161 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
9162 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9163
a61af66fc99e Initial load
duke
parents:
diff changeset
9164 // Count and Base registers are fixed because the allocator cannot
a61af66fc99e Initial load
duke
parents:
diff changeset
9165 // kill unknown registers. The encodings are generic.
a61af66fc99e Initial load
duke
parents:
diff changeset
9166 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9167 match(Set dummy (ClearArray cnt base));
a61af66fc99e Initial load
duke
parents:
diff changeset
9168 effect(TEMP temp, KILL ccr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9169 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
9170 format %{ "MOV $cnt,$temp\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9171 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9172 " BRge loop\t\t! Clearing loop\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9173 " STX G0,[$base+$temp]\t! delay slot" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9174 ins_encode( enc_Clear_Array(cnt, base, temp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9175 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
9176 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9177
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
9178 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
9179 o7RegI tmp3, flagsReg ccr) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9180 match(Set result (StrComp str1 str2));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 81
diff changeset
9181 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9182 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
9183 format %{ "String Compare $str1,$str2 -> $result" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9184 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9185 ins_pipe(long_memory_op);
a61af66fc99e Initial load
duke
parents:
diff changeset
9186 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9187
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9188 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9189 o7RegI tmp3, flagsReg ccr) %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9190 match(Set result (StrEquals str1 str2));
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9191 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9192 ins_cost(300);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9193 format %{ "String Equals $str1,$str2 -> $result" %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9194 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9195 ins_pipe(long_memory_op);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9196 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9197
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9198 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9199 flagsReg ccr) %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9200 match(Set result (AryEq ary1 ary2));
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9201 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9202 ins_cost(300);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9203 format %{ "Array Equals $ary1,$ary2 -> $result" %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9204 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9205 ins_pipe(long_memory_op);
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 647
diff changeset
9206 %}
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9207
775
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9208
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9209 //---------- Zeros Count Instructions ------------------------------------------
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9210
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9211 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9212 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9213 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9214 effect(TEMP dst, TEMP tmp, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9215
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9216 // x |= (x >> 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9217 // x |= (x >> 2);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9218 // x |= (x >> 4);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9219 // x |= (x >> 8);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9220 // x |= (x >> 16);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9221 // return (WORDBITS - popc(x));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9222 format %{ "SRL $src,1,$dst\t! count leading zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9223 "OR $src,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9224 "SRL $dst,2,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9225 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9226 "SRL $dst,4,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9227 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9228 "SRL $dst,8,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9229 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9230 "SRL $dst,16,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9231 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9232 "POPC $dst,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9233 "MOV 32,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9234 "SUB $tmp,$dst,$dst" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9235 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9236 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9237 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9238 Register Rtmp = $tmp$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9239 __ srl(Rsrc, 1, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9240 __ or3(Rsrc, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9241 __ srl(Rdst, 2, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9242 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9243 __ srl(Rdst, 4, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9244 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9245 __ srl(Rdst, 8, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9246 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9247 __ srl(Rdst, 16, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9248 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9249 __ popc(Rdst, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9250 __ mov(BitsPerInt, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9251 __ sub(Rtmp, Rdst, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9252 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9253 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9254 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9255
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9256 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9257 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9258 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9259 effect(TEMP dst, TEMP tmp, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9260
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9261 // x |= (x >> 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9262 // x |= (x >> 2);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9263 // x |= (x >> 4);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9264 // x |= (x >> 8);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9265 // x |= (x >> 16);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9266 // x |= (x >> 32);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9267 // return (WORDBITS - popc(x));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9268 format %{ "SRLX $src,1,$dst\t! count leading zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9269 "OR $src,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9270 "SRLX $dst,2,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9271 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9272 "SRLX $dst,4,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9273 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9274 "SRLX $dst,8,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9275 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9276 "SRLX $dst,16,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9277 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9278 "SRLX $dst,32,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9279 "OR $dst,$tmp,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9280 "POPC $dst,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9281 "MOV 64,$tmp\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9282 "SUB $tmp,$dst,$dst" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9283 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9284 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9285 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9286 Register Rtmp = $tmp$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9287 __ srlx(Rsrc, 1, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9288 __ or3(Rsrc, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9289 __ srlx(Rdst, 2, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9290 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9291 __ srlx(Rdst, 4, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9292 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9293 __ srlx(Rdst, 8, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9294 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9295 __ srlx(Rdst, 16, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9296 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9297 __ srlx(Rdst, 32, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9298 __ or3(Rdst, Rtmp, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9299 __ popc(Rdst, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9300 __ mov(BitsPerLong, Rtmp);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9301 __ sub(Rtmp, Rdst, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9302 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9303 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9304 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9305
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9306 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9307 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9308 match(Set dst (CountTrailingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9309 effect(TEMP dst, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9310
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9311 // return popc(~x & (x - 1));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9312 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9313 "ANDN $dst,$src,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9314 "SRL $dst,R_G0,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9315 "POPC $dst,$dst" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9316 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9317 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9318 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9319 __ sub(Rsrc, 1, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9320 __ andn(Rdst, Rsrc, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9321 __ srl(Rdst, G0, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9322 __ popc(Rdst, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9323 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9324 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9325 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9326
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9327 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9328 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9329 match(Set dst (CountTrailingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9330 effect(TEMP dst, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9331
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9332 // return popc(~x & (x - 1));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9333 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9334 "ANDN $dst,$src,$dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9335 "POPC $dst,$dst" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9336 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9337 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9338 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9339 __ sub(Rsrc, 1, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9340 __ andn(Rdst, Rsrc, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9341 __ popc(Rdst, Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9342 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9343 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9344 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9345
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 732
diff changeset
9346
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9347 //---------- Population Count Instructions -------------------------------------
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9348
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9349 instruct popCountI(iRegI dst, iRegI src) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9350 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9351 match(Set dst (PopCountI src));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9352
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9353 format %{ "POPC $src, $dst" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9354 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9355 __ popc($src$$Register, $dst$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9356 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9357 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9358 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9359
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9360 // Note: Long.bitCount(long) returns an int.
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9361 instruct popCountL(iRegI dst, iRegL src) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9362 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9363 match(Set dst (PopCountL src));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9364
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9365 format %{ "POPC $src, $dst" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9366 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9367 __ popc($src$$Register, $dst$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9368 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9369 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9370 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9371
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
9372
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9373 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
9374 //------------Bytes reverse--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9375
a61af66fc99e Initial load
duke
parents:
diff changeset
9376 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9377 match(Set dst (ReverseBytesI src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9378 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9379
a61af66fc99e Initial load
duke
parents:
diff changeset
9380 // Op cost is artificially doubled to make sure that load or store
a61af66fc99e Initial load
duke
parents:
diff changeset
9381 // instructions are preferred over this one which requires a spill
a61af66fc99e Initial load
duke
parents:
diff changeset
9382 // onto a stack slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
9383 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9384 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
9385 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9386 opcode(Assembler::lduwa_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
9387 ins_encode( form3_mem_reg_little(src, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9388 ins_pipe( iload_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
9389 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9390
a61af66fc99e Initial load
duke
parents:
diff changeset
9391 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9392 match(Set dst (ReverseBytesL src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9393 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9394
a61af66fc99e Initial load
duke
parents:
diff changeset
9395 // Op cost is artificially doubled to make sure that load or store
a61af66fc99e Initial load
duke
parents:
diff changeset
9396 // instructions are preferred over this one which requires a spill
a61af66fc99e Initial load
duke
parents:
diff changeset
9397 // onto a stack slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
9398 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9399 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
9400 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9401
a61af66fc99e Initial load
duke
parents:
diff changeset
9402 opcode(Assembler::ldxa_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
9403 ins_encode( form3_mem_reg_little(src, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9404 ins_pipe( iload_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
9405 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9406
a61af66fc99e Initial load
duke
parents:
diff changeset
9407 // Load Integer reversed byte order
a61af66fc99e Initial load
duke
parents:
diff changeset
9408 instruct loadI_reversed(iRegI dst, memory src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9409 match(Set dst (ReverseBytesI (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9410
a61af66fc99e Initial load
duke
parents:
diff changeset
9411 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9412 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
9413 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9414
a61af66fc99e Initial load
duke
parents:
diff changeset
9415 opcode(Assembler::lduwa_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
9416 ins_encode( form3_mem_reg_little( src, dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9417 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9418 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9419
a61af66fc99e Initial load
duke
parents:
diff changeset
9420 // Load Long - aligned and reversed
a61af66fc99e Initial load
duke
parents:
diff changeset
9421 instruct loadL_reversed(iRegL dst, memory src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9422 match(Set dst (ReverseBytesL (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9423
a61af66fc99e Initial load
duke
parents:
diff changeset
9424 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9425 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
9426 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9427
a61af66fc99e Initial load
duke
parents:
diff changeset
9428 opcode(Assembler::ldxa_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
9429 ins_encode( form3_mem_reg_little( src, dst ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9430 ins_pipe(iload_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9431 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9432
a61af66fc99e Initial load
duke
parents:
diff changeset
9433 // Store Integer reversed byte order
a61af66fc99e Initial load
duke
parents:
diff changeset
9434 instruct storeI_reversed(memory dst, iRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9435 match(Set dst (StoreI dst (ReverseBytesI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9436
a61af66fc99e Initial load
duke
parents:
diff changeset
9437 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9438 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
9439 format %{ "STWA $src, $dst\t!asi=primary_little" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9440
a61af66fc99e Initial load
duke
parents:
diff changeset
9441 opcode(Assembler::stwa_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
9442 ins_encode( form3_mem_reg_little( dst, src) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9443 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9444 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9445
a61af66fc99e Initial load
duke
parents:
diff changeset
9446 // Store Long reversed byte order
a61af66fc99e Initial load
duke
parents:
diff changeset
9447 instruct storeL_reversed(memory dst, iRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9448 match(Set dst (StoreL dst (ReverseBytesL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9449
a61af66fc99e Initial load
duke
parents:
diff changeset
9450 ins_cost(MEMORY_REF_COST);
a61af66fc99e Initial load
duke
parents:
diff changeset
9451 size(8);
a61af66fc99e Initial load
duke
parents:
diff changeset
9452 format %{ "STXA $src, $dst\t!asi=primary_little" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9453
a61af66fc99e Initial load
duke
parents:
diff changeset
9454 opcode(Assembler::stxa_op3);
a61af66fc99e Initial load
duke
parents:
diff changeset
9455 ins_encode( form3_mem_reg_little( dst, src) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9456 ins_pipe(istore_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9457 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9458
a61af66fc99e Initial load
duke
parents:
diff changeset
9459 //----------PEEPHOLE RULES-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9460 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
9461 // defined in the instructions definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
9462 //
605
98cb887364d3 6810672: Comment typos
twisti
parents: 558
diff changeset
9463 // peepmatch ( root_instr_name [preceding_instruction]* );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9464 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9465 // peepconstraint %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9466 // (instruction_number.operand_name relational_op instruction_number.operand_name
a61af66fc99e Initial load
duke
parents:
diff changeset
9467 // [, ...] );
a61af66fc99e Initial load
duke
parents:
diff changeset
9468 // // instruction numbers are zero-based using left to right order in peepmatch
a61af66fc99e Initial load
duke
parents:
diff changeset
9469 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9470 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9471 // // provide an instruction_number.operand_name for each operand that appears
a61af66fc99e Initial load
duke
parents:
diff changeset
9472 // // in the replacement instruction's match rule
a61af66fc99e Initial load
duke
parents:
diff changeset
9473 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9474 // ---------VM FLAGS---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9475 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9476 // All peephole optimizations can be turned off using -XX:-OptoPeephole
a61af66fc99e Initial load
duke
parents:
diff changeset
9477 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9478 // Each peephole rule is given an identifying number starting with zero and
a61af66fc99e Initial load
duke
parents:
diff changeset
9479 // increasing by one in the order seen by the parser. An individual peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
9480 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
a61af66fc99e Initial load
duke
parents:
diff changeset
9481 // on the command-line.
a61af66fc99e Initial load
duke
parents:
diff changeset
9482 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9483 // ---------CURRENT LIMITATIONS----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9484 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9485 // Only match adjacent instructions in same basic block
a61af66fc99e Initial load
duke
parents:
diff changeset
9486 // Only equality constraints
a61af66fc99e Initial load
duke
parents:
diff changeset
9487 // Only constraints between operands, not (0.dest_reg == EAX_enc)
a61af66fc99e Initial load
duke
parents:
diff changeset
9488 // Only one replacement instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
9489 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9490 // ---------EXAMPLE----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9491 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9492 // // pertinent parts of existing instructions in architecture description
a61af66fc99e Initial load
duke
parents:
diff changeset
9493 // instruct movI(eRegI dst, eRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9494 // match(Set dst (CopyI src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9495 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9496 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9497 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9498 // match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9499 // effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9500 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9501 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9502 // // Change (inc mov) to lea
a61af66fc99e Initial load
duke
parents:
diff changeset
9503 // peephole %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9504 // // increment preceeded by register-register move
a61af66fc99e Initial load
duke
parents:
diff changeset
9505 // peepmatch ( incI_eReg movI );
a61af66fc99e Initial load
duke
parents:
diff changeset
9506 // // require that the destination register of the increment
a61af66fc99e Initial load
duke
parents:
diff changeset
9507 // // match the destination register of the move
a61af66fc99e Initial load
duke
parents:
diff changeset
9508 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load
duke
parents:
diff changeset
9509 // // construct a replacement instruction that sets
a61af66fc99e Initial load
duke
parents:
diff changeset
9510 // // the destination to ( move's source register + one )
a61af66fc99e Initial load
duke
parents:
diff changeset
9511 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9512 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9513 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9514
a61af66fc99e Initial load
duke
parents:
diff changeset
9515 // // Change load of spilled value to only a spill
a61af66fc99e Initial load
duke
parents:
diff changeset
9516 // instruct storeI(memory mem, eRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9517 // match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9518 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9519 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9520 // instruct loadI(eRegI dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9521 // match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
9522 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9523 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9524 // peephole %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9525 // peepmatch ( loadI storeI );
a61af66fc99e Initial load
duke
parents:
diff changeset
9526 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
9527 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9528 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9529
a61af66fc99e Initial load
duke
parents:
diff changeset
9530 //----------SMARTSPILL RULES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9531 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
9532 // defined in the instructions definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
9533 //
a61af66fc99e Initial load
duke
parents:
diff changeset
9534 // SPARC will probably not have any of these rules due to RISC instruction set.
a61af66fc99e Initial load
duke
parents:
diff changeset
9535
a61af66fc99e Initial load
duke
parents:
diff changeset
9536 //----------PIPELINE-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9537 // Rules which define the behavior of the target architectures pipeline.