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annotate src/cpu/x86/vm/assembler_x86.hpp @ 17411:6d82c240d83e
use -G:CompileTheWorldClasspath instead of -Xbootclasspath/p when doing Graal CTW on a Graal enabled VM
author | Doug Simon <doug.simon@oracle.com> |
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date | Fri, 10 Oct 2014 11:33:48 +0200 |
parents | 88df5d7b1001 |
children | 52b4284cb496 |
rev | line source |
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0 | 1 /* |
7951 | 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
27 | |
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28 #include "asm/register.hpp" |
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29 |
0 | 30 class BiasedLockingCounters; |
31 | |
32 // Contains all the definitions needed for x86 assembly code generation. | |
33 | |
34 // Calling convention | |
35 class Argument VALUE_OBJ_CLASS_SPEC { | |
36 public: | |
37 enum { | |
38 #ifdef _LP64 | |
39 #ifdef _WIN64 | |
40 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
41 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
42 #else | |
43 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
44 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
45 #endif // _WIN64 | |
46 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
47 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
48 #else | |
49 n_register_parameters = 0 // 0 registers used to pass arguments | |
50 #endif // _LP64 | |
51 }; | |
52 }; | |
53 | |
54 | |
55 #ifdef _LP64 | |
56 // Symbolically name the register arguments used by the c calling convention. | |
57 // Windows is different from linux/solaris. So much for standards... | |
58 | |
59 #ifdef _WIN64 | |
60 | |
61 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
62 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
63 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
64 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
65 | |
304 | 66 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
67 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
68 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
69 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
0 | 70 |
71 #else | |
72 | |
73 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
74 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
75 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
76 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
77 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
78 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
79 | |
304 | 80 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
81 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
82 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
83 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
84 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
85 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
86 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
87 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
0 | 88 |
89 #endif // _WIN64 | |
90 | |
91 // Symbolically name the register arguments used by the Java calling convention. | |
92 // We have control over the convention for java so we can do what we please. | |
93 // What pleases us is to offset the java calling convention so that when | |
94 // we call a suitable jni method the arguments are lined up and we don't | |
95 // have to do little shuffling. A suitable jni method is non-static and a | |
96 // small number of arguments (two fewer args on windows) | |
97 // | |
98 // |-------------------------------------------------------| | |
99 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
100 // |-------------------------------------------------------| | |
101 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
102 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
103 // |-------------------------------------------------------| | |
104 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
105 // |-------------------------------------------------------| | |
106 | |
107 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
108 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
109 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
110 // Windows runs out of register args here | |
111 #ifdef _WIN64 | |
112 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
113 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
114 #else | |
115 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
116 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
117 #endif /* _WIN64 */ | |
118 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
119 | |
304 | 120 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
121 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
122 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
123 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
124 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
125 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
126 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
127 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
0 | 128 |
129 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
130 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
131 | |
304 | 132 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
0 | 133 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
134 | |
304 | 135 #else |
136 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
137 // Using noreg ensures if the dead code is incorrectly live and executed it | |
138 // will cause an assertion failure | |
139 #define rscratch1 noreg | |
2002 | 140 #define rscratch2 noreg |
304 | 141 |
0 | 142 #endif // _LP64 |
143 | |
1564 | 144 // JSR 292 fixed register usages: |
145 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
146 | |
0 | 147 // Address is an abstraction used to represent a memory location |
148 // using any of the amd64 addressing modes with one object. | |
149 // | |
150 // Note: A register location is represented via a Register, not | |
151 // via an address for efficiency & simplicity reasons. | |
152 | |
153 class ArrayAddress; | |
154 | |
155 class Address VALUE_OBJ_CLASS_SPEC { | |
156 public: | |
157 enum ScaleFactor { | |
158 no_scale = -1, | |
159 times_1 = 0, | |
160 times_2 = 1, | |
161 times_4 = 2, | |
304 | 162 times_8 = 3, |
163 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
0 | 164 }; |
622
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165 static ScaleFactor times(int size) { |
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166 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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167 if (size == 8) return times_8; |
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168 if (size == 4) return times_4; |
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169 if (size == 2) return times_2; |
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170 return times_1; |
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171 } |
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172 static int scale_size(ScaleFactor scale) { |
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173 assert(scale != no_scale, ""); |
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174 assert(((1 << (int)times_1) == 1 && |
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175 (1 << (int)times_2) == 2 && |
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176 (1 << (int)times_4) == 4 && |
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177 (1 << (int)times_8) == 8), ""); |
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178 return (1 << (int)scale); |
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179 } |
0 | 180 |
181 private: | |
182 Register _base; | |
183 Register _index; | |
184 ScaleFactor _scale; | |
185 int _disp; | |
186 RelocationHolder _rspec; | |
187 | |
304 | 188 // Easily misused constructors make them private |
189 // %%% can we make these go away? | |
190 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
191 Address(int disp, address loc, relocInfo::relocType rtype); | |
192 Address(int disp, address loc, RelocationHolder spec); | |
0 | 193 |
194 public: | |
304 | 195 |
196 int disp() { return _disp; } | |
0 | 197 // creation |
198 Address() | |
199 : _base(noreg), | |
200 _index(noreg), | |
201 _scale(no_scale), | |
202 _disp(0) { | |
203 } | |
204 | |
205 // No default displacement otherwise Register can be implicitly | |
206 // converted to 0(Register) which is quite a different animal. | |
207 | |
208 Address(Register base, int disp) | |
209 : _base(base), | |
210 _index(noreg), | |
211 _scale(no_scale), | |
212 _disp(disp) { | |
213 } | |
214 | |
215 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
216 : _base (base), | |
217 _index(index), | |
218 _scale(scale), | |
219 _disp (disp) { | |
220 assert(!index->is_valid() == (scale == Address::no_scale), | |
221 "inconsistent address"); | |
222 } | |
223 | |
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224 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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225 : _base (base), |
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226 _index(index.register_or_noreg()), |
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227 _scale(scale), |
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228 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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229 if (!index.is_register()) scale = Address::no_scale; |
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230 assert(!_index->is_valid() == (scale == Address::no_scale), |
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231 "inconsistent address"); |
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232 } |
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233 |
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234 Address plus_disp(int disp) const { |
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235 Address a = (*this); |
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236 a._disp += disp; |
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237 return a; |
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238 } |
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239 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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240 Address a = (*this); |
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241 a._disp += disp.constant_or_zero() * scale_size(scale); |
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242 if (disp.is_register()) { |
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243 assert(!a.index()->is_valid(), "competing indexes"); |
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244 a._index = disp.as_register(); |
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245 a._scale = scale; |
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246 } |
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247 return a; |
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248 } |
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249 bool is_same_address(Address a) const { |
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250 // disregard _rspec |
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251 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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252 } |
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253 |
0 | 254 // The following two overloads are used in connection with the |
255 // ByteSize type (see sizes.hpp). They simplify the use of | |
256 // ByteSize'd arguments in assembly code. Note that their equivalent | |
257 // for the optimized build are the member functions with int disp | |
258 // argument since ByteSize is mapped to an int type in that case. | |
259 // | |
260 // Note: DO NOT introduce similar overloaded functions for WordSize | |
261 // arguments as in the optimized mode, both ByteSize and WordSize | |
262 // are mapped to the same type and thus the compiler cannot make a | |
263 // distinction anymore (=> compiler errors). | |
264 | |
265 #ifdef ASSERT | |
266 Address(Register base, ByteSize disp) | |
267 : _base(base), | |
268 _index(noreg), | |
269 _scale(no_scale), | |
270 _disp(in_bytes(disp)) { | |
271 } | |
272 | |
273 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
274 : _base(base), | |
275 _index(index), | |
276 _scale(scale), | |
277 _disp(in_bytes(disp)) { | |
278 assert(!index->is_valid() == (scale == Address::no_scale), | |
279 "inconsistent address"); | |
280 } | |
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281 |
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282 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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283 : _base (base), |
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284 _index(index.register_or_noreg()), |
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285 _scale(scale), |
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286 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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287 if (!index.is_register()) scale = Address::no_scale; |
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288 assert(!_index->is_valid() == (scale == Address::no_scale), |
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289 "inconsistent address"); |
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290 } |
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291 |
0 | 292 #endif // ASSERT |
293 | |
294 // accessors | |
342
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295 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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296 Register base() const { return _base; } |
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297 Register index() const { return _index; } |
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298 ScaleFactor scale() const { return _scale; } |
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299 int disp() const { return _disp; } |
0 | 300 |
301 // Convert the raw encoding form into the form expected by the constructor for | |
302 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
303 // that to noreg for the Address constructor. | |
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304 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
0 | 305 |
306 static Address make_array(ArrayAddress); | |
307 | |
308 private: | |
309 bool base_needs_rex() const { | |
310 return _base != noreg && _base->encoding() >= 8; | |
311 } | |
312 | |
313 bool index_needs_rex() const { | |
314 return _index != noreg &&_index->encoding() >= 8; | |
315 } | |
316 | |
317 relocInfo::relocType reloc() const { return _rspec.type(); } | |
318 | |
319 friend class Assembler; | |
320 friend class MacroAssembler; | |
321 friend class LIR_Assembler; // base/index/scale/disp | |
322 }; | |
323 | |
324 // | |
325 // AddressLiteral has been split out from Address because operands of this type | |
326 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
327 // the few instructions that need to deal with address literals are unique and the | |
328 // MacroAssembler does not have to implement every instruction in the Assembler | |
329 // in order to search for address literals that may need special handling depending | |
330 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
331 // directories. | |
332 // | |
333 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
334 friend class ArrayAddress; | |
335 RelocationHolder _rspec; | |
336 // Typically we use AddressLiterals we want to use their rval | |
337 // However in some situations we want the lval (effect address) of the item. | |
338 // We provide a special factory for making those lvals. | |
339 bool _is_lval; | |
340 | |
341 // If the target is far we'll need to load the ea of this to | |
342 // a register to reach it. Otherwise if near we can do rip | |
343 // relative addressing. | |
344 | |
345 address _target; | |
346 | |
347 protected: | |
348 // creation | |
349 AddressLiteral() | |
350 : _is_lval(false), | |
351 _target(NULL) | |
352 {} | |
353 | |
354 public: | |
355 | |
356 | |
357 AddressLiteral(address target, relocInfo::relocType rtype); | |
358 | |
359 AddressLiteral(address target, RelocationHolder const& rspec) | |
360 : _rspec(rspec), | |
361 _is_lval(false), | |
362 _target(target) | |
363 {} | |
364 | |
365 AddressLiteral addr() { | |
366 AddressLiteral ret = *this; | |
367 ret._is_lval = true; | |
368 return ret; | |
369 } | |
370 | |
371 | |
372 private: | |
373 | |
374 address target() { return _target; } | |
375 bool is_lval() { return _is_lval; } | |
376 | |
377 relocInfo::relocType reloc() const { return _rspec.type(); } | |
378 const RelocationHolder& rspec() const { return _rspec; } | |
379 | |
380 friend class Assembler; | |
381 friend class MacroAssembler; | |
382 friend class Address; | |
383 friend class LIR_Assembler; | |
384 }; | |
385 | |
386 // Convience classes | |
387 class RuntimeAddress: public AddressLiteral { | |
388 | |
389 public: | |
390 | |
391 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
392 | |
393 }; | |
394 | |
395 class ExternalAddress: public AddressLiteral { | |
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396 private: |
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397 static relocInfo::relocType reloc_for_target(address target) { |
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398 // Sometimes ExternalAddress is used for values which aren't |
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399 // exactly addresses, like the card table base. |
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400 // external_word_type can't be used for values in the first page |
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401 // so just skip the reloc in that case. |
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402 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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403 } |
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404 |
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405 public: |
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406 |
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407 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
0 | 408 |
409 }; | |
410 | |
411 class InternalAddress: public AddressLiteral { | |
412 | |
413 public: | |
414 | |
415 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
416 | |
417 }; | |
418 | |
419 // x86 can do array addressing as a single operation since disp can be an absolute | |
420 // address amd64 can't. We create a class that expresses the concept but does extra | |
421 // magic on amd64 to get the final result | |
422 | |
423 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
424 private: | |
425 | |
426 AddressLiteral _base; | |
427 Address _index; | |
428 | |
429 public: | |
430 | |
431 ArrayAddress() {}; | |
432 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
433 AddressLiteral base() { return _base; } | |
434 Address index() { return _index; } | |
435 | |
436 }; | |
437 | |
304 | 438 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
0 | 439 |
440 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
441 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
442 // is what you get. The Assembler is generating code into a CodeBuffer. | |
443 | |
444 class Assembler : public AbstractAssembler { | |
445 friend class AbstractAssembler; // for the non-virtual hack | |
446 friend class LIR_Assembler; // as_Address() | |
304 | 447 friend class StubGenerator; |
0 | 448 |
449 public: | |
450 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
451 zero = 0x4, | |
452 notZero = 0x5, | |
453 equal = 0x4, | |
454 notEqual = 0x5, | |
455 less = 0xc, | |
456 lessEqual = 0xe, | |
457 greater = 0xf, | |
458 greaterEqual = 0xd, | |
459 below = 0x2, | |
460 belowEqual = 0x6, | |
461 above = 0x7, | |
462 aboveEqual = 0x3, | |
463 overflow = 0x0, | |
464 noOverflow = 0x1, | |
465 carrySet = 0x2, | |
466 carryClear = 0x3, | |
467 negative = 0x8, | |
468 positive = 0x9, | |
469 parity = 0xa, | |
470 noParity = 0xb | |
471 }; | |
472 | |
473 enum Prefix { | |
474 // segment overrides | |
475 CS_segment = 0x2e, | |
476 SS_segment = 0x36, | |
477 DS_segment = 0x3e, | |
478 ES_segment = 0x26, | |
479 FS_segment = 0x64, | |
480 GS_segment = 0x65, | |
481 | |
482 REX = 0x40, | |
483 | |
484 REX_B = 0x41, | |
485 REX_X = 0x42, | |
486 REX_XB = 0x43, | |
487 REX_R = 0x44, | |
488 REX_RB = 0x45, | |
489 REX_RX = 0x46, | |
490 REX_RXB = 0x47, | |
491 | |
492 REX_W = 0x48, | |
493 | |
494 REX_WB = 0x49, | |
495 REX_WX = 0x4A, | |
496 REX_WXB = 0x4B, | |
497 REX_WR = 0x4C, | |
498 REX_WRB = 0x4D, | |
499 REX_WRX = 0x4E, | |
4759 | 500 REX_WRXB = 0x4F, |
501 | |
502 VEX_3bytes = 0xC4, | |
503 VEX_2bytes = 0xC5 | |
504 }; | |
505 | |
506 enum VexPrefix { | |
507 VEX_B = 0x20, | |
508 VEX_X = 0x40, | |
509 VEX_R = 0x80, | |
510 VEX_W = 0x80 | |
511 }; | |
512 | |
513 enum VexSimdPrefix { | |
514 VEX_SIMD_NONE = 0x0, | |
515 VEX_SIMD_66 = 0x1, | |
516 VEX_SIMD_F3 = 0x2, | |
517 VEX_SIMD_F2 = 0x3 | |
518 }; | |
519 | |
520 enum VexOpcode { | |
521 VEX_OPCODE_NONE = 0x0, | |
522 VEX_OPCODE_0F = 0x1, | |
523 VEX_OPCODE_0F_38 = 0x2, | |
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524 VEX_OPCODE_0F_3A = 0x3, |
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525 VEX_OPCODE_MASK = 0x1F |
0 | 526 }; |
527 | |
528 enum WhichOperand { | |
529 // input to locate_operand, and format code for relocations | |
304 | 530 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
0 | 531 disp32_operand = 1, // embedded 32-bit displacement or address |
532 call32_operand = 2, // embedded 32-bit self-relative displacement | |
304 | 533 #ifndef _LP64 |
0 | 534 _WhichOperand_limit = 3 |
304 | 535 #else |
536 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
537 _WhichOperand_limit = 4 | |
538 #endif | |
0 | 539 }; |
540 | |
304 | 541 |
542 | |
543 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
544 // of instructions are freely declared without the need for wrapping them an ifdef. | |
545 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
546 // In the .cpp file the implementations are wrapped so that they are dropped out | |
7951 | 547 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL |
304 | 548 // to the size it was prior to merging up the 32bit and 64bit assemblers. |
549 // | |
550 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
551 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
552 | |
553 private: | |
554 | |
555 | |
556 // 64bit prefixes | |
557 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
558 int prefixq_and_encode(int reg_enc); | |
559 | |
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560 int prefix_and_encode(int dst_enc, int src_enc) { |
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561 return prefix_and_encode(dst_enc, false, src_enc, false); |
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562 } |
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563 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); |
304 | 564 int prefixq_and_encode(int dst_enc, int src_enc); |
565 | |
566 void prefix(Register reg); | |
567 void prefix(Address adr); | |
568 void prefixq(Address adr); | |
569 | |
570 void prefix(Address adr, Register reg, bool byteinst = false); | |
4759 | 571 void prefix(Address adr, XMMRegister reg); |
304 | 572 void prefixq(Address adr, Register reg); |
4759 | 573 void prefixq(Address adr, XMMRegister reg); |
304 | 574 |
575 void prefetch_prefix(Address src); | |
576 | |
4759 | 577 void rex_prefix(Address adr, XMMRegister xreg, |
578 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
579 int rex_prefix_and_encode(int dst_enc, int src_enc, | |
580 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
581 | |
582 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, | |
583 int nds_enc, VexSimdPrefix pre, VexOpcode opc, | |
584 bool vector256); | |
585 | |
586 void vex_prefix(Address adr, int nds_enc, int xreg_enc, | |
587 VexSimdPrefix pre, VexOpcode opc, | |
588 bool vex_w, bool vector256); | |
589 | |
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590 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
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591 VexSimdPrefix pre, bool vector256 = false) { |
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592 int dst_enc = dst->encoding(); |
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593 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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594 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); |
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595 } |
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596 |
4759 | 597 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
598 VexSimdPrefix pre, VexOpcode opc, | |
599 bool vex_w, bool vector256); | |
600 | |
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601 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
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602 VexSimdPrefix pre, bool vector256 = false, |
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603 VexOpcode opc = VEX_OPCODE_0F) { |
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604 int src_enc = src->encoding(); |
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605 int dst_enc = dst->encoding(); |
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606 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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607 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); |
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608 } |
4759 | 609 |
610 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, | |
611 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
612 bool rex_w = false, bool vector256 = false); | |
613 | |
614 void simd_prefix(XMMRegister dst, Address src, | |
615 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
616 simd_prefix(dst, xnoreg, src, pre, opc); | |
617 } | |
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618 |
4759 | 619 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
620 simd_prefix(src, dst, pre); | |
621 } | |
622 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, | |
623 VexSimdPrefix pre) { | |
624 bool rex_w = true; | |
625 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); | |
626 } | |
627 | |
628 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, | |
629 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
630 bool rex_w = false, bool vector256 = false); | |
631 | |
632 // Move/convert 32-bit integer value. | |
633 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, | |
634 VexSimdPrefix pre) { | |
635 // It is OK to cast from Register to XMMRegister to pass argument here | |
636 // since only encoding is used in simd_prefix_and_encode() and number of | |
637 // Gen and Xmm registers are the same. | |
638 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); | |
639 } | |
640 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
641 return simd_prefix_and_encode(dst, xnoreg, src, pre); | |
642 } | |
643 int simd_prefix_and_encode(Register dst, XMMRegister src, | |
644 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
645 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); | |
646 } | |
647 | |
648 // Move/convert 64-bit integer value. | |
649 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, | |
650 VexSimdPrefix pre) { | |
651 bool rex_w = true; | |
652 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); | |
653 } | |
654 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
655 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); | |
656 } | |
657 int simd_prefix_and_encode_q(Register dst, XMMRegister src, | |
658 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
659 bool rex_w = true; | |
660 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); | |
661 } | |
662 | |
304 | 663 // Helper functions for groups of instructions |
664 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
665 | |
666 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
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667 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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668 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
304 | 669 void emit_arith(int op1, int op2, Register dst, Register src); |
670 | |
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671 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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672 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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673 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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674 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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675 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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676 Address src, VexSimdPrefix pre, bool vector256); |
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677 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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678 XMMRegister src, VexSimdPrefix pre, bool vector256); |
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679 |
304 | 680 void emit_operand(Register reg, |
681 Register base, Register index, Address::ScaleFactor scale, | |
682 int disp, | |
683 RelocationHolder const& rspec, | |
684 int rip_relative_correction = 0); | |
685 | |
686 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
687 | |
688 // operands that only take the original 32bit registers | |
689 void emit_operand32(Register reg, Address adr); | |
690 | |
691 void emit_operand(XMMRegister reg, | |
692 Register base, Register index, Address::ScaleFactor scale, | |
693 int disp, | |
694 RelocationHolder const& rspec); | |
695 | |
696 void emit_operand(XMMRegister reg, Address adr); | |
697 | |
698 void emit_operand(MMXRegister reg, Address adr); | |
699 | |
700 // workaround gcc (3.2.1-7) bug | |
701 void emit_operand(Address adr, MMXRegister reg); | |
702 | |
703 | |
704 // Immediate-to-memory forms | |
705 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
706 | |
707 void emit_farith(int b1, int b2, int i); | |
708 | |
709 | |
710 protected: | |
711 #ifdef ASSERT | |
712 void check_relocation(RelocationHolder const& rspec, int format); | |
713 #endif | |
714 | |
715 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
716 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
717 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
718 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
719 | |
720 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
721 | |
722 // These are all easily abused and hence protected | |
723 | |
724 // 32BIT ONLY SECTION | |
725 #ifndef _LP64 | |
726 // Make these disappear in 64bit mode since they would never be correct | |
727 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
728 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
729 | |
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730 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
304 | 731 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
732 | |
733 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
734 #else | |
735 // 64BIT ONLY SECTION | |
736 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
642
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737 |
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738 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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739 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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740 |
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741 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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742 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
304 | 743 #endif // _LP64 |
744 | |
745 // These are unique in that we are ensured by the caller that the 32bit | |
746 // relative in these instructions will always be able to reach the potentially | |
747 // 64bit address described by entry. Since they can take a 64bit address they | |
748 // don't have the 32 suffix like the other instructions in this class. | |
749 | |
750 void call_literal(address entry, RelocationHolder const& rspec); | |
751 void jmp_literal(address entry, RelocationHolder const& rspec); | |
752 | |
753 // Avoid using directly section | |
754 // Instructions in this section are actually usable by anyone without danger | |
755 // of failure but have performance issues that are addressed my enhanced | |
756 // instructions which will do the proper thing base on the particular cpu. | |
757 // We protect them because we don't trust you... | |
758 | |
759 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
760 // could cause a partial flag stall since they don't set CF flag. | |
761 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
762 // which call inc() & dec() or add() & sub() in accordance with | |
763 // the product flag UseIncDec value. | |
764 | |
765 void decl(Register dst); | |
766 void decl(Address dst); | |
767 void decq(Register dst); | |
768 void decq(Address dst); | |
769 | |
770 void incl(Register dst); | |
771 void incl(Address dst); | |
772 void incq(Register dst); | |
773 void incq(Address dst); | |
774 | |
775 // New cpus require use of movsd and movss to avoid partial register stall | |
776 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
777 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
778 | |
779 // Move Scalar Single-Precision Floating-Point Values | |
780 void movss(XMMRegister dst, Address src); | |
781 void movss(XMMRegister dst, XMMRegister src); | |
782 void movss(Address dst, XMMRegister src); | |
783 | |
784 // Move Scalar Double-Precision Floating-Point Values | |
785 void movsd(XMMRegister dst, Address src); | |
786 void movsd(XMMRegister dst, XMMRegister src); | |
787 void movsd(Address dst, XMMRegister src); | |
788 void movlpd(XMMRegister dst, Address src); | |
789 | |
790 // New cpus require use of movaps and movapd to avoid partial register stall | |
791 // when moving between registers. | |
792 void movaps(XMMRegister dst, XMMRegister src); | |
793 void movapd(XMMRegister dst, XMMRegister src); | |
794 | |
795 // End avoid using directly | |
796 | |
797 | |
798 // Instruction prefixes | |
799 void prefix(Prefix p); | |
800 | |
0 | 801 public: |
802 | |
803 // Creation | |
804 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
805 | |
806 // Decoding | |
807 static address locate_operand(address inst, WhichOperand which); | |
808 static address locate_next_instruction(address inst); | |
809 | |
304 | 810 // Utilities |
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811 static bool is_polling_page_far() NOT_LP64({ return false;}); |
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812 |
304 | 813 // Generic instructions |
814 // Does 32bit or 64bit as needed for the platform. In some sense these | |
815 // belong in macro assembler but there is no need for both varieties to exist | |
816 | |
817 void lea(Register dst, Address src); | |
818 | |
819 void mov(Register dst, Register src); | |
820 | |
821 void pusha(); | |
822 void popa(); | |
823 | |
824 void pushf(); | |
825 void popf(); | |
826 | |
827 void push(int32_t imm32); | |
828 | |
829 void push(Register src); | |
830 | |
831 void pop(Register dst); | |
832 | |
833 // These are dummies to prevent surprise implicit conversions to Register | |
834 void push(void* v); | |
835 void pop(void* v); | |
836 | |
837 // These do register sized moves/scans | |
838 void rep_mov(); | |
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839 void rep_stos(); |
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840 void rep_stosb(); |
304 | 841 void repne_scan(); |
842 #ifdef _LP64 | |
843 void repne_scanl(); | |
844 #endif | |
845 | |
846 // Vanilla instructions in lexical order | |
847 | |
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848 void adcl(Address dst, int32_t imm32); |
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849 void adcl(Address dst, Register src); |
304 | 850 void adcl(Register dst, int32_t imm32); |
0 | 851 void adcl(Register dst, Address src); |
852 void adcl(Register dst, Register src); | |
853 | |
304 | 854 void adcq(Register dst, int32_t imm32); |
855 void adcq(Register dst, Address src); | |
856 void adcq(Register dst, Register src); | |
857 | |
858 void addl(Address dst, int32_t imm32); | |
0 | 859 void addl(Address dst, Register src); |
304 | 860 void addl(Register dst, int32_t imm32); |
0 | 861 void addl(Register dst, Address src); |
862 void addl(Register dst, Register src); | |
863 | |
304 | 864 void addq(Address dst, int32_t imm32); |
865 void addq(Address dst, Register src); | |
866 void addq(Register dst, int32_t imm32); | |
867 void addq(Register dst, Address src); | |
868 void addq(Register dst, Register src); | |
869 | |
0 | 870 void addr_nop_4(); |
871 void addr_nop_5(); | |
872 void addr_nop_7(); | |
873 void addr_nop_8(); | |
874 | |
304 | 875 // Add Scalar Double-Precision Floating-Point Values |
876 void addsd(XMMRegister dst, Address src); | |
877 void addsd(XMMRegister dst, XMMRegister src); | |
878 | |
879 // Add Scalar Single-Precision Floating-Point Values | |
880 void addss(XMMRegister dst, Address src); | |
881 void addss(XMMRegister dst, XMMRegister src); | |
882 | |
6894 | 883 // AES instructions |
884 void aesdec(XMMRegister dst, Address src); | |
885 void aesdec(XMMRegister dst, XMMRegister src); | |
886 void aesdeclast(XMMRegister dst, Address src); | |
887 void aesdeclast(XMMRegister dst, XMMRegister src); | |
888 void aesenc(XMMRegister dst, Address src); | |
889 void aesenc(XMMRegister dst, XMMRegister src); | |
890 void aesenclast(XMMRegister dst, Address src); | |
891 void aesenclast(XMMRegister dst, XMMRegister src); | |
892 | |
893 | |
4759 | 894 void andl(Address dst, int32_t imm32); |
304 | 895 void andl(Register dst, int32_t imm32); |
896 void andl(Register dst, Address src); | |
897 void andl(Register dst, Register src); | |
898 | |
3457 | 899 void andq(Address dst, int32_t imm32); |
304 | 900 void andq(Register dst, int32_t imm32); |
901 void andq(Register dst, Address src); | |
902 void andq(Register dst, Register src); | |
903 | |
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904 void bsfl(Register dst, Register src); |
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905 void bsrl(Register dst, Register src); |
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906 |
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907 #ifdef _LP64 |
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908 void bsfq(Register dst, Register src); |
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909 void bsrq(Register dst, Register src); |
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910 #endif |
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911 |
304 | 912 void bswapl(Register reg); |
913 | |
914 void bswapq(Register reg); | |
915 | |
0 | 916 void call(Label& L, relocInfo::relocType rtype); |
917 void call(Register reg); // push pc; pc <- reg | |
918 void call(Address adr); // push pc; pc <- adr | |
919 | |
304 | 920 void cdql(); |
921 | |
922 void cdqq(); | |
923 | |
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924 void cld(); |
304 | 925 |
926 void clflush(Address adr); | |
927 | |
928 void cmovl(Condition cc, Register dst, Register src); | |
929 void cmovl(Condition cc, Register dst, Address src); | |
930 | |
931 void cmovq(Condition cc, Register dst, Register src); | |
932 void cmovq(Condition cc, Register dst, Address src); | |
933 | |
934 | |
935 void cmpb(Address dst, int imm8); | |
936 | |
937 void cmpl(Address dst, int32_t imm32); | |
938 | |
939 void cmpl(Register dst, int32_t imm32); | |
940 void cmpl(Register dst, Register src); | |
941 void cmpl(Register dst, Address src); | |
942 | |
943 void cmpq(Address dst, int32_t imm32); | |
944 void cmpq(Address dst, Register src); | |
945 | |
946 void cmpq(Register dst, int32_t imm32); | |
947 void cmpq(Register dst, Register src); | |
948 void cmpq(Register dst, Address src); | |
949 | |
950 // these are dummies used to catch attempting to convert NULL to Register | |
951 void cmpl(Register dst, void* junk); // dummy | |
952 void cmpq(Register dst, void* junk); // dummy | |
953 | |
954 void cmpw(Address dst, int imm16); | |
955 | |
956 void cmpxchg8 (Address adr); | |
957 | |
958 void cmpxchgl(Register reg, Address adr); | |
959 | |
960 void cmpxchgq(Register reg, Address adr); | |
961 | |
962 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
963 void comisd(XMMRegister dst, Address src); | |
4759 | 964 void comisd(XMMRegister dst, XMMRegister src); |
304 | 965 |
966 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
967 void comiss(XMMRegister dst, Address src); | |
4759 | 968 void comiss(XMMRegister dst, XMMRegister src); |
304 | 969 |
970 // Identify processor type and features | |
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971 void cpuid(); |
304 | 972 |
973 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
974 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
4759 | 975 void cvtsd2ss(XMMRegister dst, Address src); |
304 | 976 |
977 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
978 void cvtsi2sdl(XMMRegister dst, Register src); | |
4759 | 979 void cvtsi2sdl(XMMRegister dst, Address src); |
304 | 980 void cvtsi2sdq(XMMRegister dst, Register src); |
4759 | 981 void cvtsi2sdq(XMMRegister dst, Address src); |
304 | 982 |
983 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
984 void cvtsi2ssl(XMMRegister dst, Register src); | |
4759 | 985 void cvtsi2ssl(XMMRegister dst, Address src); |
304 | 986 void cvtsi2ssq(XMMRegister dst, Register src); |
4759 | 987 void cvtsi2ssq(XMMRegister dst, Address src); |
304 | 988 |
989 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
990 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
991 | |
992 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
993 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
994 | |
995 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
996 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
4759 | 997 void cvtss2sd(XMMRegister dst, Address src); |
304 | 998 |
999 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
1000 void cvttsd2sil(Register dst, Address src); | |
1001 void cvttsd2sil(Register dst, XMMRegister src); | |
1002 void cvttsd2siq(Register dst, XMMRegister src); | |
1003 | |
1004 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
1005 void cvttss2sil(Register dst, XMMRegister src); | |
1006 void cvttss2siq(Register dst, XMMRegister src); | |
1007 | |
1008 // Divide Scalar Double-Precision Floating-Point Values | |
1009 void divsd(XMMRegister dst, Address src); | |
1010 void divsd(XMMRegister dst, XMMRegister src); | |
1011 | |
1012 // Divide Scalar Single-Precision Floating-Point Values | |
1013 void divss(XMMRegister dst, Address src); | |
1014 void divss(XMMRegister dst, XMMRegister src); | |
1015 | |
1016 void emms(); | |
1017 | |
1018 void fabs(); | |
1019 | |
1020 void fadd(int i); | |
1021 | |
1022 void fadd_d(Address src); | |
1023 void fadd_s(Address src); | |
1024 | |
1025 // "Alternate" versions of x87 instructions place result down in FPU | |
1026 // stack instead of on TOS | |
1027 | |
1028 void fadda(int i); // "alternate" fadd | |
1029 void faddp(int i = 1); | |
1030 | |
1031 void fchs(); | |
1032 | |
1033 void fcom(int i); | |
1034 | |
1035 void fcomp(int i = 1); | |
1036 void fcomp_d(Address src); | |
1037 void fcomp_s(Address src); | |
1038 | |
1039 void fcompp(); | |
1040 | |
1041 void fcos(); | |
1042 | |
1043 void fdecstp(); | |
1044 | |
1045 void fdiv(int i); | |
1046 void fdiv_d(Address src); | |
1047 void fdivr_s(Address src); | |
1048 void fdiva(int i); // "alternate" fdiv | |
1049 void fdivp(int i = 1); | |
1050 | |
1051 void fdivr(int i); | |
1052 void fdivr_d(Address src); | |
1053 void fdiv_s(Address src); | |
1054 | |
1055 void fdivra(int i); // "alternate" reversed fdiv | |
1056 | |
1057 void fdivrp(int i = 1); | |
1058 | |
1059 void ffree(int i = 0); | |
1060 | |
1061 void fild_d(Address adr); | |
1062 void fild_s(Address adr); | |
1063 | |
1064 void fincstp(); | |
1065 | |
1066 void finit(); | |
1067 | |
1068 void fist_s (Address adr); | |
1069 void fistp_d(Address adr); | |
1070 void fistp_s(Address adr); | |
1071 | |
1072 void fld1(); | |
1073 | |
1074 void fld_d(Address adr); | |
1075 void fld_s(Address adr); | |
1076 void fld_s(int index); | |
1077 void fld_x(Address adr); // extended-precision (80-bit) format | |
1078 | |
1079 void fldcw(Address src); | |
1080 | |
1081 void fldenv(Address src); | |
1082 | |
1083 void fldlg2(); | |
1084 | |
1085 void fldln2(); | |
1086 | |
1087 void fldz(); | |
1088 | |
1089 void flog(); | |
1090 void flog10(); | |
1091 | |
1092 void fmul(int i); | |
1093 | |
1094 void fmul_d(Address src); | |
1095 void fmul_s(Address src); | |
1096 | |
1097 void fmula(int i); // "alternate" fmul | |
1098 | |
1099 void fmulp(int i = 1); | |
1100 | |
1101 void fnsave(Address dst); | |
1102 | |
1103 void fnstcw(Address src); | |
1104 | |
1105 void fnstsw_ax(); | |
1106 | |
1107 void fprem(); | |
1108 void fprem1(); | |
1109 | |
1110 void frstor(Address src); | |
1111 | |
1112 void fsin(); | |
1113 | |
1114 void fsqrt(); | |
1115 | |
1116 void fst_d(Address adr); | |
1117 void fst_s(Address adr); | |
1118 | |
1119 void fstp_d(Address adr); | |
1120 void fstp_d(int index); | |
1121 void fstp_s(Address adr); | |
1122 void fstp_x(Address adr); // extended-precision (80-bit) format | |
1123 | |
1124 void fsub(int i); | |
1125 void fsub_d(Address src); | |
1126 void fsub_s(Address src); | |
1127 | |
1128 void fsuba(int i); // "alternate" fsub | |
1129 | |
1130 void fsubp(int i = 1); | |
1131 | |
1132 void fsubr(int i); | |
1133 void fsubr_d(Address src); | |
1134 void fsubr_s(Address src); | |
1135 | |
1136 void fsubra(int i); // "alternate" reversed fsub | |
1137 | |
1138 void fsubrp(int i = 1); | |
1139 | |
1140 void ftan(); | |
1141 | |
1142 void ftst(); | |
1143 | |
1144 void fucomi(int i = 1); | |
1145 void fucomip(int i = 1); | |
1146 | |
1147 void fwait(); | |
1148 | |
1149 void fxch(int i = 1); | |
1150 | |
1151 void fxrstor(Address src); | |
1152 | |
1153 void fxsave(Address dst); | |
1154 | |
1155 void fyl2x(); | |
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1156 void frndint(); |
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1157 void f2xm1(); |
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1158 void fldl2e(); |
304 | 1159 |
1160 void hlt(); | |
1161 | |
1162 void idivl(Register src); | |
1920 | 1163 void divl(Register src); // Unsigned division |
304 | 1164 |
1165 void idivq(Register src); | |
1166 | |
1167 void imull(Register dst, Register src); | |
1168 void imull(Register dst, Register src, int value); | |
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1169 void imull(Register dst, Address src); |
304 | 1170 |
1171 void imulq(Register dst, Register src); | |
1172 void imulq(Register dst, Register src, int value); | |
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1173 #ifdef _LP64 |
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1174 void imulq(Register dst, Address src); |
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1175 #endif |
304 | 1176 |
0 | 1177 |
1178 // jcc is the generic conditional branch generator to run- | |
1179 // time routines, jcc is used for branches to labels. jcc | |
1180 // takes a branch opcode (cc) and a label (L) and generates | |
1181 // either a backward branch or a forward branch and links it | |
1182 // to the label fixup chain. Usage: | |
1183 // | |
1184 // Label L; // unbound label | |
1185 // jcc(cc, L); // forward branch to unbound label | |
1186 // bind(L); // bind label to the current pc | |
1187 // jcc(cc, L); // backward branch to bound label | |
1188 // bind(L); // illegal: a label may be bound only once | |
1189 // | |
1190 // Note: The same Label can be used for forward and backward branches | |
1191 // but it may be bound only once. | |
1192 | |
3851 | 1193 void jcc(Condition cc, Label& L, bool maybe_short = true); |
0 | 1194 |
1195 // Conditional jump to a 8-bit offset to L. | |
1196 // WARNING: be very careful using this for forward jumps. If the label is | |
1197 // not bound within an 8-bit offset of this instruction, a run-time error | |
1198 // will occur. | |
1199 void jccb(Condition cc, Label& L); | |
1200 | |
304 | 1201 void jmp(Address entry); // pc <- entry |
1202 | |
1203 // Label operations & relative jumps (PPUM Appendix D) | |
3851 | 1204 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
304 | 1205 |
1206 void jmp(Register entry); // pc <- entry | |
1207 | |
1208 // Unconditional 8-bit offset jump to L. | |
1209 // WARNING: be very careful using this for forward jumps. If the label is | |
1210 // not bound within an 8-bit offset of this instruction, a run-time error | |
1211 // will occur. | |
1212 void jmpb(Label& L); | |
1213 | |
1214 void ldmxcsr( Address src ); | |
1215 | |
1216 void leal(Register dst, Address src); | |
1217 | |
1218 void leaq(Register dst, Address src); | |
1219 | |
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1220 void lfence(); |
304 | 1221 |
1222 void lock(); | |
1223 | |
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1224 void lzcntl(Register dst, Register src); |
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1225 |
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1226 #ifdef _LP64 |
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1227 void lzcntq(Register dst, Register src); |
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1228 #endif |
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1229 |
304 | 1230 enum Membar_mask_bits { |
1231 StoreStore = 1 << 3, | |
1232 LoadStore = 1 << 2, | |
1233 StoreLoad = 1 << 1, | |
1234 LoadLoad = 1 << 0 | |
1235 }; | |
1236 | |
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1237 // Serializes memory and blows flags |
304 | 1238 void membar(Membar_mask_bits order_constraint) { |
671
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1239 if (os::is_MP()) { |
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1240 // We only have to handle StoreLoad |
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1241 if (order_constraint & StoreLoad) { |
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1242 // All usable chips support "locked" instructions which suffice |
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1243 // as barriers, and are much faster than the alternative of |
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1244 // using cpuid instruction. We use here a locked add [esp],0. |
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1245 // This is conveniently otherwise a no-op except for blowing |
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1246 // flags. |
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1247 // Any change to this code may need to revisit other places in |
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1248 // the code where this idiom is used, in particular the |
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1249 // orderAccess code. |
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1250 lock(); |
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1251 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1252 } |
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1253 } |
304 | 1254 } |
1255 | |
1256 void mfence(); | |
1257 | |
1258 // Moves | |
1259 | |
1260 void mov64(Register dst, int64_t imm64); | |
1261 | |
1262 void movb(Address dst, Register src); | |
1263 void movb(Address dst, int imm8); | |
1264 void movb(Register dst, Address src); | |
1265 | |
1266 void movdl(XMMRegister dst, Register src); | |
1267 void movdl(Register dst, XMMRegister src); | |
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1268 void movdl(XMMRegister dst, Address src); |
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1269 void movdl(Address dst, XMMRegister src); |
304 | 1270 |
1271 // Move Double Quadword | |
1272 void movdq(XMMRegister dst, Register src); | |
1273 void movdq(Register dst, XMMRegister src); | |
1274 | |
1275 // Move Aligned Double Quadword | |
1276 void movdqa(XMMRegister dst, XMMRegister src); | |
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1277 void movdqa(XMMRegister dst, Address src); |
304 | 1278 |
405 | 1279 // Move Unaligned Double Quadword |
1280 void movdqu(Address dst, XMMRegister src); | |
1281 void movdqu(XMMRegister dst, Address src); | |
1282 void movdqu(XMMRegister dst, XMMRegister src); | |
1283 | |
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1284 // Move Unaligned 256bit Vector |
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1285 void vmovdqu(Address dst, XMMRegister src); |
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1286 void vmovdqu(XMMRegister dst, Address src); |
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1287 void vmovdqu(XMMRegister dst, XMMRegister src); |
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1288 |
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1289 // Move lower 64bit to high 64bit in 128bit register |
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1290 void movlhps(XMMRegister dst, XMMRegister src); |
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1291 |
304 | 1292 void movl(Register dst, int32_t imm32); |
1293 void movl(Address dst, int32_t imm32); | |
1294 void movl(Register dst, Register src); | |
1295 void movl(Register dst, Address src); | |
1296 void movl(Address dst, Register src); | |
1297 | |
1298 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
1299 // by giving the compiler two choices it can't resolve | |
1300 | |
1301 void movl(Address dst, void* junk); | |
1302 void movl(Register dst, void* junk); | |
1303 | |
1304 #ifdef _LP64 | |
1305 void movq(Register dst, Register src); | |
1306 void movq(Register dst, Address src); | |
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1307 void movq(Address dst, Register src); |
304 | 1308 #endif |
1309 | |
1310 void movq(Address dst, MMXRegister src ); | |
1311 void movq(MMXRegister dst, Address src ); | |
1312 | |
1313 #ifdef _LP64 | |
1314 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
1315 // by giving the compiler two choices it can't resolve | |
1316 | |
1317 void movq(Address dst, void* dummy); | |
1318 void movq(Register dst, void* dummy); | |
1319 #endif | |
1320 | |
1321 // Move Quadword | |
1322 void movq(Address dst, XMMRegister src); | |
1323 void movq(XMMRegister dst, Address src); | |
1324 | |
1325 void movsbl(Register dst, Address src); | |
1326 void movsbl(Register dst, Register src); | |
1327 | |
1328 #ifdef _LP64 | |
624 | 1329 void movsbq(Register dst, Address src); |
1330 void movsbq(Register dst, Register src); | |
1331 | |
304 | 1332 // Move signed 32bit immediate to 64bit extending sign |
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1333 void movslq(Address dst, int32_t imm64); |
304 | 1334 void movslq(Register dst, int32_t imm64); |
1335 | |
1336 void movslq(Register dst, Address src); | |
1337 void movslq(Register dst, Register src); | |
1338 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
1339 #endif | |
1340 | |
1341 void movswl(Register dst, Address src); | |
1342 void movswl(Register dst, Register src); | |
1343 | |
624 | 1344 #ifdef _LP64 |
1345 void movswq(Register dst, Address src); | |
1346 void movswq(Register dst, Register src); | |
1347 #endif | |
1348 | |
304 | 1349 void movw(Address dst, int imm16); |
1350 void movw(Register dst, Address src); | |
1351 void movw(Address dst, Register src); | |
1352 | |
1353 void movzbl(Register dst, Address src); | |
1354 void movzbl(Register dst, Register src); | |
1355 | |
624 | 1356 #ifdef _LP64 |
1357 void movzbq(Register dst, Address src); | |
1358 void movzbq(Register dst, Register src); | |
1359 #endif | |
1360 | |
304 | 1361 void movzwl(Register dst, Address src); |
1362 void movzwl(Register dst, Register src); | |
1363 | |
624 | 1364 #ifdef _LP64 |
1365 void movzwq(Register dst, Address src); | |
1366 void movzwq(Register dst, Register src); | |
1367 #endif | |
1368 | |
304 | 1369 void mull(Address src); |
1370 void mull(Register src); | |
1371 | |
1372 // Multiply Scalar Double-Precision Floating-Point Values | |
1373 void mulsd(XMMRegister dst, Address src); | |
1374 void mulsd(XMMRegister dst, XMMRegister src); | |
1375 | |
1376 // Multiply Scalar Single-Precision Floating-Point Values | |
1377 void mulss(XMMRegister dst, Address src); | |
1378 void mulss(XMMRegister dst, XMMRegister src); | |
1379 | |
1380 void negl(Register dst); | |
1381 | |
1382 #ifdef _LP64 | |
1383 void negq(Register dst); | |
1384 #endif | |
1385 | |
1386 void nop(int i = 1); | |
1387 | |
1388 void notl(Register dst); | |
1389 | |
1390 #ifdef _LP64 | |
1391 void notq(Register dst); | |
1392 #endif | |
1393 | |
1394 void orl(Address dst, int32_t imm32); | |
1395 void orl(Register dst, int32_t imm32); | |
1396 void orl(Register dst, Address src); | |
1397 void orl(Register dst, Register src); | |
1398 | |
1399 void orq(Address dst, int32_t imm32); | |
1400 void orq(Register dst, int32_t imm32); | |
1401 void orq(Register dst, Address src); | |
1402 void orq(Register dst, Register src); | |
1403 | |
4759 | 1404 // Pack with unsigned saturation |
1405 void packuswb(XMMRegister dst, XMMRegister src); | |
1406 void packuswb(XMMRegister dst, Address src); | |
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1407 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1408 |
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1409 // Pemutation of 64bit words |
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1410 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); |
4759 | 1411 |
681 | 1412 // SSE4.2 string instructions |
1413 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
1414 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
1415 | |
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1416 // SSE 4.1 extract |
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1417 void pextrd(Register dst, XMMRegister src, int imm8); |
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1418 void pextrq(Register dst, XMMRegister src, int imm8); |
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1419 |
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1420 // SSE 4.1 insert |
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1421 void pinsrd(XMMRegister dst, Register src, int imm8); |
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1422 void pinsrq(XMMRegister dst, Register src, int imm8); |
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1423 |
4759 | 1424 // SSE4.1 packed move |
1425 void pmovzxbw(XMMRegister dst, XMMRegister src); | |
1426 void pmovzxbw(XMMRegister dst, Address src); | |
1427 | |
1060 | 1428 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1429 void popl(Address dst); |
1060 | 1430 #endif |
304 | 1431 |
1432 #ifdef _LP64 | |
1433 void popq(Address dst); | |
1434 #endif | |
1435 | |
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1436 void popcntl(Register dst, Address src); |
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1437 void popcntl(Register dst, Register src); |
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1438 |
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1439 #ifdef _LP64 |
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1440 void popcntq(Register dst, Address src); |
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1441 void popcntq(Register dst, Register src); |
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1442 #endif |
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1443 |
304 | 1444 // Prefetches (SSE, SSE2, 3DNOW only) |
1445 | |
1446 void prefetchnta(Address src); | |
1447 void prefetchr(Address src); | |
1448 void prefetcht0(Address src); | |
1449 void prefetcht1(Address src); | |
1450 void prefetcht2(Address src); | |
1451 void prefetchw(Address src); | |
1452 | |
6894 | 1453 // Shuffle Bytes |
1454 void pshufb(XMMRegister dst, XMMRegister src); | |
1455 void pshufb(XMMRegister dst, Address src); | |
1456 | |
304 | 1457 // Shuffle Packed Doublewords |
1458 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
1459 void pshufd(XMMRegister dst, Address src, int mode); | |
1460 | |
1461 // Shuffle Packed Low Words | |
1462 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
1463 void pshuflw(XMMRegister dst, Address src, int mode); | |
1464 | |
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1465 // Shift Right by bytes Logical DoubleQuadword Immediate |
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1466 void psrldq(XMMRegister dst, int shift); |
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1467 |
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1468 // Logical Compare 128bit |
681 | 1469 void ptest(XMMRegister dst, XMMRegister src); |
1470 void ptest(XMMRegister dst, Address src); | |
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1471 // Logical Compare 256bit |
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1472 void vptest(XMMRegister dst, XMMRegister src); |
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1473 void vptest(XMMRegister dst, Address src); |
681 | 1474 |
304 | 1475 // Interleave Low Bytes |
1476 void punpcklbw(XMMRegister dst, XMMRegister src); | |
4759 | 1477 void punpcklbw(XMMRegister dst, Address src); |
1478 | |
1479 // Interleave Low Doublewords | |
1480 void punpckldq(XMMRegister dst, XMMRegister src); | |
1481 void punpckldq(XMMRegister dst, Address src); | |
304 | 1482 |
6225 | 1483 // Interleave Low Quadwords |
1484 void punpcklqdq(XMMRegister dst, XMMRegister src); | |
1485 | |
1060 | 1486 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1487 void pushl(Address src); |
1060 | 1488 #endif |
304 | 1489 |
1490 void pushq(Address src); | |
1491 | |
1492 void rcll(Register dst, int imm8); | |
1493 | |
1494 void rclq(Register dst, int imm8); | |
1495 | |
1496 void ret(int imm16); | |
0 | 1497 |
1498 void sahf(); | |
1499 | |
304 | 1500 void sarl(Register dst, int imm8); |
1501 void sarl(Register dst); | |
1502 | |
1503 void sarq(Register dst, int imm8); | |
1504 void sarq(Register dst); | |
1505 | |
1506 void sbbl(Address dst, int32_t imm32); | |
1507 void sbbl(Register dst, int32_t imm32); | |
1508 void sbbl(Register dst, Address src); | |
1509 void sbbl(Register dst, Register src); | |
1510 | |
1511 void sbbq(Address dst, int32_t imm32); | |
1512 void sbbq(Register dst, int32_t imm32); | |
1513 void sbbq(Register dst, Address src); | |
1514 void sbbq(Register dst, Register src); | |
1515 | |
1516 void setb(Condition cc, Register dst); | |
1517 | |
1518 void shldl(Register dst, Register src); | |
1519 | |
1520 void shll(Register dst, int imm8); | |
1521 void shll(Register dst); | |
1522 | |
1523 void shlq(Register dst, int imm8); | |
1524 void shlq(Register dst); | |
1525 | |
1526 void shrdl(Register dst, Register src); | |
1527 | |
1528 void shrl(Register dst, int imm8); | |
1529 void shrl(Register dst); | |
1530 | |
1531 void shrq(Register dst, int imm8); | |
1532 void shrq(Register dst); | |
1533 | |
1534 void smovl(); // QQQ generic? | |
1535 | |
1536 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
1537 void sqrtsd(XMMRegister dst, Address src); | |
1538 void sqrtsd(XMMRegister dst, XMMRegister src); | |
1539 | |
2008 | 1540 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
1541 void sqrtss(XMMRegister dst, Address src); | |
1542 void sqrtss(XMMRegister dst, XMMRegister src); | |
1543 | |
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1544 void std(); |
304 | 1545 |
1546 void stmxcsr( Address dst ); | |
1547 | |
1548 void subl(Address dst, int32_t imm32); | |
1549 void subl(Address dst, Register src); | |
1550 void subl(Register dst, int32_t imm32); | |
1551 void subl(Register dst, Address src); | |
1552 void subl(Register dst, Register src); | |
1553 | |
1554 void subq(Address dst, int32_t imm32); | |
1555 void subq(Address dst, Register src); | |
1556 void subq(Register dst, int32_t imm32); | |
1557 void subq(Register dst, Address src); | |
1558 void subq(Register dst, Register src); | |
1559 | |
4947
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1560 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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1561 void subl_imm32(Register dst, int32_t imm32); |
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1562 void subq_imm32(Register dst, int32_t imm32); |
304 | 1563 |
1564 // Subtract Scalar Double-Precision Floating-Point Values | |
1565 void subsd(XMMRegister dst, Address src); | |
0 | 1566 void subsd(XMMRegister dst, XMMRegister src); |
1567 | |
304 | 1568 // Subtract Scalar Single-Precision Floating-Point Values |
1569 void subss(XMMRegister dst, Address src); | |
1570 void subss(XMMRegister dst, XMMRegister src); | |
1571 | |
1572 void testb(Register dst, int imm8); | |
1573 | |
1574 void testl(Register dst, int32_t imm32); | |
1575 void testl(Register dst, Register src); | |
1576 void testl(Register dst, Address src); | |
1577 | |
1578 void testq(Register dst, int32_t imm32); | |
1579 void testq(Register dst, Register src); | |
1580 | |
1581 | |
1582 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1583 void ucomisd(XMMRegister dst, Address src); | |
0 | 1584 void ucomisd(XMMRegister dst, XMMRegister src); |
1585 | |
304 | 1586 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1587 void ucomiss(XMMRegister dst, Address src); | |
1588 void ucomiss(XMMRegister dst, XMMRegister src); | |
1589 | |
1590 void xaddl(Address dst, Register src); | |
1591 | |
1592 void xaddq(Address dst, Register src); | |
1593 | |
1594 void xchgl(Register reg, Address adr); | |
1595 void xchgl(Register dst, Register src); | |
1596 | |
1597 void xchgq(Register reg, Address adr); | |
1598 void xchgq(Register dst, Register src); | |
1599 | |
4759 | 1600 // Get Value of Extended Control Register |
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1601 void xgetbv(); |
4759 | 1602 |
304 | 1603 void xorl(Register dst, int32_t imm32); |
1604 void xorl(Register dst, Address src); | |
1605 void xorl(Register dst, Register src); | |
1606 | |
1607 void xorq(Register dst, Address src); | |
1608 void xorq(Register dst, Register src); | |
1609 | |
1610 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
4759 | 1611 |
6225 | 1612 // AVX 3-operands scalar instructions (encoded with VEX prefix) |
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1613 |
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1614 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
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1615 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1616 void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
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1617 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1618 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
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1619 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1620 void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
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1621 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1622 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
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1623 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1624 void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
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1625 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1626 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
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1627 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1628 void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
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1629 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1630 |
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1631 |
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1632 //====================VECTOR ARITHMETIC===================================== |
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1633 |
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1634 // Add Packed Floating-Point Values |
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1635 void addpd(XMMRegister dst, XMMRegister src); |
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1636 void addps(XMMRegister dst, XMMRegister src); |
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1637 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1638 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1639 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1640 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1641 |
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|
1642 // Subtract Packed Floating-Point Values |
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1643 void subpd(XMMRegister dst, XMMRegister src); |
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1644 void subps(XMMRegister dst, XMMRegister src); |
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1645 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1646 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1647 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1648 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1649 |
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|
1650 // Multiply Packed Floating-Point Values |
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1651 void mulpd(XMMRegister dst, XMMRegister src); |
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|
1652 void mulps(XMMRegister dst, XMMRegister src); |
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|
1653 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1654 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1655 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1656 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1657 |
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6340864: Implement vectorization optimizations in hotspot-server
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|
1658 // Divide Packed Floating-Point Values |
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|
1659 void divpd(XMMRegister dst, XMMRegister src); |
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6340864: Implement vectorization optimizations in hotspot-server
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|
1660 void divps(XMMRegister dst, XMMRegister src); |
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|
1661 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1662 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1663 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1664 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1665 |
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|
1666 // Bitwise Logical AND of Packed Floating-Point Values |
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|
1667 void andpd(XMMRegister dst, XMMRegister src); |
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|
1668 void andps(XMMRegister dst, XMMRegister src); |
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1669 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1670 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1671 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1672 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1673 |
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1674 // Bitwise Logical XOR of Packed Floating-Point Values |
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|
1675 void xorpd(XMMRegister dst, XMMRegister src); |
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|
1676 void xorps(XMMRegister dst, XMMRegister src); |
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1677 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1678 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6614
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1679 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1680 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1681 |
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|
1682 // Add packed integers |
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1683 void paddb(XMMRegister dst, XMMRegister src); |
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|
1684 void paddw(XMMRegister dst, XMMRegister src); |
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1685 void paddd(XMMRegister dst, XMMRegister src); |
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1686 void paddq(XMMRegister dst, XMMRegister src); |
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1687 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1688 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1689 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1690 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1691 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1692 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1693 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1694 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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|
1695 |
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|
1696 // Sub packed integers |
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1697 void psubb(XMMRegister dst, XMMRegister src); |
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1698 void psubw(XMMRegister dst, XMMRegister src); |
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1699 void psubd(XMMRegister dst, XMMRegister src); |
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1700 void psubq(XMMRegister dst, XMMRegister src); |
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1701 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1702 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1703 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1704 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1705 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1706 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1707 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1708 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1709 |
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1710 // Multiply packed integers (only shorts and ints) |
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1711 void pmullw(XMMRegister dst, XMMRegister src); |
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1712 void pmulld(XMMRegister dst, XMMRegister src); |
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1713 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1714 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1715 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1716 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1717 |
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1718 // Shift left packed integers |
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1719 void psllw(XMMRegister dst, int shift); |
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1720 void pslld(XMMRegister dst, int shift); |
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1721 void psllq(XMMRegister dst, int shift); |
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1722 void psllw(XMMRegister dst, XMMRegister shift); |
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1723 void pslld(XMMRegister dst, XMMRegister shift); |
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1724 void psllq(XMMRegister dst, XMMRegister shift); |
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1725 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1726 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1727 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1728 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1729 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1730 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1731 |
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1732 // Logical shift right packed integers |
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1733 void psrlw(XMMRegister dst, int shift); |
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1734 void psrld(XMMRegister dst, int shift); |
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1735 void psrlq(XMMRegister dst, int shift); |
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1736 void psrlw(XMMRegister dst, XMMRegister shift); |
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1737 void psrld(XMMRegister dst, XMMRegister shift); |
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1738 void psrlq(XMMRegister dst, XMMRegister shift); |
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1739 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1740 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1741 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1742 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1743 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1744 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1745 |
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1746 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) |
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1747 void psraw(XMMRegister dst, int shift); |
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1748 void psrad(XMMRegister dst, int shift); |
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1749 void psraw(XMMRegister dst, XMMRegister shift); |
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1750 void psrad(XMMRegister dst, XMMRegister shift); |
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1751 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1752 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1753 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1754 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1755 |
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1756 // And packed integers |
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1757 void pand(XMMRegister dst, XMMRegister src); |
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1758 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1759 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1760 |
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1761 // Or packed integers |
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1762 void por(XMMRegister dst, XMMRegister src); |
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1763 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1764 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1765 |
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1766 // Xor packed integers |
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1767 void pxor(XMMRegister dst, XMMRegister src); |
6225 | 1768 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6614
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1769 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1770 |
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1771 // Copy low 128bit into high 128bit of YMM registers. |
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1772 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
6225 | 1773 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1774 |
6792
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1775 // Load/store high 128bit of YMM registers which does not destroy other half. |
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1776 void vinsertf128h(XMMRegister dst, Address src); |
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1777 void vinserti128h(XMMRegister dst, Address src); |
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1778 void vextractf128h(Address dst, XMMRegister src); |
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1779 void vextracti128h(Address dst, XMMRegister src); |
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1780 |
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1781 // duplicate 4-bytes integer data from src into 8 locations in dest |
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1782 void vpbroadcastd(XMMRegister dst, XMMRegister src); |
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1783 |
11080
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1784 // Carry-Less Multiplication Quadword |
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1785 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); |
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1786 |
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1787 // AVX instruction which is used to clear upper 128 bits of YMM registers and |
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1788 // to avoid transaction penalty between AVX and SSE states. There is no |
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1789 // penalty if legacy SSE instructions are encoded using VEX prefix because |
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1790 // they always clear upper 128 bits. It should be used before calling |
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1791 // runtime code and native libraries. |
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1792 void vzeroupper(); |
4761
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1793 |
4759 | 1794 protected: |
1795 // Next instructions require address alignment 16 bytes SSE mode. | |
1796 // They should be called only from corresponding MacroAssembler instructions. | |
1797 void andpd(XMMRegister dst, Address src); | |
1798 void andps(XMMRegister dst, Address src); | |
1799 void xorpd(XMMRegister dst, Address src); | |
1800 void xorps(XMMRegister dst, Address src); | |
1801 | |
0 | 1802 }; |
1803 | |
1972 | 1804 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |