Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 20804:7848fc12602b
Merge with jdk8u40-b25
| author | Gilles Duboscq <gilles.m.duboscq@oracle.com> |
|---|---|
| date | Tue, 07 Apr 2015 14:58:49 +0200 |
| parents | 33a783b15758 318cc6fdae90 |
| children | 178a4927b95c |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
| 1972 | 27 #include "code/debugInfoRec.hpp" |
| 28 #include "code/icBuffer.hpp" | |
| 29 #include "code/vtableStubs.hpp" | |
| 30 #include "interpreter/interpreter.hpp" | |
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31 #include "oops/compiledICHolder.hpp" |
| 1972 | 32 #include "prims/jvmtiRedefineClassesTrace.hpp" |
| 33 #include "runtime/sharedRuntime.hpp" | |
| 34 #include "runtime/vframeArray.hpp" | |
| 35 #include "vmreg_sparc.inline.hpp" | |
| 36 #ifdef COMPILER1 | |
| 37 #include "c1/c1_Runtime1.hpp" | |
| 38 #endif | |
| 39 #ifdef COMPILER2 | |
| 40 #include "opto/runtime.hpp" | |
| 41 #endif | |
| 42 #ifdef SHARK | |
| 43 #include "compiler/compileBroker.hpp" | |
| 44 #include "shark/sharkCompiler.hpp" | |
| 45 #endif | |
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46 #ifdef GRAAL |
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47 #include "graal/graalJavaAccess.hpp" |
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48 #endif |
| 0 | 49 |
| 50 #define __ masm-> | |
| 51 | |
| 52 | |
| 53 class RegisterSaver { | |
| 54 | |
| 55 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O. | |
| 56 // The Oregs are problematic. In the 32bit build the compiler can | |
| 57 // have O registers live with 64 bit quantities. A window save will | |
| 58 // cut the heads off of the registers. We have to do a very extensive | |
| 59 // stack dance to save and restore these properly. | |
| 60 | |
| 61 // Note that the Oregs problem only exists if we block at either a polling | |
| 62 // page exception a compiled code safepoint that was not originally a call | |
| 63 // or deoptimize following one of these kinds of safepoints. | |
| 64 | |
| 65 // Lots of registers to save. For all builds, a window save will preserve | |
| 66 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit | |
| 67 // builds a window-save will preserve the %o registers. In the LION build | |
| 68 // we need to save the 64-bit %o registers which requires we save them | |
| 69 // before the window-save (as then they become %i registers and get their | |
| 70 // heads chopped off on interrupt). We have to save some %g registers here | |
| 71 // as well. | |
| 72 enum { | |
| 73 // This frame's save area. Includes extra space for the native call: | |
| 74 // vararg's layout space and the like. Briefly holds the caller's | |
| 75 // register save area. | |
| 76 call_args_area = frame::register_save_words_sp_offset + | |
| 77 frame::memory_parameter_word_sp_offset*wordSize, | |
| 78 // Make sure save locations are always 8 byte aligned. | |
| 79 // can't use round_to because it doesn't produce compile time constant | |
| 80 start_of_extra_save_area = ((call_args_area + 7) & ~7), | |
| 81 g1_offset = start_of_extra_save_area, // g-regs needing saving | |
| 82 g3_offset = g1_offset+8, | |
| 83 g4_offset = g3_offset+8, | |
| 84 g5_offset = g4_offset+8, | |
| 85 o0_offset = g5_offset+8, | |
| 86 o1_offset = o0_offset+8, | |
| 87 o2_offset = o1_offset+8, | |
| 88 o3_offset = o2_offset+8, | |
| 89 o4_offset = o3_offset+8, | |
| 90 o5_offset = o4_offset+8, | |
| 91 start_of_flags_save_area = o5_offset+8, | |
| 92 ccr_offset = start_of_flags_save_area, | |
| 93 fsr_offset = ccr_offset + 8, | |
| 94 d00_offset = fsr_offset+8, // Start of float save area | |
| 95 register_save_size = d00_offset+8*32 | |
| 96 }; | |
| 97 | |
| 98 | |
| 99 public: | |
| 100 | |
| 101 static int Oexception_offset() { return o0_offset; }; | |
| 102 static int G3_offset() { return g3_offset; }; | |
| 103 static int G5_offset() { return g5_offset; }; | |
| 104 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); | |
| 105 static void restore_live_registers(MacroAssembler* masm); | |
| 106 | |
| 107 // During deoptimization only the result register need to be restored | |
| 108 // all the other values have already been extracted. | |
| 109 | |
| 110 static void restore_result_registers(MacroAssembler* masm); | |
| 111 }; | |
| 112 | |
| 113 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { | |
| 114 // Record volatile registers as callee-save values in an OopMap so their save locations will be | |
| 115 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for | |
| 116 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers | |
| 117 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame | |
| 118 // (as the stub's I's) when the runtime routine called by the stub creates its frame. | |
| 119 int i; | |
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120 // Always make the frame size 16 byte aligned. |
| 0 | 121 int frame_size = round_to(additional_frame_words + register_save_size, 16); |
| 122 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words | |
| 123 int frame_size_in_slots = frame_size / sizeof(jint); | |
| 124 // CodeBlob frame size is in words. | |
| 125 *total_frame_words = frame_size / wordSize; | |
| 126 // OopMap* map = new OopMap(*total_frame_words, 0); | |
| 127 OopMap* map = new OopMap(frame_size_in_slots, 0); | |
| 128 | |
| 129 #if !defined(_LP64) | |
| 130 | |
| 131 // Save 64-bit O registers; they will get their heads chopped off on a 'save'. | |
| 132 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
| 133 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
| 134 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
| 135 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
| 136 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
| 137 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
| 138 #endif /* _LP64 */ | |
| 139 | |
| 140 __ save(SP, -frame_size, SP); | |
| 141 | |
| 142 #ifndef _LP64 | |
| 143 // Reload the 64 bit Oregs. Although they are now Iregs we load them | |
| 144 // to Oregs here to avoid interrupts cutting off their heads | |
| 145 | |
| 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
| 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
| 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
| 149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
| 150 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
| 151 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
| 152 | |
| 153 __ stx(O0, SP, o0_offset+STACK_BIAS); | |
| 154 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg()); | |
| 155 | |
| 156 __ stx(O1, SP, o1_offset+STACK_BIAS); | |
| 157 | |
| 158 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg()); | |
| 159 | |
| 160 __ stx(O2, SP, o2_offset+STACK_BIAS); | |
| 161 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg()); | |
| 162 | |
| 163 __ stx(O3, SP, o3_offset+STACK_BIAS); | |
| 164 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg()); | |
| 165 | |
| 166 __ stx(O4, SP, o4_offset+STACK_BIAS); | |
| 167 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg()); | |
| 168 | |
| 169 __ stx(O5, SP, o5_offset+STACK_BIAS); | |
| 170 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg()); | |
| 171 #endif /* _LP64 */ | |
| 172 | |
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173 |
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174 #ifdef _LP64 |
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175 int debug_offset = 0; |
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176 #else |
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177 int debug_offset = 4; |
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178 #endif |
| 0 | 179 // Save the G's |
| 180 __ stx(G1, SP, g1_offset+STACK_BIAS); | |
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181 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg()); |
| 0 | 182 |
| 183 __ stx(G3, SP, g3_offset+STACK_BIAS); | |
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184 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg()); |
| 0 | 185 |
| 186 __ stx(G4, SP, g4_offset+STACK_BIAS); | |
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187 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg()); |
| 0 | 188 |
| 189 __ stx(G5, SP, g5_offset+STACK_BIAS); | |
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190 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg()); |
| 0 | 191 |
| 192 // This is really a waste but we'll keep things as they were for now | |
| 193 if (true) { | |
| 194 #ifndef _LP64 | |
| 195 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next()); | |
| 196 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next()); | |
| 197 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next()); | |
| 198 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next()); | |
| 199 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next()); | |
| 200 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next()); | |
| 201 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next()); | |
| 202 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next()); | |
| 203 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next()); | |
| 204 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next()); | |
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205 #endif /* _LP64 */ |
| 0 | 206 } |
| 207 | |
| 208 | |
| 209 // Save the flags | |
| 210 __ rdccr( G5 ); | |
| 211 __ stx(G5, SP, ccr_offset+STACK_BIAS); | |
| 212 __ stxfsr(SP, fsr_offset+STACK_BIAS); | |
| 213 | |
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214 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles) |
| 0 | 215 int offset = d00_offset; |
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216 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
| 0 | 217 FloatRegister f = as_FloatRegister(i); |
| 218 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS); | |
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219 // Record as callee saved both halves of double registers (2 float registers). |
| 0 | 220 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg()); |
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221 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next()); |
| 0 | 222 offset += sizeof(double); |
| 223 } | |
| 224 | |
| 225 // And we're done. | |
| 226 | |
| 227 return map; | |
| 228 } | |
| 229 | |
| 230 | |
| 231 // Pop the current frame and restore all the registers that we | |
| 232 // saved. | |
| 233 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { | |
| 234 | |
| 235 // Restore all the FP registers | |
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236 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
| 0 | 237 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i)); |
| 238 } | |
| 239 | |
| 240 __ ldx(SP, ccr_offset+STACK_BIAS, G1); | |
| 241 __ wrccr (G1) ; | |
| 242 | |
| 243 // Restore the G's | |
| 244 // Note that G2 (AKA GThread) must be saved and restored separately. | |
| 245 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr. | |
| 246 | |
| 247 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
| 248 __ ldx(SP, g3_offset+STACK_BIAS, G3); | |
| 249 __ ldx(SP, g4_offset+STACK_BIAS, G4); | |
| 250 __ ldx(SP, g5_offset+STACK_BIAS, G5); | |
| 251 | |
| 252 | |
| 253 #if !defined(_LP64) | |
| 254 // Restore the 64-bit O's. | |
| 255 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
| 256 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
| 257 __ ldx(SP, o2_offset+STACK_BIAS, O2); | |
| 258 __ ldx(SP, o3_offset+STACK_BIAS, O3); | |
| 259 __ ldx(SP, o4_offset+STACK_BIAS, O4); | |
| 260 __ ldx(SP, o5_offset+STACK_BIAS, O5); | |
| 261 | |
| 262 // And temporarily place them in TLS | |
| 263 | |
| 264 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
| 265 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
| 266 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
| 267 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
| 268 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
| 269 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
| 270 #endif /* _LP64 */ | |
| 271 | |
| 272 // Restore flags | |
| 273 | |
| 274 __ ldxfsr(SP, fsr_offset+STACK_BIAS); | |
| 275 | |
| 276 __ restore(); | |
| 277 | |
| 278 #if !defined(_LP64) | |
| 279 // Now reload the 64bit Oregs after we've restore the window. | |
| 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
| 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
| 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
| 283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
| 284 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
| 285 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
| 286 #endif /* _LP64 */ | |
| 287 | |
| 288 } | |
| 289 | |
| 290 // Pop the current frame and restore the registers that might be holding | |
| 291 // a result. | |
| 292 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { | |
| 293 | |
| 294 #if !defined(_LP64) | |
| 295 // 32bit build returns longs in G1 | |
| 296 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
| 297 | |
| 298 // Retrieve the 64-bit O's. | |
| 299 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
| 300 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
| 301 // and save to TLS | |
| 302 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
| 303 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
| 304 #endif /* _LP64 */ | |
| 305 | |
| 306 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0)); | |
| 307 | |
| 308 __ restore(); | |
| 309 | |
| 310 #if !defined(_LP64) | |
| 311 // Now reload the 64bit Oregs after we've restore the window. | |
| 312 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
| 313 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
| 314 #endif /* _LP64 */ | |
| 315 | |
| 316 } | |
| 317 | |
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318 // Is vector's size (in bytes) bigger than a size saved by default? |
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319 // 8 bytes FP registers are saved by default on SPARC. |
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320 bool SharedRuntime::is_wide_vector(int size) { |
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321 // Note, MaxVectorSize == 8 on SPARC. |
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322 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size)); |
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323 return size > 8; |
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324 } |
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325 |
| 0 | 326 // The java_calling_convention describes stack locations as ideal slots on |
| 327 // a frame with no abi restrictions. Since we must observe abi restrictions | |
| 328 // (like the placement of the register window) the slots must be biased by | |
| 329 // the following value. | |
| 330 static int reg2offset(VMReg r) { | |
| 331 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
| 332 } | |
| 333 | |
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334 static VMRegPair reg64_to_VMRegPair(Register r) { |
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335 VMRegPair ret; |
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336 if (wordSize == 8) { |
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337 ret.set2(r->as_VMReg()); |
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338 } else { |
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339 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg()); |
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340 } |
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341 return ret; |
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342 } |
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343 |
| 0 | 344 // --------------------------------------------------------------------------- |
| 345 // Read the array of BasicTypes from a signature, and compute where the | |
| 346 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size) | |
| 347 // quantities. Values less than VMRegImpl::stack0 are registers, those above | |
| 348 // refer to 4-byte stack slots. All stack slots are based off of the window | |
| 349 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window, | |
| 350 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register | |
| 351 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit | |
| 352 // integer registers. Values 64-95 are the (32-bit only) float registers. | |
| 353 // Each 32-bit quantity is given its own number, so the integer registers | |
| 354 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is | |
| 355 // an O0-low and an O0-high. Essentially, all int register numbers are doubled. | |
| 356 | |
| 357 // Register results are passed in O0-O5, for outgoing call arguments. To | |
| 358 // convert to incoming arguments, convert all O's to I's. The regs array | |
| 359 // refer to the low and hi 32-bit words of 64-bit registers or stack slots. | |
| 360 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a | |
| 361 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was | |
| 362 // passed (used as a placeholder for the other half of longs and doubles in | |
| 363 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is | |
| 364 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention). | |
| 365 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first() | |
| 366 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the | |
| 367 // same VMRegPair. | |
| 368 | |
| 369 // Note: the INPUTS in sig_bt are in units of Java argument words, which are | |
| 370 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit | |
| 371 // units regardless of build. | |
| 372 | |
| 373 | |
| 374 // --------------------------------------------------------------------------- | |
| 375 // The compiled Java calling convention. The Java convention always passes | |
| 376 // 64-bit values in adjacent aligned locations (either registers or stack), | |
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377 // floats in float registers and doubles in aligned float pairs. There is |
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378 // no backing varargs store for values in registers. |
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379 // In the 32-bit build, longs are passed on the stack (cannot be |
| 0 | 380 // passed in I's, because longs in I's get their heads chopped off at |
| 381 // interrupt). | |
| 382 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, | |
| 383 VMRegPair *regs, | |
| 384 int total_args_passed, | |
| 385 int is_outgoing) { | |
| 386 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); | |
| 387 | |
| 388 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; | |
| 389 const int flt_reg_max = 8; | |
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390 |
| 0 | 391 int int_reg = 0; |
| 392 int flt_reg = 0; | |
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393 int slot = 0; |
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394 |
| 0 | 395 for (int i = 0; i < total_args_passed; i++) { |
| 396 switch (sig_bt[i]) { | |
| 397 case T_INT: | |
| 398 case T_SHORT: | |
| 399 case T_CHAR: | |
| 400 case T_BYTE: | |
| 401 case T_BOOLEAN: | |
| 402 #ifndef _LP64 | |
| 403 case T_OBJECT: | |
| 404 case T_ARRAY: | |
| 405 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
| 406 #endif // _LP64 | |
| 407 if (int_reg < int_reg_max) { | |
| 408 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
| 409 regs[i].set1(r->as_VMReg()); | |
| 410 } else { | |
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411 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
| 0 | 412 } |
| 413 break; | |
| 414 | |
| 415 #ifdef _LP64 | |
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416 case T_LONG: |
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417 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); |
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418 // fall-through |
| 0 | 419 case T_OBJECT: |
| 420 case T_ARRAY: | |
| 421 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
| 422 if (int_reg < int_reg_max) { | |
| 423 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
| 424 regs[i].set2(r->as_VMReg()); | |
| 425 } else { | |
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426 slot = round_to(slot, 2); // align |
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427 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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428 slot += 2; |
| 0 | 429 } |
| 430 break; | |
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431 #else |
| 0 | 432 case T_LONG: |
| 433 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); | |
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434 // On 32-bit SPARC put longs always on the stack to keep the pressure off |
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435 // integer argument registers. They should be used for oops. |
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436 slot = round_to(slot, 2); // align |
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437 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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438 slot += 2; |
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439 #endif |
| 0 | 440 break; |
| 441 | |
| 442 case T_FLOAT: | |
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443 if (flt_reg < flt_reg_max) { |
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444 FloatRegister r = as_FloatRegister(flt_reg++); |
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445 regs[i].set1(r->as_VMReg()); |
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446 } else { |
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447 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
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448 } |
| 0 | 449 break; |
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450 |
| 0 | 451 case T_DOUBLE: |
| 452 assert(sig_bt[i+1] == T_VOID, "expecting half"); | |
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453 if (round_to(flt_reg, 2) + 1 < flt_reg_max) { |
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454 flt_reg = round_to(flt_reg, 2); // align |
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455 FloatRegister r = as_FloatRegister(flt_reg); |
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456 regs[i].set2(r->as_VMReg()); |
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457 flt_reg += 2; |
| 0 | 458 } else { |
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459 slot = round_to(slot, 2); // align |
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460 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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461 slot += 2; |
| 0 | 462 } |
| 463 break; | |
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464 |
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465 case T_VOID: |
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466 regs[i].set_bad(); // Halves of longs & doubles |
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467 break; |
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468 |
| 0 | 469 default: |
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470 fatal(err_msg_res("unknown basic type %d", sig_bt[i])); |
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471 break; |
| 0 | 472 } |
| 473 } | |
| 474 | |
| 475 // retun the amount of stack space these arguments will need. | |
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476 return slot; |
| 0 | 477 } |
| 478 | |
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479 // Helper class mostly to avoid passing masm everywhere, and handle |
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480 // store displacement overflow logic. |
| 0 | 481 class AdapterGenerator { |
| 482 MacroAssembler *masm; | |
| 483 Register Rdisp; | |
| 484 void set_Rdisp(Register r) { Rdisp = r; } | |
| 485 | |
| 486 void patch_callers_callsite(); | |
| 487 | |
| 488 // base+st_off points to top of argument | |
| 1506 | 489 int arg_offset(const int st_off) { return st_off; } |
| 0 | 490 int next_arg_offset(const int st_off) { |
| 1506 | 491 return st_off - Interpreter::stackElementSize; |
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492 } |
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493 |
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494 // Argument slot values may be loaded first into a register because |
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495 // they might not fit into displacement. |
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496 RegisterOrConstant arg_slot(const int st_off); |
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497 RegisterOrConstant next_arg_slot(const int st_off); |
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498 |
| 0 | 499 // Stores long into offset pointed to by base |
| 500 void store_c2i_long(Register r, Register base, | |
| 501 const int st_off, bool is_stack); | |
| 502 void store_c2i_object(Register r, Register base, | |
| 503 const int st_off); | |
| 504 void store_c2i_int(Register r, Register base, | |
| 505 const int st_off); | |
| 506 void store_c2i_double(VMReg r_2, | |
| 507 VMReg r_1, Register base, const int st_off); | |
| 508 void store_c2i_float(FloatRegister f, Register base, | |
| 509 const int st_off); | |
| 510 | |
| 511 public: | |
| 512 void gen_c2i_adapter(int total_args_passed, | |
| 513 // VMReg max_arg, | |
| 514 int comp_args_on_stack, // VMRegStackSlots | |
| 515 const BasicType *sig_bt, | |
| 516 const VMRegPair *regs, | |
| 517 Label& skip_fixup); | |
| 518 void gen_i2c_adapter(int total_args_passed, | |
|
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519 // VMReg max_arg, |
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520 int comp_args_on_stack, // VMRegStackSlots |
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521 const BasicType *sig_bt, |
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522 const VMRegPair *regs, |
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523 int frame_extension_argument = -1); |
| 0 | 524 |
| 525 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} | |
| 526 }; | |
| 527 | |
| 528 | |
| 529 // Patch the callers callsite with entry to compiled code if it exists. | |
| 530 void AdapterGenerator::patch_callers_callsite() { | |
| 531 Label L; | |
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532 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
| 3839 | 533 __ br_null(G3_scratch, false, Assembler::pt, L); |
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534 __ delayed()->nop(); |
| 0 | 535 // Call into the VM to patch the caller, then jump to compiled callee |
| 536 __ save_frame(4); // Args in compiled layout; do not blow them | |
| 537 | |
| 538 // Must save all the live Gregs the list is: | |
| 539 // G1: 1st Long arg (32bit build) | |
| 540 // G2: global allocated to TLS | |
| 541 // G3: used in inline cache check (scratch) | |
| 542 // G4: 2nd Long arg (32bit build); | |
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543 // G5: used in inline cache check (Method*) |
| 0 | 544 |
| 545 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops. | |
| 546 | |
| 547 #ifdef _LP64 | |
| 548 // mov(s,d) | |
| 549 __ mov(G1, L1); | |
| 550 __ mov(G4, L4); | |
| 551 __ mov(G5_method, L5); | |
| 552 __ mov(G5_method, O0); // VM needs target method | |
| 553 __ mov(I7, O1); // VM needs caller's callsite | |
| 554 // Must be a leaf call... | |
| 555 // can be very far once the blob has been relocated | |
| 727 | 556 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)); |
| 0 | 557 __ relocate(relocInfo::runtime_call_type); |
| 727 | 558 __ jumpl_to(dest, O7, O7); |
| 0 | 559 __ delayed()->mov(G2_thread, L7_thread_cache); |
| 560 __ mov(L7_thread_cache, G2_thread); | |
| 561 __ mov(L1, G1); | |
| 562 __ mov(L4, G4); | |
| 563 __ mov(L5, G5_method); | |
| 564 #else | |
| 565 __ stx(G1, FP, -8 + STACK_BIAS); | |
| 566 __ stx(G4, FP, -16 + STACK_BIAS); | |
| 567 __ mov(G5_method, L5); | |
| 568 __ mov(G5_method, O0); // VM needs target method | |
| 569 __ mov(I7, O1); // VM needs caller's callsite | |
| 570 // Must be a leaf call... | |
| 571 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type); | |
| 572 __ delayed()->mov(G2_thread, L7_thread_cache); | |
| 573 __ mov(L7_thread_cache, G2_thread); | |
| 574 __ ldx(FP, -8 + STACK_BIAS, G1); | |
| 575 __ ldx(FP, -16 + STACK_BIAS, G4); | |
| 576 __ mov(L5, G5_method); | |
| 577 #endif /* _LP64 */ | |
| 578 | |
| 579 __ restore(); // Restore args | |
| 580 __ bind(L); | |
| 581 } | |
| 582 | |
|
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583 |
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584 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) { |
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585 RegisterOrConstant roc(arg_offset(st_off)); |
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586 return __ ensure_simm13_or_reg(roc, Rdisp); |
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587 } |
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588 |
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589 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) { |
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590 RegisterOrConstant roc(next_arg_offset(st_off)); |
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591 return __ ensure_simm13_or_reg(roc, Rdisp); |
| 0 | 592 } |
| 593 | |
|
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594 |
| 0 | 595 // Stores long into offset pointed to by base |
| 596 void AdapterGenerator::store_c2i_long(Register r, Register base, | |
| 597 const int st_off, bool is_stack) { | |
| 598 #ifdef _LP64 | |
| 599 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
| 600 // data is passed in only 1 slot. | |
| 601 __ stx(r, base, next_arg_slot(st_off)); | |
| 602 #else | |
|
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603 #ifdef COMPILER2 |
| 0 | 604 // Misaligned store of 64-bit data |
| 605 __ stw(r, base, arg_slot(st_off)); // lo bits | |
| 606 __ srlx(r, 32, r); | |
| 607 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
| 608 #else | |
| 609 if (is_stack) { | |
| 610 // Misaligned store of 64-bit data | |
| 611 __ stw(r, base, arg_slot(st_off)); // lo bits | |
| 612 __ srlx(r, 32, r); | |
| 613 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
| 614 } else { | |
| 615 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits | |
| 616 __ stw(r , base, next_arg_slot(st_off)); // hi bits | |
| 617 } | |
| 618 #endif // COMPILER2 | |
|
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619 #endif // _LP64 |
| 0 | 620 } |
| 621 | |
| 622 void AdapterGenerator::store_c2i_object(Register r, Register base, | |
| 623 const int st_off) { | |
| 624 __ st_ptr (r, base, arg_slot(st_off)); | |
| 625 } | |
| 626 | |
| 627 void AdapterGenerator::store_c2i_int(Register r, Register base, | |
| 628 const int st_off) { | |
| 629 __ st (r, base, arg_slot(st_off)); | |
| 630 } | |
| 631 | |
| 632 // Stores into offset pointed to by base | |
| 633 void AdapterGenerator::store_c2i_double(VMReg r_2, | |
| 634 VMReg r_1, Register base, const int st_off) { | |
| 635 #ifdef _LP64 | |
| 636 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
| 637 // data is passed in only 1 slot. | |
| 638 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
| 639 #else | |
| 640 // Need to marshal 64-bit value from misaligned Lesp loads | |
| 641 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
| 642 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) ); | |
| 643 #endif | |
| 644 } | |
| 645 | |
| 646 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, | |
| 647 const int st_off) { | |
| 648 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off)); | |
| 649 } | |
| 650 | |
| 651 void AdapterGenerator::gen_c2i_adapter( | |
| 652 int total_args_passed, | |
| 653 // VMReg max_arg, | |
| 654 int comp_args_on_stack, // VMRegStackSlots | |
| 655 const BasicType *sig_bt, | |
| 656 const VMRegPair *regs, | |
|
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657 Label& L_skip_fixup) { |
| 0 | 658 |
| 659 // Before we get into the guts of the C2I adapter, see if we should be here | |
| 660 // at all. We've come from compiled code and are attempting to jump to the | |
| 661 // interpreter, which means the caller made a static call to get here | |
| 662 // (vcalls always get a compiled target if there is one). Check for a | |
| 663 // compiled target. If there is one, we need to patch the caller's call. | |
| 664 // However we will run interpreted if we come thru here. The next pass | |
| 665 // thru the call site will run compiled. If we ran compiled here then | |
| 666 // we can (theorectically) do endless i2c->c2i->i2c transitions during | |
| 667 // deopt/uncommon trap cycles. If we always go interpreted here then | |
| 668 // we can have at most one and don't need to play any tricks to keep | |
| 669 // from endlessly growing the stack. | |
| 670 // | |
| 671 // Actually if we detected that we had an i2c->c2i transition here we | |
| 672 // ought to be able to reset the world back to the state of the interpreted | |
| 673 // call and not bother building another interpreter arg area. We don't | |
| 674 // do that at this point. | |
| 675 | |
| 676 patch_callers_callsite(); | |
| 677 | |
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678 __ bind(L_skip_fixup); |
| 0 | 679 |
| 680 // Since all args are passed on the stack, total_args_passed*wordSize is the | |
| 681 // space we need. Add in varargs area needed by the interpreter. Round up | |
| 682 // to stack alignment. | |
| 1506 | 683 const int arg_size = total_args_passed * Interpreter::stackElementSize; |
| 0 | 684 const int varargs_area = |
| 685 (frame::varargs_offset - frame::register_save_words)*wordSize; | |
| 686 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); | |
| 687 | |
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688 const int bias = STACK_BIAS; |
| 0 | 689 const int interp_arg_offset = frame::varargs_offset*wordSize + |
| 1506 | 690 (total_args_passed-1)*Interpreter::stackElementSize; |
| 0 | 691 |
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692 const Register base = SP; |
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693 |
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694 // Make some extra space on the stack. |
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695 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP); |
| 0 | 696 set_Rdisp(G3_scratch); |
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697 |
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698 // Write the args into the outgoing interpreter space. |
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699 for (int i = 0; i < total_args_passed; i++) { |
| 1506 | 700 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; |
| 0 | 701 VMReg r_1 = regs[i].first(); |
| 702 VMReg r_2 = regs[i].second(); | |
| 703 if (!r_1->is_valid()) { | |
| 704 assert(!r_2->is_valid(), ""); | |
| 705 continue; | |
| 706 } | |
| 707 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 | |
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708 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias; |
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709 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp); |
| 0 | 710 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle |
| 711 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); | |
| 712 else __ ldx(base, ld_off, G1_scratch); | |
| 713 } | |
| 714 | |
| 715 if (r_1->is_Register()) { | |
| 716 Register r = r_1->as_Register()->after_restore(); | |
| 717 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | |
| 718 store_c2i_object(r, base, st_off); | |
| 719 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | |
| 720 store_c2i_long(r, base, st_off, r_2->is_stack()); | |
| 721 } else { | |
| 722 store_c2i_int(r, base, st_off); | |
| 723 } | |
| 724 } else { | |
| 725 assert(r_1->is_FloatRegister(), ""); | |
| 726 if (sig_bt[i] == T_FLOAT) { | |
| 727 store_c2i_float(r_1->as_FloatRegister(), base, st_off); | |
| 728 } else { | |
| 729 assert(sig_bt[i] == T_DOUBLE, "wrong type"); | |
| 730 store_c2i_double(r_2, r_1, base, st_off); | |
| 731 } | |
| 732 } | |
| 733 } | |
| 734 | |
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735 // Load the interpreter entry point. |
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736 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); |
| 0 | 737 |
| 738 // Pass O5_savedSP as an argument to the interpreter. | |
| 739 // The interpreter will restore SP to this value before returning. | |
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740 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP); |
| 0 | 741 |
| 742 __ mov((frame::varargs_offset)*wordSize - | |
| 1506 | 743 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); |
| 0 | 744 // Jump to the interpreter just as if interpreter was doing it. |
| 745 __ jmpl(G3_scratch, 0, G0); | |
| 746 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp | |
| 747 // (really L0) is in use by the compiled frame as a generic temp. However, | |
| 748 // the interpreter does not know where its args are without some kind of | |
| 749 // arg pointer being passed in. Pass it in Gargs. | |
| 750 __ delayed()->add(SP, G1, Gargs); | |
| 751 } | |
| 752 | |
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753 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg, |
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754 address code_start, address code_end, |
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755 Label& L_ok) { |
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756 Label L_fail; |
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757 __ set(ExternalAddress(code_start), temp_reg); |
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758 __ set(pointer_delta(code_end, code_start, 1), temp2_reg); |
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759 __ cmp(pc_reg, temp_reg); |
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760 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail); |
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761 __ delayed()->add(temp_reg, temp2_reg, temp_reg); |
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762 __ cmp(pc_reg, temp_reg); |
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763 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok); |
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764 __ bind(L_fail); |
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765 } |
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766 |
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767 void AdapterGenerator::gen_i2c_adapter(int total_args_passed, |
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768 // VMReg max_arg, |
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769 int comp_args_on_stack, // VMRegStackSlots |
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770 const BasicType *sig_bt, |
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771 const VMRegPair *regs, |
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772 int frame_extension_argument) { |
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773 assert(frame_extension_argument == -1, "unsupported"); |
| 0 | 774 |
| 775 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame | |
| 776 // layout. Lesp was saved by the calling I-frame and will be restored on | |
| 777 // return. Meanwhile, outgoing arg space is all owned by the callee | |
| 778 // C-frame, so we can mangle it at will. After adjusting the frame size, | |
| 779 // hoist register arguments and repack other args according to the compiled | |
| 780 // code convention. Finally, end in a jump to the compiled code. The entry | |
| 781 // point address is the start of the buffer. | |
| 782 | |
| 783 // We will only enter here from an interpreted frame and never from after | |
| 784 // passing thru a c2i. Azul allowed this but we do not. If we lose the | |
| 785 // race and use a c2i we will remain interpreted for the race loser(s). | |
| 786 // This removes all sorts of headaches on the x86 side and also eliminates | |
| 787 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. | |
| 788 | |
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789 // More detail: |
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790 // Adapters can be frameless because they do not require the caller |
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791 // to perform additional cleanup work, such as correcting the stack pointer. |
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792 // An i2c adapter is frameless because the *caller* frame, which is interpreted, |
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793 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), |
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794 // even if a callee has modified the stack pointer. |
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795 // A c2i adapter is frameless because the *callee* frame, which is interpreted, |
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796 // routinely repairs its caller's stack pointer (from sender_sp, which is set |
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797 // up via the senderSP register). |
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798 // In other words, if *either* the caller or callee is interpreted, we can |
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799 // get the stack pointer repaired after a call. |
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800 // This is why c2i and i2c adapters cannot be indefinitely composed. |
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801 // In particular, if a c2i adapter were to somehow call an i2c adapter, |
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802 // both caller and callee would be compiled methods, and neither would |
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803 // clean up the stack pointer changes performed by the two adapters. |
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804 // If this happens, control eventually transfers back to the compiled |
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805 // caller, but with an uncorrected stack, causing delayed havoc. |
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806 |
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807 if (VerifyAdapterCalls && |
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808 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { |
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809 // So, let's test for cascading c2i/i2c adapters right now. |
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810 // assert(Interpreter::contains($return_addr) || |
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811 // StubRoutines::contains($return_addr), |
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812 // "i2c adapter must return to an interpreter frame"); |
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813 __ block_comment("verify_i2c { "); |
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814 Label L_ok; |
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815 if (Interpreter::code() != NULL) |
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816 range_check(masm, O7, O0, O1, |
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817 Interpreter::code()->code_start(), Interpreter::code()->code_end(), |
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818 L_ok); |
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819 if (StubRoutines::code1() != NULL) |
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820 range_check(masm, O7, O0, O1, |
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821 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), |
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822 L_ok); |
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823 if (StubRoutines::code2() != NULL) |
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824 range_check(masm, O7, O0, O1, |
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825 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), |
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826 L_ok); |
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827 const char* msg = "i2c adapter must return to an interpreter frame"; |
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828 __ block_comment(msg); |
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829 __ stop(msg); |
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830 __ bind(L_ok); |
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831 __ block_comment("} verify_i2ce "); |
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832 } |
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833 |
| 0 | 834 // As you can see from the list of inputs & outputs there are not a lot |
| 835 // of temp registers to work with: mostly G1, G3 & G4. | |
| 836 | |
| 837 // Inputs: | |
| 838 // G2_thread - TLS | |
| 839 // G5_method - Method oop | |
| 710 | 840 // G4 (Gargs) - Pointer to interpreter's args |
| 841 // O0..O4 - free for scratch | |
| 842 // O5_savedSP - Caller's saved SP, to be restored if needed | |
| 0 | 843 // O6 - Current SP! |
| 844 // O7 - Valid return address | |
| 710 | 845 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
| 0 | 846 |
| 847 // Outputs: | |
| 848 // G2_thread - TLS | |
| 849 // O0-O5 - Outgoing args in compiled layout | |
| 850 // O6 - Adjusted or restored SP | |
| 851 // O7 - Valid return address | |
| 1564 | 852 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
| 0 | 853 // F0-F7 - more outgoing args |
| 854 | |
| 855 | |
| 710 | 856 // Gargs is the incoming argument base, and also an outgoing argument. |
| 0 | 857 __ sub(Gargs, BytesPerWord, Gargs); |
| 858 | |
| 859 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME | |
| 860 // WITH O7 HOLDING A VALID RETURN PC | |
| 861 // | |
| 862 // | | | |
| 863 // : java stack : | |
| 864 // | | | |
| 865 // +--------------+ <--- start of outgoing args | |
| 866 // | receiver | | | |
| 867 // : rest of args : |---size is java-arg-words | |
| 868 // | | | | |
| 869 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I | |
| 870 // | | | | |
| 871 // : unused : |---Space for max Java stack, plus stack alignment | |
| 872 // | | | | |
| 873 // +--------------+ <--- SP + 16*wordsize | |
| 874 // | | | |
| 875 // : window : | |
| 876 // | | | |
| 877 // +--------------+ <--- SP | |
| 878 | |
| 879 // WE REPACK THE STACK. We use the common calling convention layout as | |
| 880 // discovered by calling SharedRuntime::calling_convention. We assume it | |
| 881 // causes an arbitrary shuffle of memory, which may require some register | |
| 882 // temps to do the shuffle. We hope for (and optimize for) the case where | |
| 883 // temps are not needed. We may have to resize the stack slightly, in case | |
| 884 // we need alignment padding (32-bit interpreter can pass longs & doubles | |
| 885 // misaligned, but the compilers expect them aligned). | |
| 886 // | |
| 887 // | | | |
| 888 // : java stack : | |
| 889 // | | | |
| 890 // +--------------+ <--- start of outgoing args | |
| 891 // | pad, align | | | |
| 892 // +--------------+ | | |
|
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893 // | ints, longs, | | |
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894 // | floats, | |---Outgoing stack args. |
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895 // : doubles : | First few args in registers. |
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896 // | | | |
| 0 | 897 // +--------------+ <--- SP' + 16*wordsize |
| 898 // | | | |
| 899 // : window : | |
| 900 // | | | |
| 901 // +--------------+ <--- SP' | |
| 902 | |
| 903 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME | |
| 904 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP | |
| 905 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. | |
| 906 | |
| 907 // Cut-out for having no stack args. Since up to 6 args are passed | |
| 908 // in registers, we will commonly have no stack args. | |
| 909 if (comp_args_on_stack > 0) { | |
| 910 // Convert VMReg stack slots to words. | |
| 911 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; | |
| 912 // Round up to miminum stack alignment, in wordSize | |
| 913 comp_words_on_stack = round_to(comp_words_on_stack, 2); | |
| 914 // Now compute the distance from Lesp to SP. This calculation does not | |
| 915 // include the space for total_args_passed because Lesp has not yet popped | |
| 916 // the arguments. | |
| 917 __ sub(SP, (comp_words_on_stack)*wordSize, SP); | |
| 918 } | |
| 919 | |
| 920 // Now generate the shuffle code. Pick up all register args and move the | |
| 921 // rest through G1_scratch. | |
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922 for (int i = 0; i < total_args_passed; i++) { |
| 0 | 923 if (sig_bt[i] == T_VOID) { |
| 924 // Longs and doubles are passed in native word order, but misaligned | |
| 925 // in the 32-bit build. | |
| 926 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | |
| 927 continue; | |
| 928 } | |
| 929 | |
| 930 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the | |
| 931 // 32-bit build and aligned in the 64-bit build. Look for the obvious | |
| 932 // ldx/lddf optimizations. | |
| 933 | |
| 934 // Load in argument order going down. | |
| 1506 | 935 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; |
| 0 | 936 set_Rdisp(G1_scratch); |
| 937 | |
| 938 VMReg r_1 = regs[i].first(); | |
| 939 VMReg r_2 = regs[i].second(); | |
| 940 if (!r_1->is_valid()) { | |
| 941 assert(!r_2->is_valid(), ""); | |
| 942 continue; | |
| 943 } | |
| 944 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9 | |
| 945 r_1 = F8->as_VMReg(); // as part of the load/store shuffle | |
| 946 if (r_2->is_valid()) r_2 = r_1->next(); | |
| 947 } | |
| 948 if (r_1->is_Register()) { // Register argument | |
| 949 Register r = r_1->as_Register()->after_restore(); | |
| 950 if (!r_2->is_valid()) { | |
| 951 __ ld(Gargs, arg_slot(ld_off), r); | |
| 952 } else { | |
| 953 #ifdef _LP64 | |
| 954 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
| 955 // data is passed in only 1 slot. | |
|
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956 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? |
| 0 | 957 next_arg_slot(ld_off) : arg_slot(ld_off); |
| 958 __ ldx(Gargs, slot, r); | |
| 959 #else | |
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960 fatal("longs should be on stack"); |
| 0 | 961 #endif |
| 962 } | |
| 963 } else { | |
| 964 assert(r_1->is_FloatRegister(), ""); | |
| 965 if (!r_2->is_valid()) { | |
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966 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); |
| 0 | 967 } else { |
| 968 #ifdef _LP64 | |
| 969 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
| 970 // data is passed in only 1 slot. This code also handles longs that | |
| 971 // are passed on the stack, but need a stack-to-stack move through a | |
| 972 // spare float register. | |
|
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973 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? |
| 0 | 974 next_arg_slot(ld_off) : arg_slot(ld_off); |
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975 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); |
| 0 | 976 #else |
| 977 // Need to marshal 64-bit value from misaligned Lesp loads | |
| 978 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); | |
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979 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); |
| 0 | 980 #endif |
| 981 } | |
| 982 } | |
| 983 // Was the argument really intended to be on the stack, but was loaded | |
| 984 // into F8/F9? | |
| 985 if (regs[i].first()->is_stack()) { | |
| 986 assert(r_1->as_FloatRegister() == F8, "fix this code"); | |
| 987 // Convert stack slot to an SP offset | |
| 988 int st_off = reg2offset(regs[i].first()) + STACK_BIAS; | |
| 989 // Store down the shuffled stack word. Target address _is_ aligned. | |
|
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990 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); |
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991 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); |
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992 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); |
| 0 | 993 } |
| 994 } | |
| 995 | |
| 996 // Jump to the compiled code just as if compiled code was doing it. | |
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997 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); |
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998 #ifdef GRAAL |
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999 // check if this call should be routed towards a specific entry point |
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1000 __ ld(Address(G2_thread, in_bytes(JavaThread::graal_alternate_call_target_offset())), G1); |
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1001 __ cmp(G0, G1); |
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1002 Label no_alternative_target; |
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1003 __ br(Assembler::equal, false, Assembler::pn, no_alternative_target); |
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1004 __ delayed()->nop(); |
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1005 |
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1006 __ ld_ptr(G2_thread, in_bytes(JavaThread::graal_alternate_call_target_offset()), G3); |
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1007 __ st(G0, Address(G2_thread, in_bytes(JavaThread::graal_alternate_call_target_offset()))); |
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1008 |
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1009 __ bind(no_alternative_target); |
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1010 #endif |
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1011 |
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1012 // 6243940 We might end up in handle_wrong_method if |
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1013 // the callee is deoptimized as we race thru here. If that |
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1014 // happens we don't want to take a safepoint because the |
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1015 // caller frame will look interpreted and arguments are now |
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1016 // "compiled" so it is much better to make this transition |
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1017 // invisible to the stack walking code. Unfortunately if |
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1018 // we try and find the callee by normal means a safepoint |
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1019 // is possible. So we stash the desired callee in the thread |
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1020 // and the vm will find there should this case occur. |
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1021 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); |
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1022 __ st_ptr(G5_method, callee_target_addr); |
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1023 __ jmpl(G3, 0, G0); |
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1024 __ delayed()->nop(); |
| 0 | 1025 } |
| 1026 | |
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1027 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, |
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1028 int total_args_passed, |
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1029 int comp_args_on_stack, |
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1030 const BasicType *sig_bt, |
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1031 const VMRegPair *regs, |
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1032 int frame_extension_argument) { |
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1033 AdapterGenerator agen(masm); |
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1034 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, frame_extension_argument); |
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1035 } |
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1036 |
| 0 | 1037 // --------------------------------------------------------------- |
| 1038 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, | |
| 1039 int total_args_passed, | |
| 1040 // VMReg max_arg, | |
| 1041 int comp_args_on_stack, // VMRegStackSlots | |
| 1042 const BasicType *sig_bt, | |
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1043 const VMRegPair *regs, |
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1044 AdapterFingerPrint* fingerprint) { |
| 0 | 1045 address i2c_entry = __ pc(); |
| 1046 | |
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1047 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); |
| 0 | 1048 |
| 1049 | |
| 1050 // ------------------------------------------------------------------------- | |
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1051 // Generate a C2I adapter. On entry we know G5 holds the Method*. The |
| 0 | 1052 // args start out packed in the compiled layout. They need to be unpacked |
| 1053 // into the interpreter layout. This will almost always require some stack | |
| 1054 // space. We grow the current (compiled) stack, then repack the args. We | |
| 1055 // finally end in a jump to the generic interpreter entry point. On exit | |
| 1056 // from the interpreter, the interpreter will restore our SP (lest the | |
| 1057 // compiled code, which relys solely on SP and not FP, get sick). | |
| 1058 | |
| 1059 address c2i_unverified_entry = __ pc(); | |
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1060 Label L_skip_fixup; |
| 0 | 1061 { |
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1062 Register R_temp = G1; // another scratch register |
| 0 | 1063 |
| 727 | 1064 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
| 0 | 1065 |
| 1066 __ verify_oop(O0); | |
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1067 __ load_klass(O0, G3_scratch); |
| 0 | 1068 |
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1069 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); |
| 0 | 1070 __ cmp(G3_scratch, R_temp); |
| 1071 | |
| 1072 Label ok, ok2; | |
| 1073 __ brx(Assembler::equal, false, Assembler::pt, ok); | |
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1074 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); |
| 727 | 1075 __ jump_to(ic_miss, G3_scratch); |
| 0 | 1076 __ delayed()->nop(); |
| 1077 | |
| 1078 __ bind(ok); | |
| 1079 // Method might have been compiled since the call site was patched to | |
| 1080 // interpreted if that is the case treat it as a miss so we can get | |
| 1081 // the call site corrected. | |
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1082 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
| 0 | 1083 __ bind(ok2); |
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1084 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup); |
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1085 __ delayed()->nop(); |
| 727 | 1086 __ jump_to(ic_miss, G3_scratch); |
| 0 | 1087 __ delayed()->nop(); |
| 1088 | |
| 1089 } | |
| 1090 | |
| 1091 address c2i_entry = __ pc(); | |
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1092 AdapterGenerator agen(masm); |
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1093 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup); |
| 0 | 1094 |
| 1095 __ flush(); | |
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1096 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); |
| 0 | 1097 |
| 1098 } | |
| 1099 | |
| 1100 // Helper function for native calling conventions | |
| 1101 static VMReg int_stk_helper( int i ) { | |
| 1102 // Bias any stack based VMReg we get by ignoring the window area | |
| 1103 // but not the register parameter save area. | |
| 1104 // | |
| 1105 // This is strange for the following reasons. We'd normally expect | |
| 1106 // the calling convention to return an VMReg for a stack slot | |
| 1107 // completely ignoring any abi reserved area. C2 thinks of that | |
| 1108 // abi area as only out_preserve_stack_slots. This does not include | |
| 1109 // the area allocated by the C abi to store down integer arguments | |
| 1110 // because the java calling convention does not use it. So | |
| 1111 // since c2 assumes that there are only out_preserve_stack_slots | |
| 1112 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack | |
| 1113 // location the c calling convention must add in this bias amount | |
| 1114 // to make up for the fact that the out_preserve_stack_slots is | |
| 1115 // insufficient for C calls. What a mess. I sure hope those 6 | |
| 1116 // stack words were worth it on every java call! | |
| 1117 | |
| 1118 // Another way of cleaning this up would be for out_preserve_stack_slots | |
| 1119 // to take a parameter to say whether it was C or java calling conventions. | |
| 1120 // Then things might look a little better (but not much). | |
| 1121 | |
| 1122 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM; | |
| 1123 if( mem_parm_offset < 0 ) { | |
| 1124 return as_oRegister(i)->as_VMReg(); | |
| 1125 } else { | |
| 1126 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word; | |
| 1127 // Now return a biased offset that will be correct when out_preserve_slots is added back in | |
| 1128 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots()); | |
| 1129 } | |
| 1130 } | |
| 1131 | |
| 1132 | |
| 1133 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, | |
| 1134 VMRegPair *regs, | |
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1135 VMRegPair *regs2, |
| 0 | 1136 int total_args_passed) { |
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1137 assert(regs2 == NULL, "not needed on sparc"); |
| 0 | 1138 |
| 1139 // Return the number of VMReg stack_slots needed for the args. | |
| 1140 // This value does not include an abi space (like register window | |
| 1141 // save area). | |
| 1142 | |
| 1143 // The native convention is V8 if !LP64 | |
| 1144 // The LP64 convention is the V9 convention which is slightly more sane. | |
| 1145 | |
| 1146 // We return the amount of VMReg stack slots we need to reserve for all | |
| 1147 // the arguments NOT counting out_preserve_stack_slots. Since we always | |
| 1148 // have space for storing at least 6 registers to memory we start with that. | |
| 1149 // See int_stk_helper for a further discussion. | |
| 1150 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots(); | |
| 1151 | |
| 1152 #ifdef _LP64 | |
| 1153 // V9 convention: All things "as-if" on double-wide stack slots. | |
| 1154 // Hoist any int/ptr/long's in the first 6 to int regs. | |
| 1155 // Hoist any flt/dbl's in the first 16 dbl regs. | |
| 1156 int j = 0; // Count of actual args, not HALVES | |
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1157 VMRegPair param_array_reg; // location of the argument in the parameter array |
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1158 for (int i = 0; i < total_args_passed; i++, j++) { |
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1159 param_array_reg.set_bad(); |
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1160 switch (sig_bt[i]) { |
| 0 | 1161 case T_BOOLEAN: |
| 1162 case T_BYTE: | |
| 1163 case T_CHAR: | |
| 1164 case T_INT: | |
| 1165 case T_SHORT: | |
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1166 regs[i].set1(int_stk_helper(j)); |
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1167 break; |
| 0 | 1168 case T_LONG: |
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1169 assert(sig_bt[i+1] == T_VOID, "expecting half"); |
| 0 | 1170 case T_ADDRESS: // raw pointers, like current thread, for VM calls |
| 1171 case T_ARRAY: | |
| 1172 case T_OBJECT: | |
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1173 case T_METADATA: |
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1174 regs[i].set2(int_stk_helper(j)); |
| 0 | 1175 break; |
| 1176 case T_FLOAT: | |
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1177 // Per SPARC Compliance Definition 2.4.1, page 3P-12 available here |
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1178 // http://www.sparc.org/wp-content/uploads/2014/01/SCD.2.4.1.pdf.gz |
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1179 // |
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1180 // "When a callee prototype exists, and does not indicate variable arguments, |
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1181 // floating-point values assigned to locations %sp+BIAS+128 through %sp+BIAS+248 |
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1182 // will be promoted to floating-point registers" |
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1183 // |
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1184 // By "promoted" it means that the argument is located in two places, an unused |
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1185 // spill slot in the "parameter array" (starts at %sp+BIAS+128), and a live |
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1186 // float register. In most cases, there are 6 or fewer arguments of any type, |
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1187 // and the standard parameter array slots (%sp+BIAS+128 to %sp+BIAS+176 exclusive) |
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1188 // serve as shadow slots. Per the spec floating point registers %d6 to %d16 |
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1189 // require slots beyond that (up to %sp+BIAS+248). |
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1190 // |
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1191 { |
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1192 // V9ism: floats go in ODD registers and stack slots |
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1193 int float_index = 1 + (j << 1); |
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1194 param_array_reg.set1(VMRegImpl::stack2reg(float_index)); |
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1195 if (j < 16) { |
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1196 regs[i].set1(as_FloatRegister(float_index)->as_VMReg()); |
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1197 } else { |
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1198 regs[i] = param_array_reg; |
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1199 } |
| 0 | 1200 } |
| 1201 break; | |
| 1202 case T_DOUBLE: | |
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1203 { |
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1204 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
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1205 // V9ism: doubles go in EVEN/ODD regs and stack slots |
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1206 int double_index = (j << 1); |
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1207 param_array_reg.set2(VMRegImpl::stack2reg(double_index)); |
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1208 if (j < 16) { |
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1209 regs[i].set2(as_FloatRegister(double_index)->as_VMReg()); |
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1210 } else { |
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1211 // V9ism: doubles go in EVEN/ODD stack slots |
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1212 regs[i] = param_array_reg; |
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1213 } |
| 0 | 1214 } |
| 1215 break; | |
|
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1216 case T_VOID: |
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1217 regs[i].set_bad(); |
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1218 j--; |
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1219 break; // Do not count HALVES |
| 0 | 1220 default: |
| 1221 ShouldNotReachHere(); | |
| 1222 } | |
|
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1223 // Keep track of the deepest parameter array slot. |
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1224 if (!param_array_reg.first()->is_valid()) { |
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1225 param_array_reg = regs[i]; |
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1226 } |
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1227 if (param_array_reg.first()->is_stack()) { |
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1228 int off = param_array_reg.first()->reg2stack(); |
| 0 | 1229 if (off > max_stack_slots) max_stack_slots = off; |
| 1230 } | |
|
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1231 if (param_array_reg.second()->is_stack()) { |
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1232 int off = param_array_reg.second()->reg2stack(); |
| 0 | 1233 if (off > max_stack_slots) max_stack_slots = off; |
| 1234 } | |
| 1235 } | |
| 1236 | |
| 1237 #else // _LP64 | |
| 1238 // V8 convention: first 6 things in O-regs, rest on stack. | |
| 1239 // Alignment is willy-nilly. | |
|
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1240 for (int i = 0; i < total_args_passed; i++) { |
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1241 switch (sig_bt[i]) { |
| 0 | 1242 case T_ADDRESS: // raw pointers, like current thread, for VM calls |
| 1243 case T_ARRAY: | |
| 1244 case T_BOOLEAN: | |
| 1245 case T_BYTE: | |
| 1246 case T_CHAR: | |
| 1247 case T_FLOAT: | |
| 1248 case T_INT: | |
| 1249 case T_OBJECT: | |
|
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1250 case T_METADATA: |
| 0 | 1251 case T_SHORT: |
|
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1252 regs[i].set1(int_stk_helper(i)); |
| 0 | 1253 break; |
| 1254 case T_DOUBLE: | |
| 1255 case T_LONG: | |
|
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1256 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
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1257 regs[i].set_pair(int_stk_helper(i + 1), int_stk_helper(i)); |
| 0 | 1258 break; |
| 1259 case T_VOID: regs[i].set_bad(); break; | |
| 1260 default: | |
| 1261 ShouldNotReachHere(); | |
| 1262 } | |
| 1263 if (regs[i].first()->is_stack()) { | |
|
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1264 int off = regs[i].first()->reg2stack(); |
| 0 | 1265 if (off > max_stack_slots) max_stack_slots = off; |
| 1266 } | |
| 1267 if (regs[i].second()->is_stack()) { | |
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1268 int off = regs[i].second()->reg2stack(); |
| 0 | 1269 if (off > max_stack_slots) max_stack_slots = off; |
| 1270 } | |
| 1271 } | |
| 1272 #endif // _LP64 | |
| 1273 | |
| 1274 return round_to(max_stack_slots + 1, 2); | |
| 1275 | |
| 1276 } | |
| 1277 | |
| 1278 | |
| 1279 // --------------------------------------------------------------------------- | |
| 1280 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
| 1281 switch (ret_type) { | |
| 1282 case T_FLOAT: | |
| 1283 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS); | |
| 1284 break; | |
| 1285 case T_DOUBLE: | |
| 1286 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS); | |
| 1287 break; | |
| 1288 } | |
| 1289 } | |
| 1290 | |
| 1291 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
| 1292 switch (ret_type) { | |
| 1293 case T_FLOAT: | |
| 1294 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0); | |
| 1295 break; | |
| 1296 case T_DOUBLE: | |
| 1297 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0); | |
| 1298 break; | |
| 1299 } | |
| 1300 } | |
| 1301 | |
| 1302 // Check and forward and pending exception. Thread is stored in | |
| 1303 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there | |
| 1304 // is no exception handler. We merely pop this frame off and throw the | |
| 1305 // exception in the caller's frame. | |
| 1306 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) { | |
| 1307 Label L; | |
| 1308 __ br_null(Rex_oop, false, Assembler::pt, L); | |
| 1309 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception | |
| 1310 // Since this is a native call, we *know* the proper exception handler | |
| 1311 // without calling into the VM: it's the empty function. Just pop this | |
| 1312 // frame and then jump to forward_exception_entry; O7 will contain the | |
| 1313 // native caller's return PC. | |
| 727 | 1314 AddressLiteral exception_entry(StubRoutines::forward_exception_entry()); |
| 1315 __ jump_to(exception_entry, G3_scratch); | |
| 0 | 1316 __ delayed()->restore(); // Pop this frame off. |
| 1317 __ bind(L); | |
| 1318 } | |
| 1319 | |
| 1320 // A simple move of integer like type | |
| 1321 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1322 if (src.first()->is_stack()) { | |
| 1323 if (dst.first()->is_stack()) { | |
| 1324 // stack to stack | |
| 1325 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1326 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1327 } else { | |
| 1328 // stack to reg | |
| 1329 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1330 } | |
| 1331 } else if (dst.first()->is_stack()) { | |
| 1332 // reg to stack | |
| 1333 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1334 } else { | |
| 1335 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1336 } | |
| 1337 } | |
| 1338 | |
| 1339 // On 64 bit we will store integer like items to the stack as | |
| 1340 // 64 bits items (sparc abi) even though java would only store | |
| 1341 // 32bits for a parameter. On 32bit it will simply be 32 bits | |
| 1342 // So this routine will do 32->32 on 32bit and 32->64 on 64bit | |
| 1343 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1344 if (src.first()->is_stack()) { | |
| 1345 if (dst.first()->is_stack()) { | |
| 1346 // stack to stack | |
| 1347 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1348 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1349 } else { | |
| 1350 // stack to reg | |
| 1351 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1352 } | |
| 1353 } else if (dst.first()->is_stack()) { | |
| 1354 // reg to stack | |
| 1355 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1356 } else { | |
| 1357 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1358 } | |
| 1359 } | |
| 1360 | |
| 1361 | |
|
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1362 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { |
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1363 if (src.first()->is_stack()) { |
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1364 if (dst.first()->is_stack()) { |
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1365 // stack to stack |
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1366 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5); |
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1367 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); |
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1368 } else { |
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1369 // stack to reg |
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1370 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
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1371 } |
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1372 } else if (dst.first()->is_stack()) { |
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1373 // reg to stack |
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1374 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); |
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1375 } else { |
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1376 __ mov(src.first()->as_Register(), dst.first()->as_Register()); |
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1377 } |
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1378 } |
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1379 |
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1380 |
| 0 | 1381 // An oop arg. Must pass a handle not the oop itself |
| 1382 static void object_move(MacroAssembler* masm, | |
| 1383 OopMap* map, | |
| 1384 int oop_handle_offset, | |
| 1385 int framesize_in_slots, | |
| 1386 VMRegPair src, | |
| 1387 VMRegPair dst, | |
| 1388 bool is_receiver, | |
| 1389 int* receiver_offset) { | |
| 1390 | |
| 1391 // must pass a handle. First figure out the location we use as a handle | |
| 1392 | |
| 1393 if (src.first()->is_stack()) { | |
| 1394 // Oop is already on the stack | |
| 1395 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register(); | |
| 1396 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle); | |
| 1397 __ ld_ptr(rHandle, 0, L4); | |
| 1398 #ifdef _LP64 | |
| 1399 __ movr( Assembler::rc_z, L4, G0, rHandle ); | |
| 1400 #else | |
| 1401 __ tst( L4 ); | |
| 1402 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
| 1403 #endif | |
| 1404 if (dst.first()->is_stack()) { | |
| 1405 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1406 } | |
| 1407 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); | |
| 1408 if (is_receiver) { | |
| 1409 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; | |
| 1410 } | |
| 1411 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); | |
| 1412 } else { | |
| 1413 // Oop is in an input register pass we must flush it to the stack | |
| 1414 const Register rOop = src.first()->as_Register(); | |
| 1415 const Register rHandle = L5; | |
| 1416 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset; | |
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1417 int offset = oop_slot * VMRegImpl::stack_slot_size; |
| 0 | 1418 __ st_ptr(rOop, SP, offset + STACK_BIAS); |
| 1419 if (is_receiver) { | |
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1420 *receiver_offset = offset; |
| 0 | 1421 } |
| 1422 map->set_oop(VMRegImpl::stack2reg(oop_slot)); | |
| 1423 __ add(SP, offset + STACK_BIAS, rHandle); | |
| 1424 #ifdef _LP64 | |
| 1425 __ movr( Assembler::rc_z, rOop, G0, rHandle ); | |
| 1426 #else | |
| 1427 __ tst( rOop ); | |
| 1428 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
| 1429 #endif | |
| 1430 | |
| 1431 if (dst.first()->is_stack()) { | |
| 1432 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1433 } else { | |
| 1434 __ mov(rHandle, dst.first()->as_Register()); | |
| 1435 } | |
| 1436 } | |
| 1437 } | |
| 1438 | |
| 1439 // A float arg may have to do float reg int reg conversion | |
| 1440 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1441 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); | |
| 1442 | |
| 1443 if (src.first()->is_stack()) { | |
| 1444 if (dst.first()->is_stack()) { | |
| 1445 // stack to stack the easiest of the bunch | |
| 1446 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1447 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1448 } else { | |
| 1449 // stack to reg | |
| 1450 if (dst.first()->is_Register()) { | |
| 1451 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1452 } else { | |
| 1453 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1454 } | |
| 1455 } | |
| 1456 } else if (dst.first()->is_stack()) { | |
| 1457 // reg to stack | |
| 1458 if (src.first()->is_Register()) { | |
| 1459 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1460 } else { | |
| 1461 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1462 } | |
| 1463 } else { | |
| 1464 // reg to reg | |
| 1465 if (src.first()->is_Register()) { | |
| 1466 if (dst.first()->is_Register()) { | |
| 1467 // gpr -> gpr | |
| 1468 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1469 } else { | |
| 1470 // gpr -> fpr | |
| 1471 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS); | |
| 1472 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1473 } | |
| 1474 } else if (dst.first()->is_Register()) { | |
| 1475 // fpr -> gpr | |
| 1476 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS); | |
| 1477 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register()); | |
| 1478 } else { | |
| 1479 // fpr -> fpr | |
| 1480 // In theory these overlap but the ordering is such that this is likely a nop | |
| 1481 if ( src.first() != dst.first()) { | |
| 1482 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
| 1483 } | |
| 1484 } | |
| 1485 } | |
| 1486 } | |
| 1487 | |
| 1488 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1489 VMRegPair src_lo(src.first()); | |
| 1490 VMRegPair src_hi(src.second()); | |
| 1491 VMRegPair dst_lo(dst.first()); | |
| 1492 VMRegPair dst_hi(dst.second()); | |
| 1493 simple_move32(masm, src_lo, dst_lo); | |
| 1494 simple_move32(masm, src_hi, dst_hi); | |
| 1495 } | |
| 1496 | |
| 1497 // A long move | |
| 1498 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1499 | |
| 1500 // Do the simple ones here else do two int moves | |
| 1501 if (src.is_single_phys_reg() ) { | |
| 1502 if (dst.is_single_phys_reg()) { | |
| 1503 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1504 } else { | |
| 1505 // split src into two separate registers | |
| 1506 // Remember hi means hi address or lsw on sparc | |
| 1507 // Move msw to lsw | |
| 1508 if (dst.second()->is_reg()) { | |
| 1509 // MSW -> MSW | |
| 1510 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register()); | |
| 1511 // Now LSW -> LSW | |
| 1512 // this will only move lo -> lo and ignore hi | |
| 1513 VMRegPair split(dst.second()); | |
| 1514 simple_move32(masm, src, split); | |
| 1515 } else { | |
| 1516 VMRegPair split(src.first(), L4->as_VMReg()); | |
| 1517 // MSW -> MSW (lo ie. first word) | |
| 1518 __ srax(src.first()->as_Register(), 32, L4); | |
| 1519 split_long_move(masm, split, dst); | |
| 1520 } | |
| 1521 } | |
| 1522 } else if (dst.is_single_phys_reg()) { | |
| 1523 if (src.is_adjacent_aligned_on_stack(2)) { | |
| 304 | 1524 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
| 0 | 1525 } else { |
| 1526 // dst is a single reg. | |
| 1527 // Remember lo is low address not msb for stack slots | |
| 1528 // and lo is the "real" register for registers | |
| 1529 // src is | |
| 1530 | |
| 1531 VMRegPair split; | |
| 1532 | |
| 1533 if (src.first()->is_reg()) { | |
| 1534 // src.lo (msw) is a reg, src.hi is stk/reg | |
| 1535 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg] | |
| 1536 split.set_pair(dst.first(), src.first()); | |
| 1537 } else { | |
| 1538 // msw is stack move to L5 | |
| 1539 // lsw is stack move to dst.lo (real reg) | |
| 1540 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5 | |
| 1541 split.set_pair(dst.first(), L5->as_VMReg()); | |
| 1542 } | |
| 1543 | |
| 1544 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg) | |
| 1545 // msw -> src.lo/L5, lsw -> dst.lo | |
| 1546 split_long_move(masm, src, split); | |
| 1547 | |
| 1548 // So dst now has the low order correct position the | |
| 1549 // msw half | |
| 1550 __ sllx(split.first()->as_Register(), 32, L5); | |
| 1551 | |
| 1552 const Register d = dst.first()->as_Register(); | |
| 1553 __ or3(L5, d, d); | |
| 1554 } | |
| 1555 } else { | |
| 1556 // For LP64 we can probably do better. | |
| 1557 split_long_move(masm, src, dst); | |
| 1558 } | |
| 1559 } | |
| 1560 | |
| 1561 // A double move | |
| 1562 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1563 | |
| 1564 // The painful thing here is that like long_move a VMRegPair might be | |
| 1565 // 1: a single physical register | |
| 1566 // 2: two physical registers (v8) | |
| 1567 // 3: a physical reg [lo] and a stack slot [hi] (v8) | |
| 1568 // 4: two stack slots | |
| 1569 | |
| 1570 // Since src is always a java calling convention we know that the src pair | |
| 1571 // is always either all registers or all stack (and aligned?) | |
| 1572 | |
| 1573 // in a register [lo] and a stack slot [hi] | |
| 1574 if (src.first()->is_stack()) { | |
| 1575 if (dst.first()->is_stack()) { | |
| 1576 // stack to stack the easiest of the bunch | |
| 1577 // ought to be a way to do this where if alignment is ok we use ldd/std when possible | |
| 1578 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1579 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
| 1580 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1581 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1582 } else { | |
| 1583 // stack to reg | |
| 1584 if (dst.second()->is_stack()) { | |
| 1585 // stack -> reg, stack -> stack | |
| 1586 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
| 1587 if (dst.first()->is_Register()) { | |
| 1588 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1589 } else { | |
| 1590 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1591 } | |
| 1592 // This was missing. (very rare case) | |
| 1593 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1594 } else { | |
| 1595 // stack -> reg | |
| 1596 // Eventually optimize for alignment QQQ | |
| 1597 if (dst.first()->is_Register()) { | |
| 1598 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1599 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register()); | |
| 1600 } else { | |
| 1601 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1602 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister()); | |
| 1603 } | |
| 1604 } | |
| 1605 } | |
| 1606 } else if (dst.first()->is_stack()) { | |
| 1607 // reg to stack | |
| 1608 if (src.first()->is_Register()) { | |
| 1609 // Eventually optimize for alignment QQQ | |
| 1610 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1611 if (src.second()->is_stack()) { | |
| 1612 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
| 1613 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1614 } else { | |
| 1615 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1616 } | |
| 1617 } else { | |
| 1618 // fpr to stack | |
| 1619 if (src.second()->is_stack()) { | |
| 1620 ShouldNotReachHere(); | |
| 1621 } else { | |
| 1622 // Is the stack aligned? | |
| 1623 if (reg2offset(dst.first()) & 0x7) { | |
| 1624 // No do as pairs | |
| 1625 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1626 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1627 } else { | |
| 1628 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1629 } | |
| 1630 } | |
| 1631 } | |
| 1632 } else { | |
| 1633 // reg to reg | |
| 1634 if (src.first()->is_Register()) { | |
| 1635 if (dst.first()->is_Register()) { | |
| 1636 // gpr -> gpr | |
| 1637 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1638 __ mov(src.second()->as_Register(), dst.second()->as_Register()); | |
| 1639 } else { | |
| 1640 // gpr -> fpr | |
| 1641 // ought to be able to do a single store | |
| 1642 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS); | |
| 1643 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS); | |
| 1644 // ought to be able to do a single load | |
| 1645 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1646 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister()); | |
| 1647 } | |
| 1648 } else if (dst.first()->is_Register()) { | |
| 1649 // fpr -> gpr | |
| 1650 // ought to be able to do a single store | |
| 1651 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS); | |
| 1652 // ought to be able to do a single load | |
| 1653 // REMEMBER first() is low address not LSB | |
| 1654 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register()); | |
| 1655 if (dst.second()->is_Register()) { | |
| 1656 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register()); | |
| 1657 } else { | |
| 1658 __ ld(FP, -4 + STACK_BIAS, L4); | |
| 1659 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1660 } | |
| 1661 } else { | |
| 1662 // fpr -> fpr | |
| 1663 // In theory these overlap but the ordering is such that this is likely a nop | |
| 1664 if ( src.first() != dst.first()) { | |
| 1665 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
| 1666 } | |
| 1667 } | |
| 1668 } | |
| 1669 } | |
| 1670 | |
| 1671 // Creates an inner frame if one hasn't already been created, and | |
| 1672 // saves a copy of the thread in L7_thread_cache | |
| 1673 static void create_inner_frame(MacroAssembler* masm, bool* already_created) { | |
| 1674 if (!*already_created) { | |
| 1675 __ save_frame(0); | |
| 1676 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below | |
| 1677 // Don't use save_thread because it smashes G2 and we merely want to save a | |
| 1678 // copy | |
| 1679 __ mov(G2_thread, L7_thread_cache); | |
| 1680 *already_created = true; | |
| 1681 } | |
| 1682 } | |
| 1683 | |
|
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1684 |
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1685 static void save_or_restore_arguments(MacroAssembler* masm, |
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1686 const int stack_slots, |
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1687 const int total_in_args, |
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1688 const int arg_save_area, |
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1689 OopMap* map, |
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1690 VMRegPair* in_regs, |
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1691 BasicType* in_sig_bt) { |
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1692 // if map is non-NULL then the code should store the values, |
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1693 // otherwise it should load them. |
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1694 if (map != NULL) { |
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1695 // Fill in the map |
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1696 for (int i = 0; i < total_in_args; i++) { |
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1697 if (in_sig_bt[i] == T_ARRAY) { |
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1698 if (in_regs[i].first()->is_stack()) { |
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1699 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); |
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1700 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); |
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1701 } else if (in_regs[i].first()->is_Register()) { |
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1702 map->set_oop(in_regs[i].first()); |
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1703 } else { |
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1704 ShouldNotReachHere(); |
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1705 } |
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1706 } |
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1707 } |
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1708 } |
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1709 |
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1710 // Save or restore double word values |
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1711 int handle_index = 0; |
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1712 for (int i = 0; i < total_in_args; i++) { |
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1713 int slot = handle_index + arg_save_area; |
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1714 int offset = slot * VMRegImpl::stack_slot_size; |
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1715 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) { |
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1716 const Register reg = in_regs[i].first()->as_Register(); |
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1717 if (reg->is_global()) { |
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1718 handle_index += 2; |
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1719 assert(handle_index <= stack_slots, "overflow"); |
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1720 if (map != NULL) { |
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1721 __ stx(reg, SP, offset + STACK_BIAS); |
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1722 } else { |
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1723 __ ldx(SP, offset + STACK_BIAS, reg); |
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1724 } |
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1725 } |
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1726 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) { |
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1727 handle_index += 2; |
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1728 assert(handle_index <= stack_slots, "overflow"); |
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1729 if (map != NULL) { |
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1730 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1731 } else { |
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1732 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1733 } |
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1734 } |
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1735 } |
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1736 // Save floats |
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1737 for (int i = 0; i < total_in_args; i++) { |
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1738 int slot = handle_index + arg_save_area; |
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1739 int offset = slot * VMRegImpl::stack_slot_size; |
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1740 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) { |
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1741 handle_index++; |
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1742 assert(handle_index <= stack_slots, "overflow"); |
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1743 if (map != NULL) { |
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1744 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1745 } else { |
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1746 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1747 } |
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1748 } |
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1749 } |
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1750 |
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1751 } |
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1752 |
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1753 |
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1754 // Check GC_locker::needs_gc and enter the runtime if it's true. This |
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1755 // keeps a new JNI critical region from starting until a GC has been |
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1756 // forced. Save down any oops in registers and describe them in an |
|
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1757 // OopMap. |
|
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1758 static void check_needs_gc_for_critical_native(MacroAssembler* masm, |
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1759 const int stack_slots, |
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1760 const int total_in_args, |
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1761 const int arg_save_area, |
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1762 OopMapSet* oop_maps, |
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1763 VMRegPair* in_regs, |
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1764 BasicType* in_sig_bt) { |
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1765 __ block_comment("check GC_locker::needs_gc"); |
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1766 Label cont; |
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1767 AddressLiteral sync_state(GC_locker::needs_gc_address()); |
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1768 __ load_bool_contents(sync_state, G3_scratch); |
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1769 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont); |
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1770 __ delayed()->nop(); |
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1771 |
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1772 // Save down any values that are live in registers and call into the |
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1773 // runtime to halt for a GC |
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1774 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1775 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1776 arg_save_area, map, in_regs, in_sig_bt); |
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1777 |
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1778 __ mov(G2_thread, L7_thread_cache); |
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1779 |
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1780 __ set_last_Java_frame(SP, noreg); |
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1781 |
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1782 __ block_comment("block_for_jni_critical"); |
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1783 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type); |
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1784 __ delayed()->mov(L7_thread_cache, O0); |
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1785 oop_maps->add_gc_map( __ offset(), map); |
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1786 |
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1787 __ restore_thread(L7_thread_cache); // restore G2_thread |
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1788 __ reset_last_Java_frame(); |
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1789 |
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1790 // Reload all the register arguments |
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1791 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1792 arg_save_area, NULL, in_regs, in_sig_bt); |
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1793 |
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1794 __ bind(cont); |
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1795 #ifdef ASSERT |
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1796 if (StressCriticalJNINatives) { |
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1797 // Stress register saving |
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1798 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1799 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1800 arg_save_area, map, in_regs, in_sig_bt); |
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1801 // Destroy argument registers |
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1802 for (int i = 0; i < total_in_args; i++) { |
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1803 if (in_regs[i].first()->is_Register()) { |
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1804 const Register reg = in_regs[i].first()->as_Register(); |
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1805 if (reg->is_global()) { |
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1806 __ mov(G0, reg); |
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1807 } |
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1808 } else if (in_regs[i].first()->is_FloatRegister()) { |
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1809 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister()); |
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1810 } |
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1811 } |
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1812 |
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1813 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1814 arg_save_area, NULL, in_regs, in_sig_bt); |
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1815 } |
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1816 #endif |
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1817 } |
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1818 |
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1819 // Unpack an array argument into a pointer to the body and the length |
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1820 // if the array is non-null, otherwise pass 0 for both. |
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1821 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { |
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1822 // Pass the length, ptr pair |
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1823 Label is_null, done; |
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1824 if (reg.first()->is_stack()) { |
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1825 VMRegPair tmp = reg64_to_VMRegPair(L2); |
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1826 // Load the arg up from the stack |
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1827 move_ptr(masm, reg, tmp); |
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1828 reg = tmp; |
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1829 } |
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1830 __ cmp(reg.first()->as_Register(), G0); |
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1831 __ brx(Assembler::equal, false, Assembler::pt, is_null); |
|
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1832 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4); |
|
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1833 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg); |
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1834 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4); |
|
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1835 move32_64(masm, reg64_to_VMRegPair(L4), length_arg); |
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1836 __ ba_short(done); |
|
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1837 __ bind(is_null); |
|
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1838 // Pass zeros |
|
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1839 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg); |
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1840 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); |
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1841 __ bind(done); |
|
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1842 } |
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1843 |
|
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1844 static void verify_oop_args(MacroAssembler* masm, |
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1845 methodHandle method, |
|
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1846 const BasicType* sig_bt, |
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1847 const VMRegPair* regs) { |
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1848 Register temp_reg = G5_method; // not part of any compiled calling seq |
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1849 if (VerifyOops) { |
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1850 for (int i = 0; i < method->size_of_parameters(); i++) { |
|
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1851 if (sig_bt[i] == T_OBJECT || |
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1852 sig_bt[i] == T_ARRAY) { |
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1853 VMReg r = regs[i].first(); |
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1854 assert(r->is_valid(), "bad oop arg"); |
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1855 if (r->is_stack()) { |
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1856 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1857 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg); |
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1858 __ ld_ptr(SP, ld_off, temp_reg); |
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1859 __ verify_oop(temp_reg); |
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1860 } else { |
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1861 __ verify_oop(r->as_Register()); |
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1862 } |
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1863 } |
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1864 } |
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1865 } |
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1866 } |
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1867 |
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1868 static void gen_special_dispatch(MacroAssembler* masm, |
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1869 methodHandle method, |
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1870 const BasicType* sig_bt, |
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1871 const VMRegPair* regs) { |
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1872 verify_oop_args(masm, method, sig_bt, regs); |
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1873 vmIntrinsics::ID iid = method->intrinsic_id(); |
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1874 |
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1875 // Now write the args into the outgoing interpreter space |
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1876 bool has_receiver = false; |
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1877 Register receiver_reg = noreg; |
|
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1878 int member_arg_pos = -1; |
|
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1879 Register member_reg = noreg; |
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1880 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); |
|
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1881 if (ref_kind != 0) { |
|
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1882 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument |
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1883 member_reg = G5_method; // known to be free at this point |
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1884 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); |
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1885 } else if (iid == vmIntrinsics::_invokeBasic) { |
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1886 has_receiver = true; |
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1887 } else { |
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1888 fatal(err_msg_res("unexpected intrinsic id %d", iid)); |
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1889 } |
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1890 |
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1891 if (member_reg != noreg) { |
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1892 // Load the member_arg into register, if necessary. |
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1893 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); |
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1894 VMReg r = regs[member_arg_pos].first(); |
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1895 if (r->is_stack()) { |
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1896 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1897 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
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1898 __ ld_ptr(SP, ld_off, member_reg); |
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1899 } else { |
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1900 // no data motion is needed |
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1901 member_reg = r->as_Register(); |
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1902 } |
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1903 } |
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1904 |
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1905 if (has_receiver) { |
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1906 // Make sure the receiver is loaded into a register. |
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1907 assert(method->size_of_parameters() > 0, "oob"); |
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1908 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); |
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1909 VMReg r = regs[0].first(); |
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1910 assert(r->is_valid(), "bad receiver arg"); |
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1911 if (r->is_stack()) { |
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1912 // Porting note: This assumes that compiled calling conventions always |
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1913 // pass the receiver oop in a register. If this is not true on some |
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1914 // platform, pick a temp and load the receiver from stack. |
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1915 fatal("receiver always in a register"); |
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1916 receiver_reg = G3_scratch; // known to be free at this point |
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1917 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1918 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
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1919 __ ld_ptr(SP, ld_off, receiver_reg); |
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1920 } else { |
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1921 // no data motion is needed |
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1922 receiver_reg = r->as_Register(); |
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1923 } |
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1924 } |
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1925 |
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1926 // Figure out which address we are really jumping to: |
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1927 MethodHandles::generate_method_handle_dispatch(masm, iid, |
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1928 receiver_reg, member_reg, /*for_compiler_entry:*/ true); |
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1929 } |
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1930 |
| 0 | 1931 // --------------------------------------------------------------------------- |
| 1932 // Generate a native wrapper for a given method. The method takes arguments | |
| 1933 // in the Java compiled code convention, marshals them to the native | |
| 1934 // convention (handlizes oops, etc), transitions to native, makes the call, | |
| 1935 // returns to java state (possibly blocking), unhandlizes any result and | |
| 1936 // returns. | |
|
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1937 // |
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1938 // Critical native functions are a shorthand for the use of |
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1939 // GetPrimtiveArrayCritical and disallow the use of any other JNI |
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1940 // functions. The wrapper is expected to unpack the arguments before |
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1941 // passing them to the callee and perform checks before and after the |
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1942 // native call to ensure that they GC_locker |
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1943 // lock_critical/unlock_critical semantics are followed. Some other |
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1944 // parts of JNI setup are skipped like the tear down of the JNI handle |
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1945 // block and the check for pending exceptions it's impossible for them |
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1946 // to be thrown. |
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1947 // |
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1948 // They are roughly structured like this: |
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1949 // if (GC_locker::needs_gc()) |
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1950 // SharedRuntime::block_for_jni_critical(); |
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1951 // tranistion to thread_in_native |
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1952 // unpack arrray arguments and call native entry point |
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1953 // check for safepoint in progress |
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1954 // check if any thread suspend flags are set |
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1955 // call into JVM and possible unlock the JNI critical |
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1956 // if a GC was suppressed while in the critical native. |
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1957 // transition back to thread_in_Java |
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1958 // return to caller |
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1959 // |
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1960 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, |
| 0 | 1961 methodHandle method, |
|
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1962 int compile_id, |
|
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1963 BasicType* in_sig_bt, |
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1964 VMRegPair* in_regs, |
| 0 | 1965 BasicType ret_type) { |
|
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1966 if (method->is_method_handle_intrinsic()) { |
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1967 vmIntrinsics::ID iid = method->intrinsic_id(); |
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1968 intptr_t start = (intptr_t)__ pc(); |
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1969 int vep_offset = ((intptr_t)__ pc()) - start; |
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1970 gen_special_dispatch(masm, |
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1971 method, |
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1972 in_sig_bt, |
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1973 in_regs); |
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1974 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period |
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1975 __ flush(); |
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1976 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually |
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1977 return nmethod::new_native_nmethod(method, |
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1978 compile_id, |
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1979 masm->code(), |
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1980 vep_offset, |
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1981 frame_complete, |
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1982 stack_slots / VMRegImpl::slots_per_word, |
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1983 in_ByteSize(-1), |
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1984 in_ByteSize(-1), |
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1985 (OopMapSet*)NULL); |
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1986 } |
|
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1987 bool is_critical_native = true; |
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1988 address native_func = method->critical_native_function(); |
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1989 if (native_func == NULL) { |
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1990 native_func = method->native_function(); |
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1991 is_critical_native = false; |
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1992 } |
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1993 assert(native_func != NULL, "must have function"); |
| 0 | 1994 |
| 1995 // Native nmethod wrappers never take possesion of the oop arguments. | |
| 1996 // So the caller will gc the arguments. The only thing we need an | |
| 1997 // oopMap for is if the call is static | |
| 1998 // | |
| 1999 // An OopMap for lock (and class if static), and one for the VM call itself | |
| 2000 OopMapSet *oop_maps = new OopMapSet(); | |
| 2001 intptr_t start = (intptr_t)__ pc(); | |
| 2002 | |
| 2003 // First thing make an ic check to see if we should even be here | |
| 2004 { | |
| 2005 Label L; | |
| 2006 const Register temp_reg = G3_scratch; | |
| 727 | 2007 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
| 0 | 2008 __ verify_oop(O0); |
|
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2009 __ load_klass(O0, temp_reg); |
| 3839 | 2010 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
| 0 | 2011 |
| 727 | 2012 __ jump_to(ic_miss, temp_reg); |
| 0 | 2013 __ delayed()->nop(); |
| 2014 __ align(CodeEntryAlignment); | |
| 2015 __ bind(L); | |
| 2016 } | |
| 2017 | |
| 2018 int vep_offset = ((intptr_t)__ pc()) - start; | |
| 2019 | |
| 2020 #ifdef COMPILER1 | |
| 2021 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) { | |
| 2022 // Object.hashCode can pull the hashCode from the header word | |
| 2023 // instead of doing a full VM transition once it's been computed. | |
| 2024 // Since hashCode is usually polymorphic at call sites we can't do | |
| 2025 // this optimization at the call site without a lot of work. | |
| 2026 Label slowCase; | |
| 2027 Register receiver = O0; | |
| 2028 Register result = O0; | |
| 2029 Register header = G3_scratch; | |
| 2030 Register hash = G3_scratch; // overwrite header value with hash value | |
| 2031 Register mask = G1; // to get hash field from header | |
| 2032 | |
| 2033 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked. | |
| 2034 // We depend on hash_mask being at most 32 bits and avoid the use of | |
| 2035 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit | |
| 2036 // vm: see markOop.hpp. | |
| 2037 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header); | |
| 2038 __ sethi(markOopDesc::hash_mask, mask); | |
| 2039 __ btst(markOopDesc::unlocked_value, header); | |
| 2040 __ br(Assembler::zero, false, Assembler::pn, slowCase); | |
| 2041 if (UseBiasedLocking) { | |
| 2042 // Check if biased and fall through to runtime if so | |
| 2043 __ delayed()->nop(); | |
| 2044 __ btst(markOopDesc::biased_lock_bit_in_place, header); | |
| 2045 __ br(Assembler::notZero, false, Assembler::pn, slowCase); | |
| 2046 } | |
| 2047 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask); | |
| 2048 | |
| 2049 // Check for a valid (non-zero) hash code and get its value. | |
| 2050 #ifdef _LP64 | |
| 2051 __ srlx(header, markOopDesc::hash_shift, hash); | |
| 2052 #else | |
| 2053 __ srl(header, markOopDesc::hash_shift, hash); | |
| 2054 #endif | |
| 2055 __ andcc(hash, mask, hash); | |
| 2056 __ br(Assembler::equal, false, Assembler::pn, slowCase); | |
| 2057 __ delayed()->nop(); | |
| 2058 | |
| 2059 // leaf return. | |
| 2060 __ retl(); | |
| 2061 __ delayed()->mov(hash, result); | |
| 2062 __ bind(slowCase); | |
| 2063 } | |
| 2064 #endif // COMPILER1 | |
| 2065 | |
| 2066 | |
| 2067 // We have received a description of where all the java arg are located | |
| 2068 // on entry to the wrapper. We need to convert these args to where | |
| 2069 // the jni function will expect them. To figure out where they go | |
| 2070 // we convert the java signature to a C signature by inserting | |
| 2071 // the hidden arguments as arg[0] and possibly arg[1] (static method) | |
| 2072 | |
|
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2073 const int total_in_args = method->size_of_parameters(); |
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2074 int total_c_args = total_in_args; |
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2075 int total_save_slots = 6 * VMRegImpl::slots_per_word; |
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2076 if (!is_critical_native) { |
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2077 total_c_args += 1; |
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2078 if (method->is_static()) { |
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2079 total_c_args++; |
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2080 } |
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2081 } else { |
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2082 for (int i = 0; i < total_in_args; i++) { |
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2083 if (in_sig_bt[i] == T_ARRAY) { |
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2084 // These have to be saved and restored across the safepoint |
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2085 total_c_args++; |
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2086 } |
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2087 } |
| 0 | 2088 } |
| 2089 | |
| 2090 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); | |
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2091 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); |
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2092 BasicType* in_elem_bt = NULL; |
| 0 | 2093 |
| 2094 int argc = 0; | |
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2095 if (!is_critical_native) { |
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2096 out_sig_bt[argc++] = T_ADDRESS; |
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2097 if (method->is_static()) { |
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2098 out_sig_bt[argc++] = T_OBJECT; |
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2099 } |
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2100 |
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2101 for (int i = 0; i < total_in_args ; i++ ) { |
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2102 out_sig_bt[argc++] = in_sig_bt[i]; |
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2103 } |
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2104 } else { |
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2105 Thread* THREAD = Thread::current(); |
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2106 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); |
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2107 SignatureStream ss(method->signature()); |
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2108 for (int i = 0; i < total_in_args ; i++ ) { |
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2109 if (in_sig_bt[i] == T_ARRAY) { |
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2110 // Arrays are passed as int, elem* pair |
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2111 out_sig_bt[argc++] = T_INT; |
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2112 out_sig_bt[argc++] = T_ADDRESS; |
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2113 Symbol* atype = ss.as_symbol(CHECK_NULL); |
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2114 const char* at = atype->as_C_string(); |
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2115 if (strlen(at) == 2) { |
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2116 assert(at[0] == '[', "must be"); |
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2117 switch (at[1]) { |
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2118 case 'B': in_elem_bt[i] = T_BYTE; break; |
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2119 case 'C': in_elem_bt[i] = T_CHAR; break; |
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2120 case 'D': in_elem_bt[i] = T_DOUBLE; break; |
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2121 case 'F': in_elem_bt[i] = T_FLOAT; break; |
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2122 case 'I': in_elem_bt[i] = T_INT; break; |
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2123 case 'J': in_elem_bt[i] = T_LONG; break; |
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2124 case 'S': in_elem_bt[i] = T_SHORT; break; |
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2125 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; |
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2126 default: ShouldNotReachHere(); |
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2127 } |
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2128 } |
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2129 } else { |
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2130 out_sig_bt[argc++] = in_sig_bt[i]; |
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2131 in_elem_bt[i] = T_VOID; |
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2132 } |
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2133 if (in_sig_bt[i] != T_VOID) { |
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2134 assert(in_sig_bt[i] == ss.type(), "must match"); |
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2135 ss.next(); |
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2136 } |
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2137 } |
| 0 | 2138 } |
| 2139 | |
| 2140 // Now figure out where the args must be stored and how much stack space | |
| 2141 // they require (neglecting out_preserve_stack_slots but space for storing | |
| 2142 // the 1st six register arguments). It's weird see int_stk_helper. | |
| 2143 // | |
| 2144 int out_arg_slots; | |
|
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2145 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); |
| 0 | 2146 |
|
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2147 if (is_critical_native) { |
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2148 // Critical natives may have to call out so they need a save area |
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2149 // for register arguments. |
|
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2150 int double_slots = 0; |
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2151 int single_slots = 0; |
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2152 for ( int i = 0; i < total_in_args; i++) { |
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2153 if (in_regs[i].first()->is_Register()) { |
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2154 const Register reg = in_regs[i].first()->as_Register(); |
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2155 switch (in_sig_bt[i]) { |
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2156 case T_ARRAY: |
|
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2157 case T_BOOLEAN: |
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2158 case T_BYTE: |
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2159 case T_SHORT: |
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2160 case T_CHAR: |
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2161 case T_INT: assert(reg->is_in(), "don't need to save these"); break; |
|
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2162 case T_LONG: if (reg->is_global()) double_slots++; break; |
|
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2163 default: ShouldNotReachHere(); |
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2164 } |
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2165 } else if (in_regs[i].first()->is_FloatRegister()) { |
|
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2166 switch (in_sig_bt[i]) { |
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2167 case T_FLOAT: single_slots++; break; |
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2168 case T_DOUBLE: double_slots++; break; |
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2169 default: ShouldNotReachHere(); |
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2170 } |
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2171 } |
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2172 } |
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2173 total_save_slots = double_slots * 2 + single_slots; |
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2174 } |
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2175 |
| 0 | 2176 // Compute framesize for the wrapper. We need to handlize all oops in |
| 2177 // registers. We must create space for them here that is disjoint from | |
| 2178 // the windowed save area because we have no control over when we might | |
| 2179 // flush the window again and overwrite values that gc has since modified. | |
| 2180 // (The live window race) | |
| 2181 // | |
| 2182 // We always just allocate 6 word for storing down these object. This allow | |
| 2183 // us to simply record the base and use the Ireg number to decide which | |
| 2184 // slot to use. (Note that the reg number is the inbound number not the | |
| 2185 // outbound number). | |
| 2186 // We must shuffle args to match the native convention, and include var-args space. | |
| 2187 | |
| 2188 // Calculate the total number of stack slots we will need. | |
| 2189 | |
| 2190 // First count the abi requirement plus all of the outgoing args | |
| 2191 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; | |
| 2192 | |
| 2193 // Now the space for the inbound oop handle area | |
| 2194 | |
|
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2195 int oop_handle_offset = round_to(stack_slots, 2); |
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2196 stack_slots += total_save_slots; |
| 0 | 2197 |
| 2198 // Now any space we need for handlizing a klass if static method | |
| 2199 | |
| 2200 int klass_slot_offset = 0; | |
| 2201 int klass_offset = -1; | |
| 2202 int lock_slot_offset = 0; | |
| 2203 bool is_static = false; | |
| 2204 | |
| 2205 if (method->is_static()) { | |
| 2206 klass_slot_offset = stack_slots; | |
| 2207 stack_slots += VMRegImpl::slots_per_word; | |
| 2208 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; | |
| 2209 is_static = true; | |
| 2210 } | |
| 2211 | |
| 2212 // Plus a lock if needed | |
| 2213 | |
| 2214 if (method->is_synchronized()) { | |
| 2215 lock_slot_offset = stack_slots; | |
| 2216 stack_slots += VMRegImpl::slots_per_word; | |
| 2217 } | |
| 2218 | |
| 2219 // Now a place to save return value or as a temporary for any gpr -> fpr moves | |
| 2220 stack_slots += 2; | |
| 2221 | |
| 2222 // Ok The space we have allocated will look like: | |
| 2223 // | |
| 2224 // | |
| 2225 // FP-> | | | |
| 2226 // |---------------------| | |
| 2227 // | 2 slots for moves | | |
| 2228 // |---------------------| | |
| 2229 // | lock box (if sync) | | |
| 2230 // |---------------------| <- lock_slot_offset | |
| 2231 // | klass (if static) | | |
| 2232 // |---------------------| <- klass_slot_offset | |
| 2233 // | oopHandle area | | |
| 2234 // |---------------------| <- oop_handle_offset | |
| 2235 // | outbound memory | | |
| 2236 // | based arguments | | |
| 2237 // | | | |
| 2238 // |---------------------| | |
| 2239 // | vararg area | | |
| 2240 // |---------------------| | |
| 2241 // | | | |
| 2242 // SP-> | out_preserved_slots | | |
| 2243 // | |
| 2244 // | |
| 2245 | |
| 2246 | |
| 2247 // Now compute actual number of stack words we need rounding to make | |
| 2248 // stack properly aligned. | |
| 2249 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word); | |
| 2250 | |
| 2251 int stack_size = stack_slots * VMRegImpl::stack_slot_size; | |
| 2252 | |
| 2253 // Generate stack overflow check before creating frame | |
| 2254 __ generate_stack_overflow_check(stack_size); | |
| 2255 | |
| 2256 // Generate a new frame for the wrapper. | |
| 2257 __ save(SP, -stack_size, SP); | |
| 2258 | |
| 2259 int frame_complete = ((intptr_t)__ pc()) - start; | |
| 2260 | |
| 2261 __ verify_thread(); | |
| 2262 | |
|
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2263 if (is_critical_native) { |
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2264 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args, |
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2265 oop_handle_offset, oop_maps, in_regs, in_sig_bt); |
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2266 } |
| 0 | 2267 |
| 2268 // | |
| 2269 // We immediately shuffle the arguments so that any vm call we have to | |
| 2270 // make from here on out (sync slow path, jvmti, etc.) we will have | |
| 2271 // captured the oops from our caller and have a valid oopMap for | |
| 2272 // them. | |
| 2273 | |
| 2274 // ----------------- | |
| 2275 // The Grand Shuffle | |
| 2276 // | |
| 2277 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* | |
| 2278 // (derived from JavaThread* which is in L7_thread_cache) and, if static, | |
| 2279 // the class mirror instead of a receiver. This pretty much guarantees that | |
| 2280 // register layout will not match. We ignore these extra arguments during | |
| 2281 // the shuffle. The shuffle is described by the two calling convention | |
| 2282 // vectors we have in our possession. We simply walk the java vector to | |
| 2283 // get the source locations and the c vector to get the destinations. | |
| 2284 // Because we have a new window and the argument registers are completely | |
| 2285 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about | |
| 2286 // here. | |
| 2287 | |
| 2288 // This is a trick. We double the stack slots so we can claim | |
| 2289 // the oops in the caller's frame. Since we are sure to have | |
| 2290 // more args than the caller doubling is enough to make | |
| 2291 // sure we can capture all the incoming oop args from the | |
| 2292 // caller. | |
| 2293 // | |
| 2294 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); | |
| 2295 // Record sp-based slot for receiver on stack for non-static methods | |
| 2296 int receiver_offset = -1; | |
| 2297 | |
| 2298 // We move the arguments backward because the floating point registers | |
| 2299 // destination will always be to a register with a greater or equal register | |
| 2300 // number or the stack. | |
| 2301 | |
| 2302 #ifdef ASSERT | |
| 2303 bool reg_destroyed[RegisterImpl::number_of_registers]; | |
| 2304 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; | |
| 2305 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { | |
| 2306 reg_destroyed[r] = false; | |
| 2307 } | |
| 2308 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { | |
| 2309 freg_destroyed[f] = false; | |
| 2310 } | |
| 2311 | |
| 2312 #endif /* ASSERT */ | |
| 2313 | |
|
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2314 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) { |
| 0 | 2315 |
| 2316 #ifdef ASSERT | |
| 2317 if (in_regs[i].first()->is_Register()) { | |
| 2318 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!"); | |
| 2319 } else if (in_regs[i].first()->is_FloatRegister()) { | |
| 2320 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!"); | |
| 2321 } | |
| 2322 if (out_regs[c_arg].first()->is_Register()) { | |
| 2323 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; | |
| 2324 } else if (out_regs[c_arg].first()->is_FloatRegister()) { | |
| 2325 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true; | |
| 2326 } | |
| 2327 #endif /* ASSERT */ | |
| 2328 | |
| 2329 switch (in_sig_bt[i]) { | |
| 2330 case T_ARRAY: | |
|
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2331 if (is_critical_native) { |
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2332 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]); |
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2333 c_arg--; |
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2334 break; |
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2335 } |
| 0 | 2336 case T_OBJECT: |
|
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2337 assert(!is_critical_native, "no oop arguments"); |
| 0 | 2338 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], |
| 2339 ((i == 0) && (!is_static)), | |
| 2340 &receiver_offset); | |
| 2341 break; | |
| 2342 case T_VOID: | |
| 2343 break; | |
| 2344 | |
| 2345 case T_FLOAT: | |
| 2346 float_move(masm, in_regs[i], out_regs[c_arg]); | |
|
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2347 break; |
| 0 | 2348 |
| 2349 case T_DOUBLE: | |
| 2350 assert( i + 1 < total_in_args && | |
| 2351 in_sig_bt[i + 1] == T_VOID && | |
| 2352 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); | |
| 2353 double_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2354 break; | |
| 2355 | |
| 2356 case T_LONG : | |
| 2357 long_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2358 break; | |
| 2359 | |
| 2360 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); | |
| 2361 | |
| 2362 default: | |
| 2363 move32_64(masm, in_regs[i], out_regs[c_arg]); | |
| 2364 } | |
| 2365 } | |
| 2366 | |
| 2367 // Pre-load a static method's oop into O1. Used both by locking code and | |
| 2368 // the normal JNI call code. | |
|
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2369 if (method->is_static() && !is_critical_native) { |
|
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2370 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1); |
| 0 | 2371 |
| 2372 // Now handlize the static class mirror in O1. It's known not-null. | |
| 2373 __ st_ptr(O1, SP, klass_offset + STACK_BIAS); | |
| 2374 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); | |
| 2375 __ add(SP, klass_offset + STACK_BIAS, O1); | |
| 2376 } | |
| 2377 | |
| 2378 | |
| 2379 const Register L6_handle = L6; | |
| 2380 | |
| 2381 if (method->is_synchronized()) { | |
|
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2382 assert(!is_critical_native, "unhandled"); |
| 0 | 2383 __ mov(O1, L6_handle); |
| 2384 } | |
| 2385 | |
| 2386 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs | |
| 2387 // except O6/O7. So if we must call out we must push a new frame. We immediately | |
| 2388 // push a new frame and flush the windows. | |
| 2389 #ifdef _LP64 | |
| 2390 intptr_t thepc = (intptr_t) __ pc(); | |
| 2391 { | |
| 2392 address here = __ pc(); | |
| 2393 // Call the next instruction | |
| 2394 __ call(here + 8, relocInfo::none); | |
| 2395 __ delayed()->nop(); | |
| 2396 } | |
| 2397 #else | |
| 2398 intptr_t thepc = __ load_pc_address(O7, 0); | |
| 2399 #endif /* _LP64 */ | |
| 2400 | |
| 2401 // We use the same pc/oopMap repeatedly when we call out | |
| 2402 oop_maps->add_gc_map(thepc - start, map); | |
| 2403 | |
| 2404 // O7 now has the pc loaded that we will use when we finally call to native. | |
| 2405 | |
| 2406 // Save thread in L7; it crosses a bunch of VM calls below | |
| 2407 // Don't use save_thread because it smashes G2 and we merely | |
| 2408 // want to save a copy | |
| 2409 __ mov(G2_thread, L7_thread_cache); | |
| 2410 | |
| 2411 | |
| 2412 // If we create an inner frame once is plenty | |
| 2413 // when we create it we must also save G2_thread | |
| 2414 bool inner_frame_created = false; | |
| 2415 | |
| 2416 // dtrace method entry support | |
| 2417 { | |
| 2418 SkipIfEqual skip_if( | |
| 2419 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
| 2420 // create inner frame | |
| 2421 __ save_frame(0); | |
| 2422 __ mov(G2_thread, L7_thread_cache); | |
|
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2423 __ set_metadata_constant(method(), O1); |
| 0 | 2424 __ call_VM_leaf(L7_thread_cache, |
| 2425 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), | |
| 2426 G2_thread, O1); | |
| 2427 __ restore(); | |
| 2428 } | |
| 2429 | |
|
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2430 // RedefineClasses() tracing support for obsolete method entry |
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2431 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { |
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2432 // create inner frame |
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2433 __ save_frame(0); |
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2434 __ mov(G2_thread, L7_thread_cache); |
|
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2435 __ set_metadata_constant(method(), O1); |
|
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2436 __ call_VM_leaf(L7_thread_cache, |
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2437 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), |
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|
2438 G2_thread, O1); |
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2439 __ restore(); |
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2440 } |
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|
2441 |
| 0 | 2442 // We are in the jni frame unless saved_frame is true in which case |
| 2443 // we are in one frame deeper (the "inner" frame). If we are in the | |
| 2444 // "inner" frames the args are in the Iregs and if the jni frame then | |
| 2445 // they are in the Oregs. | |
| 2446 // If we ever need to go to the VM (for locking, jvmti) then | |
| 2447 // we will always be in the "inner" frame. | |
| 2448 | |
| 2449 // Lock a synchronized method | |
| 2450 int lock_offset = -1; // Set if locked | |
| 2451 if (method->is_synchronized()) { | |
| 2452 Register Roop = O1; | |
| 2453 const Register L3_box = L3; | |
| 2454 | |
| 2455 create_inner_frame(masm, &inner_frame_created); | |
| 2456 | |
| 2457 __ ld_ptr(I1, 0, O1); | |
| 2458 Label done; | |
| 2459 | |
| 2460 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size); | |
| 2461 __ add(FP, lock_offset+STACK_BIAS, L3_box); | |
| 2462 #ifdef ASSERT | |
| 2463 if (UseBiasedLocking) { | |
| 2464 // making the box point to itself will make it clear it went unused | |
| 2465 // but also be obviously invalid | |
| 2466 __ st_ptr(L3_box, L3_box, 0); | |
| 2467 } | |
| 2468 #endif // ASSERT | |
| 2469 // | |
| 2470 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch | |
| 2471 // | |
| 2472 __ compiler_lock_object(Roop, L1, L3_box, L2); | |
| 2473 __ br(Assembler::equal, false, Assembler::pt, done); | |
| 2474 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box); | |
| 2475 | |
| 2476 | |
| 2477 // None of the above fast optimizations worked so we have to get into the | |
| 2478 // slow case of monitor enter. Inline a special case of call_VM that | |
| 2479 // disallows any pending_exception. | |
| 2480 __ mov(Roop, O0); // Need oop in O0 | |
| 2481 __ mov(L3_box, O1); | |
| 2482 | |
| 2483 // Record last_Java_sp, in case the VM code releases the JVM lock. | |
| 2484 | |
| 2485 __ set_last_Java_frame(FP, I7); | |
| 2486 | |
| 2487 // do the call | |
| 2488 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); | |
| 2489 __ delayed()->mov(L7_thread_cache, O2); | |
| 2490 | |
| 2491 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2492 __ reset_last_Java_frame(); | |
| 2493 | |
| 2494 #ifdef ASSERT | |
| 2495 { Label L; | |
| 2496 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
| 3839 | 2497 __ br_null_short(O0, Assembler::pt, L); |
| 0 | 2498 __ stop("no pending exception allowed on exit from IR::monitorenter"); |
| 2499 __ bind(L); | |
| 2500 } | |
| 2501 #endif | |
| 2502 __ bind(done); | |
| 2503 } | |
| 2504 | |
| 2505 | |
| 2506 // Finally just about ready to make the JNI call | |
| 2507 | |
| 10997 | 2508 __ flushw(); |
| 0 | 2509 if (inner_frame_created) { |
| 2510 __ restore(); | |
| 2511 } else { | |
| 2512 // Store only what we need from this frame | |
| 2513 // QQQ I think that non-v9 (like we care) we don't need these saves | |
| 2514 // either as the flush traps and the current window goes too. | |
| 2515 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
| 2516 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
| 2517 } | |
| 2518 | |
| 2519 // get JNIEnv* which is first argument to native | |
|
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2520 if (!is_critical_native) { |
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2521 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0); |
|
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|
2522 } |
| 0 | 2523 |
| 2524 // Use that pc we placed in O7 a while back as the current frame anchor | |
| 2525 __ set_last_Java_frame(SP, O7); | |
| 2526 | |
|
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2527 // We flushed the windows ages ago now mark them as flushed before transitioning. |
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2528 __ set(JavaFrameAnchor::flushed, G3_scratch); |
|
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2529 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); |
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2530 |
| 0 | 2531 // Transition from _thread_in_Java to _thread_in_native. |
| 2532 __ set(_thread_in_native, G3_scratch); | |
| 2533 | |
| 2534 #ifdef _LP64 | |
|
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2535 AddressLiteral dest(native_func); |
| 0 | 2536 __ relocate(relocInfo::runtime_call_type); |
| 727 | 2537 __ jumpl_to(dest, O7, O7); |
| 0 | 2538 #else |
|
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|
2539 __ call(native_func, relocInfo::runtime_call_type); |
| 0 | 2540 #endif |
|
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|
2541 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
| 0 | 2542 |
| 2543 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2544 | |
| 2545 // Unpack native results. For int-types, we do any needed sign-extension | |
| 2546 // and move things into I0. The return value there will survive any VM | |
| 2547 // calls for blocking or unlocking. An FP or OOP result (handle) is done | |
| 2548 // specially in the slow-path code. | |
| 2549 switch (ret_type) { | |
| 2550 case T_VOID: break; // Nothing to do! | |
| 2551 case T_FLOAT: break; // Got it where we want it (unless slow-path) | |
| 2552 case T_DOUBLE: break; // Got it where we want it (unless slow-path) | |
| 2553 // In 64 bits build result is in O0, in O0, O1 in 32bit build | |
| 2554 case T_LONG: | |
| 2555 #ifndef _LP64 | |
| 2556 __ mov(O1, I1); | |
| 2557 #endif | |
| 2558 // Fall thru | |
| 2559 case T_OBJECT: // Really a handle | |
| 2560 case T_ARRAY: | |
| 2561 case T_INT: | |
| 2562 __ mov(O0, I0); | |
| 2563 break; | |
| 2564 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false | |
| 2565 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break; | |
| 2566 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value! | |
| 2567 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break; | |
| 2568 break; // Cannot de-handlize until after reclaiming jvm_lock | |
| 2569 default: | |
| 2570 ShouldNotReachHere(); | |
| 2571 } | |
| 2572 | |
|
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2573 Label after_transition; |
| 0 | 2574 // must we block? |
| 2575 | |
| 2576 // Block, if necessary, before resuming in _thread_in_Java state. | |
| 2577 // In order for GC to work, don't clear the last_Java_sp until after blocking. | |
| 2578 { Label no_block; | |
| 727 | 2579 AddressLiteral sync_state(SafepointSynchronize::address_of_state()); |
| 0 | 2580 |
| 2581 // Switch thread to "native transition" state before reading the synchronization state. | |
| 2582 // This additional state is necessary because reading and testing the synchronization | |
| 2583 // state is not atomic w.r.t. GC, as this scenario demonstrates: | |
| 2584 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. | |
| 2585 // VM thread changes sync state to synchronizing and suspends threads for GC. | |
| 2586 // Thread A is resumed to finish this native method, but doesn't block here since it | |
| 2587 // didn't see any synchronization is progress, and escapes. | |
| 2588 __ set(_thread_in_native_trans, G3_scratch); | |
| 727 | 2589 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
| 0 | 2590 if(os::is_MP()) { |
| 2591 if (UseMembar) { | |
| 2592 // Force this write out before the read below | |
| 2593 __ membar(Assembler::StoreLoad); | |
| 2594 } else { | |
| 2595 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 2596 // We use the current thread pointer to calculate a thread specific | |
| 2597 // offset to write to within the page. This minimizes bus traffic | |
| 2598 // due to cache line collision. | |
| 2599 __ serialize_memory(G2_thread, G1_scratch, G3_scratch); | |
| 2600 } | |
| 2601 } | |
| 2602 __ load_contents(sync_state, G3_scratch); | |
| 2603 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized); | |
| 2604 | |
| 2605 Label L; | |
| 727 | 2606 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset()); |
| 0 | 2607 __ br(Assembler::notEqual, false, Assembler::pn, L); |
| 727 | 2608 __ delayed()->ld(suspend_state, G3_scratch); |
| 3839 | 2609 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block); |
| 0 | 2610 __ bind(L); |
| 2611 | |
| 2612 // Block. Save any potential method result value before the operation and | |
| 2613 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this | |
| 2614 // lets us share the oopMap we used when we went native rather the create | |
| 2615 // a distinct one for this pc | |
| 2616 // | |
| 2617 save_native_result(masm, ret_type, stack_slots); | |
|
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2618 if (!is_critical_native) { |
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2619 __ call_VM_leaf(L7_thread_cache, |
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2620 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), |
|
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2621 G2_thread); |
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2622 } else { |
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2623 __ call_VM_leaf(L7_thread_cache, |
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2624 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), |
|
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2625 G2_thread); |
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2626 } |
| 0 | 2627 |
| 2628 // Restore any method result value | |
| 2629 restore_native_result(masm, ret_type, stack_slots); | |
|
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2630 |
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2631 if (is_critical_native) { |
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2632 // The call above performed the transition to thread_in_Java so |
|
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2633 // skip the transition logic below. |
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2634 __ ba(after_transition); |
|
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2635 __ delayed()->nop(); |
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2636 } |
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2637 |
| 0 | 2638 __ bind(no_block); |
| 2639 } | |
| 2640 | |
| 2641 // thread state is thread_in_native_trans. Any safepoint blocking has already | |
| 2642 // happened so we can now change state to _thread_in_Java. | |
| 2643 __ set(_thread_in_Java, G3_scratch); | |
| 727 | 2644 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
|
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2645 __ bind(after_transition); |
| 0 | 2646 |
| 2647 Label no_reguard; | |
| 727 | 2648 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch); |
| 3839 | 2649 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard); |
| 0 | 2650 |
| 2651 save_native_result(masm, ret_type, stack_slots); | |
| 2652 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); | |
| 2653 __ delayed()->nop(); | |
| 2654 | |
| 2655 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2656 restore_native_result(masm, ret_type, stack_slots); | |
| 2657 | |
| 2658 __ bind(no_reguard); | |
| 2659 | |
| 2660 // Handle possible exception (will unlock if necessary) | |
| 2661 | |
| 2662 // native result if any is live in freg or I0 (and I1 if long and 32bit vm) | |
| 2663 | |
| 2664 // Unlock | |
| 2665 if (method->is_synchronized()) { | |
| 2666 Label done; | |
| 2667 Register I2_ex_oop = I2; | |
| 2668 const Register L3_box = L3; | |
| 2669 // Get locked oop from the handle we passed to jni | |
| 2670 __ ld_ptr(L6_handle, 0, L4); | |
| 2671 __ add(SP, lock_offset+STACK_BIAS, L3_box); | |
| 2672 // Must save pending exception around the slow-path VM call. Since it's a | |
| 2673 // leaf call, the pending exception (if any) can be kept in a register. | |
| 2674 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop); | |
| 2675 // Now unlock | |
| 2676 // (Roop, Rmark, Rbox, Rscratch) | |
| 2677 __ compiler_unlock_object(L4, L1, L3_box, L2); | |
| 2678 __ br(Assembler::equal, false, Assembler::pt, done); | |
| 2679 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box); | |
| 2680 | |
| 2681 // save and restore any potential method result value around the unlocking | |
| 2682 // operation. Will save in I0 (or stack for FP returns). | |
| 2683 save_native_result(masm, ret_type, stack_slots); | |
| 2684 | |
| 2685 // Must clear pending-exception before re-entering the VM. Since this is | |
| 2686 // a leaf call, pending-exception-oop can be safely kept in a register. | |
| 2687 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
| 2688 | |
| 2689 // slow case of monitor enter. Inline a special case of call_VM that | |
| 2690 // disallows any pending_exception. | |
| 2691 __ mov(L3_box, O1); | |
| 2692 | |
| 2693 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type); | |
| 2694 __ delayed()->mov(L4, O0); // Need oop in O0 | |
| 2695 | |
| 2696 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2697 | |
| 2698 #ifdef ASSERT | |
| 2699 { Label L; | |
| 2700 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
| 3839 | 2701 __ br_null_short(O0, Assembler::pt, L); |
| 0 | 2702 __ stop("no pending exception allowed on exit from IR::monitorexit"); |
| 2703 __ bind(L); | |
| 2704 } | |
| 2705 #endif | |
| 2706 restore_native_result(masm, ret_type, stack_slots); | |
| 2707 // check_forward_pending_exception jump to forward_exception if any pending | |
| 2708 // exception is set. The forward_exception routine expects to see the | |
| 2709 // exception in pending_exception and not in a register. Kind of clumsy, | |
| 2710 // since all folks who branch to forward_exception must have tested | |
| 2711 // pending_exception first and hence have it in a register already. | |
| 2712 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
| 2713 __ bind(done); | |
| 2714 } | |
| 2715 | |
| 2716 // Tell dtrace about this method exit | |
| 2717 { | |
| 2718 SkipIfEqual skip_if( | |
| 2719 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
| 2720 save_native_result(masm, ret_type, stack_slots); | |
|
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2721 __ set_metadata_constant(method(), O1); |
| 0 | 2722 __ call_VM_leaf(L7_thread_cache, |
| 2723 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), | |
| 2724 G2_thread, O1); | |
| 2725 restore_native_result(masm, ret_type, stack_slots); | |
| 2726 } | |
| 2727 | |
| 2728 // Clear "last Java frame" SP and PC. | |
| 2729 __ verify_thread(); // G2_thread must be correct | |
| 2730 __ reset_last_Java_frame(); | |
| 2731 | |
| 2732 // Unpack oop result | |
| 2733 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { | |
| 2734 Label L; | |
| 2735 __ addcc(G0, I0, G0); | |
| 2736 __ brx(Assembler::notZero, true, Assembler::pt, L); | |
| 2737 __ delayed()->ld_ptr(I0, 0, I0); | |
| 2738 __ mov(G0, I0); | |
| 2739 __ bind(L); | |
| 2740 __ verify_oop(I0); | |
| 2741 } | |
| 2742 | |
|
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2743 if (!is_critical_native) { |
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2744 // reset handle block |
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2745 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5); |
|
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2746 __ st(G0, L5, JNIHandleBlock::top_offset_in_bytes()); |
|
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2747 |
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2748 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch); |
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2749 check_forward_pending_exception(masm, G3_scratch); |
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2750 } |
| 0 | 2751 |
| 2752 | |
| 2753 // Return | |
| 2754 | |
| 2755 #ifndef _LP64 | |
| 2756 if (ret_type == T_LONG) { | |
| 2757 | |
| 2758 // Must leave proper result in O0,O1 and G1 (c2/tiered only) | |
| 2759 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
| 2760 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
| 2761 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
| 2762 } | |
| 2763 #endif | |
| 2764 | |
| 2765 __ ret(); | |
| 2766 __ delayed()->restore(); | |
| 2767 | |
| 2768 __ flush(); | |
| 2769 | |
| 2770 nmethod *nm = nmethod::new_native_nmethod(method, | |
|
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2771 compile_id, |
| 0 | 2772 masm->code(), |
| 2773 vep_offset, | |
| 2774 frame_complete, | |
| 2775 stack_slots / VMRegImpl::slots_per_word, | |
| 2776 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), | |
| 2777 in_ByteSize(lock_offset), | |
| 2778 oop_maps); | |
|
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2779 |
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2780 if (is_critical_native) { |
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|
2781 nm->set_lazy_critical_native(true); |
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2782 } |
| 0 | 2783 return nm; |
| 2784 | |
| 2785 } | |
| 2786 | |
|
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2787 #ifdef HAVE_DTRACE_H |
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2788 // --------------------------------------------------------------------------- |
|
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2789 // Generate a dtrace nmethod for a given signature. The method takes arguments |
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2790 // in the Java compiled code convention, marshals them to the native |
|
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2791 // abi and then leaves nops at the position you would expect to call a native |
|
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2792 // function. When the probe is enabled the nops are replaced with a trap |
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2793 // instruction that dtrace inserts and the trace will cause a notification |
|
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2794 // to dtrace. |
|
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2795 // |
|
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2796 // The probes are only able to take primitive types and java/lang/String as |
|
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2797 // arguments. No other java types are allowed. Strings are converted to utf8 |
|
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2798 // strings so that from dtrace point of view java strings are converted to C |
|
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2799 // strings. There is an arbitrary fixed limit on the total space that a method |
|
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2800 // can use for converting the strings. (256 chars per string in the signature). |
|
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2801 // So any java string larger then this is truncated. |
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2802 |
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2803 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; |
|
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2804 static bool offsets_initialized = false; |
|
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2805 |
|
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2806 nmethod *SharedRuntime::generate_dtrace_nmethod( |
|
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2807 MacroAssembler *masm, methodHandle method) { |
|
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2808 |
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2809 |
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2810 // generate_dtrace_nmethod is guarded by a mutex so we are sure to |
|
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2811 // be single threaded in this method. |
|
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2812 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); |
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2813 |
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2814 // Fill in the signature array, for the calling-convention call. |
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2815 int total_args_passed = method->size_of_parameters(); |
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2816 |
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2817 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); |
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2818 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); |
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2819 |
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2820 // The signature we are going to use for the trap that dtrace will see |
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2821 // java/lang/String is converted. We drop "this" and any other object |
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2822 // is converted to NULL. (A one-slot java/lang/Long object reference |
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2823 // is converted to a two-slot long, which is why we double the allocation). |
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2824 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); |
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2825 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); |
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2826 |
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2827 int i=0; |
|
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2828 int total_strings = 0; |
|
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2829 int first_arg_to_pass = 0; |
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2830 int total_c_args = 0; |
|
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2831 |
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2832 // Skip the receiver as dtrace doesn't want to see it |
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2833 if( !method->is_static() ) { |
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2834 in_sig_bt[i++] = T_OBJECT; |
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2835 first_arg_to_pass = 1; |
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2836 } |
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2837 |
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2838 SignatureStream ss(method->signature()); |
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2839 for ( ; !ss.at_return_type(); ss.next()) { |
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2840 BasicType bt = ss.type(); |
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2841 in_sig_bt[i++] = bt; // Collect remaining bits of signature |
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2842 out_sig_bt[total_c_args++] = bt; |
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2843 if( bt == T_OBJECT) { |
|
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2844 Symbol* s = ss.as_symbol_or_null(); |
|
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2845 if (s == vmSymbols::java_lang_String()) { |
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2846 total_strings++; |
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2847 out_sig_bt[total_c_args-1] = T_ADDRESS; |
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2848 } else if (s == vmSymbols::java_lang_Boolean() || |
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2849 s == vmSymbols::java_lang_Byte()) { |
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2850 out_sig_bt[total_c_args-1] = T_BYTE; |
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2851 } else if (s == vmSymbols::java_lang_Character() || |
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2852 s == vmSymbols::java_lang_Short()) { |
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2853 out_sig_bt[total_c_args-1] = T_SHORT; |
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2854 } else if (s == vmSymbols::java_lang_Integer() || |
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2855 s == vmSymbols::java_lang_Float()) { |
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2856 out_sig_bt[total_c_args-1] = T_INT; |
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2857 } else if (s == vmSymbols::java_lang_Long() || |
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2858 s == vmSymbols::java_lang_Double()) { |
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2859 out_sig_bt[total_c_args-1] = T_LONG; |
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2860 out_sig_bt[total_c_args++] = T_VOID; |
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2861 } |
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2862 } else if ( bt == T_LONG || bt == T_DOUBLE ) { |
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2863 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots |
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2864 // We convert double to long |
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2865 out_sig_bt[total_c_args-1] = T_LONG; |
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2866 out_sig_bt[total_c_args++] = T_VOID; |
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2867 } else if ( bt == T_FLOAT) { |
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2868 // We convert float to int |
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2869 out_sig_bt[total_c_args-1] = T_INT; |
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2870 } |
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2871 } |
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2872 |
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2873 assert(i==total_args_passed, "validly parsed signature"); |
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2874 |
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2875 // Now get the compiled-Java layout as input arguments |
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2876 int comp_args_on_stack; |
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2877 comp_args_on_stack = SharedRuntime::java_calling_convention( |
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2878 in_sig_bt, in_regs, total_args_passed, false); |
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2879 |
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2880 // We have received a description of where all the java arg are located |
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2881 // on entry to the wrapper. We need to convert these args to where |
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2882 // the a native (non-jni) function would expect them. To figure out |
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2883 // where they go we convert the java signature to a C signature and remove |
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2884 // T_VOID for any long/double we might have received. |
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2885 |
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2886 |
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2887 // Now figure out where the args must be stored and how much stack space |
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2888 // they require (neglecting out_preserve_stack_slots but space for storing |
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2889 // the 1st six register arguments). It's weird see int_stk_helper. |
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2890 // |
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2891 int out_arg_slots; |
|
14416
6a936747b569
8024344: PPC64 (part 112): C argument in register AND stack slot.
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|
2892 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); |
|
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2893 |
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2894 // Calculate the total number of stack slots we will need. |
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2895 |
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2896 // First count the abi requirement plus all of the outgoing args |
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2897 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; |
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2898 |
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2899 // Plus a temp for possible converion of float/double/long register args |
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2900 |
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2901 int conversion_temp = stack_slots; |
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2902 stack_slots += 2; |
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2903 |
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2904 |
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2905 // Now space for the string(s) we must convert |
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2906 |
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2907 int string_locs = stack_slots; |
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2908 stack_slots += total_strings * |
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2909 (max_dtrace_string_size / VMRegImpl::stack_slot_size); |
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2910 |
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2911 // Ok The space we have allocated will look like: |
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2912 // |
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2913 // |
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2914 // FP-> | | |
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2915 // |---------------------| |
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2916 // | string[n] | |
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2917 // |---------------------| <- string_locs[n] |
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2918 // | string[n-1] | |
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2919 // |---------------------| <- string_locs[n-1] |
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2920 // | ... | |
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2921 // | ... | |
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2922 // |---------------------| <- string_locs[1] |
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2923 // | string[0] | |
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2924 // |---------------------| <- string_locs[0] |
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2925 // | temp | |
|
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2926 // |---------------------| <- conversion_temp |
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2927 // | outbound memory | |
|
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2928 // | based arguments | |
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2929 // | | |
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2930 // |---------------------| |
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2931 // | | |
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2932 // SP-> | out_preserved_slots | |
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2933 // |
|
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2934 // |
|
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2935 |
|
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2936 // Now compute actual number of stack words we need rounding to make |
|
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2937 // stack properly aligned. |
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2938 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); |
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2939 |
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2940 int stack_size = stack_slots * VMRegImpl::stack_slot_size; |
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2941 |
|
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2942 intptr_t start = (intptr_t)__ pc(); |
|
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2943 |
|
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2944 // First thing make an ic check to see if we should even be here |
|
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2945 |
|
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2946 { |
|
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|
2947 Label L; |
|
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2948 const Register temp_reg = G3_scratch; |
| 727 | 2949 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
|
116
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2950 __ verify_oop(O0); |
|
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2951 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg); |
| 3839 | 2952 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
|
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2953 |
| 727 | 2954 __ jump_to(ic_miss, temp_reg); |
|
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2955 __ delayed()->nop(); |
|
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2956 __ align(CodeEntryAlignment); |
|
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2957 __ bind(L); |
|
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|
2958 } |
|
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|
2959 |
|
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2960 int vep_offset = ((intptr_t)__ pc()) - start; |
|
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2961 |
|
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|
2962 |
|
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2963 // The instruction at the verified entry point must be 5 bytes or longer |
|
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2964 // because it can be patched on the fly by make_non_entrant. The stack bang |
|
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2965 // instruction fits that requirement. |
|
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2966 |
|
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2967 // Generate stack overflow check before creating frame |
|
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2968 __ generate_stack_overflow_check(stack_size); |
|
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2969 |
|
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|
2970 assert(((intptr_t)__ pc() - start - vep_offset) >= 5, |
|
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2971 "valid size for make_non_entrant"); |
|
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2972 |
|
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2973 // Generate a new frame for the wrapper. |
|
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2974 __ save(SP, -stack_size, SP); |
|
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2975 |
|
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2976 // Frame is now completed as far a size and linkage. |
|
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2977 |
|
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2978 int frame_complete = ((intptr_t)__ pc()) - start; |
|
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2979 |
|
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2980 #ifdef ASSERT |
|
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2981 bool reg_destroyed[RegisterImpl::number_of_registers]; |
|
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2982 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; |
|
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2983 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { |
|
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2984 reg_destroyed[r] = false; |
|
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2985 } |
|
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2986 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { |
|
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2987 freg_destroyed[f] = false; |
|
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|
2988 } |
|
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|
2989 |
|
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|
2990 #endif /* ASSERT */ |
|
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2991 |
|
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|
2992 VMRegPair zero; |
|
176
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2993 const Register g0 = G0; // without this we get a compiler warning (why??) |
|
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2994 zero.set2(g0->as_VMReg()); |
|
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2995 |
|
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|
2996 int c_arg, j_arg; |
|
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2997 |
|
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|
2998 Register conversion_off = noreg; |
|
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2999 |
|
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3000 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
|
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3001 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
|
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3002 |
|
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|
3003 VMRegPair src = in_regs[j_arg]; |
|
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3004 VMRegPair dst = out_regs[c_arg]; |
|
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|
3005 |
|
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|
3006 #ifdef ASSERT |
|
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|
3007 if (src.first()->is_Register()) { |
|
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3008 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!"); |
|
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|
3009 } else if (src.first()->is_FloatRegister()) { |
|
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|
3010 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding( |
|
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|
3011 FloatRegisterImpl::S)], "ack!"); |
|
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|
3012 } |
|
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|
3013 if (dst.first()->is_Register()) { |
|
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|
3014 reg_destroyed[dst.first()->as_Register()->encoding()] = true; |
|
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|
3015 } else if (dst.first()->is_FloatRegister()) { |
|
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|
3016 freg_destroyed[dst.first()->as_FloatRegister()->encoding( |
|
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|
3017 FloatRegisterImpl::S)] = true; |
|
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|
3018 } |
|
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|
3019 #endif /* ASSERT */ |
|
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|
3020 |
|
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|
3021 switch (in_sig_bt[j_arg]) { |
|
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3022 case T_ARRAY: |
|
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|
3023 case T_OBJECT: |
|
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|
3024 { |
|
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|
3025 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT || |
|
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|
3026 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { |
|
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|
3027 // need to unbox a one-slot value |
|
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|
3028 Register in_reg = L0; |
|
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|
3029 Register tmp = L2; |
|
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3030 if ( src.first()->is_reg() ) { |
|
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|
3031 in_reg = src.first()->as_Register(); |
|
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|
3032 } else { |
|
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|
3033 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS), |
|
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|
3034 "must be"); |
|
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|
3035 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg); |
|
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|
3036 } |
|
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|
3037 // If the final destination is an acceptable register |
|
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|
3038 if ( dst.first()->is_reg() ) { |
|
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|
3039 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) { |
|
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|
3040 tmp = dst.first()->as_Register(); |
|
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|
3041 } |
|
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|
3042 } |
|
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|
3043 |
|
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|
3044 Label skipUnbox; |
|
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3045 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) { |
|
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3046 __ mov(G0, tmp->successor()); |
|
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3047 } |
|
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|
3048 __ br_null(in_reg, true, Assembler::pn, skipUnbox); |
|
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|
3049 __ delayed()->mov(G0, tmp); |
|
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|
3050 |
|
165
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|
3051 BasicType bt = out_sig_bt[c_arg]; |
|
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3052 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); |
|
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3053 switch (bt) { |
|
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3054 case T_BYTE: |
|
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|
3055 __ ldub(in_reg, box_offset, tmp); break; |
|
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3056 case T_SHORT: |
|
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3057 __ lduh(in_reg, box_offset, tmp); break; |
|
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3058 case T_INT: |
|
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|
3059 __ ld(in_reg, box_offset, tmp); break; |
|
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3060 case T_LONG: |
|
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|
3061 __ ld_long(in_reg, box_offset, tmp); break; |
|
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|
3062 default: ShouldNotReachHere(); |
|
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diff
changeset
|
3063 } |
|
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3064 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3065 __ bind(skipUnbox); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3066 // If tmp wasn't final destination copy to final destination |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3067 if (tmp == L2) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3068 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3069 if (out_sig_bt[c_arg] == T_LONG) { |
|
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kamg
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113
diff
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|
3070 long_move(masm, tmp_as_VM, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3071 } else { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3072 move32_64(masm, tmp_as_VM, out_regs[c_arg]); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3073 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3074 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3075 if (out_sig_bt[c_arg] == T_LONG) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3076 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3077 ++c_arg; // move over the T_VOID to keep the loop indices in sync |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3078 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3079 } else if (out_sig_bt[c_arg] == T_ADDRESS) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3080 Register s = |
|
018d5b58dd4f
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kamg
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113
diff
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|
3081 src.first()->is_reg() ? src.first()->as_Register() : L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3082 Register d = |
|
018d5b58dd4f
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kamg
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113
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|
3083 dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3084 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3085 // We store the oop now so that the conversion pass can reach |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3086 // while in the inner frame. This will be the only store if |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3087 // the oop is NULL. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3088 if (s != L2) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3089 // src is register |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3090 if (d != L2) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3091 // dst is register |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3092 __ mov(s, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3093 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3094 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3095 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3096 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3097 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3098 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3099 // src not a register |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3100 assert(Assembler::is_simm13(reg2offset(src.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3101 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3102 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3103 if (d == L2) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3104 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3105 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3106 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3107 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3108 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3109 } else if (out_sig_bt[c_arg] != T_VOID) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3110 // Convert the arg to NULL |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3111 if (dst.first()->is_reg()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3112 __ mov(G0, dst.first()->as_Register()); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3113 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3114 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3115 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3116 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3117 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3118 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3119 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3120 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3121 case T_VOID: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3122 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3123 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3124 case T_FLOAT: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3125 if (src.first()->is_stack()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3126 // Stack to stack/reg is simple |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3127 move32_64(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3128 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3129 if (dst.first()->is_reg()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3130 // freg -> reg |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3131 int off = |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3132 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3133 Register d = dst.first()->as_Register(); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3134 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3135 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3136 SP, off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3137 __ ld(SP, off, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3138 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3139 if (conversion_off == noreg) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3140 __ set(off, L6); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3141 conversion_off = L6; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3142 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3143 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3144 SP, conversion_off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3145 __ ld(SP, conversion_off , d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3146 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3147 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3148 // freg -> mem |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3149 int off = STACK_BIAS + reg2offset(dst.first()); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3150 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3151 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3152 SP, off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3153 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3154 if (conversion_off == noreg) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3155 __ set(off, L6); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3156 conversion_off = L6; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3157 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3158 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3159 SP, conversion_off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3160 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3161 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3162 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3163 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3164 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3165 case T_DOUBLE: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3166 assert( j_arg + 1 < total_args_passed && |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3167 in_sig_bt[j_arg + 1] == T_VOID && |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3168 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3169 if (src.first()->is_stack()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3170 // Stack to stack/reg is simple |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3171 long_move(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3172 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3173 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3174 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3175 // Destination could be an odd reg on 32bit in which case |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3176 // we can't load direct to the destination. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3177 |
|
018d5b58dd4f
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113
diff
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|
3178 if (!d->is_even() && wordSize == 4) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3179 d = L2; |
|
018d5b58dd4f
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kamg
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113
diff
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|
3180 } |
|
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kamg
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113
diff
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|
3181 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
|
018d5b58dd4f
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kamg
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|
3182 if (Assembler::is_simm13(off)) { |
|
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113
diff
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|
3183 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
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kamg
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|
3184 SP, off); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3185 __ ld_long(SP, off, d); |
|
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113
diff
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|
3186 } else { |
|
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kamg
parents:
113
diff
changeset
|
3187 if (conversion_off == noreg) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3188 __ set(off, L6); |
|
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kamg
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113
diff
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|
3189 conversion_off = L6; |
|
018d5b58dd4f
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kamg
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113
diff
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|
3190 } |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3191 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
|
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kamg
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diff
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|
3192 SP, conversion_off); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3193 __ ld_long(SP, conversion_off, d); |
|
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kamg
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113
diff
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|
3194 } |
|
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kamg
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113
diff
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|
3195 if (d == L2) { |
|
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|
3196 long_move(masm, reg64_to_VMRegPair(L2), dst); |
|
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kamg
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|
3197 } |
|
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kamg
parents:
113
diff
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|
3198 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3199 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3200 |
|
018d5b58dd4f
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kamg
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113
diff
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|
3201 case T_LONG : |
|
018d5b58dd4f
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|
3202 // 32bit can't do a split move of something like g1 -> O0, O1 |
|
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|
3203 // so use a memory temp |
|
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|
3204 if (src.is_single_phys_reg() && wordSize == 4) { |
|
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kamg
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|
3205 Register tmp = L2; |
|
018d5b58dd4f
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|
3206 if (dst.first()->is_reg() && |
|
018d5b58dd4f
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|
3207 (wordSize == 8 || dst.first()->as_Register()->is_even())) { |
|
018d5b58dd4f
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|
3208 tmp = dst.first()->as_Register(); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3209 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3210 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3211 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
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|
3212 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3213 __ stx(src.first()->as_Register(), SP, off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
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|
3214 __ ld_long(SP, off, tmp); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3215 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3216 if (conversion_off == noreg) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3217 __ set(off, L6); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3218 conversion_off = L6; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3219 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3220 __ stx(src.first()->as_Register(), SP, conversion_off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3221 __ ld_long(SP, conversion_off, tmp); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3222 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3223 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3224 if (tmp == L2) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3225 long_move(masm, reg64_to_VMRegPair(L2), dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3226 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3227 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3228 long_move(masm, src, dst); |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3229 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3230 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3231 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3232 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3233 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3234 default: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3235 move32_64(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3236 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3237 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3238 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3239 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3240 // If we have any strings we must store any register based arg to the stack |
|
018d5b58dd4f
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kamg
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113
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|
3241 // This includes any still live xmm registers too. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3242 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3243 if (total_strings > 0 ) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3244 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3245 // protect all the arg registers |
|
018d5b58dd4f
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kamg
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113
diff
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|
3246 __ save_frame(0); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3247 __ mov(G2_thread, L7_thread_cache); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3248 const Register L2_string_off = L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3249 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3250 // Get first string offset |
|
018d5b58dd4f
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kamg
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113
diff
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|
3251 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3252 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3253 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) { |
|
018d5b58dd4f
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kamg
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113
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|
3254 if (out_sig_bt[c_arg] == T_ADDRESS) { |
|
018d5b58dd4f
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kamg
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113
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|
3255 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3256 VMRegPair dst = out_regs[c_arg]; |
|
018d5b58dd4f
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kamg
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113
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|
3257 const Register d = dst.first()->is_reg() ? |
|
018d5b58dd4f
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kamg
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113
diff
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|
3258 dst.first()->as_Register()->after_save() : noreg; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3259 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3260 // It's a string the oop and it was already copied to the out arg |
|
018d5b58dd4f
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kamg
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113
diff
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|
3261 // position |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3262 if (d != noreg) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3263 __ mov(d, O0); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3264 } else { |
|
018d5b58dd4f
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kamg
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113
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|
3265 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
|
018d5b58dd4f
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113
diff
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|
3266 "must be"); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3267 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3268 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3269 Label skip; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3270 |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3271 __ br_null(O0, false, Assembler::pn, skip); |
|
018d5b58dd4f
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kamg
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113
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|
3272 __ delayed()->add(FP, L2_string_off, O1); |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3273 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3274 if (d != noreg) { |
|
018d5b58dd4f
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113
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|
3275 __ mov(O1, d); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3276 } else { |
|
018d5b58dd4f
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kamg
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|
3277 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
|
018d5b58dd4f
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113
diff
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|
3278 "must be"); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3279 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3280 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3281 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3282 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf), |
|
018d5b58dd4f
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kamg
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|
3283 relocInfo::runtime_call_type); |
|
018d5b58dd4f
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113
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|
3284 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off); |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3285 |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3286 __ bind(skip); |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3287 |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3288 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3289 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3290 } |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3291 __ mov(L7_thread_cache, G2_thread); |
|
018d5b58dd4f
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113
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|
3292 __ restore(); |
|
018d5b58dd4f
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|
3293 |
|
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3294 } |
|
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3295 |
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3296 |
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3297 // Ok now we are done. Need to place the nop that dtrace wants in order to |
|
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3298 // patch in the trap |
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3299 |
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3300 int patch_offset = ((intptr_t)__ pc()) - start; |
|
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3301 |
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3302 __ nop(); |
|
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3303 |
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3304 |
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3305 // Return |
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3306 |
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3307 __ ret(); |
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3308 __ delayed()->restore(); |
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3309 |
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3310 __ flush(); |
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3311 |
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3312 nmethod *nm = nmethod::new_dtrace_nmethod( |
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3313 method, masm->code(), vep_offset, patch_offset, frame_complete, |
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3314 stack_slots / VMRegImpl::slots_per_word); |
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3315 return nm; |
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3316 |
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3317 } |
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3318 |
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3319 #endif // HAVE_DTRACE_H |
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3320 |
| 0 | 3321 // this function returns the adjust size (in number of words) to a c2i adapter |
| 3322 // activation for use during deoptimization | |
| 3323 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { | |
| 3324 assert(callee_locals >= callee_parameters, | |
| 3325 "test and remove; got more parms than locals"); | |
| 3326 if (callee_locals < callee_parameters) | |
| 3327 return 0; // No adjustment for negative locals | |
| 1506 | 3328 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; |
| 0 | 3329 return round_to(diff, WordsPerLong); |
| 3330 } | |
| 3331 | |
| 3332 // "Top of Stack" slots that may be unused by the calling convention but must | |
| 3333 // otherwise be preserved. | |
| 3334 // On Intel these are not necessary and the value can be zero. | |
| 3335 // On Sparc this describes the words reserved for storing a register window | |
| 3336 // when an interrupt occurs. | |
| 3337 uint SharedRuntime::out_preserve_stack_slots() { | |
| 3338 return frame::register_save_words * VMRegImpl::slots_per_word; | |
| 3339 } | |
| 3340 | |
| 3341 static void gen_new_frame(MacroAssembler* masm, bool deopt) { | |
| 3342 // | |
| 3343 // Common out the new frame generation for deopt and uncommon trap | |
| 3344 // | |
| 3345 Register G3pcs = G3_scratch; // Array of new pcs (input) | |
| 3346 Register Oreturn0 = O0; | |
| 3347 Register Oreturn1 = O1; | |
| 3348 Register O2UnrollBlock = O2; | |
| 3349 Register O3array = O3; // Array of frame sizes (input) | |
| 3350 Register O4array_size = O4; // number of frames (input) | |
| 3351 Register O7frame_size = O7; // number of frames (input) | |
| 3352 | |
| 3353 __ ld_ptr(O3array, 0, O7frame_size); | |
| 3354 __ sub(G0, O7frame_size, O7frame_size); | |
| 3355 __ save(SP, O7frame_size, SP); | |
| 3356 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc | |
| 3357 | |
| 3358 #ifdef ASSERT | |
| 3359 // make sure that the frames are aligned properly | |
| 3360 #ifndef _LP64 | |
| 3361 __ btst(wordSize*2-1, SP); | |
| 5923 | 3362 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc); |
| 0 | 3363 #endif |
| 3364 #endif | |
| 3365 | |
| 3366 // Deopt needs to pass some extra live values from frame to frame | |
| 3367 | |
| 3368 if (deopt) { | |
| 3369 __ mov(Oreturn0->after_save(), Oreturn0); | |
| 3370 __ mov(Oreturn1->after_save(), Oreturn1); | |
| 3371 } | |
| 3372 | |
| 3373 __ mov(O4array_size->after_save(), O4array_size); | |
| 3374 __ sub(O4array_size, 1, O4array_size); | |
| 3375 __ mov(O3array->after_save(), O3array); | |
| 3376 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock); | |
| 3377 __ add(G3pcs, wordSize, G3pcs); // point to next pc value | |
| 3378 | |
| 3379 #ifdef ASSERT | |
| 3380 // trash registers to show a clear pattern in backtraces | |
| 3381 __ set(0xDEAD0000, I0); | |
| 3382 __ add(I0, 2, I1); | |
| 3383 __ add(I0, 4, I2); | |
| 3384 __ add(I0, 6, I3); | |
| 3385 __ add(I0, 8, I4); | |
| 3386 // Don't touch I5 could have valuable savedSP | |
| 3387 __ set(0xDEADBEEF, L0); | |
| 3388 __ mov(L0, L1); | |
| 3389 __ mov(L0, L2); | |
| 3390 __ mov(L0, L3); | |
| 3391 __ mov(L0, L4); | |
| 3392 __ mov(L0, L5); | |
| 3393 | |
| 3394 // trash the return value as there is nothing to return yet | |
| 3395 __ set(0xDEAD0001, O7); | |
| 3396 #endif | |
| 3397 | |
| 3398 __ mov(SP, O5_savedSP); | |
| 3399 } | |
| 3400 | |
| 3401 | |
| 3402 static void make_new_frames(MacroAssembler* masm, bool deopt) { | |
| 3403 // | |
| 3404 // loop through the UnrollBlock info and create new frames | |
| 3405 // | |
| 3406 Register G3pcs = G3_scratch; | |
| 3407 Register Oreturn0 = O0; | |
| 3408 Register Oreturn1 = O1; | |
| 3409 Register O2UnrollBlock = O2; | |
| 3410 Register O3array = O3; | |
| 3411 Register O4array_size = O4; | |
| 3412 Label loop; | |
| 3413 | |
|
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3414 #ifdef ASSERT |
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3415 // Compilers generate code that bang the stack by as much as the |
|
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3416 // interpreter would need. So this stack banging should never |
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3417 // trigger a fault. Verify that it does not on non product builds. |
| 0 | 3418 if (UseStackBanging) { |
| 3419 // Get total frame size for interpreted frames | |
| 727 | 3420 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4); |
| 0 | 3421 __ bang_stack_size(O4, O3, G3_scratch); |
| 3422 } | |
|
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3423 #endif |
| 0 | 3424 |
| 727 | 3425 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size); |
| 3426 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs); | |
| 3427 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array); | |
| 0 | 3428 |
| 3429 // Adjust old interpreter frame to make space for new frame's extra java locals | |
| 3430 // | |
| 3431 // We capture the original sp for the transition frame only because it is needed in | |
| 3432 // order to properly calculate interpreter_sp_adjustment. Even though in real life | |
| 3433 // every interpreter frame captures a savedSP it is only needed at the transition | |
| 3434 // (fortunately). If we had to have it correct everywhere then we would need to | |
| 3435 // be told the sp_adjustment for each frame we create. If the frame size array | |
| 3436 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size] | |
| 3437 // for each frame we create and keep up the illusion every where. | |
| 3438 // | |
| 3439 | |
| 727 | 3440 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7); |
| 0 | 3441 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment |
| 3442 __ sub(SP, O7, SP); | |
| 3443 | |
| 3444 #ifdef ASSERT | |
| 3445 // make sure that there is at least one entry in the array | |
| 3446 __ tst(O4array_size); | |
| 5923 | 3447 __ breakpoint_trap(Assembler::zero, Assembler::icc); |
| 0 | 3448 #endif |
| 3449 | |
| 3450 // Now push the new interpreter frames | |
| 3451 __ bind(loop); | |
| 3452 | |
| 3453 // allocate a new frame, filling the registers | |
| 3454 | |
| 3455 gen_new_frame(masm, deopt); // allocate an interpreter frame | |
| 3456 | |
| 3839 | 3457 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop); |
| 0 | 3458 __ delayed()->add(O3array, wordSize, O3array); |
| 3459 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc | |
| 3460 | |
| 3461 } | |
| 3462 | |
| 3463 //------------------------------generate_deopt_blob---------------------------- | |
| 3464 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
| 3465 // instead. | |
| 3466 void SharedRuntime::generate_deopt_blob() { | |
| 3467 // allocate space for the code | |
| 3468 ResourceMark rm; | |
| 3469 // setup code generation tools | |
| 3470 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code | |
|
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3471 #ifdef ASSERT |
|
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3472 if (UseStackBanging) { |
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3473 pad += StackShadowPages*16 + 32; |
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3474 } |
|
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3475 #endif |
|
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|
3476 #ifdef GRAAL |
|
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|
3477 pad += 1000; // Increase the buffer size when compiling for GRAAL |
|
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|
3478 #endif |
| 0 | 3479 #ifdef _LP64 |
|
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|
3480 CodeBuffer buffer("deopt_blob", 2100+pad+1000, 512); |
| 0 | 3481 #else |
| 3482 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread) | |
| 3483 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread) | |
| 3484 CodeBuffer buffer("deopt_blob", 1600+pad, 512); | |
| 3485 #endif /* _LP64 */ | |
| 3486 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3487 FloatRegister Freturn0 = F0; | |
| 3488 Register Greturn1 = G1; | |
| 3489 Register Oreturn0 = O0; | |
| 3490 Register Oreturn1 = O1; | |
| 3491 Register O2UnrollBlock = O2; | |
| 1037 | 3492 Register L0deopt_mode = L0; |
| 3493 Register G4deopt_mode = G4_scratch; | |
| 0 | 3494 int frame_size_words; |
| 727 | 3495 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS); |
| 0 | 3496 #if !defined(_LP64) && defined(COMPILER2) |
| 727 | 3497 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS); |
| 0 | 3498 #endif |
| 3499 Label cont; | |
| 3500 | |
| 3501 OopMapSet *oop_maps = new OopMapSet(); | |
| 3502 | |
| 3503 // | |
| 3504 // This is the entry point for code which is returning to a de-optimized | |
| 3505 // frame. | |
| 3506 // The steps taken by this frame are as follows: | |
| 3507 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1) | |
| 3508 // and all potentially live registers (at a pollpoint many registers can be live). | |
| 3509 // | |
| 3510 // - call the C routine: Deoptimization::fetch_unroll_info (this function | |
| 3511 // returns information about the number and size of interpreter frames | |
| 3512 // which are equivalent to the frame which is being deoptimized) | |
| 3513 // - deallocate the unpack frame, restoring only results values. Other | |
| 3514 // volatile registers will now be captured in the vframeArray as needed. | |
| 3515 // - deallocate the deoptimization frame | |
| 3516 // - in a loop using the information returned in the previous step | |
| 3517 // push new interpreter frames (take care to propagate the return | |
| 3518 // values through each new frame pushed) | |
| 3519 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0) | |
| 3520 // - call the C routine: Deoptimization::unpack_frames (this function | |
| 3521 // lays out values on the interpreter frame which was just created) | |
| 3522 // - deallocate the dummy unpack_frame | |
| 3523 // - ensure that all the return values are correctly set and then do | |
| 3524 // a return to the interpreter entry point | |
| 3525 // | |
| 3526 // Refer to the following methods for more information: | |
| 3527 // - Deoptimization::fetch_unroll_info | |
| 3528 // - Deoptimization::unpack_frames | |
| 3529 | |
| 3530 OopMap* map = NULL; | |
| 3531 | |
| 3532 int start = __ offset(); | |
| 3533 | |
| 3534 // restore G2, the trampoline destroyed it | |
| 3535 __ get_thread(); | |
| 3536 | |
| 3537 // On entry we have been called by the deoptimized nmethod with a call that | |
| 3538 // replaced the original call (or safepoint polling location) so the deoptimizing | |
| 3539 // pc is now in O7. Return values are still in the expected places | |
| 3540 | |
| 3541 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3839 | 3542 __ ba(cont); |
| 1037 | 3543 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode); |
| 0 | 3544 |
|
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3545 |
|
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|
3546 #ifdef GRAAL |
|
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3547 masm->block_comment("BEGIN GRAAL"); |
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|
3548 int implicit_exception_uncommon_trap_offset = __ offset() - start; |
|
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|
3549 //__ pushptr(Address(G2_thread, in_bytes(JavaThread::graal_implicit_exception_pc_offset()))); |
|
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|
3550 __ ld_ptr(G2_thread, in_bytes(JavaThread::graal_implicit_exception_pc_offset()), O7); |
|
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|
3551 //__ add(G0, 0x321, O7); |
|
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|
3552 __ add(O7, -8, O7); |
|
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|
3553 //__ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); |
|
19462
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3554 |
|
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|
3555 int uncommon_trap_offset = __ offset() - start; |
|
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3556 |
|
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|
3557 // Save everything in sight. |
|
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|
3558 masm->block_comment("save_live_regs"); |
|
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|
3559 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); |
|
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|
3560 masm->block_comment("/save_live_regs"); |
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|
3561 //__ ld_ptr(G2_thread, in_bytes(JavaThread::graal_implicit_exception_pc_offset()), O7); |
|
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|
3562 // fetch_unroll_info needs to call last_java_frame() |
|
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parents:
16307
diff
changeset
|
3563 masm->block_comment("set_last_java_frame"); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
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diff
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|
3564 __ set_last_Java_frame(SP, NULL); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
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diff
changeset
|
3565 masm->block_comment("/set_last_java_frame"); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
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diff
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|
3566 |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
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diff
changeset
|
3567 //__ movl(c_rarg1, Address(r15_thread, in_bytes(ThreadShadow::pending_deoptimization_offset()))); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
16307
diff
changeset
|
3568 __ ld(G2_thread, in_bytes(ThreadShadow::pending_deoptimization_offset()), O1); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
16307
diff
changeset
|
3569 //__ movl(Address(r15_thread, in_bytes(ThreadShadow::pending_deoptimization_offset())), -1); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
16307
diff
changeset
|
3570 __ sub(G0, 1, L1); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3571 __ st_ptr(L1, G2_thread, in_bytes(ThreadShadow::pending_deoptimization_offset())); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3572 |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
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diff
changeset
|
3573 __ mov((int32_t)Deoptimization::Unpack_reexecute, L0deopt_mode); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3574 __ mov(G2_thread, O0); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3575 __ call(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3576 __ delayed()->nop(); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3577 oop_maps->add_gc_map( __ offset()-start, map->deep_copy()); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3578 __ get_thread(); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
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|
3579 __ add(O7, 8, O7); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
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|
3580 __ reset_last_Java_frame(); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
16307
diff
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|
3581 |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3582 Label after_fetch_unroll_info_call; |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3583 __ ba(after_fetch_unroll_info_call); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
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|
3584 __ delayed()->nop(); // Delay slot |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
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|
3585 masm->block_comment("END GRAAL"); |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16307
diff
changeset
|
3586 #endif // GRAAL |
|
51f392557124
[SPARC] Improving implicit exception handling on sparc
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parents:
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diff
changeset
|
3587 |
| 0 | 3588 int exception_offset = __ offset() - start; |
| 3589 | |
| 3590 // restore G2, the trampoline destroyed it | |
| 3591 __ get_thread(); | |
| 3592 | |
| 3593 // On entry we have been jumped to by the exception handler (or exception_blob | |
| 3594 // for server). O0 contains the exception oop and O7 contains the original | |
| 3595 // exception pc. So if we push a frame here it will look to the | |
| 3596 // stack walking code (fetch_unroll_info) just like a normal call so | |
| 3597 // state will be extracted normally. | |
| 3598 | |
| 3599 // save exception oop in JavaThread and fall through into the | |
| 3600 // exception_in_tls case since they are handled in same way except | |
| 3601 // for where the pending exception is kept. | |
| 727 | 3602 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset()); |
| 0 | 3603 |
| 3604 // | |
| 3605 // Vanilla deoptimization with an exception pending in exception_oop | |
| 3606 // | |
| 3607 int exception_in_tls_offset = __ offset() - start; | |
| 3608 | |
| 3609 // No need to update oop_map as each call to save_live_registers will produce identical oopmap | |
|
16641
422eda5267b3
[SPARC] Temporary fix to get the stack for deoptimization right when exception is thrown
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
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diff
changeset
|
3610 // Opens a new stack frame |
| 0 | 3611 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); |
| 3612 | |
| 3613 // Restore G2_thread | |
| 3614 __ get_thread(); | |
| 3615 | |
|
16941
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3616 #ifdef GRAAL |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
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parents:
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diff
changeset
|
3617 // load throwing pc from JavaThread and patch it as the return address |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3618 // of the current frame. Then clear the field in JavaThread |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3619 __ block_comment("load throwing pc and patch return"); |
|
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Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3620 Address exception_pc(G2_thread, JavaThread::exception_pc_offset()); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3621 Label has_no_pc; |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3622 // TODO: Remove this weird check if we should patch the return pc |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3623 // This is because when graal decides to deoptimize and the ExceptionHandlerStub.java |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3624 // jumps back to this code and the I7 register contains the pc pointing to the begin |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3625 // of this code. If this is the case (PC within a certain range) then we need to patch |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
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parents:
16657
diff
changeset
|
3626 // the return pc. |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3627 // THIS NEEDS REWORK! (sa) |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3628 __ rdpc(L0); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3629 __ sub(L0, I7, L0); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3630 __ cmp(L0, 0xFFF); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3631 __ br(Assembler::greater, false, Assembler::pt, has_no_pc); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3632 __ delayed() -> nop(); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
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diff
changeset
|
3633 __ cmp(L0, -0xFFF); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3634 __ br(Assembler::less, false, Assembler::pt, has_no_pc); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3635 __ delayed() -> nop(); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3636 __ ld_ptr(exception_pc, I7); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3637 __ sub(I7, 8, I7); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3638 __ st_ptr(G0, exception_pc); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3639 __ bind(has_no_pc); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3640 __ block_comment("/load throwing pc and patch return"); |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3641 #endif // GAAL |
|
4e3b63e7a9f6
Fixing relock on interpreter when entering synchronized methods.
Stefan Anzinger <stefan.anzinger@oracle.com>
parents:
16657
diff
changeset
|
3642 |
| 0 | 3643 #ifdef ASSERT |
| 3644 { | |
| 3645 // verify that there is really an exception oop in exception_oop | |
| 3646 Label has_exception; | |
| 727 | 3647 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); |
| 3839 | 3648 __ br_notnull_short(Oexception, Assembler::pt, has_exception); |
| 0 | 3649 __ stop("no exception in thread"); |
| 3650 __ bind(has_exception); | |
| 3651 | |
| 3652 // verify that there is no pending exception | |
| 3653 Label no_pending_exception; | |
| 727 | 3654 Address exception_addr(G2_thread, Thread::pending_exception_offset()); |
| 0 | 3655 __ ld_ptr(exception_addr, Oexception); |
| 3839 | 3656 __ br_null_short(Oexception, Assembler::pt, no_pending_exception); |
| 0 | 3657 __ stop("must not have pending exception here"); |
| 3658 __ bind(no_pending_exception); | |
| 3659 } | |
| 3660 #endif | |
| 3661 | |
| 3839 | 3662 __ ba(cont); |
| 1037 | 3663 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);; |
| 0 | 3664 |
| 3665 // | |
| 3666 // Reexecute entry, similar to c2 uncommon trap | |
| 3667 // | |
| 3668 int reexecute_offset = __ offset() - start; | |
|
16641
422eda5267b3
[SPARC] Temporary fix to get the stack for deoptimization right when exception is thrown
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16326
diff
changeset
|
3669 #if defined(COMPILERGRAAL) && !defined(COMPILER1) |
|
422eda5267b3
[SPARC] Temporary fix to get the stack for deoptimization right when exception is thrown
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16326
diff
changeset
|
3670 // Graal does not use this kind of deoptimization |
|
422eda5267b3
[SPARC] Temporary fix to get the stack for deoptimization right when exception is thrown
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16326
diff
changeset
|
3671 __ should_not_reach_here(); |
|
422eda5267b3
[SPARC] Temporary fix to get the stack for deoptimization right when exception is thrown
Stefan Anzinger <stefan.anzinger@gmail.com>
parents:
16326
diff
changeset
|
3672 #endif |
| 0 | 3673 // No need to update oop_map as each call to save_live_registers will produce identical oopmap |
| 3674 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3675 | |
| 1037 | 3676 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode); |
| 0 | 3677 |
| 3678 __ bind(cont); | |
| 3679 | |
| 3680 __ set_last_Java_frame(SP, noreg); | |
| 3681 | |
| 3682 // do the call by hand so we can get the oopmap | |
| 3683 | |
| 3684 __ mov(G2_thread, L7_thread_cache); | |
| 3685 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type); | |
| 3686 __ delayed()->mov(G2_thread, O0); | |
| 3687 | |
| 3688 // Set an oopmap for the call site this describes all our saved volatile registers | |
| 3689 | |
| 3690 oop_maps->add_gc_map( __ offset()-start, map); | |
| 3691 | |
| 3692 __ mov(L7_thread_cache, G2_thread); | |
| 3693 | |
| 3694 __ reset_last_Java_frame(); | |
| 3695 | |
|
16326
51f392557124
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diff
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|
3696 #ifdef GRAAL |
|
51f392557124
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parents:
16307
diff
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|
3697 __ bind(after_fetch_unroll_info_call); |
|
51f392557124
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parents:
16307
diff
changeset
|
3698 #endif |
| 0 | 3699 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers |
| 3700 // so this move will survive | |
| 3701 | |
| 1037 | 3702 __ mov(L0deopt_mode, G4deopt_mode); |
| 0 | 3703 |
| 3704 __ mov(O0, O2UnrollBlock->after_save()); | |
| 3705 | |
| 3706 RegisterSaver::restore_result_registers(masm); | |
| 3707 | |
| 3708 Label noException; | |
| 3839 | 3709 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException); |
| 0 | 3710 |
| 3711 // Move the pending exception from exception_oop to Oexception so | |
| 3712 // the pending exception will be picked up the interpreter. | |
| 3713 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception); | |
| 3714 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); | |
|
12884
e504cd481ec0
8026376: assert(false) failed: DEBUG MESSAGE: exception pc already set
twisti
parents:
10997
diff
changeset
|
3715 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
| 0 | 3716 __ bind(noException); |
| 3717 | |
| 3718 // deallocate the deoptimization frame taking care to preserve the return values | |
| 3719 __ mov(Oreturn0, Oreturn0->after_save()); | |
| 3720 __ mov(Oreturn1, Oreturn1->after_save()); | |
| 3721 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
| 3722 __ restore(); | |
| 3723 | |
| 3724 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
| 3725 | |
| 3726 make_new_frames(masm, true); | |
| 3727 | |
| 3728 // push a dummy "unpack_frame" taking care of float return values and | |
| 3729 // call Deoptimization::unpack_frames to have the unpacker layout | |
| 3730 // information in the interpreter frames just created and then return | |
| 3731 // to the interpreter entry point | |
| 3732 __ save(SP, -frame_size_words*wordSize, SP); | |
| 3733 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr); | |
| 3734 #if !defined(_LP64) | |
| 3735 #if defined(COMPILER2) | |
| 1783 | 3736 // 32-bit 1-register longs return longs in G1 |
| 3737 __ stx(Greturn1, saved_Greturn1_addr); | |
| 0 | 3738 #endif |
| 3739 __ set_last_Java_frame(SP, noreg); | |
| 1037 | 3740 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode); |
| 0 | 3741 #else |
| 3742 // LP64 uses g4 in set_last_Java_frame | |
| 1037 | 3743 __ mov(G4deopt_mode, O1); |
| 0 | 3744 __ set_last_Java_frame(SP, G0); |
| 3745 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1); | |
| 3746 #endif | |
| 3747 __ reset_last_Java_frame(); | |
| 3748 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0); | |
| 3749 | |
| 3750 #if !defined(_LP64) && defined(COMPILER2) | |
| 3751 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into | |
| 1783 | 3752 // I0/I1 if the return value is long. |
| 3753 Label not_long; | |
| 3839 | 3754 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long); |
| 1783 | 3755 __ ldd(saved_Greturn1_addr,I0); |
| 3756 __ bind(not_long); | |
| 0 | 3757 #endif |
| 3758 __ ret(); | |
| 3759 __ delayed()->restore(); | |
| 3760 | |
| 3761 masm->flush(); | |
| 3762 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words); | |
| 3763 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); | |
|
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|
3764 #ifdef GRAAL |
|
19462
33a783b15758
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Doug Simon <doug.simon@oracle.com>
parents:
18125
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changeset
|
3765 _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset); |
|
16326
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|
3766 _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset); |
|
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|
3767 #endif |
| 0 | 3768 } |
| 3769 | |
| 3770 #ifdef COMPILER2 | |
| 3771 | |
| 3772 //------------------------------generate_uncommon_trap_blob-------------------- | |
| 3773 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
| 3774 // instead. | |
| 3775 void SharedRuntime::generate_uncommon_trap_blob() { | |
| 3776 // allocate space for the code | |
| 3777 ResourceMark rm; | |
| 3778 // setup code generation tools | |
| 3779 int pad = VerifyThread ? 512 : 0; | |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17850
diff
changeset
|
3780 #ifdef ASSERT |
|
4957
931e5f39e365
7147064: assert(allocates2(pc)) failed: not in CodeBuffer memory: 0xffffffff778d9d60 <= 0xffffffff778da69c
kvn
parents:
4873
diff
changeset
|
3781 if (UseStackBanging) { |
|
931e5f39e365
7147064: assert(allocates2(pc)) failed: not in CodeBuffer memory: 0xffffffff778d9d60 <= 0xffffffff778da69c
kvn
parents:
4873
diff
changeset
|
3782 pad += StackShadowPages*16 + 32; |
|
931e5f39e365
7147064: assert(allocates2(pc)) failed: not in CodeBuffer memory: 0xffffffff778d9d60 <= 0xffffffff778da69c
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parents:
4873
diff
changeset
|
3783 } |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
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17850
diff
changeset
|
3784 #endif |
| 0 | 3785 #ifdef _LP64 |
| 3786 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512); | |
| 3787 #else | |
| 3788 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread) | |
| 3789 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread) | |
| 3790 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512); | |
| 3791 #endif | |
| 3792 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3793 Register O2UnrollBlock = O2; | |
| 3794 Register O2klass_index = O2; | |
| 3795 | |
| 3796 // | |
| 3797 // This is the entry point for all traps the compiler takes when it thinks | |
| 3798 // it cannot handle further execution of compilation code. The frame is | |
| 3799 // deoptimized in these cases and converted into interpreter frames for | |
| 3800 // execution | |
| 3801 // The steps taken by this frame are as follows: | |
| 3802 // - push a fake "unpack_frame" | |
| 3803 // - call the C routine Deoptimization::uncommon_trap (this function | |
| 3804 // packs the current compiled frame into vframe arrays and returns | |
| 3805 // information about the number and size of interpreter frames which | |
| 3806 // are equivalent to the frame which is being deoptimized) | |
| 3807 // - deallocate the "unpack_frame" | |
| 3808 // - deallocate the deoptimization frame | |
| 3809 // - in a loop using the information returned in the previous step | |
| 3810 // push interpreter frames; | |
| 3811 // - create a dummy "unpack_frame" | |
| 3812 // - call the C routine: Deoptimization::unpack_frames (this function | |
| 3813 // lays out values on the interpreter frame which was just created) | |
| 3814 // - deallocate the dummy unpack_frame | |
| 3815 // - return to the interpreter entry point | |
| 3816 // | |
| 3817 // Refer to the following methods for more information: | |
| 3818 // - Deoptimization::uncommon_trap | |
| 3819 // - Deoptimization::unpack_frame | |
| 3820 | |
| 3821 // the unloaded class index is in O0 (first parameter to this blob) | |
| 3822 | |
| 3823 // push a dummy "unpack_frame" | |
| 3824 // and call Deoptimization::uncommon_trap to pack the compiled frame into | |
| 3825 // vframe array and return the UnrollBlock information | |
| 3826 __ save_frame(0); | |
| 3827 __ set_last_Java_frame(SP, noreg); | |
| 3828 __ mov(I0, O2klass_index); | |
| 3829 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index); | |
| 3830 __ reset_last_Java_frame(); | |
| 3831 __ mov(O0, O2UnrollBlock->after_save()); | |
| 3832 __ restore(); | |
| 3833 | |
| 3834 // deallocate the deoptimized frame taking care to preserve the return values | |
| 3835 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
| 3836 __ restore(); | |
| 3837 | |
| 3838 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
| 3839 | |
| 3840 make_new_frames(masm, false); | |
| 3841 | |
| 3842 // push a dummy "unpack_frame" taking care of float return values and | |
| 3843 // call Deoptimization::unpack_frames to have the unpacker layout | |
| 3844 // information in the interpreter frames just created and then return | |
| 3845 // to the interpreter entry point | |
| 3846 __ save_frame(0); | |
| 3847 __ set_last_Java_frame(SP, noreg); | |
| 3848 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case | |
| 3849 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3); | |
| 3850 __ reset_last_Java_frame(); | |
| 3851 __ ret(); | |
| 3852 __ delayed()->restore(); | |
| 3853 | |
| 3854 masm->flush(); | |
| 3855 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize); | |
| 3856 } | |
| 3857 | |
| 3858 #endif // COMPILER2 | |
| 3859 | |
| 3860 //------------------------------generate_handler_blob------------------- | |
| 3861 // | |
| 3862 // Generate a special Compile2Runtime blob that saves all registers, and sets | |
| 3863 // up an OopMap. | |
| 3864 // | |
| 3865 // This blob is jumped to (via a breakpoint and the signal handler) from a | |
| 3866 // safepoint in compiled code. On entry to this blob, O7 contains the | |
| 3867 // address in the original nmethod at which we should resume normal execution. | |
| 3868 // Thus, this blob looks like a subroutine which must preserve lots of | |
| 3869 // registers and return normally. Note that O7 is never register-allocated, | |
| 3870 // so it is guaranteed to be free here. | |
| 3871 // | |
| 3872 | |
| 3873 // The hardest part of what this blob must do is to save the 64-bit %o | |
| 3874 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and | |
| 3875 // an interrupt will chop off their heads. Making space in the caller's frame | |
| 3876 // first will let us save the 64-bit %o's before save'ing, but we cannot hand | |
| 3877 // the adjusted FP off to the GC stack-crawler: this will modify the caller's | |
| 3878 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save | |
| 3879 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP). | |
| 3880 // Tricky, tricky, tricky... | |
| 3881 | |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6790
diff
changeset
|
3882 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { |
| 0 | 3883 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
| 3884 | |
| 3885 // allocate space for the code | |
| 3886 ResourceMark rm; | |
| 3887 // setup code generation tools | |
| 3888 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
| 3889 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
| 3890 // even larger with TraceJumps | |
| 3891 int pad = TraceJumps ? 512 : 0; | |
| 3892 CodeBuffer buffer("handler_blob", 1600 + pad, 512); | |
| 3893 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3894 int frame_size_words; | |
| 3895 OopMapSet *oop_maps = new OopMapSet(); | |
| 3896 OopMap* map = NULL; | |
| 3897 | |
| 3898 int start = __ offset(); | |
| 3899 | |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6790
diff
changeset
|
3900 bool cause_return = (poll_type == POLL_AT_RETURN); |
| 0 | 3901 // If this causes a return before the processing, then do a "restore" |
| 3902 if (cause_return) { | |
| 3903 __ restore(); | |
| 3904 } else { | |
| 3905 // Make it look like we were called via the poll | |
| 3906 // so that frame constructor always sees a valid return address | |
| 3907 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7); | |
| 3908 __ sub(O7, frame::pc_return_offset, O7); | |
| 3909 } | |
| 3910 | |
| 3911 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3912 | |
| 3913 // setup last_Java_sp (blows G4) | |
| 3914 __ set_last_Java_frame(SP, noreg); | |
| 3915 | |
| 3916 // call into the runtime to handle illegal instructions exception | |
| 3917 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
| 3918 __ mov(G2_thread, O0); | |
| 3919 __ save_thread(L7_thread_cache); | |
| 3920 __ call(call_ptr); | |
| 3921 __ delayed()->nop(); | |
| 3922 | |
| 3923 // Set an oopmap for the call site. | |
| 3924 // We need this not only for callee-saved registers, but also for volatile | |
| 3925 // registers that the compiler might be keeping live across a safepoint. | |
| 3926 | |
| 3927 oop_maps->add_gc_map( __ offset() - start, map); | |
| 3928 | |
| 3929 __ restore_thread(L7_thread_cache); | |
| 3930 // clear last_Java_sp | |
| 3931 __ reset_last_Java_frame(); | |
| 3932 | |
| 3933 // Check for exceptions | |
| 3934 Label pending; | |
| 3935 | |
| 3936 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
| 3839 | 3937 __ br_notnull_short(O1, Assembler::pn, pending); |
| 0 | 3938 |
| 3939 RegisterSaver::restore_live_registers(masm); | |
| 3940 | |
| 3941 // We are back the the original state on entry and ready to go. | |
| 3942 | |
| 3943 __ retl(); | |
| 3944 __ delayed()->nop(); | |
| 3945 | |
| 3946 // Pending exception after the safepoint | |
| 3947 | |
| 3948 __ bind(pending); | |
| 3949 | |
| 3950 RegisterSaver::restore_live_registers(masm); | |
| 3951 | |
| 3952 // We are back the the original state on entry. | |
| 3953 | |
| 3954 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
| 3955 // so it looks like the original nmethod called forward_exception_entry. | |
| 3956 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
| 3957 __ JMP(O0, 0); | |
| 3958 __ delayed()->nop(); | |
| 3959 | |
| 3960 // ------------- | |
| 3961 // make sure all code is generated | |
| 3962 masm->flush(); | |
| 3963 | |
| 3964 // return exception blob | |
| 3965 return SafepointBlob::create(&buffer, oop_maps, frame_size_words); | |
| 3966 } | |
| 3967 | |
| 3968 // | |
| 3969 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss | |
| 3970 // | |
| 3971 // Generate a stub that calls into vm to find out the proper destination | |
| 3972 // of a java call. All the argument registers are live at this point | |
| 3973 // but since this is generic code we don't know what they are and the caller | |
| 3974 // must do any gc of the args. | |
| 3975 // | |
|
3442
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7045514: SPARC assembly code for JSR 292 ricochet frames
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2405
diff
changeset
|
3976 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { |
| 0 | 3977 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
| 3978 | |
| 3979 // allocate space for the code | |
| 3980 ResourceMark rm; | |
| 3981 // setup code generation tools | |
| 3982 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
| 3983 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
| 3984 // even larger with TraceJumps | |
| 3985 int pad = TraceJumps ? 512 : 0; | |
| 3986 CodeBuffer buffer(name, 1600 + pad, 512); | |
| 3987 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3988 int frame_size_words; | |
| 3989 OopMapSet *oop_maps = new OopMapSet(); | |
| 3990 OopMap* map = NULL; | |
| 3991 | |
| 3992 int start = __ offset(); | |
| 3993 | |
| 3994 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3995 | |
| 3996 int frame_complete = __ offset(); | |
| 3997 | |
| 3998 // setup last_Java_sp (blows G4) | |
| 3999 __ set_last_Java_frame(SP, noreg); | |
| 4000 | |
| 4001 // call into the runtime to handle illegal instructions exception | |
| 4002 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
| 4003 __ mov(G2_thread, O0); | |
| 4004 __ save_thread(L7_thread_cache); | |
| 4005 __ call(destination, relocInfo::runtime_call_type); | |
| 4006 __ delayed()->nop(); | |
| 4007 | |
| 4008 // O0 contains the address we are going to jump to assuming no exception got installed | |
| 4009 | |
| 4010 // Set an oopmap for the call site. | |
| 4011 // We need this not only for callee-saved registers, but also for volatile | |
| 4012 // registers that the compiler might be keeping live across a safepoint. | |
| 4013 | |
| 4014 oop_maps->add_gc_map( __ offset() - start, map); | |
| 4015 | |
| 4016 __ restore_thread(L7_thread_cache); | |
| 4017 // clear last_Java_sp | |
| 4018 __ reset_last_Java_frame(); | |
| 4019 | |
| 4020 // Check for exceptions | |
| 4021 Label pending; | |
| 4022 | |
| 4023 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
| 3839 | 4024 __ br_notnull_short(O1, Assembler::pn, pending); |
| 0 | 4025 |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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6266
diff
changeset
|
4026 // get the returned Method* |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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6266
diff
changeset
|
4027 |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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6266
diff
changeset
|
4028 __ get_vm_result_2(G5_method); |
| 0 | 4029 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS); |
| 4030 | |
| 4031 // O0 is where we want to jump, overwrite G3 which is saved and scratch | |
| 4032 | |
| 4033 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS); | |
| 4034 | |
| 4035 RegisterSaver::restore_live_registers(masm); | |
| 4036 | |
| 4037 // We are back the the original state on entry and ready to go. | |
| 4038 | |
| 4039 __ JMP(G3, 0); | |
| 4040 __ delayed()->nop(); | |
| 4041 | |
| 4042 // Pending exception after the safepoint | |
| 4043 | |
| 4044 __ bind(pending); | |
| 4045 | |
| 4046 RegisterSaver::restore_live_registers(masm); | |
| 4047 | |
| 4048 // We are back the the original state on entry. | |
| 4049 | |
| 4050 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
| 4051 // so it looks like the original nmethod called forward_exception_entry. | |
| 4052 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
| 4053 __ JMP(O0, 0); | |
| 4054 __ delayed()->nop(); | |
| 4055 | |
| 4056 // ------------- | |
| 4057 // make sure all code is generated | |
| 4058 masm->flush(); | |
| 4059 | |
| 4060 // return the blob | |
| 4061 // frame_size_words or bytes?? | |
| 4062 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); | |
| 4063 } |