Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 14030:f6c04e69cf75
SharedRuntime: add gen_i2c_adapter, implement it with pre-existing methods in each architecture.
| author | Gilles Duboscq <duboscq@ssw.jku.at> |
|---|---|
| date | Thu, 27 Feb 2014 16:05:29 +0100 |
| parents | 096c224171c4 |
| children | d8041d695d19 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
| 1972 | 27 #include "code/debugInfoRec.hpp" |
| 28 #include "code/icBuffer.hpp" | |
| 29 #include "code/vtableStubs.hpp" | |
| 30 #include "interpreter/interpreter.hpp" | |
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31 #include "oops/compiledICHolder.hpp" |
| 1972 | 32 #include "prims/jvmtiRedefineClassesTrace.hpp" |
| 33 #include "runtime/sharedRuntime.hpp" | |
| 34 #include "runtime/vframeArray.hpp" | |
| 35 #include "vmreg_sparc.inline.hpp" | |
| 36 #ifdef COMPILER1 | |
| 37 #include "c1/c1_Runtime1.hpp" | |
| 38 #endif | |
| 39 #ifdef COMPILER2 | |
| 40 #include "opto/runtime.hpp" | |
| 41 #endif | |
| 42 #ifdef SHARK | |
| 43 #include "compiler/compileBroker.hpp" | |
| 44 #include "shark/sharkCompiler.hpp" | |
| 45 #endif | |
| 0 | 46 |
| 47 #define __ masm-> | |
| 48 | |
| 49 | |
| 50 class RegisterSaver { | |
| 51 | |
| 52 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O. | |
| 53 // The Oregs are problematic. In the 32bit build the compiler can | |
| 54 // have O registers live with 64 bit quantities. A window save will | |
| 55 // cut the heads off of the registers. We have to do a very extensive | |
| 56 // stack dance to save and restore these properly. | |
| 57 | |
| 58 // Note that the Oregs problem only exists if we block at either a polling | |
| 59 // page exception a compiled code safepoint that was not originally a call | |
| 60 // or deoptimize following one of these kinds of safepoints. | |
| 61 | |
| 62 // Lots of registers to save. For all builds, a window save will preserve | |
| 63 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit | |
| 64 // builds a window-save will preserve the %o registers. In the LION build | |
| 65 // we need to save the 64-bit %o registers which requires we save them | |
| 66 // before the window-save (as then they become %i registers and get their | |
| 67 // heads chopped off on interrupt). We have to save some %g registers here | |
| 68 // as well. | |
| 69 enum { | |
| 70 // This frame's save area. Includes extra space for the native call: | |
| 71 // vararg's layout space and the like. Briefly holds the caller's | |
| 72 // register save area. | |
| 73 call_args_area = frame::register_save_words_sp_offset + | |
| 74 frame::memory_parameter_word_sp_offset*wordSize, | |
| 75 // Make sure save locations are always 8 byte aligned. | |
| 76 // can't use round_to because it doesn't produce compile time constant | |
| 77 start_of_extra_save_area = ((call_args_area + 7) & ~7), | |
| 78 g1_offset = start_of_extra_save_area, // g-regs needing saving | |
| 79 g3_offset = g1_offset+8, | |
| 80 g4_offset = g3_offset+8, | |
| 81 g5_offset = g4_offset+8, | |
| 82 o0_offset = g5_offset+8, | |
| 83 o1_offset = o0_offset+8, | |
| 84 o2_offset = o1_offset+8, | |
| 85 o3_offset = o2_offset+8, | |
| 86 o4_offset = o3_offset+8, | |
| 87 o5_offset = o4_offset+8, | |
| 88 start_of_flags_save_area = o5_offset+8, | |
| 89 ccr_offset = start_of_flags_save_area, | |
| 90 fsr_offset = ccr_offset + 8, | |
| 91 d00_offset = fsr_offset+8, // Start of float save area | |
| 92 register_save_size = d00_offset+8*32 | |
| 93 }; | |
| 94 | |
| 95 | |
| 96 public: | |
| 97 | |
| 98 static int Oexception_offset() { return o0_offset; }; | |
| 99 static int G3_offset() { return g3_offset; }; | |
| 100 static int G5_offset() { return g5_offset; }; | |
| 101 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); | |
| 102 static void restore_live_registers(MacroAssembler* masm); | |
| 103 | |
| 104 // During deoptimization only the result register need to be restored | |
| 105 // all the other values have already been extracted. | |
| 106 | |
| 107 static void restore_result_registers(MacroAssembler* masm); | |
| 108 }; | |
| 109 | |
| 110 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { | |
| 111 // Record volatile registers as callee-save values in an OopMap so their save locations will be | |
| 112 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for | |
| 113 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers | |
| 114 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame | |
| 115 // (as the stub's I's) when the runtime routine called by the stub creates its frame. | |
| 116 int i; | |
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117 // Always make the frame size 16 byte aligned. |
| 0 | 118 int frame_size = round_to(additional_frame_words + register_save_size, 16); |
| 119 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words | |
| 120 int frame_size_in_slots = frame_size / sizeof(jint); | |
| 121 // CodeBlob frame size is in words. | |
| 122 *total_frame_words = frame_size / wordSize; | |
| 123 // OopMap* map = new OopMap(*total_frame_words, 0); | |
| 124 OopMap* map = new OopMap(frame_size_in_slots, 0); | |
| 125 | |
| 126 #if !defined(_LP64) | |
| 127 | |
| 128 // Save 64-bit O registers; they will get their heads chopped off on a 'save'. | |
| 129 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
| 130 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
| 131 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
| 132 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
| 133 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
| 134 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
| 135 #endif /* _LP64 */ | |
| 136 | |
| 137 __ save(SP, -frame_size, SP); | |
| 138 | |
| 139 #ifndef _LP64 | |
| 140 // Reload the 64 bit Oregs. Although they are now Iregs we load them | |
| 141 // to Oregs here to avoid interrupts cutting off their heads | |
| 142 | |
| 143 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
| 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
| 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
| 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
| 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
| 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
| 149 | |
| 150 __ stx(O0, SP, o0_offset+STACK_BIAS); | |
| 151 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg()); | |
| 152 | |
| 153 __ stx(O1, SP, o1_offset+STACK_BIAS); | |
| 154 | |
| 155 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg()); | |
| 156 | |
| 157 __ stx(O2, SP, o2_offset+STACK_BIAS); | |
| 158 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg()); | |
| 159 | |
| 160 __ stx(O3, SP, o3_offset+STACK_BIAS); | |
| 161 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg()); | |
| 162 | |
| 163 __ stx(O4, SP, o4_offset+STACK_BIAS); | |
| 164 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg()); | |
| 165 | |
| 166 __ stx(O5, SP, o5_offset+STACK_BIAS); | |
| 167 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg()); | |
| 168 #endif /* _LP64 */ | |
| 169 | |
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170 |
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171 #ifdef _LP64 |
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172 int debug_offset = 0; |
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173 #else |
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174 int debug_offset = 4; |
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175 #endif |
| 0 | 176 // Save the G's |
| 177 __ stx(G1, SP, g1_offset+STACK_BIAS); | |
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178 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg()); |
| 0 | 179 |
| 180 __ stx(G3, SP, g3_offset+STACK_BIAS); | |
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181 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg()); |
| 0 | 182 |
| 183 __ stx(G4, SP, g4_offset+STACK_BIAS); | |
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184 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg()); |
| 0 | 185 |
| 186 __ stx(G5, SP, g5_offset+STACK_BIAS); | |
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187 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg()); |
| 0 | 188 |
| 189 // This is really a waste but we'll keep things as they were for now | |
| 190 if (true) { | |
| 191 #ifndef _LP64 | |
| 192 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next()); | |
| 193 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next()); | |
| 194 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next()); | |
| 195 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next()); | |
| 196 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next()); | |
| 197 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next()); | |
| 198 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next()); | |
| 199 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next()); | |
| 200 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next()); | |
| 201 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next()); | |
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202 #endif /* _LP64 */ |
| 0 | 203 } |
| 204 | |
| 205 | |
| 206 // Save the flags | |
| 207 __ rdccr( G5 ); | |
| 208 __ stx(G5, SP, ccr_offset+STACK_BIAS); | |
| 209 __ stxfsr(SP, fsr_offset+STACK_BIAS); | |
| 210 | |
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211 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles) |
| 0 | 212 int offset = d00_offset; |
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213 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
| 0 | 214 FloatRegister f = as_FloatRegister(i); |
| 215 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS); | |
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216 // Record as callee saved both halves of double registers (2 float registers). |
| 0 | 217 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg()); |
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218 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next()); |
| 0 | 219 offset += sizeof(double); |
| 220 } | |
| 221 | |
| 222 // And we're done. | |
| 223 | |
| 224 return map; | |
| 225 } | |
| 226 | |
| 227 | |
| 228 // Pop the current frame and restore all the registers that we | |
| 229 // saved. | |
| 230 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { | |
| 231 | |
| 232 // Restore all the FP registers | |
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233 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
| 0 | 234 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i)); |
| 235 } | |
| 236 | |
| 237 __ ldx(SP, ccr_offset+STACK_BIAS, G1); | |
| 238 __ wrccr (G1) ; | |
| 239 | |
| 240 // Restore the G's | |
| 241 // Note that G2 (AKA GThread) must be saved and restored separately. | |
| 242 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr. | |
| 243 | |
| 244 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
| 245 __ ldx(SP, g3_offset+STACK_BIAS, G3); | |
| 246 __ ldx(SP, g4_offset+STACK_BIAS, G4); | |
| 247 __ ldx(SP, g5_offset+STACK_BIAS, G5); | |
| 248 | |
| 249 | |
| 250 #if !defined(_LP64) | |
| 251 // Restore the 64-bit O's. | |
| 252 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
| 253 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
| 254 __ ldx(SP, o2_offset+STACK_BIAS, O2); | |
| 255 __ ldx(SP, o3_offset+STACK_BIAS, O3); | |
| 256 __ ldx(SP, o4_offset+STACK_BIAS, O4); | |
| 257 __ ldx(SP, o5_offset+STACK_BIAS, O5); | |
| 258 | |
| 259 // And temporarily place them in TLS | |
| 260 | |
| 261 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
| 262 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
| 263 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
| 264 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
| 265 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
| 266 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
| 267 #endif /* _LP64 */ | |
| 268 | |
| 269 // Restore flags | |
| 270 | |
| 271 __ ldxfsr(SP, fsr_offset+STACK_BIAS); | |
| 272 | |
| 273 __ restore(); | |
| 274 | |
| 275 #if !defined(_LP64) | |
| 276 // Now reload the 64bit Oregs after we've restore the window. | |
| 277 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
| 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
| 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
| 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
| 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
| 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
| 283 #endif /* _LP64 */ | |
| 284 | |
| 285 } | |
| 286 | |
| 287 // Pop the current frame and restore the registers that might be holding | |
| 288 // a result. | |
| 289 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { | |
| 290 | |
| 291 #if !defined(_LP64) | |
| 292 // 32bit build returns longs in G1 | |
| 293 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
| 294 | |
| 295 // Retrieve the 64-bit O's. | |
| 296 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
| 297 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
| 298 // and save to TLS | |
| 299 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
| 300 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
| 301 #endif /* _LP64 */ | |
| 302 | |
| 303 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0)); | |
| 304 | |
| 305 __ restore(); | |
| 306 | |
| 307 #if !defined(_LP64) | |
| 308 // Now reload the 64bit Oregs after we've restore the window. | |
| 309 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
| 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
| 311 #endif /* _LP64 */ | |
| 312 | |
| 313 } | |
| 314 | |
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315 // Is vector's size (in bytes) bigger than a size saved by default? |
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316 // 8 bytes FP registers are saved by default on SPARC. |
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317 bool SharedRuntime::is_wide_vector(int size) { |
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318 // Note, MaxVectorSize == 8 on SPARC. |
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319 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size)); |
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320 return size > 8; |
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321 } |
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322 |
| 0 | 323 // The java_calling_convention describes stack locations as ideal slots on |
| 324 // a frame with no abi restrictions. Since we must observe abi restrictions | |
| 325 // (like the placement of the register window) the slots must be biased by | |
| 326 // the following value. | |
| 327 static int reg2offset(VMReg r) { | |
| 328 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
| 329 } | |
| 330 | |
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331 static VMRegPair reg64_to_VMRegPair(Register r) { |
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332 VMRegPair ret; |
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333 if (wordSize == 8) { |
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334 ret.set2(r->as_VMReg()); |
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335 } else { |
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336 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg()); |
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337 } |
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338 return ret; |
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339 } |
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340 |
| 0 | 341 // --------------------------------------------------------------------------- |
| 342 // Read the array of BasicTypes from a signature, and compute where the | |
| 343 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size) | |
| 344 // quantities. Values less than VMRegImpl::stack0 are registers, those above | |
| 345 // refer to 4-byte stack slots. All stack slots are based off of the window | |
| 346 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window, | |
| 347 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register | |
| 348 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit | |
| 349 // integer registers. Values 64-95 are the (32-bit only) float registers. | |
| 350 // Each 32-bit quantity is given its own number, so the integer registers | |
| 351 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is | |
| 352 // an O0-low and an O0-high. Essentially, all int register numbers are doubled. | |
| 353 | |
| 354 // Register results are passed in O0-O5, for outgoing call arguments. To | |
| 355 // convert to incoming arguments, convert all O's to I's. The regs array | |
| 356 // refer to the low and hi 32-bit words of 64-bit registers or stack slots. | |
| 357 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a | |
| 358 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was | |
| 359 // passed (used as a placeholder for the other half of longs and doubles in | |
| 360 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is | |
| 361 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention). | |
| 362 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first() | |
| 363 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the | |
| 364 // same VMRegPair. | |
| 365 | |
| 366 // Note: the INPUTS in sig_bt are in units of Java argument words, which are | |
| 367 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit | |
| 368 // units regardless of build. | |
| 369 | |
| 370 | |
| 371 // --------------------------------------------------------------------------- | |
| 372 // The compiled Java calling convention. The Java convention always passes | |
| 373 // 64-bit values in adjacent aligned locations (either registers or stack), | |
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374 // floats in float registers and doubles in aligned float pairs. There is |
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375 // no backing varargs store for values in registers. |
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376 // In the 32-bit build, longs are passed on the stack (cannot be |
| 0 | 377 // passed in I's, because longs in I's get their heads chopped off at |
| 378 // interrupt). | |
| 379 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, | |
| 380 VMRegPair *regs, | |
| 381 int total_args_passed, | |
| 382 int is_outgoing) { | |
| 383 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); | |
| 384 | |
| 385 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; | |
| 386 const int flt_reg_max = 8; | |
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387 |
| 0 | 388 int int_reg = 0; |
| 389 int flt_reg = 0; | |
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390 int slot = 0; |
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391 |
| 0 | 392 for (int i = 0; i < total_args_passed; i++) { |
| 393 switch (sig_bt[i]) { | |
| 394 case T_INT: | |
| 395 case T_SHORT: | |
| 396 case T_CHAR: | |
| 397 case T_BYTE: | |
| 398 case T_BOOLEAN: | |
| 399 #ifndef _LP64 | |
| 400 case T_OBJECT: | |
| 401 case T_ARRAY: | |
| 402 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
| 403 #endif // _LP64 | |
| 404 if (int_reg < int_reg_max) { | |
| 405 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
| 406 regs[i].set1(r->as_VMReg()); | |
| 407 } else { | |
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408 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
| 0 | 409 } |
| 410 break; | |
| 411 | |
| 412 #ifdef _LP64 | |
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413 case T_LONG: |
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414 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); |
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415 // fall-through |
| 0 | 416 case T_OBJECT: |
| 417 case T_ARRAY: | |
| 418 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
| 419 if (int_reg < int_reg_max) { | |
| 420 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
| 421 regs[i].set2(r->as_VMReg()); | |
| 422 } else { | |
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423 slot = round_to(slot, 2); // align |
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424 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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425 slot += 2; |
| 0 | 426 } |
| 427 break; | |
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428 #else |
| 0 | 429 case T_LONG: |
| 430 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); | |
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431 // On 32-bit SPARC put longs always on the stack to keep the pressure off |
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432 // integer argument registers. They should be used for oops. |
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433 slot = round_to(slot, 2); // align |
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434 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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435 slot += 2; |
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436 #endif |
| 0 | 437 break; |
| 438 | |
| 439 case T_FLOAT: | |
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440 if (flt_reg < flt_reg_max) { |
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441 FloatRegister r = as_FloatRegister(flt_reg++); |
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442 regs[i].set1(r->as_VMReg()); |
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443 } else { |
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444 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
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445 } |
| 0 | 446 break; |
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447 |
| 0 | 448 case T_DOUBLE: |
| 449 assert(sig_bt[i+1] == T_VOID, "expecting half"); | |
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450 if (round_to(flt_reg, 2) + 1 < flt_reg_max) { |
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451 flt_reg = round_to(flt_reg, 2); // align |
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452 FloatRegister r = as_FloatRegister(flt_reg); |
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453 regs[i].set2(r->as_VMReg()); |
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454 flt_reg += 2; |
| 0 | 455 } else { |
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456 slot = round_to(slot, 2); // align |
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457 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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458 slot += 2; |
| 0 | 459 } |
| 460 break; | |
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461 |
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462 case T_VOID: |
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463 regs[i].set_bad(); // Halves of longs & doubles |
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464 break; |
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465 |
| 0 | 466 default: |
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467 fatal(err_msg_res("unknown basic type %d", sig_bt[i])); |
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468 break; |
| 0 | 469 } |
| 470 } | |
| 471 | |
| 472 // retun the amount of stack space these arguments will need. | |
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473 return slot; |
| 0 | 474 } |
| 475 | |
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476 // Helper class mostly to avoid passing masm everywhere, and handle |
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477 // store displacement overflow logic. |
| 0 | 478 class AdapterGenerator { |
| 479 MacroAssembler *masm; | |
| 480 Register Rdisp; | |
| 481 void set_Rdisp(Register r) { Rdisp = r; } | |
| 482 | |
| 483 void patch_callers_callsite(); | |
| 484 | |
| 485 // base+st_off points to top of argument | |
| 1506 | 486 int arg_offset(const int st_off) { return st_off; } |
| 0 | 487 int next_arg_offset(const int st_off) { |
| 1506 | 488 return st_off - Interpreter::stackElementSize; |
|
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489 } |
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490 |
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491 // Argument slot values may be loaded first into a register because |
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492 // they might not fit into displacement. |
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493 RegisterOrConstant arg_slot(const int st_off); |
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494 RegisterOrConstant next_arg_slot(const int st_off); |
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495 |
| 0 | 496 // Stores long into offset pointed to by base |
| 497 void store_c2i_long(Register r, Register base, | |
| 498 const int st_off, bool is_stack); | |
| 499 void store_c2i_object(Register r, Register base, | |
| 500 const int st_off); | |
| 501 void store_c2i_int(Register r, Register base, | |
| 502 const int st_off); | |
| 503 void store_c2i_double(VMReg r_2, | |
| 504 VMReg r_1, Register base, const int st_off); | |
| 505 void store_c2i_float(FloatRegister f, Register base, | |
| 506 const int st_off); | |
| 507 | |
| 508 public: | |
| 509 void gen_c2i_adapter(int total_args_passed, | |
| 510 // VMReg max_arg, | |
| 511 int comp_args_on_stack, // VMRegStackSlots | |
| 512 const BasicType *sig_bt, | |
| 513 const VMRegPair *regs, | |
| 514 Label& skip_fixup); | |
| 515 void gen_i2c_adapter(int total_args_passed, | |
| 516 // VMReg max_arg, | |
| 517 int comp_args_on_stack, // VMRegStackSlots | |
| 518 const BasicType *sig_bt, | |
| 519 const VMRegPair *regs); | |
| 520 | |
| 521 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} | |
| 522 }; | |
| 523 | |
| 524 | |
| 525 // Patch the callers callsite with entry to compiled code if it exists. | |
| 526 void AdapterGenerator::patch_callers_callsite() { | |
| 527 Label L; | |
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528 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
| 3839 | 529 __ br_null(G3_scratch, false, Assembler::pt, L); |
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530 __ delayed()->nop(); |
| 0 | 531 // Call into the VM to patch the caller, then jump to compiled callee |
| 532 __ save_frame(4); // Args in compiled layout; do not blow them | |
| 533 | |
| 534 // Must save all the live Gregs the list is: | |
| 535 // G1: 1st Long arg (32bit build) | |
| 536 // G2: global allocated to TLS | |
| 537 // G3: used in inline cache check (scratch) | |
| 538 // G4: 2nd Long arg (32bit build); | |
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539 // G5: used in inline cache check (Method*) |
| 0 | 540 |
| 541 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops. | |
| 542 | |
| 543 #ifdef _LP64 | |
| 544 // mov(s,d) | |
| 545 __ mov(G1, L1); | |
| 546 __ mov(G4, L4); | |
| 547 __ mov(G5_method, L5); | |
| 548 __ mov(G5_method, O0); // VM needs target method | |
| 549 __ mov(I7, O1); // VM needs caller's callsite | |
| 550 // Must be a leaf call... | |
| 551 // can be very far once the blob has been relocated | |
| 727 | 552 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)); |
| 0 | 553 __ relocate(relocInfo::runtime_call_type); |
| 727 | 554 __ jumpl_to(dest, O7, O7); |
| 0 | 555 __ delayed()->mov(G2_thread, L7_thread_cache); |
| 556 __ mov(L7_thread_cache, G2_thread); | |
| 557 __ mov(L1, G1); | |
| 558 __ mov(L4, G4); | |
| 559 __ mov(L5, G5_method); | |
| 560 #else | |
| 561 __ stx(G1, FP, -8 + STACK_BIAS); | |
| 562 __ stx(G4, FP, -16 + STACK_BIAS); | |
| 563 __ mov(G5_method, L5); | |
| 564 __ mov(G5_method, O0); // VM needs target method | |
| 565 __ mov(I7, O1); // VM needs caller's callsite | |
| 566 // Must be a leaf call... | |
| 567 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type); | |
| 568 __ delayed()->mov(G2_thread, L7_thread_cache); | |
| 569 __ mov(L7_thread_cache, G2_thread); | |
| 570 __ ldx(FP, -8 + STACK_BIAS, G1); | |
| 571 __ ldx(FP, -16 + STACK_BIAS, G4); | |
| 572 __ mov(L5, G5_method); | |
| 573 #endif /* _LP64 */ | |
| 574 | |
| 575 __ restore(); // Restore args | |
| 576 __ bind(L); | |
| 577 } | |
| 578 | |
|
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579 |
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580 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) { |
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581 RegisterOrConstant roc(arg_offset(st_off)); |
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582 return __ ensure_simm13_or_reg(roc, Rdisp); |
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583 } |
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584 |
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585 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) { |
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586 RegisterOrConstant roc(next_arg_offset(st_off)); |
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587 return __ ensure_simm13_or_reg(roc, Rdisp); |
| 0 | 588 } |
| 589 | |
|
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590 |
| 0 | 591 // Stores long into offset pointed to by base |
| 592 void AdapterGenerator::store_c2i_long(Register r, Register base, | |
| 593 const int st_off, bool is_stack) { | |
| 594 #ifdef _LP64 | |
| 595 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
| 596 // data is passed in only 1 slot. | |
| 597 __ stx(r, base, next_arg_slot(st_off)); | |
| 598 #else | |
|
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599 #ifdef COMPILER2 |
| 0 | 600 // Misaligned store of 64-bit data |
| 601 __ stw(r, base, arg_slot(st_off)); // lo bits | |
| 602 __ srlx(r, 32, r); | |
| 603 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
| 604 #else | |
| 605 if (is_stack) { | |
| 606 // Misaligned store of 64-bit data | |
| 607 __ stw(r, base, arg_slot(st_off)); // lo bits | |
| 608 __ srlx(r, 32, r); | |
| 609 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
| 610 } else { | |
| 611 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits | |
| 612 __ stw(r , base, next_arg_slot(st_off)); // hi bits | |
| 613 } | |
| 614 #endif // COMPILER2 | |
|
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615 #endif // _LP64 |
| 0 | 616 } |
| 617 | |
| 618 void AdapterGenerator::store_c2i_object(Register r, Register base, | |
| 619 const int st_off) { | |
| 620 __ st_ptr (r, base, arg_slot(st_off)); | |
| 621 } | |
| 622 | |
| 623 void AdapterGenerator::store_c2i_int(Register r, Register base, | |
| 624 const int st_off) { | |
| 625 __ st (r, base, arg_slot(st_off)); | |
| 626 } | |
| 627 | |
| 628 // Stores into offset pointed to by base | |
| 629 void AdapterGenerator::store_c2i_double(VMReg r_2, | |
| 630 VMReg r_1, Register base, const int st_off) { | |
| 631 #ifdef _LP64 | |
| 632 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
| 633 // data is passed in only 1 slot. | |
| 634 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
| 635 #else | |
| 636 // Need to marshal 64-bit value from misaligned Lesp loads | |
| 637 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
| 638 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) ); | |
| 639 #endif | |
| 640 } | |
| 641 | |
| 642 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, | |
| 643 const int st_off) { | |
| 644 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off)); | |
| 645 } | |
| 646 | |
| 647 void AdapterGenerator::gen_c2i_adapter( | |
| 648 int total_args_passed, | |
| 649 // VMReg max_arg, | |
| 650 int comp_args_on_stack, // VMRegStackSlots | |
| 651 const BasicType *sig_bt, | |
| 652 const VMRegPair *regs, | |
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653 Label& L_skip_fixup) { |
| 0 | 654 |
| 655 // Before we get into the guts of the C2I adapter, see if we should be here | |
| 656 // at all. We've come from compiled code and are attempting to jump to the | |
| 657 // interpreter, which means the caller made a static call to get here | |
| 658 // (vcalls always get a compiled target if there is one). Check for a | |
| 659 // compiled target. If there is one, we need to patch the caller's call. | |
| 660 // However we will run interpreted if we come thru here. The next pass | |
| 661 // thru the call site will run compiled. If we ran compiled here then | |
| 662 // we can (theorectically) do endless i2c->c2i->i2c transitions during | |
| 663 // deopt/uncommon trap cycles. If we always go interpreted here then | |
| 664 // we can have at most one and don't need to play any tricks to keep | |
| 665 // from endlessly growing the stack. | |
| 666 // | |
| 667 // Actually if we detected that we had an i2c->c2i transition here we | |
| 668 // ought to be able to reset the world back to the state of the interpreted | |
| 669 // call and not bother building another interpreter arg area. We don't | |
| 670 // do that at this point. | |
| 671 | |
| 672 patch_callers_callsite(); | |
| 673 | |
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674 __ bind(L_skip_fixup); |
| 0 | 675 |
| 676 // Since all args are passed on the stack, total_args_passed*wordSize is the | |
| 677 // space we need. Add in varargs area needed by the interpreter. Round up | |
| 678 // to stack alignment. | |
| 1506 | 679 const int arg_size = total_args_passed * Interpreter::stackElementSize; |
| 0 | 680 const int varargs_area = |
| 681 (frame::varargs_offset - frame::register_save_words)*wordSize; | |
| 682 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); | |
| 683 | |
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684 const int bias = STACK_BIAS; |
| 0 | 685 const int interp_arg_offset = frame::varargs_offset*wordSize + |
| 1506 | 686 (total_args_passed-1)*Interpreter::stackElementSize; |
| 0 | 687 |
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688 const Register base = SP; |
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689 |
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690 // Make some extra space on the stack. |
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691 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP); |
| 0 | 692 set_Rdisp(G3_scratch); |
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693 |
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694 // Write the args into the outgoing interpreter space. |
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695 for (int i = 0; i < total_args_passed; i++) { |
| 1506 | 696 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; |
| 0 | 697 VMReg r_1 = regs[i].first(); |
| 698 VMReg r_2 = regs[i].second(); | |
| 699 if (!r_1->is_valid()) { | |
| 700 assert(!r_2->is_valid(), ""); | |
| 701 continue; | |
| 702 } | |
| 703 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 | |
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704 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias; |
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705 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp); |
| 0 | 706 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle |
| 707 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); | |
| 708 else __ ldx(base, ld_off, G1_scratch); | |
| 709 } | |
| 710 | |
| 711 if (r_1->is_Register()) { | |
| 712 Register r = r_1->as_Register()->after_restore(); | |
| 713 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | |
| 714 store_c2i_object(r, base, st_off); | |
| 715 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | |
| 716 store_c2i_long(r, base, st_off, r_2->is_stack()); | |
| 717 } else { | |
| 718 store_c2i_int(r, base, st_off); | |
| 719 } | |
| 720 } else { | |
| 721 assert(r_1->is_FloatRegister(), ""); | |
| 722 if (sig_bt[i] == T_FLOAT) { | |
| 723 store_c2i_float(r_1->as_FloatRegister(), base, st_off); | |
| 724 } else { | |
| 725 assert(sig_bt[i] == T_DOUBLE, "wrong type"); | |
| 726 store_c2i_double(r_2, r_1, base, st_off); | |
| 727 } | |
| 728 } | |
| 729 } | |
| 730 | |
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731 // Load the interpreter entry point. |
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732 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); |
| 0 | 733 |
| 734 // Pass O5_savedSP as an argument to the interpreter. | |
| 735 // The interpreter will restore SP to this value before returning. | |
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736 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP); |
| 0 | 737 |
| 738 __ mov((frame::varargs_offset)*wordSize - | |
| 1506 | 739 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); |
| 0 | 740 // Jump to the interpreter just as if interpreter was doing it. |
| 741 __ jmpl(G3_scratch, 0, G0); | |
| 742 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp | |
| 743 // (really L0) is in use by the compiled frame as a generic temp. However, | |
| 744 // the interpreter does not know where its args are without some kind of | |
| 745 // arg pointer being passed in. Pass it in Gargs. | |
| 746 __ delayed()->add(SP, G1, Gargs); | |
| 747 } | |
| 748 | |
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749 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg, |
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750 address code_start, address code_end, |
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751 Label& L_ok) { |
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752 Label L_fail; |
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753 __ set(ExternalAddress(code_start), temp_reg); |
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754 __ set(pointer_delta(code_end, code_start, 1), temp2_reg); |
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755 __ cmp(pc_reg, temp_reg); |
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756 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail); |
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757 __ delayed()->add(temp_reg, temp2_reg, temp_reg); |
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758 __ cmp(pc_reg, temp_reg); |
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759 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok); |
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760 __ bind(L_fail); |
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761 } |
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762 |
| 0 | 763 void AdapterGenerator::gen_i2c_adapter( |
| 764 int total_args_passed, | |
| 765 // VMReg max_arg, | |
| 766 int comp_args_on_stack, // VMRegStackSlots | |
| 767 const BasicType *sig_bt, | |
| 768 const VMRegPair *regs) { | |
| 769 | |
| 770 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame | |
| 771 // layout. Lesp was saved by the calling I-frame and will be restored on | |
| 772 // return. Meanwhile, outgoing arg space is all owned by the callee | |
| 773 // C-frame, so we can mangle it at will. After adjusting the frame size, | |
| 774 // hoist register arguments and repack other args according to the compiled | |
| 775 // code convention. Finally, end in a jump to the compiled code. The entry | |
| 776 // point address is the start of the buffer. | |
| 777 | |
| 778 // We will only enter here from an interpreted frame and never from after | |
| 779 // passing thru a c2i. Azul allowed this but we do not. If we lose the | |
| 780 // race and use a c2i we will remain interpreted for the race loser(s). | |
| 781 // This removes all sorts of headaches on the x86 side and also eliminates | |
| 782 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. | |
| 783 | |
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784 // More detail: |
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785 // Adapters can be frameless because they do not require the caller |
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786 // to perform additional cleanup work, such as correcting the stack pointer. |
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787 // An i2c adapter is frameless because the *caller* frame, which is interpreted, |
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788 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), |
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789 // even if a callee has modified the stack pointer. |
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790 // A c2i adapter is frameless because the *callee* frame, which is interpreted, |
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791 // routinely repairs its caller's stack pointer (from sender_sp, which is set |
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792 // up via the senderSP register). |
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793 // In other words, if *either* the caller or callee is interpreted, we can |
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794 // get the stack pointer repaired after a call. |
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795 // This is why c2i and i2c adapters cannot be indefinitely composed. |
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796 // In particular, if a c2i adapter were to somehow call an i2c adapter, |
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797 // both caller and callee would be compiled methods, and neither would |
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798 // clean up the stack pointer changes performed by the two adapters. |
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799 // If this happens, control eventually transfers back to the compiled |
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800 // caller, but with an uncorrected stack, causing delayed havoc. |
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801 |
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802 if (VerifyAdapterCalls && |
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803 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { |
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804 // So, let's test for cascading c2i/i2c adapters right now. |
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805 // assert(Interpreter::contains($return_addr) || |
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806 // StubRoutines::contains($return_addr), |
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807 // "i2c adapter must return to an interpreter frame"); |
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808 __ block_comment("verify_i2c { "); |
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809 Label L_ok; |
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810 if (Interpreter::code() != NULL) |
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811 range_check(masm, O7, O0, O1, |
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812 Interpreter::code()->code_start(), Interpreter::code()->code_end(), |
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813 L_ok); |
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814 if (StubRoutines::code1() != NULL) |
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815 range_check(masm, O7, O0, O1, |
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816 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), |
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817 L_ok); |
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818 if (StubRoutines::code2() != NULL) |
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819 range_check(masm, O7, O0, O1, |
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820 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), |
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821 L_ok); |
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822 const char* msg = "i2c adapter must return to an interpreter frame"; |
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823 __ block_comment(msg); |
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824 __ stop(msg); |
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825 __ bind(L_ok); |
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826 __ block_comment("} verify_i2ce "); |
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827 } |
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828 |
| 0 | 829 // As you can see from the list of inputs & outputs there are not a lot |
| 830 // of temp registers to work with: mostly G1, G3 & G4. | |
| 831 | |
| 832 // Inputs: | |
| 833 // G2_thread - TLS | |
| 834 // G5_method - Method oop | |
| 710 | 835 // G4 (Gargs) - Pointer to interpreter's args |
| 836 // O0..O4 - free for scratch | |
| 837 // O5_savedSP - Caller's saved SP, to be restored if needed | |
| 0 | 838 // O6 - Current SP! |
| 839 // O7 - Valid return address | |
| 710 | 840 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
| 0 | 841 |
| 842 // Outputs: | |
| 843 // G2_thread - TLS | |
| 844 // O0-O5 - Outgoing args in compiled layout | |
| 845 // O6 - Adjusted or restored SP | |
| 846 // O7 - Valid return address | |
| 1564 | 847 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
| 0 | 848 // F0-F7 - more outgoing args |
| 849 | |
| 850 | |
| 710 | 851 // Gargs is the incoming argument base, and also an outgoing argument. |
| 0 | 852 __ sub(Gargs, BytesPerWord, Gargs); |
| 853 | |
| 854 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME | |
| 855 // WITH O7 HOLDING A VALID RETURN PC | |
| 856 // | |
| 857 // | | | |
| 858 // : java stack : | |
| 859 // | | | |
| 860 // +--------------+ <--- start of outgoing args | |
| 861 // | receiver | | | |
| 862 // : rest of args : |---size is java-arg-words | |
| 863 // | | | | |
| 864 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I | |
| 865 // | | | | |
| 866 // : unused : |---Space for max Java stack, plus stack alignment | |
| 867 // | | | | |
| 868 // +--------------+ <--- SP + 16*wordsize | |
| 869 // | | | |
| 870 // : window : | |
| 871 // | | | |
| 872 // +--------------+ <--- SP | |
| 873 | |
| 874 // WE REPACK THE STACK. We use the common calling convention layout as | |
| 875 // discovered by calling SharedRuntime::calling_convention. We assume it | |
| 876 // causes an arbitrary shuffle of memory, which may require some register | |
| 877 // temps to do the shuffle. We hope for (and optimize for) the case where | |
| 878 // temps are not needed. We may have to resize the stack slightly, in case | |
| 879 // we need alignment padding (32-bit interpreter can pass longs & doubles | |
| 880 // misaligned, but the compilers expect them aligned). | |
| 881 // | |
| 882 // | | | |
| 883 // : java stack : | |
| 884 // | | | |
| 885 // +--------------+ <--- start of outgoing args | |
| 886 // | pad, align | | | |
| 887 // +--------------+ | | |
|
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888 // | ints, longs, | | |
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889 // | floats, | |---Outgoing stack args. |
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890 // : doubles : | First few args in registers. |
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891 // | | | |
| 0 | 892 // +--------------+ <--- SP' + 16*wordsize |
| 893 // | | | |
| 894 // : window : | |
| 895 // | | | |
| 896 // +--------------+ <--- SP' | |
| 897 | |
| 898 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME | |
| 899 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP | |
| 900 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. | |
| 901 | |
| 902 // Cut-out for having no stack args. Since up to 6 args are passed | |
| 903 // in registers, we will commonly have no stack args. | |
| 904 if (comp_args_on_stack > 0) { | |
| 905 // Convert VMReg stack slots to words. | |
| 906 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; | |
| 907 // Round up to miminum stack alignment, in wordSize | |
| 908 comp_words_on_stack = round_to(comp_words_on_stack, 2); | |
| 909 // Now compute the distance from Lesp to SP. This calculation does not | |
| 910 // include the space for total_args_passed because Lesp has not yet popped | |
| 911 // the arguments. | |
| 912 __ sub(SP, (comp_words_on_stack)*wordSize, SP); | |
| 913 } | |
| 914 | |
| 915 // Now generate the shuffle code. Pick up all register args and move the | |
| 916 // rest through G1_scratch. | |
|
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917 for (int i = 0; i < total_args_passed; i++) { |
| 0 | 918 if (sig_bt[i] == T_VOID) { |
| 919 // Longs and doubles are passed in native word order, but misaligned | |
| 920 // in the 32-bit build. | |
| 921 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | |
| 922 continue; | |
| 923 } | |
| 924 | |
| 925 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the | |
| 926 // 32-bit build and aligned in the 64-bit build. Look for the obvious | |
| 927 // ldx/lddf optimizations. | |
| 928 | |
| 929 // Load in argument order going down. | |
| 1506 | 930 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; |
| 0 | 931 set_Rdisp(G1_scratch); |
| 932 | |
| 933 VMReg r_1 = regs[i].first(); | |
| 934 VMReg r_2 = regs[i].second(); | |
| 935 if (!r_1->is_valid()) { | |
| 936 assert(!r_2->is_valid(), ""); | |
| 937 continue; | |
| 938 } | |
| 939 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9 | |
| 940 r_1 = F8->as_VMReg(); // as part of the load/store shuffle | |
| 941 if (r_2->is_valid()) r_2 = r_1->next(); | |
| 942 } | |
| 943 if (r_1->is_Register()) { // Register argument | |
| 944 Register r = r_1->as_Register()->after_restore(); | |
| 945 if (!r_2->is_valid()) { | |
| 946 __ ld(Gargs, arg_slot(ld_off), r); | |
| 947 } else { | |
| 948 #ifdef _LP64 | |
| 949 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
| 950 // data is passed in only 1 slot. | |
|
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951 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? |
| 0 | 952 next_arg_slot(ld_off) : arg_slot(ld_off); |
| 953 __ ldx(Gargs, slot, r); | |
| 954 #else | |
|
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955 fatal("longs should be on stack"); |
| 0 | 956 #endif |
| 957 } | |
| 958 } else { | |
| 959 assert(r_1->is_FloatRegister(), ""); | |
| 960 if (!r_2->is_valid()) { | |
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961 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); |
| 0 | 962 } else { |
| 963 #ifdef _LP64 | |
| 964 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
| 965 // data is passed in only 1 slot. This code also handles longs that | |
| 966 // are passed on the stack, but need a stack-to-stack move through a | |
| 967 // spare float register. | |
|
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968 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? |
| 0 | 969 next_arg_slot(ld_off) : arg_slot(ld_off); |
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970 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); |
| 0 | 971 #else |
| 972 // Need to marshal 64-bit value from misaligned Lesp loads | |
| 973 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); | |
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974 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); |
| 0 | 975 #endif |
| 976 } | |
| 977 } | |
| 978 // Was the argument really intended to be on the stack, but was loaded | |
| 979 // into F8/F9? | |
| 980 if (regs[i].first()->is_stack()) { | |
| 981 assert(r_1->as_FloatRegister() == F8, "fix this code"); | |
| 982 // Convert stack slot to an SP offset | |
| 983 int st_off = reg2offset(regs[i].first()) + STACK_BIAS; | |
| 984 // Store down the shuffled stack word. Target address _is_ aligned. | |
|
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985 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); |
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986 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); |
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987 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); |
| 0 | 988 } |
| 989 } | |
| 990 | |
| 991 // Jump to the compiled code just as if compiled code was doing it. | |
|
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992 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); |
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993 |
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994 // 6243940 We might end up in handle_wrong_method if |
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995 // the callee is deoptimized as we race thru here. If that |
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996 // happens we don't want to take a safepoint because the |
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997 // caller frame will look interpreted and arguments are now |
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998 // "compiled" so it is much better to make this transition |
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999 // invisible to the stack walking code. Unfortunately if |
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1000 // we try and find the callee by normal means a safepoint |
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1001 // is possible. So we stash the desired callee in the thread |
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1002 // and the vm will find there should this case occur. |
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1003 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); |
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1004 __ st_ptr(G5_method, callee_target_addr); |
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1005 __ jmpl(G3, 0, G0); |
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1006 __ delayed()->nop(); |
| 0 | 1007 } |
| 1008 | |
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1009 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, |
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1010 int total_args_passed, |
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1011 int comp_args_on_stack, |
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1012 const BasicType *sig_bt, |
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1013 const VMRegPair *regs) { |
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1014 AdapterGenerator agen(masm); |
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1015 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs); |
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1016 } |
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1017 |
| 0 | 1018 // --------------------------------------------------------------- |
| 1019 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, | |
| 1020 int total_args_passed, | |
| 1021 // VMReg max_arg, | |
| 1022 int comp_args_on_stack, // VMRegStackSlots | |
| 1023 const BasicType *sig_bt, | |
|
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1024 const VMRegPair *regs, |
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1025 AdapterFingerPrint* fingerprint) { |
| 0 | 1026 address i2c_entry = __ pc(); |
| 1027 | |
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1028 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); |
| 0 | 1029 |
| 1030 | |
| 1031 // ------------------------------------------------------------------------- | |
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1032 // Generate a C2I adapter. On entry we know G5 holds the Method*. The |
| 0 | 1033 // args start out packed in the compiled layout. They need to be unpacked |
| 1034 // into the interpreter layout. This will almost always require some stack | |
| 1035 // space. We grow the current (compiled) stack, then repack the args. We | |
| 1036 // finally end in a jump to the generic interpreter entry point. On exit | |
| 1037 // from the interpreter, the interpreter will restore our SP (lest the | |
| 1038 // compiled code, which relys solely on SP and not FP, get sick). | |
| 1039 | |
| 1040 address c2i_unverified_entry = __ pc(); | |
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1041 Label L_skip_fixup; |
| 0 | 1042 { |
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1043 Register R_temp = G1; // another scratch register |
| 0 | 1044 |
| 727 | 1045 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
| 0 | 1046 |
| 1047 __ verify_oop(O0); | |
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1048 __ load_klass(O0, G3_scratch); |
| 0 | 1049 |
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1050 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); |
| 0 | 1051 __ cmp(G3_scratch, R_temp); |
| 1052 | |
| 1053 Label ok, ok2; | |
| 1054 __ brx(Assembler::equal, false, Assembler::pt, ok); | |
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1055 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); |
| 727 | 1056 __ jump_to(ic_miss, G3_scratch); |
| 0 | 1057 __ delayed()->nop(); |
| 1058 | |
| 1059 __ bind(ok); | |
| 1060 // Method might have been compiled since the call site was patched to | |
| 1061 // interpreted if that is the case treat it as a miss so we can get | |
| 1062 // the call site corrected. | |
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1063 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
| 0 | 1064 __ bind(ok2); |
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1065 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup); |
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1066 __ delayed()->nop(); |
| 727 | 1067 __ jump_to(ic_miss, G3_scratch); |
| 0 | 1068 __ delayed()->nop(); |
| 1069 | |
| 1070 } | |
| 1071 | |
| 1072 address c2i_entry = __ pc(); | |
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1073 AdapterGenerator agen(masm); |
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1074 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup); |
| 0 | 1075 |
| 1076 __ flush(); | |
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1077 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); |
| 0 | 1078 |
| 1079 } | |
| 1080 | |
| 1081 // Helper function for native calling conventions | |
| 1082 static VMReg int_stk_helper( int i ) { | |
| 1083 // Bias any stack based VMReg we get by ignoring the window area | |
| 1084 // but not the register parameter save area. | |
| 1085 // | |
| 1086 // This is strange for the following reasons. We'd normally expect | |
| 1087 // the calling convention to return an VMReg for a stack slot | |
| 1088 // completely ignoring any abi reserved area. C2 thinks of that | |
| 1089 // abi area as only out_preserve_stack_slots. This does not include | |
| 1090 // the area allocated by the C abi to store down integer arguments | |
| 1091 // because the java calling convention does not use it. So | |
| 1092 // since c2 assumes that there are only out_preserve_stack_slots | |
| 1093 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack | |
| 1094 // location the c calling convention must add in this bias amount | |
| 1095 // to make up for the fact that the out_preserve_stack_slots is | |
| 1096 // insufficient for C calls. What a mess. I sure hope those 6 | |
| 1097 // stack words were worth it on every java call! | |
| 1098 | |
| 1099 // Another way of cleaning this up would be for out_preserve_stack_slots | |
| 1100 // to take a parameter to say whether it was C or java calling conventions. | |
| 1101 // Then things might look a little better (but not much). | |
| 1102 | |
| 1103 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM; | |
| 1104 if( mem_parm_offset < 0 ) { | |
| 1105 return as_oRegister(i)->as_VMReg(); | |
| 1106 } else { | |
| 1107 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word; | |
| 1108 // Now return a biased offset that will be correct when out_preserve_slots is added back in | |
| 1109 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots()); | |
| 1110 } | |
| 1111 } | |
| 1112 | |
| 1113 | |
| 1114 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, | |
| 1115 VMRegPair *regs, | |
| 1116 int total_args_passed) { | |
| 1117 | |
| 1118 // Return the number of VMReg stack_slots needed for the args. | |
| 1119 // This value does not include an abi space (like register window | |
| 1120 // save area). | |
| 1121 | |
| 1122 // The native convention is V8 if !LP64 | |
| 1123 // The LP64 convention is the V9 convention which is slightly more sane. | |
| 1124 | |
| 1125 // We return the amount of VMReg stack slots we need to reserve for all | |
| 1126 // the arguments NOT counting out_preserve_stack_slots. Since we always | |
| 1127 // have space for storing at least 6 registers to memory we start with that. | |
| 1128 // See int_stk_helper for a further discussion. | |
| 1129 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots(); | |
| 1130 | |
| 1131 #ifdef _LP64 | |
| 1132 // V9 convention: All things "as-if" on double-wide stack slots. | |
| 1133 // Hoist any int/ptr/long's in the first 6 to int regs. | |
| 1134 // Hoist any flt/dbl's in the first 16 dbl regs. | |
| 1135 int j = 0; // Count of actual args, not HALVES | |
| 1136 for( int i=0; i<total_args_passed; i++, j++ ) { | |
| 1137 switch( sig_bt[i] ) { | |
| 1138 case T_BOOLEAN: | |
| 1139 case T_BYTE: | |
| 1140 case T_CHAR: | |
| 1141 case T_INT: | |
| 1142 case T_SHORT: | |
| 1143 regs[i].set1( int_stk_helper( j ) ); break; | |
| 1144 case T_LONG: | |
| 1145 assert( sig_bt[i+1] == T_VOID, "expecting half" ); | |
| 1146 case T_ADDRESS: // raw pointers, like current thread, for VM calls | |
| 1147 case T_ARRAY: | |
| 1148 case T_OBJECT: | |
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1149 case T_METADATA: |
| 0 | 1150 regs[i].set2( int_stk_helper( j ) ); |
| 1151 break; | |
| 1152 case T_FLOAT: | |
| 1153 if ( j < 16 ) { | |
| 1154 // V9ism: floats go in ODD registers | |
| 1155 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg()); | |
| 1156 } else { | |
| 1157 // V9ism: floats go in ODD stack slot | |
| 1158 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1))); | |
| 1159 } | |
| 1160 break; | |
| 1161 case T_DOUBLE: | |
| 1162 assert( sig_bt[i+1] == T_VOID, "expecting half" ); | |
| 1163 if ( j < 16 ) { | |
| 1164 // V9ism: doubles go in EVEN/ODD regs | |
| 1165 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg()); | |
| 1166 } else { | |
| 1167 // V9ism: doubles go in EVEN/ODD stack slots | |
| 1168 regs[i].set2(VMRegImpl::stack2reg(j<<1)); | |
| 1169 } | |
| 1170 break; | |
| 1171 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES | |
| 1172 default: | |
| 1173 ShouldNotReachHere(); | |
| 1174 } | |
| 1175 if (regs[i].first()->is_stack()) { | |
| 1176 int off = regs[i].first()->reg2stack(); | |
| 1177 if (off > max_stack_slots) max_stack_slots = off; | |
| 1178 } | |
| 1179 if (regs[i].second()->is_stack()) { | |
| 1180 int off = regs[i].second()->reg2stack(); | |
| 1181 if (off > max_stack_slots) max_stack_slots = off; | |
| 1182 } | |
| 1183 } | |
| 1184 | |
| 1185 #else // _LP64 | |
| 1186 // V8 convention: first 6 things in O-regs, rest on stack. | |
| 1187 // Alignment is willy-nilly. | |
| 1188 for( int i=0; i<total_args_passed; i++ ) { | |
| 1189 switch( sig_bt[i] ) { | |
| 1190 case T_ADDRESS: // raw pointers, like current thread, for VM calls | |
| 1191 case T_ARRAY: | |
| 1192 case T_BOOLEAN: | |
| 1193 case T_BYTE: | |
| 1194 case T_CHAR: | |
| 1195 case T_FLOAT: | |
| 1196 case T_INT: | |
| 1197 case T_OBJECT: | |
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1198 case T_METADATA: |
| 0 | 1199 case T_SHORT: |
| 1200 regs[i].set1( int_stk_helper( i ) ); | |
| 1201 break; | |
| 1202 case T_DOUBLE: | |
| 1203 case T_LONG: | |
| 1204 assert( sig_bt[i+1] == T_VOID, "expecting half" ); | |
| 1205 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) ); | |
| 1206 break; | |
| 1207 case T_VOID: regs[i].set_bad(); break; | |
| 1208 default: | |
| 1209 ShouldNotReachHere(); | |
| 1210 } | |
| 1211 if (regs[i].first()->is_stack()) { | |
| 1212 int off = regs[i].first()->reg2stack(); | |
| 1213 if (off > max_stack_slots) max_stack_slots = off; | |
| 1214 } | |
| 1215 if (regs[i].second()->is_stack()) { | |
| 1216 int off = regs[i].second()->reg2stack(); | |
| 1217 if (off > max_stack_slots) max_stack_slots = off; | |
| 1218 } | |
| 1219 } | |
| 1220 #endif // _LP64 | |
| 1221 | |
| 1222 return round_to(max_stack_slots + 1, 2); | |
| 1223 | |
| 1224 } | |
| 1225 | |
| 1226 | |
| 1227 // --------------------------------------------------------------------------- | |
| 1228 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
| 1229 switch (ret_type) { | |
| 1230 case T_FLOAT: | |
| 1231 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS); | |
| 1232 break; | |
| 1233 case T_DOUBLE: | |
| 1234 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS); | |
| 1235 break; | |
| 1236 } | |
| 1237 } | |
| 1238 | |
| 1239 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
| 1240 switch (ret_type) { | |
| 1241 case T_FLOAT: | |
| 1242 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0); | |
| 1243 break; | |
| 1244 case T_DOUBLE: | |
| 1245 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0); | |
| 1246 break; | |
| 1247 } | |
| 1248 } | |
| 1249 | |
| 1250 // Check and forward and pending exception. Thread is stored in | |
| 1251 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there | |
| 1252 // is no exception handler. We merely pop this frame off and throw the | |
| 1253 // exception in the caller's frame. | |
| 1254 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) { | |
| 1255 Label L; | |
| 1256 __ br_null(Rex_oop, false, Assembler::pt, L); | |
| 1257 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception | |
| 1258 // Since this is a native call, we *know* the proper exception handler | |
| 1259 // without calling into the VM: it's the empty function. Just pop this | |
| 1260 // frame and then jump to forward_exception_entry; O7 will contain the | |
| 1261 // native caller's return PC. | |
| 727 | 1262 AddressLiteral exception_entry(StubRoutines::forward_exception_entry()); |
| 1263 __ jump_to(exception_entry, G3_scratch); | |
| 0 | 1264 __ delayed()->restore(); // Pop this frame off. |
| 1265 __ bind(L); | |
| 1266 } | |
| 1267 | |
| 1268 // A simple move of integer like type | |
| 1269 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1270 if (src.first()->is_stack()) { | |
| 1271 if (dst.first()->is_stack()) { | |
| 1272 // stack to stack | |
| 1273 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1274 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1275 } else { | |
| 1276 // stack to reg | |
| 1277 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1278 } | |
| 1279 } else if (dst.first()->is_stack()) { | |
| 1280 // reg to stack | |
| 1281 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1282 } else { | |
| 1283 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1284 } | |
| 1285 } | |
| 1286 | |
| 1287 // On 64 bit we will store integer like items to the stack as | |
| 1288 // 64 bits items (sparc abi) even though java would only store | |
| 1289 // 32bits for a parameter. On 32bit it will simply be 32 bits | |
| 1290 // So this routine will do 32->32 on 32bit and 32->64 on 64bit | |
| 1291 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1292 if (src.first()->is_stack()) { | |
| 1293 if (dst.first()->is_stack()) { | |
| 1294 // stack to stack | |
| 1295 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1296 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1297 } else { | |
| 1298 // stack to reg | |
| 1299 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1300 } | |
| 1301 } else if (dst.first()->is_stack()) { | |
| 1302 // reg to stack | |
| 1303 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1304 } else { | |
| 1305 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1306 } | |
| 1307 } | |
| 1308 | |
| 1309 | |
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1310 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { |
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1311 if (src.first()->is_stack()) { |
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1312 if (dst.first()->is_stack()) { |
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1313 // stack to stack |
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1314 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5); |
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1315 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); |
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1316 } else { |
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1317 // stack to reg |
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1318 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
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1319 } |
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1320 } else if (dst.first()->is_stack()) { |
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1321 // reg to stack |
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1322 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); |
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1323 } else { |
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1324 __ mov(src.first()->as_Register(), dst.first()->as_Register()); |
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1325 } |
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1326 } |
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1327 |
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1328 |
| 0 | 1329 // An oop arg. Must pass a handle not the oop itself |
| 1330 static void object_move(MacroAssembler* masm, | |
| 1331 OopMap* map, | |
| 1332 int oop_handle_offset, | |
| 1333 int framesize_in_slots, | |
| 1334 VMRegPair src, | |
| 1335 VMRegPair dst, | |
| 1336 bool is_receiver, | |
| 1337 int* receiver_offset) { | |
| 1338 | |
| 1339 // must pass a handle. First figure out the location we use as a handle | |
| 1340 | |
| 1341 if (src.first()->is_stack()) { | |
| 1342 // Oop is already on the stack | |
| 1343 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register(); | |
| 1344 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle); | |
| 1345 __ ld_ptr(rHandle, 0, L4); | |
| 1346 #ifdef _LP64 | |
| 1347 __ movr( Assembler::rc_z, L4, G0, rHandle ); | |
| 1348 #else | |
| 1349 __ tst( L4 ); | |
| 1350 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
| 1351 #endif | |
| 1352 if (dst.first()->is_stack()) { | |
| 1353 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1354 } | |
| 1355 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); | |
| 1356 if (is_receiver) { | |
| 1357 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; | |
| 1358 } | |
| 1359 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); | |
| 1360 } else { | |
| 1361 // Oop is in an input register pass we must flush it to the stack | |
| 1362 const Register rOop = src.first()->as_Register(); | |
| 1363 const Register rHandle = L5; | |
| 1364 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset; | |
| 1365 int offset = oop_slot*VMRegImpl::stack_slot_size; | |
| 1366 Label skip; | |
| 1367 __ st_ptr(rOop, SP, offset + STACK_BIAS); | |
| 1368 if (is_receiver) { | |
| 1369 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size; | |
| 1370 } | |
| 1371 map->set_oop(VMRegImpl::stack2reg(oop_slot)); | |
| 1372 __ add(SP, offset + STACK_BIAS, rHandle); | |
| 1373 #ifdef _LP64 | |
| 1374 __ movr( Assembler::rc_z, rOop, G0, rHandle ); | |
| 1375 #else | |
| 1376 __ tst( rOop ); | |
| 1377 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
| 1378 #endif | |
| 1379 | |
| 1380 if (dst.first()->is_stack()) { | |
| 1381 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1382 } else { | |
| 1383 __ mov(rHandle, dst.first()->as_Register()); | |
| 1384 } | |
| 1385 } | |
| 1386 } | |
| 1387 | |
| 1388 // A float arg may have to do float reg int reg conversion | |
| 1389 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1390 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); | |
| 1391 | |
| 1392 if (src.first()->is_stack()) { | |
| 1393 if (dst.first()->is_stack()) { | |
| 1394 // stack to stack the easiest of the bunch | |
| 1395 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1396 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1397 } else { | |
| 1398 // stack to reg | |
| 1399 if (dst.first()->is_Register()) { | |
| 1400 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1401 } else { | |
| 1402 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1403 } | |
| 1404 } | |
| 1405 } else if (dst.first()->is_stack()) { | |
| 1406 // reg to stack | |
| 1407 if (src.first()->is_Register()) { | |
| 1408 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1409 } else { | |
| 1410 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1411 } | |
| 1412 } else { | |
| 1413 // reg to reg | |
| 1414 if (src.first()->is_Register()) { | |
| 1415 if (dst.first()->is_Register()) { | |
| 1416 // gpr -> gpr | |
| 1417 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1418 } else { | |
| 1419 // gpr -> fpr | |
| 1420 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS); | |
| 1421 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1422 } | |
| 1423 } else if (dst.first()->is_Register()) { | |
| 1424 // fpr -> gpr | |
| 1425 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS); | |
| 1426 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register()); | |
| 1427 } else { | |
| 1428 // fpr -> fpr | |
| 1429 // In theory these overlap but the ordering is such that this is likely a nop | |
| 1430 if ( src.first() != dst.first()) { | |
| 1431 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
| 1432 } | |
| 1433 } | |
| 1434 } | |
| 1435 } | |
| 1436 | |
| 1437 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1438 VMRegPair src_lo(src.first()); | |
| 1439 VMRegPair src_hi(src.second()); | |
| 1440 VMRegPair dst_lo(dst.first()); | |
| 1441 VMRegPair dst_hi(dst.second()); | |
| 1442 simple_move32(masm, src_lo, dst_lo); | |
| 1443 simple_move32(masm, src_hi, dst_hi); | |
| 1444 } | |
| 1445 | |
| 1446 // A long move | |
| 1447 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1448 | |
| 1449 // Do the simple ones here else do two int moves | |
| 1450 if (src.is_single_phys_reg() ) { | |
| 1451 if (dst.is_single_phys_reg()) { | |
| 1452 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1453 } else { | |
| 1454 // split src into two separate registers | |
| 1455 // Remember hi means hi address or lsw on sparc | |
| 1456 // Move msw to lsw | |
| 1457 if (dst.second()->is_reg()) { | |
| 1458 // MSW -> MSW | |
| 1459 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register()); | |
| 1460 // Now LSW -> LSW | |
| 1461 // this will only move lo -> lo and ignore hi | |
| 1462 VMRegPair split(dst.second()); | |
| 1463 simple_move32(masm, src, split); | |
| 1464 } else { | |
| 1465 VMRegPair split(src.first(), L4->as_VMReg()); | |
| 1466 // MSW -> MSW (lo ie. first word) | |
| 1467 __ srax(src.first()->as_Register(), 32, L4); | |
| 1468 split_long_move(masm, split, dst); | |
| 1469 } | |
| 1470 } | |
| 1471 } else if (dst.is_single_phys_reg()) { | |
| 1472 if (src.is_adjacent_aligned_on_stack(2)) { | |
| 304 | 1473 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
| 0 | 1474 } else { |
| 1475 // dst is a single reg. | |
| 1476 // Remember lo is low address not msb for stack slots | |
| 1477 // and lo is the "real" register for registers | |
| 1478 // src is | |
| 1479 | |
| 1480 VMRegPair split; | |
| 1481 | |
| 1482 if (src.first()->is_reg()) { | |
| 1483 // src.lo (msw) is a reg, src.hi is stk/reg | |
| 1484 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg] | |
| 1485 split.set_pair(dst.first(), src.first()); | |
| 1486 } else { | |
| 1487 // msw is stack move to L5 | |
| 1488 // lsw is stack move to dst.lo (real reg) | |
| 1489 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5 | |
| 1490 split.set_pair(dst.first(), L5->as_VMReg()); | |
| 1491 } | |
| 1492 | |
| 1493 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg) | |
| 1494 // msw -> src.lo/L5, lsw -> dst.lo | |
| 1495 split_long_move(masm, src, split); | |
| 1496 | |
| 1497 // So dst now has the low order correct position the | |
| 1498 // msw half | |
| 1499 __ sllx(split.first()->as_Register(), 32, L5); | |
| 1500 | |
| 1501 const Register d = dst.first()->as_Register(); | |
| 1502 __ or3(L5, d, d); | |
| 1503 } | |
| 1504 } else { | |
| 1505 // For LP64 we can probably do better. | |
| 1506 split_long_move(masm, src, dst); | |
| 1507 } | |
| 1508 } | |
| 1509 | |
| 1510 // A double move | |
| 1511 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1512 | |
| 1513 // The painful thing here is that like long_move a VMRegPair might be | |
| 1514 // 1: a single physical register | |
| 1515 // 2: two physical registers (v8) | |
| 1516 // 3: a physical reg [lo] and a stack slot [hi] (v8) | |
| 1517 // 4: two stack slots | |
| 1518 | |
| 1519 // Since src is always a java calling convention we know that the src pair | |
| 1520 // is always either all registers or all stack (and aligned?) | |
| 1521 | |
| 1522 // in a register [lo] and a stack slot [hi] | |
| 1523 if (src.first()->is_stack()) { | |
| 1524 if (dst.first()->is_stack()) { | |
| 1525 // stack to stack the easiest of the bunch | |
| 1526 // ought to be a way to do this where if alignment is ok we use ldd/std when possible | |
| 1527 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
| 1528 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
| 1529 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1530 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1531 } else { | |
| 1532 // stack to reg | |
| 1533 if (dst.second()->is_stack()) { | |
| 1534 // stack -> reg, stack -> stack | |
| 1535 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
| 1536 if (dst.first()->is_Register()) { | |
| 1537 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1538 } else { | |
| 1539 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1540 } | |
| 1541 // This was missing. (very rare case) | |
| 1542 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1543 } else { | |
| 1544 // stack -> reg | |
| 1545 // Eventually optimize for alignment QQQ | |
| 1546 if (dst.first()->is_Register()) { | |
| 1547 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
| 1548 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register()); | |
| 1549 } else { | |
| 1550 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1551 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister()); | |
| 1552 } | |
| 1553 } | |
| 1554 } | |
| 1555 } else if (dst.first()->is_stack()) { | |
| 1556 // reg to stack | |
| 1557 if (src.first()->is_Register()) { | |
| 1558 // Eventually optimize for alignment QQQ | |
| 1559 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1560 if (src.second()->is_stack()) { | |
| 1561 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
| 1562 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1563 } else { | |
| 1564 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1565 } | |
| 1566 } else { | |
| 1567 // fpr to stack | |
| 1568 if (src.second()->is_stack()) { | |
| 1569 ShouldNotReachHere(); | |
| 1570 } else { | |
| 1571 // Is the stack aligned? | |
| 1572 if (reg2offset(dst.first()) & 0x7) { | |
| 1573 // No do as pairs | |
| 1574 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1575 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1576 } else { | |
| 1577 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
| 1578 } | |
| 1579 } | |
| 1580 } | |
| 1581 } else { | |
| 1582 // reg to reg | |
| 1583 if (src.first()->is_Register()) { | |
| 1584 if (dst.first()->is_Register()) { | |
| 1585 // gpr -> gpr | |
| 1586 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
| 1587 __ mov(src.second()->as_Register(), dst.second()->as_Register()); | |
| 1588 } else { | |
| 1589 // gpr -> fpr | |
| 1590 // ought to be able to do a single store | |
| 1591 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS); | |
| 1592 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS); | |
| 1593 // ought to be able to do a single load | |
| 1594 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
| 1595 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister()); | |
| 1596 } | |
| 1597 } else if (dst.first()->is_Register()) { | |
| 1598 // fpr -> gpr | |
| 1599 // ought to be able to do a single store | |
| 1600 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS); | |
| 1601 // ought to be able to do a single load | |
| 1602 // REMEMBER first() is low address not LSB | |
| 1603 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register()); | |
| 1604 if (dst.second()->is_Register()) { | |
| 1605 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register()); | |
| 1606 } else { | |
| 1607 __ ld(FP, -4 + STACK_BIAS, L4); | |
| 1608 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
| 1609 } | |
| 1610 } else { | |
| 1611 // fpr -> fpr | |
| 1612 // In theory these overlap but the ordering is such that this is likely a nop | |
| 1613 if ( src.first() != dst.first()) { | |
| 1614 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
| 1615 } | |
| 1616 } | |
| 1617 } | |
| 1618 } | |
| 1619 | |
| 1620 // Creates an inner frame if one hasn't already been created, and | |
| 1621 // saves a copy of the thread in L7_thread_cache | |
| 1622 static void create_inner_frame(MacroAssembler* masm, bool* already_created) { | |
| 1623 if (!*already_created) { | |
| 1624 __ save_frame(0); | |
| 1625 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below | |
| 1626 // Don't use save_thread because it smashes G2 and we merely want to save a | |
| 1627 // copy | |
| 1628 __ mov(G2_thread, L7_thread_cache); | |
| 1629 *already_created = true; | |
| 1630 } | |
| 1631 } | |
| 1632 | |
|
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1633 |
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1634 static void save_or_restore_arguments(MacroAssembler* masm, |
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1635 const int stack_slots, |
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1636 const int total_in_args, |
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1637 const int arg_save_area, |
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1638 OopMap* map, |
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1639 VMRegPair* in_regs, |
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1640 BasicType* in_sig_bt) { |
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1641 // if map is non-NULL then the code should store the values, |
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1642 // otherwise it should load them. |
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1643 if (map != NULL) { |
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1644 // Fill in the map |
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1645 for (int i = 0; i < total_in_args; i++) { |
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1646 if (in_sig_bt[i] == T_ARRAY) { |
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1647 if (in_regs[i].first()->is_stack()) { |
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1648 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); |
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1649 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); |
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1650 } else if (in_regs[i].first()->is_Register()) { |
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1651 map->set_oop(in_regs[i].first()); |
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1652 } else { |
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1653 ShouldNotReachHere(); |
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1654 } |
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1655 } |
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1656 } |
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1657 } |
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1658 |
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1659 // Save or restore double word values |
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1660 int handle_index = 0; |
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1661 for (int i = 0; i < total_in_args; i++) { |
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1662 int slot = handle_index + arg_save_area; |
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1663 int offset = slot * VMRegImpl::stack_slot_size; |
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1664 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) { |
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1665 const Register reg = in_regs[i].first()->as_Register(); |
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1666 if (reg->is_global()) { |
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1667 handle_index += 2; |
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1668 assert(handle_index <= stack_slots, "overflow"); |
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1669 if (map != NULL) { |
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1670 __ stx(reg, SP, offset + STACK_BIAS); |
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1671 } else { |
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1672 __ ldx(SP, offset + STACK_BIAS, reg); |
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1673 } |
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1674 } |
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1675 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) { |
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1676 handle_index += 2; |
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1677 assert(handle_index <= stack_slots, "overflow"); |
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1678 if (map != NULL) { |
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1679 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1680 } else { |
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1681 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1682 } |
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1683 } |
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1684 } |
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1685 // Save floats |
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1686 for (int i = 0; i < total_in_args; i++) { |
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1687 int slot = handle_index + arg_save_area; |
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1688 int offset = slot * VMRegImpl::stack_slot_size; |
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1689 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) { |
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1690 handle_index++; |
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1691 assert(handle_index <= stack_slots, "overflow"); |
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1692 if (map != NULL) { |
|
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1693 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
|
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1694 } else { |
|
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1695 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
|
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1696 } |
|
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1697 } |
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1698 } |
|
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|
1699 |
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1700 } |
|
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1701 |
|
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1702 |
|
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1703 // Check GC_locker::needs_gc and enter the runtime if it's true. This |
|
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1704 // keeps a new JNI critical region from starting until a GC has been |
|
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1705 // forced. Save down any oops in registers and describe them in an |
|
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1706 // OopMap. |
|
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1707 static void check_needs_gc_for_critical_native(MacroAssembler* masm, |
|
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1708 const int stack_slots, |
|
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1709 const int total_in_args, |
|
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|
1710 const int arg_save_area, |
|
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|
1711 OopMapSet* oop_maps, |
|
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1712 VMRegPair* in_regs, |
|
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1713 BasicType* in_sig_bt) { |
|
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1714 __ block_comment("check GC_locker::needs_gc"); |
|
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1715 Label cont; |
|
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1716 AddressLiteral sync_state(GC_locker::needs_gc_address()); |
|
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1717 __ load_bool_contents(sync_state, G3_scratch); |
|
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1718 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont); |
|
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1719 __ delayed()->nop(); |
|
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1720 |
|
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1721 // Save down any values that are live in registers and call into the |
|
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1722 // runtime to halt for a GC |
|
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1723 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
|
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1724 save_or_restore_arguments(masm, stack_slots, total_in_args, |
|
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1725 arg_save_area, map, in_regs, in_sig_bt); |
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1726 |
|
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1727 __ mov(G2_thread, L7_thread_cache); |
|
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|
1728 |
|
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|
1729 __ set_last_Java_frame(SP, noreg); |
|
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|
1730 |
|
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1731 __ block_comment("block_for_jni_critical"); |
|
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1732 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type); |
|
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|
1733 __ delayed()->mov(L7_thread_cache, O0); |
|
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|
1734 oop_maps->add_gc_map( __ offset(), map); |
|
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|
1735 |
|
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1736 __ restore_thread(L7_thread_cache); // restore G2_thread |
|
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|
1737 __ reset_last_Java_frame(); |
|
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|
1738 |
|
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|
1739 // Reload all the register arguments |
|
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|
1740 save_or_restore_arguments(masm, stack_slots, total_in_args, |
|
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|
1741 arg_save_area, NULL, in_regs, in_sig_bt); |
|
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|
1742 |
|
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1743 __ bind(cont); |
|
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|
1744 #ifdef ASSERT |
|
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|
1745 if (StressCriticalJNINatives) { |
|
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|
1746 // Stress register saving |
|
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1747 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
|
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|
1748 save_or_restore_arguments(masm, stack_slots, total_in_args, |
|
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|
1749 arg_save_area, map, in_regs, in_sig_bt); |
|
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|
1750 // Destroy argument registers |
|
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|
1751 for (int i = 0; i < total_in_args; i++) { |
|
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|
1752 if (in_regs[i].first()->is_Register()) { |
|
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|
1753 const Register reg = in_regs[i].first()->as_Register(); |
|
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|
1754 if (reg->is_global()) { |
|
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|
1755 __ mov(G0, reg); |
|
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|
1756 } |
|
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|
1757 } else if (in_regs[i].first()->is_FloatRegister()) { |
|
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|
1758 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister()); |
|
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|
1759 } |
|
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|
1760 } |
|
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|
1761 |
|
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|
1762 save_or_restore_arguments(masm, stack_slots, total_in_args, |
|
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|
1763 arg_save_area, NULL, in_regs, in_sig_bt); |
|
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|
1764 } |
|
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|
1765 #endif |
|
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|
1766 } |
|
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|
1767 |
|
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|
1768 // Unpack an array argument into a pointer to the body and the length |
|
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|
1769 // if the array is non-null, otherwise pass 0 for both. |
|
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|
1770 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { |
|
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|
1771 // Pass the length, ptr pair |
|
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|
1772 Label is_null, done; |
|
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|
1773 if (reg.first()->is_stack()) { |
|
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|
1774 VMRegPair tmp = reg64_to_VMRegPair(L2); |
|
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|
1775 // Load the arg up from the stack |
|
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|
1776 move_ptr(masm, reg, tmp); |
|
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|
1777 reg = tmp; |
|
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|
1778 } |
|
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|
1779 __ cmp(reg.first()->as_Register(), G0); |
|
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|
1780 __ brx(Assembler::equal, false, Assembler::pt, is_null); |
|
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|
1781 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4); |
|
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|
1782 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg); |
|
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|
1783 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4); |
|
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|
1784 move32_64(masm, reg64_to_VMRegPair(L4), length_arg); |
|
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|
1785 __ ba_short(done); |
|
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|
1786 __ bind(is_null); |
|
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|
1787 // Pass zeros |
|
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|
1788 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg); |
|
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|
1789 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); |
|
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|
1790 __ bind(done); |
|
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|
1791 } |
|
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|
1792 |
|
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|
1793 static void verify_oop_args(MacroAssembler* masm, |
|
6790
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|
1794 methodHandle method, |
|
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1795 const BasicType* sig_bt, |
|
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1796 const VMRegPair* regs) { |
|
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|
1797 Register temp_reg = G5_method; // not part of any compiled calling seq |
|
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|
1798 if (VerifyOops) { |
|
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|
1799 for (int i = 0; i < method->size_of_parameters(); i++) { |
|
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1800 if (sig_bt[i] == T_OBJECT || |
|
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|
1801 sig_bt[i] == T_ARRAY) { |
|
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|
1802 VMReg r = regs[i].first(); |
|
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|
1803 assert(r->is_valid(), "bad oop arg"); |
|
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1804 if (r->is_stack()) { |
|
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|
1805 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
|
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|
1806 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg); |
|
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|
1807 __ ld_ptr(SP, ld_off, temp_reg); |
|
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|
1808 __ verify_oop(temp_reg); |
|
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|
1809 } else { |
|
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|
1810 __ verify_oop(r->as_Register()); |
|
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|
1811 } |
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1812 } |
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1813 } |
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1814 } |
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1815 } |
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1816 |
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1817 static void gen_special_dispatch(MacroAssembler* masm, |
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1818 methodHandle method, |
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1819 const BasicType* sig_bt, |
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1820 const VMRegPair* regs) { |
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1821 verify_oop_args(masm, method, sig_bt, regs); |
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1822 vmIntrinsics::ID iid = method->intrinsic_id(); |
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1823 |
| 10684 | 1824 #ifdef GRAAL |
| 1825 if (iid == vmIntrinsics::_CompilerToVMImpl_executeCompiledMethod) { | |
| 1826 // We are called from compiled code here. The three object arguments | |
| 1827 // are already in the correct registers (j_rarg0, jrarg1, jrarg2). The | |
| 1828 // fourth argument (j_rarg3) is a pointer to the HotSpotInstalledCode object. | |
| 1829 | |
| 1830 // Load the nmethod pointer from the HotSpotInstalledCode object | |
| 1831 // __ movq(j_rarg3, Address(j_rarg3, sizeof(oopDesc))); | |
| 1832 | |
| 1833 // Check whether the nmethod was invalidated | |
| 1834 // __ testq(j_rarg3, j_rarg3); | |
| 1835 // Label invalid_nmethod; | |
| 1836 // __ jcc(Assembler::zero, invalid_nmethod); | |
| 1837 | |
| 1838 // Perform a tail call to the verified entry point of the nmethod. | |
| 1839 // __ jmp(Address(j_rarg3, nmethod::verified_entry_point_offset())); | |
| 1840 | |
| 1841 // __ bind(invalid_nmethod); | |
| 1842 | |
| 1843 // __ jump(RuntimeAddress(StubRoutines::throw_InvalidInstalledCodeException_entry())); | |
| 1844 __ stop("_CompilerToVMImpl_executeCompiledMethod not implemented"); | |
| 1845 return; | |
| 1846 } | |
| 1847 #endif | |
| 1848 | |
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1849 // Now write the args into the outgoing interpreter space |
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1850 bool has_receiver = false; |
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1851 Register receiver_reg = noreg; |
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1852 int member_arg_pos = -1; |
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1853 Register member_reg = noreg; |
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1854 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); |
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1855 if (ref_kind != 0) { |
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1856 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument |
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1857 member_reg = G5_method; // known to be free at this point |
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1858 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); |
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1859 } else if (iid == vmIntrinsics::_invokeBasic) { |
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1860 has_receiver = true; |
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1861 } else { |
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1862 fatal(err_msg_res("unexpected intrinsic id %d", iid)); |
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1863 } |
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1864 |
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1865 if (member_reg != noreg) { |
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1866 // Load the member_arg into register, if necessary. |
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1867 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); |
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1868 VMReg r = regs[member_arg_pos].first(); |
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1869 if (r->is_stack()) { |
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1870 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1871 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
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1872 __ ld_ptr(SP, ld_off, member_reg); |
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1873 } else { |
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1874 // no data motion is needed |
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1875 member_reg = r->as_Register(); |
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1876 } |
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1877 } |
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1878 |
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1879 if (has_receiver) { |
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1880 // Make sure the receiver is loaded into a register. |
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1881 assert(method->size_of_parameters() > 0, "oob"); |
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1882 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); |
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1883 VMReg r = regs[0].first(); |
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1884 assert(r->is_valid(), "bad receiver arg"); |
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1885 if (r->is_stack()) { |
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1886 // Porting note: This assumes that compiled calling conventions always |
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1887 // pass the receiver oop in a register. If this is not true on some |
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1888 // platform, pick a temp and load the receiver from stack. |
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1889 fatal("receiver always in a register"); |
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1890 receiver_reg = G3_scratch; // known to be free at this point |
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1891 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1892 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
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1893 __ ld_ptr(SP, ld_off, receiver_reg); |
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1894 } else { |
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1895 // no data motion is needed |
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1896 receiver_reg = r->as_Register(); |
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1897 } |
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1898 } |
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1899 |
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1900 // Figure out which address we are really jumping to: |
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1901 MethodHandles::generate_method_handle_dispatch(masm, iid, |
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1902 receiver_reg, member_reg, /*for_compiler_entry:*/ true); |
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1903 } |
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1904 |
| 0 | 1905 // --------------------------------------------------------------------------- |
| 1906 // Generate a native wrapper for a given method. The method takes arguments | |
| 1907 // in the Java compiled code convention, marshals them to the native | |
| 1908 // convention (handlizes oops, etc), transitions to native, makes the call, | |
| 1909 // returns to java state (possibly blocking), unhandlizes any result and | |
| 1910 // returns. | |
|
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1911 // |
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1912 // Critical native functions are a shorthand for the use of |
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1913 // GetPrimtiveArrayCritical and disallow the use of any other JNI |
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1914 // functions. The wrapper is expected to unpack the arguments before |
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1915 // passing them to the callee and perform checks before and after the |
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1916 // native call to ensure that they GC_locker |
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1917 // lock_critical/unlock_critical semantics are followed. Some other |
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1918 // parts of JNI setup are skipped like the tear down of the JNI handle |
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1919 // block and the check for pending exceptions it's impossible for them |
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1920 // to be thrown. |
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1921 // |
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1922 // They are roughly structured like this: |
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1923 // if (GC_locker::needs_gc()) |
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1924 // SharedRuntime::block_for_jni_critical(); |
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1925 // tranistion to thread_in_native |
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1926 // unpack arrray arguments and call native entry point |
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1927 // check for safepoint in progress |
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1928 // check if any thread suspend flags are set |
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1929 // call into JVM and possible unlock the JNI critical |
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1930 // if a GC was suppressed while in the critical native. |
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1931 // transition back to thread_in_Java |
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1932 // return to caller |
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1933 // |
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1934 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, |
| 0 | 1935 methodHandle method, |
|
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1936 int compile_id, |
|
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1937 BasicType* in_sig_bt, |
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1938 VMRegPair* in_regs, |
| 0 | 1939 BasicType ret_type) { |
|
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1940 if (method->is_method_handle_intrinsic()) { |
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1941 vmIntrinsics::ID iid = method->intrinsic_id(); |
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1942 intptr_t start = (intptr_t)__ pc(); |
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1943 int vep_offset = ((intptr_t)__ pc()) - start; |
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1944 gen_special_dispatch(masm, |
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1945 method, |
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1946 in_sig_bt, |
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1947 in_regs); |
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1948 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period |
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1949 __ flush(); |
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1950 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually |
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1951 return nmethod::new_native_nmethod(method, |
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1952 compile_id, |
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1953 masm->code(), |
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1954 vep_offset, |
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1955 frame_complete, |
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1956 stack_slots / VMRegImpl::slots_per_word, |
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1957 in_ByteSize(-1), |
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1958 in_ByteSize(-1), |
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1959 (OopMapSet*)NULL); |
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1960 } |
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1961 bool is_critical_native = true; |
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1962 address native_func = method->critical_native_function(); |
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1963 if (native_func == NULL) { |
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1964 native_func = method->native_function(); |
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1965 is_critical_native = false; |
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1966 } |
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1967 assert(native_func != NULL, "must have function"); |
| 0 | 1968 |
| 1969 // Native nmethod wrappers never take possesion of the oop arguments. | |
| 1970 // So the caller will gc the arguments. The only thing we need an | |
| 1971 // oopMap for is if the call is static | |
| 1972 // | |
| 1973 // An OopMap for lock (and class if static), and one for the VM call itself | |
| 1974 OopMapSet *oop_maps = new OopMapSet(); | |
| 1975 intptr_t start = (intptr_t)__ pc(); | |
| 1976 | |
| 1977 // First thing make an ic check to see if we should even be here | |
| 1978 { | |
| 1979 Label L; | |
| 1980 const Register temp_reg = G3_scratch; | |
| 727 | 1981 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
| 0 | 1982 __ verify_oop(O0); |
|
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1983 __ load_klass(O0, temp_reg); |
| 3839 | 1984 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
| 0 | 1985 |
| 727 | 1986 __ jump_to(ic_miss, temp_reg); |
| 0 | 1987 __ delayed()->nop(); |
| 1988 __ align(CodeEntryAlignment); | |
| 1989 __ bind(L); | |
| 1990 } | |
| 1991 | |
| 1992 int vep_offset = ((intptr_t)__ pc()) - start; | |
| 1993 | |
| 1994 #ifdef COMPILER1 | |
| 1995 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) { | |
| 1996 // Object.hashCode can pull the hashCode from the header word | |
| 1997 // instead of doing a full VM transition once it's been computed. | |
| 1998 // Since hashCode is usually polymorphic at call sites we can't do | |
| 1999 // this optimization at the call site without a lot of work. | |
| 2000 Label slowCase; | |
| 2001 Register receiver = O0; | |
| 2002 Register result = O0; | |
| 2003 Register header = G3_scratch; | |
| 2004 Register hash = G3_scratch; // overwrite header value with hash value | |
| 2005 Register mask = G1; // to get hash field from header | |
| 2006 | |
| 2007 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked. | |
| 2008 // We depend on hash_mask being at most 32 bits and avoid the use of | |
| 2009 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit | |
| 2010 // vm: see markOop.hpp. | |
| 2011 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header); | |
| 2012 __ sethi(markOopDesc::hash_mask, mask); | |
| 2013 __ btst(markOopDesc::unlocked_value, header); | |
| 2014 __ br(Assembler::zero, false, Assembler::pn, slowCase); | |
| 2015 if (UseBiasedLocking) { | |
| 2016 // Check if biased and fall through to runtime if so | |
| 2017 __ delayed()->nop(); | |
| 2018 __ btst(markOopDesc::biased_lock_bit_in_place, header); | |
| 2019 __ br(Assembler::notZero, false, Assembler::pn, slowCase); | |
| 2020 } | |
| 2021 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask); | |
| 2022 | |
| 2023 // Check for a valid (non-zero) hash code and get its value. | |
| 2024 #ifdef _LP64 | |
| 2025 __ srlx(header, markOopDesc::hash_shift, hash); | |
| 2026 #else | |
| 2027 __ srl(header, markOopDesc::hash_shift, hash); | |
| 2028 #endif | |
| 2029 __ andcc(hash, mask, hash); | |
| 2030 __ br(Assembler::equal, false, Assembler::pn, slowCase); | |
| 2031 __ delayed()->nop(); | |
| 2032 | |
| 2033 // leaf return. | |
| 2034 __ retl(); | |
| 2035 __ delayed()->mov(hash, result); | |
| 2036 __ bind(slowCase); | |
| 2037 } | |
| 2038 #endif // COMPILER1 | |
| 2039 | |
| 2040 | |
| 2041 // We have received a description of where all the java arg are located | |
| 2042 // on entry to the wrapper. We need to convert these args to where | |
| 2043 // the jni function will expect them. To figure out where they go | |
| 2044 // we convert the java signature to a C signature by inserting | |
| 2045 // the hidden arguments as arg[0] and possibly arg[1] (static method) | |
| 2046 | |
|
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2047 const int total_in_args = method->size_of_parameters(); |
|
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2048 int total_c_args = total_in_args; |
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2049 int total_save_slots = 6 * VMRegImpl::slots_per_word; |
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2050 if (!is_critical_native) { |
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2051 total_c_args += 1; |
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2052 if (method->is_static()) { |
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2053 total_c_args++; |
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2054 } |
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2055 } else { |
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2056 for (int i = 0; i < total_in_args; i++) { |
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2057 if (in_sig_bt[i] == T_ARRAY) { |
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2058 // These have to be saved and restored across the safepoint |
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2059 total_c_args++; |
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2060 } |
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2061 } |
| 0 | 2062 } |
| 2063 | |
| 2064 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); | |
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2065 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); |
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2066 BasicType* in_elem_bt = NULL; |
| 0 | 2067 |
| 2068 int argc = 0; | |
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2069 if (!is_critical_native) { |
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2070 out_sig_bt[argc++] = T_ADDRESS; |
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2071 if (method->is_static()) { |
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2072 out_sig_bt[argc++] = T_OBJECT; |
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2073 } |
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2074 |
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2075 for (int i = 0; i < total_in_args ; i++ ) { |
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2076 out_sig_bt[argc++] = in_sig_bt[i]; |
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2077 } |
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2078 } else { |
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2079 Thread* THREAD = Thread::current(); |
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2080 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); |
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2081 SignatureStream ss(method->signature()); |
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2082 for (int i = 0; i < total_in_args ; i++ ) { |
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2083 if (in_sig_bt[i] == T_ARRAY) { |
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2084 // Arrays are passed as int, elem* pair |
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2085 out_sig_bt[argc++] = T_INT; |
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2086 out_sig_bt[argc++] = T_ADDRESS; |
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2087 Symbol* atype = ss.as_symbol(CHECK_NULL); |
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2088 const char* at = atype->as_C_string(); |
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2089 if (strlen(at) == 2) { |
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2090 assert(at[0] == '[', "must be"); |
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2091 switch (at[1]) { |
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2092 case 'B': in_elem_bt[i] = T_BYTE; break; |
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2093 case 'C': in_elem_bt[i] = T_CHAR; break; |
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2094 case 'D': in_elem_bt[i] = T_DOUBLE; break; |
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2095 case 'F': in_elem_bt[i] = T_FLOAT; break; |
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2096 case 'I': in_elem_bt[i] = T_INT; break; |
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2097 case 'J': in_elem_bt[i] = T_LONG; break; |
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2098 case 'S': in_elem_bt[i] = T_SHORT; break; |
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2099 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; |
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2100 default: ShouldNotReachHere(); |
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2101 } |
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2102 } |
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2103 } else { |
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2104 out_sig_bt[argc++] = in_sig_bt[i]; |
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2105 in_elem_bt[i] = T_VOID; |
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2106 } |
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2107 if (in_sig_bt[i] != T_VOID) { |
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2108 assert(in_sig_bt[i] == ss.type(), "must match"); |
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2109 ss.next(); |
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2110 } |
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2111 } |
| 0 | 2112 } |
| 2113 | |
| 2114 // Now figure out where the args must be stored and how much stack space | |
| 2115 // they require (neglecting out_preserve_stack_slots but space for storing | |
| 2116 // the 1st six register arguments). It's weird see int_stk_helper. | |
| 2117 // | |
| 2118 int out_arg_slots; | |
| 2119 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); | |
| 2120 | |
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2121 if (is_critical_native) { |
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2122 // Critical natives may have to call out so they need a save area |
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2123 // for register arguments. |
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2124 int double_slots = 0; |
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2125 int single_slots = 0; |
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2126 for ( int i = 0; i < total_in_args; i++) { |
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2127 if (in_regs[i].first()->is_Register()) { |
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2128 const Register reg = in_regs[i].first()->as_Register(); |
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2129 switch (in_sig_bt[i]) { |
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2130 case T_ARRAY: |
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2131 case T_BOOLEAN: |
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2132 case T_BYTE: |
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2133 case T_SHORT: |
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2134 case T_CHAR: |
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2135 case T_INT: assert(reg->is_in(), "don't need to save these"); break; |
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2136 case T_LONG: if (reg->is_global()) double_slots++; break; |
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2137 default: ShouldNotReachHere(); |
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2138 } |
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2139 } else if (in_regs[i].first()->is_FloatRegister()) { |
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2140 switch (in_sig_bt[i]) { |
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2141 case T_FLOAT: single_slots++; break; |
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2142 case T_DOUBLE: double_slots++; break; |
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2143 default: ShouldNotReachHere(); |
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2144 } |
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2145 } |
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2146 } |
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2147 total_save_slots = double_slots * 2 + single_slots; |
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2148 } |
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2149 |
| 0 | 2150 // Compute framesize for the wrapper. We need to handlize all oops in |
| 2151 // registers. We must create space for them here that is disjoint from | |
| 2152 // the windowed save area because we have no control over when we might | |
| 2153 // flush the window again and overwrite values that gc has since modified. | |
| 2154 // (The live window race) | |
| 2155 // | |
| 2156 // We always just allocate 6 word for storing down these object. This allow | |
| 2157 // us to simply record the base and use the Ireg number to decide which | |
| 2158 // slot to use. (Note that the reg number is the inbound number not the | |
| 2159 // outbound number). | |
| 2160 // We must shuffle args to match the native convention, and include var-args space. | |
| 2161 | |
| 2162 // Calculate the total number of stack slots we will need. | |
| 2163 | |
| 2164 // First count the abi requirement plus all of the outgoing args | |
| 2165 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; | |
| 2166 | |
| 2167 // Now the space for the inbound oop handle area | |
| 2168 | |
|
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2169 int oop_handle_offset = round_to(stack_slots, 2); |
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2170 stack_slots += total_save_slots; |
| 0 | 2171 |
| 2172 // Now any space we need for handlizing a klass if static method | |
| 2173 | |
| 2174 int klass_slot_offset = 0; | |
| 2175 int klass_offset = -1; | |
| 2176 int lock_slot_offset = 0; | |
| 2177 bool is_static = false; | |
| 2178 | |
| 2179 if (method->is_static()) { | |
| 2180 klass_slot_offset = stack_slots; | |
| 2181 stack_slots += VMRegImpl::slots_per_word; | |
| 2182 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; | |
| 2183 is_static = true; | |
| 2184 } | |
| 2185 | |
| 2186 // Plus a lock if needed | |
| 2187 | |
| 2188 if (method->is_synchronized()) { | |
| 2189 lock_slot_offset = stack_slots; | |
| 2190 stack_slots += VMRegImpl::slots_per_word; | |
| 2191 } | |
| 2192 | |
| 2193 // Now a place to save return value or as a temporary for any gpr -> fpr moves | |
| 2194 stack_slots += 2; | |
| 2195 | |
| 2196 // Ok The space we have allocated will look like: | |
| 2197 // | |
| 2198 // | |
| 2199 // FP-> | | | |
| 2200 // |---------------------| | |
| 2201 // | 2 slots for moves | | |
| 2202 // |---------------------| | |
| 2203 // | lock box (if sync) | | |
| 2204 // |---------------------| <- lock_slot_offset | |
| 2205 // | klass (if static) | | |
| 2206 // |---------------------| <- klass_slot_offset | |
| 2207 // | oopHandle area | | |
| 2208 // |---------------------| <- oop_handle_offset | |
| 2209 // | outbound memory | | |
| 2210 // | based arguments | | |
| 2211 // | | | |
| 2212 // |---------------------| | |
| 2213 // | vararg area | | |
| 2214 // |---------------------| | |
| 2215 // | | | |
| 2216 // SP-> | out_preserved_slots | | |
| 2217 // | |
| 2218 // | |
| 2219 | |
| 2220 | |
| 2221 // Now compute actual number of stack words we need rounding to make | |
| 2222 // stack properly aligned. | |
| 2223 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word); | |
| 2224 | |
| 2225 int stack_size = stack_slots * VMRegImpl::stack_slot_size; | |
| 2226 | |
| 2227 // Generate stack overflow check before creating frame | |
| 2228 __ generate_stack_overflow_check(stack_size); | |
| 2229 | |
| 2230 // Generate a new frame for the wrapper. | |
| 2231 __ save(SP, -stack_size, SP); | |
| 2232 | |
| 2233 int frame_complete = ((intptr_t)__ pc()) - start; | |
| 2234 | |
| 2235 __ verify_thread(); | |
| 2236 | |
|
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2237 if (is_critical_native) { |
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2238 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args, |
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2239 oop_handle_offset, oop_maps, in_regs, in_sig_bt); |
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2240 } |
| 0 | 2241 |
| 2242 // | |
| 2243 // We immediately shuffle the arguments so that any vm call we have to | |
| 2244 // make from here on out (sync slow path, jvmti, etc.) we will have | |
| 2245 // captured the oops from our caller and have a valid oopMap for | |
| 2246 // them. | |
| 2247 | |
| 2248 // ----------------- | |
| 2249 // The Grand Shuffle | |
| 2250 // | |
| 2251 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* | |
| 2252 // (derived from JavaThread* which is in L7_thread_cache) and, if static, | |
| 2253 // the class mirror instead of a receiver. This pretty much guarantees that | |
| 2254 // register layout will not match. We ignore these extra arguments during | |
| 2255 // the shuffle. The shuffle is described by the two calling convention | |
| 2256 // vectors we have in our possession. We simply walk the java vector to | |
| 2257 // get the source locations and the c vector to get the destinations. | |
| 2258 // Because we have a new window and the argument registers are completely | |
| 2259 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about | |
| 2260 // here. | |
| 2261 | |
| 2262 // This is a trick. We double the stack slots so we can claim | |
| 2263 // the oops in the caller's frame. Since we are sure to have | |
| 2264 // more args than the caller doubling is enough to make | |
| 2265 // sure we can capture all the incoming oop args from the | |
| 2266 // caller. | |
| 2267 // | |
| 2268 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); | |
| 2269 // Record sp-based slot for receiver on stack for non-static methods | |
| 2270 int receiver_offset = -1; | |
| 2271 | |
| 2272 // We move the arguments backward because the floating point registers | |
| 2273 // destination will always be to a register with a greater or equal register | |
| 2274 // number or the stack. | |
| 2275 | |
| 2276 #ifdef ASSERT | |
| 2277 bool reg_destroyed[RegisterImpl::number_of_registers]; | |
| 2278 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; | |
| 2279 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { | |
| 2280 reg_destroyed[r] = false; | |
| 2281 } | |
| 2282 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { | |
| 2283 freg_destroyed[f] = false; | |
| 2284 } | |
| 2285 | |
| 2286 #endif /* ASSERT */ | |
| 2287 | |
|
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2288 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) { |
| 0 | 2289 |
| 2290 #ifdef ASSERT | |
| 2291 if (in_regs[i].first()->is_Register()) { | |
| 2292 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!"); | |
| 2293 } else if (in_regs[i].first()->is_FloatRegister()) { | |
| 2294 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!"); | |
| 2295 } | |
| 2296 if (out_regs[c_arg].first()->is_Register()) { | |
| 2297 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; | |
| 2298 } else if (out_regs[c_arg].first()->is_FloatRegister()) { | |
| 2299 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true; | |
| 2300 } | |
| 2301 #endif /* ASSERT */ | |
| 2302 | |
| 2303 switch (in_sig_bt[i]) { | |
| 2304 case T_ARRAY: | |
|
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2305 if (is_critical_native) { |
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2306 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]); |
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2307 c_arg--; |
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2308 break; |
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2309 } |
| 0 | 2310 case T_OBJECT: |
|
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2311 assert(!is_critical_native, "no oop arguments"); |
| 0 | 2312 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], |
| 2313 ((i == 0) && (!is_static)), | |
| 2314 &receiver_offset); | |
| 2315 break; | |
| 2316 case T_VOID: | |
| 2317 break; | |
| 2318 | |
| 2319 case T_FLOAT: | |
| 2320 float_move(masm, in_regs[i], out_regs[c_arg]); | |
|
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2321 break; |
| 0 | 2322 |
| 2323 case T_DOUBLE: | |
| 2324 assert( i + 1 < total_in_args && | |
| 2325 in_sig_bt[i + 1] == T_VOID && | |
| 2326 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); | |
| 2327 double_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2328 break; | |
| 2329 | |
| 2330 case T_LONG : | |
| 2331 long_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2332 break; | |
| 2333 | |
| 2334 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); | |
| 2335 | |
| 2336 default: | |
| 2337 move32_64(masm, in_regs[i], out_regs[c_arg]); | |
| 2338 } | |
| 2339 } | |
| 2340 | |
| 2341 // Pre-load a static method's oop into O1. Used both by locking code and | |
| 2342 // the normal JNI call code. | |
|
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2343 if (method->is_static() && !is_critical_native) { |
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2344 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1); |
| 0 | 2345 |
| 2346 // Now handlize the static class mirror in O1. It's known not-null. | |
| 2347 __ st_ptr(O1, SP, klass_offset + STACK_BIAS); | |
| 2348 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); | |
| 2349 __ add(SP, klass_offset + STACK_BIAS, O1); | |
| 2350 } | |
| 2351 | |
| 2352 | |
| 2353 const Register L6_handle = L6; | |
| 2354 | |
| 2355 if (method->is_synchronized()) { | |
|
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2356 assert(!is_critical_native, "unhandled"); |
| 0 | 2357 __ mov(O1, L6_handle); |
| 2358 } | |
| 2359 | |
| 2360 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs | |
| 2361 // except O6/O7. So if we must call out we must push a new frame. We immediately | |
| 2362 // push a new frame and flush the windows. | |
| 2363 #ifdef _LP64 | |
| 2364 intptr_t thepc = (intptr_t) __ pc(); | |
| 2365 { | |
| 2366 address here = __ pc(); | |
| 2367 // Call the next instruction | |
| 2368 __ call(here + 8, relocInfo::none); | |
| 2369 __ delayed()->nop(); | |
| 2370 } | |
| 2371 #else | |
| 2372 intptr_t thepc = __ load_pc_address(O7, 0); | |
| 2373 #endif /* _LP64 */ | |
| 2374 | |
| 2375 // We use the same pc/oopMap repeatedly when we call out | |
| 2376 oop_maps->add_gc_map(thepc - start, map); | |
| 2377 | |
| 2378 // O7 now has the pc loaded that we will use when we finally call to native. | |
| 2379 | |
| 2380 // Save thread in L7; it crosses a bunch of VM calls below | |
| 2381 // Don't use save_thread because it smashes G2 and we merely | |
| 2382 // want to save a copy | |
| 2383 __ mov(G2_thread, L7_thread_cache); | |
| 2384 | |
| 2385 | |
| 2386 // If we create an inner frame once is plenty | |
| 2387 // when we create it we must also save G2_thread | |
| 2388 bool inner_frame_created = false; | |
| 2389 | |
| 2390 // dtrace method entry support | |
| 2391 { | |
| 2392 SkipIfEqual skip_if( | |
| 2393 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
| 2394 // create inner frame | |
| 2395 __ save_frame(0); | |
| 2396 __ mov(G2_thread, L7_thread_cache); | |
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2397 __ set_metadata_constant(method(), O1); |
| 0 | 2398 __ call_VM_leaf(L7_thread_cache, |
| 2399 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), | |
| 2400 G2_thread, O1); | |
| 2401 __ restore(); | |
| 2402 } | |
| 2403 | |
|
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2404 // RedefineClasses() tracing support for obsolete method entry |
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2405 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { |
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2406 // create inner frame |
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2407 __ save_frame(0); |
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2408 __ mov(G2_thread, L7_thread_cache); |
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2409 __ set_metadata_constant(method(), O1); |
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2410 __ call_VM_leaf(L7_thread_cache, |
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2411 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), |
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2412 G2_thread, O1); |
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2413 __ restore(); |
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2414 } |
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2415 |
| 0 | 2416 // We are in the jni frame unless saved_frame is true in which case |
| 2417 // we are in one frame deeper (the "inner" frame). If we are in the | |
| 2418 // "inner" frames the args are in the Iregs and if the jni frame then | |
| 2419 // they are in the Oregs. | |
| 2420 // If we ever need to go to the VM (for locking, jvmti) then | |
| 2421 // we will always be in the "inner" frame. | |
| 2422 | |
| 2423 // Lock a synchronized method | |
| 2424 int lock_offset = -1; // Set if locked | |
| 2425 if (method->is_synchronized()) { | |
| 2426 Register Roop = O1; | |
| 2427 const Register L3_box = L3; | |
| 2428 | |
| 2429 create_inner_frame(masm, &inner_frame_created); | |
| 2430 | |
| 2431 __ ld_ptr(I1, 0, O1); | |
| 2432 Label done; | |
| 2433 | |
| 2434 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size); | |
| 2435 __ add(FP, lock_offset+STACK_BIAS, L3_box); | |
| 2436 #ifdef ASSERT | |
| 2437 if (UseBiasedLocking) { | |
| 2438 // making the box point to itself will make it clear it went unused | |
| 2439 // but also be obviously invalid | |
| 2440 __ st_ptr(L3_box, L3_box, 0); | |
| 2441 } | |
| 2442 #endif // ASSERT | |
| 2443 // | |
| 2444 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch | |
| 2445 // | |
| 2446 __ compiler_lock_object(Roop, L1, L3_box, L2); | |
| 2447 __ br(Assembler::equal, false, Assembler::pt, done); | |
| 2448 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box); | |
| 2449 | |
| 2450 | |
| 2451 // None of the above fast optimizations worked so we have to get into the | |
| 2452 // slow case of monitor enter. Inline a special case of call_VM that | |
| 2453 // disallows any pending_exception. | |
| 2454 __ mov(Roop, O0); // Need oop in O0 | |
| 2455 __ mov(L3_box, O1); | |
| 2456 | |
| 2457 // Record last_Java_sp, in case the VM code releases the JVM lock. | |
| 2458 | |
| 2459 __ set_last_Java_frame(FP, I7); | |
| 2460 | |
| 2461 // do the call | |
| 2462 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); | |
| 2463 __ delayed()->mov(L7_thread_cache, O2); | |
| 2464 | |
| 2465 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2466 __ reset_last_Java_frame(); | |
| 2467 | |
| 2468 #ifdef ASSERT | |
| 2469 { Label L; | |
| 2470 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
| 3839 | 2471 __ br_null_short(O0, Assembler::pt, L); |
| 0 | 2472 __ stop("no pending exception allowed on exit from IR::monitorenter"); |
| 2473 __ bind(L); | |
| 2474 } | |
| 2475 #endif | |
| 2476 __ bind(done); | |
| 2477 } | |
| 2478 | |
| 2479 | |
| 2480 // Finally just about ready to make the JNI call | |
| 2481 | |
| 10997 | 2482 __ flushw(); |
| 0 | 2483 if (inner_frame_created) { |
| 2484 __ restore(); | |
| 2485 } else { | |
| 2486 // Store only what we need from this frame | |
| 2487 // QQQ I think that non-v9 (like we care) we don't need these saves | |
| 2488 // either as the flush traps and the current window goes too. | |
| 2489 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
| 2490 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
| 2491 } | |
| 2492 | |
| 2493 // get JNIEnv* which is first argument to native | |
|
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2494 if (!is_critical_native) { |
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2495 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0); |
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2496 } |
| 0 | 2497 |
| 2498 // Use that pc we placed in O7 a while back as the current frame anchor | |
| 2499 __ set_last_Java_frame(SP, O7); | |
| 2500 | |
|
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2501 // We flushed the windows ages ago now mark them as flushed before transitioning. |
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2502 __ set(JavaFrameAnchor::flushed, G3_scratch); |
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2503 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); |
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2504 |
| 0 | 2505 // Transition from _thread_in_Java to _thread_in_native. |
| 2506 __ set(_thread_in_native, G3_scratch); | |
| 2507 | |
| 2508 #ifdef _LP64 | |
|
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2509 AddressLiteral dest(native_func); |
| 0 | 2510 __ relocate(relocInfo::runtime_call_type); |
| 727 | 2511 __ jumpl_to(dest, O7, O7); |
| 0 | 2512 #else |
|
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2513 __ call(native_func, relocInfo::runtime_call_type); |
| 0 | 2514 #endif |
|
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2515 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
| 0 | 2516 |
| 2517 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2518 | |
| 2519 // Unpack native results. For int-types, we do any needed sign-extension | |
| 2520 // and move things into I0. The return value there will survive any VM | |
| 2521 // calls for blocking or unlocking. An FP or OOP result (handle) is done | |
| 2522 // specially in the slow-path code. | |
| 2523 switch (ret_type) { | |
| 2524 case T_VOID: break; // Nothing to do! | |
| 2525 case T_FLOAT: break; // Got it where we want it (unless slow-path) | |
| 2526 case T_DOUBLE: break; // Got it where we want it (unless slow-path) | |
| 2527 // In 64 bits build result is in O0, in O0, O1 in 32bit build | |
| 2528 case T_LONG: | |
| 2529 #ifndef _LP64 | |
| 2530 __ mov(O1, I1); | |
| 2531 #endif | |
| 2532 // Fall thru | |
| 2533 case T_OBJECT: // Really a handle | |
| 2534 case T_ARRAY: | |
| 2535 case T_INT: | |
| 2536 __ mov(O0, I0); | |
| 2537 break; | |
| 2538 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false | |
| 2539 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break; | |
| 2540 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value! | |
| 2541 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break; | |
| 2542 break; // Cannot de-handlize until after reclaiming jvm_lock | |
| 2543 default: | |
| 2544 ShouldNotReachHere(); | |
| 2545 } | |
| 2546 | |
|
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2547 Label after_transition; |
| 0 | 2548 // must we block? |
| 2549 | |
| 2550 // Block, if necessary, before resuming in _thread_in_Java state. | |
| 2551 // In order for GC to work, don't clear the last_Java_sp until after blocking. | |
| 2552 { Label no_block; | |
| 727 | 2553 AddressLiteral sync_state(SafepointSynchronize::address_of_state()); |
| 0 | 2554 |
| 2555 // Switch thread to "native transition" state before reading the synchronization state. | |
| 2556 // This additional state is necessary because reading and testing the synchronization | |
| 2557 // state is not atomic w.r.t. GC, as this scenario demonstrates: | |
| 2558 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. | |
| 2559 // VM thread changes sync state to synchronizing and suspends threads for GC. | |
| 2560 // Thread A is resumed to finish this native method, but doesn't block here since it | |
| 2561 // didn't see any synchronization is progress, and escapes. | |
| 2562 __ set(_thread_in_native_trans, G3_scratch); | |
| 727 | 2563 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
| 0 | 2564 if(os::is_MP()) { |
| 2565 if (UseMembar) { | |
| 2566 // Force this write out before the read below | |
| 2567 __ membar(Assembler::StoreLoad); | |
| 2568 } else { | |
| 2569 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 2570 // We use the current thread pointer to calculate a thread specific | |
| 2571 // offset to write to within the page. This minimizes bus traffic | |
| 2572 // due to cache line collision. | |
| 2573 __ serialize_memory(G2_thread, G1_scratch, G3_scratch); | |
| 2574 } | |
| 2575 } | |
| 2576 __ load_contents(sync_state, G3_scratch); | |
| 2577 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized); | |
| 2578 | |
| 2579 Label L; | |
| 727 | 2580 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset()); |
| 0 | 2581 __ br(Assembler::notEqual, false, Assembler::pn, L); |
| 727 | 2582 __ delayed()->ld(suspend_state, G3_scratch); |
| 3839 | 2583 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block); |
| 0 | 2584 __ bind(L); |
| 2585 | |
| 2586 // Block. Save any potential method result value before the operation and | |
| 2587 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this | |
| 2588 // lets us share the oopMap we used when we went native rather the create | |
| 2589 // a distinct one for this pc | |
| 2590 // | |
| 2591 save_native_result(masm, ret_type, stack_slots); | |
|
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2592 if (!is_critical_native) { |
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2593 __ call_VM_leaf(L7_thread_cache, |
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2594 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), |
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2595 G2_thread); |
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2596 } else { |
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2597 __ call_VM_leaf(L7_thread_cache, |
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2598 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), |
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2599 G2_thread); |
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2600 } |
| 0 | 2601 |
| 2602 // Restore any method result value | |
| 2603 restore_native_result(masm, ret_type, stack_slots); | |
|
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2604 |
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2605 if (is_critical_native) { |
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2606 // The call above performed the transition to thread_in_Java so |
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2607 // skip the transition logic below. |
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2608 __ ba(after_transition); |
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2609 __ delayed()->nop(); |
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|
2610 } |
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2611 |
| 0 | 2612 __ bind(no_block); |
| 2613 } | |
| 2614 | |
| 2615 // thread state is thread_in_native_trans. Any safepoint blocking has already | |
| 2616 // happened so we can now change state to _thread_in_Java. | |
| 2617 __ set(_thread_in_Java, G3_scratch); | |
| 727 | 2618 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
|
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2619 __ bind(after_transition); |
| 0 | 2620 |
| 2621 Label no_reguard; | |
| 727 | 2622 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch); |
| 3839 | 2623 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard); |
| 0 | 2624 |
| 2625 save_native_result(masm, ret_type, stack_slots); | |
| 2626 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); | |
| 2627 __ delayed()->nop(); | |
| 2628 | |
| 2629 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2630 restore_native_result(masm, ret_type, stack_slots); | |
| 2631 | |
| 2632 __ bind(no_reguard); | |
| 2633 | |
| 2634 // Handle possible exception (will unlock if necessary) | |
| 2635 | |
| 2636 // native result if any is live in freg or I0 (and I1 if long and 32bit vm) | |
| 2637 | |
| 2638 // Unlock | |
| 2639 if (method->is_synchronized()) { | |
| 2640 Label done; | |
| 2641 Register I2_ex_oop = I2; | |
| 2642 const Register L3_box = L3; | |
| 2643 // Get locked oop from the handle we passed to jni | |
| 2644 __ ld_ptr(L6_handle, 0, L4); | |
| 2645 __ add(SP, lock_offset+STACK_BIAS, L3_box); | |
| 2646 // Must save pending exception around the slow-path VM call. Since it's a | |
| 2647 // leaf call, the pending exception (if any) can be kept in a register. | |
| 2648 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop); | |
| 2649 // Now unlock | |
| 2650 // (Roop, Rmark, Rbox, Rscratch) | |
| 2651 __ compiler_unlock_object(L4, L1, L3_box, L2); | |
| 2652 __ br(Assembler::equal, false, Assembler::pt, done); | |
| 2653 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box); | |
| 2654 | |
| 2655 // save and restore any potential method result value around the unlocking | |
| 2656 // operation. Will save in I0 (or stack for FP returns). | |
| 2657 save_native_result(masm, ret_type, stack_slots); | |
| 2658 | |
| 2659 // Must clear pending-exception before re-entering the VM. Since this is | |
| 2660 // a leaf call, pending-exception-oop can be safely kept in a register. | |
| 2661 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
| 2662 | |
| 2663 // slow case of monitor enter. Inline a special case of call_VM that | |
| 2664 // disallows any pending_exception. | |
| 2665 __ mov(L3_box, O1); | |
| 2666 | |
| 2667 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type); | |
| 2668 __ delayed()->mov(L4, O0); // Need oop in O0 | |
| 2669 | |
| 2670 __ restore_thread(L7_thread_cache); // restore G2_thread | |
| 2671 | |
| 2672 #ifdef ASSERT | |
| 2673 { Label L; | |
| 2674 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
| 3839 | 2675 __ br_null_short(O0, Assembler::pt, L); |
| 0 | 2676 __ stop("no pending exception allowed on exit from IR::monitorexit"); |
| 2677 __ bind(L); | |
| 2678 } | |
| 2679 #endif | |
| 2680 restore_native_result(masm, ret_type, stack_slots); | |
| 2681 // check_forward_pending_exception jump to forward_exception if any pending | |
| 2682 // exception is set. The forward_exception routine expects to see the | |
| 2683 // exception in pending_exception and not in a register. Kind of clumsy, | |
| 2684 // since all folks who branch to forward_exception must have tested | |
| 2685 // pending_exception first and hence have it in a register already. | |
| 2686 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
| 2687 __ bind(done); | |
| 2688 } | |
| 2689 | |
| 2690 // Tell dtrace about this method exit | |
| 2691 { | |
| 2692 SkipIfEqual skip_if( | |
| 2693 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
| 2694 save_native_result(masm, ret_type, stack_slots); | |
|
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2695 __ set_metadata_constant(method(), O1); |
| 0 | 2696 __ call_VM_leaf(L7_thread_cache, |
| 2697 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), | |
| 2698 G2_thread, O1); | |
| 2699 restore_native_result(masm, ret_type, stack_slots); | |
| 2700 } | |
| 2701 | |
| 2702 // Clear "last Java frame" SP and PC. | |
| 2703 __ verify_thread(); // G2_thread must be correct | |
| 2704 __ reset_last_Java_frame(); | |
| 2705 | |
| 2706 // Unpack oop result | |
| 2707 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { | |
| 2708 Label L; | |
| 2709 __ addcc(G0, I0, G0); | |
| 2710 __ brx(Assembler::notZero, true, Assembler::pt, L); | |
| 2711 __ delayed()->ld_ptr(I0, 0, I0); | |
| 2712 __ mov(G0, I0); | |
| 2713 __ bind(L); | |
| 2714 __ verify_oop(I0); | |
| 2715 } | |
| 2716 | |
|
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2717 if (!is_critical_native) { |
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|
2718 // reset handle block |
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|
2719 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5); |
|
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|
2720 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes()); |
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|
2721 |
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2722 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch); |
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|
2723 check_forward_pending_exception(masm, G3_scratch); |
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|
2724 } |
| 0 | 2725 |
| 2726 | |
| 2727 // Return | |
| 2728 | |
| 2729 #ifndef _LP64 | |
| 2730 if (ret_type == T_LONG) { | |
| 2731 | |
| 2732 // Must leave proper result in O0,O1 and G1 (c2/tiered only) | |
| 2733 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
| 2734 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
| 2735 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
| 2736 } | |
| 2737 #endif | |
| 2738 | |
| 2739 __ ret(); | |
| 2740 __ delayed()->restore(); | |
| 2741 | |
| 2742 __ flush(); | |
| 2743 | |
| 2744 nmethod *nm = nmethod::new_native_nmethod(method, | |
|
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2745 compile_id, |
| 0 | 2746 masm->code(), |
| 2747 vep_offset, | |
| 2748 frame_complete, | |
| 2749 stack_slots / VMRegImpl::slots_per_word, | |
| 2750 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), | |
| 2751 in_ByteSize(lock_offset), | |
| 2752 oop_maps); | |
|
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|
2753 |
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2754 if (is_critical_native) { |
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|
2755 nm->set_lazy_critical_native(true); |
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|
2756 } |
| 0 | 2757 return nm; |
| 2758 | |
| 2759 } | |
| 2760 | |
|
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2761 #ifdef HAVE_DTRACE_H |
|
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2762 // --------------------------------------------------------------------------- |
|
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2763 // Generate a dtrace nmethod for a given signature. The method takes arguments |
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2764 // in the Java compiled code convention, marshals them to the native |
|
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2765 // abi and then leaves nops at the position you would expect to call a native |
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2766 // function. When the probe is enabled the nops are replaced with a trap |
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2767 // instruction that dtrace inserts and the trace will cause a notification |
|
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2768 // to dtrace. |
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2769 // |
|
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2770 // The probes are only able to take primitive types and java/lang/String as |
|
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2771 // arguments. No other java types are allowed. Strings are converted to utf8 |
|
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2772 // strings so that from dtrace point of view java strings are converted to C |
|
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2773 // strings. There is an arbitrary fixed limit on the total space that a method |
|
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2774 // can use for converting the strings. (256 chars per string in the signature). |
|
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2775 // So any java string larger then this is truncated. |
|
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2776 |
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|
2777 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; |
|
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2778 static bool offsets_initialized = false; |
|
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2779 |
|
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|
2780 nmethod *SharedRuntime::generate_dtrace_nmethod( |
|
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2781 MacroAssembler *masm, methodHandle method) { |
|
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2782 |
|
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2783 |
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2784 // generate_dtrace_nmethod is guarded by a mutex so we are sure to |
|
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2785 // be single threaded in this method. |
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2786 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); |
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2787 |
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2788 // Fill in the signature array, for the calling-convention call. |
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2789 int total_args_passed = method->size_of_parameters(); |
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2790 |
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2791 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); |
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2792 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); |
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2793 |
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2794 // The signature we are going to use for the trap that dtrace will see |
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2795 // java/lang/String is converted. We drop "this" and any other object |
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2796 // is converted to NULL. (A one-slot java/lang/Long object reference |
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2797 // is converted to a two-slot long, which is why we double the allocation). |
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2798 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); |
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2799 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); |
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2800 |
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2801 int i=0; |
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2802 int total_strings = 0; |
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2803 int first_arg_to_pass = 0; |
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2804 int total_c_args = 0; |
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2805 |
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2806 // Skip the receiver as dtrace doesn't want to see it |
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2807 if( !method->is_static() ) { |
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2808 in_sig_bt[i++] = T_OBJECT; |
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2809 first_arg_to_pass = 1; |
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2810 } |
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2811 |
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2812 SignatureStream ss(method->signature()); |
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2813 for ( ; !ss.at_return_type(); ss.next()) { |
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2814 BasicType bt = ss.type(); |
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2815 in_sig_bt[i++] = bt; // Collect remaining bits of signature |
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2816 out_sig_bt[total_c_args++] = bt; |
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2817 if( bt == T_OBJECT) { |
|
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2818 Symbol* s = ss.as_symbol_or_null(); |
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2819 if (s == vmSymbols::java_lang_String()) { |
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2820 total_strings++; |
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2821 out_sig_bt[total_c_args-1] = T_ADDRESS; |
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2822 } else if (s == vmSymbols::java_lang_Boolean() || |
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2823 s == vmSymbols::java_lang_Byte()) { |
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2824 out_sig_bt[total_c_args-1] = T_BYTE; |
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2825 } else if (s == vmSymbols::java_lang_Character() || |
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2826 s == vmSymbols::java_lang_Short()) { |
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2827 out_sig_bt[total_c_args-1] = T_SHORT; |
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2828 } else if (s == vmSymbols::java_lang_Integer() || |
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2829 s == vmSymbols::java_lang_Float()) { |
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2830 out_sig_bt[total_c_args-1] = T_INT; |
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2831 } else if (s == vmSymbols::java_lang_Long() || |
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2832 s == vmSymbols::java_lang_Double()) { |
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2833 out_sig_bt[total_c_args-1] = T_LONG; |
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2834 out_sig_bt[total_c_args++] = T_VOID; |
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2835 } |
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2836 } else if ( bt == T_LONG || bt == T_DOUBLE ) { |
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2837 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots |
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2838 // We convert double to long |
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2839 out_sig_bt[total_c_args-1] = T_LONG; |
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2840 out_sig_bt[total_c_args++] = T_VOID; |
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2841 } else if ( bt == T_FLOAT) { |
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2842 // We convert float to int |
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2843 out_sig_bt[total_c_args-1] = T_INT; |
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2844 } |
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2845 } |
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2846 |
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2847 assert(i==total_args_passed, "validly parsed signature"); |
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2848 |
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2849 // Now get the compiled-Java layout as input arguments |
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2850 int comp_args_on_stack; |
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2851 comp_args_on_stack = SharedRuntime::java_calling_convention( |
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2852 in_sig_bt, in_regs, total_args_passed, false); |
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2853 |
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2854 // We have received a description of where all the java arg are located |
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2855 // on entry to the wrapper. We need to convert these args to where |
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2856 // the a native (non-jni) function would expect them. To figure out |
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2857 // where they go we convert the java signature to a C signature and remove |
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2858 // T_VOID for any long/double we might have received. |
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2859 |
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2860 |
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2861 // Now figure out where the args must be stored and how much stack space |
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2862 // they require (neglecting out_preserve_stack_slots but space for storing |
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2863 // the 1st six register arguments). It's weird see int_stk_helper. |
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2864 // |
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2865 int out_arg_slots; |
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2866 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); |
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2867 |
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2868 // Calculate the total number of stack slots we will need. |
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2869 |
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2870 // First count the abi requirement plus all of the outgoing args |
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2871 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; |
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2872 |
|
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2873 // Plus a temp for possible converion of float/double/long register args |
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2874 |
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2875 int conversion_temp = stack_slots; |
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2876 stack_slots += 2; |
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2877 |
|
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2878 |
|
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2879 // Now space for the string(s) we must convert |
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2880 |
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2881 int string_locs = stack_slots; |
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2882 stack_slots += total_strings * |
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2883 (max_dtrace_string_size / VMRegImpl::stack_slot_size); |
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2884 |
|
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2885 // Ok The space we have allocated will look like: |
|
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2886 // |
|
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2887 // |
|
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2888 // FP-> | | |
|
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2889 // |---------------------| |
|
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2890 // | string[n] | |
|
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2891 // |---------------------| <- string_locs[n] |
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2892 // | string[n-1] | |
|
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2893 // |---------------------| <- string_locs[n-1] |
|
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2894 // | ... | |
|
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2895 // | ... | |
|
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2896 // |---------------------| <- string_locs[1] |
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2897 // | string[0] | |
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2898 // |---------------------| <- string_locs[0] |
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2899 // | temp | |
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2900 // |---------------------| <- conversion_temp |
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2901 // | outbound memory | |
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2902 // | based arguments | |
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2903 // | | |
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2904 // |---------------------| |
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2905 // | | |
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2906 // SP-> | out_preserved_slots | |
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2907 // |
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2908 // |
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2909 |
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2910 // Now compute actual number of stack words we need rounding to make |
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2911 // stack properly aligned. |
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2912 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); |
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2913 |
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2914 int stack_size = stack_slots * VMRegImpl::stack_slot_size; |
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2915 |
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2916 intptr_t start = (intptr_t)__ pc(); |
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2917 |
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2918 // First thing make an ic check to see if we should even be here |
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2919 |
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2920 { |
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2921 Label L; |
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2922 const Register temp_reg = G3_scratch; |
| 727 | 2923 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
|
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2924 __ verify_oop(O0); |
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2925 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg); |
| 3839 | 2926 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
|
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2927 |
| 727 | 2928 __ jump_to(ic_miss, temp_reg); |
|
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2929 __ delayed()->nop(); |
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2930 __ align(CodeEntryAlignment); |
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2931 __ bind(L); |
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2932 } |
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2933 |
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2934 int vep_offset = ((intptr_t)__ pc()) - start; |
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2935 |
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2936 |
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2937 // The instruction at the verified entry point must be 5 bytes or longer |
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2938 // because it can be patched on the fly by make_non_entrant. The stack bang |
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2939 // instruction fits that requirement. |
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2940 |
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2941 // Generate stack overflow check before creating frame |
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2942 __ generate_stack_overflow_check(stack_size); |
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2943 |
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2944 assert(((intptr_t)__ pc() - start - vep_offset) >= 5, |
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2945 "valid size for make_non_entrant"); |
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2946 |
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2947 // Generate a new frame for the wrapper. |
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2948 __ save(SP, -stack_size, SP); |
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2949 |
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2950 // Frame is now completed as far a size and linkage. |
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2951 |
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2952 int frame_complete = ((intptr_t)__ pc()) - start; |
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2953 |
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2954 #ifdef ASSERT |
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2955 bool reg_destroyed[RegisterImpl::number_of_registers]; |
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2956 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; |
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2957 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { |
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2958 reg_destroyed[r] = false; |
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2959 } |
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2960 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { |
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2961 freg_destroyed[f] = false; |
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2962 } |
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2963 |
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2964 #endif /* ASSERT */ |
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2965 |
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2966 VMRegPair zero; |
|
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2967 const Register g0 = G0; // without this we get a compiler warning (why??) |
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2968 zero.set2(g0->as_VMReg()); |
|
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2969 |
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2970 int c_arg, j_arg; |
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2971 |
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2972 Register conversion_off = noreg; |
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2973 |
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2974 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
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2975 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
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2976 |
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2977 VMRegPair src = in_regs[j_arg]; |
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2978 VMRegPair dst = out_regs[c_arg]; |
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2979 |
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2980 #ifdef ASSERT |
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2981 if (src.first()->is_Register()) { |
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2982 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!"); |
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2983 } else if (src.first()->is_FloatRegister()) { |
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2984 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding( |
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2985 FloatRegisterImpl::S)], "ack!"); |
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2986 } |
|
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2987 if (dst.first()->is_Register()) { |
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2988 reg_destroyed[dst.first()->as_Register()->encoding()] = true; |
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2989 } else if (dst.first()->is_FloatRegister()) { |
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2990 freg_destroyed[dst.first()->as_FloatRegister()->encoding( |
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2991 FloatRegisterImpl::S)] = true; |
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2992 } |
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2993 #endif /* ASSERT */ |
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2994 |
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2995 switch (in_sig_bt[j_arg]) { |
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2996 case T_ARRAY: |
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2997 case T_OBJECT: |
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2998 { |
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2999 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT || |
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3000 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { |
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3001 // need to unbox a one-slot value |
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3002 Register in_reg = L0; |
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3003 Register tmp = L2; |
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3004 if ( src.first()->is_reg() ) { |
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3005 in_reg = src.first()->as_Register(); |
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3006 } else { |
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3007 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS), |
|
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3008 "must be"); |
|
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3009 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg); |
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3010 } |
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3011 // If the final destination is an acceptable register |
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3012 if ( dst.first()->is_reg() ) { |
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|
3013 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) { |
|
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|
3014 tmp = dst.first()->as_Register(); |
|
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kamg
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|
3015 } |
|
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kamg
parents:
113
diff
changeset
|
3016 } |
|
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3017 |
|
018d5b58dd4f
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kamg
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113
diff
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|
3018 Label skipUnbox; |
|
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|
3019 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) { |
|
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diff
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|
3020 __ mov(G0, tmp->successor()); |
|
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kamg
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113
diff
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|
3021 } |
|
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kamg
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113
diff
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|
3022 __ br_null(in_reg, true, Assembler::pn, skipUnbox); |
|
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|
3023 __ delayed()->mov(G0, tmp); |
|
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kamg
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113
diff
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|
3024 |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
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116
diff
changeset
|
3025 BasicType bt = out_sig_bt[c_arg]; |
|
437d03ea40b1
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kvn
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116
diff
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|
3026 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); |
|
437d03ea40b1
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|
3027 switch (bt) { |
|
116
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|
3028 case T_BYTE: |
|
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kamg
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113
diff
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|
3029 __ ldub(in_reg, box_offset, tmp); break; |
|
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kamg
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113
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|
3030 case T_SHORT: |
|
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kamg
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diff
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|
3031 __ lduh(in_reg, box_offset, tmp); break; |
|
018d5b58dd4f
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kamg
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|
3032 case T_INT: |
|
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kamg
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diff
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|
3033 __ ld(in_reg, box_offset, tmp); break; |
|
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kamg
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113
diff
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|
3034 case T_LONG: |
|
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kamg
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113
diff
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|
3035 __ ld_long(in_reg, box_offset, tmp); break; |
|
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kamg
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113
diff
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|
3036 default: ShouldNotReachHere(); |
|
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kamg
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113
diff
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|
3037 } |
|
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3038 |
|
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113
diff
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|
3039 __ bind(skipUnbox); |
|
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kamg
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113
diff
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|
3040 // If tmp wasn't final destination copy to final destination |
|
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kamg
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113
diff
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|
3041 if (tmp == L2) { |
|
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kamg
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113
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|
3042 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2); |
|
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|
3043 if (out_sig_bt[c_arg] == T_LONG) { |
|
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kamg
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113
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|
3044 long_move(masm, tmp_as_VM, dst); |
|
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113
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|
3045 } else { |
|
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kamg
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|
3046 move32_64(masm, tmp_as_VM, out_regs[c_arg]); |
|
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kamg
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113
diff
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|
3047 } |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3048 } |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3049 if (out_sig_bt[c_arg] == T_LONG) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3050 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3051 ++c_arg; // move over the T_VOID to keep the loop indices in sync |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3052 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3053 } else if (out_sig_bt[c_arg] == T_ADDRESS) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3054 Register s = |
|
018d5b58dd4f
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kamg
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113
diff
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|
3055 src.first()->is_reg() ? src.first()->as_Register() : L2; |
|
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kamg
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113
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|
3056 Register d = |
|
018d5b58dd4f
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kamg
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113
diff
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|
3057 dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3058 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3059 // We store the oop now so that the conversion pass can reach |
|
018d5b58dd4f
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kamg
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113
diff
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|
3060 // while in the inner frame. This will be the only store if |
|
018d5b58dd4f
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kamg
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113
diff
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|
3061 // the oop is NULL. |
|
018d5b58dd4f
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kamg
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113
diff
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|
3062 if (s != L2) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3063 // src is register |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3064 if (d != L2) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3065 // dst is register |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3066 __ mov(s, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3067 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3068 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3069 STACK_BIAS), "must be"); |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3070 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3071 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3072 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3073 // src not a register |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3074 assert(Assembler::is_simm13(reg2offset(src.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3075 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3076 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3077 if (d == L2) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3078 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3079 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3080 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3081 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3082 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3083 } else if (out_sig_bt[c_arg] != T_VOID) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3084 // Convert the arg to NULL |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3085 if (dst.first()->is_reg()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3086 __ mov(G0, dst.first()->as_Register()); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3087 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3088 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3089 STACK_BIAS), "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3090 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3091 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3092 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3093 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3094 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3095 case T_VOID: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3096 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3097 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3098 case T_FLOAT: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3099 if (src.first()->is_stack()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3100 // Stack to stack/reg is simple |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3101 move32_64(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3102 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3103 if (dst.first()->is_reg()) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3104 // freg -> reg |
|
018d5b58dd4f
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kamg
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113
diff
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|
3105 int off = |
|
018d5b58dd4f
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kamg
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113
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changeset
|
3106 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
|
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kamg
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|
3107 Register d = dst.first()->as_Register(); |
|
018d5b58dd4f
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kamg
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113
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|
3108 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3109 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
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kamg
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113
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|
3110 SP, off); |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3111 __ ld(SP, off, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3112 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3113 if (conversion_off == noreg) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3114 __ set(off, L6); |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3115 conversion_off = L6; |
|
018d5b58dd4f
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kamg
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113
diff
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|
3116 } |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3117 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3118 SP, conversion_off); |
|
018d5b58dd4f
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113
diff
changeset
|
3119 __ ld(SP, conversion_off , d); |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3120 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3121 } else { |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3122 // freg -> mem |
|
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113
diff
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|
3123 int off = STACK_BIAS + reg2offset(dst.first()); |
|
018d5b58dd4f
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kamg
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diff
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|
3124 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
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diff
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|
3125 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
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kamg
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diff
changeset
|
3126 SP, off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3127 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3128 if (conversion_off == noreg) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3129 __ set(off, L6); |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3130 conversion_off = L6; |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3131 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3132 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3133 SP, conversion_off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3134 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3135 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3136 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3137 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3138 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3139 case T_DOUBLE: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3140 assert( j_arg + 1 < total_args_passed && |
|
018d5b58dd4f
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kamg
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113
diff
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|
3141 in_sig_bt[j_arg + 1] == T_VOID && |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3142 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3143 if (src.first()->is_stack()) { |
|
018d5b58dd4f
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kamg
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113
diff
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|
3144 // Stack to stack/reg is simple |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3145 long_move(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3146 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3147 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3148 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3149 // Destination could be an odd reg on 32bit in which case |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3150 // we can't load direct to the destination. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3151 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3152 if (!d->is_even() && wordSize == 4) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3153 d = L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3154 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3155 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3156 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3157 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3158 SP, off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3159 __ ld_long(SP, off, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3160 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3161 if (conversion_off == noreg) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3162 __ set(off, L6); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3163 conversion_off = L6; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3164 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3165 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3166 SP, conversion_off); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3167 __ ld_long(SP, conversion_off, d); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3168 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3169 if (d == L2) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3170 long_move(masm, reg64_to_VMRegPair(L2), dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3171 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3172 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3173 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3174 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3175 case T_LONG : |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3176 // 32bit can't do a split move of something like g1 -> O0, O1 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3177 // so use a memory temp |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3178 if (src.is_single_phys_reg() && wordSize == 4) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3179 Register tmp = L2; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3180 if (dst.first()->is_reg() && |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3181 (wordSize == 8 || dst.first()->as_Register()->is_even())) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3182 tmp = dst.first()->as_Register(); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3183 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3184 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3185 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3186 if (Assembler::is_simm13(off)) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3187 __ stx(src.first()->as_Register(), SP, off); |
|
018d5b58dd4f
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kamg
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113
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|
3188 __ ld_long(SP, off, tmp); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3189 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3190 if (conversion_off == noreg) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3191 __ set(off, L6); |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3192 conversion_off = L6; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3193 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3194 __ stx(src.first()->as_Register(), SP, conversion_off); |
|
018d5b58dd4f
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kamg
parents:
113
diff
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|
3195 __ ld_long(SP, conversion_off, tmp); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3196 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3197 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3198 if (tmp == L2) { |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3199 long_move(masm, reg64_to_VMRegPair(L2), dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3200 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3201 } else { |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3202 long_move(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3203 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3204 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3205 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3206 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3207 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3208 default: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3209 move32_64(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3210 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3211 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3212 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3213 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3214 // If we have any strings we must store any register based arg to the stack |
|
018d5b58dd4f
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|
3215 // This includes any still live xmm registers too. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3216 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3217 if (total_strings > 0 ) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3218 |
|
018d5b58dd4f
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kamg
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113
diff
changeset
|
3219 // protect all the arg registers |
|
018d5b58dd4f
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kamg
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113
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|
3220 __ save_frame(0); |
|
018d5b58dd4f
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kamg
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113
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|
3221 __ mov(G2_thread, L7_thread_cache); |
|
018d5b58dd4f
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kamg
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113
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|
3222 const Register L2_string_off = L2; |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3223 |
|
018d5b58dd4f
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kamg
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113
diff
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|
3224 // Get first string offset |
|
018d5b58dd4f
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kamg
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113
diff
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|
3225 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off); |
|
018d5b58dd4f
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kamg
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113
diff
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|
3226 |
|
018d5b58dd4f
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kamg
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113
diff
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|
3227 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) { |
|
018d5b58dd4f
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|
3228 if (out_sig_bt[c_arg] == T_ADDRESS) { |
|
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3229 |
|
018d5b58dd4f
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kamg
parents:
113
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changeset
|
3230 VMRegPair dst = out_regs[c_arg]; |
|
018d5b58dd4f
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|
3231 const Register d = dst.first()->is_reg() ? |
|
018d5b58dd4f
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|
3232 dst.first()->as_Register()->after_save() : noreg; |
|
018d5b58dd4f
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kamg
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113
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|
3233 |
|
018d5b58dd4f
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|
3234 // It's a string the oop and it was already copied to the out arg |
|
018d5b58dd4f
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kamg
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113
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|
3235 // position |
|
018d5b58dd4f
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kamg
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|
3236 if (d != noreg) { |
|
018d5b58dd4f
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|
3237 __ mov(d, O0); |
|
018d5b58dd4f
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kamg
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113
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|
3238 } else { |
|
018d5b58dd4f
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|
3239 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
|
018d5b58dd4f
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|
3240 "must be"); |
|
018d5b58dd4f
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113
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|
3241 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0); |
|
018d5b58dd4f
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|
3242 } |
|
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3243 Label skip; |
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3244 |
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3245 __ br_null(O0, false, Assembler::pn, skip); |
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3246 __ delayed()->add(FP, L2_string_off, O1); |
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3247 |
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3248 if (d != noreg) { |
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3249 __ mov(O1, d); |
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3250 } else { |
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3251 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
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3252 "must be"); |
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3253 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS); |
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3254 } |
|
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3255 |
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3256 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf), |
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3257 relocInfo::runtime_call_type); |
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3258 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off); |
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3259 |
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3260 __ bind(skip); |
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3261 |
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3262 } |
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3263 |
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3264 } |
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3265 __ mov(L7_thread_cache, G2_thread); |
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3266 __ restore(); |
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3267 |
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3268 } |
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3269 |
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3270 |
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3271 // Ok now we are done. Need to place the nop that dtrace wants in order to |
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3272 // patch in the trap |
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3273 |
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3274 int patch_offset = ((intptr_t)__ pc()) - start; |
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3275 |
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3276 __ nop(); |
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3277 |
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3278 |
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3279 // Return |
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3280 |
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3281 __ ret(); |
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3282 __ delayed()->restore(); |
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3283 |
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3284 __ flush(); |
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3285 |
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3286 nmethod *nm = nmethod::new_dtrace_nmethod( |
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3287 method, masm->code(), vep_offset, patch_offset, frame_complete, |
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3288 stack_slots / VMRegImpl::slots_per_word); |
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3289 return nm; |
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3290 |
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3291 } |
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3292 |
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3293 #endif // HAVE_DTRACE_H |
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3294 |
| 0 | 3295 // this function returns the adjust size (in number of words) to a c2i adapter |
| 3296 // activation for use during deoptimization | |
| 3297 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { | |
| 3298 assert(callee_locals >= callee_parameters, | |
| 3299 "test and remove; got more parms than locals"); | |
| 3300 if (callee_locals < callee_parameters) | |
| 3301 return 0; // No adjustment for negative locals | |
| 1506 | 3302 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; |
| 0 | 3303 return round_to(diff, WordsPerLong); |
| 3304 } | |
| 3305 | |
| 3306 // "Top of Stack" slots that may be unused by the calling convention but must | |
| 3307 // otherwise be preserved. | |
| 3308 // On Intel these are not necessary and the value can be zero. | |
| 3309 // On Sparc this describes the words reserved for storing a register window | |
| 3310 // when an interrupt occurs. | |
| 3311 uint SharedRuntime::out_preserve_stack_slots() { | |
| 3312 return frame::register_save_words * VMRegImpl::slots_per_word; | |
| 3313 } | |
| 3314 | |
| 3315 static void gen_new_frame(MacroAssembler* masm, bool deopt) { | |
| 3316 // | |
| 3317 // Common out the new frame generation for deopt and uncommon trap | |
| 3318 // | |
| 3319 Register G3pcs = G3_scratch; // Array of new pcs (input) | |
| 3320 Register Oreturn0 = O0; | |
| 3321 Register Oreturn1 = O1; | |
| 3322 Register O2UnrollBlock = O2; | |
| 3323 Register O3array = O3; // Array of frame sizes (input) | |
| 3324 Register O4array_size = O4; // number of frames (input) | |
| 3325 Register O7frame_size = O7; // number of frames (input) | |
| 3326 | |
| 3327 __ ld_ptr(O3array, 0, O7frame_size); | |
| 3328 __ sub(G0, O7frame_size, O7frame_size); | |
| 3329 __ save(SP, O7frame_size, SP); | |
| 3330 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc | |
| 3331 | |
| 3332 #ifdef ASSERT | |
| 3333 // make sure that the frames are aligned properly | |
| 3334 #ifndef _LP64 | |
| 3335 __ btst(wordSize*2-1, SP); | |
| 5923 | 3336 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc); |
| 0 | 3337 #endif |
| 3338 #endif | |
| 3339 | |
| 3340 // Deopt needs to pass some extra live values from frame to frame | |
| 3341 | |
| 3342 if (deopt) { | |
| 3343 __ mov(Oreturn0->after_save(), Oreturn0); | |
| 3344 __ mov(Oreturn1->after_save(), Oreturn1); | |
| 3345 } | |
| 3346 | |
| 3347 __ mov(O4array_size->after_save(), O4array_size); | |
| 3348 __ sub(O4array_size, 1, O4array_size); | |
| 3349 __ mov(O3array->after_save(), O3array); | |
| 3350 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock); | |
| 3351 __ add(G3pcs, wordSize, G3pcs); // point to next pc value | |
| 3352 | |
| 3353 #ifdef ASSERT | |
| 3354 // trash registers to show a clear pattern in backtraces | |
| 3355 __ set(0xDEAD0000, I0); | |
| 3356 __ add(I0, 2, I1); | |
| 3357 __ add(I0, 4, I2); | |
| 3358 __ add(I0, 6, I3); | |
| 3359 __ add(I0, 8, I4); | |
| 3360 // Don't touch I5 could have valuable savedSP | |
| 3361 __ set(0xDEADBEEF, L0); | |
| 3362 __ mov(L0, L1); | |
| 3363 __ mov(L0, L2); | |
| 3364 __ mov(L0, L3); | |
| 3365 __ mov(L0, L4); | |
| 3366 __ mov(L0, L5); | |
| 3367 | |
| 3368 // trash the return value as there is nothing to return yet | |
| 3369 __ set(0xDEAD0001, O7); | |
| 3370 #endif | |
| 3371 | |
| 3372 __ mov(SP, O5_savedSP); | |
| 3373 } | |
| 3374 | |
| 3375 | |
| 3376 static void make_new_frames(MacroAssembler* masm, bool deopt) { | |
| 3377 // | |
| 3378 // loop through the UnrollBlock info and create new frames | |
| 3379 // | |
| 3380 Register G3pcs = G3_scratch; | |
| 3381 Register Oreturn0 = O0; | |
| 3382 Register Oreturn1 = O1; | |
| 3383 Register O2UnrollBlock = O2; | |
| 3384 Register O3array = O3; | |
| 3385 Register O4array_size = O4; | |
| 3386 Label loop; | |
| 3387 | |
| 3388 // Before we make new frames, check to see if stack is available. | |
| 3389 // Do this after the caller's return address is on top of stack | |
| 3390 if (UseStackBanging) { | |
| 3391 // Get total frame size for interpreted frames | |
| 727 | 3392 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4); |
| 0 | 3393 __ bang_stack_size(O4, O3, G3_scratch); |
| 3394 } | |
| 3395 | |
| 727 | 3396 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size); |
| 3397 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs); | |
| 3398 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array); | |
| 0 | 3399 |
| 3400 // Adjust old interpreter frame to make space for new frame's extra java locals | |
| 3401 // | |
| 3402 // We capture the original sp for the transition frame only because it is needed in | |
| 3403 // order to properly calculate interpreter_sp_adjustment. Even though in real life | |
| 3404 // every interpreter frame captures a savedSP it is only needed at the transition | |
| 3405 // (fortunately). If we had to have it correct everywhere then we would need to | |
| 3406 // be told the sp_adjustment for each frame we create. If the frame size array | |
| 3407 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size] | |
| 3408 // for each frame we create and keep up the illusion every where. | |
| 3409 // | |
| 3410 | |
| 727 | 3411 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7); |
| 0 | 3412 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment |
| 3413 __ sub(SP, O7, SP); | |
| 3414 | |
| 3415 #ifdef ASSERT | |
| 3416 // make sure that there is at least one entry in the array | |
| 3417 __ tst(O4array_size); | |
| 5923 | 3418 __ breakpoint_trap(Assembler::zero, Assembler::icc); |
| 0 | 3419 #endif |
| 3420 | |
| 3421 // Now push the new interpreter frames | |
| 3422 __ bind(loop); | |
| 3423 | |
| 3424 // allocate a new frame, filling the registers | |
| 3425 | |
| 3426 gen_new_frame(masm, deopt); // allocate an interpreter frame | |
| 3427 | |
| 3839 | 3428 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop); |
| 0 | 3429 __ delayed()->add(O3array, wordSize, O3array); |
| 3430 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc | |
| 3431 | |
| 3432 } | |
| 3433 | |
| 3434 //------------------------------generate_deopt_blob---------------------------- | |
| 3435 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
| 3436 // instead. | |
| 3437 void SharedRuntime::generate_deopt_blob() { | |
| 3438 // allocate space for the code | |
| 3439 ResourceMark rm; | |
| 3440 // setup code generation tools | |
| 3441 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code | |
|
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3442 if (UseStackBanging) { |
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3443 pad += StackShadowPages*16 + 32; |
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3444 } |
| 0 | 3445 #ifdef _LP64 |
| 3446 CodeBuffer buffer("deopt_blob", 2100+pad, 512); | |
| 3447 #else | |
| 3448 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread) | |
| 3449 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread) | |
| 3450 CodeBuffer buffer("deopt_blob", 1600+pad, 512); | |
| 3451 #endif /* _LP64 */ | |
| 3452 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3453 FloatRegister Freturn0 = F0; | |
| 3454 Register Greturn1 = G1; | |
| 3455 Register Oreturn0 = O0; | |
| 3456 Register Oreturn1 = O1; | |
| 3457 Register O2UnrollBlock = O2; | |
| 1037 | 3458 Register L0deopt_mode = L0; |
| 3459 Register G4deopt_mode = G4_scratch; | |
| 0 | 3460 int frame_size_words; |
| 727 | 3461 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS); |
| 0 | 3462 #if !defined(_LP64) && defined(COMPILER2) |
| 727 | 3463 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS); |
| 0 | 3464 #endif |
| 3465 Label cont; | |
| 3466 | |
| 3467 OopMapSet *oop_maps = new OopMapSet(); | |
| 3468 | |
| 3469 // | |
| 3470 // This is the entry point for code which is returning to a de-optimized | |
| 3471 // frame. | |
| 3472 // The steps taken by this frame are as follows: | |
| 3473 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1) | |
| 3474 // and all potentially live registers (at a pollpoint many registers can be live). | |
| 3475 // | |
| 3476 // - call the C routine: Deoptimization::fetch_unroll_info (this function | |
| 3477 // returns information about the number and size of interpreter frames | |
| 3478 // which are equivalent to the frame which is being deoptimized) | |
| 3479 // - deallocate the unpack frame, restoring only results values. Other | |
| 3480 // volatile registers will now be captured in the vframeArray as needed. | |
| 3481 // - deallocate the deoptimization frame | |
| 3482 // - in a loop using the information returned in the previous step | |
| 3483 // push new interpreter frames (take care to propagate the return | |
| 3484 // values through each new frame pushed) | |
| 3485 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0) | |
| 3486 // - call the C routine: Deoptimization::unpack_frames (this function | |
| 3487 // lays out values on the interpreter frame which was just created) | |
| 3488 // - deallocate the dummy unpack_frame | |
| 3489 // - ensure that all the return values are correctly set and then do | |
| 3490 // a return to the interpreter entry point | |
| 3491 // | |
| 3492 // Refer to the following methods for more information: | |
| 3493 // - Deoptimization::fetch_unroll_info | |
| 3494 // - Deoptimization::unpack_frames | |
| 3495 | |
| 3496 OopMap* map = NULL; | |
| 3497 | |
| 3498 int start = __ offset(); | |
| 3499 | |
| 3500 // restore G2, the trampoline destroyed it | |
| 3501 __ get_thread(); | |
| 3502 | |
| 3503 // On entry we have been called by the deoptimized nmethod with a call that | |
| 3504 // replaced the original call (or safepoint polling location) so the deoptimizing | |
| 3505 // pc is now in O7. Return values are still in the expected places | |
| 3506 | |
| 3507 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3839 | 3508 __ ba(cont); |
| 1037 | 3509 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode); |
| 0 | 3510 |
| 3511 int exception_offset = __ offset() - start; | |
| 3512 | |
| 3513 // restore G2, the trampoline destroyed it | |
| 3514 __ get_thread(); | |
| 3515 | |
| 3516 // On entry we have been jumped to by the exception handler (or exception_blob | |
| 3517 // for server). O0 contains the exception oop and O7 contains the original | |
| 3518 // exception pc. So if we push a frame here it will look to the | |
| 3519 // stack walking code (fetch_unroll_info) just like a normal call so | |
| 3520 // state will be extracted normally. | |
| 3521 | |
| 3522 // save exception oop in JavaThread and fall through into the | |
| 3523 // exception_in_tls case since they are handled in same way except | |
| 3524 // for where the pending exception is kept. | |
| 727 | 3525 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset()); |
| 0 | 3526 |
| 3527 // | |
| 3528 // Vanilla deoptimization with an exception pending in exception_oop | |
| 3529 // | |
| 3530 int exception_in_tls_offset = __ offset() - start; | |
| 3531 | |
| 3532 // No need to update oop_map as each call to save_live_registers will produce identical oopmap | |
| 3533 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3534 | |
| 3535 // Restore G2_thread | |
| 3536 __ get_thread(); | |
| 3537 | |
| 3538 #ifdef ASSERT | |
| 3539 { | |
| 3540 // verify that there is really an exception oop in exception_oop | |
| 3541 Label has_exception; | |
| 727 | 3542 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); |
| 3839 | 3543 __ br_notnull_short(Oexception, Assembler::pt, has_exception); |
| 0 | 3544 __ stop("no exception in thread"); |
| 3545 __ bind(has_exception); | |
| 3546 | |
| 3547 // verify that there is no pending exception | |
| 3548 Label no_pending_exception; | |
| 727 | 3549 Address exception_addr(G2_thread, Thread::pending_exception_offset()); |
| 0 | 3550 __ ld_ptr(exception_addr, Oexception); |
| 3839 | 3551 __ br_null_short(Oexception, Assembler::pt, no_pending_exception); |
| 0 | 3552 __ stop("must not have pending exception here"); |
| 3553 __ bind(no_pending_exception); | |
| 3554 } | |
| 3555 #endif | |
| 3556 | |
| 3839 | 3557 __ ba(cont); |
| 1037 | 3558 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);; |
| 0 | 3559 |
| 3560 // | |
| 3561 // Reexecute entry, similar to c2 uncommon trap | |
| 3562 // | |
| 3563 int reexecute_offset = __ offset() - start; | |
| 3564 | |
| 3565 // No need to update oop_map as each call to save_live_registers will produce identical oopmap | |
| 3566 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3567 | |
| 1037 | 3568 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode); |
| 0 | 3569 |
| 3570 __ bind(cont); | |
| 3571 | |
| 3572 __ set_last_Java_frame(SP, noreg); | |
| 3573 | |
| 3574 // do the call by hand so we can get the oopmap | |
| 3575 | |
| 3576 __ mov(G2_thread, L7_thread_cache); | |
| 3577 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type); | |
| 3578 __ delayed()->mov(G2_thread, O0); | |
| 3579 | |
| 3580 // Set an oopmap for the call site this describes all our saved volatile registers | |
| 3581 | |
| 3582 oop_maps->add_gc_map( __ offset()-start, map); | |
| 3583 | |
| 3584 __ mov(L7_thread_cache, G2_thread); | |
| 3585 | |
| 3586 __ reset_last_Java_frame(); | |
| 3587 | |
| 3588 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers | |
| 3589 // so this move will survive | |
| 3590 | |
| 1037 | 3591 __ mov(L0deopt_mode, G4deopt_mode); |
| 0 | 3592 |
| 3593 __ mov(O0, O2UnrollBlock->after_save()); | |
| 3594 | |
| 3595 RegisterSaver::restore_result_registers(masm); | |
| 3596 | |
| 3597 Label noException; | |
| 3839 | 3598 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException); |
| 0 | 3599 |
| 3600 // Move the pending exception from exception_oop to Oexception so | |
| 3601 // the pending exception will be picked up the interpreter. | |
| 3602 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception); | |
| 3603 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); | |
|
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|
3604 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
| 0 | 3605 __ bind(noException); |
| 3606 | |
| 3607 // deallocate the deoptimization frame taking care to preserve the return values | |
| 3608 __ mov(Oreturn0, Oreturn0->after_save()); | |
| 3609 __ mov(Oreturn1, Oreturn1->after_save()); | |
| 3610 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
| 3611 __ restore(); | |
| 3612 | |
| 3613 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
| 3614 | |
| 3615 make_new_frames(masm, true); | |
| 3616 | |
| 3617 // push a dummy "unpack_frame" taking care of float return values and | |
| 3618 // call Deoptimization::unpack_frames to have the unpacker layout | |
| 3619 // information in the interpreter frames just created and then return | |
| 3620 // to the interpreter entry point | |
| 3621 __ save(SP, -frame_size_words*wordSize, SP); | |
| 3622 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr); | |
| 3623 #if !defined(_LP64) | |
| 3624 #if defined(COMPILER2) | |
| 1783 | 3625 // 32-bit 1-register longs return longs in G1 |
| 3626 __ stx(Greturn1, saved_Greturn1_addr); | |
| 0 | 3627 #endif |
| 3628 __ set_last_Java_frame(SP, noreg); | |
| 1037 | 3629 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode); |
| 0 | 3630 #else |
| 3631 // LP64 uses g4 in set_last_Java_frame | |
| 1037 | 3632 __ mov(G4deopt_mode, O1); |
| 0 | 3633 __ set_last_Java_frame(SP, G0); |
| 3634 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1); | |
| 3635 #endif | |
| 3636 __ reset_last_Java_frame(); | |
| 3637 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0); | |
| 3638 | |
| 3639 #if !defined(_LP64) && defined(COMPILER2) | |
| 3640 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into | |
| 1783 | 3641 // I0/I1 if the return value is long. |
| 3642 Label not_long; | |
| 3839 | 3643 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long); |
| 1783 | 3644 __ ldd(saved_Greturn1_addr,I0); |
| 3645 __ bind(not_long); | |
| 0 | 3646 #endif |
| 3647 __ ret(); | |
| 3648 __ delayed()->restore(); | |
| 3649 | |
| 3650 masm->flush(); | |
| 3651 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words); | |
| 3652 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); | |
| 3653 } | |
| 3654 | |
| 3655 #ifdef COMPILER2 | |
| 3656 | |
| 3657 //------------------------------generate_uncommon_trap_blob-------------------- | |
| 3658 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
| 3659 // instead. | |
| 3660 void SharedRuntime::generate_uncommon_trap_blob() { | |
| 3661 // allocate space for the code | |
| 3662 ResourceMark rm; | |
| 3663 // setup code generation tools | |
| 3664 int pad = VerifyThread ? 512 : 0; | |
|
4957
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7147064: assert(allocates2(pc)) failed: not in CodeBuffer memory: 0xffffffff778d9d60 <= 0xffffffff778da69c
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diff
changeset
|
3665 if (UseStackBanging) { |
|
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diff
changeset
|
3666 pad += StackShadowPages*16 + 32; |
|
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diff
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|
3667 } |
| 0 | 3668 #ifdef _LP64 |
| 3669 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512); | |
| 3670 #else | |
| 3671 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread) | |
| 3672 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread) | |
| 3673 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512); | |
| 3674 #endif | |
| 3675 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3676 Register O2UnrollBlock = O2; | |
| 3677 Register O2klass_index = O2; | |
| 3678 | |
| 3679 // | |
| 3680 // This is the entry point for all traps the compiler takes when it thinks | |
| 3681 // it cannot handle further execution of compilation code. The frame is | |
| 3682 // deoptimized in these cases and converted into interpreter frames for | |
| 3683 // execution | |
| 3684 // The steps taken by this frame are as follows: | |
| 3685 // - push a fake "unpack_frame" | |
| 3686 // - call the C routine Deoptimization::uncommon_trap (this function | |
| 3687 // packs the current compiled frame into vframe arrays and returns | |
| 3688 // information about the number and size of interpreter frames which | |
| 3689 // are equivalent to the frame which is being deoptimized) | |
| 3690 // - deallocate the "unpack_frame" | |
| 3691 // - deallocate the deoptimization frame | |
| 3692 // - in a loop using the information returned in the previous step | |
| 3693 // push interpreter frames; | |
| 3694 // - create a dummy "unpack_frame" | |
| 3695 // - call the C routine: Deoptimization::unpack_frames (this function | |
| 3696 // lays out values on the interpreter frame which was just created) | |
| 3697 // - deallocate the dummy unpack_frame | |
| 3698 // - return to the interpreter entry point | |
| 3699 // | |
| 3700 // Refer to the following methods for more information: | |
| 3701 // - Deoptimization::uncommon_trap | |
| 3702 // - Deoptimization::unpack_frame | |
| 3703 | |
| 3704 // the unloaded class index is in O0 (first parameter to this blob) | |
| 3705 | |
| 3706 // push a dummy "unpack_frame" | |
| 3707 // and call Deoptimization::uncommon_trap to pack the compiled frame into | |
| 3708 // vframe array and return the UnrollBlock information | |
| 3709 __ save_frame(0); | |
| 3710 __ set_last_Java_frame(SP, noreg); | |
| 3711 __ mov(I0, O2klass_index); | |
| 3712 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index); | |
| 3713 __ reset_last_Java_frame(); | |
| 3714 __ mov(O0, O2UnrollBlock->after_save()); | |
| 3715 __ restore(); | |
| 3716 | |
| 3717 // deallocate the deoptimized frame taking care to preserve the return values | |
| 3718 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
| 3719 __ restore(); | |
| 3720 | |
| 3721 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
| 3722 | |
| 3723 make_new_frames(masm, false); | |
| 3724 | |
| 3725 // push a dummy "unpack_frame" taking care of float return values and | |
| 3726 // call Deoptimization::unpack_frames to have the unpacker layout | |
| 3727 // information in the interpreter frames just created and then return | |
| 3728 // to the interpreter entry point | |
| 3729 __ save_frame(0); | |
| 3730 __ set_last_Java_frame(SP, noreg); | |
| 3731 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case | |
| 3732 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3); | |
| 3733 __ reset_last_Java_frame(); | |
| 3734 __ ret(); | |
| 3735 __ delayed()->restore(); | |
| 3736 | |
| 3737 masm->flush(); | |
| 3738 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize); | |
| 3739 } | |
| 3740 | |
| 3741 #endif // COMPILER2 | |
| 3742 | |
| 3743 //------------------------------generate_handler_blob------------------- | |
| 3744 // | |
| 3745 // Generate a special Compile2Runtime blob that saves all registers, and sets | |
| 3746 // up an OopMap. | |
| 3747 // | |
| 3748 // This blob is jumped to (via a breakpoint and the signal handler) from a | |
| 3749 // safepoint in compiled code. On entry to this blob, O7 contains the | |
| 3750 // address in the original nmethod at which we should resume normal execution. | |
| 3751 // Thus, this blob looks like a subroutine which must preserve lots of | |
| 3752 // registers and return normally. Note that O7 is never register-allocated, | |
| 3753 // so it is guaranteed to be free here. | |
| 3754 // | |
| 3755 | |
| 3756 // The hardest part of what this blob must do is to save the 64-bit %o | |
| 3757 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and | |
| 3758 // an interrupt will chop off their heads. Making space in the caller's frame | |
| 3759 // first will let us save the 64-bit %o's before save'ing, but we cannot hand | |
| 3760 // the adjusted FP off to the GC stack-crawler: this will modify the caller's | |
| 3761 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save | |
| 3762 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP). | |
| 3763 // Tricky, tricky, tricky... | |
| 3764 | |
|
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6790
diff
changeset
|
3765 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { |
| 0 | 3766 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
| 3767 | |
| 3768 // allocate space for the code | |
| 3769 ResourceMark rm; | |
| 3770 // setup code generation tools | |
| 3771 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
| 3772 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
| 3773 // even larger with TraceJumps | |
| 3774 int pad = TraceJumps ? 512 : 0; | |
| 3775 CodeBuffer buffer("handler_blob", 1600 + pad, 512); | |
| 3776 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3777 int frame_size_words; | |
| 3778 OopMapSet *oop_maps = new OopMapSet(); | |
| 3779 OopMap* map = NULL; | |
| 3780 | |
| 3781 int start = __ offset(); | |
| 3782 | |
|
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diff
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|
3783 bool cause_return = (poll_type == POLL_AT_RETURN); |
| 0 | 3784 // If this causes a return before the processing, then do a "restore" |
| 3785 if (cause_return) { | |
| 3786 __ restore(); | |
| 3787 } else { | |
| 3788 // Make it look like we were called via the poll | |
| 3789 // so that frame constructor always sees a valid return address | |
| 3790 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7); | |
| 3791 __ sub(O7, frame::pc_return_offset, O7); | |
| 3792 } | |
| 3793 | |
| 3794 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3795 | |
| 3796 // setup last_Java_sp (blows G4) | |
| 3797 __ set_last_Java_frame(SP, noreg); | |
| 3798 | |
| 3799 // call into the runtime to handle illegal instructions exception | |
| 3800 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
| 3801 __ mov(G2_thread, O0); | |
| 3802 __ save_thread(L7_thread_cache); | |
| 3803 __ call(call_ptr); | |
| 3804 __ delayed()->nop(); | |
| 3805 | |
| 3806 // Set an oopmap for the call site. | |
| 3807 // We need this not only for callee-saved registers, but also for volatile | |
| 3808 // registers that the compiler might be keeping live across a safepoint. | |
| 3809 | |
| 3810 oop_maps->add_gc_map( __ offset() - start, map); | |
| 3811 | |
| 3812 __ restore_thread(L7_thread_cache); | |
| 3813 // clear last_Java_sp | |
| 3814 __ reset_last_Java_frame(); | |
| 3815 | |
| 3816 // Check for exceptions | |
| 3817 Label pending; | |
| 3818 | |
| 3819 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
| 3839 | 3820 __ br_notnull_short(O1, Assembler::pn, pending); |
| 0 | 3821 |
| 3822 RegisterSaver::restore_live_registers(masm); | |
| 3823 | |
| 3824 // We are back the the original state on entry and ready to go. | |
| 3825 | |
| 3826 __ retl(); | |
| 3827 __ delayed()->nop(); | |
| 3828 | |
| 3829 // Pending exception after the safepoint | |
| 3830 | |
| 3831 __ bind(pending); | |
| 3832 | |
| 3833 RegisterSaver::restore_live_registers(masm); | |
| 3834 | |
| 3835 // We are back the the original state on entry. | |
| 3836 | |
| 3837 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
| 3838 // so it looks like the original nmethod called forward_exception_entry. | |
| 3839 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
| 3840 __ JMP(O0, 0); | |
| 3841 __ delayed()->nop(); | |
| 3842 | |
| 3843 // ------------- | |
| 3844 // make sure all code is generated | |
| 3845 masm->flush(); | |
| 3846 | |
| 3847 // return exception blob | |
| 3848 return SafepointBlob::create(&buffer, oop_maps, frame_size_words); | |
| 3849 } | |
| 3850 | |
| 3851 // | |
| 3852 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss | |
| 3853 // | |
| 3854 // Generate a stub that calls into vm to find out the proper destination | |
| 3855 // of a java call. All the argument registers are live at this point | |
| 3856 // but since this is generic code we don't know what they are and the caller | |
| 3857 // must do any gc of the args. | |
| 3858 // | |
|
3442
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2405
diff
changeset
|
3859 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { |
| 0 | 3860 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
| 3861 | |
| 3862 // allocate space for the code | |
| 3863 ResourceMark rm; | |
| 3864 // setup code generation tools | |
| 3865 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
| 3866 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
| 3867 // even larger with TraceJumps | |
| 3868 int pad = TraceJumps ? 512 : 0; | |
| 3869 CodeBuffer buffer(name, 1600 + pad, 512); | |
| 3870 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3871 int frame_size_words; | |
| 3872 OopMapSet *oop_maps = new OopMapSet(); | |
| 3873 OopMap* map = NULL; | |
| 3874 | |
| 3875 int start = __ offset(); | |
| 3876 | |
| 3877 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
| 3878 | |
| 3879 int frame_complete = __ offset(); | |
| 3880 | |
| 3881 // setup last_Java_sp (blows G4) | |
| 3882 __ set_last_Java_frame(SP, noreg); | |
| 3883 | |
| 3884 // call into the runtime to handle illegal instructions exception | |
| 3885 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
| 3886 __ mov(G2_thread, O0); | |
| 3887 __ save_thread(L7_thread_cache); | |
| 3888 __ call(destination, relocInfo::runtime_call_type); | |
| 3889 __ delayed()->nop(); | |
| 3890 | |
| 3891 // O0 contains the address we are going to jump to assuming no exception got installed | |
| 3892 | |
| 3893 // Set an oopmap for the call site. | |
| 3894 // We need this not only for callee-saved registers, but also for volatile | |
| 3895 // registers that the compiler might be keeping live across a safepoint. | |
| 3896 | |
| 3897 oop_maps->add_gc_map( __ offset() - start, map); | |
| 3898 | |
| 3899 __ restore_thread(L7_thread_cache); | |
| 3900 // clear last_Java_sp | |
| 3901 __ reset_last_Java_frame(); | |
| 3902 | |
| 3903 // Check for exceptions | |
| 3904 Label pending; | |
| 3905 | |
| 3906 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
| 3839 | 3907 __ br_notnull_short(O1, Assembler::pn, pending); |
| 0 | 3908 |
|
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6266
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|
3909 // get the returned Method* |
|
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|
3910 |
|
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|
3911 __ get_vm_result_2(G5_method); |
| 0 | 3912 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS); |
| 3913 | |
| 3914 // O0 is where we want to jump, overwrite G3 which is saved and scratch | |
| 3915 | |
| 3916 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS); | |
| 3917 | |
| 3918 RegisterSaver::restore_live_registers(masm); | |
| 3919 | |
| 3920 // We are back the the original state on entry and ready to go. | |
| 3921 | |
| 3922 __ JMP(G3, 0); | |
| 3923 __ delayed()->nop(); | |
| 3924 | |
| 3925 // Pending exception after the safepoint | |
| 3926 | |
| 3927 __ bind(pending); | |
| 3928 | |
| 3929 RegisterSaver::restore_live_registers(masm); | |
| 3930 | |
| 3931 // We are back the the original state on entry. | |
| 3932 | |
| 3933 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
| 3934 // so it looks like the original nmethod called forward_exception_entry. | |
| 3935 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
| 3936 __ JMP(O0, 0); | |
| 3937 __ delayed()->nop(); | |
| 3938 | |
| 3939 // ------------- | |
| 3940 // make sure all code is generated | |
| 3941 masm->flush(); | |
| 3942 | |
| 3943 // return the blob | |
| 3944 // frame_size_words or bytes?? | |
| 3945 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); | |
| 3946 } |