Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.hpp @ 20804:7848fc12602b
Merge with jdk8u40-b25
| author | Gilles Duboscq <gilles.m.duboscq@oracle.com> |
|---|---|
| date | Tue, 07 Apr 2015 14:58:49 +0200 |
| parents | 52b4284cb496 166d744df0de |
| children |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 7951 | 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
| 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
| 27 | |
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28 #include "asm/register.hpp" |
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29 |
| 0 | 30 class BiasedLockingCounters; |
| 31 | |
| 32 // Contains all the definitions needed for x86 assembly code generation. | |
| 33 | |
| 34 // Calling convention | |
| 35 class Argument VALUE_OBJ_CLASS_SPEC { | |
| 36 public: | |
| 37 enum { | |
| 38 #ifdef _LP64 | |
| 39 #ifdef _WIN64 | |
| 40 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 41 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
| 42 #else | |
| 43 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 44 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
| 45 #endif // _WIN64 | |
| 46 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
| 47 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
| 48 #else | |
| 49 n_register_parameters = 0 // 0 registers used to pass arguments | |
| 50 #endif // _LP64 | |
| 51 }; | |
| 52 }; | |
| 53 | |
| 54 | |
| 55 #ifdef _LP64 | |
| 56 // Symbolically name the register arguments used by the c calling convention. | |
| 57 // Windows is different from linux/solaris. So much for standards... | |
| 58 | |
| 59 #ifdef _WIN64 | |
| 60 | |
| 61 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
| 62 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
| 63 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
| 64 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
| 65 | |
| 304 | 66 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
| 67 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 68 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 69 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 0 | 70 |
| 71 #else | |
| 72 | |
| 73 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
| 74 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
| 75 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
| 76 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
| 77 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
| 78 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
| 79 | |
| 304 | 80 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
| 81 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 82 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 83 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 84 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
| 85 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
| 86 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
| 87 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
| 0 | 88 |
| 89 #endif // _WIN64 | |
| 90 | |
| 91 // Symbolically name the register arguments used by the Java calling convention. | |
| 92 // We have control over the convention for java so we can do what we please. | |
| 93 // What pleases us is to offset the java calling convention so that when | |
| 94 // we call a suitable jni method the arguments are lined up and we don't | |
| 95 // have to do little shuffling. A suitable jni method is non-static and a | |
| 96 // small number of arguments (two fewer args on windows) | |
| 97 // | |
| 98 // |-------------------------------------------------------| | |
| 99 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
| 100 // |-------------------------------------------------------| | |
| 101 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
| 102 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
| 103 // |-------------------------------------------------------| | |
| 104 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
| 105 // |-------------------------------------------------------| | |
| 106 | |
| 107 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
| 108 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
| 109 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
| 110 // Windows runs out of register args here | |
| 111 #ifdef _WIN64 | |
| 112 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
| 113 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
| 114 #else | |
| 115 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
| 116 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
| 117 #endif /* _WIN64 */ | |
| 118 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
| 119 | |
| 304 | 120 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
| 121 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
| 122 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
| 123 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
| 124 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
| 125 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
| 126 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
| 127 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
| 0 | 128 |
| 129 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
| 130 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
| 131 | |
| 304 | 132 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
| 0 | 133 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
| 134 | |
| 304 | 135 #else |
| 136 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
| 137 // Using noreg ensures if the dead code is incorrectly live and executed it | |
| 138 // will cause an assertion failure | |
| 139 #define rscratch1 noreg | |
| 2002 | 140 #define rscratch2 noreg |
| 304 | 141 |
| 0 | 142 #endif // _LP64 |
| 143 | |
| 1564 | 144 // JSR 292 fixed register usages: |
| 145 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
| 146 | |
| 0 | 147 // Address is an abstraction used to represent a memory location |
| 148 // using any of the amd64 addressing modes with one object. | |
| 149 // | |
| 150 // Note: A register location is represented via a Register, not | |
| 151 // via an address for efficiency & simplicity reasons. | |
| 152 | |
| 153 class ArrayAddress; | |
| 154 | |
| 155 class Address VALUE_OBJ_CLASS_SPEC { | |
| 156 public: | |
| 157 enum ScaleFactor { | |
| 158 no_scale = -1, | |
| 159 times_1 = 0, | |
| 160 times_2 = 1, | |
| 161 times_4 = 2, | |
| 304 | 162 times_8 = 3, |
| 163 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
| 0 | 164 }; |
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165 static ScaleFactor times(int size) { |
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166 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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167 if (size == 8) return times_8; |
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168 if (size == 4) return times_4; |
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169 if (size == 2) return times_2; |
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170 return times_1; |
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171 } |
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172 static int scale_size(ScaleFactor scale) { |
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173 assert(scale != no_scale, ""); |
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174 assert(((1 << (int)times_1) == 1 && |
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175 (1 << (int)times_2) == 2 && |
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176 (1 << (int)times_4) == 4 && |
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177 (1 << (int)times_8) == 8), ""); |
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178 return (1 << (int)scale); |
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179 } |
| 0 | 180 |
| 181 private: | |
| 182 Register _base; | |
| 183 Register _index; | |
| 184 ScaleFactor _scale; | |
| 185 int _disp; | |
| 186 RelocationHolder _rspec; | |
| 187 | |
| 304 | 188 // Easily misused constructors make them private |
| 189 // %%% can we make these go away? | |
| 190 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
| 191 Address(int disp, address loc, relocInfo::relocType rtype); | |
| 192 Address(int disp, address loc, RelocationHolder spec); | |
| 0 | 193 |
| 194 public: | |
| 304 | 195 |
| 196 int disp() { return _disp; } | |
| 0 | 197 // creation |
| 198 Address() | |
| 199 : _base(noreg), | |
| 200 _index(noreg), | |
| 201 _scale(no_scale), | |
| 202 _disp(0) { | |
| 203 } | |
| 204 | |
| 205 // No default displacement otherwise Register can be implicitly | |
| 206 // converted to 0(Register) which is quite a different animal. | |
| 207 | |
| 208 Address(Register base, int disp) | |
| 209 : _base(base), | |
| 210 _index(noreg), | |
| 211 _scale(no_scale), | |
| 212 _disp(disp) { | |
| 213 } | |
| 214 | |
| 215 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
| 216 : _base (base), | |
| 217 _index(index), | |
| 218 _scale(scale), | |
| 219 _disp (disp) { | |
| 220 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 221 "inconsistent address"); | |
| 222 } | |
| 223 | |
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224 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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225 : _base (base), |
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226 _index(index.register_or_noreg()), |
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227 _scale(scale), |
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228 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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229 if (!index.is_register()) scale = Address::no_scale; |
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230 assert(!_index->is_valid() == (scale == Address::no_scale), |
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231 "inconsistent address"); |
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232 } |
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233 |
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234 Address plus_disp(int disp) const { |
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235 Address a = (*this); |
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236 a._disp += disp; |
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237 return a; |
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238 } |
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239 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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240 Address a = (*this); |
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241 a._disp += disp.constant_or_zero() * scale_size(scale); |
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242 if (disp.is_register()) { |
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243 assert(!a.index()->is_valid(), "competing indexes"); |
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244 a._index = disp.as_register(); |
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245 a._scale = scale; |
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246 } |
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247 return a; |
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248 } |
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249 bool is_same_address(Address a) const { |
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250 // disregard _rspec |
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251 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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252 } |
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253 |
| 0 | 254 // The following two overloads are used in connection with the |
| 255 // ByteSize type (see sizes.hpp). They simplify the use of | |
| 256 // ByteSize'd arguments in assembly code. Note that their equivalent | |
| 257 // for the optimized build are the member functions with int disp | |
| 258 // argument since ByteSize is mapped to an int type in that case. | |
| 259 // | |
| 260 // Note: DO NOT introduce similar overloaded functions for WordSize | |
| 261 // arguments as in the optimized mode, both ByteSize and WordSize | |
| 262 // are mapped to the same type and thus the compiler cannot make a | |
| 263 // distinction anymore (=> compiler errors). | |
| 264 | |
| 265 #ifdef ASSERT | |
| 266 Address(Register base, ByteSize disp) | |
| 267 : _base(base), | |
| 268 _index(noreg), | |
| 269 _scale(no_scale), | |
| 270 _disp(in_bytes(disp)) { | |
| 271 } | |
| 272 | |
| 273 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
| 274 : _base(base), | |
| 275 _index(index), | |
| 276 _scale(scale), | |
| 277 _disp(in_bytes(disp)) { | |
| 278 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 279 "inconsistent address"); | |
| 280 } | |
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281 |
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282 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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283 : _base (base), |
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284 _index(index.register_or_noreg()), |
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285 _scale(scale), |
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286 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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287 if (!index.is_register()) scale = Address::no_scale; |
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288 assert(!_index->is_valid() == (scale == Address::no_scale), |
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289 "inconsistent address"); |
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290 } |
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291 |
| 0 | 292 #endif // ASSERT |
| 293 | |
| 294 // accessors | |
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295 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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296 Register base() const { return _base; } |
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297 Register index() const { return _index; } |
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298 ScaleFactor scale() const { return _scale; } |
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299 int disp() const { return _disp; } |
| 0 | 300 |
| 301 // Convert the raw encoding form into the form expected by the constructor for | |
| 302 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 303 // that to noreg for the Address constructor. | |
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304 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
| 0 | 305 |
| 306 static Address make_array(ArrayAddress); | |
| 307 | |
| 308 private: | |
| 309 bool base_needs_rex() const { | |
| 310 return _base != noreg && _base->encoding() >= 8; | |
| 311 } | |
| 312 | |
| 313 bool index_needs_rex() const { | |
| 314 return _index != noreg &&_index->encoding() >= 8; | |
| 315 } | |
| 316 | |
| 317 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 318 | |
| 319 friend class Assembler; | |
| 320 friend class MacroAssembler; | |
| 321 friend class LIR_Assembler; // base/index/scale/disp | |
| 322 }; | |
| 323 | |
| 324 // | |
| 325 // AddressLiteral has been split out from Address because operands of this type | |
| 326 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
| 327 // the few instructions that need to deal with address literals are unique and the | |
| 328 // MacroAssembler does not have to implement every instruction in the Assembler | |
| 329 // in order to search for address literals that may need special handling depending | |
| 330 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
| 331 // directories. | |
| 332 // | |
| 333 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
| 334 friend class ArrayAddress; | |
| 335 RelocationHolder _rspec; | |
| 336 // Typically we use AddressLiterals we want to use their rval | |
| 337 // However in some situations we want the lval (effect address) of the item. | |
| 338 // We provide a special factory for making those lvals. | |
| 339 bool _is_lval; | |
| 340 | |
| 341 // If the target is far we'll need to load the ea of this to | |
| 342 // a register to reach it. Otherwise if near we can do rip | |
| 343 // relative addressing. | |
| 344 | |
| 345 address _target; | |
| 346 | |
| 347 protected: | |
| 348 // creation | |
| 349 AddressLiteral() | |
| 350 : _is_lval(false), | |
| 351 _target(NULL) | |
| 352 {} | |
| 353 | |
| 354 public: | |
| 355 | |
| 356 | |
| 357 AddressLiteral(address target, relocInfo::relocType rtype); | |
| 358 | |
| 359 AddressLiteral(address target, RelocationHolder const& rspec) | |
| 360 : _rspec(rspec), | |
| 361 _is_lval(false), | |
| 362 _target(target) | |
| 363 {} | |
| 364 | |
| 365 AddressLiteral addr() { | |
| 366 AddressLiteral ret = *this; | |
| 367 ret._is_lval = true; | |
| 368 return ret; | |
| 369 } | |
| 370 | |
| 371 | |
| 372 private: | |
| 373 | |
| 374 address target() { return _target; } | |
| 375 bool is_lval() { return _is_lval; } | |
| 376 | |
| 377 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 378 const RelocationHolder& rspec() const { return _rspec; } | |
| 379 | |
| 380 friend class Assembler; | |
| 381 friend class MacroAssembler; | |
| 382 friend class Address; | |
| 383 friend class LIR_Assembler; | |
| 384 }; | |
| 385 | |
| 386 // Convience classes | |
| 387 class RuntimeAddress: public AddressLiteral { | |
| 388 | |
| 389 public: | |
| 390 | |
| 391 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
| 392 | |
| 393 }; | |
| 394 | |
| 395 class ExternalAddress: public AddressLiteral { | |
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396 private: |
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397 static relocInfo::relocType reloc_for_target(address target) { |
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398 // Sometimes ExternalAddress is used for values which aren't |
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399 // exactly addresses, like the card table base. |
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400 // external_word_type can't be used for values in the first page |
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401 // so just skip the reloc in that case. |
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402 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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403 } |
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404 |
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405 public: |
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406 |
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407 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
| 0 | 408 |
| 409 }; | |
| 410 | |
| 411 class InternalAddress: public AddressLiteral { | |
| 412 | |
| 413 public: | |
| 414 | |
| 415 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
| 416 | |
| 417 }; | |
| 418 | |
| 419 // x86 can do array addressing as a single operation since disp can be an absolute | |
| 420 // address amd64 can't. We create a class that expresses the concept but does extra | |
| 421 // magic on amd64 to get the final result | |
| 422 | |
| 423 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
| 424 private: | |
| 425 | |
| 426 AddressLiteral _base; | |
| 427 Address _index; | |
| 428 | |
| 429 public: | |
| 430 | |
| 431 ArrayAddress() {}; | |
| 432 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
| 433 AddressLiteral base() { return _base; } | |
| 434 Address index() { return _index; } | |
| 435 | |
| 436 }; | |
| 437 | |
| 304 | 438 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
| 0 | 439 |
| 440 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
| 441 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
| 442 // is what you get. The Assembler is generating code into a CodeBuffer. | |
| 443 | |
| 444 class Assembler : public AbstractAssembler { | |
| 445 friend class AbstractAssembler; // for the non-virtual hack | |
| 446 friend class LIR_Assembler; // as_Address() | |
| 304 | 447 friend class StubGenerator; |
| 0 | 448 |
| 449 public: | |
| 450 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
| 451 zero = 0x4, | |
| 452 notZero = 0x5, | |
| 453 equal = 0x4, | |
| 454 notEqual = 0x5, | |
| 455 less = 0xc, | |
| 456 lessEqual = 0xe, | |
| 457 greater = 0xf, | |
| 458 greaterEqual = 0xd, | |
| 459 below = 0x2, | |
| 460 belowEqual = 0x6, | |
| 461 above = 0x7, | |
| 462 aboveEqual = 0x3, | |
| 463 overflow = 0x0, | |
| 464 noOverflow = 0x1, | |
| 465 carrySet = 0x2, | |
| 466 carryClear = 0x3, | |
| 467 negative = 0x8, | |
| 468 positive = 0x9, | |
| 469 parity = 0xa, | |
| 470 noParity = 0xb | |
| 471 }; | |
| 472 | |
| 473 enum Prefix { | |
| 474 // segment overrides | |
| 475 CS_segment = 0x2e, | |
| 476 SS_segment = 0x36, | |
| 477 DS_segment = 0x3e, | |
| 478 ES_segment = 0x26, | |
| 479 FS_segment = 0x64, | |
| 480 GS_segment = 0x65, | |
| 481 | |
| 482 REX = 0x40, | |
| 483 | |
| 484 REX_B = 0x41, | |
| 485 REX_X = 0x42, | |
| 486 REX_XB = 0x43, | |
| 487 REX_R = 0x44, | |
| 488 REX_RB = 0x45, | |
| 489 REX_RX = 0x46, | |
| 490 REX_RXB = 0x47, | |
| 491 | |
| 492 REX_W = 0x48, | |
| 493 | |
| 494 REX_WB = 0x49, | |
| 495 REX_WX = 0x4A, | |
| 496 REX_WXB = 0x4B, | |
| 497 REX_WR = 0x4C, | |
| 498 REX_WRB = 0x4D, | |
| 499 REX_WRX = 0x4E, | |
| 4759 | 500 REX_WRXB = 0x4F, |
| 501 | |
| 502 VEX_3bytes = 0xC4, | |
| 503 VEX_2bytes = 0xC5 | |
| 504 }; | |
| 505 | |
| 506 enum VexPrefix { | |
| 507 VEX_B = 0x20, | |
| 508 VEX_X = 0x40, | |
| 509 VEX_R = 0x80, | |
| 510 VEX_W = 0x80 | |
| 511 }; | |
| 512 | |
| 513 enum VexSimdPrefix { | |
| 514 VEX_SIMD_NONE = 0x0, | |
| 515 VEX_SIMD_66 = 0x1, | |
| 516 VEX_SIMD_F3 = 0x2, | |
| 517 VEX_SIMD_F2 = 0x3 | |
| 518 }; | |
| 519 | |
| 520 enum VexOpcode { | |
| 521 VEX_OPCODE_NONE = 0x0, | |
| 522 VEX_OPCODE_0F = 0x1, | |
| 523 VEX_OPCODE_0F_38 = 0x2, | |
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524 VEX_OPCODE_0F_3A = 0x3, |
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525 VEX_OPCODE_MASK = 0x1F |
| 0 | 526 }; |
| 527 | |
| 528 enum WhichOperand { | |
| 529 // input to locate_operand, and format code for relocations | |
| 304 | 530 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
| 0 | 531 disp32_operand = 1, // embedded 32-bit displacement or address |
| 532 call32_operand = 2, // embedded 32-bit self-relative displacement | |
| 304 | 533 #ifndef _LP64 |
| 0 | 534 _WhichOperand_limit = 3 |
| 304 | 535 #else |
| 536 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
| 537 _WhichOperand_limit = 4 | |
| 538 #endif | |
| 0 | 539 }; |
| 540 | |
| 304 | 541 |
| 542 | |
| 543 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
| 544 // of instructions are freely declared without the need for wrapping them an ifdef. | |
| 545 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
| 546 // In the .cpp file the implementations are wrapped so that they are dropped out | |
| 7951 | 547 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL |
| 304 | 548 // to the size it was prior to merging up the 32bit and 64bit assemblers. |
| 549 // | |
| 550 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
| 551 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
| 552 | |
| 553 private: | |
| 554 | |
| 555 | |
| 556 // 64bit prefixes | |
| 557 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
| 558 int prefixq_and_encode(int reg_enc); | |
| 559 | |
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560 int prefix_and_encode(int dst_enc, int src_enc) { |
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561 return prefix_and_encode(dst_enc, false, src_enc, false); |
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562 } |
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563 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); |
| 304 | 564 int prefixq_and_encode(int dst_enc, int src_enc); |
| 565 | |
| 566 void prefix(Register reg); | |
| 567 void prefix(Address adr); | |
| 568 void prefixq(Address adr); | |
| 569 | |
| 570 void prefix(Address adr, Register reg, bool byteinst = false); | |
| 4759 | 571 void prefix(Address adr, XMMRegister reg); |
| 304 | 572 void prefixq(Address adr, Register reg); |
| 4759 | 573 void prefixq(Address adr, XMMRegister reg); |
| 304 | 574 |
| 575 void prefetch_prefix(Address src); | |
| 576 | |
| 4759 | 577 void rex_prefix(Address adr, XMMRegister xreg, |
| 578 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
| 579 int rex_prefix_and_encode(int dst_enc, int src_enc, | |
| 580 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
| 581 | |
| 582 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, | |
| 583 int nds_enc, VexSimdPrefix pre, VexOpcode opc, | |
| 584 bool vector256); | |
| 585 | |
| 586 void vex_prefix(Address adr, int nds_enc, int xreg_enc, | |
| 587 VexSimdPrefix pre, VexOpcode opc, | |
| 588 bool vex_w, bool vector256); | |
| 589 | |
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590 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
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591 VexSimdPrefix pre, bool vector256 = false) { |
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592 int dst_enc = dst->encoding(); |
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593 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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594 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); |
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595 } |
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596 |
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597 void vex_prefix_0F38(Register dst, Register nds, Address src) { |
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598 bool vex_w = false; |
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599 bool vector256 = false; |
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600 vex_prefix(src, nds->encoding(), dst->encoding(), |
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601 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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602 } |
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603 |
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604 void vex_prefix_0F38_q(Register dst, Register nds, Address src) { |
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605 bool vex_w = true; |
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606 bool vector256 = false; |
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607 vex_prefix(src, nds->encoding(), dst->encoding(), |
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608 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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609 } |
| 4759 | 610 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
| 611 VexSimdPrefix pre, VexOpcode opc, | |
| 612 bool vex_w, bool vector256); | |
| 613 | |
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614 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) { |
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615 bool vex_w = false; |
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616 bool vector256 = false; |
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617 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
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618 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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619 } |
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620 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) { |
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621 bool vex_w = true; |
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622 bool vector256 = false; |
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623 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
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624 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
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625 } |
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626 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
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627 VexSimdPrefix pre, bool vector256 = false, |
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628 VexOpcode opc = VEX_OPCODE_0F) { |
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629 int src_enc = src->encoding(); |
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630 int dst_enc = dst->encoding(); |
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631 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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632 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); |
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633 } |
| 4759 | 634 |
| 635 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, | |
| 636 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
| 637 bool rex_w = false, bool vector256 = false); | |
| 638 | |
| 639 void simd_prefix(XMMRegister dst, Address src, | |
| 640 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 641 simd_prefix(dst, xnoreg, src, pre, opc); | |
| 642 } | |
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643 |
| 4759 | 644 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
| 645 simd_prefix(src, dst, pre); | |
| 646 } | |
| 647 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, | |
| 648 VexSimdPrefix pre) { | |
| 649 bool rex_w = true; | |
| 650 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); | |
| 651 } | |
| 652 | |
| 653 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, | |
| 654 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
| 655 bool rex_w = false, bool vector256 = false); | |
| 656 | |
| 657 // Move/convert 32-bit integer value. | |
| 658 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, | |
| 659 VexSimdPrefix pre) { | |
| 660 // It is OK to cast from Register to XMMRegister to pass argument here | |
| 661 // since only encoding is used in simd_prefix_and_encode() and number of | |
| 662 // Gen and Xmm registers are the same. | |
| 663 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); | |
| 664 } | |
| 665 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
| 666 return simd_prefix_and_encode(dst, xnoreg, src, pre); | |
| 667 } | |
| 668 int simd_prefix_and_encode(Register dst, XMMRegister src, | |
| 669 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 670 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); | |
| 671 } | |
| 672 | |
| 673 // Move/convert 64-bit integer value. | |
| 674 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, | |
| 675 VexSimdPrefix pre) { | |
| 676 bool rex_w = true; | |
| 677 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); | |
| 678 } | |
| 679 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
| 680 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); | |
| 681 } | |
| 682 int simd_prefix_and_encode_q(Register dst, XMMRegister src, | |
| 683 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 684 bool rex_w = true; | |
| 685 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); | |
| 686 } | |
| 687 | |
| 304 | 688 // Helper functions for groups of instructions |
| 689 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
| 690 | |
| 691 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
|
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692 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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693 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
| 304 | 694 void emit_arith(int op1, int op2, Register dst, Register src); |
| 695 | |
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696 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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697 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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698 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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699 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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700 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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701 Address src, VexSimdPrefix pre, bool vector256); |
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702 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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703 XMMRegister src, VexSimdPrefix pre, bool vector256); |
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704 |
| 304 | 705 void emit_operand(Register reg, |
| 706 Register base, Register index, Address::ScaleFactor scale, | |
| 707 int disp, | |
| 708 RelocationHolder const& rspec, | |
| 709 int rip_relative_correction = 0); | |
| 710 | |
| 711 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
| 712 | |
| 713 // operands that only take the original 32bit registers | |
| 714 void emit_operand32(Register reg, Address adr); | |
| 715 | |
| 716 void emit_operand(XMMRegister reg, | |
| 717 Register base, Register index, Address::ScaleFactor scale, | |
| 718 int disp, | |
| 719 RelocationHolder const& rspec); | |
| 720 | |
| 721 void emit_operand(XMMRegister reg, Address adr); | |
| 722 | |
| 723 void emit_operand(MMXRegister reg, Address adr); | |
| 724 | |
| 725 // workaround gcc (3.2.1-7) bug | |
| 726 void emit_operand(Address adr, MMXRegister reg); | |
| 727 | |
| 728 | |
| 729 // Immediate-to-memory forms | |
| 730 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
| 731 | |
| 732 void emit_farith(int b1, int b2, int i); | |
| 733 | |
| 734 | |
| 735 protected: | |
| 736 #ifdef ASSERT | |
| 737 void check_relocation(RelocationHolder const& rspec, int format); | |
| 738 #endif | |
| 739 | |
| 740 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
| 741 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
| 742 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
| 743 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
| 744 | |
| 745 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
| 746 | |
| 747 // These are all easily abused and hence protected | |
| 748 | |
| 749 // 32BIT ONLY SECTION | |
| 750 #ifndef _LP64 | |
| 751 // Make these disappear in 64bit mode since they would never be correct | |
| 752 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 753 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 754 | |
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755 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
| 304 | 756 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
| 757 | |
| 758 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 759 #else | |
| 760 // 64BIT ONLY SECTION | |
| 761 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
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762 |
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763 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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764 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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765 |
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766 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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767 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
| 304 | 768 #endif // _LP64 |
| 769 | |
| 770 // These are unique in that we are ensured by the caller that the 32bit | |
| 771 // relative in these instructions will always be able to reach the potentially | |
| 772 // 64bit address described by entry. Since they can take a 64bit address they | |
| 773 // don't have the 32 suffix like the other instructions in this class. | |
| 774 | |
| 775 void call_literal(address entry, RelocationHolder const& rspec); | |
| 776 void jmp_literal(address entry, RelocationHolder const& rspec); | |
| 777 | |
| 778 // Avoid using directly section | |
| 779 // Instructions in this section are actually usable by anyone without danger | |
| 780 // of failure but have performance issues that are addressed my enhanced | |
| 781 // instructions which will do the proper thing base on the particular cpu. | |
| 782 // We protect them because we don't trust you... | |
| 783 | |
| 784 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
| 785 // could cause a partial flag stall since they don't set CF flag. | |
| 786 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
| 787 // which call inc() & dec() or add() & sub() in accordance with | |
| 788 // the product flag UseIncDec value. | |
| 789 | |
| 790 void decl(Register dst); | |
| 791 void decl(Address dst); | |
| 792 void decq(Register dst); | |
| 793 void decq(Address dst); | |
| 794 | |
| 795 void incl(Register dst); | |
| 796 void incl(Address dst); | |
| 797 void incq(Register dst); | |
| 798 void incq(Address dst); | |
| 799 | |
| 800 // New cpus require use of movsd and movss to avoid partial register stall | |
| 801 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 802 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 803 | |
| 804 // Move Scalar Single-Precision Floating-Point Values | |
| 805 void movss(XMMRegister dst, Address src); | |
| 806 void movss(XMMRegister dst, XMMRegister src); | |
| 807 void movss(Address dst, XMMRegister src); | |
| 808 | |
| 809 // Move Scalar Double-Precision Floating-Point Values | |
| 810 void movsd(XMMRegister dst, Address src); | |
| 811 void movsd(XMMRegister dst, XMMRegister src); | |
| 812 void movsd(Address dst, XMMRegister src); | |
| 813 void movlpd(XMMRegister dst, Address src); | |
| 814 | |
| 815 // New cpus require use of movaps and movapd to avoid partial register stall | |
| 816 // when moving between registers. | |
| 817 void movaps(XMMRegister dst, XMMRegister src); | |
| 818 void movapd(XMMRegister dst, XMMRegister src); | |
| 819 | |
| 820 // End avoid using directly | |
| 821 | |
| 822 | |
| 823 // Instruction prefixes | |
| 824 void prefix(Prefix p); | |
| 825 | |
| 0 | 826 public: |
| 827 | |
| 828 // Creation | |
| 829 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
| 830 | |
| 831 // Decoding | |
| 832 static address locate_operand(address inst, WhichOperand which); | |
| 833 static address locate_next_instruction(address inst); | |
| 834 | |
| 304 | 835 // Utilities |
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836 static bool is_polling_page_far() NOT_LP64({ return false;}); |
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837 |
| 304 | 838 // Generic instructions |
| 839 // Does 32bit or 64bit as needed for the platform. In some sense these | |
| 840 // belong in macro assembler but there is no need for both varieties to exist | |
| 841 | |
| 842 void lea(Register dst, Address src); | |
| 843 | |
| 844 void mov(Register dst, Register src); | |
| 845 | |
| 846 void pusha(); | |
| 847 void popa(); | |
| 848 | |
| 849 void pushf(); | |
| 850 void popf(); | |
| 851 | |
| 852 void push(int32_t imm32); | |
| 853 | |
| 854 void push(Register src); | |
| 855 | |
| 856 void pop(Register dst); | |
| 857 | |
| 858 // These are dummies to prevent surprise implicit conversions to Register | |
| 859 void push(void* v); | |
| 860 void pop(void* v); | |
| 861 | |
| 862 // These do register sized moves/scans | |
| 863 void rep_mov(); | |
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864 void rep_stos(); |
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865 void rep_stosb(); |
| 304 | 866 void repne_scan(); |
| 867 #ifdef _LP64 | |
| 868 void repne_scanl(); | |
| 869 #endif | |
| 870 | |
| 871 // Vanilla instructions in lexical order | |
| 872 | |
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873 void adcl(Address dst, int32_t imm32); |
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874 void adcl(Address dst, Register src); |
| 304 | 875 void adcl(Register dst, int32_t imm32); |
| 0 | 876 void adcl(Register dst, Address src); |
| 877 void adcl(Register dst, Register src); | |
| 878 | |
| 304 | 879 void adcq(Register dst, int32_t imm32); |
| 880 void adcq(Register dst, Address src); | |
| 881 void adcq(Register dst, Register src); | |
| 882 | |
| 883 void addl(Address dst, int32_t imm32); | |
| 0 | 884 void addl(Address dst, Register src); |
| 304 | 885 void addl(Register dst, int32_t imm32); |
| 0 | 886 void addl(Register dst, Address src); |
| 887 void addl(Register dst, Register src); | |
| 888 | |
| 304 | 889 void addq(Address dst, int32_t imm32); |
| 890 void addq(Address dst, Register src); | |
| 891 void addq(Register dst, int32_t imm32); | |
| 892 void addq(Register dst, Address src); | |
| 893 void addq(Register dst, Register src); | |
| 894 | |
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895 #ifdef _LP64 |
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896 //Add Unsigned Integers with Carry Flag |
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897 void adcxq(Register dst, Register src); |
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898 |
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899 //Add Unsigned Integers with Overflow Flag |
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900 void adoxq(Register dst, Register src); |
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901 #endif |
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902 |
| 0 | 903 void addr_nop_4(); |
| 904 void addr_nop_5(); | |
| 905 void addr_nop_7(); | |
| 906 void addr_nop_8(); | |
| 907 | |
| 304 | 908 // Add Scalar Double-Precision Floating-Point Values |
| 909 void addsd(XMMRegister dst, Address src); | |
| 910 void addsd(XMMRegister dst, XMMRegister src); | |
| 911 | |
| 912 // Add Scalar Single-Precision Floating-Point Values | |
| 913 void addss(XMMRegister dst, Address src); | |
| 914 void addss(XMMRegister dst, XMMRegister src); | |
| 915 | |
| 6894 | 916 // AES instructions |
| 917 void aesdec(XMMRegister dst, Address src); | |
| 918 void aesdec(XMMRegister dst, XMMRegister src); | |
| 919 void aesdeclast(XMMRegister dst, Address src); | |
| 920 void aesdeclast(XMMRegister dst, XMMRegister src); | |
| 921 void aesenc(XMMRegister dst, Address src); | |
| 922 void aesenc(XMMRegister dst, XMMRegister src); | |
| 923 void aesenclast(XMMRegister dst, Address src); | |
| 924 void aesenclast(XMMRegister dst, XMMRegister src); | |
| 925 | |
| 926 | |
| 4759 | 927 void andl(Address dst, int32_t imm32); |
| 304 | 928 void andl(Register dst, int32_t imm32); |
| 929 void andl(Register dst, Address src); | |
| 930 void andl(Register dst, Register src); | |
| 931 | |
| 3457 | 932 void andq(Address dst, int32_t imm32); |
| 304 | 933 void andq(Register dst, int32_t imm32); |
| 934 void andq(Register dst, Address src); | |
| 935 void andq(Register dst, Register src); | |
| 936 | |
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937 // BMI instructions |
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938 void andnl(Register dst, Register src1, Register src2); |
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939 void andnl(Register dst, Register src1, Address src2); |
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940 void andnq(Register dst, Register src1, Register src2); |
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941 void andnq(Register dst, Register src1, Address src2); |
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942 |
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943 void blsil(Register dst, Register src); |
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944 void blsil(Register dst, Address src); |
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945 void blsiq(Register dst, Register src); |
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946 void blsiq(Register dst, Address src); |
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947 |
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948 void blsmskl(Register dst, Register src); |
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949 void blsmskl(Register dst, Address src); |
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950 void blsmskq(Register dst, Register src); |
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951 void blsmskq(Register dst, Address src); |
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952 |
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953 void blsrl(Register dst, Register src); |
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954 void blsrl(Register dst, Address src); |
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955 void blsrq(Register dst, Register src); |
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956 void blsrq(Register dst, Address src); |
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957 |
|
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958 void bsfl(Register dst, Register src); |
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959 void bsrl(Register dst, Register src); |
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960 |
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961 #ifdef _LP64 |
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962 void bsfq(Register dst, Register src); |
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963 void bsrq(Register dst, Register src); |
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964 #endif |
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965 |
| 304 | 966 void bswapl(Register reg); |
| 967 | |
| 968 void bswapq(Register reg); | |
| 969 | |
| 0 | 970 void call(Label& L, relocInfo::relocType rtype); |
| 971 void call(Register reg); // push pc; pc <- reg | |
| 972 void call(Address adr); // push pc; pc <- adr | |
| 973 | |
| 304 | 974 void cdql(); |
| 975 | |
| 976 void cdqq(); | |
| 977 | |
|
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978 void cld(); |
| 304 | 979 |
| 980 void clflush(Address adr); | |
| 981 | |
| 982 void cmovl(Condition cc, Register dst, Register src); | |
| 983 void cmovl(Condition cc, Register dst, Address src); | |
| 984 | |
| 985 void cmovq(Condition cc, Register dst, Register src); | |
| 986 void cmovq(Condition cc, Register dst, Address src); | |
| 987 | |
| 988 | |
| 989 void cmpb(Address dst, int imm8); | |
| 990 | |
| 991 void cmpl(Address dst, int32_t imm32); | |
| 992 | |
| 993 void cmpl(Register dst, int32_t imm32); | |
| 994 void cmpl(Register dst, Register src); | |
| 995 void cmpl(Register dst, Address src); | |
| 996 | |
| 997 void cmpq(Address dst, int32_t imm32); | |
| 998 void cmpq(Address dst, Register src); | |
| 999 | |
| 1000 void cmpq(Register dst, int32_t imm32); | |
| 1001 void cmpq(Register dst, Register src); | |
| 1002 void cmpq(Register dst, Address src); | |
| 1003 | |
| 1004 // these are dummies used to catch attempting to convert NULL to Register | |
| 1005 void cmpl(Register dst, void* junk); // dummy | |
| 1006 void cmpq(Register dst, void* junk); // dummy | |
| 1007 | |
| 1008 void cmpw(Address dst, int imm16); | |
| 1009 | |
| 1010 void cmpxchg8 (Address adr); | |
| 1011 | |
| 1012 void cmpxchgl(Register reg, Address adr); | |
| 1013 | |
| 1014 void cmpxchgq(Register reg, Address adr); | |
| 1015 | |
| 1016 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
| 1017 void comisd(XMMRegister dst, Address src); | |
| 4759 | 1018 void comisd(XMMRegister dst, XMMRegister src); |
| 304 | 1019 |
| 1020 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
| 1021 void comiss(XMMRegister dst, Address src); | |
| 4759 | 1022 void comiss(XMMRegister dst, XMMRegister src); |
| 304 | 1023 |
| 1024 // Identify processor type and features | |
|
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1025 void cpuid(); |
| 304 | 1026 |
| 1027 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
| 1028 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
| 4759 | 1029 void cvtsd2ss(XMMRegister dst, Address src); |
| 304 | 1030 |
| 1031 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
| 1032 void cvtsi2sdl(XMMRegister dst, Register src); | |
| 4759 | 1033 void cvtsi2sdl(XMMRegister dst, Address src); |
| 304 | 1034 void cvtsi2sdq(XMMRegister dst, Register src); |
| 4759 | 1035 void cvtsi2sdq(XMMRegister dst, Address src); |
| 304 | 1036 |
| 1037 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
| 1038 void cvtsi2ssl(XMMRegister dst, Register src); | |
| 4759 | 1039 void cvtsi2ssl(XMMRegister dst, Address src); |
| 304 | 1040 void cvtsi2ssq(XMMRegister dst, Register src); |
| 4759 | 1041 void cvtsi2ssq(XMMRegister dst, Address src); |
| 304 | 1042 |
| 1043 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
| 1044 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
| 1045 | |
| 1046 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
| 1047 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
| 1048 | |
| 1049 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
| 1050 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
| 4759 | 1051 void cvtss2sd(XMMRegister dst, Address src); |
| 304 | 1052 |
| 1053 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
| 1054 void cvttsd2sil(Register dst, Address src); | |
| 1055 void cvttsd2sil(Register dst, XMMRegister src); | |
| 1056 void cvttsd2siq(Register dst, XMMRegister src); | |
| 1057 | |
| 1058 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
| 1059 void cvttss2sil(Register dst, XMMRegister src); | |
| 1060 void cvttss2siq(Register dst, XMMRegister src); | |
| 1061 | |
| 1062 // Divide Scalar Double-Precision Floating-Point Values | |
| 1063 void divsd(XMMRegister dst, Address src); | |
| 1064 void divsd(XMMRegister dst, XMMRegister src); | |
| 1065 | |
| 1066 // Divide Scalar Single-Precision Floating-Point Values | |
| 1067 void divss(XMMRegister dst, Address src); | |
| 1068 void divss(XMMRegister dst, XMMRegister src); | |
| 1069 | |
| 1070 void emms(); | |
| 1071 | |
| 1072 void fabs(); | |
| 1073 | |
| 1074 void fadd(int i); | |
| 1075 | |
| 1076 void fadd_d(Address src); | |
| 1077 void fadd_s(Address src); | |
| 1078 | |
| 1079 // "Alternate" versions of x87 instructions place result down in FPU | |
| 1080 // stack instead of on TOS | |
| 1081 | |
| 1082 void fadda(int i); // "alternate" fadd | |
| 1083 void faddp(int i = 1); | |
| 1084 | |
| 1085 void fchs(); | |
| 1086 | |
| 1087 void fcom(int i); | |
| 1088 | |
| 1089 void fcomp(int i = 1); | |
| 1090 void fcomp_d(Address src); | |
| 1091 void fcomp_s(Address src); | |
| 1092 | |
| 1093 void fcompp(); | |
| 1094 | |
| 1095 void fcos(); | |
| 1096 | |
| 1097 void fdecstp(); | |
| 1098 | |
| 1099 void fdiv(int i); | |
| 1100 void fdiv_d(Address src); | |
| 1101 void fdivr_s(Address src); | |
| 1102 void fdiva(int i); // "alternate" fdiv | |
| 1103 void fdivp(int i = 1); | |
| 1104 | |
| 1105 void fdivr(int i); | |
| 1106 void fdivr_d(Address src); | |
| 1107 void fdiv_s(Address src); | |
| 1108 | |
| 1109 void fdivra(int i); // "alternate" reversed fdiv | |
| 1110 | |
| 1111 void fdivrp(int i = 1); | |
| 1112 | |
| 1113 void ffree(int i = 0); | |
| 1114 | |
| 1115 void fild_d(Address adr); | |
| 1116 void fild_s(Address adr); | |
| 1117 | |
| 1118 void fincstp(); | |
| 1119 | |
| 1120 void finit(); | |
| 1121 | |
| 1122 void fist_s (Address adr); | |
| 1123 void fistp_d(Address adr); | |
| 1124 void fistp_s(Address adr); | |
| 1125 | |
| 1126 void fld1(); | |
| 1127 | |
| 1128 void fld_d(Address adr); | |
| 1129 void fld_s(Address adr); | |
| 1130 void fld_s(int index); | |
| 1131 void fld_x(Address adr); // extended-precision (80-bit) format | |
| 1132 | |
| 1133 void fldcw(Address src); | |
| 1134 | |
| 1135 void fldenv(Address src); | |
| 1136 | |
| 1137 void fldlg2(); | |
| 1138 | |
| 1139 void fldln2(); | |
| 1140 | |
| 1141 void fldz(); | |
| 1142 | |
| 1143 void flog(); | |
| 1144 void flog10(); | |
| 1145 | |
| 1146 void fmul(int i); | |
| 1147 | |
| 1148 void fmul_d(Address src); | |
| 1149 void fmul_s(Address src); | |
| 1150 | |
| 1151 void fmula(int i); // "alternate" fmul | |
| 1152 | |
| 1153 void fmulp(int i = 1); | |
| 1154 | |
| 1155 void fnsave(Address dst); | |
| 1156 | |
| 1157 void fnstcw(Address src); | |
| 1158 | |
| 1159 void fnstsw_ax(); | |
| 1160 | |
| 1161 void fprem(); | |
| 1162 void fprem1(); | |
| 1163 | |
| 1164 void frstor(Address src); | |
| 1165 | |
| 1166 void fsin(); | |
| 1167 | |
| 1168 void fsqrt(); | |
| 1169 | |
| 1170 void fst_d(Address adr); | |
| 1171 void fst_s(Address adr); | |
| 1172 | |
| 1173 void fstp_d(Address adr); | |
| 1174 void fstp_d(int index); | |
| 1175 void fstp_s(Address adr); | |
| 1176 void fstp_x(Address adr); // extended-precision (80-bit) format | |
| 1177 | |
| 1178 void fsub(int i); | |
| 1179 void fsub_d(Address src); | |
| 1180 void fsub_s(Address src); | |
| 1181 | |
| 1182 void fsuba(int i); // "alternate" fsub | |
| 1183 | |
| 1184 void fsubp(int i = 1); | |
| 1185 | |
| 1186 void fsubr(int i); | |
| 1187 void fsubr_d(Address src); | |
| 1188 void fsubr_s(Address src); | |
| 1189 | |
| 1190 void fsubra(int i); // "alternate" reversed fsub | |
| 1191 | |
| 1192 void fsubrp(int i = 1); | |
| 1193 | |
| 1194 void ftan(); | |
| 1195 | |
| 1196 void ftst(); | |
| 1197 | |
| 1198 void fucomi(int i = 1); | |
| 1199 void fucomip(int i = 1); | |
| 1200 | |
| 1201 void fwait(); | |
| 1202 | |
| 1203 void fxch(int i = 1); | |
| 1204 | |
| 1205 void fxrstor(Address src); | |
| 1206 | |
| 1207 void fxsave(Address dst); | |
| 1208 | |
| 1209 void fyl2x(); | |
|
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1210 void frndint(); |
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1211 void f2xm1(); |
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1212 void fldl2e(); |
| 304 | 1213 |
| 1214 void hlt(); | |
| 1215 | |
| 1216 void idivl(Register src); | |
| 1920 | 1217 void divl(Register src); // Unsigned division |
| 304 | 1218 |
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1219 #ifdef _LP64 |
| 304 | 1220 void idivq(Register src); |
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1221 #endif |
| 304 | 1222 |
| 1223 void imull(Register dst, Register src); | |
| 1224 void imull(Register dst, Register src, int value); | |
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1225 void imull(Register dst, Address src); |
| 304 | 1226 |
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1227 #ifdef _LP64 |
| 304 | 1228 void imulq(Register dst, Register src); |
| 1229 void imulq(Register dst, Register src, int value); | |
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1230 void imulq(Register dst, Address src); |
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1231 #endif |
| 304 | 1232 |
| 0 | 1233 // jcc is the generic conditional branch generator to run- |
| 1234 // time routines, jcc is used for branches to labels. jcc | |
| 1235 // takes a branch opcode (cc) and a label (L) and generates | |
| 1236 // either a backward branch or a forward branch and links it | |
| 1237 // to the label fixup chain. Usage: | |
| 1238 // | |
| 1239 // Label L; // unbound label | |
| 1240 // jcc(cc, L); // forward branch to unbound label | |
| 1241 // bind(L); // bind label to the current pc | |
| 1242 // jcc(cc, L); // backward branch to bound label | |
| 1243 // bind(L); // illegal: a label may be bound only once | |
| 1244 // | |
| 1245 // Note: The same Label can be used for forward and backward branches | |
| 1246 // but it may be bound only once. | |
| 1247 | |
| 3851 | 1248 void jcc(Condition cc, Label& L, bool maybe_short = true); |
| 0 | 1249 |
| 1250 // Conditional jump to a 8-bit offset to L. | |
| 1251 // WARNING: be very careful using this for forward jumps. If the label is | |
| 1252 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 1253 // will occur. | |
| 1254 void jccb(Condition cc, Label& L); | |
| 1255 | |
| 304 | 1256 void jmp(Address entry); // pc <- entry |
| 1257 | |
| 1258 // Label operations & relative jumps (PPUM Appendix D) | |
| 3851 | 1259 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
| 304 | 1260 |
| 1261 void jmp(Register entry); // pc <- entry | |
| 1262 | |
| 1263 // Unconditional 8-bit offset jump to L. | |
| 1264 // WARNING: be very careful using this for forward jumps. If the label is | |
| 1265 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 1266 // will occur. | |
| 1267 void jmpb(Label& L); | |
| 1268 | |
| 1269 void ldmxcsr( Address src ); | |
| 1270 | |
| 1271 void leal(Register dst, Address src); | |
| 1272 | |
| 1273 void leaq(Register dst, Address src); | |
| 1274 | |
|
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1275 void lfence(); |
| 304 | 1276 |
| 1277 void lock(); | |
| 1278 | |
|
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1279 void lzcntl(Register dst, Register src); |
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1280 |
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1281 #ifdef _LP64 |
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1282 void lzcntq(Register dst, Register src); |
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1283 #endif |
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1284 |
| 304 | 1285 enum Membar_mask_bits { |
| 1286 StoreStore = 1 << 3, | |
| 1287 LoadStore = 1 << 2, | |
| 1288 StoreLoad = 1 << 1, | |
| 1289 LoadLoad = 1 << 0 | |
| 1290 }; | |
| 1291 | |
|
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1292 // Serializes memory and blows flags |
| 304 | 1293 void membar(Membar_mask_bits order_constraint) { |
|
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1294 if (os::is_MP()) { |
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1295 // We only have to handle StoreLoad |
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1296 if (order_constraint & StoreLoad) { |
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1297 // All usable chips support "locked" instructions which suffice |
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1298 // as barriers, and are much faster than the alternative of |
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1299 // using cpuid instruction. We use here a locked add [esp],0. |
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1300 // This is conveniently otherwise a no-op except for blowing |
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1301 // flags. |
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1302 // Any change to this code may need to revisit other places in |
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1303 // the code where this idiom is used, in particular the |
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1304 // orderAccess code. |
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1305 lock(); |
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1306 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1307 } |
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1308 } |
| 304 | 1309 } |
| 1310 | |
| 1311 void mfence(); | |
| 1312 | |
| 1313 // Moves | |
| 1314 | |
| 1315 void mov64(Register dst, int64_t imm64); | |
| 1316 | |
| 1317 void movb(Address dst, Register src); | |
| 1318 void movb(Address dst, int imm8); | |
| 1319 void movb(Register dst, Address src); | |
| 1320 | |
| 1321 void movdl(XMMRegister dst, Register src); | |
| 1322 void movdl(Register dst, XMMRegister src); | |
|
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1323 void movdl(XMMRegister dst, Address src); |
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1324 void movdl(Address dst, XMMRegister src); |
| 304 | 1325 |
| 1326 // Move Double Quadword | |
| 1327 void movdq(XMMRegister dst, Register src); | |
| 1328 void movdq(Register dst, XMMRegister src); | |
| 1329 | |
| 1330 // Move Aligned Double Quadword | |
| 1331 void movdqa(XMMRegister dst, XMMRegister src); | |
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1332 void movdqa(XMMRegister dst, Address src); |
| 304 | 1333 |
| 405 | 1334 // Move Unaligned Double Quadword |
| 1335 void movdqu(Address dst, XMMRegister src); | |
| 1336 void movdqu(XMMRegister dst, Address src); | |
| 1337 void movdqu(XMMRegister dst, XMMRegister src); | |
| 1338 | |
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1339 // Move Unaligned 256bit Vector |
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1340 void vmovdqu(Address dst, XMMRegister src); |
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1341 void vmovdqu(XMMRegister dst, Address src); |
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1342 void vmovdqu(XMMRegister dst, XMMRegister src); |
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1343 |
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1344 // Move lower 64bit to high 64bit in 128bit register |
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1345 void movlhps(XMMRegister dst, XMMRegister src); |
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1346 |
| 304 | 1347 void movl(Register dst, int32_t imm32); |
| 1348 void movl(Address dst, int32_t imm32); | |
| 1349 void movl(Register dst, Register src); | |
| 1350 void movl(Register dst, Address src); | |
| 1351 void movl(Address dst, Register src); | |
| 1352 | |
| 1353 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
| 1354 // by giving the compiler two choices it can't resolve | |
| 1355 | |
| 1356 void movl(Address dst, void* junk); | |
| 1357 void movl(Register dst, void* junk); | |
| 1358 | |
| 1359 #ifdef _LP64 | |
| 1360 void movq(Register dst, Register src); | |
| 1361 void movq(Register dst, Address src); | |
|
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1362 void movq(Address dst, Register src); |
| 304 | 1363 #endif |
| 1364 | |
| 1365 void movq(Address dst, MMXRegister src ); | |
| 1366 void movq(MMXRegister dst, Address src ); | |
| 1367 | |
| 1368 #ifdef _LP64 | |
| 1369 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
| 1370 // by giving the compiler two choices it can't resolve | |
| 1371 | |
| 1372 void movq(Address dst, void* dummy); | |
| 1373 void movq(Register dst, void* dummy); | |
| 1374 #endif | |
| 1375 | |
| 1376 // Move Quadword | |
| 1377 void movq(Address dst, XMMRegister src); | |
| 1378 void movq(XMMRegister dst, Address src); | |
| 1379 | |
| 1380 void movsbl(Register dst, Address src); | |
| 1381 void movsbl(Register dst, Register src); | |
| 1382 | |
| 1383 #ifdef _LP64 | |
| 624 | 1384 void movsbq(Register dst, Address src); |
| 1385 void movsbq(Register dst, Register src); | |
| 1386 | |
| 304 | 1387 // Move signed 32bit immediate to 64bit extending sign |
|
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|
1388 void movslq(Address dst, int32_t imm64); |
| 304 | 1389 void movslq(Register dst, int32_t imm64); |
| 1390 | |
| 1391 void movslq(Register dst, Address src); | |
| 1392 void movslq(Register dst, Register src); | |
| 1393 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
| 1394 #endif | |
| 1395 | |
| 1396 void movswl(Register dst, Address src); | |
| 1397 void movswl(Register dst, Register src); | |
| 1398 | |
| 624 | 1399 #ifdef _LP64 |
| 1400 void movswq(Register dst, Address src); | |
| 1401 void movswq(Register dst, Register src); | |
| 1402 #endif | |
| 1403 | |
| 304 | 1404 void movw(Address dst, int imm16); |
| 1405 void movw(Register dst, Address src); | |
| 1406 void movw(Address dst, Register src); | |
| 1407 | |
| 1408 void movzbl(Register dst, Address src); | |
| 1409 void movzbl(Register dst, Register src); | |
| 1410 | |
| 624 | 1411 #ifdef _LP64 |
| 1412 void movzbq(Register dst, Address src); | |
| 1413 void movzbq(Register dst, Register src); | |
| 1414 #endif | |
| 1415 | |
| 304 | 1416 void movzwl(Register dst, Address src); |
| 1417 void movzwl(Register dst, Register src); | |
| 1418 | |
| 624 | 1419 #ifdef _LP64 |
| 1420 void movzwq(Register dst, Address src); | |
| 1421 void movzwq(Register dst, Register src); | |
| 1422 #endif | |
| 1423 | |
|
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1424 // Unsigned multiply with RAX destination register |
| 304 | 1425 void mull(Address src); |
| 1426 void mull(Register src); | |
| 1427 | |
|
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1428 #ifdef _LP64 |
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|
1429 void mulq(Address src); |
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1430 void mulq(Register src); |
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1431 void mulxq(Register dst1, Register dst2, Register src); |
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1432 #endif |
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|
1433 |
| 304 | 1434 // Multiply Scalar Double-Precision Floating-Point Values |
| 1435 void mulsd(XMMRegister dst, Address src); | |
| 1436 void mulsd(XMMRegister dst, XMMRegister src); | |
| 1437 | |
| 1438 // Multiply Scalar Single-Precision Floating-Point Values | |
| 1439 void mulss(XMMRegister dst, Address src); | |
| 1440 void mulss(XMMRegister dst, XMMRegister src); | |
| 1441 | |
| 1442 void negl(Register dst); | |
| 1443 | |
| 1444 #ifdef _LP64 | |
| 1445 void negq(Register dst); | |
| 1446 #endif | |
| 1447 | |
| 1448 void nop(int i = 1); | |
| 1449 | |
| 1450 void notl(Register dst); | |
| 1451 | |
| 1452 #ifdef _LP64 | |
| 1453 void notq(Register dst); | |
| 1454 #endif | |
| 1455 | |
| 1456 void orl(Address dst, int32_t imm32); | |
| 1457 void orl(Register dst, int32_t imm32); | |
| 1458 void orl(Register dst, Address src); | |
| 1459 void orl(Register dst, Register src); | |
| 1460 | |
| 1461 void orq(Address dst, int32_t imm32); | |
| 1462 void orq(Register dst, int32_t imm32); | |
| 1463 void orq(Register dst, Address src); | |
| 1464 void orq(Register dst, Register src); | |
| 1465 | |
| 4759 | 1466 // Pack with unsigned saturation |
| 1467 void packuswb(XMMRegister dst, XMMRegister src); | |
| 1468 void packuswb(XMMRegister dst, Address src); | |
|
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1469 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1470 |
|
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1471 // Pemutation of 64bit words |
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1472 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); |
| 4759 | 1473 |
| 17780 | 1474 void pause(); |
| 1475 | |
| 681 | 1476 // SSE4.2 string instructions |
| 1477 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
| 1478 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
| 1479 | |
|
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1480 // SSE 4.1 extract |
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1481 void pextrd(Register dst, XMMRegister src, int imm8); |
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1482 void pextrq(Register dst, XMMRegister src, int imm8); |
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1483 |
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1484 // SSE 4.1 insert |
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1485 void pinsrd(XMMRegister dst, Register src, int imm8); |
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1486 void pinsrq(XMMRegister dst, Register src, int imm8); |
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1487 |
| 4759 | 1488 // SSE4.1 packed move |
| 1489 void pmovzxbw(XMMRegister dst, XMMRegister src); | |
| 1490 void pmovzxbw(XMMRegister dst, Address src); | |
| 1491 | |
| 1060 | 1492 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 1493 void popl(Address dst); |
| 1060 | 1494 #endif |
| 304 | 1495 |
| 1496 #ifdef _LP64 | |
| 1497 void popq(Address dst); | |
| 1498 #endif | |
| 1499 | |
|
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1500 void popcntl(Register dst, Address src); |
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1501 void popcntl(Register dst, Register src); |
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1502 |
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1503 #ifdef _LP64 |
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1504 void popcntq(Register dst, Address src); |
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1505 void popcntq(Register dst, Register src); |
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1506 #endif |
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|
1507 |
| 304 | 1508 // Prefetches (SSE, SSE2, 3DNOW only) |
| 1509 | |
| 1510 void prefetchnta(Address src); | |
| 1511 void prefetchr(Address src); | |
| 1512 void prefetcht0(Address src); | |
| 1513 void prefetcht1(Address src); | |
| 1514 void prefetcht2(Address src); | |
| 1515 void prefetchw(Address src); | |
| 1516 | |
| 6894 | 1517 // Shuffle Bytes |
| 1518 void pshufb(XMMRegister dst, XMMRegister src); | |
| 1519 void pshufb(XMMRegister dst, Address src); | |
| 1520 | |
| 304 | 1521 // Shuffle Packed Doublewords |
| 1522 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
| 1523 void pshufd(XMMRegister dst, Address src, int mode); | |
| 1524 | |
| 1525 // Shuffle Packed Low Words | |
| 1526 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
| 1527 void pshuflw(XMMRegister dst, Address src, int mode); | |
| 1528 | |
|
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1529 // Shift Right by bytes Logical DoubleQuadword Immediate |
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1530 void psrldq(XMMRegister dst, int shift); |
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1531 |
|
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1532 // Logical Compare 128bit |
| 681 | 1533 void ptest(XMMRegister dst, XMMRegister src); |
| 1534 void ptest(XMMRegister dst, Address src); | |
|
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1535 // Logical Compare 256bit |
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1536 void vptest(XMMRegister dst, XMMRegister src); |
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1537 void vptest(XMMRegister dst, Address src); |
| 681 | 1538 |
| 304 | 1539 // Interleave Low Bytes |
| 1540 void punpcklbw(XMMRegister dst, XMMRegister src); | |
| 4759 | 1541 void punpcklbw(XMMRegister dst, Address src); |
| 1542 | |
| 1543 // Interleave Low Doublewords | |
| 1544 void punpckldq(XMMRegister dst, XMMRegister src); | |
| 1545 void punpckldq(XMMRegister dst, Address src); | |
| 304 | 1546 |
| 6225 | 1547 // Interleave Low Quadwords |
| 1548 void punpcklqdq(XMMRegister dst, XMMRegister src); | |
| 1549 | |
| 1060 | 1550 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 1551 void pushl(Address src); |
| 1060 | 1552 #endif |
| 304 | 1553 |
| 1554 void pushq(Address src); | |
| 1555 | |
| 1556 void rcll(Register dst, int imm8); | |
| 1557 | |
| 1558 void rclq(Register dst, int imm8); | |
| 1559 | |
| 17780 | 1560 void rdtsc(); |
| 1561 | |
| 304 | 1562 void ret(int imm16); |
| 0 | 1563 |
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1564 #ifdef _LP64 |
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1565 void rorq(Register dst, int imm8); |
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1566 void rorxq(Register dst, Register src, int imm8); |
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1567 #endif |
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|
1568 |
| 0 | 1569 void sahf(); |
| 1570 | |
| 304 | 1571 void sarl(Register dst, int imm8); |
| 1572 void sarl(Register dst); | |
| 1573 | |
| 1574 void sarq(Register dst, int imm8); | |
| 1575 void sarq(Register dst); | |
| 1576 | |
| 1577 void sbbl(Address dst, int32_t imm32); | |
| 1578 void sbbl(Register dst, int32_t imm32); | |
| 1579 void sbbl(Register dst, Address src); | |
| 1580 void sbbl(Register dst, Register src); | |
| 1581 | |
| 1582 void sbbq(Address dst, int32_t imm32); | |
| 1583 void sbbq(Register dst, int32_t imm32); | |
| 1584 void sbbq(Register dst, Address src); | |
| 1585 void sbbq(Register dst, Register src); | |
| 1586 | |
| 1587 void setb(Condition cc, Register dst); | |
| 1588 | |
| 1589 void shldl(Register dst, Register src); | |
| 1590 | |
| 1591 void shll(Register dst, int imm8); | |
| 1592 void shll(Register dst); | |
| 1593 | |
| 1594 void shlq(Register dst, int imm8); | |
| 1595 void shlq(Register dst); | |
| 1596 | |
| 1597 void shrdl(Register dst, Register src); | |
| 1598 | |
| 1599 void shrl(Register dst, int imm8); | |
| 1600 void shrl(Register dst); | |
| 1601 | |
| 1602 void shrq(Register dst, int imm8); | |
| 1603 void shrq(Register dst); | |
| 1604 | |
| 1605 void smovl(); // QQQ generic? | |
| 1606 | |
| 1607 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
| 1608 void sqrtsd(XMMRegister dst, Address src); | |
| 1609 void sqrtsd(XMMRegister dst, XMMRegister src); | |
| 1610 | |
| 2008 | 1611 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
| 1612 void sqrtss(XMMRegister dst, Address src); | |
| 1613 void sqrtss(XMMRegister dst, XMMRegister src); | |
| 1614 | |
|
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1615 void std(); |
| 304 | 1616 |
| 1617 void stmxcsr( Address dst ); | |
| 1618 | |
| 1619 void subl(Address dst, int32_t imm32); | |
| 1620 void subl(Address dst, Register src); | |
| 1621 void subl(Register dst, int32_t imm32); | |
| 1622 void subl(Register dst, Address src); | |
| 1623 void subl(Register dst, Register src); | |
| 1624 | |
| 1625 void subq(Address dst, int32_t imm32); | |
| 1626 void subq(Address dst, Register src); | |
| 1627 void subq(Register dst, int32_t imm32); | |
| 1628 void subq(Register dst, Address src); | |
| 1629 void subq(Register dst, Register src); | |
| 1630 | |
|
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1631 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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1632 void subl_imm32(Register dst, int32_t imm32); |
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1633 void subq_imm32(Register dst, int32_t imm32); |
| 304 | 1634 |
| 1635 // Subtract Scalar Double-Precision Floating-Point Values | |
| 1636 void subsd(XMMRegister dst, Address src); | |
| 0 | 1637 void subsd(XMMRegister dst, XMMRegister src); |
| 1638 | |
| 304 | 1639 // Subtract Scalar Single-Precision Floating-Point Values |
| 1640 void subss(XMMRegister dst, Address src); | |
| 1641 void subss(XMMRegister dst, XMMRegister src); | |
| 1642 | |
| 1643 void testb(Register dst, int imm8); | |
| 1644 | |
| 1645 void testl(Register dst, int32_t imm32); | |
| 1646 void testl(Register dst, Register src); | |
| 1647 void testl(Register dst, Address src); | |
| 1648 | |
| 1649 void testq(Register dst, int32_t imm32); | |
| 1650 void testq(Register dst, Register src); | |
| 1651 | |
|
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1652 // BMI - count trailing zeros |
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1653 void tzcntl(Register dst, Register src); |
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1654 void tzcntq(Register dst, Register src); |
| 304 | 1655 |
| 1656 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
| 1657 void ucomisd(XMMRegister dst, Address src); | |
| 0 | 1658 void ucomisd(XMMRegister dst, XMMRegister src); |
| 1659 | |
| 304 | 1660 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
| 1661 void ucomiss(XMMRegister dst, Address src); | |
| 1662 void ucomiss(XMMRegister dst, XMMRegister src); | |
| 1663 | |
| 17780 | 1664 void xabort(int8_t imm8); |
| 1665 | |
| 304 | 1666 void xaddl(Address dst, Register src); |
| 1667 | |
| 1668 void xaddq(Address dst, Register src); | |
| 1669 | |
| 17780 | 1670 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); |
| 1671 | |
| 304 | 1672 void xchgl(Register reg, Address adr); |
| 1673 void xchgl(Register dst, Register src); | |
| 1674 | |
| 1675 void xchgq(Register reg, Address adr); | |
| 1676 void xchgq(Register dst, Register src); | |
| 1677 | |
| 17780 | 1678 void xend(); |
| 1679 | |
| 4759 | 1680 // Get Value of Extended Control Register |
|
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1681 void xgetbv(); |
| 4759 | 1682 |
| 304 | 1683 void xorl(Register dst, int32_t imm32); |
| 1684 void xorl(Register dst, Address src); | |
| 1685 void xorl(Register dst, Register src); | |
| 1686 | |
| 1687 void xorq(Register dst, Address src); | |
| 1688 void xorq(Register dst, Register src); | |
| 1689 | |
| 1690 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
| 4759 | 1691 |
| 6225 | 1692 // AVX 3-operands scalar instructions (encoded with VEX prefix) |
|
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1693 |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
1694 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1695 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1696 void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1697 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1698 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1699 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1700 void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
1701 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1702 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
4759
diff
changeset
|
1703 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1704 void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
4759
diff
changeset
|
1705 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1706 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1707 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1708 void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1709 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
1710 |
|
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1711 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1712 //====================VECTOR ARITHMETIC===================================== |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1713 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1714 // Add Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1715 void addpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
1716 void addps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1717 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1718 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1719 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1720 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1721 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1722 // Subtract Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1723 void subpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1724 void subps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1725 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1726 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1727 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1728 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1729 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1730 // Multiply Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1731 void mulpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1732 void mulps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1733 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1734 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1735 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1736 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1737 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1738 // Divide Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1739 void divpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1740 void divps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1741 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1742 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1743 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1744 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1745 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1746 // Bitwise Logical AND of Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1747 void andpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1748 void andps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1749 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1750 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1751 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1752 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1753 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1754 // Bitwise Logical XOR of Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1755 void xorpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1756 void xorps(XMMRegister dst, XMMRegister src); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
1757 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
1758 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1759 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1760 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1761 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1762 // Add packed integers |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1763 void paddb(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1764 void paddw(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1765 void paddd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1766 void paddq(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1767 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1768 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1769 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1770 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1771 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1772 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1773 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1774 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1775 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1776 // Sub packed integers |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1777 void psubb(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1778 void psubw(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1779 void psubd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1780 void psubq(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1781 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1782 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1783 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1784 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1785 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1786 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1787 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1788 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1789 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1790 // Multiply packed integers (only shorts and ints) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1791 void pmullw(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1792 void pmulld(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1793 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1794 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1795 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1796 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1797 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1798 // Shift left packed integers |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
1799 void psllw(XMMRegister dst, int shift); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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changeset
|
1800 void pslld(XMMRegister dst, int shift); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
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changeset
|
1801 void psllq(XMMRegister dst, int shift); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
1802 void psllw(XMMRegister dst, XMMRegister shift); |
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1803 void pslld(XMMRegister dst, XMMRegister shift); |
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1804 void psllq(XMMRegister dst, XMMRegister shift); |
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1805 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1806 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1807 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1808 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1809 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1810 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1811 |
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1812 // Logical shift right packed integers |
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1813 void psrlw(XMMRegister dst, int shift); |
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1814 void psrld(XMMRegister dst, int shift); |
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1815 void psrlq(XMMRegister dst, int shift); |
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1816 void psrlw(XMMRegister dst, XMMRegister shift); |
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1817 void psrld(XMMRegister dst, XMMRegister shift); |
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1818 void psrlq(XMMRegister dst, XMMRegister shift); |
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1819 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1820 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1821 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1822 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1823 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1824 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1825 |
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1826 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) |
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1827 void psraw(XMMRegister dst, int shift); |
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1828 void psrad(XMMRegister dst, int shift); |
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1829 void psraw(XMMRegister dst, XMMRegister shift); |
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1830 void psrad(XMMRegister dst, XMMRegister shift); |
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1831 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1832 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
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1833 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1834 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
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1835 |
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1836 // And packed integers |
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1837 void pand(XMMRegister dst, XMMRegister src); |
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1838 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1839 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1840 |
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1841 // Or packed integers |
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1842 void por(XMMRegister dst, XMMRegister src); |
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1843 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1844 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1845 |
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1846 // Xor packed integers |
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1847 void pxor(XMMRegister dst, XMMRegister src); |
| 6225 | 1848 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
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1849 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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1850 |
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1851 // Copy low 128bit into high 128bit of YMM registers. |
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1852 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
| 6225 | 1853 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
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1854 |
|
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1855 // Load/store high 128bit of YMM registers which does not destroy other half. |
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1856 void vinsertf128h(XMMRegister dst, Address src); |
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1857 void vinserti128h(XMMRegister dst, Address src); |
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1858 void vextractf128h(Address dst, XMMRegister src); |
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1859 void vextracti128h(Address dst, XMMRegister src); |
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1860 |
|
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1861 // duplicate 4-bytes integer data from src into 8 locations in dest |
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1862 void vpbroadcastd(XMMRegister dst, XMMRegister src); |
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1863 |
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1864 // Carry-Less Multiplication Quadword |
|
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1865 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask); |
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1866 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); |
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1867 |
|
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1868 // AVX instruction which is used to clear upper 128 bits of YMM registers and |
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1869 // to avoid transaction penalty between AVX and SSE states. There is no |
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1870 // penalty if legacy SSE instructions are encoded using VEX prefix because |
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1871 // they always clear upper 128 bits. It should be used before calling |
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1872 // runtime code and native libraries. |
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1873 void vzeroupper(); |
|
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1874 |
| 4759 | 1875 protected: |
| 1876 // Next instructions require address alignment 16 bytes SSE mode. | |
| 1877 // They should be called only from corresponding MacroAssembler instructions. | |
| 1878 void andpd(XMMRegister dst, Address src); | |
| 1879 void andps(XMMRegister dst, Address src); | |
| 1880 void xorpd(XMMRegister dst, Address src); | |
| 1881 void xorps(XMMRegister dst, Address src); | |
| 1882 | |
| 0 | 1883 }; |
| 1884 | |
| 1972 | 1885 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |