Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 20804:7848fc12602b
Merge with jdk8u40-b25
| author | Gilles Duboscq <gilles.m.duboscq@oracle.com> |
|---|---|
| date | Tue, 07 Apr 2015 14:58:49 +0200 |
| parents | 52b4284cb496 166d744df0de |
| children |
| rev | line source |
|---|---|
| 585 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 585 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
| 26 #define CPU_X86_VM_VM_VERSION_X86_HPP | |
| 27 | |
| 28 #include "runtime/globals_extension.hpp" | |
| 29 #include "runtime/vm_version.hpp" | |
| 30 | |
| 585 | 31 class VM_Version : public Abstract_VM_Version { |
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32 friend class VMStructs; |
| 585 | 33 public: |
| 34 // cpuid result register layouts. These are all unions of a uint32_t | |
| 35 // (in case anyone wants access to the register as a whole) and a bitfield. | |
| 36 | |
| 37 union StdCpuid1Eax { | |
| 38 uint32_t value; | |
| 39 struct { | |
| 40 uint32_t stepping : 4, | |
| 41 model : 4, | |
| 42 family : 4, | |
| 43 proc_type : 2, | |
| 44 : 2, | |
| 45 ext_model : 4, | |
| 46 ext_family : 8, | |
| 47 : 4; | |
| 48 } bits; | |
| 49 }; | |
| 50 | |
| 51 union StdCpuid1Ebx { // example, unused | |
| 52 uint32_t value; | |
| 53 struct { | |
| 54 uint32_t brand_id : 8, | |
| 55 clflush_size : 8, | |
| 56 threads_per_cpu : 8, | |
| 57 apic_id : 8; | |
| 58 } bits; | |
| 59 }; | |
| 60 | |
| 61 union StdCpuid1Ecx { | |
| 62 uint32_t value; | |
| 63 struct { | |
| 64 uint32_t sse3 : 1, | |
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65 clmul : 1, |
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66 : 1, |
| 585 | 67 monitor : 1, |
| 68 : 1, | |
| 69 vmx : 1, | |
| 70 : 1, | |
| 71 est : 1, | |
| 72 : 1, | |
| 73 ssse3 : 1, | |
| 74 cid : 1, | |
| 75 : 2, | |
| 76 cmpxchg16: 1, | |
| 77 : 4, | |
| 78 dca : 1, | |
| 79 sse4_1 : 1, | |
| 80 sse4_2 : 1, | |
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81 : 2, |
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82 popcnt : 1, |
| 6894 | 83 : 1, |
| 84 aes : 1, | |
| 85 : 1, | |
| 4759 | 86 osxsave : 1, |
| 87 avx : 1, | |
| 88 : 3; | |
| 585 | 89 } bits; |
| 90 }; | |
| 91 | |
| 92 union StdCpuid1Edx { | |
| 93 uint32_t value; | |
| 94 struct { | |
| 95 uint32_t : 4, | |
| 96 tsc : 1, | |
| 97 : 3, | |
| 98 cmpxchg8 : 1, | |
| 99 : 6, | |
| 100 cmov : 1, | |
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101 : 3, |
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102 clflush : 1, |
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103 : 3, |
| 585 | 104 mmx : 1, |
| 105 fxsr : 1, | |
| 106 sse : 1, | |
| 107 sse2 : 1, | |
| 108 : 1, | |
| 109 ht : 1, | |
| 110 : 3; | |
| 111 } bits; | |
| 112 }; | |
| 113 | |
| 114 union DcpCpuid4Eax { | |
| 115 uint32_t value; | |
| 116 struct { | |
| 117 uint32_t cache_type : 5, | |
| 118 : 21, | |
| 119 cores_per_cpu : 6; | |
| 120 } bits; | |
| 121 }; | |
| 122 | |
| 123 union DcpCpuid4Ebx { | |
| 124 uint32_t value; | |
| 125 struct { | |
| 126 uint32_t L1_line_size : 12, | |
| 127 partitions : 10, | |
| 128 associativity : 10; | |
| 129 } bits; | |
| 130 }; | |
| 131 | |
| 1622 | 132 union TplCpuidBEbx { |
| 133 uint32_t value; | |
| 134 struct { | |
| 135 uint32_t logical_cpus : 16, | |
| 136 : 16; | |
| 137 } bits; | |
| 138 }; | |
| 139 | |
| 585 | 140 union ExtCpuid1Ecx { |
| 141 uint32_t value; | |
| 142 struct { | |
| 143 uint32_t LahfSahf : 1, | |
| 144 CmpLegacy : 1, | |
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145 : 3, |
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146 lzcnt_intel : 1, |
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147 lzcnt : 1, |
| 585 | 148 sse4a : 1, |
| 149 misalignsse : 1, | |
| 150 prefetchw : 1, | |
| 151 : 22; | |
| 152 } bits; | |
| 153 }; | |
| 154 | |
| 155 union ExtCpuid1Edx { | |
| 156 uint32_t value; | |
| 157 struct { | |
| 158 uint32_t : 22, | |
| 159 mmx_amd : 1, | |
| 160 mmx : 1, | |
| 161 fxsr : 1, | |
| 162 : 4, | |
| 163 long_mode : 1, | |
| 164 tdnow2 : 1, | |
| 165 tdnow : 1; | |
| 166 } bits; | |
| 167 }; | |
| 168 | |
| 169 union ExtCpuid5Ex { | |
| 170 uint32_t value; | |
| 171 struct { | |
| 172 uint32_t L1_line_size : 8, | |
| 173 L1_tag_lines : 8, | |
| 174 L1_assoc : 8, | |
| 175 L1_size : 8; | |
| 176 } bits; | |
| 177 }; | |
| 178 | |
| 4771 | 179 union ExtCpuid7Edx { |
| 180 uint32_t value; | |
| 181 struct { | |
| 182 uint32_t : 8, | |
| 183 tsc_invariance : 1, | |
| 184 : 23; | |
| 185 } bits; | |
| 186 }; | |
| 187 | |
| 585 | 188 union ExtCpuid8Ecx { |
| 189 uint32_t value; | |
| 190 struct { | |
| 191 uint32_t cores_per_cpu : 8, | |
| 192 : 24; | |
| 193 } bits; | |
| 194 }; | |
| 195 | |
| 4759 | 196 union SefCpuid7Eax { |
| 197 uint32_t value; | |
| 198 }; | |
| 199 | |
| 200 union SefCpuid7Ebx { | |
| 201 uint32_t value; | |
| 202 struct { | |
| 203 uint32_t fsgsbase : 1, | |
| 204 : 2, | |
| 205 bmi1 : 1, | |
| 206 : 1, | |
| 207 avx2 : 1, | |
| 208 : 2, | |
| 209 bmi2 : 1, | |
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210 erms : 1, |
| 17780 | 211 : 1, |
| 212 rtm : 1, | |
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213 : 7, |
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214 adx : 1, |
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215 : 12; |
| 4759 | 216 } bits; |
| 217 }; | |
| 218 | |
| 219 union XemXcr0Eax { | |
| 220 uint32_t value; | |
| 221 struct { | |
| 222 uint32_t x87 : 1, | |
| 223 sse : 1, | |
| 224 ymm : 1, | |
| 225 : 29; | |
| 226 } bits; | |
| 227 }; | |
| 228 | |
| 585 | 229 protected: |
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230 static int _cpu; |
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231 static int _model; |
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232 static int _stepping; |
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233 static int _cpuFeatures; // features returned by the "cpuid" instruction |
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234 // 0 if this instruction is not available |
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235 static const char* _features_str; |
| 585 | 236 |
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237 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV |
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238 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV |
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239 |
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240 enum { |
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241 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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242 CPU_CMOV = (1 << 1), |
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243 CPU_FXSR = (1 << 2), |
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244 CPU_HT = (1 << 3), |
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245 CPU_MMX = (1 << 4), |
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246 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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247 // may not necessarily support other 3dnow instructions |
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248 CPU_SSE = (1 << 6), |
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249 CPU_SSE2 = (1 << 7), |
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250 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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251 CPU_SSSE3 = (1 << 9), |
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252 CPU_SSE4A = (1 << 10), |
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253 CPU_SSE4_1 = (1 << 11), |
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254 CPU_SSE4_2 = (1 << 12), |
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255 CPU_POPCNT = (1 << 13), |
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256 CPU_LZCNT = (1 << 14), |
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257 CPU_TSC = (1 << 15), |
| 4771 | 258 CPU_TSCINV = (1 << 16), |
| 259 CPU_AVX = (1 << 17), | |
| 6894 | 260 CPU_AVX2 = (1 << 18), |
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261 CPU_AES = (1 << 19), |
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262 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions |
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263 CPU_CLMUL = (1 << 21), // carryless multiply for CRC |
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264 CPU_BMI1 = (1 << 22), |
| 17780 | 265 CPU_BMI2 = (1 << 23), |
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266 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions |
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267 CPU_ADX = (1 << 25) |
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268 } cpuFeatureFlags; |
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269 |
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270 enum { |
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271 // AMD |
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272 CPU_FAMILY_AMD_11H = 0x11, |
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273 // Intel |
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274 CPU_FAMILY_INTEL_CORE = 6, |
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275 CPU_MODEL_NEHALEM = 0x1e, |
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276 CPU_MODEL_NEHALEM_EP = 0x1a, |
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277 CPU_MODEL_NEHALEM_EX = 0x2e, |
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278 CPU_MODEL_WESTMERE = 0x25, |
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279 CPU_MODEL_WESTMERE_EP = 0x2c, |
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280 CPU_MODEL_WESTMERE_EX = 0x2f, |
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281 CPU_MODEL_SANDYBRIDGE = 0x2a, |
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282 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, |
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283 CPU_MODEL_IVYBRIDGE_EP = 0x3a, |
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284 CPU_MODEL_HASWELL_E3 = 0x3c, |
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285 CPU_MODEL_HASWELL_E7 = 0x3f, |
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286 CPU_MODEL_BROADWELL = 0x3d |
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287 } cpuExtendedFamily; |
| 585 | 288 |
| 289 // cpuid information block. All info derived from executing cpuid with | |
| 290 // various function numbers is stored here. Intel and AMD info is | |
| 291 // merged in this block: accessor methods disentangle it. | |
| 292 // | |
| 293 // The info block is laid out in subblocks of 4 dwords corresponding to | |
| 294 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
| 295 struct CpuidInfo { | |
| 296 // cpuid function 0 | |
| 297 uint32_t std_max_function; | |
| 298 uint32_t std_vendor_name_0; | |
| 299 uint32_t std_vendor_name_1; | |
| 300 uint32_t std_vendor_name_2; | |
| 301 | |
| 302 // cpuid function 1 | |
| 303 StdCpuid1Eax std_cpuid1_eax; | |
| 304 StdCpuid1Ebx std_cpuid1_ebx; | |
| 305 StdCpuid1Ecx std_cpuid1_ecx; | |
| 306 StdCpuid1Edx std_cpuid1_edx; | |
| 307 | |
| 308 // cpuid function 4 (deterministic cache parameters) | |
| 309 DcpCpuid4Eax dcp_cpuid4_eax; | |
| 310 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
| 311 uint32_t dcp_cpuid4_ecx; // unused currently | |
| 312 uint32_t dcp_cpuid4_edx; // unused currently | |
| 313 | |
| 4759 | 314 // cpuid function 7 (structured extended features) |
| 315 SefCpuid7Eax sef_cpuid7_eax; | |
| 316 SefCpuid7Ebx sef_cpuid7_ebx; | |
| 317 uint32_t sef_cpuid7_ecx; // unused currently | |
| 318 uint32_t sef_cpuid7_edx; // unused currently | |
| 319 | |
| 1622 | 320 // cpuid function 0xB (processor topology) |
| 321 // ecx = 0 | |
| 322 uint32_t tpl_cpuidB0_eax; | |
| 323 TplCpuidBEbx tpl_cpuidB0_ebx; | |
| 324 uint32_t tpl_cpuidB0_ecx; // unused currently | |
| 325 uint32_t tpl_cpuidB0_edx; // unused currently | |
| 326 | |
| 327 // ecx = 1 | |
| 328 uint32_t tpl_cpuidB1_eax; | |
| 329 TplCpuidBEbx tpl_cpuidB1_ebx; | |
| 330 uint32_t tpl_cpuidB1_ecx; // unused currently | |
| 331 uint32_t tpl_cpuidB1_edx; // unused currently | |
| 332 | |
| 333 // ecx = 2 | |
| 334 uint32_t tpl_cpuidB2_eax; | |
| 335 TplCpuidBEbx tpl_cpuidB2_ebx; | |
| 336 uint32_t tpl_cpuidB2_ecx; // unused currently | |
| 337 uint32_t tpl_cpuidB2_edx; // unused currently | |
| 338 | |
| 585 | 339 // cpuid function 0x80000000 // example, unused |
| 340 uint32_t ext_max_function; | |
| 341 uint32_t ext_vendor_name_0; | |
| 342 uint32_t ext_vendor_name_1; | |
| 343 uint32_t ext_vendor_name_2; | |
| 344 | |
| 345 // cpuid function 0x80000001 | |
| 346 uint32_t ext_cpuid1_eax; // reserved | |
| 347 uint32_t ext_cpuid1_ebx; // reserved | |
| 348 ExtCpuid1Ecx ext_cpuid1_ecx; | |
| 349 ExtCpuid1Edx ext_cpuid1_edx; | |
| 350 | |
| 351 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
| 352 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
| 353 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
| 354 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
| 355 | |
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356 // cpuid function 0x80000005 // AMD L1, Intel reserved |
| 585 | 357 uint32_t ext_cpuid5_eax; // unused currently |
| 358 uint32_t ext_cpuid5_ebx; // reserved | |
| 359 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
| 360 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
| 361 | |
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362 // cpuid function 0x80000007 |
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363 uint32_t ext_cpuid7_eax; // reserved |
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364 uint32_t ext_cpuid7_ebx; // reserved |
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365 uint32_t ext_cpuid7_ecx; // reserved |
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366 ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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367 |
| 585 | 368 // cpuid function 0x80000008 |
| 369 uint32_t ext_cpuid8_eax; // unused currently | |
| 370 uint32_t ext_cpuid8_ebx; // reserved | |
| 371 ExtCpuid8Ecx ext_cpuid8_ecx; | |
| 372 uint32_t ext_cpuid8_edx; // reserved | |
| 4759 | 373 |
| 374 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
| 375 XemXcr0Eax xem_xcr0_eax; | |
| 376 uint32_t xem_xcr0_edx; // reserved | |
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377 |
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378 // Space to save ymm registers after signal handle |
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379 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 |
| 585 | 380 }; |
| 381 | |
| 382 // The actual cpuid info block | |
| 383 static CpuidInfo _cpuid_info; | |
| 384 | |
| 385 // Extractors and predicates | |
| 386 static uint32_t extended_cpu_family() { | |
| 387 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
| 388 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
| 389 return result; | |
| 390 } | |
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391 |
| 585 | 392 static uint32_t extended_cpu_model() { |
| 393 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
| 394 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
| 395 return result; | |
| 396 } | |
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397 |
| 585 | 398 static uint32_t cpu_stepping() { |
| 399 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
| 400 return result; | |
| 401 } | |
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402 |
| 585 | 403 static uint logical_processor_count() { |
| 404 uint result = threads_per_core(); | |
| 405 return result; | |
| 406 } | |
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407 |
| 585 | 408 static uint32_t feature_flags() { |
| 409 uint32_t result = 0; | |
| 410 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
| 411 result |= CPU_CX8; | |
| 412 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
| 413 result |= CPU_CMOV; | |
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414 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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415 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
| 585 | 416 result |= CPU_FXSR; |
| 417 // HT flag is set for multi-core processors also. | |
| 418 if (threads_per_core() > 1) | |
| 419 result |= CPU_HT; | |
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420 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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421 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
| 585 | 422 result |= CPU_MMX; |
| 423 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
| 424 result |= CPU_SSE; | |
| 425 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
| 426 result |= CPU_SSE2; | |
| 427 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
| 428 result |= CPU_SSE3; | |
| 429 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
| 430 result |= CPU_SSSE3; | |
| 431 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
| 432 result |= CPU_SSE4_1; | |
| 433 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
| 434 result |= CPU_SSE4_2; | |
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435 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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436 result |= CPU_POPCNT; |
| 4759 | 437 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
| 438 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
| 439 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
| 440 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
| 441 result |= CPU_AVX; | |
| 442 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
| 443 result |= CPU_AVX2; | |
| 444 } | |
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445 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) |
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446 result |= CPU_BMI1; |
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447 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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448 result |= CPU_TSC; |
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449 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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450 result |= CPU_TSCINV; |
| 6894 | 451 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) |
| 452 result |= CPU_AES; | |
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453 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) |
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454 result |= CPU_ERMS; |
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455 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) |
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456 result |= CPU_CLMUL; |
| 17780 | 457 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) |
| 458 result |= CPU_RTM; | |
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459 |
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460 // AMD features. |
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461 if (is_amd()) { |
| 2479 | 462 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
| 463 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) | |
| 464 result |= CPU_3DNOW_PREFETCH; | |
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465 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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466 result |= CPU_LZCNT; |
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467 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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468 result |= CPU_SSE4A; |
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469 } |
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470 // Intel features. |
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471 if(is_intel()) { |
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472 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) |
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473 result |= CPU_ADX; |
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474 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) |
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475 result |= CPU_BMI2; |
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476 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) |
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477 result |= CPU_LZCNT; |
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478 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw |
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479 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { |
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480 result |= CPU_3DNOW_PREFETCH; |
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481 } |
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482 } |
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483 |
| 585 | 484 return result; |
| 485 } | |
| 486 | |
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487 static bool os_supports_avx_vectors() { |
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488 if (!supports_avx()) { |
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489 return false; |
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490 } |
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491 // Verify that OS save/restore all bits of AVX registers |
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492 // during signal processing. |
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493 int nreg = 2 LP64_ONLY(+2); |
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494 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register |
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495 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { |
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496 return false; |
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497 } |
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498 } |
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499 return true; |
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500 } |
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501 |
| 585 | 502 static void get_processor_features(); |
| 503 | |
| 504 public: | |
| 505 // Offsets for cpuid asm stub | |
| 506 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
| 507 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
| 508 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
| 4759 | 509 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
| 585 | 510 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
| 511 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
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512 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
| 585 | 513 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
| 1622 | 514 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
| 515 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
| 516 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
| 4759 | 517 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
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518 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } |
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519 |
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520 // The value used to check ymm register after signal handle |
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521 static int ymm_test_value() { return 0xCAFEBABE; } |
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522 |
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523 static void get_cpu_info_wrapper(); |
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524 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } |
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525 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } |
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526 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } |
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527 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } |
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528 |
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529 static void clean_cpuFeatures() { _cpuFeatures = 0; } |
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530 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } |
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531 |
| 585 | 532 |
| 533 // Initialization | |
| 534 static void initialize(); | |
| 535 | |
| 17780 | 536 // Override Abstract_VM_Version implementation |
| 537 static bool use_biased_locking(); | |
| 538 | |
| 585 | 539 // Asserts |
| 540 static void assert_is_initialized() { | |
| 541 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
| 542 } | |
| 543 | |
| 544 // | |
| 545 // Processor family: | |
| 546 // 3 - 386 | |
| 547 // 4 - 486 | |
| 548 // 5 - Pentium | |
| 549 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
| 550 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
| 551 // family 6 model: 9, 13, 14, 15 | |
| 552 // 0x0f - Pentium 4, Opteron | |
| 553 // | |
| 554 // Note: The cpu family should be used to select between | |
| 555 // instruction sequences which are valid on all Intel | |
| 556 // processors. Use the feature test functions below to | |
| 557 // determine whether a particular instruction is supported. | |
| 558 // | |
| 559 static int cpu_family() { return _cpu;} | |
| 560 static bool is_P6() { return cpu_family() >= 6; } | |
| 561 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
| 562 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
| 563 | |
| 1647 | 564 static bool supports_processor_topology() { |
| 565 return (_cpuid_info.std_max_function >= 0xB) && | |
| 566 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. | |
| 567 // Some cpus have max cpuid >= 0xB but do not support processor topology. | |
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568 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); |
| 1647 | 569 } |
| 570 | |
| 585 | 571 static uint cores_per_cpu() { |
| 572 uint result = 1; | |
| 573 if (is_intel()) { | |
| 1647 | 574 if (supports_processor_topology()) { |
| 1622 | 575 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
| 576 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
| 577 } else { | |
| 578 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
| 579 } | |
| 585 | 580 } else if (is_amd()) { |
| 581 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
| 582 } | |
| 583 return result; | |
| 584 } | |
| 585 | |
| 586 static uint threads_per_core() { | |
| 587 uint result = 1; | |
| 1647 | 588 if (is_intel() && supports_processor_topology()) { |
| 1622 | 589 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
| 590 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
| 585 | 591 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
| 592 cores_per_cpu(); | |
| 593 } | |
| 594 return result; | |
| 595 } | |
| 596 | |
| 3854 | 597 static intx prefetch_data_size() { |
| 585 | 598 intx result = 0; |
| 599 if (is_intel()) { | |
| 600 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
| 601 } else if (is_amd()) { | |
| 602 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
| 603 } | |
| 604 if (result < 32) // not defined ? | |
| 605 result = 32; // 32 bytes by default on x86 and other x64 | |
| 606 return result; | |
| 607 } | |
| 608 | |
| 609 // | |
| 610 // Feature identification | |
| 611 // | |
| 612 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
| 613 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
| 614 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
| 615 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
| 616 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
| 617 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
| 618 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
| 619 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
| 620 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
| 621 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
| 622 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
| 623 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
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624 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
| 4759 | 625 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
| 626 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
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627 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
| 6894 | 628 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } |
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629 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } |
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630 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } |
| 17780 | 631 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } |
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632 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } |
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633 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } |
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634 static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; } |
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635 // Intel features |
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636 static bool is_intel_family_core() { return is_intel() && |
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637 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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638 |
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639 static bool is_intel_tsc_synched_at_init() { |
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640 if (is_intel_family_core()) { |
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641 uint32_t ext_model = extended_cpu_model(); |
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642 if (ext_model == CPU_MODEL_NEHALEM_EP || |
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643 ext_model == CPU_MODEL_WESTMERE_EP || |
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644 ext_model == CPU_MODEL_SANDYBRIDGE_EP || |
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645 ext_model == CPU_MODEL_IVYBRIDGE_EP) { |
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646 // <= 2-socket invariant tsc support. EX versions are usually used |
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647 // in > 2-socket systems and likely don't synchronize tscs at |
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648 // initialization. |
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649 // Code that uses tsc values must be prepared for them to arbitrarily |
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650 // jump forward or backward. |
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651 return true; |
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652 } |
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653 } |
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654 return false; |
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655 } |
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656 |
| 585 | 657 // AMD features |
| 2479 | 658 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
| 585 | 659 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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660 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
| 585 | 661 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
| 662 | |
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663 static bool is_amd_Barcelona() { return is_amd() && |
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664 extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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665 |
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666 // Intel and AMD newer cores support fast timestamps well |
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667 static bool supports_tscinv_bit() { |
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668 return (_cpuFeatures & CPU_TSCINV) != 0; |
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669 } |
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670 static bool supports_tscinv() { |
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671 return supports_tscinv_bit() && |
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672 ( (is_amd() && !is_amd_Barcelona()) || |
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673 is_intel_tsc_synched_at_init() ); |
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674 } |
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675 |
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676 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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677 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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678 supports_sse3() && _model != 0x1C; } |
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679 |
| 585 | 680 static bool supports_compare_and_exchange() { return true; } |
| 681 | |
| 682 static const char* cpu_features() { return _features_str; } | |
| 683 | |
| 684 static intx allocate_prefetch_distance() { | |
| 685 // This method should be called before allocate_prefetch_style(). | |
| 686 // | |
| 687 // Hardware prefetching (distance/size in bytes): | |
| 688 // Pentium 3 - 64 / 32 | |
| 689 // Pentium 4 - 256 / 128 | |
| 690 // Athlon - 64 / 32 ???? | |
| 691 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
| 692 // Core - 128 / 64 | |
| 693 // | |
| 694 // Software prefetching (distance in bytes / instruction with best score): | |
| 695 // Pentium 3 - 128 / prefetchnta | |
| 696 // Pentium 4 - 512 / prefetchnta | |
| 697 // Athlon - 128 / prefetchnta | |
| 698 // Opteron - 256 / prefetchnta | |
| 699 // Core - 256 / prefetchnta | |
| 700 // It will be used only when AllocatePrefetchStyle > 0 | |
| 701 | |
| 702 intx count = AllocatePrefetchDistance; | |
| 703 if (count < 0) { // default ? | |
| 704 if (is_amd()) { // AMD | |
| 705 if (supports_sse2()) | |
| 706 count = 256; // Opteron | |
| 707 else | |
| 708 count = 128; // Athlon | |
| 709 } else { // Intel | |
| 710 if (supports_sse2()) | |
| 711 if (cpu_family() == 6) { | |
| 712 count = 256; // Pentium M, Core, Core2 | |
| 713 } else { | |
| 714 count = 512; // Pentium 4 | |
| 715 } | |
| 716 else | |
| 717 count = 128; // Pentium 3 (and all other old CPUs) | |
| 718 } | |
| 719 } | |
| 720 return count; | |
| 721 } | |
| 722 static intx allocate_prefetch_style() { | |
| 723 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
| 724 // Return 0 if AllocatePrefetchDistance was not defined. | |
| 725 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
| 726 } | |
| 727 | |
| 728 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
| 729 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
| 730 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
| 731 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
| 732 | |
| 733 // gc copy/scan is disabled if prefetchw isn't supported, because | |
| 734 // Prefetch::write emits an inlined prefetchw on Linux. | |
| 735 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
| 736 // The used prefetcht0 instruction works for both amd64 and em64t. | |
| 737 static intx prefetch_copy_interval_in_bytes() { | |
| 738 intx interval = PrefetchCopyIntervalInBytes; | |
| 739 return interval >= 0 ? interval : 576; | |
| 740 } | |
| 741 static intx prefetch_scan_interval_in_bytes() { | |
| 742 intx interval = PrefetchScanIntervalInBytes; | |
| 743 return interval >= 0 ? interval : 576; | |
| 744 } | |
| 745 static intx prefetch_fields_ahead() { | |
| 746 intx count = PrefetchFieldsAhead; | |
| 747 return count >= 0 ? count : 1; | |
| 748 } | |
| 749 }; | |
| 1972 | 750 |
| 751 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |