Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 2119:d4fca0a6abde
7011386: race in objArrayKlass::array_klass_impl
Summary: Move _lower_dimension field initialization before _higher_dimension and add storestore barrier.
Reviewed-by: dholmes, iveresov, never
author | kvn |
---|---|
date | Tue, 11 Jan 2011 20:26:13 -0800 |
parents | 4de5f4101cfd |
children | 06f017f7daa7 b1a2afa37ec4 |
rev | line source |
---|---|
0 | 1 /* |
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2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "assembler_x86.inline.hpp" | |
27 #include "gc_interface/collectedHeap.inline.hpp" | |
28 #include "interpreter/interpreter.hpp" | |
29 #include "memory/cardTableModRefBS.hpp" | |
30 #include "memory/resourceArea.hpp" | |
31 #include "prims/methodHandles.hpp" | |
32 #include "runtime/biasedLocking.hpp" | |
33 #include "runtime/interfaceSupport.hpp" | |
34 #include "runtime/objectMonitor.hpp" | |
35 #include "runtime/os.hpp" | |
36 #include "runtime/sharedRuntime.hpp" | |
37 #include "runtime/stubRoutines.hpp" | |
38 #ifndef SERIALGC | |
39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
41 #include "gc_implementation/g1/heapRegion.hpp" | |
42 #endif | |
0 | 43 |
44 // Implementation of AddressLiteral | |
45 | |
46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
47 _is_lval = false; | |
48 _target = target; | |
49 switch (rtype) { | |
50 case relocInfo::oop_type: | |
51 // Oops are a special case. Normally they would be their own section | |
52 // but in cases like icBuffer they are literals in the code stream that | |
53 // we don't have a section for. We use none so that we get a literal address | |
54 // which is always patchable. | |
55 break; | |
56 case relocInfo::external_word_type: | |
57 _rspec = external_word_Relocation::spec(target); | |
58 break; | |
59 case relocInfo::internal_word_type: | |
60 _rspec = internal_word_Relocation::spec(target); | |
61 break; | |
62 case relocInfo::opt_virtual_call_type: | |
63 _rspec = opt_virtual_call_Relocation::spec(); | |
64 break; | |
65 case relocInfo::static_call_type: | |
66 _rspec = static_call_Relocation::spec(); | |
67 break; | |
68 case relocInfo::runtime_call_type: | |
69 _rspec = runtime_call_Relocation::spec(); | |
70 break; | |
71 case relocInfo::poll_type: | |
72 case relocInfo::poll_return_type: | |
73 _rspec = Relocation::spec_simple(rtype); | |
74 break; | |
75 case relocInfo::none: | |
76 break; | |
77 default: | |
78 ShouldNotReachHere(); | |
79 break; | |
80 } | |
81 } | |
82 | |
83 // Implementation of Address | |
84 | |
304 | 85 #ifdef _LP64 |
86 | |
0 | 87 Address Address::make_array(ArrayAddress adr) { |
88 // Not implementable on 64bit machines | |
89 // Should have been handled higher up the call chain. | |
90 ShouldNotReachHere(); | |
304 | 91 return Address(); |
92 } | |
93 | |
94 // exceedingly dangerous constructor | |
95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
96 _base = noreg; | |
97 _index = noreg; | |
98 _scale = no_scale; | |
99 _disp = disp; | |
100 switch (rtype) { | |
101 case relocInfo::external_word_type: | |
102 _rspec = external_word_Relocation::spec(loc); | |
103 break; | |
104 case relocInfo::internal_word_type: | |
105 _rspec = internal_word_Relocation::spec(loc); | |
106 break; | |
107 case relocInfo::runtime_call_type: | |
108 // HMM | |
109 _rspec = runtime_call_Relocation::spec(); | |
110 break; | |
111 case relocInfo::poll_type: | |
112 case relocInfo::poll_return_type: | |
113 _rspec = Relocation::spec_simple(rtype); | |
114 break; | |
115 case relocInfo::none: | |
116 break; | |
117 default: | |
118 ShouldNotReachHere(); | |
119 } | |
120 } | |
121 #else // LP64 | |
122 | |
123 Address Address::make_array(ArrayAddress adr) { | |
0 | 124 AddressLiteral base = adr.base(); |
125 Address index = adr.index(); | |
126 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
128 array._rspec = base._rspec; | |
129 return array; | |
304 | 130 } |
0 | 131 |
132 // exceedingly dangerous constructor | |
133 Address::Address(address loc, RelocationHolder spec) { | |
134 _base = noreg; | |
135 _index = noreg; | |
136 _scale = no_scale; | |
137 _disp = (intptr_t) loc; | |
138 _rspec = spec; | |
139 } | |
304 | 140 |
0 | 141 #endif // _LP64 |
142 | |
304 | 143 |
144 | |
0 | 145 // Convert the raw encoding form into the form expected by the constructor for |
146 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
147 // that to noreg for the Address constructor. | |
624 | 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
149 RelocationHolder rspec; | |
150 if (disp_is_oop) { | |
151 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
152 } | |
0 | 153 bool valid_index = index != rsp->encoding(); |
154 if (valid_index) { | |
155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 156 madr._rspec = rspec; |
0 | 157 return madr; |
158 } else { | |
159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 160 madr._rspec = rspec; |
0 | 161 return madr; |
162 } | |
163 } | |
164 | |
165 // Implementation of Assembler | |
166 | |
167 int AbstractAssembler::code_fill_byte() { | |
168 return (u_char)'\xF4'; // hlt | |
169 } | |
170 | |
171 // make this go away someday | |
172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
173 if (rtype == relocInfo::none) | |
174 emit_long(data); | |
175 else emit_data(data, Relocation::spec_simple(rtype), format); | |
176 } | |
177 | |
178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 179 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
181 if (rspec.type() != relocInfo::none) { | |
182 #ifdef ASSERT | |
183 check_relocation(rspec, format); | |
184 #endif | |
185 // Do not use AbstractAssembler::relocate, which is not intended for | |
186 // embedded words. Instead, relocate to the enclosing instruction. | |
187 | |
188 // hack. call32 is too wide for mask so use disp32 | |
189 if (format == call32_operand) | |
190 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
191 else | |
192 code_section()->relocate(inst_mark(), rspec, format); | |
193 } | |
194 emit_long(data); | |
195 } | |
196 | |
304 | 197 static int encode(Register r) { |
198 int enc = r->encoding(); | |
199 if (enc >= 8) { | |
200 enc -= 8; | |
201 } | |
202 return enc; | |
203 } | |
204 | |
205 static int encode(XMMRegister r) { | |
206 int enc = r->encoding(); | |
207 if (enc >= 8) { | |
208 enc -= 8; | |
209 } | |
210 return enc; | |
211 } | |
0 | 212 |
213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
214 assert(dst->has_byte_register(), "must have byte register"); | |
215 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
216 assert(isByte(imm8), "not a byte"); | |
217 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
218 emit_byte(op1); | |
304 | 219 emit_byte(op2 | encode(dst)); |
0 | 220 emit_byte(imm8); |
221 } | |
222 | |
223 | |
304 | 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
226 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
228 if (is8bit(imm32)) { | |
229 emit_byte(op1 | 0x02); // set sign bit | |
304 | 230 emit_byte(op2 | encode(dst)); |
0 | 231 emit_byte(imm32 & 0xFF); |
232 } else { | |
233 emit_byte(op1); | |
304 | 234 emit_byte(op2 | encode(dst)); |
0 | 235 emit_long(imm32); |
236 } | |
237 } | |
238 | |
239 // immediate-to-memory forms | |
304 | 240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
243 if (is8bit(imm32)) { | |
244 emit_byte(op1 | 0x02); // set sign bit | |
304 | 245 emit_operand(rm, adr, 1); |
0 | 246 emit_byte(imm32 & 0xFF); |
247 } else { | |
248 emit_byte(op1); | |
304 | 249 emit_operand(rm, adr, 4); |
0 | 250 emit_long(imm32); |
251 } | |
252 } | |
253 | |
254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
304 | 255 LP64_ONLY(ShouldNotReachHere()); |
0 | 256 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
257 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
259 InstructionMark im(this); | |
260 emit_byte(op1); | |
304 | 261 emit_byte(op2 | encode(dst)); |
262 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
0 | 263 } |
264 | |
265 | |
266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
267 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
268 emit_byte(op1); | |
304 | 269 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
270 } | |
271 | |
272 | |
273 void Assembler::emit_operand(Register reg, Register base, Register index, | |
274 Address::ScaleFactor scale, int disp, | |
275 RelocationHolder const& rspec, | |
276 int rip_relative_correction) { | |
0 | 277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 278 |
279 // Encode the registers as needed in the fields they are used in | |
280 | |
281 int regenc = encode(reg) << 3; | |
282 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
283 int baseenc = base->is_valid() ? encode(base) : 0; | |
284 | |
0 | 285 if (base->is_valid()) { |
286 if (index->is_valid()) { | |
287 assert(scale != Address::no_scale, "inconsistent address"); | |
288 // [base + index*scale + disp] | |
304 | 289 if (disp == 0 && rtype == relocInfo::none && |
290 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 291 // [base + index*scale] |
292 // [00 reg 100][ss index base] | |
293 assert(index != rsp, "illegal addressing mode"); | |
304 | 294 emit_byte(0x04 | regenc); |
295 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 296 } else if (is8bit(disp) && rtype == relocInfo::none) { |
297 // [base + index*scale + imm8] | |
298 // [01 reg 100][ss index base] imm8 | |
299 assert(index != rsp, "illegal addressing mode"); | |
304 | 300 emit_byte(0x44 | regenc); |
301 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 302 emit_byte(disp & 0xFF); |
303 } else { | |
304 | 304 // [base + index*scale + disp32] |
305 // [10 reg 100][ss index base] disp32 | |
0 | 306 assert(index != rsp, "illegal addressing mode"); |
304 | 307 emit_byte(0x84 | regenc); |
308 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 309 emit_data(disp, rspec, disp32_operand); |
310 } | |
304 | 311 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
312 // [rsp + disp] | |
0 | 313 if (disp == 0 && rtype == relocInfo::none) { |
304 | 314 // [rsp] |
0 | 315 // [00 reg 100][00 100 100] |
304 | 316 emit_byte(0x04 | regenc); |
0 | 317 emit_byte(0x24); |
318 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
304 | 319 // [rsp + imm8] |
320 // [01 reg 100][00 100 100] disp8 | |
321 emit_byte(0x44 | regenc); | |
0 | 322 emit_byte(0x24); |
323 emit_byte(disp & 0xFF); | |
324 } else { | |
304 | 325 // [rsp + imm32] |
326 // [10 reg 100][00 100 100] disp32 | |
327 emit_byte(0x84 | regenc); | |
0 | 328 emit_byte(0x24); |
329 emit_data(disp, rspec, disp32_operand); | |
330 } | |
331 } else { | |
332 // [base + disp] | |
304 | 333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
334 if (disp == 0 && rtype == relocInfo::none && | |
335 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 336 // [base] |
337 // [00 reg base] | |
304 | 338 emit_byte(0x00 | regenc | baseenc); |
0 | 339 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 340 // [base + disp8] |
341 // [01 reg base] disp8 | |
342 emit_byte(0x40 | regenc | baseenc); | |
0 | 343 emit_byte(disp & 0xFF); |
344 } else { | |
304 | 345 // [base + disp32] |
346 // [10 reg base] disp32 | |
347 emit_byte(0x80 | regenc | baseenc); | |
0 | 348 emit_data(disp, rspec, disp32_operand); |
349 } | |
350 } | |
351 } else { | |
352 if (index->is_valid()) { | |
353 assert(scale != Address::no_scale, "inconsistent address"); | |
354 // [index*scale + disp] | |
304 | 355 // [00 reg 100][ss index 101] disp32 |
0 | 356 assert(index != rsp, "illegal addressing mode"); |
304 | 357 emit_byte(0x04 | regenc); |
358 emit_byte(scale << 6 | indexenc | 0x05); | |
0 | 359 emit_data(disp, rspec, disp32_operand); |
304 | 360 } else if (rtype != relocInfo::none ) { |
361 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
362 // [00 000 101] disp32 | |
363 | |
364 emit_byte(0x05 | regenc); | |
365 // Note that the RIP-rel. correction applies to the generated | |
366 // disp field, but _not_ to the target address in the rspec. | |
367 | |
368 // disp was created by converting the target address minus the pc | |
369 // at the start of the instruction. That needs more correction here. | |
370 // intptr_t disp = target - next_ip; | |
371 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
373 int64_t adjusted = disp; | |
374 // Do rip-rel adjustment for 64bit | |
375 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
376 assert(is_simm32(adjusted), | |
377 "must be 32bit offset (RIP relative address)"); | |
378 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
379 | |
0 | 380 } else { |
304 | 381 // 32bit never did this, did everything as the rip-rel/disp code above |
382 // [disp] ABSOLUTE | |
383 // [00 reg 100][00 100 101] disp32 | |
384 emit_byte(0x04 | regenc); | |
385 emit_byte(0x25); | |
0 | 386 emit_data(disp, rspec, disp32_operand); |
387 } | |
388 } | |
389 } | |
390 | |
304 | 391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
392 Address::ScaleFactor scale, int disp, | |
393 RelocationHolder const& rspec) { | |
394 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
395 } | |
396 | |
0 | 397 // Secret local extension to Assembler::WhichOperand: |
398 #define end_pc_operand (_WhichOperand_limit) | |
399 | |
400 address Assembler::locate_operand(address inst, WhichOperand which) { | |
401 // Decode the given instruction, and return the address of | |
402 // an embedded 32-bit operand word. | |
403 | |
404 // If "which" is disp32_operand, selects the displacement portion | |
405 // of an effective address specifier. | |
304 | 406 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 407 // If "which" is call32_operand, selects the displacement of a call or jump. |
408 // Caller is responsible for ensuring that there is such an operand, | |
304 | 409 // and that it is 32/64 bits wide. |
0 | 410 |
411 // If "which" is end_pc_operand, find the end of the instruction. | |
412 | |
413 address ip = inst; | |
304 | 414 bool is_64bit = false; |
415 | |
416 debug_only(bool has_disp32 = false); | |
417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
418 | |
419 again_after_prefix: | |
0 | 420 switch (0xFF & *ip++) { |
421 | |
422 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 425 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 426 #define REP16(x) REP8((x)+0): \ |
0 | 427 case REP8((x)+8) |
428 | |
429 case CS_segment: | |
430 case SS_segment: | |
431 case DS_segment: | |
432 case ES_segment: | |
433 case FS_segment: | |
434 case GS_segment: | |
304 | 435 // Seems dubious |
436 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 437 assert(ip == inst+1, "only one prefix allowed"); |
438 goto again_after_prefix; | |
439 | |
304 | 440 case 0x67: |
441 case REX: | |
442 case REX_B: | |
443 case REX_X: | |
444 case REX_XB: | |
445 case REX_R: | |
446 case REX_RB: | |
447 case REX_RX: | |
448 case REX_RXB: | |
449 NOT_LP64(assert(false, "64bit prefixes")); | |
450 goto again_after_prefix; | |
451 | |
452 case REX_W: | |
453 case REX_WB: | |
454 case REX_WX: | |
455 case REX_WXB: | |
456 case REX_WR: | |
457 case REX_WRB: | |
458 case REX_WRX: | |
459 case REX_WRXB: | |
460 NOT_LP64(assert(false, "64bit prefixes")); | |
461 is_64bit = true; | |
462 goto again_after_prefix; | |
463 | |
464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 465 case 0x88: // movb a, r |
466 case 0x89: // movl a, r | |
467 case 0x8A: // movb r, a | |
468 case 0x8B: // movl r, a | |
469 case 0x8F: // popl a | |
304 | 470 debug_only(has_disp32 = true); |
0 | 471 break; |
472 | |
304 | 473 case 0x68: // pushq #32 |
474 if (which == end_pc_operand) { | |
475 return ip + 4; | |
476 } | |
477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 478 return ip; // not produced by emit_operand |
479 | |
480 case 0x66: // movw ... (size prefix) | |
304 | 481 again_after_size_prefix2: |
0 | 482 switch (0xFF & *ip++) { |
304 | 483 case REX: |
484 case REX_B: | |
485 case REX_X: | |
486 case REX_XB: | |
487 case REX_R: | |
488 case REX_RB: | |
489 case REX_RX: | |
490 case REX_RXB: | |
491 case REX_W: | |
492 case REX_WB: | |
493 case REX_WX: | |
494 case REX_WXB: | |
495 case REX_WR: | |
496 case REX_WRB: | |
497 case REX_WRX: | |
498 case REX_WRXB: | |
499 NOT_LP64(assert(false, "64bit prefix found")); | |
500 goto again_after_size_prefix2; | |
0 | 501 case 0x8B: // movw r, a |
502 case 0x89: // movw a, r | |
304 | 503 debug_only(has_disp32 = true); |
0 | 504 break; |
505 case 0xC7: // movw a, #16 | |
304 | 506 debug_only(has_disp32 = true); |
0 | 507 tail_size = 2; // the imm16 |
508 break; | |
509 case 0x0F: // several SSE/SSE2 variants | |
510 ip--; // reparse the 0x0F | |
511 goto again_after_prefix; | |
512 default: | |
513 ShouldNotReachHere(); | |
514 } | |
515 break; | |
516 | |
304 | 517 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
519 // these asserts are somewhat nonsensical | |
520 #ifndef _LP64 | |
521 assert(which == imm_operand || which == disp32_operand, ""); | |
522 #else | |
523 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
524 which == narrow_oop_operand && !is_64bit, ""); | |
525 #endif // _LP64 | |
0 | 526 return ip; |
527 | |
528 case 0x69: // imul r, a, #32 | |
529 case 0xC7: // movl a, #32(oop?) | |
530 tail_size = 4; | |
304 | 531 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 532 break; |
533 | |
534 case 0x0F: // movx..., etc. | |
535 switch (0xFF & *ip++) { | |
536 case 0x12: // movlps | |
537 case 0x28: // movaps | |
538 case 0x2E: // ucomiss | |
539 case 0x2F: // comiss | |
540 case 0x54: // andps | |
541 case 0x55: // andnps | |
542 case 0x56: // orps | |
543 case 0x57: // xorps | |
544 case 0x6E: // movd | |
545 case 0x7E: // movd | |
546 case 0xAE: // ldmxcsr a | |
304 | 547 // 64bit side says it these have both operands but that doesn't |
548 // appear to be true | |
549 debug_only(has_disp32 = true); | |
0 | 550 break; |
551 | |
552 case 0xAD: // shrd r, a, %cl | |
553 case 0xAF: // imul r, a | |
304 | 554 case 0xBE: // movsbl r, a (movsxb) |
555 case 0xBF: // movswl r, a (movsxw) | |
556 case 0xB6: // movzbl r, a (movzxb) | |
557 case 0xB7: // movzwl r, a (movzxw) | |
0 | 558 case REP16(0x40): // cmovl cc, r, a |
559 case 0xB0: // cmpxchgb | |
560 case 0xB1: // cmpxchg | |
561 case 0xC1: // xaddl | |
562 case 0xC7: // cmpxchg8 | |
563 case REP16(0x90): // setcc a | |
304 | 564 debug_only(has_disp32 = true); |
0 | 565 // fall out of the switch to decode the address |
566 break; | |
304 | 567 |
0 | 568 case 0xAC: // shrd r, a, #8 |
304 | 569 debug_only(has_disp32 = true); |
0 | 570 tail_size = 1; // the imm8 |
571 break; | |
304 | 572 |
0 | 573 case REP16(0x80): // jcc rdisp32 |
574 if (which == end_pc_operand) return ip + 4; | |
304 | 575 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 576 return ip; |
577 default: | |
578 ShouldNotReachHere(); | |
579 } | |
580 break; | |
581 | |
582 case 0x81: // addl a, #32; addl r, #32 | |
583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 584 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 585 tail_size = 4; |
304 | 586 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 587 break; |
588 | |
589 case 0x83: // addl a, #8; addl r, #8 | |
590 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 591 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 592 tail_size = 1; |
593 break; | |
594 | |
595 case 0x9B: | |
596 switch (0xFF & *ip++) { | |
597 case 0xD9: // fnstcw a | |
304 | 598 debug_only(has_disp32 = true); |
0 | 599 break; |
600 default: | |
601 ShouldNotReachHere(); | |
602 } | |
603 break; | |
604 | |
605 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
606 case REP4(0x10): // adc... | |
607 case REP4(0x20): // and... | |
608 case REP4(0x30): // xor... | |
609 case REP4(0x08): // or... | |
610 case REP4(0x18): // sbb... | |
611 case REP4(0x28): // sub... | |
304 | 612 case 0xF7: // mull a |
613 case 0x8D: // lea r, a | |
614 case 0x87: // xchg r, a | |
0 | 615 case REP4(0x38): // cmp... |
304 | 616 case 0x85: // test r, a |
617 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 618 break; |
619 | |
620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
621 case 0xC6: // movb a, #8 | |
622 case 0x80: // cmpb a, #8 | |
623 case 0x6B: // imul r, a, #8 | |
304 | 624 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 625 tail_size = 1; // the imm8 |
626 break; | |
627 | |
628 case 0xE8: // call rdisp32 | |
629 case 0xE9: // jmp rdisp32 | |
630 if (which == end_pc_operand) return ip + 4; | |
304 | 631 assert(which == call32_operand, "call has no disp32 or imm"); |
0 | 632 return ip; |
633 | |
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
637 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
639 case 0xDF: // fild_d a; fistp_d a | |
640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 643 debug_only(has_disp32 = true); |
0 | 644 break; |
645 | |
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646 case 0xF0: // Lock |
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647 assert(os::is_MP(), "only on MP"); |
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648 goto again_after_prefix; |
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649 |
0 | 650 case 0xF3: // For SSE |
651 case 0xF2: // For SSE2 | |
304 | 652 switch (0xFF & *ip++) { |
653 case REX: | |
654 case REX_B: | |
655 case REX_X: | |
656 case REX_XB: | |
657 case REX_R: | |
658 case REX_RB: | |
659 case REX_RX: | |
660 case REX_RXB: | |
661 case REX_W: | |
662 case REX_WB: | |
663 case REX_WX: | |
664 case REX_WXB: | |
665 case REX_WR: | |
666 case REX_WRB: | |
667 case REX_WRX: | |
668 case REX_WRXB: | |
669 NOT_LP64(assert(false, "found 64bit prefix")); | |
670 ip++; | |
671 default: | |
672 ip++; | |
673 } | |
674 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 675 break; |
676 | |
677 default: | |
678 ShouldNotReachHere(); | |
679 | |
304 | 680 #undef REP8 |
681 #undef REP16 | |
0 | 682 } |
683 | |
684 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 685 #ifdef _LP64 |
686 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
687 #else | |
688 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
689 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
690 #endif // LP64 | |
691 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 692 |
693 // parse the output of emit_operand | |
694 int op2 = 0xFF & *ip++; | |
695 int base = op2 & 0x07; | |
696 int op3 = -1; | |
697 const int b100 = 4; | |
698 const int b101 = 5; | |
699 if (base == b100 && (op2 >> 6) != 3) { | |
700 op3 = 0xFF & *ip++; | |
701 base = op3 & 0x07; // refetch the base | |
702 } | |
703 // now ip points at the disp (if any) | |
704 | |
705 switch (op2 >> 6) { | |
706 case 0: | |
707 // [00 reg 100][ss index base] | |
304 | 708 // [00 reg 100][00 100 esp] |
0 | 709 // [00 reg base] |
710 // [00 reg 100][ss index 101][disp32] | |
711 // [00 reg 101] [disp32] | |
712 | |
713 if (base == b101) { | |
714 if (which == disp32_operand) | |
715 return ip; // caller wants the disp32 | |
716 ip += 4; // skip the disp32 | |
717 } | |
718 break; | |
719 | |
720 case 1: | |
721 // [01 reg 100][ss index base][disp8] | |
304 | 722 // [01 reg 100][00 100 esp][disp8] |
0 | 723 // [01 reg base] [disp8] |
724 ip += 1; // skip the disp8 | |
725 break; | |
726 | |
727 case 2: | |
728 // [10 reg 100][ss index base][disp32] | |
304 | 729 // [10 reg 100][00 100 esp][disp32] |
0 | 730 // [10 reg base] [disp32] |
731 if (which == disp32_operand) | |
732 return ip; // caller wants the disp32 | |
733 ip += 4; // skip the disp32 | |
734 break; | |
735 | |
736 case 3: | |
737 // [11 reg base] (not a memory addressing mode) | |
738 break; | |
739 } | |
740 | |
741 if (which == end_pc_operand) { | |
742 return ip + tail_size; | |
743 } | |
744 | |
304 | 745 #ifdef _LP64 |
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746 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 747 #else |
748 assert(which == imm_operand, "instruction has only an imm field"); | |
749 #endif // LP64 | |
0 | 750 return ip; |
751 } | |
752 | |
753 address Assembler::locate_next_instruction(address inst) { | |
754 // Secretly share code with locate_operand: | |
755 return locate_operand(inst, end_pc_operand); | |
756 } | |
757 | |
758 | |
759 #ifdef ASSERT | |
760 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
761 address inst = inst_mark(); | |
762 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
763 address opnd; | |
764 | |
765 Relocation* r = rspec.reloc(); | |
766 if (r->type() == relocInfo::none) { | |
767 return; | |
768 } else if (r->is_call() || format == call32_operand) { | |
769 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
770 opnd = locate_operand(inst, call32_operand); | |
771 } else if (r->is_data()) { | |
304 | 772 assert(format == imm_operand || format == disp32_operand |
773 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 774 opnd = locate_operand(inst, (WhichOperand)format); |
775 } else { | |
304 | 776 assert(format == imm_operand, "cannot specify a format"); |
0 | 777 return; |
778 } | |
779 assert(opnd == pc(), "must put operand where relocs can find it"); | |
780 } | |
304 | 781 #endif // ASSERT |
782 | |
783 void Assembler::emit_operand32(Register reg, Address adr) { | |
784 assert(reg->encoding() < 8, "no extended registers"); | |
785 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
786 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
787 adr._rspec); | |
788 } | |
789 | |
790 void Assembler::emit_operand(Register reg, Address adr, | |
791 int rip_relative_correction) { | |
792 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
793 adr._rspec, | |
794 rip_relative_correction); | |
795 } | |
796 | |
797 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
798 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
799 adr._rspec); | |
800 } | |
801 | |
802 // MMX operations | |
803 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
804 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
805 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
806 } | |
807 | |
808 // work around gcc (3.2.1-7a) bug | |
809 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
810 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
811 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 812 } |
813 | |
814 | |
815 void Assembler::emit_farith(int b1, int b2, int i) { | |
816 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
817 assert(0 <= i && i < 8, "illegal stack offset"); | |
818 emit_byte(b1); | |
819 emit_byte(b2 + i); | |
820 } | |
821 | |
822 | |
304 | 823 // Now the Assembler instruction (identical for 32/64 bits) |
824 | |
825 void Assembler::adcl(Register dst, int32_t imm32) { | |
826 prefix(dst); | |
0 | 827 emit_arith(0x81, 0xD0, dst, imm32); |
828 } | |
829 | |
830 void Assembler::adcl(Register dst, Address src) { | |
831 InstructionMark im(this); | |
304 | 832 prefix(src, dst); |
0 | 833 emit_byte(0x13); |
834 emit_operand(dst, src); | |
835 } | |
836 | |
837 void Assembler::adcl(Register dst, Register src) { | |
304 | 838 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 839 emit_arith(0x13, 0xC0, dst, src); |
840 } | |
841 | |
304 | 842 void Assembler::addl(Address dst, int32_t imm32) { |
843 InstructionMark im(this); | |
844 prefix(dst); | |
845 emit_arith_operand(0x81, rax, dst, imm32); | |
846 } | |
0 | 847 |
848 void Assembler::addl(Address dst, Register src) { | |
849 InstructionMark im(this); | |
304 | 850 prefix(dst, src); |
0 | 851 emit_byte(0x01); |
852 emit_operand(src, dst); | |
853 } | |
854 | |
304 | 855 void Assembler::addl(Register dst, int32_t imm32) { |
856 prefix(dst); | |
0 | 857 emit_arith(0x81, 0xC0, dst, imm32); |
858 } | |
859 | |
860 void Assembler::addl(Register dst, Address src) { | |
861 InstructionMark im(this); | |
304 | 862 prefix(src, dst); |
0 | 863 emit_byte(0x03); |
864 emit_operand(dst, src); | |
865 } | |
866 | |
867 void Assembler::addl(Register dst, Register src) { | |
304 | 868 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 869 emit_arith(0x03, 0xC0, dst, src); |
870 } | |
871 | |
872 void Assembler::addr_nop_4() { | |
873 // 4 bytes: NOP DWORD PTR [EAX+0] | |
874 emit_byte(0x0F); | |
875 emit_byte(0x1F); | |
876 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
877 emit_byte(0); // 8-bits offset (1 byte) | |
878 } | |
879 | |
880 void Assembler::addr_nop_5() { | |
881 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
882 emit_byte(0x0F); | |
883 emit_byte(0x1F); | |
884 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
885 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
886 emit_byte(0); // 8-bits offset (1 byte) | |
887 } | |
888 | |
889 void Assembler::addr_nop_7() { | |
890 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
891 emit_byte(0x0F); | |
892 emit_byte(0x1F); | |
893 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
894 emit_long(0); // 32-bits offset (4 bytes) | |
895 } | |
896 | |
897 void Assembler::addr_nop_8() { | |
898 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
899 emit_byte(0x0F); | |
900 emit_byte(0x1F); | |
901 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
902 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
903 emit_long(0); // 32-bits offset (4 bytes) | |
904 } | |
905 | |
304 | 906 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
908 emit_byte(0xF2); | |
909 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
910 emit_byte(0x0F); | |
911 emit_byte(0x58); | |
912 emit_byte(0xC0 | encode); | |
913 } | |
914 | |
915 void Assembler::addsd(XMMRegister dst, Address src) { | |
916 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
917 InstructionMark im(this); | |
918 emit_byte(0xF2); | |
919 prefix(src, dst); | |
920 emit_byte(0x0F); | |
921 emit_byte(0x58); | |
922 emit_operand(dst, src); | |
923 } | |
924 | |
925 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
926 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
927 emit_byte(0xF3); | |
928 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
929 emit_byte(0x0F); | |
930 emit_byte(0x58); | |
931 emit_byte(0xC0 | encode); | |
932 } | |
933 | |
934 void Assembler::addss(XMMRegister dst, Address src) { | |
935 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
936 InstructionMark im(this); | |
937 emit_byte(0xF3); | |
938 prefix(src, dst); | |
939 emit_byte(0x0F); | |
940 emit_byte(0x58); | |
941 emit_operand(dst, src); | |
942 } | |
943 | |
944 void Assembler::andl(Register dst, int32_t imm32) { | |
945 prefix(dst); | |
946 emit_arith(0x81, 0xE0, dst, imm32); | |
947 } | |
948 | |
949 void Assembler::andl(Register dst, Address src) { | |
950 InstructionMark im(this); | |
951 prefix(src, dst); | |
952 emit_byte(0x23); | |
953 emit_operand(dst, src); | |
954 } | |
955 | |
956 void Assembler::andl(Register dst, Register src) { | |
957 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
958 emit_arith(0x23, 0xC0, dst, src); | |
959 } | |
960 | |
961 void Assembler::andpd(XMMRegister dst, Address src) { | |
962 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
963 InstructionMark im(this); | |
964 emit_byte(0x66); | |
965 prefix(src, dst); | |
966 emit_byte(0x0F); | |
967 emit_byte(0x54); | |
968 emit_operand(dst, src); | |
969 } | |
970 | |
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971 void Assembler::bsfl(Register dst, Register src) { |
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972 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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973 emit_byte(0x0F); |
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974 emit_byte(0xBC); |
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975 emit_byte(0xC0 | encode); |
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976 } |
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977 |
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978 void Assembler::bsrl(Register dst, Register src) { |
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979 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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980 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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981 emit_byte(0x0F); |
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982 emit_byte(0xBD); |
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983 emit_byte(0xC0 | encode); |
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984 } |
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985 |
304 | 986 void Assembler::bswapl(Register reg) { // bswap |
987 int encode = prefix_and_encode(reg->encoding()); | |
988 emit_byte(0x0F); | |
989 emit_byte(0xC8 | encode); | |
990 } | |
991 | |
992 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
993 // suspect disp32 is always good | |
994 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
995 | |
996 if (L.is_bound()) { | |
997 const int long_size = 5; | |
998 int offs = (int)( target(L) - pc() ); | |
999 assert(offs <= 0, "assembler error"); | |
1000 InstructionMark im(this); | |
1001 // 1110 1000 #32-bit disp | |
1002 emit_byte(0xE8); | |
1003 emit_data(offs - long_size, rtype, operand); | |
1004 } else { | |
1005 InstructionMark im(this); | |
1006 // 1110 1000 #32-bit disp | |
1007 L.add_patch_at(code(), locator()); | |
1008 | |
1009 emit_byte(0xE8); | |
1010 emit_data(int(0), rtype, operand); | |
1011 } | |
1012 } | |
1013 | |
1014 void Assembler::call(Register dst) { | |
1015 // This was originally using a 32bit register encoding | |
1016 // and surely we want 64bit! | |
1017 // this is a 32bit encoding but in 64bit mode the default | |
1018 // operand size is 64bit so there is no need for the | |
1019 // wide prefix. So prefix only happens if we use the | |
1020 // new registers. Much like push/pop. | |
1021 int x = offset(); | |
1022 // this may be true but dbx disassembles it as if it | |
1023 // were 32bits... | |
1024 // int encode = prefix_and_encode(dst->encoding()); | |
1025 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
1026 int encode = prefixq_and_encode(dst->encoding()); | |
1027 | |
1028 emit_byte(0xFF); | |
1029 emit_byte(0xD0 | encode); | |
1030 } | |
1031 | |
1032 | |
1033 void Assembler::call(Address adr) { | |
1034 InstructionMark im(this); | |
1035 prefix(adr); | |
1036 emit_byte(0xFF); | |
1037 emit_operand(rdx, adr); | |
1038 } | |
1039 | |
1040 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1041 assert(entry != NULL, "call most probably wrong"); | |
1042 InstructionMark im(this); | |
1043 emit_byte(0xE8); | |
1044 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
1045 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
1046 // Technically, should use call32_operand, but this format is | |
1047 // implied by the fact that we're emitting a call instruction. | |
1048 | |
1049 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1050 emit_data((int) disp, rspec, operand); | |
1051 } | |
1052 | |
1053 void Assembler::cdql() { | |
1054 emit_byte(0x99); | |
1055 } | |
1056 | |
1057 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
1058 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1059 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1060 emit_byte(0x0F); | |
1061 emit_byte(0x40 | cc); | |
1062 emit_byte(0xC0 | encode); | |
1063 } | |
1064 | |
1065 | |
1066 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1067 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1068 prefix(src, dst); | |
1069 emit_byte(0x0F); | |
1070 emit_byte(0x40 | cc); | |
1071 emit_operand(dst, src); | |
1072 } | |
1073 | |
1074 void Assembler::cmpb(Address dst, int imm8) { | |
1075 InstructionMark im(this); | |
1076 prefix(dst); | |
1077 emit_byte(0x80); | |
1078 emit_operand(rdi, dst, 1); | |
1079 emit_byte(imm8); | |
1080 } | |
1081 | |
1082 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1083 InstructionMark im(this); | |
1084 prefix(dst); | |
1085 emit_byte(0x81); | |
1086 emit_operand(rdi, dst, 4); | |
1087 emit_long(imm32); | |
1088 } | |
1089 | |
1090 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1091 prefix(dst); | |
1092 emit_arith(0x81, 0xF8, dst, imm32); | |
1093 } | |
1094 | |
1095 void Assembler::cmpl(Register dst, Register src) { | |
1096 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1097 emit_arith(0x3B, 0xC0, dst, src); | |
1098 } | |
1099 | |
1100 | |
1101 void Assembler::cmpl(Register dst, Address src) { | |
1102 InstructionMark im(this); | |
1103 prefix(src, dst); | |
1104 emit_byte(0x3B); | |
1105 emit_operand(dst, src); | |
1106 } | |
1107 | |
1108 void Assembler::cmpw(Address dst, int imm16) { | |
1109 InstructionMark im(this); | |
1110 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
1111 emit_byte(0x66); | |
1112 emit_byte(0x81); | |
1113 emit_operand(rdi, dst, 2); | |
1114 emit_word(imm16); | |
1115 } | |
1116 | |
1117 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1118 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1119 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1120 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
1121 if (Atomics & 2) { | |
1122 // caveat: no instructionmark, so this isn't relocatable. | |
1123 // Emit a synthetic, non-atomic, CAS equivalent. | |
1124 // Beware. The synthetic form sets all ICCs, not just ZF. | |
1125 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
1126 cmpl(rax, adr); | |
1127 movl(rax, adr); | |
1128 if (reg != rax) { | |
1129 Label L ; | |
1130 jcc(Assembler::notEqual, L); | |
1131 movl(adr, reg); | |
1132 bind(L); | |
1133 } | |
1134 } else { | |
1135 InstructionMark im(this); | |
1136 prefix(adr, reg); | |
1137 emit_byte(0x0F); | |
1138 emit_byte(0xB1); | |
1139 emit_operand(reg, adr); | |
1140 } | |
1141 } | |
1142 | |
1143 void Assembler::comisd(XMMRegister dst, Address src) { | |
1144 // NOTE: dbx seems to decode this as comiss even though the | |
1145 // 0x66 is there. Strangly ucomisd comes out correct | |
1146 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1147 emit_byte(0x66); | |
1148 comiss(dst, src); | |
1149 } | |
1150 | |
1151 void Assembler::comiss(XMMRegister dst, Address src) { | |
1152 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1153 | |
1154 InstructionMark im(this); | |
1155 prefix(src, dst); | |
1156 emit_byte(0x0F); | |
1157 emit_byte(0x2F); | |
1158 emit_operand(dst, src); | |
1159 } | |
1160 | |
1161 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
1162 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1163 emit_byte(0xF3); | |
1164 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1165 emit_byte(0x0F); | |
1166 emit_byte(0xE6); | |
1167 emit_byte(0xC0 | encode); | |
1168 } | |
1169 | |
1170 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1171 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1172 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1173 emit_byte(0x0F); | |
1174 emit_byte(0x5B); | |
1175 emit_byte(0xC0 | encode); | |
1176 } | |
1177 | |
1178 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1179 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1180 emit_byte(0xF2); | |
1181 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1182 emit_byte(0x0F); | |
1183 emit_byte(0x5A); | |
1184 emit_byte(0xC0 | encode); | |
1185 } | |
1186 | |
1187 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
1188 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1189 emit_byte(0xF2); | |
1190 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1191 emit_byte(0x0F); | |
1192 emit_byte(0x2A); | |
1193 emit_byte(0xC0 | encode); | |
1194 } | |
1195 | |
1196 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
1197 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1198 emit_byte(0xF3); | |
1199 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1200 emit_byte(0x0F); | |
1201 emit_byte(0x2A); | |
1202 emit_byte(0xC0 | encode); | |
1203 } | |
1204 | |
1205 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
1206 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1207 emit_byte(0xF3); | |
1208 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1209 emit_byte(0x0F); | |
1210 emit_byte(0x5A); | |
1211 emit_byte(0xC0 | encode); | |
1212 } | |
1213 | |
1214 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
1215 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1216 emit_byte(0xF2); | |
1217 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1218 emit_byte(0x0F); | |
1219 emit_byte(0x2C); | |
1220 emit_byte(0xC0 | encode); | |
1221 } | |
1222 | |
1223 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1224 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1225 emit_byte(0xF3); | |
1226 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1227 emit_byte(0x0F); | |
1228 emit_byte(0x2C); | |
1229 emit_byte(0xC0 | encode); | |
1230 } | |
1231 | |
1232 void Assembler::decl(Address dst) { | |
1233 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1234 InstructionMark im(this); | |
1235 prefix(dst); | |
1236 emit_byte(0xFF); | |
1237 emit_operand(rcx, dst); | |
1238 } | |
1239 | |
1240 void Assembler::divsd(XMMRegister dst, Address src) { | |
1241 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1242 InstructionMark im(this); | |
1243 emit_byte(0xF2); | |
1244 prefix(src, dst); | |
1245 emit_byte(0x0F); | |
1246 emit_byte(0x5E); | |
1247 emit_operand(dst, src); | |
1248 } | |
1249 | |
1250 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1251 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1252 emit_byte(0xF2); | |
1253 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1254 emit_byte(0x0F); | |
1255 emit_byte(0x5E); | |
1256 emit_byte(0xC0 | encode); | |
1257 } | |
1258 | |
1259 void Assembler::divss(XMMRegister dst, Address src) { | |
1260 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1261 InstructionMark im(this); | |
1262 emit_byte(0xF3); | |
1263 prefix(src, dst); | |
1264 emit_byte(0x0F); | |
1265 emit_byte(0x5E); | |
1266 emit_operand(dst, src); | |
1267 } | |
1268 | |
1269 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1270 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1271 emit_byte(0xF3); | |
1272 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1273 emit_byte(0x0F); | |
1274 emit_byte(0x5E); | |
1275 emit_byte(0xC0 | encode); | |
1276 } | |
1277 | |
1278 void Assembler::emms() { | |
1279 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
1280 emit_byte(0x0F); | |
1281 emit_byte(0x77); | |
1282 } | |
1283 | |
1284 void Assembler::hlt() { | |
1285 emit_byte(0xF4); | |
1286 } | |
1287 | |
1288 void Assembler::idivl(Register src) { | |
1289 int encode = prefix_and_encode(src->encoding()); | |
1290 emit_byte(0xF7); | |
1291 emit_byte(0xF8 | encode); | |
1292 } | |
1293 | |
1920 | 1294 void Assembler::divl(Register src) { // Unsigned |
1295 int encode = prefix_and_encode(src->encoding()); | |
1296 emit_byte(0xF7); | |
1297 emit_byte(0xF0 | encode); | |
1298 } | |
1299 | |
304 | 1300 void Assembler::imull(Register dst, Register src) { |
1301 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1302 emit_byte(0x0F); | |
1303 emit_byte(0xAF); | |
1304 emit_byte(0xC0 | encode); | |
1305 } | |
1306 | |
1307 | |
1308 void Assembler::imull(Register dst, Register src, int value) { | |
1309 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1310 if (is8bit(value)) { | |
1311 emit_byte(0x6B); | |
1312 emit_byte(0xC0 | encode); | |
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1313 emit_byte(value & 0xFF); |
304 | 1314 } else { |
1315 emit_byte(0x69); | |
1316 emit_byte(0xC0 | encode); | |
1317 emit_long(value); | |
1318 } | |
1319 } | |
1320 | |
1321 void Assembler::incl(Address dst) { | |
1322 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1323 InstructionMark im(this); | |
1324 prefix(dst); | |
1325 emit_byte(0xFF); | |
1326 emit_operand(rax, dst); | |
1327 } | |
1328 | |
1329 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { | |
1330 InstructionMark im(this); | |
1331 relocate(rtype); | |
1332 assert((0 <= cc) && (cc < 16), "illegal cc"); | |
1333 if (L.is_bound()) { | |
1334 address dst = target(L); | |
1335 assert(dst != NULL, "jcc most probably wrong"); | |
1336 | |
1337 const int short_size = 2; | |
1338 const int long_size = 6; | |
1339 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
1340 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
1341 // 0111 tttn #8-bit disp | |
1342 emit_byte(0x70 | cc); | |
1343 emit_byte((offs - short_size) & 0xFF); | |
1344 } else { | |
1345 // 0000 1111 1000 tttn #32-bit disp | |
1346 assert(is_simm32(offs - long_size), | |
1347 "must be 32bit offset (call4)"); | |
1348 emit_byte(0x0F); | |
1349 emit_byte(0x80 | cc); | |
1350 emit_long(offs - long_size); | |
1351 } | |
1352 } else { | |
1353 // Note: could eliminate cond. jumps to this jump if condition | |
1354 // is the same however, seems to be rather unlikely case. | |
1355 // Note: use jccb() if label to be bound is very close to get | |
1356 // an 8-bit displacement | |
1357 L.add_patch_at(code(), locator()); | |
1358 emit_byte(0x0F); | |
1359 emit_byte(0x80 | cc); | |
1360 emit_long(0); | |
1361 } | |
1362 } | |
1363 | |
1364 void Assembler::jccb(Condition cc, Label& L) { | |
1365 if (L.is_bound()) { | |
1366 const int short_size = 2; | |
1367 address entry = target(L); | |
1368 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
1369 "Dispacement too large for a short jmp"); | |
1370 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
1371 // 0111 tttn #8-bit disp | |
1372 emit_byte(0x70 | cc); | |
1373 emit_byte((offs - short_size) & 0xFF); | |
1374 } else { | |
1375 InstructionMark im(this); | |
1376 L.add_patch_at(code(), locator()); | |
1377 emit_byte(0x70 | cc); | |
1378 emit_byte(0); | |
1379 } | |
1380 } | |
1381 | |
1382 void Assembler::jmp(Address adr) { | |
1383 InstructionMark im(this); | |
1384 prefix(adr); | |
1385 emit_byte(0xFF); | |
1386 emit_operand(rsp, adr); | |
1387 } | |
1388 | |
1389 void Assembler::jmp(Label& L, relocInfo::relocType rtype) { | |
1390 if (L.is_bound()) { | |
1391 address entry = target(L); | |
1392 assert(entry != NULL, "jmp most probably wrong"); | |
1393 InstructionMark im(this); | |
1394 const int short_size = 2; | |
1395 const int long_size = 5; | |
1396 intptr_t offs = entry - _code_pos; | |
1397 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
1398 emit_byte(0xEB); | |
1399 emit_byte((offs - short_size) & 0xFF); | |
1400 } else { | |
1401 emit_byte(0xE9); | |
1402 emit_long(offs - long_size); | |
1403 } | |
1404 } else { | |
1405 // By default, forward jumps are always 32-bit displacements, since | |
1406 // we can't yet know where the label will be bound. If you're sure that | |
1407 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1408 // force an 8-bit displacement. | |
1409 InstructionMark im(this); | |
1410 relocate(rtype); | |
1411 L.add_patch_at(code(), locator()); | |
1412 emit_byte(0xE9); | |
1413 emit_long(0); | |
1414 } | |
1415 } | |
1416 | |
1417 void Assembler::jmp(Register entry) { | |
1418 int encode = prefix_and_encode(entry->encoding()); | |
1419 emit_byte(0xFF); | |
1420 emit_byte(0xE0 | encode); | |
1421 } | |
1422 | |
1423 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1424 InstructionMark im(this); | |
1425 emit_byte(0xE9); | |
1426 assert(dest != NULL, "must have a target"); | |
1427 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
1428 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
1429 emit_data(disp, rspec.reloc(), call32_operand); | |
1430 } | |
1431 | |
1432 void Assembler::jmpb(Label& L) { | |
1433 if (L.is_bound()) { | |
1434 const int short_size = 2; | |
1435 address entry = target(L); | |
1436 assert(is8bit((entry - _code_pos) + short_size), | |
1437 "Dispacement too large for a short jmp"); | |
1438 assert(entry != NULL, "jmp most probably wrong"); | |
1439 intptr_t offs = entry - _code_pos; | |
1440 emit_byte(0xEB); | |
1441 emit_byte((offs - short_size) & 0xFF); | |
1442 } else { | |
1443 InstructionMark im(this); | |
1444 L.add_patch_at(code(), locator()); | |
1445 emit_byte(0xEB); | |
1446 emit_byte(0); | |
1447 } | |
1448 } | |
1449 | |
1450 void Assembler::ldmxcsr( Address src) { | |
1451 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1452 InstructionMark im(this); | |
1453 prefix(src); | |
1454 emit_byte(0x0F); | |
1455 emit_byte(0xAE); | |
1456 emit_operand(as_Register(2), src); | |
1457 } | |
1458 | |
1459 void Assembler::leal(Register dst, Address src) { | |
1460 InstructionMark im(this); | |
1461 #ifdef _LP64 | |
1462 emit_byte(0x67); // addr32 | |
1463 prefix(src, dst); | |
1464 #endif // LP64 | |
1465 emit_byte(0x8D); | |
1466 emit_operand(dst, src); | |
1467 } | |
1468 | |
1469 void Assembler::lock() { | |
1470 if (Atomics & 1) { | |
1471 // Emit either nothing, a NOP, or a NOP: prefix | |
1472 emit_byte(0x90) ; | |
1473 } else { | |
1474 emit_byte(0xF0); | |
1475 } | |
1476 } | |
1477 | |
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1478 void Assembler::lzcntl(Register dst, Register src) { |
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1479 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1480 emit_byte(0xF3); |
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1481 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1482 emit_byte(0x0F); |
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1483 emit_byte(0xBD); |
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1484 emit_byte(0xC0 | encode); |
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1485 } |
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1486 |
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1487 // Emit mfence instruction |
304 | 1488 void Assembler::mfence() { |
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1489 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1490 emit_byte( 0x0F ); |
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1491 emit_byte( 0xAE ); |
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1492 emit_byte( 0xF0 ); |
304 | 1493 } |
1494 | |
1495 void Assembler::mov(Register dst, Register src) { | |
1496 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1497 } | |
1498 | |
1499 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1500 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1501 int dstenc = dst->encoding(); | |
1502 int srcenc = src->encoding(); | |
1503 emit_byte(0x66); | |
1504 if (dstenc < 8) { | |
1505 if (srcenc >= 8) { | |
1506 prefix(REX_B); | |
1507 srcenc -= 8; | |
1508 } | |
1509 } else { | |
1510 if (srcenc < 8) { | |
1511 prefix(REX_R); | |
1512 } else { | |
1513 prefix(REX_RB); | |
1514 srcenc -= 8; | |
1515 } | |
1516 dstenc -= 8; | |
1517 } | |
1518 emit_byte(0x0F); | |
1519 emit_byte(0x28); | |
1520 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
1521 } | |
1522 | |
1523 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1524 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1525 int dstenc = dst->encoding(); | |
1526 int srcenc = src->encoding(); | |
1527 if (dstenc < 8) { | |
1528 if (srcenc >= 8) { | |
1529 prefix(REX_B); | |
1530 srcenc -= 8; | |
1531 } | |
1532 } else { | |
1533 if (srcenc < 8) { | |
1534 prefix(REX_R); | |
1535 } else { | |
1536 prefix(REX_RB); | |
1537 srcenc -= 8; | |
1538 } | |
1539 dstenc -= 8; | |
1540 } | |
1541 emit_byte(0x0F); | |
1542 emit_byte(0x28); | |
1543 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
1544 } | |
1545 | |
1546 void Assembler::movb(Register dst, Address src) { | |
1547 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1548 InstructionMark im(this); | |
1549 prefix(src, dst, true); | |
1550 emit_byte(0x8A); | |
1551 emit_operand(dst, src); | |
1552 } | |
1553 | |
1554 | |
1555 void Assembler::movb(Address dst, int imm8) { | |
1556 InstructionMark im(this); | |
1557 prefix(dst); | |
1558 emit_byte(0xC6); | |
1559 emit_operand(rax, dst, 1); | |
1560 emit_byte(imm8); | |
1561 } | |
1562 | |
1563 | |
1564 void Assembler::movb(Address dst, Register src) { | |
1565 assert(src->has_byte_register(), "must have byte register"); | |
1566 InstructionMark im(this); | |
1567 prefix(dst, src, true); | |
1568 emit_byte(0x88); | |
1569 emit_operand(src, dst); | |
1570 } | |
1571 | |
1572 void Assembler::movdl(XMMRegister dst, Register src) { | |
1573 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1574 emit_byte(0x66); | |
1575 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1576 emit_byte(0x0F); | |
1577 emit_byte(0x6E); | |
1578 emit_byte(0xC0 | encode); | |
1579 } | |
1580 | |
1581 void Assembler::movdl(Register dst, XMMRegister src) { | |
1582 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1583 emit_byte(0x66); | |
1584 // swap src/dst to get correct prefix | |
1585 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
1586 emit_byte(0x0F); | |
1587 emit_byte(0x7E); | |
1588 emit_byte(0xC0 | encode); | |
1589 } | |
1590 | |
1591 void Assembler::movdqa(XMMRegister dst, Address src) { | |
1592 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1593 InstructionMark im(this); | |
1594 emit_byte(0x66); | |
1595 prefix(src, dst); | |
1596 emit_byte(0x0F); | |
1597 emit_byte(0x6F); | |
1598 emit_operand(dst, src); | |
1599 } | |
1600 | |
1601 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
1602 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1603 emit_byte(0x66); | |
1604 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1605 emit_byte(0x0F); | |
1606 emit_byte(0x6F); | |
1607 emit_byte(0xC0 | encode); | |
1608 } | |
1609 | |
1610 void Assembler::movdqa(Address dst, XMMRegister src) { | |
1611 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1612 InstructionMark im(this); | |
1613 emit_byte(0x66); | |
1614 prefix(dst, src); | |
1615 emit_byte(0x0F); | |
1616 emit_byte(0x7F); | |
1617 emit_operand(src, dst); | |
1618 } | |
1619 | |
405 | 1620 void Assembler::movdqu(XMMRegister dst, Address src) { |
1621 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1622 InstructionMark im(this); | |
1623 emit_byte(0xF3); | |
1624 prefix(src, dst); | |
1625 emit_byte(0x0F); | |
1626 emit_byte(0x6F); | |
1627 emit_operand(dst, src); | |
1628 } | |
1629 | |
1630 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1631 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1632 emit_byte(0xF3); | |
1633 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1634 emit_byte(0x0F); | |
1635 emit_byte(0x6F); | |
1636 emit_byte(0xC0 | encode); | |
1637 } | |
1638 | |
1639 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1640 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1641 InstructionMark im(this); | |
1642 emit_byte(0xF3); | |
1643 prefix(dst, src); | |
1644 emit_byte(0x0F); | |
1645 emit_byte(0x7F); | |
1646 emit_operand(src, dst); | |
1647 } | |
1648 | |
304 | 1649 // Uses zero extension on 64bit |
1650 | |
1651 void Assembler::movl(Register dst, int32_t imm32) { | |
1652 int encode = prefix_and_encode(dst->encoding()); | |
1653 emit_byte(0xB8 | encode); | |
1654 emit_long(imm32); | |
1655 } | |
1656 | |
1657 void Assembler::movl(Register dst, Register src) { | |
1658 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1659 emit_byte(0x8B); | |
1660 emit_byte(0xC0 | encode); | |
1661 } | |
1662 | |
1663 void Assembler::movl(Register dst, Address src) { | |
1664 InstructionMark im(this); | |
1665 prefix(src, dst); | |
1666 emit_byte(0x8B); | |
1667 emit_operand(dst, src); | |
1668 } | |
1669 | |
1670 void Assembler::movl(Address dst, int32_t imm32) { | |
1671 InstructionMark im(this); | |
1672 prefix(dst); | |
1673 emit_byte(0xC7); | |
1674 emit_operand(rax, dst, 4); | |
1675 emit_long(imm32); | |
1676 } | |
1677 | |
1678 void Assembler::movl(Address dst, Register src) { | |
1679 InstructionMark im(this); | |
1680 prefix(dst, src); | |
1681 emit_byte(0x89); | |
1682 emit_operand(src, dst); | |
1683 } | |
1684 | |
1685 // New cpus require to use movsd and movss to avoid partial register stall | |
1686 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1687 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1688 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1690 InstructionMark im(this); | |
1691 emit_byte(0x66); | |
1692 prefix(src, dst); | |
1693 emit_byte(0x0F); | |
1694 emit_byte(0x12); | |
1695 emit_operand(dst, src); | |
1696 } | |
1697 | |
1698 void Assembler::movq( MMXRegister dst, Address src ) { | |
1699 assert( VM_Version::supports_mmx(), "" ); | |
1700 emit_byte(0x0F); | |
1701 emit_byte(0x6F); | |
1702 emit_operand(dst, src); | |
1703 } | |
1704 | |
1705 void Assembler::movq( Address dst, MMXRegister src ) { | |
1706 assert( VM_Version::supports_mmx(), "" ); | |
1707 emit_byte(0x0F); | |
1708 emit_byte(0x7F); | |
1709 // workaround gcc (3.2.1-7a) bug | |
1710 // In that version of gcc with only an emit_operand(MMX, Address) | |
1711 // gcc will tail jump and try and reverse the parameters completely | |
1712 // obliterating dst in the process. By having a version available | |
1713 // that doesn't need to swap the args at the tail jump the bug is | |
1714 // avoided. | |
1715 emit_operand(dst, src); | |
1716 } | |
1717 | |
1718 void Assembler::movq(XMMRegister dst, Address src) { | |
1719 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1720 InstructionMark im(this); | |
1721 emit_byte(0xF3); | |
1722 prefix(src, dst); | |
1723 emit_byte(0x0F); | |
1724 emit_byte(0x7E); | |
1725 emit_operand(dst, src); | |
1726 } | |
1727 | |
1728 void Assembler::movq(Address dst, XMMRegister src) { | |
1729 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1730 InstructionMark im(this); | |
1731 emit_byte(0x66); | |
1732 prefix(dst, src); | |
1733 emit_byte(0x0F); | |
1734 emit_byte(0xD6); | |
1735 emit_operand(src, dst); | |
1736 } | |
1737 | |
1738 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1739 InstructionMark im(this); | |
1740 prefix(src, dst); | |
1741 emit_byte(0x0F); | |
1742 emit_byte(0xBE); | |
1743 emit_operand(dst, src); | |
1744 } | |
1745 | |
1746 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1747 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1748 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
1749 emit_byte(0x0F); | |
1750 emit_byte(0xBE); | |
1751 emit_byte(0xC0 | encode); | |
1752 } | |
1753 | |
1754 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1755 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1756 emit_byte(0xF2); | |
1757 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1758 emit_byte(0x0F); | |
1759 emit_byte(0x10); | |
1760 emit_byte(0xC0 | encode); | |
1761 } | |
1762 | |
1763 void Assembler::movsd(XMMRegister dst, Address src) { | |
1764 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1765 InstructionMark im(this); | |
1766 emit_byte(0xF2); | |
1767 prefix(src, dst); | |
1768 emit_byte(0x0F); | |
1769 emit_byte(0x10); | |
1770 emit_operand(dst, src); | |
1771 } | |
1772 | |
1773 void Assembler::movsd(Address dst, XMMRegister src) { | |
1774 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1775 InstructionMark im(this); | |
1776 emit_byte(0xF2); | |
1777 prefix(dst, src); | |
1778 emit_byte(0x0F); | |
1779 emit_byte(0x11); | |
1780 emit_operand(src, dst); | |
1781 } | |
1782 | |
1783 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1784 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1785 emit_byte(0xF3); | |
1786 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1787 emit_byte(0x0F); | |
1788 emit_byte(0x10); | |
1789 emit_byte(0xC0 | encode); | |
1790 } | |
1791 | |
1792 void Assembler::movss(XMMRegister dst, Address src) { | |
1793 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1794 InstructionMark im(this); | |
1795 emit_byte(0xF3); | |
1796 prefix(src, dst); | |
1797 emit_byte(0x0F); | |
1798 emit_byte(0x10); | |
1799 emit_operand(dst, src); | |
1800 } | |
1801 | |
1802 void Assembler::movss(Address dst, XMMRegister src) { | |
1803 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1804 InstructionMark im(this); | |
1805 emit_byte(0xF3); | |
1806 prefix(dst, src); | |
1807 emit_byte(0x0F); | |
1808 emit_byte(0x11); | |
1809 emit_operand(src, dst); | |
1810 } | |
1811 | |
1812 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1813 InstructionMark im(this); | |
1814 prefix(src, dst); | |
1815 emit_byte(0x0F); | |
1816 emit_byte(0xBF); | |
1817 emit_operand(dst, src); | |
1818 } | |
1819 | |
1820 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1821 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1822 emit_byte(0x0F); | |
1823 emit_byte(0xBF); | |
1824 emit_byte(0xC0 | encode); | |
1825 } | |
1826 | |
1827 void Assembler::movw(Address dst, int imm16) { | |
1828 InstructionMark im(this); | |
1829 | |
1830 emit_byte(0x66); // switch to 16-bit mode | |
1831 prefix(dst); | |
1832 emit_byte(0xC7); | |
1833 emit_operand(rax, dst, 2); | |
1834 emit_word(imm16); | |
1835 } | |
1836 | |
1837 void Assembler::movw(Register dst, Address src) { | |
1838 InstructionMark im(this); | |
1839 emit_byte(0x66); | |
1840 prefix(src, dst); | |
1841 emit_byte(0x8B); | |
1842 emit_operand(dst, src); | |
1843 } | |
1844 | |
1845 void Assembler::movw(Address dst, Register src) { | |
1846 InstructionMark im(this); | |
1847 emit_byte(0x66); | |
1848 prefix(dst, src); | |
1849 emit_byte(0x89); | |
1850 emit_operand(src, dst); | |
1851 } | |
1852 | |
1853 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1854 InstructionMark im(this); | |
1855 prefix(src, dst); | |
1856 emit_byte(0x0F); | |
1857 emit_byte(0xB6); | |
1858 emit_operand(dst, src); | |
1859 } | |
1860 | |
1861 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
1862 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1863 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
1864 emit_byte(0x0F); | |
1865 emit_byte(0xB6); | |
1866 emit_byte(0xC0 | encode); | |
1867 } | |
1868 | |
1869 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
1870 InstructionMark im(this); | |
1871 prefix(src, dst); | |
1872 emit_byte(0x0F); | |
1873 emit_byte(0xB7); | |
1874 emit_operand(dst, src); | |
1875 } | |
1876 | |
1877 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
1878 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1879 emit_byte(0x0F); | |
1880 emit_byte(0xB7); | |
1881 emit_byte(0xC0 | encode); | |
1882 } | |
1883 | |
1884 void Assembler::mull(Address src) { | |
1885 InstructionMark im(this); | |
1886 prefix(src); | |
1887 emit_byte(0xF7); | |
1888 emit_operand(rsp, src); | |
1889 } | |
1890 | |
1891 void Assembler::mull(Register src) { | |
1892 int encode = prefix_and_encode(src->encoding()); | |
1893 emit_byte(0xF7); | |
1894 emit_byte(0xE0 | encode); | |
1895 } | |
1896 | |
1897 void Assembler::mulsd(XMMRegister dst, Address src) { | |
1898 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1899 InstructionMark im(this); | |
1900 emit_byte(0xF2); | |
1901 prefix(src, dst); | |
1902 emit_byte(0x0F); | |
1903 emit_byte(0x59); | |
1904 emit_operand(dst, src); | |
1905 } | |
1906 | |
1907 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
1908 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1909 emit_byte(0xF2); | |
1910 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1911 emit_byte(0x0F); | |
1912 emit_byte(0x59); | |
1913 emit_byte(0xC0 | encode); | |
1914 } | |
1915 | |
1916 void Assembler::mulss(XMMRegister dst, Address src) { | |
1917 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1918 InstructionMark im(this); | |
1919 emit_byte(0xF3); | |
1920 prefix(src, dst); | |
1921 emit_byte(0x0F); | |
1922 emit_byte(0x59); | |
1923 emit_operand(dst, src); | |
1924 } | |
1925 | |
1926 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
1927 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1928 emit_byte(0xF3); | |
1929 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1930 emit_byte(0x0F); | |
1931 emit_byte(0x59); | |
1932 emit_byte(0xC0 | encode); | |
1933 } | |
1934 | |
1935 void Assembler::negl(Register dst) { | |
1936 int encode = prefix_and_encode(dst->encoding()); | |
1937 emit_byte(0xF7); | |
1938 emit_byte(0xD8 | encode); | |
1939 } | |
1940 | |
0 | 1941 void Assembler::nop(int i) { |
304 | 1942 #ifdef ASSERT |
0 | 1943 assert(i > 0, " "); |
304 | 1944 // The fancy nops aren't currently recognized by debuggers making it a |
1945 // pain to disassemble code while debugging. If asserts are on clearly | |
1946 // speed is not an issue so simply use the single byte traditional nop | |
1947 // to do alignment. | |
1948 | |
1949 for (; i > 0 ; i--) emit_byte(0x90); | |
1950 return; | |
1951 | |
1952 #endif // ASSERT | |
1953 | |
0 | 1954 if (UseAddressNop && VM_Version::is_intel()) { |
1955 // | |
1956 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
1957 // 1: 0x90 | |
1958 // 2: 0x66 0x90 | |
1959 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
1960 // 4: 0x0F 0x1F 0x40 0x00 | |
1961 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
1962 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
1963 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
1964 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1965 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1966 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1967 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1968 | |
1969 // The rest coding is Intel specific - don't use consecutive address nops | |
1970 | |
1971 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1972 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1973 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1974 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1975 | |
1976 while(i >= 15) { | |
1977 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
1978 i -= 15; | |
1979 emit_byte(0x66); // size prefix | |
1980 emit_byte(0x66); // size prefix | |
1981 emit_byte(0x66); // size prefix | |
1982 addr_nop_8(); | |
1983 emit_byte(0x66); // size prefix | |
1984 emit_byte(0x66); // size prefix | |
1985 emit_byte(0x66); // size prefix | |
1986 emit_byte(0x90); // nop | |
1987 } | |
1988 switch (i) { | |
1989 case 14: | |
1990 emit_byte(0x66); // size prefix | |
1991 case 13: | |
1992 emit_byte(0x66); // size prefix | |
1993 case 12: | |
1994 addr_nop_8(); | |
1995 emit_byte(0x66); // size prefix | |
1996 emit_byte(0x66); // size prefix | |
1997 emit_byte(0x66); // size prefix | |
1998 emit_byte(0x90); // nop | |
1999 break; | |
2000 case 11: | |
2001 emit_byte(0x66); // size prefix | |
2002 case 10: | |
2003 emit_byte(0x66); // size prefix | |
2004 case 9: | |
2005 emit_byte(0x66); // size prefix | |
2006 case 8: | |
2007 addr_nop_8(); | |
2008 break; | |
2009 case 7: | |
2010 addr_nop_7(); | |
2011 break; | |
2012 case 6: | |
2013 emit_byte(0x66); // size prefix | |
2014 case 5: | |
2015 addr_nop_5(); | |
2016 break; | |
2017 case 4: | |
2018 addr_nop_4(); | |
2019 break; | |
2020 case 3: | |
2021 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
2022 emit_byte(0x66); // size prefix | |
2023 case 2: | |
2024 emit_byte(0x66); // size prefix | |
2025 case 1: | |
2026 emit_byte(0x90); // nop | |
2027 break; | |
2028 default: | |
2029 assert(i == 0, " "); | |
2030 } | |
2031 return; | |
2032 } | |
2033 if (UseAddressNop && VM_Version::is_amd()) { | |
2034 // | |
2035 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
2036 // 1: 0x90 | |
2037 // 2: 0x66 0x90 | |
2038 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2039 // 4: 0x0F 0x1F 0x40 0x00 | |
2040 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2041 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2042 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2043 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2044 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2045 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2046 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2047 | |
2048 // The rest coding is AMD specific - use consecutive address nops | |
2049 | |
2050 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2051 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2052 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2053 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2054 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2055 // Size prefixes (0x66) are added for larger sizes | |
2056 | |
2057 while(i >= 22) { | |
2058 i -= 11; | |
2059 emit_byte(0x66); // size prefix | |
2060 emit_byte(0x66); // size prefix | |
2061 emit_byte(0x66); // size prefix | |
2062 addr_nop_8(); | |
2063 } | |
2064 // Generate first nop for size between 21-12 | |
2065 switch (i) { | |
2066 case 21: | |
2067 i -= 1; | |
2068 emit_byte(0x66); // size prefix | |
2069 case 20: | |
2070 case 19: | |
2071 i -= 1; | |
2072 emit_byte(0x66); // size prefix | |
2073 case 18: | |
2074 case 17: | |
2075 i -= 1; | |
2076 emit_byte(0x66); // size prefix | |
2077 case 16: | |
2078 case 15: | |
2079 i -= 8; | |
2080 addr_nop_8(); | |
2081 break; | |
2082 case 14: | |
2083 case 13: | |
2084 i -= 7; | |
2085 addr_nop_7(); | |
2086 break; | |
2087 case 12: | |
2088 i -= 6; | |
2089 emit_byte(0x66); // size prefix | |
2090 addr_nop_5(); | |
2091 break; | |
2092 default: | |
2093 assert(i < 12, " "); | |
2094 } | |
2095 | |
2096 // Generate second nop for size between 11-1 | |
2097 switch (i) { | |
2098 case 11: | |
2099 emit_byte(0x66); // size prefix | |
2100 case 10: | |
2101 emit_byte(0x66); // size prefix | |
2102 case 9: | |
2103 emit_byte(0x66); // size prefix | |
2104 case 8: | |
2105 addr_nop_8(); | |
2106 break; | |
2107 case 7: | |
2108 addr_nop_7(); | |
2109 break; | |
2110 case 6: | |
2111 emit_byte(0x66); // size prefix | |
2112 case 5: | |
2113 addr_nop_5(); | |
2114 break; | |
2115 case 4: | |
2116 addr_nop_4(); | |
2117 break; | |
2118 case 3: | |
2119 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
2120 emit_byte(0x66); // size prefix | |
2121 case 2: | |
2122 emit_byte(0x66); // size prefix | |
2123 case 1: | |
2124 emit_byte(0x90); // nop | |
2125 break; | |
2126 default: | |
2127 assert(i == 0, " "); | |
2128 } | |
2129 return; | |
2130 } | |
2131 | |
2132 // Using nops with size prefixes "0x66 0x90". | |
2133 // From AMD Optimization Guide: | |
2134 // 1: 0x90 | |
2135 // 2: 0x66 0x90 | |
2136 // 3: 0x66 0x66 0x90 | |
2137 // 4: 0x66 0x66 0x66 0x90 | |
2138 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2139 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2140 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2141 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2142 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2143 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2144 // | |
2145 while(i > 12) { | |
2146 i -= 4; | |
2147 emit_byte(0x66); // size prefix | |
2148 emit_byte(0x66); | |
2149 emit_byte(0x66); | |
2150 emit_byte(0x90); // nop | |
2151 } | |
2152 // 1 - 12 nops | |
2153 if(i > 8) { | |
2154 if(i > 9) { | |
2155 i -= 1; | |
2156 emit_byte(0x66); | |
2157 } | |
2158 i -= 3; | |
2159 emit_byte(0x66); | |
2160 emit_byte(0x66); | |
2161 emit_byte(0x90); | |
2162 } | |
2163 // 1 - 8 nops | |
2164 if(i > 4) { | |
2165 if(i > 6) { | |
2166 i -= 1; | |
2167 emit_byte(0x66); | |
2168 } | |
2169 i -= 3; | |
2170 emit_byte(0x66); | |
2171 emit_byte(0x66); | |
2172 emit_byte(0x90); | |
2173 } | |
2174 switch (i) { | |
2175 case 4: | |
2176 emit_byte(0x66); | |
2177 case 3: | |
2178 emit_byte(0x66); | |
2179 case 2: | |
2180 emit_byte(0x66); | |
2181 case 1: | |
2182 emit_byte(0x90); | |
2183 break; | |
2184 default: | |
2185 assert(i == 0, " "); | |
2186 } | |
2187 } | |
2188 | |
304 | 2189 void Assembler::notl(Register dst) { |
2190 int encode = prefix_and_encode(dst->encoding()); | |
2191 emit_byte(0xF7); | |
2192 emit_byte(0xD0 | encode ); | |
2193 } | |
2194 | |
2195 void Assembler::orl(Address dst, int32_t imm32) { | |
2196 InstructionMark im(this); | |
2197 prefix(dst); | |
2198 emit_byte(0x81); | |
2199 emit_operand(rcx, dst, 4); | |
2200 emit_long(imm32); | |
2201 } | |
2202 | |
2203 void Assembler::orl(Register dst, int32_t imm32) { | |
2204 prefix(dst); | |
2205 emit_arith(0x81, 0xC8, dst, imm32); | |
2206 } | |
2207 | |
2208 | |
2209 void Assembler::orl(Register dst, Address src) { | |
2210 InstructionMark im(this); | |
2211 prefix(src, dst); | |
2212 emit_byte(0x0B); | |
2213 emit_operand(dst, src); | |
2214 } | |
2215 | |
2216 | |
2217 void Assembler::orl(Register dst, Register src) { | |
2218 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2219 emit_arith(0x0B, 0xC0, dst, src); | |
2220 } | |
2221 | |
681 | 2222 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2223 assert(VM_Version::supports_sse4_2(), ""); | |
2224 | |
2225 InstructionMark im(this); | |
2226 emit_byte(0x66); | |
2227 prefix(src, dst); | |
2228 emit_byte(0x0F); | |
2229 emit_byte(0x3A); | |
2230 emit_byte(0x61); | |
2231 emit_operand(dst, src); | |
2232 emit_byte(imm8); | |
2233 } | |
2234 | |
2235 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
2236 assert(VM_Version::supports_sse4_2(), ""); | |
2237 | |
2238 emit_byte(0x66); | |
2239 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2240 emit_byte(0x0F); | |
2241 emit_byte(0x3A); | |
2242 emit_byte(0x61); | |
2243 emit_byte(0xC0 | encode); | |
2244 emit_byte(imm8); | |
2245 } | |
2246 | |
304 | 2247 // generic |
2248 void Assembler::pop(Register dst) { | |
2249 int encode = prefix_and_encode(dst->encoding()); | |
2250 emit_byte(0x58 | encode); | |
2251 } | |
2252 | |
643
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2253 void Assembler::popcntl(Register dst, Address src) { |
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2254 assert(VM_Version::supports_popcnt(), "must support"); |
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2255 InstructionMark im(this); |
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2256 emit_byte(0xF3); |
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2257 prefix(src, dst); |
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2258 emit_byte(0x0F); |
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2259 emit_byte(0xB8); |
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2260 emit_operand(dst, src); |
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2261 } |
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2262 |
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2263 void Assembler::popcntl(Register dst, Register src) { |
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2264 assert(VM_Version::supports_popcnt(), "must support"); |
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2265 emit_byte(0xF3); |
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2266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2267 emit_byte(0x0F); |
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2268 emit_byte(0xB8); |
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2269 emit_byte(0xC0 | encode); |
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2270 } |
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2271 |
304 | 2272 void Assembler::popf() { |
2273 emit_byte(0x9D); | |
2274 } | |
2275 | |
1060 | 2276 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2277 void Assembler::popl(Address dst) { |
2278 // NOTE: this will adjust stack by 8byte on 64bits | |
2279 InstructionMark im(this); | |
2280 prefix(dst); | |
2281 emit_byte(0x8F); | |
2282 emit_operand(rax, dst); | |
2283 } | |
1060 | 2284 #endif |
304 | 2285 |
2286 void Assembler::prefetch_prefix(Address src) { | |
2287 prefix(src); | |
2288 emit_byte(0x0F); | |
2289 } | |
2290 | |
2291 void Assembler::prefetchnta(Address src) { | |
2292 NOT_LP64(assert(VM_Version::supports_sse2(), "must support")); | |
2293 InstructionMark im(this); | |
2294 prefetch_prefix(src); | |
2295 emit_byte(0x18); | |
2296 emit_operand(rax, src); // 0, src | |
2297 } | |
2298 | |
2299 void Assembler::prefetchr(Address src) { | |
2300 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
2301 InstructionMark im(this); | |
2302 prefetch_prefix(src); | |
2303 emit_byte(0x0D); | |
2304 emit_operand(rax, src); // 0, src | |
2305 } | |
2306 | |
2307 void Assembler::prefetcht0(Address src) { | |
2308 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2309 InstructionMark im(this); | |
2310 prefetch_prefix(src); | |
2311 emit_byte(0x18); | |
2312 emit_operand(rcx, src); // 1, src | |
2313 } | |
2314 | |
2315 void Assembler::prefetcht1(Address src) { | |
2316 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2317 InstructionMark im(this); | |
2318 prefetch_prefix(src); | |
2319 emit_byte(0x18); | |
2320 emit_operand(rdx, src); // 2, src | |
2321 } | |
2322 | |
2323 void Assembler::prefetcht2(Address src) { | |
2324 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2325 InstructionMark im(this); | |
2326 prefetch_prefix(src); | |
2327 emit_byte(0x18); | |
2328 emit_operand(rbx, src); // 3, src | |
2329 } | |
2330 | |
2331 void Assembler::prefetchw(Address src) { | |
2332 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
2333 InstructionMark im(this); | |
2334 prefetch_prefix(src); | |
2335 emit_byte(0x0D); | |
2336 emit_operand(rcx, src); // 1, src | |
2337 } | |
2338 | |
2339 void Assembler::prefix(Prefix p) { | |
2340 a_byte(p); | |
2341 } | |
2342 | |
2343 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | |
2344 assert(isByte(mode), "invalid value"); | |
2345 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2346 | |
2347 emit_byte(0x66); | |
2348 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2349 emit_byte(0x0F); | |
2350 emit_byte(0x70); | |
2351 emit_byte(0xC0 | encode); | |
2352 emit_byte(mode & 0xFF); | |
2353 | |
2354 } | |
2355 | |
2356 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2357 assert(isByte(mode), "invalid value"); | |
2358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2359 | |
2360 InstructionMark im(this); | |
2361 emit_byte(0x66); | |
2362 prefix(src, dst); | |
2363 emit_byte(0x0F); | |
2364 emit_byte(0x70); | |
2365 emit_operand(dst, src); | |
2366 emit_byte(mode & 0xFF); | |
2367 } | |
2368 | |
2369 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2370 assert(isByte(mode), "invalid value"); | |
2371 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2372 | |
2373 emit_byte(0xF2); | |
2374 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2375 emit_byte(0x0F); | |
2376 emit_byte(0x70); | |
2377 emit_byte(0xC0 | encode); | |
2378 emit_byte(mode & 0xFF); | |
2379 } | |
2380 | |
2381 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2382 assert(isByte(mode), "invalid value"); | |
2383 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2384 | |
2385 InstructionMark im(this); | |
2386 emit_byte(0xF2); | |
2387 prefix(src, dst); // QQ new | |
2388 emit_byte(0x0F); | |
2389 emit_byte(0x70); | |
2390 emit_operand(dst, src); | |
2391 emit_byte(mode & 0xFF); | |
2392 } | |
2393 | |
2394 void Assembler::psrlq(XMMRegister dst, int shift) { | |
2395 // HMM Table D-1 says sse2 or mmx | |
2396 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2397 | |
2398 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
2399 emit_byte(0x66); | |
2400 emit_byte(0x0F); | |
2401 emit_byte(0x73); | |
2402 emit_byte(0xC0 | encode); | |
2403 emit_byte(shift); | |
2404 } | |
2405 | |
681 | 2406 void Assembler::ptest(XMMRegister dst, Address src) { |
2407 assert(VM_Version::supports_sse4_1(), ""); | |
2408 | |
2409 InstructionMark im(this); | |
2410 emit_byte(0x66); | |
2411 prefix(src, dst); | |
2412 emit_byte(0x0F); | |
2413 emit_byte(0x38); | |
2414 emit_byte(0x17); | |
2415 emit_operand(dst, src); | |
2416 } | |
2417 | |
2418 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
2419 assert(VM_Version::supports_sse4_1(), ""); | |
2420 | |
2421 emit_byte(0x66); | |
2422 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2423 emit_byte(0x0F); | |
2424 emit_byte(0x38); | |
2425 emit_byte(0x17); | |
2426 emit_byte(0xC0 | encode); | |
2427 } | |
2428 | |
304 | 2429 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2430 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2431 emit_byte(0x66); | |
2432 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2433 emit_byte(0x0F); | |
2434 emit_byte(0x60); | |
2435 emit_byte(0xC0 | encode); | |
2436 } | |
2437 | |
2438 void Assembler::push(int32_t imm32) { | |
2439 // in 64bits we push 64bits onto the stack but only | |
2440 // take a 32bit immediate | |
2441 emit_byte(0x68); | |
2442 emit_long(imm32); | |
2443 } | |
2444 | |
2445 void Assembler::push(Register src) { | |
2446 int encode = prefix_and_encode(src->encoding()); | |
2447 | |
2448 emit_byte(0x50 | encode); | |
2449 } | |
2450 | |
2451 void Assembler::pushf() { | |
2452 emit_byte(0x9C); | |
2453 } | |
2454 | |
1060 | 2455 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2456 void Assembler::pushl(Address src) { |
2457 // Note this will push 64bit on 64bit | |
2458 InstructionMark im(this); | |
2459 prefix(src); | |
2460 emit_byte(0xFF); | |
2461 emit_operand(rsi, src); | |
2462 } | |
1060 | 2463 #endif |
304 | 2464 |
2465 void Assembler::pxor(XMMRegister dst, Address src) { | |
2466 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2467 InstructionMark im(this); | |
2468 emit_byte(0x66); | |
2469 prefix(src, dst); | |
2470 emit_byte(0x0F); | |
2471 emit_byte(0xEF); | |
2472 emit_operand(dst, src); | |
2473 } | |
2474 | |
2475 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
2476 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2477 InstructionMark im(this); | |
2478 emit_byte(0x66); | |
2479 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2480 emit_byte(0x0F); | |
2481 emit_byte(0xEF); | |
2482 emit_byte(0xC0 | encode); | |
2483 } | |
2484 | |
2485 void Assembler::rcll(Register dst, int imm8) { | |
2486 assert(isShiftCount(imm8), "illegal shift count"); | |
2487 int encode = prefix_and_encode(dst->encoding()); | |
2488 if (imm8 == 1) { | |
2489 emit_byte(0xD1); | |
2490 emit_byte(0xD0 | encode); | |
2491 } else { | |
2492 emit_byte(0xC1); | |
2493 emit_byte(0xD0 | encode); | |
2494 emit_byte(imm8); | |
2495 } | |
2496 } | |
2497 | |
2498 // copies data from [esi] to [edi] using rcx pointer sized words | |
2499 // generic | |
2500 void Assembler::rep_mov() { | |
2501 emit_byte(0xF3); | |
2502 // MOVSQ | |
2503 LP64_ONLY(prefix(REX_W)); | |
2504 emit_byte(0xA5); | |
2505 } | |
2506 | |
2507 // sets rcx pointer sized words with rax, value at [edi] | |
2508 // generic | |
2509 void Assembler::rep_set() { // rep_set | |
2510 emit_byte(0xF3); | |
2511 // STOSQ | |
2512 LP64_ONLY(prefix(REX_W)); | |
2513 emit_byte(0xAB); | |
2514 } | |
2515 | |
2516 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2517 // generic | |
2518 void Assembler::repne_scan() { // repne_scan | |
2519 emit_byte(0xF2); | |
2520 // SCASQ | |
2521 LP64_ONLY(prefix(REX_W)); | |
2522 emit_byte(0xAF); | |
2523 } | |
2524 | |
2525 #ifdef _LP64 | |
2526 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2527 // generic | |
2528 void Assembler::repne_scanl() { // repne_scan | |
2529 emit_byte(0xF2); | |
2530 // SCASL | |
2531 emit_byte(0xAF); | |
2532 } | |
2533 #endif | |
2534 | |
0 | 2535 void Assembler::ret(int imm16) { |
2536 if (imm16 == 0) { | |
2537 emit_byte(0xC3); | |
2538 } else { | |
2539 emit_byte(0xC2); | |
2540 emit_word(imm16); | |
2541 } | |
2542 } | |
2543 | |
304 | 2544 void Assembler::sahf() { |
2545 #ifdef _LP64 | |
2546 // Not supported in 64bit mode | |
2547 ShouldNotReachHere(); | |
2548 #endif | |
2549 emit_byte(0x9E); | |
2550 } | |
2551 | |
2552 void Assembler::sarl(Register dst, int imm8) { | |
2553 int encode = prefix_and_encode(dst->encoding()); | |
2554 assert(isShiftCount(imm8), "illegal shift count"); | |
2555 if (imm8 == 1) { | |
2556 emit_byte(0xD1); | |
2557 emit_byte(0xF8 | encode); | |
2558 } else { | |
2559 emit_byte(0xC1); | |
2560 emit_byte(0xF8 | encode); | |
2561 emit_byte(imm8); | |
2562 } | |
2563 } | |
2564 | |
2565 void Assembler::sarl(Register dst) { | |
2566 int encode = prefix_and_encode(dst->encoding()); | |
2567 emit_byte(0xD3); | |
2568 emit_byte(0xF8 | encode); | |
2569 } | |
2570 | |
2571 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2572 InstructionMark im(this); | |
2573 prefix(dst); | |
2574 emit_arith_operand(0x81, rbx, dst, imm32); | |
2575 } | |
2576 | |
2577 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2578 prefix(dst); | |
2579 emit_arith(0x81, 0xD8, dst, imm32); | |
2580 } | |
2581 | |
2582 | |
2583 void Assembler::sbbl(Register dst, Address src) { | |
2584 InstructionMark im(this); | |
2585 prefix(src, dst); | |
2586 emit_byte(0x1B); | |
2587 emit_operand(dst, src); | |
2588 } | |
2589 | |
2590 void Assembler::sbbl(Register dst, Register src) { | |
2591 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2592 emit_arith(0x1B, 0xC0, dst, src); | |
2593 } | |
2594 | |
2595 void Assembler::setb(Condition cc, Register dst) { | |
2596 assert(0 <= cc && cc < 16, "illegal cc"); | |
2597 int encode = prefix_and_encode(dst->encoding(), true); | |
0 | 2598 emit_byte(0x0F); |
304 | 2599 emit_byte(0x90 | cc); |
2600 emit_byte(0xC0 | encode); | |
2601 } | |
2602 | |
2603 void Assembler::shll(Register dst, int imm8) { | |
2604 assert(isShiftCount(imm8), "illegal shift count"); | |
2605 int encode = prefix_and_encode(dst->encoding()); | |
2606 if (imm8 == 1 ) { | |
2607 emit_byte(0xD1); | |
2608 emit_byte(0xE0 | encode); | |
2609 } else { | |
2610 emit_byte(0xC1); | |
2611 emit_byte(0xE0 | encode); | |
2612 emit_byte(imm8); | |
2613 } | |
2614 } | |
2615 | |
2616 void Assembler::shll(Register dst) { | |
2617 int encode = prefix_and_encode(dst->encoding()); | |
2618 emit_byte(0xD3); | |
2619 emit_byte(0xE0 | encode); | |
2620 } | |
2621 | |
2622 void Assembler::shrl(Register dst, int imm8) { | |
2623 assert(isShiftCount(imm8), "illegal shift count"); | |
2624 int encode = prefix_and_encode(dst->encoding()); | |
2625 emit_byte(0xC1); | |
2626 emit_byte(0xE8 | encode); | |
2627 emit_byte(imm8); | |
2628 } | |
2629 | |
2630 void Assembler::shrl(Register dst) { | |
2631 int encode = prefix_and_encode(dst->encoding()); | |
2632 emit_byte(0xD3); | |
2633 emit_byte(0xE8 | encode); | |
2634 } | |
0 | 2635 |
2636 // copies a single word from [esi] to [edi] | |
2637 void Assembler::smovl() { | |
2638 emit_byte(0xA5); | |
2639 } | |
2640 | |
304 | 2641 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2642 // HMM Table D-1 says sse2 | |
2643 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2644 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2645 emit_byte(0xF2); | |
2646 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2647 emit_byte(0x0F); | |
2648 emit_byte(0x51); | |
2649 emit_byte(0xC0 | encode); | |
2650 } | |
2651 | |
2008 | 2652 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2654 InstructionMark im(this); | |
2655 emit_byte(0xF2); | |
2656 prefix(src, dst); | |
2657 emit_byte(0x0F); | |
2658 emit_byte(0x51); | |
2659 emit_operand(dst, src); | |
2660 } | |
2661 | |
2662 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
2663 // HMM Table D-1 says sse2 | |
2664 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2665 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2666 emit_byte(0xF3); | |
2667 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2668 emit_byte(0x0F); | |
2669 emit_byte(0x51); | |
2670 emit_byte(0xC0 | encode); | |
2671 } | |
2672 | |
2673 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
2674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2675 InstructionMark im(this); | |
2676 emit_byte(0xF3); | |
2677 prefix(src, dst); | |
2678 emit_byte(0x0F); | |
2679 emit_byte(0x51); | |
2680 emit_operand(dst, src); | |
2681 } | |
2682 | |
304 | 2683 void Assembler::stmxcsr( Address dst) { |
2684 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2685 InstructionMark im(this); | |
2686 prefix(dst); | |
2687 emit_byte(0x0F); | |
2688 emit_byte(0xAE); | |
2689 emit_operand(as_Register(3), dst); | |
2690 } | |
2691 | |
2692 void Assembler::subl(Address dst, int32_t imm32) { | |
2693 InstructionMark im(this); | |
2694 prefix(dst); | |
2695 if (is8bit(imm32)) { | |
2696 emit_byte(0x83); | |
2697 emit_operand(rbp, dst, 1); | |
2698 emit_byte(imm32 & 0xFF); | |
2699 } else { | |
2700 emit_byte(0x81); | |
2701 emit_operand(rbp, dst, 4); | |
2702 emit_long(imm32); | |
2703 } | |
2704 } | |
2705 | |
2706 void Assembler::subl(Register dst, int32_t imm32) { | |
2707 prefix(dst); | |
2708 emit_arith(0x81, 0xE8, dst, imm32); | |
2709 } | |
2710 | |
2711 void Assembler::subl(Address dst, Register src) { | |
2712 InstructionMark im(this); | |
2713 prefix(dst, src); | |
2714 emit_byte(0x29); | |
2715 emit_operand(src, dst); | |
2716 } | |
2717 | |
2718 void Assembler::subl(Register dst, Address src) { | |
2719 InstructionMark im(this); | |
2720 prefix(src, dst); | |
2721 emit_byte(0x2B); | |
2722 emit_operand(dst, src); | |
2723 } | |
2724 | |
2725 void Assembler::subl(Register dst, Register src) { | |
2726 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2727 emit_arith(0x2B, 0xC0, dst, src); | |
2728 } | |
2729 | |
2730 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2731 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2732 emit_byte(0xF2); | |
2733 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2734 emit_byte(0x0F); | |
2735 emit_byte(0x5C); | |
2736 emit_byte(0xC0 | encode); | |
2737 } | |
2738 | |
2739 void Assembler::subsd(XMMRegister dst, Address src) { | |
2740 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2741 InstructionMark im(this); | |
2742 emit_byte(0xF2); | |
2743 prefix(src, dst); | |
2744 emit_byte(0x0F); | |
2745 emit_byte(0x5C); | |
2746 emit_operand(dst, src); | |
2747 } | |
2748 | |
2749 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2750 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
0 | 2751 emit_byte(0xF3); |
304 | 2752 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2753 emit_byte(0x0F); | |
2754 emit_byte(0x5C); | |
2755 emit_byte(0xC0 | encode); | |
2756 } | |
2757 | |
2758 void Assembler::subss(XMMRegister dst, Address src) { | |
2759 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2760 InstructionMark im(this); | |
2761 emit_byte(0xF3); | |
2762 prefix(src, dst); | |
2763 emit_byte(0x0F); | |
2764 emit_byte(0x5C); | |
2765 emit_operand(dst, src); | |
2766 } | |
2767 | |
2768 void Assembler::testb(Register dst, int imm8) { | |
2769 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2770 (void) prefix_and_encode(dst->encoding(), true); | |
2771 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2772 } | |
2773 | |
2774 void Assembler::testl(Register dst, int32_t imm32) { | |
2775 // not using emit_arith because test | |
2776 // doesn't support sign-extension of | |
2777 // 8bit operands | |
2778 int encode = dst->encoding(); | |
2779 if (encode == 0) { | |
2780 emit_byte(0xA9); | |
2781 } else { | |
2782 encode = prefix_and_encode(encode); | |
2783 emit_byte(0xF7); | |
2784 emit_byte(0xC0 | encode); | |
2785 } | |
2786 emit_long(imm32); | |
2787 } | |
2788 | |
2789 void Assembler::testl(Register dst, Register src) { | |
2790 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2791 emit_arith(0x85, 0xC0, dst, src); | |
2792 } | |
2793 | |
2794 void Assembler::testl(Register dst, Address src) { | |
2795 InstructionMark im(this); | |
2796 prefix(src, dst); | |
2797 emit_byte(0x85); | |
2798 emit_operand(dst, src); | |
2799 } | |
2800 | |
2801 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
2802 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2803 emit_byte(0x66); | |
2804 ucomiss(dst, src); | |
2805 } | |
2806 | |
2807 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2808 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2809 emit_byte(0x66); | |
2810 ucomiss(dst, src); | |
2811 } | |
2812 | |
2813 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2814 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2815 | |
2816 InstructionMark im(this); | |
2817 prefix(src, dst); | |
2818 emit_byte(0x0F); | |
2819 emit_byte(0x2E); | |
2820 emit_operand(dst, src); | |
2821 } | |
2822 | |
2823 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2824 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2825 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2826 emit_byte(0x0F); | |
2827 emit_byte(0x2E); | |
2828 emit_byte(0xC0 | encode); | |
2829 } | |
2830 | |
2831 | |
2832 void Assembler::xaddl(Address dst, Register src) { | |
2833 InstructionMark im(this); | |
2834 prefix(dst, src); | |
0 | 2835 emit_byte(0x0F); |
304 | 2836 emit_byte(0xC1); |
2837 emit_operand(src, dst); | |
2838 } | |
2839 | |
2840 void Assembler::xchgl(Register dst, Address src) { // xchg | |
2841 InstructionMark im(this); | |
2842 prefix(src, dst); | |
2843 emit_byte(0x87); | |
2844 emit_operand(dst, src); | |
2845 } | |
2846 | |
2847 void Assembler::xchgl(Register dst, Register src) { | |
2848 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2849 emit_byte(0x87); | |
2850 emit_byte(0xc0 | encode); | |
2851 } | |
2852 | |
2853 void Assembler::xorl(Register dst, int32_t imm32) { | |
2854 prefix(dst); | |
2855 emit_arith(0x81, 0xF0, dst, imm32); | |
2856 } | |
2857 | |
2858 void Assembler::xorl(Register dst, Address src) { | |
2859 InstructionMark im(this); | |
2860 prefix(src, dst); | |
2861 emit_byte(0x33); | |
2862 emit_operand(dst, src); | |
2863 } | |
2864 | |
2865 void Assembler::xorl(Register dst, Register src) { | |
2866 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2867 emit_arith(0x33, 0xC0, dst, src); | |
2868 } | |
2869 | |
2870 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
2871 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2872 emit_byte(0x66); | |
2873 xorps(dst, src); | |
2874 } | |
2875 | |
2876 void Assembler::xorpd(XMMRegister dst, Address src) { | |
2877 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2878 InstructionMark im(this); | |
2879 emit_byte(0x66); | |
2880 prefix(src, dst); | |
2881 emit_byte(0x0F); | |
2882 emit_byte(0x57); | |
2883 emit_operand(dst, src); | |
2884 } | |
2885 | |
2886 | |
2887 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
2888 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2889 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2890 emit_byte(0x0F); | |
2891 emit_byte(0x57); | |
2892 emit_byte(0xC0 | encode); | |
2893 } | |
2894 | |
2895 void Assembler::xorps(XMMRegister dst, Address src) { | |
2896 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2897 InstructionMark im(this); | |
2898 prefix(src, dst); | |
2899 emit_byte(0x0F); | |
2900 emit_byte(0x57); | |
2901 emit_operand(dst, src); | |
2902 } | |
2903 | |
2904 #ifndef _LP64 | |
2905 // 32bit only pieces of the assembler | |
2906 | |
2907 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
2908 // NO PREFIX AS NEVER 64BIT | |
2909 InstructionMark im(this); | |
2910 emit_byte(0x81); | |
2911 emit_byte(0xF8 | src1->encoding()); | |
2912 emit_data(imm32, rspec, 0); | |
2913 } | |
2914 | |
2915 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
2916 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
2917 InstructionMark im(this); | |
2918 emit_byte(0x81); | |
2919 emit_operand(rdi, src1); | |
2920 emit_data(imm32, rspec, 0); | |
2921 } | |
2922 | |
2923 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
2924 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
2925 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
2926 void Assembler::cmpxchg8(Address adr) { | |
2927 InstructionMark im(this); | |
2928 emit_byte(0x0F); | |
2929 emit_byte(0xc7); | |
2930 emit_operand(rcx, adr); | |
2931 } | |
2932 | |
2933 void Assembler::decl(Register dst) { | |
2934 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
2935 emit_byte(0x48 | dst->encoding()); | |
2936 } | |
2937 | |
2938 #endif // _LP64 | |
2939 | |
2940 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
2941 | |
2942 void Assembler::fabs() { | |
2943 emit_byte(0xD9); | |
2944 emit_byte(0xE1); | |
2945 } | |
2946 | |
2947 void Assembler::fadd(int i) { | |
2948 emit_farith(0xD8, 0xC0, i); | |
2949 } | |
2950 | |
2951 void Assembler::fadd_d(Address src) { | |
2952 InstructionMark im(this); | |
2953 emit_byte(0xDC); | |
2954 emit_operand32(rax, src); | |
2955 } | |
2956 | |
2957 void Assembler::fadd_s(Address src) { | |
2958 InstructionMark im(this); | |
2959 emit_byte(0xD8); | |
2960 emit_operand32(rax, src); | |
2961 } | |
2962 | |
2963 void Assembler::fadda(int i) { | |
2964 emit_farith(0xDC, 0xC0, i); | |
2965 } | |
2966 | |
2967 void Assembler::faddp(int i) { | |
2968 emit_farith(0xDE, 0xC0, i); | |
2969 } | |
2970 | |
2971 void Assembler::fchs() { | |
2972 emit_byte(0xD9); | |
2973 emit_byte(0xE0); | |
2974 } | |
2975 | |
2976 void Assembler::fcom(int i) { | |
2977 emit_farith(0xD8, 0xD0, i); | |
2978 } | |
2979 | |
2980 void Assembler::fcomp(int i) { | |
2981 emit_farith(0xD8, 0xD8, i); | |
2982 } | |
2983 | |
2984 void Assembler::fcomp_d(Address src) { | |
2985 InstructionMark im(this); | |
2986 emit_byte(0xDC); | |
2987 emit_operand32(rbx, src); | |
2988 } | |
2989 | |
2990 void Assembler::fcomp_s(Address src) { | |
2991 InstructionMark im(this); | |
2992 emit_byte(0xD8); | |
2993 emit_operand32(rbx, src); | |
2994 } | |
2995 | |
2996 void Assembler::fcompp() { | |
2997 emit_byte(0xDE); | |
2998 emit_byte(0xD9); | |
2999 } | |
3000 | |
3001 void Assembler::fcos() { | |
3002 emit_byte(0xD9); | |
0 | 3003 emit_byte(0xFF); |
304 | 3004 } |
3005 | |
3006 void Assembler::fdecstp() { | |
3007 emit_byte(0xD9); | |
3008 emit_byte(0xF6); | |
3009 } | |
3010 | |
3011 void Assembler::fdiv(int i) { | |
3012 emit_farith(0xD8, 0xF0, i); | |
3013 } | |
3014 | |
3015 void Assembler::fdiv_d(Address src) { | |
3016 InstructionMark im(this); | |
3017 emit_byte(0xDC); | |
3018 emit_operand32(rsi, src); | |
3019 } | |
3020 | |
3021 void Assembler::fdiv_s(Address src) { | |
3022 InstructionMark im(this); | |
3023 emit_byte(0xD8); | |
3024 emit_operand32(rsi, src); | |
3025 } | |
3026 | |
3027 void Assembler::fdiva(int i) { | |
3028 emit_farith(0xDC, 0xF8, i); | |
3029 } | |
3030 | |
3031 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
3032 // is erroneous for some of the floating-point instructions below. | |
3033 | |
3034 void Assembler::fdivp(int i) { | |
3035 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
3036 } | |
3037 | |
3038 void Assembler::fdivr(int i) { | |
3039 emit_farith(0xD8, 0xF8, i); | |
3040 } | |
3041 | |
3042 void Assembler::fdivr_d(Address src) { | |
3043 InstructionMark im(this); | |
3044 emit_byte(0xDC); | |
3045 emit_operand32(rdi, src); | |
3046 } | |
3047 | |
3048 void Assembler::fdivr_s(Address src) { | |
3049 InstructionMark im(this); | |
3050 emit_byte(0xD8); | |
3051 emit_operand32(rdi, src); | |
3052 } | |
3053 | |
3054 void Assembler::fdivra(int i) { | |
3055 emit_farith(0xDC, 0xF0, i); | |
3056 } | |
3057 | |
3058 void Assembler::fdivrp(int i) { | |
3059 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
3060 } | |
3061 | |
3062 void Assembler::ffree(int i) { | |
3063 emit_farith(0xDD, 0xC0, i); | |
3064 } | |
3065 | |
3066 void Assembler::fild_d(Address adr) { | |
3067 InstructionMark im(this); | |
3068 emit_byte(0xDF); | |
3069 emit_operand32(rbp, adr); | |
3070 } | |
3071 | |
3072 void Assembler::fild_s(Address adr) { | |
3073 InstructionMark im(this); | |
3074 emit_byte(0xDB); | |
3075 emit_operand32(rax, adr); | |
3076 } | |
3077 | |
3078 void Assembler::fincstp() { | |
3079 emit_byte(0xD9); | |
3080 emit_byte(0xF7); | |
3081 } | |
3082 | |
3083 void Assembler::finit() { | |
3084 emit_byte(0x9B); | |
3085 emit_byte(0xDB); | |
3086 emit_byte(0xE3); | |
3087 } | |
3088 | |
3089 void Assembler::fist_s(Address adr) { | |
3090 InstructionMark im(this); | |
3091 emit_byte(0xDB); | |
3092 emit_operand32(rdx, adr); | |
3093 } | |
3094 | |
3095 void Assembler::fistp_d(Address adr) { | |
3096 InstructionMark im(this); | |
3097 emit_byte(0xDF); | |
3098 emit_operand32(rdi, adr); | |
3099 } | |
3100 | |
3101 void Assembler::fistp_s(Address adr) { | |
3102 InstructionMark im(this); | |
3103 emit_byte(0xDB); | |
3104 emit_operand32(rbx, adr); | |
3105 } | |
0 | 3106 |
3107 void Assembler::fld1() { | |
3108 emit_byte(0xD9); | |
3109 emit_byte(0xE8); | |
3110 } | |
3111 | |
304 | 3112 void Assembler::fld_d(Address adr) { |
3113 InstructionMark im(this); | |
3114 emit_byte(0xDD); | |
3115 emit_operand32(rax, adr); | |
3116 } | |
0 | 3117 |
3118 void Assembler::fld_s(Address adr) { | |
3119 InstructionMark im(this); | |
3120 emit_byte(0xD9); | |
304 | 3121 emit_operand32(rax, adr); |
3122 } | |
3123 | |
3124 | |
3125 void Assembler::fld_s(int index) { | |
0 | 3126 emit_farith(0xD9, 0xC0, index); |
3127 } | |
3128 | |
3129 void Assembler::fld_x(Address adr) { | |
3130 InstructionMark im(this); | |
3131 emit_byte(0xDB); | |
304 | 3132 emit_operand32(rbp, adr); |
3133 } | |
3134 | |
3135 void Assembler::fldcw(Address src) { | |
3136 InstructionMark im(this); | |
3137 emit_byte(0xd9); | |
3138 emit_operand32(rbp, src); | |
3139 } | |
3140 | |
3141 void Assembler::fldenv(Address src) { | |
0 | 3142 InstructionMark im(this); |
3143 emit_byte(0xD9); | |
304 | 3144 emit_operand32(rsp, src); |
3145 } | |
3146 | |
3147 void Assembler::fldlg2() { | |
0 | 3148 emit_byte(0xD9); |
304 | 3149 emit_byte(0xEC); |
3150 } | |
0 | 3151 |
3152 void Assembler::fldln2() { | |
3153 emit_byte(0xD9); | |
3154 emit_byte(0xED); | |
3155 } | |
3156 | |
304 | 3157 void Assembler::fldz() { |
0 | 3158 emit_byte(0xD9); |
304 | 3159 emit_byte(0xEE); |
3160 } | |
0 | 3161 |
3162 void Assembler::flog() { | |
3163 fldln2(); | |
3164 fxch(); | |
3165 fyl2x(); | |
3166 } | |
3167 | |
3168 void Assembler::flog10() { | |
3169 fldlg2(); | |
3170 fxch(); | |
3171 fyl2x(); | |
3172 } | |
3173 | |
304 | 3174 void Assembler::fmul(int i) { |
3175 emit_farith(0xD8, 0xC8, i); | |
3176 } | |
3177 | |
3178 void Assembler::fmul_d(Address src) { | |
3179 InstructionMark im(this); | |
3180 emit_byte(0xDC); | |
3181 emit_operand32(rcx, src); | |
3182 } | |
3183 | |
3184 void Assembler::fmul_s(Address src) { | |
3185 InstructionMark im(this); | |
3186 emit_byte(0xD8); | |
3187 emit_operand32(rcx, src); | |
3188 } | |
3189 | |
3190 void Assembler::fmula(int i) { | |
3191 emit_farith(0xDC, 0xC8, i); | |
3192 } | |
3193 | |
3194 void Assembler::fmulp(int i) { | |
3195 emit_farith(0xDE, 0xC8, i); | |
3196 } | |
3197 | |
3198 void Assembler::fnsave(Address dst) { | |
3199 InstructionMark im(this); | |
3200 emit_byte(0xDD); | |
3201 emit_operand32(rsi, dst); | |
3202 } | |
3203 | |
3204 void Assembler::fnstcw(Address src) { | |
3205 InstructionMark im(this); | |
3206 emit_byte(0x9B); | |
3207 emit_byte(0xD9); | |
3208 emit_operand32(rdi, src); | |
3209 } | |
3210 | |
3211 void Assembler::fnstsw_ax() { | |
3212 emit_byte(0xdF); | |
3213 emit_byte(0xE0); | |
3214 } | |
3215 | |
3216 void Assembler::fprem() { | |
3217 emit_byte(0xD9); | |
3218 emit_byte(0xF8); | |
3219 } | |
3220 | |
3221 void Assembler::fprem1() { | |
3222 emit_byte(0xD9); | |
3223 emit_byte(0xF5); | |
3224 } | |
3225 | |
3226 void Assembler::frstor(Address src) { | |
3227 InstructionMark im(this); | |
3228 emit_byte(0xDD); | |
3229 emit_operand32(rsp, src); | |
3230 } | |
0 | 3231 |
3232 void Assembler::fsin() { | |
3233 emit_byte(0xD9); | |
3234 emit_byte(0xFE); | |
3235 } | |
3236 | |
304 | 3237 void Assembler::fsqrt() { |
3238 emit_byte(0xD9); | |
3239 emit_byte(0xFA); | |
3240 } | |
3241 | |
3242 void Assembler::fst_d(Address adr) { | |
3243 InstructionMark im(this); | |
3244 emit_byte(0xDD); | |
3245 emit_operand32(rdx, adr); | |
3246 } | |
3247 | |
3248 void Assembler::fst_s(Address adr) { | |
3249 InstructionMark im(this); | |
3250 emit_byte(0xD9); | |
3251 emit_operand32(rdx, adr); | |
3252 } | |
3253 | |
3254 void Assembler::fstp_d(Address adr) { | |
3255 InstructionMark im(this); | |
3256 emit_byte(0xDD); | |
3257 emit_operand32(rbx, adr); | |
3258 } | |
3259 | |
3260 void Assembler::fstp_d(int index) { | |
3261 emit_farith(0xDD, 0xD8, index); | |
3262 } | |
3263 | |
3264 void Assembler::fstp_s(Address adr) { | |
3265 InstructionMark im(this); | |
0 | 3266 emit_byte(0xD9); |
304 | 3267 emit_operand32(rbx, adr); |
3268 } | |
3269 | |
3270 void Assembler::fstp_x(Address adr) { | |
3271 InstructionMark im(this); | |
3272 emit_byte(0xDB); | |
3273 emit_operand32(rdi, adr); | |
3274 } | |
3275 | |
3276 void Assembler::fsub(int i) { | |
3277 emit_farith(0xD8, 0xE0, i); | |
3278 } | |
3279 | |
3280 void Assembler::fsub_d(Address src) { | |
3281 InstructionMark im(this); | |
3282 emit_byte(0xDC); | |
3283 emit_operand32(rsp, src); | |
3284 } | |
3285 | |
3286 void Assembler::fsub_s(Address src) { | |
3287 InstructionMark im(this); | |
3288 emit_byte(0xD8); | |
3289 emit_operand32(rsp, src); | |
3290 } | |
3291 | |
3292 void Assembler::fsuba(int i) { | |
3293 emit_farith(0xDC, 0xE8, i); | |
3294 } | |
3295 | |
3296 void Assembler::fsubp(int i) { | |
3297 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
3298 } | |
3299 | |
3300 void Assembler::fsubr(int i) { | |
3301 emit_farith(0xD8, 0xE8, i); | |
3302 } | |
3303 | |
3304 void Assembler::fsubr_d(Address src) { | |
3305 InstructionMark im(this); | |
3306 emit_byte(0xDC); | |
3307 emit_operand32(rbp, src); | |
3308 } | |
3309 | |
3310 void Assembler::fsubr_s(Address src) { | |
3311 InstructionMark im(this); | |
3312 emit_byte(0xD8); | |
3313 emit_operand32(rbp, src); | |
3314 } | |
3315 | |
3316 void Assembler::fsubra(int i) { | |
3317 emit_farith(0xDC, 0xE0, i); | |
3318 } | |
3319 | |
3320 void Assembler::fsubrp(int i) { | |
3321 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 3322 } |
3323 | |
3324 void Assembler::ftan() { | |
3325 emit_byte(0xD9); | |
3326 emit_byte(0xF2); | |
3327 emit_byte(0xDD); | |
3328 emit_byte(0xD8); | |
3329 } | |
3330 | |
304 | 3331 void Assembler::ftst() { |
0 | 3332 emit_byte(0xD9); |
304 | 3333 emit_byte(0xE4); |
3334 } | |
0 | 3335 |
3336 void Assembler::fucomi(int i) { | |
3337 // make sure the instruction is supported (introduced for P6, together with cmov) | |
3338 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
3339 emit_farith(0xDB, 0xE8, i); | |
3340 } | |
3341 | |
3342 void Assembler::fucomip(int i) { | |
3343 // make sure the instruction is supported (introduced for P6, together with cmov) | |
3344 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
3345 emit_farith(0xDF, 0xE8, i); | |
3346 } | |
3347 | |
3348 void Assembler::fwait() { | |
3349 emit_byte(0x9B); | |
3350 } | |
3351 | |
304 | 3352 void Assembler::fxch(int i) { |
3353 emit_farith(0xD9, 0xC8, i); | |
3354 } | |
3355 | |
3356 void Assembler::fyl2x() { | |
0 | 3357 emit_byte(0xD9); |
304 | 3358 emit_byte(0xF1); |
3359 } | |
3360 | |
3361 | |
3362 #ifndef _LP64 | |
3363 | |
3364 void Assembler::incl(Register dst) { | |
3365 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
3366 emit_byte(0x40 | dst->encoding()); | |
3367 } | |
3368 | |
3369 void Assembler::lea(Register dst, Address src) { | |
3370 leal(dst, src); | |
3371 } | |
3372 | |
3373 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
3374 InstructionMark im(this); | |
3375 emit_byte(0xC7); | |
3376 emit_operand(rax, dst); | |
3377 emit_data((int)imm32, rspec, 0); | |
3378 } | |
3379 | |
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3380 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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3381 InstructionMark im(this); |
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3382 int encode = prefix_and_encode(dst->encoding()); |
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3383 emit_byte(0xB8 | encode); |
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3384 emit_data((int)imm32, rspec, 0); |
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3385 } |
304 | 3386 |
3387 void Assembler::popa() { // 32bit | |
3388 emit_byte(0x61); | |
3389 } | |
3390 | |
3391 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
3392 InstructionMark im(this); | |
3393 emit_byte(0x68); | |
3394 emit_data(imm32, rspec, 0); | |
3395 } | |
3396 | |
3397 void Assembler::pusha() { // 32bit | |
3398 emit_byte(0x60); | |
3399 } | |
3400 | |
3401 void Assembler::set_byte_if_not_zero(Register dst) { | |
0 | 3402 emit_byte(0x0F); |
304 | 3403 emit_byte(0x95); |
3404 emit_byte(0xE0 | dst->encoding()); | |
3405 } | |
3406 | |
3407 void Assembler::shldl(Register dst, Register src) { | |
0 | 3408 emit_byte(0x0F); |
304 | 3409 emit_byte(0xA5); |
3410 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
3411 } | |
3412 | |
3413 void Assembler::shrdl(Register dst, Register src) { | |
0 | 3414 emit_byte(0x0F); |
304 | 3415 emit_byte(0xAD); |
3416 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
3417 } | |
3418 | |
3419 #else // LP64 | |
3420 | |
1369 | 3421 void Assembler::set_byte_if_not_zero(Register dst) { |
3422 int enc = prefix_and_encode(dst->encoding(), true); | |
3423 emit_byte(0x0F); | |
3424 emit_byte(0x95); | |
3425 emit_byte(0xE0 | enc); | |
3426 } | |
3427 | |
304 | 3428 // 64bit only pieces of the assembler |
3429 // This should only be used by 64bit instructions that can use rip-relative | |
3430 // it cannot be used by instructions that want an immediate value. | |
3431 | |
3432 bool Assembler::reachable(AddressLiteral adr) { | |
3433 int64_t disp; | |
3434 // None will force a 64bit literal to the code stream. Likely a placeholder | |
3435 // for something that will be patched later and we need to certain it will | |
3436 // always be reachable. | |
3437 if (adr.reloc() == relocInfo::none) { | |
3438 return false; | |
3439 } | |
3440 if (adr.reloc() == relocInfo::internal_word_type) { | |
3441 // This should be rip relative and easily reachable. | |
3442 return true; | |
3443 } | |
3444 if (adr.reloc() == relocInfo::virtual_call_type || | |
3445 adr.reloc() == relocInfo::opt_virtual_call_type || | |
3446 adr.reloc() == relocInfo::static_call_type || | |
3447 adr.reloc() == relocInfo::static_stub_type ) { | |
3448 // This should be rip relative within the code cache and easily | |
3449 // reachable until we get huge code caches. (At which point | |
3450 // ic code is going to have issues). | |
3451 return true; | |
3452 } | |
3453 if (adr.reloc() != relocInfo::external_word_type && | |
3454 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
3455 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
3456 adr.reloc() != relocInfo::runtime_call_type ) { | |
3457 return false; | |
3458 } | |
3459 | |
3460 // Stress the correction code | |
3461 if (ForceUnreachable) { | |
3462 // Must be runtimecall reloc, see if it is in the codecache | |
3463 // Flipping stuff in the codecache to be unreachable causes issues | |
3464 // with things like inline caches where the additional instructions | |
3465 // are not handled. | |
3466 if (CodeCache::find_blob(adr._target) == NULL) { | |
3467 return false; | |
3468 } | |
3469 } | |
3470 // For external_word_type/runtime_call_type if it is reachable from where we | |
3471 // are now (possibly a temp buffer) and where we might end up | |
3472 // anywhere in the codeCache then we are always reachable. | |
3473 // This would have to change if we ever save/restore shared code | |
3474 // to be more pessimistic. | |
3475 | |
3476 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
3477 if (!is_simm32(disp)) return false; | |
3478 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
3479 if (!is_simm32(disp)) return false; | |
3480 | |
3481 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
3482 | |
3483 // Because rip relative is a disp + address_of_next_instruction and we | |
3484 // don't know the value of address_of_next_instruction we apply a fudge factor | |
3485 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
3486 // We don't have to fudge the checks above here because they are already worst case. | |
3487 | |
3488 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
3489 // + 4 because better safe than sorry. | |
3490 const int fudge = 12 + 4; | |
3491 if (disp < 0) { | |
3492 disp -= fudge; | |
3493 } else { | |
3494 disp += fudge; | |
3495 } | |
3496 return is_simm32(disp); | |
3497 } | |
3498 | |
3499 void Assembler::emit_data64(jlong data, | |
3500 relocInfo::relocType rtype, | |
3501 int format) { | |
3502 if (rtype == relocInfo::none) { | |
3503 emit_long64(data); | |
3504 } else { | |
3505 emit_data64(data, Relocation::spec_simple(rtype), format); | |
3506 } | |
3507 } | |
3508 | |
3509 void Assembler::emit_data64(jlong data, | |
3510 RelocationHolder const& rspec, | |
3511 int format) { | |
3512 assert(imm_operand == 0, "default format must be immediate in this file"); | |
3513 assert(imm_operand == format, "must be immediate"); | |
3514 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
3515 // Do not use AbstractAssembler::relocate, which is not intended for | |
3516 // embedded words. Instead, relocate to the enclosing instruction. | |
3517 code_section()->relocate(inst_mark(), rspec, format); | |
3518 #ifdef ASSERT | |
3519 check_relocation(rspec, format); | |
3520 #endif | |
3521 emit_long64(data); | |
3522 } | |
3523 | |
3524 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
3525 if (reg_enc >= 8) { | |
3526 prefix(REX_B); | |
3527 reg_enc -= 8; | |
3528 } else if (byteinst && reg_enc >= 4) { | |
3529 prefix(REX); | |
3530 } | |
3531 return reg_enc; | |
3532 } | |
3533 | |
3534 int Assembler::prefixq_and_encode(int reg_enc) { | |
3535 if (reg_enc < 8) { | |
3536 prefix(REX_W); | |
3537 } else { | |
3538 prefix(REX_WB); | |
3539 reg_enc -= 8; | |
3540 } | |
3541 return reg_enc; | |
3542 } | |
3543 | |
3544 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
3545 if (dst_enc < 8) { | |
3546 if (src_enc >= 8) { | |
3547 prefix(REX_B); | |
3548 src_enc -= 8; | |
3549 } else if (byteinst && src_enc >= 4) { | |
3550 prefix(REX); | |
3551 } | |
3552 } else { | |
3553 if (src_enc < 8) { | |
3554 prefix(REX_R); | |
3555 } else { | |
3556 prefix(REX_RB); | |
3557 src_enc -= 8; | |
3558 } | |
3559 dst_enc -= 8; | |
3560 } | |
3561 return dst_enc << 3 | src_enc; | |
3562 } | |
3563 | |
3564 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
3565 if (dst_enc < 8) { | |
3566 if (src_enc < 8) { | |
3567 prefix(REX_W); | |
3568 } else { | |
3569 prefix(REX_WB); | |
3570 src_enc -= 8; | |
3571 } | |
3572 } else { | |
3573 if (src_enc < 8) { | |
3574 prefix(REX_WR); | |
3575 } else { | |
3576 prefix(REX_WRB); | |
3577 src_enc -= 8; | |
3578 } | |
3579 dst_enc -= 8; | |
3580 } | |
3581 return dst_enc << 3 | src_enc; | |
3582 } | |
3583 | |
3584 void Assembler::prefix(Register reg) { | |
3585 if (reg->encoding() >= 8) { | |
3586 prefix(REX_B); | |
3587 } | |
3588 } | |
3589 | |
3590 void Assembler::prefix(Address adr) { | |
3591 if (adr.base_needs_rex()) { | |
3592 if (adr.index_needs_rex()) { | |
3593 prefix(REX_XB); | |
3594 } else { | |
3595 prefix(REX_B); | |
3596 } | |
3597 } else { | |
3598 if (adr.index_needs_rex()) { | |
3599 prefix(REX_X); | |
3600 } | |
3601 } | |
3602 } | |
3603 | |
3604 void Assembler::prefixq(Address adr) { | |
3605 if (adr.base_needs_rex()) { | |
3606 if (adr.index_needs_rex()) { | |
3607 prefix(REX_WXB); | |
3608 } else { | |
3609 prefix(REX_WB); | |
3610 } | |
3611 } else { | |
3612 if (adr.index_needs_rex()) { | |
3613 prefix(REX_WX); | |
3614 } else { | |
3615 prefix(REX_W); | |
3616 } | |
3617 } | |
3618 } | |
3619 | |
3620 | |
3621 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
3622 if (reg->encoding() < 8) { | |
3623 if (adr.base_needs_rex()) { | |
3624 if (adr.index_needs_rex()) { | |
3625 prefix(REX_XB); | |
3626 } else { | |
3627 prefix(REX_B); | |
3628 } | |
3629 } else { | |
3630 if (adr.index_needs_rex()) { | |
3631 prefix(REX_X); | |
3632 } else if (reg->encoding() >= 4 ) { | |
3633 prefix(REX); | |
3634 } | |
3635 } | |
3636 } else { | |
3637 if (adr.base_needs_rex()) { | |
3638 if (adr.index_needs_rex()) { | |
3639 prefix(REX_RXB); | |
3640 } else { | |
3641 prefix(REX_RB); | |
3642 } | |
3643 } else { | |
3644 if (adr.index_needs_rex()) { | |
3645 prefix(REX_RX); | |
3646 } else { | |
3647 prefix(REX_R); | |
3648 } | |
3649 } | |
3650 } | |
3651 } | |
3652 | |
3653 void Assembler::prefixq(Address adr, Register src) { | |
3654 if (src->encoding() < 8) { | |
3655 if (adr.base_needs_rex()) { | |
3656 if (adr.index_needs_rex()) { | |
3657 prefix(REX_WXB); | |
3658 } else { | |
3659 prefix(REX_WB); | |
3660 } | |
3661 } else { | |
3662 if (adr.index_needs_rex()) { | |
3663 prefix(REX_WX); | |
3664 } else { | |
3665 prefix(REX_W); | |
3666 } | |
3667 } | |
3668 } else { | |
3669 if (adr.base_needs_rex()) { | |
3670 if (adr.index_needs_rex()) { | |
3671 prefix(REX_WRXB); | |
3672 } else { | |
3673 prefix(REX_WRB); | |
3674 } | |
3675 } else { | |
3676 if (adr.index_needs_rex()) { | |
3677 prefix(REX_WRX); | |
3678 } else { | |
3679 prefix(REX_WR); | |
3680 } | |
3681 } | |
3682 } | |
3683 } | |
3684 | |
3685 void Assembler::prefix(Address adr, XMMRegister reg) { | |
3686 if (reg->encoding() < 8) { | |
3687 if (adr.base_needs_rex()) { | |
3688 if (adr.index_needs_rex()) { | |
3689 prefix(REX_XB); | |
3690 } else { | |
3691 prefix(REX_B); | |
3692 } | |
3693 } else { | |
3694 if (adr.index_needs_rex()) { | |
3695 prefix(REX_X); | |
3696 } | |
3697 } | |
3698 } else { | |
3699 if (adr.base_needs_rex()) { | |
3700 if (adr.index_needs_rex()) { | |
3701 prefix(REX_RXB); | |
3702 } else { | |
3703 prefix(REX_RB); | |
3704 } | |
3705 } else { | |
3706 if (adr.index_needs_rex()) { | |
3707 prefix(REX_RX); | |
3708 } else { | |
3709 prefix(REX_R); | |
3710 } | |
3711 } | |
3712 } | |
3713 } | |
3714 | |
3715 void Assembler::adcq(Register dst, int32_t imm32) { | |
3716 (void) prefixq_and_encode(dst->encoding()); | |
3717 emit_arith(0x81, 0xD0, dst, imm32); | |
3718 } | |
3719 | |
3720 void Assembler::adcq(Register dst, Address src) { | |
3721 InstructionMark im(this); | |
3722 prefixq(src, dst); | |
3723 emit_byte(0x13); | |
3724 emit_operand(dst, src); | |
3725 } | |
3726 | |
3727 void Assembler::adcq(Register dst, Register src) { | |
3728 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3729 emit_arith(0x13, 0xC0, dst, src); | |
3730 } | |
3731 | |
3732 void Assembler::addq(Address dst, int32_t imm32) { | |
3733 InstructionMark im(this); | |
3734 prefixq(dst); | |
3735 emit_arith_operand(0x81, rax, dst,imm32); | |
3736 } | |
3737 | |
3738 void Assembler::addq(Address dst, Register src) { | |
3739 InstructionMark im(this); | |
3740 prefixq(dst, src); | |
3741 emit_byte(0x01); | |
3742 emit_operand(src, dst); | |
3743 } | |
3744 | |
3745 void Assembler::addq(Register dst, int32_t imm32) { | |
3746 (void) prefixq_and_encode(dst->encoding()); | |
3747 emit_arith(0x81, 0xC0, dst, imm32); | |
3748 } | |
3749 | |
3750 void Assembler::addq(Register dst, Address src) { | |
3751 InstructionMark im(this); | |
3752 prefixq(src, dst); | |
3753 emit_byte(0x03); | |
3754 emit_operand(dst, src); | |
3755 } | |
3756 | |
3757 void Assembler::addq(Register dst, Register src) { | |
3758 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3759 emit_arith(0x03, 0xC0, dst, src); | |
3760 } | |
3761 | |
3762 void Assembler::andq(Register dst, int32_t imm32) { | |
3763 (void) prefixq_and_encode(dst->encoding()); | |
3764 emit_arith(0x81, 0xE0, dst, imm32); | |
3765 } | |
3766 | |
3767 void Assembler::andq(Register dst, Address src) { | |
3768 InstructionMark im(this); | |
3769 prefixq(src, dst); | |
3770 emit_byte(0x23); | |
3771 emit_operand(dst, src); | |
3772 } | |
3773 | |
3774 void Assembler::andq(Register dst, Register src) { | |
3775 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3776 emit_arith(0x23, 0xC0, dst, src); | |
3777 } | |
3778 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3779 void Assembler::bsfq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3780 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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changeset
|
3781 emit_byte(0x0F); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3782 emit_byte(0xBC); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3783 emit_byte(0xC0 | encode); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3784 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
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diff
changeset
|
3785 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3786 void Assembler::bsrq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3787 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3788 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3789 emit_byte(0x0F); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3790 emit_byte(0xBD); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3791 emit_byte(0xC0 | encode); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3792 } |
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diff
changeset
|
3793 |
304 | 3794 void Assembler::bswapq(Register reg) { |
3795 int encode = prefixq_and_encode(reg->encoding()); | |
3796 emit_byte(0x0F); | |
3797 emit_byte(0xC8 | encode); | |
3798 } | |
3799 | |
3800 void Assembler::cdqq() { | |
3801 prefix(REX_W); | |
3802 emit_byte(0x99); | |
3803 } | |
3804 | |
3805 void Assembler::clflush(Address adr) { | |
3806 prefix(adr); | |
3807 emit_byte(0x0F); | |
3808 emit_byte(0xAE); | |
3809 emit_operand(rdi, adr); | |
3810 } | |
3811 | |
3812 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
3813 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3814 emit_byte(0x0F); | |
3815 emit_byte(0x40 | cc); | |
3816 emit_byte(0xC0 | encode); | |
3817 } | |
3818 | |
3819 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
3820 InstructionMark im(this); | |
3821 prefixq(src, dst); | |
3822 emit_byte(0x0F); | |
3823 emit_byte(0x40 | cc); | |
3824 emit_operand(dst, src); | |
3825 } | |
3826 | |
3827 void Assembler::cmpq(Address dst, int32_t imm32) { | |
3828 InstructionMark im(this); | |
3829 prefixq(dst); | |
3830 emit_byte(0x81); | |
3831 emit_operand(rdi, dst, 4); | |
3832 emit_long(imm32); | |
3833 } | |
3834 | |
3835 void Assembler::cmpq(Register dst, int32_t imm32) { | |
3836 (void) prefixq_and_encode(dst->encoding()); | |
3837 emit_arith(0x81, 0xF8, dst, imm32); | |
3838 } | |
3839 | |
3840 void Assembler::cmpq(Address dst, Register src) { | |
3841 InstructionMark im(this); | |
3842 prefixq(dst, src); | |
3843 emit_byte(0x3B); | |
3844 emit_operand(src, dst); | |
3845 } | |
3846 | |
3847 void Assembler::cmpq(Register dst, Register src) { | |
3848 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3849 emit_arith(0x3B, 0xC0, dst, src); | |
3850 } | |
3851 | |
3852 void Assembler::cmpq(Register dst, Address src) { | |
3853 InstructionMark im(this); | |
3854 prefixq(src, dst); | |
3855 emit_byte(0x3B); | |
3856 emit_operand(dst, src); | |
3857 } | |
3858 | |
3859 void Assembler::cmpxchgq(Register reg, Address adr) { | |
3860 InstructionMark im(this); | |
3861 prefixq(adr, reg); | |
3862 emit_byte(0x0F); | |
3863 emit_byte(0xB1); | |
3864 emit_operand(reg, adr); | |
3865 } | |
3866 | |
3867 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
3868 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3869 emit_byte(0xF2); | |
3870 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3871 emit_byte(0x0F); | |
3872 emit_byte(0x2A); | |
3873 emit_byte(0xC0 | encode); | |
3874 } | |
3875 | |
3876 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
3877 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3878 emit_byte(0xF3); | |
3879 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3880 emit_byte(0x0F); | |
3881 emit_byte(0x2A); | |
3882 emit_byte(0xC0 | encode); | |
3883 } | |
3884 | |
3885 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
3886 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3887 emit_byte(0xF2); | |
3888 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3889 emit_byte(0x0F); | |
3890 emit_byte(0x2C); | |
3891 emit_byte(0xC0 | encode); | |
3892 } | |
3893 | |
3894 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
3895 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3896 emit_byte(0xF3); | |
3897 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3898 emit_byte(0x0F); | |
3899 emit_byte(0x2C); | |
3900 emit_byte(0xC0 | encode); | |
3901 } | |
3902 | |
3903 void Assembler::decl(Register dst) { | |
3904 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
3905 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
3906 int encode = prefix_and_encode(dst->encoding()); | |
3907 emit_byte(0xFF); | |
3908 emit_byte(0xC8 | encode); | |
3909 } | |
3910 | |
3911 void Assembler::decq(Register dst) { | |
3912 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
3913 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3914 int encode = prefixq_and_encode(dst->encoding()); | |
3915 emit_byte(0xFF); | |
3916 emit_byte(0xC8 | encode); | |
3917 } | |
3918 | |
3919 void Assembler::decq(Address dst) { | |
3920 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
3921 InstructionMark im(this); | |
3922 prefixq(dst); | |
3923 emit_byte(0xFF); | |
3924 emit_operand(rcx, dst); | |
3925 } | |
3926 | |
3927 void Assembler::fxrstor(Address src) { | |
3928 prefixq(src); | |
3929 emit_byte(0x0F); | |
3930 emit_byte(0xAE); | |
3931 emit_operand(as_Register(1), src); | |
3932 } | |
3933 | |
3934 void Assembler::fxsave(Address dst) { | |
3935 prefixq(dst); | |
3936 emit_byte(0x0F); | |
3937 emit_byte(0xAE); | |
3938 emit_operand(as_Register(0), dst); | |
3939 } | |
3940 | |
3941 void Assembler::idivq(Register src) { | |
3942 int encode = prefixq_and_encode(src->encoding()); | |
3943 emit_byte(0xF7); | |
3944 emit_byte(0xF8 | encode); | |
3945 } | |
3946 | |
3947 void Assembler::imulq(Register dst, Register src) { | |
3948 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3949 emit_byte(0x0F); | |
3950 emit_byte(0xAF); | |
3951 emit_byte(0xC0 | encode); | |
3952 } | |
3953 | |
3954 void Assembler::imulq(Register dst, Register src, int value) { | |
3955 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3956 if (is8bit(value)) { | |
3957 emit_byte(0x6B); | |
3958 emit_byte(0xC0 | encode); | |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1846
diff
changeset
|
3959 emit_byte(value & 0xFF); |
304 | 3960 } else { |
3961 emit_byte(0x69); | |
3962 emit_byte(0xC0 | encode); | |
3963 emit_long(value); | |
3964 } | |
3965 } | |
3966 | |
3967 void Assembler::incl(Register dst) { | |
3968 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
3969 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3970 int encode = prefix_and_encode(dst->encoding()); | |
3971 emit_byte(0xFF); | |
3972 emit_byte(0xC0 | encode); | |
3973 } | |
3974 | |
3975 void Assembler::incq(Register dst) { | |
3976 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
3977 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3978 int encode = prefixq_and_encode(dst->encoding()); | |
3979 emit_byte(0xFF); | |
3980 emit_byte(0xC0 | encode); | |
3981 } | |
3982 | |
3983 void Assembler::incq(Address dst) { | |
3984 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
3985 InstructionMark im(this); | |
3986 prefixq(dst); | |
3987 emit_byte(0xFF); | |
3988 emit_operand(rax, dst); | |
3989 } | |
3990 | |
3991 void Assembler::lea(Register dst, Address src) { | |
3992 leaq(dst, src); | |
3993 } | |
3994 | |
3995 void Assembler::leaq(Register dst, Address src) { | |
3996 InstructionMark im(this); | |
3997 prefixq(src, dst); | |
3998 emit_byte(0x8D); | |
3999 emit_operand(dst, src); | |
4000 } | |
4001 | |
4002 void Assembler::mov64(Register dst, int64_t imm64) { | |
4003 InstructionMark im(this); | |
4004 int encode = prefixq_and_encode(dst->encoding()); | |
4005 emit_byte(0xB8 | encode); | |
4006 emit_long64(imm64); | |
4007 } | |
4008 | |
4009 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
4010 InstructionMark im(this); | |
4011 int encode = prefixq_and_encode(dst->encoding()); | |
4012 emit_byte(0xB8 | encode); | |
4013 emit_data64(imm64, rspec); | |
4014 } | |
4015 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
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|
4016 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
4017 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4018 int encode = prefix_and_encode(dst->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4019 emit_byte(0xB8 | encode); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4020 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
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|
4021 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
4022 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4023 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4024 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4025 prefix(dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4026 emit_byte(0xC7); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4027 emit_operand(rax, dst, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4028 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4029 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
4030 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4031 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4032 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4033 int encode = prefix_and_encode(src1->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
4034 emit_byte(0x81); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
4035 emit_byte(0xF8 | encode); |
660978a2a31a
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diff
changeset
|
4036 emit_data((int)imm32, rspec, narrow_oop_operand); |
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624
diff
changeset
|
4037 } |
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624
diff
changeset
|
4038 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
4039 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
4040 InstructionMark im(this); |
660978a2a31a
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kvn
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624
diff
changeset
|
4041 prefix(src1); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
4042 emit_byte(0x81); |
660978a2a31a
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|
4043 emit_operand(rax, src1, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4044 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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diff
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|
4045 } |
660978a2a31a
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diff
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|
4046 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4047 void Assembler::lzcntq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4048 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4049 emit_byte(0xF3); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4050 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
93c14e5562c4
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twisti
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diff
changeset
|
4051 emit_byte(0x0F); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4052 emit_byte(0xBD); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4053 emit_byte(0xC0 | encode); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
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|
4054 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4055 |
304 | 4056 void Assembler::movdq(XMMRegister dst, Register src) { |
4057 // table D-1 says MMX/SSE2 | |
4058 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
0 | 4059 emit_byte(0x66); |
304 | 4060 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
0 | 4061 emit_byte(0x0F); |
304 | 4062 emit_byte(0x6E); |
4063 emit_byte(0xC0 | encode); | |
4064 } | |
4065 | |
4066 void Assembler::movdq(Register dst, XMMRegister src) { | |
4067 // table D-1 says MMX/SSE2 | |
4068 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
0 | 4069 emit_byte(0x66); |
304 | 4070 // swap src/dst to get correct prefix |
4071 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
0 | 4072 emit_byte(0x0F); |
4073 emit_byte(0x7E); | |
304 | 4074 emit_byte(0xC0 | encode); |
4075 } | |
4076 | |
4077 void Assembler::movq(Register dst, Register src) { | |
4078 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4079 emit_byte(0x8B); | |
4080 emit_byte(0xC0 | encode); | |
4081 } | |
4082 | |
4083 void Assembler::movq(Register dst, Address src) { | |
4084 InstructionMark im(this); | |
4085 prefixq(src, dst); | |
4086 emit_byte(0x8B); | |
4087 emit_operand(dst, src); | |
4088 } | |
4089 | |
4090 void Assembler::movq(Address dst, Register src) { | |
4091 InstructionMark im(this); | |
4092 prefixq(dst, src); | |
4093 emit_byte(0x89); | |
4094 emit_operand(src, dst); | |
4095 } | |
4096 | |
624 | 4097 void Assembler::movsbq(Register dst, Address src) { |
4098 InstructionMark im(this); | |
4099 prefixq(src, dst); | |
4100 emit_byte(0x0F); | |
4101 emit_byte(0xBE); | |
4102 emit_operand(dst, src); | |
4103 } | |
4104 | |
4105 void Assembler::movsbq(Register dst, Register src) { | |
4106 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4107 emit_byte(0x0F); | |
4108 emit_byte(0xBE); | |
4109 emit_byte(0xC0 | encode); | |
4110 } | |
4111 | |
304 | 4112 void Assembler::movslq(Register dst, int32_t imm32) { |
4113 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
4114 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
4115 // as a result we shouldn't use until tested at runtime... | |
4116 ShouldNotReachHere(); | |
4117 InstructionMark im(this); | |
4118 int encode = prefixq_and_encode(dst->encoding()); | |
4119 emit_byte(0xC7 | encode); | |
4120 emit_long(imm32); | |
4121 } | |
4122 | |
4123 void Assembler::movslq(Address dst, int32_t imm32) { | |
4124 assert(is_simm32(imm32), "lost bits"); | |
4125 InstructionMark im(this); | |
4126 prefixq(dst); | |
4127 emit_byte(0xC7); | |
4128 emit_operand(rax, dst, 4); | |
4129 emit_long(imm32); | |
4130 } | |
4131 | |
4132 void Assembler::movslq(Register dst, Address src) { | |
4133 InstructionMark im(this); | |
4134 prefixq(src, dst); | |
4135 emit_byte(0x63); | |
4136 emit_operand(dst, src); | |
4137 } | |
4138 | |
4139 void Assembler::movslq(Register dst, Register src) { | |
4140 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4141 emit_byte(0x63); | |
4142 emit_byte(0xC0 | encode); | |
4143 } | |
4144 | |
624 | 4145 void Assembler::movswq(Register dst, Address src) { |
4146 InstructionMark im(this); | |
4147 prefixq(src, dst); | |
4148 emit_byte(0x0F); | |
4149 emit_byte(0xBF); | |
4150 emit_operand(dst, src); | |
4151 } | |
4152 | |
4153 void Assembler::movswq(Register dst, Register src) { | |
4154 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4155 emit_byte(0x0F); | |
4156 emit_byte(0xBF); | |
4157 emit_byte(0xC0 | encode); | |
4158 } | |
4159 | |
4160 void Assembler::movzbq(Register dst, Address src) { | |
4161 InstructionMark im(this); | |
4162 prefixq(src, dst); | |
4163 emit_byte(0x0F); | |
4164 emit_byte(0xB6); | |
4165 emit_operand(dst, src); | |
4166 } | |
4167 | |
4168 void Assembler::movzbq(Register dst, Register src) { | |
4169 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4170 emit_byte(0x0F); | |
4171 emit_byte(0xB6); | |
4172 emit_byte(0xC0 | encode); | |
4173 } | |
4174 | |
4175 void Assembler::movzwq(Register dst, Address src) { | |
4176 InstructionMark im(this); | |
4177 prefixq(src, dst); | |
4178 emit_byte(0x0F); | |
4179 emit_byte(0xB7); | |
4180 emit_operand(dst, src); | |
4181 } | |
4182 | |
4183 void Assembler::movzwq(Register dst, Register src) { | |
4184 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4185 emit_byte(0x0F); | |
4186 emit_byte(0xB7); | |
4187 emit_byte(0xC0 | encode); | |
4188 } | |
4189 | |
304 | 4190 void Assembler::negq(Register dst) { |
4191 int encode = prefixq_and_encode(dst->encoding()); | |
4192 emit_byte(0xF7); | |
4193 emit_byte(0xD8 | encode); | |
4194 } | |
4195 | |
4196 void Assembler::notq(Register dst) { | |
4197 int encode = prefixq_and_encode(dst->encoding()); | |
4198 emit_byte(0xF7); | |
4199 emit_byte(0xD0 | encode); | |
4200 } | |
4201 | |
4202 void Assembler::orq(Address dst, int32_t imm32) { | |
4203 InstructionMark im(this); | |
4204 prefixq(dst); | |
4205 emit_byte(0x81); | |
4206 emit_operand(rcx, dst, 4); | |
4207 emit_long(imm32); | |
4208 } | |
4209 | |
4210 void Assembler::orq(Register dst, int32_t imm32) { | |
4211 (void) prefixq_and_encode(dst->encoding()); | |
4212 emit_arith(0x81, 0xC8, dst, imm32); | |
4213 } | |
4214 | |
4215 void Assembler::orq(Register dst, Address src) { | |
4216 InstructionMark im(this); | |
4217 prefixq(src, dst); | |
4218 emit_byte(0x0B); | |
4219 emit_operand(dst, src); | |
4220 } | |
4221 | |
4222 void Assembler::orq(Register dst, Register src) { | |
4223 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4224 emit_arith(0x0B, 0xC0, dst, src); | |
4225 } | |
4226 | |
4227 void Assembler::popa() { // 64bit | |
4228 movq(r15, Address(rsp, 0)); | |
4229 movq(r14, Address(rsp, wordSize)); | |
4230 movq(r13, Address(rsp, 2 * wordSize)); | |
4231 movq(r12, Address(rsp, 3 * wordSize)); | |
4232 movq(r11, Address(rsp, 4 * wordSize)); | |
4233 movq(r10, Address(rsp, 5 * wordSize)); | |
4234 movq(r9, Address(rsp, 6 * wordSize)); | |
4235 movq(r8, Address(rsp, 7 * wordSize)); | |
4236 movq(rdi, Address(rsp, 8 * wordSize)); | |
4237 movq(rsi, Address(rsp, 9 * wordSize)); | |
4238 movq(rbp, Address(rsp, 10 * wordSize)); | |
4239 // skip rsp | |
4240 movq(rbx, Address(rsp, 12 * wordSize)); | |
4241 movq(rdx, Address(rsp, 13 * wordSize)); | |
4242 movq(rcx, Address(rsp, 14 * wordSize)); | |
4243 movq(rax, Address(rsp, 15 * wordSize)); | |
4244 | |
4245 addq(rsp, 16 * wordSize); | |
4246 } | |
4247 | |
643
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4248 void Assembler::popcntq(Register dst, Address src) { |
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4249 assert(VM_Version::supports_popcnt(), "must support"); |
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4250 InstructionMark im(this); |
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4251 emit_byte(0xF3); |
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4252 prefixq(src, dst); |
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4253 emit_byte(0x0F); |
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4254 emit_byte(0xB8); |
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4255 emit_operand(dst, src); |
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4256 } |
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4257 |
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4258 void Assembler::popcntq(Register dst, Register src) { |
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4259 assert(VM_Version::supports_popcnt(), "must support"); |
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4260 emit_byte(0xF3); |
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4261 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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4262 emit_byte(0x0F); |
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4263 emit_byte(0xB8); |
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4264 emit_byte(0xC0 | encode); |
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4265 } |
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4266 |
304 | 4267 void Assembler::popq(Address dst) { |
4268 InstructionMark im(this); | |
4269 prefixq(dst); | |
4270 emit_byte(0x8F); | |
4271 emit_operand(rax, dst); | |
4272 } | |
4273 | |
4274 void Assembler::pusha() { // 64bit | |
4275 // we have to store original rsp. ABI says that 128 bytes | |
4276 // below rsp are local scratch. | |
4277 movq(Address(rsp, -5 * wordSize), rsp); | |
4278 | |
4279 subq(rsp, 16 * wordSize); | |
4280 | |
4281 movq(Address(rsp, 15 * wordSize), rax); | |
4282 movq(Address(rsp, 14 * wordSize), rcx); | |
4283 movq(Address(rsp, 13 * wordSize), rdx); | |
4284 movq(Address(rsp, 12 * wordSize), rbx); | |
4285 // skip rsp | |
4286 movq(Address(rsp, 10 * wordSize), rbp); | |
4287 movq(Address(rsp, 9 * wordSize), rsi); | |
4288 movq(Address(rsp, 8 * wordSize), rdi); | |
4289 movq(Address(rsp, 7 * wordSize), r8); | |
4290 movq(Address(rsp, 6 * wordSize), r9); | |
4291 movq(Address(rsp, 5 * wordSize), r10); | |
4292 movq(Address(rsp, 4 * wordSize), r11); | |
4293 movq(Address(rsp, 3 * wordSize), r12); | |
4294 movq(Address(rsp, 2 * wordSize), r13); | |
4295 movq(Address(rsp, wordSize), r14); | |
4296 movq(Address(rsp, 0), r15); | |
4297 } | |
4298 | |
4299 void Assembler::pushq(Address src) { | |
4300 InstructionMark im(this); | |
4301 prefixq(src); | |
4302 emit_byte(0xFF); | |
4303 emit_operand(rsi, src); | |
4304 } | |
4305 | |
4306 void Assembler::rclq(Register dst, int imm8) { | |
4307 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4308 int encode = prefixq_and_encode(dst->encoding()); | |
4309 if (imm8 == 1) { | |
4310 emit_byte(0xD1); | |
4311 emit_byte(0xD0 | encode); | |
4312 } else { | |
4313 emit_byte(0xC1); | |
4314 emit_byte(0xD0 | encode); | |
4315 emit_byte(imm8); | |
4316 } | |
4317 } | |
4318 void Assembler::sarq(Register dst, int imm8) { | |
4319 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4320 int encode = prefixq_and_encode(dst->encoding()); | |
4321 if (imm8 == 1) { | |
4322 emit_byte(0xD1); | |
4323 emit_byte(0xF8 | encode); | |
4324 } else { | |
4325 emit_byte(0xC1); | |
4326 emit_byte(0xF8 | encode); | |
4327 emit_byte(imm8); | |
4328 } | |
4329 } | |
4330 | |
4331 void Assembler::sarq(Register dst) { | |
4332 int encode = prefixq_and_encode(dst->encoding()); | |
4333 emit_byte(0xD3); | |
4334 emit_byte(0xF8 | encode); | |
4335 } | |
4336 void Assembler::sbbq(Address dst, int32_t imm32) { | |
4337 InstructionMark im(this); | |
4338 prefixq(dst); | |
4339 emit_arith_operand(0x81, rbx, dst, imm32); | |
4340 } | |
4341 | |
4342 void Assembler::sbbq(Register dst, int32_t imm32) { | |
4343 (void) prefixq_and_encode(dst->encoding()); | |
4344 emit_arith(0x81, 0xD8, dst, imm32); | |
4345 } | |
4346 | |
4347 void Assembler::sbbq(Register dst, Address src) { | |
4348 InstructionMark im(this); | |
4349 prefixq(src, dst); | |
4350 emit_byte(0x1B); | |
4351 emit_operand(dst, src); | |
4352 } | |
4353 | |
4354 void Assembler::sbbq(Register dst, Register src) { | |
4355 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4356 emit_arith(0x1B, 0xC0, dst, src); | |
4357 } | |
4358 | |
4359 void Assembler::shlq(Register dst, int imm8) { | |
4360 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4361 int encode = prefixq_and_encode(dst->encoding()); | |
4362 if (imm8 == 1) { | |
4363 emit_byte(0xD1); | |
4364 emit_byte(0xE0 | encode); | |
4365 } else { | |
4366 emit_byte(0xC1); | |
4367 emit_byte(0xE0 | encode); | |
4368 emit_byte(imm8); | |
4369 } | |
4370 } | |
4371 | |
4372 void Assembler::shlq(Register dst) { | |
4373 int encode = prefixq_and_encode(dst->encoding()); | |
4374 emit_byte(0xD3); | |
4375 emit_byte(0xE0 | encode); | |
4376 } | |
4377 | |
4378 void Assembler::shrq(Register dst, int imm8) { | |
4379 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4380 int encode = prefixq_and_encode(dst->encoding()); | |
4381 emit_byte(0xC1); | |
4382 emit_byte(0xE8 | encode); | |
4383 emit_byte(imm8); | |
4384 } | |
4385 | |
4386 void Assembler::shrq(Register dst) { | |
4387 int encode = prefixq_and_encode(dst->encoding()); | |
4388 emit_byte(0xD3); | |
4389 emit_byte(0xE8 | encode); | |
4390 } | |
4391 | |
4392 void Assembler::subq(Address dst, int32_t imm32) { | |
4393 InstructionMark im(this); | |
4394 prefixq(dst); | |
4395 if (is8bit(imm32)) { | |
4396 emit_byte(0x83); | |
4397 emit_operand(rbp, dst, 1); | |
4398 emit_byte(imm32 & 0xFF); | |
4399 } else { | |
4400 emit_byte(0x81); | |
4401 emit_operand(rbp, dst, 4); | |
4402 emit_long(imm32); | |
4403 } | |
4404 } | |
4405 | |
4406 void Assembler::subq(Register dst, int32_t imm32) { | |
4407 (void) prefixq_and_encode(dst->encoding()); | |
4408 emit_arith(0x81, 0xE8, dst, imm32); | |
4409 } | |
4410 | |
4411 void Assembler::subq(Address dst, Register src) { | |
4412 InstructionMark im(this); | |
4413 prefixq(dst, src); | |
4414 emit_byte(0x29); | |
4415 emit_operand(src, dst); | |
4416 } | |
4417 | |
4418 void Assembler::subq(Register dst, Address src) { | |
4419 InstructionMark im(this); | |
4420 prefixq(src, dst); | |
4421 emit_byte(0x2B); | |
4422 emit_operand(dst, src); | |
4423 } | |
4424 | |
4425 void Assembler::subq(Register dst, Register src) { | |
4426 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4427 emit_arith(0x2B, 0xC0, dst, src); | |
4428 } | |
4429 | |
4430 void Assembler::testq(Register dst, int32_t imm32) { | |
4431 // not using emit_arith because test | |
4432 // doesn't support sign-extension of | |
4433 // 8bit operands | |
4434 int encode = dst->encoding(); | |
4435 if (encode == 0) { | |
4436 prefix(REX_W); | |
4437 emit_byte(0xA9); | |
4438 } else { | |
4439 encode = prefixq_and_encode(encode); | |
4440 emit_byte(0xF7); | |
4441 emit_byte(0xC0 | encode); | |
4442 } | |
4443 emit_long(imm32); | |
4444 } | |
4445 | |
4446 void Assembler::testq(Register dst, Register src) { | |
4447 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4448 emit_arith(0x85, 0xC0, dst, src); | |
4449 } | |
4450 | |
4451 void Assembler::xaddq(Address dst, Register src) { | |
4452 InstructionMark im(this); | |
4453 prefixq(dst, src); | |
71 | 4454 emit_byte(0x0F); |
304 | 4455 emit_byte(0xC1); |
4456 emit_operand(src, dst); | |
4457 } | |
4458 | |
4459 void Assembler::xchgq(Register dst, Address src) { | |
4460 InstructionMark im(this); | |
4461 prefixq(src, dst); | |
4462 emit_byte(0x87); | |
4463 emit_operand(dst, src); | |
4464 } | |
4465 | |
4466 void Assembler::xchgq(Register dst, Register src) { | |
4467 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4468 emit_byte(0x87); | |
4469 emit_byte(0xc0 | encode); | |
4470 } | |
4471 | |
4472 void Assembler::xorq(Register dst, Register src) { | |
4473 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4474 emit_arith(0x33, 0xC0, dst, src); | |
4475 } | |
4476 | |
4477 void Assembler::xorq(Register dst, Address src) { | |
4478 InstructionMark im(this); | |
4479 prefixq(src, dst); | |
4480 emit_byte(0x33); | |
4481 emit_operand(dst, src); | |
4482 } | |
4483 | |
4484 #endif // !LP64 | |
4485 | |
4486 static Assembler::Condition reverse[] = { | |
4487 Assembler::noOverflow /* overflow = 0x0 */ , | |
4488 Assembler::overflow /* noOverflow = 0x1 */ , | |
4489 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
4490 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
4491 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
4492 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
4493 Assembler::above /* belowEqual = 0x6 */ , | |
4494 Assembler::belowEqual /* above = 0x7 */ , | |
4495 Assembler::positive /* negative = 0x8 */ , | |
4496 Assembler::negative /* positive = 0x9 */ , | |
4497 Assembler::noParity /* parity = 0xa */ , | |
4498 Assembler::parity /* noParity = 0xb */ , | |
4499 Assembler::greaterEqual /* less = 0xc */ , | |
4500 Assembler::less /* greaterEqual = 0xd */ , | |
4501 Assembler::greater /* lessEqual = 0xe */ , | |
4502 Assembler::lessEqual /* greater = 0xf, */ | |
4503 | |
4504 }; | |
4505 | |
0 | 4506 |
4507 // Implementation of MacroAssembler | |
4508 | |
304 | 4509 // First all the versions that have distinct versions depending on 32/64 bit |
4510 // Unless the difference is trivial (1 line or so). | |
4511 | |
4512 #ifndef _LP64 | |
4513 | |
4514 // 32bit versions | |
4515 | |
0 | 4516 Address MacroAssembler::as_Address(AddressLiteral adr) { |
4517 return Address(adr.target(), adr.rspec()); | |
4518 } | |
4519 | |
4520 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
4521 return Address::make_array(adr); | |
4522 } | |
4523 | |
304 | 4524 int MacroAssembler::biased_locking_enter(Register lock_reg, |
4525 Register obj_reg, | |
4526 Register swap_reg, | |
4527 Register tmp_reg, | |
4528 bool swap_reg_contains_mark, | |
4529 Label& done, | |
4530 Label* slow_case, | |
4531 BiasedLockingCounters* counters) { | |
4532 assert(UseBiasedLocking, "why call this otherwise?"); | |
4533 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
4534 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
4535 | |
4536 if (PrintBiasedLockingStatistics && counters == NULL) | |
4537 counters = BiasedLocking::counters(); | |
4538 | |
4539 bool need_tmp_reg = false; | |
4540 if (tmp_reg == noreg) { | |
4541 need_tmp_reg = true; | |
4542 tmp_reg = lock_reg; | |
4543 } else { | |
4544 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
4545 } | |
4546 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
4547 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
4548 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
4549 Address saved_mark_addr(lock_reg, 0); | |
4550 | |
4551 // Biased locking | |
4552 // See whether the lock is currently biased toward our thread and | |
4553 // whether the epoch is still valid | |
4554 // Note that the runtime guarantees sufficient alignment of JavaThread | |
4555 // pointers to allow age to be placed into low bits | |
4556 // First check to see whether biasing is even enabled for this object | |
4557 Label cas_label; | |
4558 int null_check_offset = -1; | |
4559 if (!swap_reg_contains_mark) { | |
4560 null_check_offset = offset(); | |
4561 movl(swap_reg, mark_addr); | |
4562 } | |
4563 if (need_tmp_reg) { | |
4564 push(tmp_reg); | |
4565 } | |
4566 movl(tmp_reg, swap_reg); | |
4567 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
4568 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
4569 if (need_tmp_reg) { | |
4570 pop(tmp_reg); | |
4571 } | |
4572 jcc(Assembler::notEqual, cas_label); | |
4573 // The bias pattern is present in the object's header. Need to check | |
4574 // whether the bias owner and the epoch are both still current. | |
4575 // Note that because there is no current thread register on x86 we | |
4576 // need to store off the mark word we read out of the object to | |
4577 // avoid reloading it and needing to recheck invariants below. This | |
4578 // store is unfortunate but it makes the overall code shorter and | |
4579 // simpler. | |
4580 movl(saved_mark_addr, swap_reg); | |
4581 if (need_tmp_reg) { | |
4582 push(tmp_reg); | |
4583 } | |
4584 get_thread(tmp_reg); | |
4585 xorl(swap_reg, tmp_reg); | |
4586 if (swap_reg_contains_mark) { | |
4587 null_check_offset = offset(); | |
4588 } | |
4589 movl(tmp_reg, klass_addr); | |
4590 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4591 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
4592 if (need_tmp_reg) { | |
4593 pop(tmp_reg); | |
4594 } | |
4595 if (counters != NULL) { | |
4596 cond_inc32(Assembler::zero, | |
4597 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
4598 } | |
4599 jcc(Assembler::equal, done); | |
4600 | |
4601 Label try_revoke_bias; | |
4602 Label try_rebias; | |
4603 | |
4604 // At this point we know that the header has the bias pattern and | |
4605 // that we are not the bias owner in the current epoch. We need to | |
4606 // figure out more details about the state of the header in order to | |
4607 // know what operations can be legally performed on the object's | |
4608 // header. | |
4609 | |
4610 // If the low three bits in the xor result aren't clear, that means | |
4611 // the prototype header is no longer biased and we have to revoke | |
4612 // the bias on this object. | |
4613 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
4614 jcc(Assembler::notZero, try_revoke_bias); | |
4615 | |
4616 // Biasing is still enabled for this data type. See whether the | |
4617 // epoch of the current bias is still valid, meaning that the epoch | |
4618 // bits of the mark word are equal to the epoch bits of the | |
4619 // prototype header. (Note that the prototype header's epoch bits | |
4620 // only change at a safepoint.) If not, attempt to rebias the object | |
4621 // toward the current thread. Note that we must be absolutely sure | |
4622 // that the current epoch is invalid in order to do this because | |
4623 // otherwise the manipulations it performs on the mark word are | |
4624 // illegal. | |
4625 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
4626 jcc(Assembler::notZero, try_rebias); | |
4627 | |
4628 // The epoch of the current bias is still valid but we know nothing | |
4629 // about the owner; it might be set or it might be clear. Try to | |
4630 // acquire the bias of the object using an atomic operation. If this | |
4631 // fails we will go in to the runtime to revoke the object's bias. | |
4632 // Note that we first construct the presumed unbiased header so we | |
4633 // don't accidentally blow away another thread's valid bias. | |
4634 movl(swap_reg, saved_mark_addr); | |
4635 andl(swap_reg, | |
4636 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
4637 if (need_tmp_reg) { | |
4638 push(tmp_reg); | |
4639 } | |
4640 get_thread(tmp_reg); | |
4641 orl(tmp_reg, swap_reg); | |
4642 if (os::is_MP()) { | |
4643 lock(); | |
4644 } | |
4645 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4646 if (need_tmp_reg) { | |
4647 pop(tmp_reg); | |
4648 } | |
4649 // If the biasing toward our thread failed, this means that | |
4650 // another thread succeeded in biasing it toward itself and we | |
4651 // need to revoke that bias. The revocation will occur in the | |
4652 // interpreter runtime in the slow case. | |
4653 if (counters != NULL) { | |
4654 cond_inc32(Assembler::zero, | |
4655 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
4656 } | |
4657 if (slow_case != NULL) { | |
4658 jcc(Assembler::notZero, *slow_case); | |
4659 } | |
4660 jmp(done); | |
4661 | |
4662 bind(try_rebias); | |
4663 // At this point we know the epoch has expired, meaning that the | |
4664 // current "bias owner", if any, is actually invalid. Under these | |
4665 // circumstances _only_, we are allowed to use the current header's | |
4666 // value as the comparison value when doing the cas to acquire the | |
4667 // bias in the current epoch. In other words, we allow transfer of | |
4668 // the bias from one thread to another directly in this situation. | |
4669 // | |
4670 // FIXME: due to a lack of registers we currently blow away the age | |
4671 // bits in this situation. Should attempt to preserve them. | |
4672 if (need_tmp_reg) { | |
4673 push(tmp_reg); | |
4674 } | |
4675 get_thread(tmp_reg); | |
4676 movl(swap_reg, klass_addr); | |
4677 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4678 movl(swap_reg, saved_mark_addr); | |
4679 if (os::is_MP()) { | |
4680 lock(); | |
4681 } | |
4682 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4683 if (need_tmp_reg) { | |
4684 pop(tmp_reg); | |
4685 } | |
4686 // If the biasing toward our thread failed, then another thread | |
4687 // succeeded in biasing it toward itself and we need to revoke that | |
4688 // bias. The revocation will occur in the runtime in the slow case. | |
4689 if (counters != NULL) { | |
4690 cond_inc32(Assembler::zero, | |
4691 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
4692 } | |
4693 if (slow_case != NULL) { | |
4694 jcc(Assembler::notZero, *slow_case); | |
4695 } | |
4696 jmp(done); | |
4697 | |
4698 bind(try_revoke_bias); | |
4699 // The prototype mark in the klass doesn't have the bias bit set any | |
4700 // more, indicating that objects of this data type are not supposed | |
4701 // to be biased any more. We are going to try to reset the mark of | |
4702 // this object to the prototype value and fall through to the | |
4703 // CAS-based locking scheme. Note that if our CAS fails, it means | |
4704 // that another thread raced us for the privilege of revoking the | |
4705 // bias of this particular object, so it's okay to continue in the | |
4706 // normal locking code. | |
4707 // | |
4708 // FIXME: due to a lack of registers we currently blow away the age | |
4709 // bits in this situation. Should attempt to preserve them. | |
4710 movl(swap_reg, saved_mark_addr); | |
4711 if (need_tmp_reg) { | |
4712 push(tmp_reg); | |
4713 } | |
4714 movl(tmp_reg, klass_addr); | |
4715 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4716 if (os::is_MP()) { | |
4717 lock(); | |
4718 } | |
4719 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4720 if (need_tmp_reg) { | |
4721 pop(tmp_reg); | |
4722 } | |
4723 // Fall through to the normal CAS-based lock, because no matter what | |
4724 // the result of the above CAS, some thread must have succeeded in | |
4725 // removing the bias bit from the object's header. | |
4726 if (counters != NULL) { | |
4727 cond_inc32(Assembler::zero, | |
4728 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
4729 } | |
4730 | |
4731 bind(cas_label); | |
4732 | |
4733 return null_check_offset; | |
4734 } | |
4735 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
4736 int number_of_arguments) { | |
4737 call(RuntimeAddress(entry_point)); | |
4738 increment(rsp, number_of_arguments * wordSize); | |
4739 } | |
4740 | |
4741 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
4742 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4743 } | |
4744 | |
4745 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
4746 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4747 } | |
4748 | |
4749 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
4750 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
4751 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
4752 cdql(); | |
4753 } else { | |
4754 movl(hi, lo); | |
4755 sarl(hi, 31); | |
4756 } | |
4757 } | |
4758 | |
0 | 4759 void MacroAssembler::fat_nop() { |
4760 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
4761 emit_byte(0x26); // es: | |
4762 emit_byte(0x2e); // cs: | |
4763 emit_byte(0x64); // fs: | |
4764 emit_byte(0x65); // gs: | |
4765 emit_byte(0x90); | |
4766 } | |
4767 | |
304 | 4768 void MacroAssembler::jC2(Register tmp, Label& L) { |
4769 // set parity bit if FPU flag C2 is set (via rax) | |
4770 save_rax(tmp); | |
4771 fwait(); fnstsw_ax(); | |
4772 sahf(); | |
4773 restore_rax(tmp); | |
4774 // branch | |
4775 jcc(Assembler::parity, L); | |
4776 } | |
4777 | |
4778 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
4779 // set parity bit if FPU flag C2 is set (via rax) | |
4780 save_rax(tmp); | |
4781 fwait(); fnstsw_ax(); | |
4782 sahf(); | |
4783 restore_rax(tmp); | |
4784 // branch | |
4785 jcc(Assembler::noParity, L); | |
4786 } | |
4787 | |
0 | 4788 // 32bit can do a case table jump in one instruction but we no longer allow the base |
4789 // to be installed in the Address class | |
4790 void MacroAssembler::jump(ArrayAddress entry) { | |
4791 jmp(as_Address(entry)); | |
4792 } | |
4793 | |
304 | 4794 // Note: y_lo will be destroyed |
4795 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
4796 // Long compare for Java (semantics as described in JVM spec.) | |
4797 Label high, low, done; | |
4798 | |
4799 cmpl(x_hi, y_hi); | |
4800 jcc(Assembler::less, low); | |
4801 jcc(Assembler::greater, high); | |
4802 // x_hi is the return register | |
4803 xorl(x_hi, x_hi); | |
4804 cmpl(x_lo, y_lo); | |
4805 jcc(Assembler::below, low); | |
4806 jcc(Assembler::equal, done); | |
4807 | |
4808 bind(high); | |
4809 xorl(x_hi, x_hi); | |
4810 increment(x_hi); | |
4811 jmp(done); | |
4812 | |
4813 bind(low); | |
4814 xorl(x_hi, x_hi); | |
4815 decrementl(x_hi); | |
4816 | |
4817 bind(done); | |
4818 } | |
4819 | |
4820 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
4821 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
0 | 4822 } |
4823 | |
4824 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
4825 // leal(dst, as_Address(adr)); | |
304 | 4826 // see note in movl as to why we must use a move |
0 | 4827 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
4828 } | |
4829 | |
4830 void MacroAssembler::leave() { | |
304 | 4831 mov(rsp, rbp); |
4832 pop(rbp); | |
4833 } | |
0 | 4834 |
4835 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
4836 // Multiplication of two Java long values stored on the stack | |
4837 // as illustrated below. Result is in rdx:rax. | |
4838 // | |
4839 // rsp ---> [ ?? ] \ \ | |
4840 // .... | y_rsp_offset | | |
4841 // [ y_lo ] / (in bytes) | x_rsp_offset | |
4842 // [ y_hi ] | (in bytes) | |
4843 // .... | | |
4844 // [ x_lo ] / | |
4845 // [ x_hi ] | |
4846 // .... | |
4847 // | |
4848 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
4849 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
4850 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
4851 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
4852 Label quick; | |
4853 // load x_hi, y_hi and check if quick | |
4854 // multiplication is possible | |
4855 movl(rbx, x_hi); | |
4856 movl(rcx, y_hi); | |
4857 movl(rax, rbx); | |
4858 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
4859 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
4860 // do full multiplication | |
4861 // 1st step | |
4862 mull(y_lo); // x_hi * y_lo | |
4863 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
4864 // 2nd step | |
4865 movl(rax, x_lo); | |
4866 mull(rcx); // x_lo * y_hi | |
4867 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
4868 // 3rd step | |
4869 bind(quick); // note: rbx, = 0 if quick multiply! | |
4870 movl(rax, x_lo); | |
4871 mull(y_lo); // x_lo * y_lo | |
4872 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
4873 } | |
4874 | |
304 | 4875 void MacroAssembler::lneg(Register hi, Register lo) { |
4876 negl(lo); | |
4877 adcl(hi, 0); | |
4878 negl(hi); | |
4879 } | |
0 | 4880 |
4881 void MacroAssembler::lshl(Register hi, Register lo) { | |
4882 // Java shift left long support (semantics as described in JVM spec., p.305) | |
4883 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
4884 // shift value is in rcx ! | |
4885 assert(hi != rcx, "must not use rcx"); | |
4886 assert(lo != rcx, "must not use rcx"); | |
4887 const Register s = rcx; // shift count | |
4888 const int n = BitsPerWord; | |
4889 Label L; | |
4890 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
4891 cmpl(s, n); // if (s < n) | |
4892 jcc(Assembler::less, L); // else (s >= n) | |
4893 movl(hi, lo); // x := x << n | |
4894 xorl(lo, lo); | |
4895 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
4896 bind(L); // s (mod n) < n | |
4897 shldl(hi, lo); // x := x << s | |
4898 shll(lo); | |
4899 } | |
4900 | |
4901 | |
4902 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
4903 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
4904 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
4905 assert(hi != rcx, "must not use rcx"); | |
4906 assert(lo != rcx, "must not use rcx"); | |
4907 const Register s = rcx; // shift count | |
4908 const int n = BitsPerWord; | |
4909 Label L; | |
4910 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
4911 cmpl(s, n); // if (s < n) | |
4912 jcc(Assembler::less, L); // else (s >= n) | |
4913 movl(lo, hi); // x := x >> n | |
4914 if (sign_extension) sarl(hi, 31); | |
4915 else xorl(hi, hi); | |
4916 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
4917 bind(L); // s (mod n) < n | |
4918 shrdl(lo, hi); // x := x >> s | |
4919 if (sign_extension) sarl(hi); | |
4920 else shrl(hi); | |
4921 } | |
4922 | |
304 | 4923 void MacroAssembler::movoop(Register dst, jobject obj) { |
4924 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4925 } | |
4926 | |
4927 void MacroAssembler::movoop(Address dst, jobject obj) { | |
4928 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4929 } | |
4930 | |
4931 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
4932 if (src.is_lval()) { | |
4933 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
4934 } else { | |
4935 movl(dst, as_Address(src)); | |
4936 } | |
4937 } | |
4938 | |
4939 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
4940 movl(as_Address(dst), src); | |
4941 } | |
4942 | |
4943 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
4944 movl(dst, as_Address(src)); | |
4945 } | |
4946 | |
4947 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
4948 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
4949 movl(dst, src); | |
4950 } | |
4951 | |
4952 | |
4953 void MacroAssembler::pop_callee_saved_registers() { | |
4954 pop(rcx); | |
4955 pop(rdx); | |
4956 pop(rdi); | |
4957 pop(rsi); | |
4958 } | |
4959 | |
4960 void MacroAssembler::pop_fTOS() { | |
4961 fld_d(Address(rsp, 0)); | |
4962 addl(rsp, 2 * wordSize); | |
4963 } | |
4964 | |
4965 void MacroAssembler::push_callee_saved_registers() { | |
4966 push(rsi); | |
4967 push(rdi); | |
4968 push(rdx); | |
4969 push(rcx); | |
4970 } | |
4971 | |
4972 void MacroAssembler::push_fTOS() { | |
4973 subl(rsp, 2 * wordSize); | |
4974 fstp_d(Address(rsp, 0)); | |
4975 } | |
4976 | |
4977 | |
4978 void MacroAssembler::pushoop(jobject obj) { | |
4979 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4980 } | |
4981 | |
4982 | |
4983 void MacroAssembler::pushptr(AddressLiteral src) { | |
4984 if (src.is_lval()) { | |
4985 push_literal32((int32_t)src.target(), src.rspec()); | |
4986 } else { | |
4987 pushl(as_Address(src)); | |
4988 } | |
4989 } | |
4990 | |
4991 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
4992 xorl(dst, dst); | |
4993 set_byte_if_not_zero(dst); | |
4994 } | |
4995 | |
4996 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
4997 masm->push(arg); | |
4998 } | |
4999 | |
5000 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
5001 masm->push(arg); | |
5002 } | |
5003 | |
5004 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
5005 masm->push(arg); | |
5006 } | |
5007 | |
5008 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
5009 masm->push(arg); | |
5010 } | |
5011 | |
5012 #ifndef PRODUCT | |
5013 extern "C" void findpc(intptr_t x); | |
5014 #endif | |
5015 | |
5016 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
5017 // In order to get locks to work, we need to fake a in_VM state | |
5018 JavaThread* thread = JavaThread::current(); | |
5019 JavaThreadState saved_state = thread->thread_state(); | |
5020 thread->set_thread_state(_thread_in_vm); | |
5021 if (ShowMessageBoxOnError) { | |
5022 JavaThread* thread = JavaThread::current(); | |
5023 JavaThreadState saved_state = thread->thread_state(); | |
5024 thread->set_thread_state(_thread_in_vm); | |
5025 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
5026 ttyLocker ttyl; | |
5027 BytecodeCounter::print(); | |
5028 } | |
5029 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
5030 // This is the value of eip which points to where verify_oop will return. | |
5031 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
5032 ttyLocker ttyl; | |
5033 tty->print_cr("eip = 0x%08x", eip); | |
5034 #ifndef PRODUCT | |
1793
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|
5035 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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diff
changeset
|
5036 tty->cr(); |
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jrose
parents:
1763
diff
changeset
|
5037 findpc(eip); |
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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1763
diff
changeset
|
5038 tty->cr(); |
d257356e35f0
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diff
changeset
|
5039 } |
304 | 5040 #endif |
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d257356e35f0
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|
5041 tty->print_cr("rax = 0x%08x", rax); |
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diff
changeset
|
5042 tty->print_cr("rbx = 0x%08x", rbx); |
304 | 5043 tty->print_cr("rcx = 0x%08x", rcx); |
5044 tty->print_cr("rdx = 0x%08x", rdx); | |
5045 tty->print_cr("rdi = 0x%08x", rdi); | |
5046 tty->print_cr("rsi = 0x%08x", rsi); | |
1793
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
5047 tty->print_cr("rbp = 0x%08x", rbp); |
304 | 5048 tty->print_cr("rsp = 0x%08x", rsp); |
5049 BREAKPOINT; | |
1793
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
5050 assert(false, "start up GDB"); |
304 | 5051 } |
5052 } else { | |
5053 ttyLocker ttyl; | |
5054 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
5055 assert(false, "DEBUG MESSAGE"); | |
5056 } | |
5057 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
5058 } | |
5059 | |
5060 void MacroAssembler::stop(const char* msg) { | |
5061 ExternalAddress message((address)msg); | |
5062 // push address of message | |
5063 pushptr(message.addr()); | |
5064 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
5065 pusha(); // push registers | |
5066 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
5067 hlt(); | |
5068 } | |
5069 | |
5070 void MacroAssembler::warn(const char* msg) { | |
5071 push_CPU_state(); | |
5072 | |
5073 ExternalAddress message((address) msg); | |
5074 // push address of message | |
5075 pushptr(message.addr()); | |
5076 | |
5077 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
5078 addl(rsp, wordSize); // discard argument | |
5079 pop_CPU_state(); | |
5080 } | |
5081 | |
5082 #else // _LP64 | |
5083 | |
5084 // 64 bit versions | |
5085 | |
5086 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
5087 // amd64 always does this as a pc-rel | |
5088 // we can be absolute or disp based on the instruction type | |
5089 // jmp/call are displacements others are absolute | |
5090 assert(!adr.is_lval(), "must be rval"); | |
5091 assert(reachable(adr), "must be"); | |
5092 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
5093 | |
5094 } | |
5095 | |
5096 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
5097 AddressLiteral base = adr.base(); | |
5098 lea(rscratch1, base); | |
5099 Address index = adr.index(); | |
5100 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
5101 Address array(rscratch1, index._index, index._scale, index._disp); | |
5102 return array; | |
5103 } | |
5104 | |
5105 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
5106 Register obj_reg, | |
5107 Register swap_reg, | |
5108 Register tmp_reg, | |
5109 bool swap_reg_contains_mark, | |
5110 Label& done, | |
5111 Label* slow_case, | |
5112 BiasedLockingCounters* counters) { | |
5113 assert(UseBiasedLocking, "why call this otherwise?"); | |
5114 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
5115 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
5116 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
5117 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
5118 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
5119 Address saved_mark_addr(lock_reg, 0); | |
5120 | |
5121 if (PrintBiasedLockingStatistics && counters == NULL) | |
5122 counters = BiasedLocking::counters(); | |
5123 | |
5124 // Biased locking | |
5125 // See whether the lock is currently biased toward our thread and | |
5126 // whether the epoch is still valid | |
5127 // Note that the runtime guarantees sufficient alignment of JavaThread | |
5128 // pointers to allow age to be placed into low bits | |
5129 // First check to see whether biasing is even enabled for this object | |
5130 Label cas_label; | |
5131 int null_check_offset = -1; | |
5132 if (!swap_reg_contains_mark) { | |
5133 null_check_offset = offset(); | |
5134 movq(swap_reg, mark_addr); | |
5135 } | |
5136 movq(tmp_reg, swap_reg); | |
5137 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
5138 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
5139 jcc(Assembler::notEqual, cas_label); | |
5140 // The bias pattern is present in the object's header. Need to check | |
5141 // whether the bias owner and the epoch are both still current. | |
5142 load_prototype_header(tmp_reg, obj_reg); | |
5143 orq(tmp_reg, r15_thread); | |
5144 xorq(tmp_reg, swap_reg); | |
5145 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
5146 if (counters != NULL) { | |
5147 cond_inc32(Assembler::zero, | |
5148 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
5149 } | |
0 | 5150 jcc(Assembler::equal, done); |
5151 | |
304 | 5152 Label try_revoke_bias; |
5153 Label try_rebias; | |
5154 | |
5155 // At this point we know that the header has the bias pattern and | |
5156 // that we are not the bias owner in the current epoch. We need to | |
5157 // figure out more details about the state of the header in order to | |
5158 // know what operations can be legally performed on the object's | |
5159 // header. | |
5160 | |
5161 // If the low three bits in the xor result aren't clear, that means | |
5162 // the prototype header is no longer biased and we have to revoke | |
5163 // the bias on this object. | |
5164 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
5165 jcc(Assembler::notZero, try_revoke_bias); | |
5166 | |
5167 // Biasing is still enabled for this data type. See whether the | |
5168 // epoch of the current bias is still valid, meaning that the epoch | |
5169 // bits of the mark word are equal to the epoch bits of the | |
5170 // prototype header. (Note that the prototype header's epoch bits | |
5171 // only change at a safepoint.) If not, attempt to rebias the object | |
5172 // toward the current thread. Note that we must be absolutely sure | |
5173 // that the current epoch is invalid in order to do this because | |
5174 // otherwise the manipulations it performs on the mark word are | |
5175 // illegal. | |
5176 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
5177 jcc(Assembler::notZero, try_rebias); | |
5178 | |
5179 // The epoch of the current bias is still valid but we know nothing | |
5180 // about the owner; it might be set or it might be clear. Try to | |
5181 // acquire the bias of the object using an atomic operation. If this | |
5182 // fails we will go in to the runtime to revoke the object's bias. | |
5183 // Note that we first construct the presumed unbiased header so we | |
5184 // don't accidentally blow away another thread's valid bias. | |
5185 andq(swap_reg, | |
5186 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
5187 movq(tmp_reg, swap_reg); | |
5188 orq(tmp_reg, r15_thread); | |
5189 if (os::is_MP()) { | |
5190 lock(); | |
5191 } | |
5192 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5193 // If the biasing toward our thread failed, this means that | |
5194 // another thread succeeded in biasing it toward itself and we | |
5195 // need to revoke that bias. The revocation will occur in the | |
5196 // interpreter runtime in the slow case. | |
5197 if (counters != NULL) { | |
5198 cond_inc32(Assembler::zero, | |
5199 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
5200 } | |
5201 if (slow_case != NULL) { | |
5202 jcc(Assembler::notZero, *slow_case); | |
5203 } | |
0 | 5204 jmp(done); |
5205 | |
304 | 5206 bind(try_rebias); |
5207 // At this point we know the epoch has expired, meaning that the | |
5208 // current "bias owner", if any, is actually invalid. Under these | |
5209 // circumstances _only_, we are allowed to use the current header's | |
5210 // value as the comparison value when doing the cas to acquire the | |
5211 // bias in the current epoch. In other words, we allow transfer of | |
5212 // the bias from one thread to another directly in this situation. | |
5213 // | |
5214 // FIXME: due to a lack of registers we currently blow away the age | |
5215 // bits in this situation. Should attempt to preserve them. | |
5216 load_prototype_header(tmp_reg, obj_reg); | |
5217 orq(tmp_reg, r15_thread); | |
5218 if (os::is_MP()) { | |
5219 lock(); | |
5220 } | |
5221 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5222 // If the biasing toward our thread failed, then another thread | |
5223 // succeeded in biasing it toward itself and we need to revoke that | |
5224 // bias. The revocation will occur in the runtime in the slow case. | |
5225 if (counters != NULL) { | |
5226 cond_inc32(Assembler::zero, | |
5227 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
5228 } | |
5229 if (slow_case != NULL) { | |
5230 jcc(Assembler::notZero, *slow_case); | |
0 | 5231 } |
5232 jmp(done); | |
5233 | |
304 | 5234 bind(try_revoke_bias); |
5235 // The prototype mark in the klass doesn't have the bias bit set any | |
5236 // more, indicating that objects of this data type are not supposed | |
5237 // to be biased any more. We are going to try to reset the mark of | |
5238 // this object to the prototype value and fall through to the | |
5239 // CAS-based locking scheme. Note that if our CAS fails, it means | |
5240 // that another thread raced us for the privilege of revoking the | |
5241 // bias of this particular object, so it's okay to continue in the | |
5242 // normal locking code. | |
5243 // | |
5244 // FIXME: due to a lack of registers we currently blow away the age | |
5245 // bits in this situation. Should attempt to preserve them. | |
5246 load_prototype_header(tmp_reg, obj_reg); | |
5247 if (os::is_MP()) { | |
5248 lock(); | |
5249 } | |
5250 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5251 // Fall through to the normal CAS-based lock, because no matter what | |
5252 // the result of the above CAS, some thread must have succeeded in | |
5253 // removing the bias bit from the object's header. | |
5254 if (counters != NULL) { | |
5255 cond_inc32(Assembler::zero, | |
5256 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
5257 } | |
5258 | |
5259 bind(cas_label); | |
5260 | |
5261 return null_check_offset; | |
5262 } | |
5263 | |
5264 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
5265 Label L, E; | |
5266 | |
5267 #ifdef _WIN64 | |
5268 // Windows always allocates space for it's register args | |
5269 assert(num_args <= 4, "only register arguments supported"); | |
5270 subq(rsp, frame::arg_reg_save_area_bytes); | |
5271 #endif | |
5272 | |
5273 // Align stack if necessary | |
5274 testl(rsp, 15); | |
5275 jcc(Assembler::zero, L); | |
5276 | |
5277 subq(rsp, 8); | |
5278 { | |
5279 call(RuntimeAddress(entry_point)); | |
5280 } | |
5281 addq(rsp, 8); | |
5282 jmp(E); | |
5283 | |
5284 bind(L); | |
5285 { | |
5286 call(RuntimeAddress(entry_point)); | |
5287 } | |
5288 | |
5289 bind(E); | |
5290 | |
5291 #ifdef _WIN64 | |
5292 // restore stack pointer | |
5293 addq(rsp, frame::arg_reg_save_area_bytes); | |
5294 #endif | |
5295 | |
5296 } | |
5297 | |
5298 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
5299 assert(!src2.is_lval(), "should use cmpptr"); | |
5300 | |
5301 if (reachable(src2)) { | |
5302 cmpq(src1, as_Address(src2)); | |
5303 } else { | |
5304 lea(rscratch1, src2); | |
5305 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
5306 } | |
5307 } | |
5308 | |
5309 int MacroAssembler::corrected_idivq(Register reg) { | |
5310 // Full implementation of Java ldiv and lrem; checks for special | |
5311 // case as described in JVM spec., p.243 & p.271. The function | |
5312 // returns the (pc) offset of the idivl instruction - may be needed | |
5313 // for implicit exceptions. | |
5314 // | |
5315 // normal case special case | |
5316 // | |
5317 // input : rax: dividend min_long | |
5318 // reg: divisor (may not be eax/edx) -1 | |
5319 // | |
5320 // output: rax: quotient (= rax idiv reg) min_long | |
5321 // rdx: remainder (= rax irem reg) 0 | |
5322 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
5323 static const int64_t min_long = 0x8000000000000000; | |
5324 Label normal_case, special_case; | |
5325 | |
5326 // check for special case | |
5327 cmp64(rax, ExternalAddress((address) &min_long)); | |
5328 jcc(Assembler::notEqual, normal_case); | |
5329 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
5330 // remainder = 0) | |
5331 cmpq(reg, -1); | |
5332 jcc(Assembler::equal, special_case); | |
5333 | |
5334 // handle normal case | |
5335 bind(normal_case); | |
5336 cdqq(); | |
5337 int idivq_offset = offset(); | |
5338 idivq(reg); | |
5339 | |
5340 // normal and special case exit | |
5341 bind(special_case); | |
5342 | |
5343 return idivq_offset; | |
5344 } | |
5345 | |
5346 void MacroAssembler::decrementq(Register reg, int value) { | |
5347 if (value == min_jint) { subq(reg, value); return; } | |
5348 if (value < 0) { incrementq(reg, -value); return; } | |
5349 if (value == 0) { ; return; } | |
5350 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
5351 /* else */ { subq(reg, value) ; return; } | |
5352 } | |
5353 | |
5354 void MacroAssembler::decrementq(Address dst, int value) { | |
5355 if (value == min_jint) { subq(dst, value); return; } | |
5356 if (value < 0) { incrementq(dst, -value); return; } | |
5357 if (value == 0) { ; return; } | |
5358 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
5359 /* else */ { subq(dst, value) ; return; } | |
5360 } | |
5361 | |
5362 void MacroAssembler::fat_nop() { | |
5363 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
5364 // Recommened sequence from 'Software Optimization Guide for the AMD | |
5365 // Hammer Processor' | |
5366 emit_byte(0x66); | |
5367 emit_byte(0x66); | |
5368 emit_byte(0x90); | |
5369 emit_byte(0x66); | |
5370 emit_byte(0x90); | |
5371 } | |
5372 | |
5373 void MacroAssembler::incrementq(Register reg, int value) { | |
5374 if (value == min_jint) { addq(reg, value); return; } | |
5375 if (value < 0) { decrementq(reg, -value); return; } | |
5376 if (value == 0) { ; return; } | |
5377 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
5378 /* else */ { addq(reg, value) ; return; } | |
5379 } | |
5380 | |
5381 void MacroAssembler::incrementq(Address dst, int value) { | |
5382 if (value == min_jint) { addq(dst, value); return; } | |
5383 if (value < 0) { decrementq(dst, -value); return; } | |
5384 if (value == 0) { ; return; } | |
5385 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
5386 /* else */ { addq(dst, value) ; return; } | |
5387 } | |
5388 | |
5389 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
5390 // to be installed in the Address class | |
5391 void MacroAssembler::jump(ArrayAddress entry) { | |
5392 lea(rscratch1, entry.base()); | |
5393 Address dispatch = entry.index(); | |
5394 assert(dispatch._base == noreg, "must be"); | |
5395 dispatch._base = rscratch1; | |
5396 jmp(dispatch); | |
5397 } | |
5398 | |
5399 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
5400 ShouldNotReachHere(); // 64bit doesn't use two regs | |
5401 cmpq(x_lo, y_lo); | |
5402 } | |
5403 | |
5404 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
5405 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
5406 } | |
5407 | |
5408 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
5409 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
5410 movptr(dst, rscratch1); | |
5411 } | |
5412 | |
5413 void MacroAssembler::leave() { | |
5414 // %%% is this really better? Why not on 32bit too? | |
5415 emit_byte(0xC9); // LEAVE | |
5416 } | |
5417 | |
5418 void MacroAssembler::lneg(Register hi, Register lo) { | |
5419 ShouldNotReachHere(); // 64bit doesn't use two regs | |
5420 negq(lo); | |
5421 } | |
5422 | |
5423 void MacroAssembler::movoop(Register dst, jobject obj) { | |
5424 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
5425 } | |
5426 | |
5427 void MacroAssembler::movoop(Address dst, jobject obj) { | |
5428 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
5429 movq(dst, rscratch1); | |
5430 } | |
5431 | |
5432 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
5433 if (src.is_lval()) { | |
5434 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
5435 } else { | |
5436 if (reachable(src)) { | |
5437 movq(dst, as_Address(src)); | |
5438 } else { | |
5439 lea(rscratch1, src); | |
5440 movq(dst, Address(rscratch1,0)); | |
0 | 5441 } |
304 | 5442 } |
5443 } | |
5444 | |
5445 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
5446 movq(as_Address(dst), src); | |
5447 } | |
5448 | |
5449 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
5450 movq(dst, as_Address(src)); | |
5451 } | |
5452 | |
5453 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
5454 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
5455 mov64(rscratch1, src); | |
5456 movq(dst, rscratch1); | |
5457 } | |
5458 | |
5459 // These are mostly for initializing NULL | |
5460 void MacroAssembler::movptr(Address dst, int32_t src) { | |
5461 movslq(dst, src); | |
5462 } | |
5463 | |
5464 void MacroAssembler::movptr(Register dst, int32_t src) { | |
5465 mov64(dst, (intptr_t)src); | |
5466 } | |
5467 | |
5468 void MacroAssembler::pushoop(jobject obj) { | |
5469 movoop(rscratch1, obj); | |
5470 push(rscratch1); | |
5471 } | |
5472 | |
5473 void MacroAssembler::pushptr(AddressLiteral src) { | |
5474 lea(rscratch1, src); | |
5475 if (src.is_lval()) { | |
5476 push(rscratch1); | |
5477 } else { | |
5478 pushq(Address(rscratch1, 0)); | |
5479 } | |
5480 } | |
5481 | |
5482 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
5483 bool clear_pc) { | |
5484 // we must set sp to zero to clear frame | |
512
db4caa99ef11
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420
diff
changeset
|
5485 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
304 | 5486 // must clear fp, so that compiled frames are not confused; it is |
5487 // possible that we need it only for debugging | |
5488 if (clear_fp) { | |
512
db4caa99ef11
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xlu
parents:
420
diff
changeset
|
5489 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
304 | 5490 } |
5491 | |
5492 if (clear_pc) { | |
512
db4caa99ef11
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parents:
420
diff
changeset
|
5493 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
304 | 5494 } |
5495 } | |
5496 | |
5497 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
5498 Register last_java_fp, | |
5499 address last_java_pc) { | |
5500 // determine last_java_sp register | |
5501 if (!last_java_sp->is_valid()) { | |
5502 last_java_sp = rsp; | |
5503 } | |
5504 | |
5505 // last_java_fp is optional | |
5506 if (last_java_fp->is_valid()) { | |
5507 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
5508 last_java_fp); | |
5509 } | |
5510 | |
5511 // last_java_pc is optional | |
5512 if (last_java_pc != NULL) { | |
5513 Address java_pc(r15_thread, | |
5514 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
5515 lea(rscratch1, InternalAddress(last_java_pc)); | |
5516 movptr(java_pc, rscratch1); | |
5517 } | |
5518 | |
5519 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
5520 } | |
5521 | |
5522 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
5523 if (c_rarg0 != arg ) { | |
5524 masm->mov(c_rarg0, arg); | |
5525 } | |
5526 } | |
5527 | |
5528 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
5529 if (c_rarg1 != arg ) { | |
5530 masm->mov(c_rarg1, arg); | |
5531 } | |
5532 } | |
5533 | |
5534 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
5535 if (c_rarg2 != arg ) { | |
5536 masm->mov(c_rarg2, arg); | |
5537 } | |
5538 } | |
5539 | |
5540 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
5541 if (c_rarg3 != arg ) { | |
5542 masm->mov(c_rarg3, arg); | |
5543 } | |
5544 } | |
5545 | |
5546 void MacroAssembler::stop(const char* msg) { | |
5547 address rip = pc(); | |
5548 pusha(); // get regs on stack | |
5549 lea(c_rarg0, ExternalAddress((address) msg)); | |
5550 lea(c_rarg1, InternalAddress(rip)); | |
5551 movq(c_rarg2, rsp); // pass pointer to regs array | |
5552 andq(rsp, -16); // align stack as required by ABI | |
5553 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
5554 hlt(); | |
5555 } | |
5556 | |
5557 void MacroAssembler::warn(const char* msg) { | |
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5558 push(rsp); |
304 | 5559 andq(rsp, -16); // align stack as required by push_CPU_state and call |
5560 | |
5561 push_CPU_state(); // keeps alignment at 16 bytes | |
5562 lea(c_rarg0, ExternalAddress((address) msg)); | |
5563 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
5564 pop_CPU_state(); | |
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5565 pop(rsp); |
304 | 5566 } |
5567 | |
5568 #ifndef PRODUCT | |
5569 extern "C" void findpc(intptr_t x); | |
5570 #endif | |
5571 | |
5572 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
5573 // In order to get locks to work, we need to fake a in_VM state | |
5574 if (ShowMessageBoxOnError ) { | |
5575 JavaThread* thread = JavaThread::current(); | |
5576 JavaThreadState saved_state = thread->thread_state(); | |
5577 thread->set_thread_state(_thread_in_vm); | |
5578 #ifndef PRODUCT | |
5579 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
5580 ttyLocker ttyl; | |
5581 BytecodeCounter::print(); | |
0 | 5582 } |
304 | 5583 #endif |
5584 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
5585 // XXX correct this offset for amd64 | |
5586 // This is the value of eip which points to where verify_oop will return. | |
5587 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
5588 ttyLocker ttyl; | |
5589 tty->print_cr("rip = 0x%016lx", pc); | |
5590 #ifndef PRODUCT | |
5591 tty->cr(); | |
5592 findpc(pc); | |
5593 tty->cr(); | |
5594 #endif | |
5595 tty->print_cr("rax = 0x%016lx", regs[15]); | |
5596 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
5597 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
5598 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
5599 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
5600 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
5601 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
5602 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
5603 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
5604 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
5605 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
5606 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
5607 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
5608 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
5609 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
5610 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
5611 BREAKPOINT; | |
0 | 5612 } |
304 | 5613 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
5614 } else { | |
5615 ttyLocker ttyl; | |
5616 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
5617 msg); | |
5618 } | |
5619 } | |
5620 | |
5621 #endif // _LP64 | |
5622 | |
5623 // Now versions that are common to 32/64 bit | |
5624 | |
5625 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
5626 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
5627 } | |
5628 | |
5629 void MacroAssembler::addptr(Register dst, Register src) { | |
5630 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
5631 } | |
5632 | |
5633 void MacroAssembler::addptr(Address dst, Register src) { | |
5634 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
5635 } | |
5636 | |
5637 void MacroAssembler::align(int modulus) { | |
5638 if (offset() % modulus != 0) { | |
5639 nop(modulus - (offset() % modulus)); | |
5640 } | |
5641 } | |
5642 | |
5643 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
1060 | 5644 if (reachable(src)) { |
5645 andpd(dst, as_Address(src)); | |
5646 } else { | |
5647 lea(rscratch1, src); | |
5648 andpd(dst, Address(rscratch1, 0)); | |
5649 } | |
304 | 5650 } |
5651 | |
5652 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
5653 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
5654 } | |
5655 | |
5656 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
5657 pushf(); | |
5658 if (os::is_MP()) | |
5659 lock(); | |
5660 incrementl(counter_addr); | |
5661 popf(); | |
5662 } | |
5663 | |
5664 // Writes to stack successive pages until offset reached to check for | |
5665 // stack overflow + shadow pages. This clobbers tmp. | |
5666 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
5667 movptr(tmp, rsp); | |
5668 // Bang stack for total size given plus shadow page size. | |
5669 // Bang one page at a time because large size can bang beyond yellow and | |
5670 // red zones. | |
5671 Label loop; | |
5672 bind(loop); | |
5673 movl(Address(tmp, (-os::vm_page_size())), size ); | |
5674 subptr(tmp, os::vm_page_size()); | |
5675 subl(size, os::vm_page_size()); | |
5676 jcc(Assembler::greater, loop); | |
5677 | |
5678 // Bang down shadow pages too. | |
5679 // The -1 because we already subtracted 1 page. | |
5680 for (int i = 0; i< StackShadowPages-1; i++) { | |
5681 // this could be any sized move but this is can be a debugging crumb | |
5682 // so the bigger the better. | |
5683 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
5684 } | |
5685 } | |
5686 | |
5687 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
5688 assert(UseBiasedLocking, "why call this otherwise?"); | |
5689 | |
5690 // Check for biased locking unlock case, which is a no-op | |
5691 // Note: we do not have to check the thread ID for two reasons. | |
5692 // First, the interpreter checks for IllegalMonitorStateException at | |
5693 // a higher level. Second, if the bias was revoked while we held the | |
5694 // lock, the object could not be rebiased toward another thread, so | |
5695 // the bias bit would be clear. | |
5696 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
5697 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
5698 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
5699 jcc(Assembler::equal, done); | |
5700 } | |
5701 | |
5702 void MacroAssembler::c2bool(Register x) { | |
5703 // implements x == 0 ? 0 : 1 | |
5704 // note: must only look at least-significant byte of x | |
5705 // since C-style booleans are stored in one byte | |
5706 // only! (was bug) | |
5707 andl(x, 0xFF); | |
5708 setb(Assembler::notZero, x); | |
5709 } | |
5710 | |
5711 // Wouldn't need if AddressLiteral version had new name | |
5712 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
5713 Assembler::call(L, rtype); | |
5714 } | |
5715 | |
5716 void MacroAssembler::call(Register entry) { | |
5717 Assembler::call(entry); | |
5718 } | |
5719 | |
5720 void MacroAssembler::call(AddressLiteral entry) { | |
5721 if (reachable(entry)) { | |
5722 Assembler::call_literal(entry.target(), entry.rspec()); | |
5723 } else { | |
5724 lea(rscratch1, entry); | |
5725 Assembler::call(rscratch1); | |
5726 } | |
5727 } | |
5728 | |
5729 // Implementation of call_VM versions | |
5730 | |
5731 void MacroAssembler::call_VM(Register oop_result, | |
5732 address entry_point, | |
5733 bool check_exceptions) { | |
5734 Label C, E; | |
5735 call(C, relocInfo::none); | |
5736 jmp(E); | |
5737 | |
5738 bind(C); | |
5739 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
5740 ret(0); | |
5741 | |
5742 bind(E); | |
5743 } | |
5744 | |
5745 void MacroAssembler::call_VM(Register oop_result, | |
5746 address entry_point, | |
5747 Register arg_1, | |
5748 bool check_exceptions) { | |
5749 Label C, E; | |
5750 call(C, relocInfo::none); | |
5751 jmp(E); | |
5752 | |
5753 bind(C); | |
5754 pass_arg1(this, arg_1); | |
5755 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
5756 ret(0); | |
5757 | |
5758 bind(E); | |
5759 } | |
5760 | |
5761 void MacroAssembler::call_VM(Register oop_result, | |
5762 address entry_point, | |
5763 Register arg_1, | |
5764 Register arg_2, | |
5765 bool check_exceptions) { | |
5766 Label C, E; | |
5767 call(C, relocInfo::none); | |
5768 jmp(E); | |
5769 | |
5770 bind(C); | |
5771 | |
5772 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5773 | |
5774 pass_arg2(this, arg_2); | |
5775 pass_arg1(this, arg_1); | |
5776 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
5777 ret(0); | |
5778 | |
5779 bind(E); | |
5780 } | |
5781 | |
5782 void MacroAssembler::call_VM(Register oop_result, | |
5783 address entry_point, | |
5784 Register arg_1, | |
5785 Register arg_2, | |
5786 Register arg_3, | |
5787 bool check_exceptions) { | |
5788 Label C, E; | |
5789 call(C, relocInfo::none); | |
5790 jmp(E); | |
5791 | |
5792 bind(C); | |
5793 | |
5794 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
5795 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
5796 pass_arg3(this, arg_3); | |
5797 | |
5798 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5799 pass_arg2(this, arg_2); | |
5800 | |
5801 pass_arg1(this, arg_1); | |
5802 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
5803 ret(0); | |
5804 | |
5805 bind(E); | |
5806 } | |
5807 | |
5808 void MacroAssembler::call_VM(Register oop_result, | |
5809 Register last_java_sp, | |
5810 address entry_point, | |
5811 int number_of_arguments, | |
5812 bool check_exceptions) { | |
5813 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
5814 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
5815 } | |
5816 | |
5817 void MacroAssembler::call_VM(Register oop_result, | |
5818 Register last_java_sp, | |
5819 address entry_point, | |
5820 Register arg_1, | |
5821 bool check_exceptions) { | |
5822 pass_arg1(this, arg_1); | |
5823 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
5824 } | |
5825 | |
5826 void MacroAssembler::call_VM(Register oop_result, | |
5827 Register last_java_sp, | |
5828 address entry_point, | |
5829 Register arg_1, | |
5830 Register arg_2, | |
5831 bool check_exceptions) { | |
5832 | |
5833 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5834 pass_arg2(this, arg_2); | |
5835 pass_arg1(this, arg_1); | |
5836 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
5837 } | |
5838 | |
5839 void MacroAssembler::call_VM(Register oop_result, | |
5840 Register last_java_sp, | |
5841 address entry_point, | |
5842 Register arg_1, | |
5843 Register arg_2, | |
5844 Register arg_3, | |
5845 bool check_exceptions) { | |
5846 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
5847 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
5848 pass_arg3(this, arg_3); | |
5849 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5850 pass_arg2(this, arg_2); | |
5851 pass_arg1(this, arg_1); | |
5852 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
5853 } | |
5854 | |
5855 void MacroAssembler::call_VM_base(Register oop_result, | |
5856 Register java_thread, | |
5857 Register last_java_sp, | |
5858 address entry_point, | |
5859 int number_of_arguments, | |
5860 bool check_exceptions) { | |
5861 // determine java_thread register | |
5862 if (!java_thread->is_valid()) { | |
5863 #ifdef _LP64 | |
5864 java_thread = r15_thread; | |
5865 #else | |
5866 java_thread = rdi; | |
5867 get_thread(java_thread); | |
5868 #endif // LP64 | |
5869 } | |
5870 // determine last_java_sp register | |
5871 if (!last_java_sp->is_valid()) { | |
5872 last_java_sp = rsp; | |
5873 } | |
5874 // debugging support | |
5875 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
5876 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5877 #ifdef ASSERT |
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5878 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");) |
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5879 #endif // ASSERT |
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5880 |
304 | 5881 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
5882 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
5883 | |
5884 // push java thread (becomes first argument of C function) | |
5885 | |
5886 NOT_LP64(push(java_thread); number_of_arguments++); | |
5887 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
5888 | |
5889 // set last Java frame before call | |
5890 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
5891 | |
5892 // Only interpreter should have to set fp | |
5893 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
5894 | |
5895 // do the call, remove parameters | |
5896 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
5897 | |
5898 // restore the thread (cannot use the pushed argument since arguments | |
5899 // may be overwritten by C code generated by an optimizing compiler); | |
5900 // however can use the register value directly if it is callee saved. | |
5901 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
5902 // rdi & rsi (also r15) are callee saved -> nothing to do | |
5903 #ifdef ASSERT | |
5904 guarantee(java_thread != rax, "change this code"); | |
5905 push(rax); | |
5906 { Label L; | |
5907 get_thread(rax); | |
5908 cmpptr(java_thread, rax); | |
5909 jcc(Assembler::equal, L); | |
5910 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
5911 bind(L); | |
0 | 5912 } |
304 | 5913 pop(rax); |
5914 #endif | |
5915 } else { | |
5916 get_thread(java_thread); | |
5917 } | |
5918 // reset last Java frame | |
5919 // Only interpreter should have to clear fp | |
5920 reset_last_Java_frame(java_thread, true, false); | |
5921 | |
5922 #ifndef CC_INTERP | |
5923 // C++ interp handles this in the interpreter | |
5924 check_and_handle_popframe(java_thread); | |
5925 check_and_handle_earlyret(java_thread); | |
5926 #endif /* CC_INTERP */ | |
5927 | |
5928 if (check_exceptions) { | |
5929 // check for pending exceptions (java_thread is set upon return) | |
5930 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
5931 #ifndef _LP64 | |
5932 jump_cc(Assembler::notEqual, | |
5933 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
5934 #else | |
5935 // This used to conditionally jump to forward_exception however it is | |
5936 // possible if we relocate that the branch will not reach. So we must jump | |
5937 // around so we can always reach | |
5938 | |
5939 Label ok; | |
5940 jcc(Assembler::equal, ok); | |
5941 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
5942 bind(ok); | |
5943 #endif // LP64 | |
5944 } | |
5945 | |
5946 // get oop result if there is one and reset the value in the thread | |
5947 if (oop_result->is_valid()) { | |
5948 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5949 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
304 | 5950 verify_oop(oop_result, "broken oop in call_VM_base"); |
5951 } | |
5952 } | |
5953 | |
5954 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
5955 | |
5956 // Calculate the value for last_Java_sp | |
5957 // somewhat subtle. call_VM does an intermediate call | |
5958 // which places a return address on the stack just under the | |
5959 // stack pointer as the user finsihed with it. This allows | |
5960 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
5961 // On 32bit we then have to push additional args on the stack to accomplish | |
5962 // the actual requested call. On 64bit call_VM only can use register args | |
5963 // so the only extra space is the return address that call_VM created. | |
5964 // This hopefully explains the calculations here. | |
5965 | |
5966 #ifdef _LP64 | |
5967 // We've pushed one address, correct last_Java_sp | |
5968 lea(rax, Address(rsp, wordSize)); | |
5969 #else | |
5970 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
5971 #endif // LP64 | |
5972 | |
5973 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
5974 | |
5975 } | |
5976 | |
5977 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
5978 call_VM_leaf_base(entry_point, number_of_arguments); | |
5979 } | |
5980 | |
5981 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
5982 pass_arg0(this, arg_0); | |
5983 call_VM_leaf(entry_point, 1); | |
5984 } | |
5985 | |
5986 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
5987 | |
5988 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
5989 pass_arg1(this, arg_1); | |
5990 pass_arg0(this, arg_0); | |
5991 call_VM_leaf(entry_point, 2); | |
5992 } | |
5993 | |
5994 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
5995 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
5996 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5997 pass_arg2(this, arg_2); | |
5998 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
5999 pass_arg1(this, arg_1); | |
6000 pass_arg0(this, arg_0); | |
6001 call_VM_leaf(entry_point, 3); | |
6002 } | |
6003 | |
6004 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
6005 } | |
6006 | |
6007 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
6008 } | |
6009 | |
6010 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
6011 if (reachable(src1)) { | |
6012 cmpl(as_Address(src1), imm); | |
6013 } else { | |
6014 lea(rscratch1, src1); | |
6015 cmpl(Address(rscratch1, 0), imm); | |
6016 } | |
6017 } | |
6018 | |
6019 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
6020 assert(!src2.is_lval(), "use cmpptr"); | |
6021 if (reachable(src2)) { | |
6022 cmpl(src1, as_Address(src2)); | |
6023 } else { | |
6024 lea(rscratch1, src2); | |
6025 cmpl(src1, Address(rscratch1, 0)); | |
6026 } | |
6027 } | |
6028 | |
6029 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
6030 Assembler::cmpl(src1, imm); | |
6031 } | |
6032 | |
6033 void MacroAssembler::cmp32(Register src1, Address src2) { | |
6034 Assembler::cmpl(src1, src2); | |
6035 } | |
6036 | |
6037 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
6038 ucomisd(opr1, opr2); | |
6039 | |
6040 Label L; | |
6041 if (unordered_is_less) { | |
6042 movl(dst, -1); | |
6043 jcc(Assembler::parity, L); | |
6044 jcc(Assembler::below , L); | |
6045 movl(dst, 0); | |
6046 jcc(Assembler::equal , L); | |
6047 increment(dst); | |
6048 } else { // unordered is greater | |
6049 movl(dst, 1); | |
6050 jcc(Assembler::parity, L); | |
6051 jcc(Assembler::above , L); | |
6052 movl(dst, 0); | |
6053 jcc(Assembler::equal , L); | |
6054 decrementl(dst); | |
6055 } | |
6056 bind(L); | |
6057 } | |
6058 | |
6059 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
6060 ucomiss(opr1, opr2); | |
6061 | |
6062 Label L; | |
6063 if (unordered_is_less) { | |
6064 movl(dst, -1); | |
6065 jcc(Assembler::parity, L); | |
6066 jcc(Assembler::below , L); | |
6067 movl(dst, 0); | |
6068 jcc(Assembler::equal , L); | |
6069 increment(dst); | |
6070 } else { // unordered is greater | |
6071 movl(dst, 1); | |
6072 jcc(Assembler::parity, L); | |
6073 jcc(Assembler::above , L); | |
6074 movl(dst, 0); | |
6075 jcc(Assembler::equal , L); | |
6076 decrementl(dst); | |
6077 } | |
6078 bind(L); | |
6079 } | |
6080 | |
6081 | |
6082 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
6083 if (reachable(src1)) { | |
6084 cmpb(as_Address(src1), imm); | |
6085 } else { | |
6086 lea(rscratch1, src1); | |
6087 cmpb(Address(rscratch1, 0), imm); | |
6088 } | |
6089 } | |
6090 | |
6091 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
6092 #ifdef _LP64 | |
6093 if (src2.is_lval()) { | |
6094 movptr(rscratch1, src2); | |
6095 Assembler::cmpq(src1, rscratch1); | |
6096 } else if (reachable(src2)) { | |
6097 cmpq(src1, as_Address(src2)); | |
6098 } else { | |
6099 lea(rscratch1, src2); | |
6100 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
6101 } | |
6102 #else | |
6103 if (src2.is_lval()) { | |
6104 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
6105 } else { | |
6106 cmpl(src1, as_Address(src2)); | |
6107 } | |
6108 #endif // _LP64 | |
6109 } | |
6110 | |
6111 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
6112 assert(src2.is_lval(), "not a mem-mem compare"); | |
6113 #ifdef _LP64 | |
6114 // moves src2's literal address | |
6115 movptr(rscratch1, src2); | |
6116 Assembler::cmpq(src1, rscratch1); | |
6117 #else | |
6118 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
6119 #endif // _LP64 | |
6120 } | |
6121 | |
6122 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
6123 if (reachable(adr)) { | |
6124 if (os::is_MP()) | |
6125 lock(); | |
6126 cmpxchgptr(reg, as_Address(adr)); | |
6127 } else { | |
6128 lea(rscratch1, adr); | |
6129 if (os::is_MP()) | |
6130 lock(); | |
6131 cmpxchgptr(reg, Address(rscratch1, 0)); | |
6132 } | |
6133 } | |
6134 | |
6135 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
6136 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
6137 } | |
6138 | |
6139 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
1060 | 6140 if (reachable(src)) { |
6141 comisd(dst, as_Address(src)); | |
6142 } else { | |
6143 lea(rscratch1, src); | |
6144 comisd(dst, Address(rscratch1, 0)); | |
6145 } | |
304 | 6146 } |
6147 | |
6148 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
1060 | 6149 if (reachable(src)) { |
6150 comiss(dst, as_Address(src)); | |
6151 } else { | |
6152 lea(rscratch1, src); | |
6153 comiss(dst, Address(rscratch1, 0)); | |
6154 } | |
304 | 6155 } |
6156 | |
6157 | |
6158 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
6159 Condition negated_cond = negate_condition(cond); | |
6160 Label L; | |
6161 jcc(negated_cond, L); | |
6162 atomic_incl(counter_addr); | |
6163 bind(L); | |
6164 } | |
6165 | |
6166 int MacroAssembler::corrected_idivl(Register reg) { | |
6167 // Full implementation of Java idiv and irem; checks for | |
6168 // special case as described in JVM spec., p.243 & p.271. | |
6169 // The function returns the (pc) offset of the idivl | |
6170 // instruction - may be needed for implicit exceptions. | |
6171 // | |
6172 // normal case special case | |
6173 // | |
6174 // input : rax,: dividend min_int | |
6175 // reg: divisor (may not be rax,/rdx) -1 | |
6176 // | |
6177 // output: rax,: quotient (= rax, idiv reg) min_int | |
6178 // rdx: remainder (= rax, irem reg) 0 | |
6179 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
6180 const int min_int = 0x80000000; | |
6181 Label normal_case, special_case; | |
6182 | |
6183 // check for special case | |
6184 cmpl(rax, min_int); | |
6185 jcc(Assembler::notEqual, normal_case); | |
6186 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
6187 cmpl(reg, -1); | |
6188 jcc(Assembler::equal, special_case); | |
6189 | |
6190 // handle normal case | |
6191 bind(normal_case); | |
6192 cdql(); | |
6193 int idivl_offset = offset(); | |
6194 idivl(reg); | |
6195 | |
6196 // normal and special case exit | |
6197 bind(special_case); | |
6198 | |
6199 return idivl_offset; | |
6200 } | |
6201 | |
6202 | |
6203 | |
6204 void MacroAssembler::decrementl(Register reg, int value) { | |
6205 if (value == min_jint) {subl(reg, value) ; return; } | |
6206 if (value < 0) { incrementl(reg, -value); return; } | |
6207 if (value == 0) { ; return; } | |
6208 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
6209 /* else */ { subl(reg, value) ; return; } | |
6210 } | |
6211 | |
6212 void MacroAssembler::decrementl(Address dst, int value) { | |
6213 if (value == min_jint) {subl(dst, value) ; return; } | |
6214 if (value < 0) { incrementl(dst, -value); return; } | |
6215 if (value == 0) { ; return; } | |
6216 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
6217 /* else */ { subl(dst, value) ; return; } | |
6218 } | |
6219 | |
6220 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
6221 assert (shift_value > 0, "illegal shift value"); | |
6222 Label _is_positive; | |
6223 testl (reg, reg); | |
6224 jcc (Assembler::positive, _is_positive); | |
6225 int offset = (1 << shift_value) - 1 ; | |
6226 | |
6227 if (offset == 1) { | |
6228 incrementl(reg); | |
6229 } else { | |
6230 addl(reg, offset); | |
6231 } | |
6232 | |
6233 bind (_is_positive); | |
6234 sarl(reg, shift_value); | |
6235 } | |
6236 | |
6237 // !defined(COMPILER2) is because of stupid core builds | |
6238 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
6239 void MacroAssembler::empty_FPU_stack() { | |
6240 if (VM_Version::supports_mmx()) { | |
6241 emms(); | |
6242 } else { | |
6243 for (int i = 8; i-- > 0; ) ffree(i); | |
6244 } | |
6245 } | |
6246 #endif // !LP64 || C1 || !C2 | |
6247 | |
6248 | |
6249 // Defines obj, preserves var_size_in_bytes | |
6250 void MacroAssembler::eden_allocate(Register obj, | |
6251 Register var_size_in_bytes, | |
6252 int con_size_in_bytes, | |
6253 Register t1, | |
6254 Label& slow_case) { | |
6255 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
6256 assert_different_registers(obj, var_size_in_bytes, t1); | |
362 | 6257 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
6258 jmp(slow_case); | |
304 | 6259 } else { |
362 | 6260 Register end = t1; |
6261 Label retry; | |
6262 bind(retry); | |
6263 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
6264 movptr(obj, heap_top); | |
6265 if (var_size_in_bytes == noreg) { | |
6266 lea(end, Address(obj, con_size_in_bytes)); | |
6267 } else { | |
6268 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
6269 } | |
6270 // if end < obj then we wrapped around => object too long => slow case | |
6271 cmpptr(end, obj); | |
6272 jcc(Assembler::below, slow_case); | |
6273 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
6274 jcc(Assembler::above, slow_case); | |
6275 // Compare obj with the top addr, and if still equal, store the new top addr in | |
6276 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
6277 // it otherwise. Use lock prefix for atomicity on MPs. | |
6278 locked_cmpxchgptr(end, heap_top); | |
6279 jcc(Assembler::notEqual, retry); | |
6280 } | |
304 | 6281 } |
6282 | |
6283 void MacroAssembler::enter() { | |
6284 push(rbp); | |
6285 mov(rbp, rsp); | |
6286 } | |
0 | 6287 |
6288 void MacroAssembler::fcmp(Register tmp) { | |
6289 fcmp(tmp, 1, true, true); | |
6290 } | |
6291 | |
6292 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
6293 assert(!pop_right || pop_left, "usage error"); | |
6294 if (VM_Version::supports_cmov()) { | |
6295 assert(tmp == noreg, "unneeded temp"); | |
6296 if (pop_left) { | |
6297 fucomip(index); | |
6298 } else { | |
6299 fucomi(index); | |
6300 } | |
6301 if (pop_right) { | |
6302 fpop(); | |
6303 } | |
6304 } else { | |
6305 assert(tmp != noreg, "need temp"); | |
6306 if (pop_left) { | |
6307 if (pop_right) { | |
6308 fcompp(); | |
6309 } else { | |
6310 fcomp(index); | |
6311 } | |
6312 } else { | |
6313 fcom(index); | |
6314 } | |
6315 // convert FPU condition into eflags condition via rax, | |
6316 save_rax(tmp); | |
6317 fwait(); fnstsw_ax(); | |
6318 sahf(); | |
6319 restore_rax(tmp); | |
6320 } | |
6321 // condition codes set as follows: | |
6322 // | |
6323 // CF (corresponds to C0) if x < y | |
6324 // PF (corresponds to C2) if unordered | |
6325 // ZF (corresponds to C3) if x = y | |
6326 } | |
6327 | |
6328 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
6329 fcmp2int(dst, unordered_is_less, 1, true, true); | |
6330 } | |
6331 | |
6332 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
6333 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
6334 Label L; | |
6335 if (unordered_is_less) { | |
6336 movl(dst, -1); | |
6337 jcc(Assembler::parity, L); | |
6338 jcc(Assembler::below , L); | |
6339 movl(dst, 0); | |
6340 jcc(Assembler::equal , L); | |
6341 increment(dst); | |
6342 } else { // unordered is greater | |
6343 movl(dst, 1); | |
6344 jcc(Assembler::parity, L); | |
6345 jcc(Assembler::above , L); | |
6346 movl(dst, 0); | |
6347 jcc(Assembler::equal , L); | |
304 | 6348 decrementl(dst); |
0 | 6349 } |
6350 bind(L); | |
6351 } | |
6352 | |
304 | 6353 void MacroAssembler::fld_d(AddressLiteral src) { |
6354 fld_d(as_Address(src)); | |
6355 } | |
6356 | |
6357 void MacroAssembler::fld_s(AddressLiteral src) { | |
6358 fld_s(as_Address(src)); | |
6359 } | |
6360 | |
6361 void MacroAssembler::fld_x(AddressLiteral src) { | |
6362 Assembler::fld_x(as_Address(src)); | |
6363 } | |
6364 | |
6365 void MacroAssembler::fldcw(AddressLiteral src) { | |
6366 Assembler::fldcw(as_Address(src)); | |
6367 } | |
0 | 6368 |
6369 void MacroAssembler::fpop() { | |
6370 ffree(); | |
6371 fincstp(); | |
6372 } | |
6373 | |
304 | 6374 void MacroAssembler::fremr(Register tmp) { |
6375 save_rax(tmp); | |
6376 { Label L; | |
6377 bind(L); | |
6378 fprem(); | |
6379 fwait(); fnstsw_ax(); | |
6380 #ifdef _LP64 | |
6381 testl(rax, 0x400); | |
6382 jcc(Assembler::notEqual, L); | |
6383 #else | |
6384 sahf(); | |
6385 jcc(Assembler::parity, L); | |
6386 #endif // _LP64 | |
6387 } | |
6388 restore_rax(tmp); | |
6389 // Result is in ST0. | |
6390 // Note: fxch & fpop to get rid of ST1 | |
6391 // (otherwise FPU stack could overflow eventually) | |
6392 fxch(1); | |
6393 fpop(); | |
6394 } | |
6395 | |
6396 | |
6397 void MacroAssembler::incrementl(AddressLiteral dst) { | |
6398 if (reachable(dst)) { | |
6399 incrementl(as_Address(dst)); | |
0 | 6400 } else { |
304 | 6401 lea(rscratch1, dst); |
6402 incrementl(Address(rscratch1, 0)); | |
6403 } | |
6404 } | |
6405 | |
6406 void MacroAssembler::incrementl(ArrayAddress dst) { | |
6407 incrementl(as_Address(dst)); | |
6408 } | |
6409 | |
6410 void MacroAssembler::incrementl(Register reg, int value) { | |
6411 if (value == min_jint) {addl(reg, value) ; return; } | |
6412 if (value < 0) { decrementl(reg, -value); return; } | |
6413 if (value == 0) { ; return; } | |
6414 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
6415 /* else */ { addl(reg, value) ; return; } | |
6416 } | |
6417 | |
6418 void MacroAssembler::incrementl(Address dst, int value) { | |
6419 if (value == min_jint) {addl(dst, value) ; return; } | |
6420 if (value < 0) { decrementl(dst, -value); return; } | |
6421 if (value == 0) { ; return; } | |
6422 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
6423 /* else */ { addl(dst, value) ; return; } | |
6424 } | |
6425 | |
6426 void MacroAssembler::jump(AddressLiteral dst) { | |
6427 if (reachable(dst)) { | |
6428 jmp_literal(dst.target(), dst.rspec()); | |
6429 } else { | |
6430 lea(rscratch1, dst); | |
6431 jmp(rscratch1); | |
6432 } | |
6433 } | |
6434 | |
6435 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
6436 if (reachable(dst)) { | |
6437 InstructionMark im(this); | |
6438 relocate(dst.reloc()); | |
6439 const int short_size = 2; | |
6440 const int long_size = 6; | |
6441 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
6442 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
6443 // 0111 tttn #8-bit disp | |
6444 emit_byte(0x70 | cc); | |
6445 emit_byte((offs - short_size) & 0xFF); | |
6446 } else { | |
6447 // 0000 1111 1000 tttn #32-bit disp | |
6448 emit_byte(0x0F); | |
6449 emit_byte(0x80 | cc); | |
6450 emit_long(offs - long_size); | |
6451 } | |
0 | 6452 } else { |
304 | 6453 #ifdef ASSERT |
6454 warning("reversing conditional branch"); | |
6455 #endif /* ASSERT */ | |
6456 Label skip; | |
6457 jccb(reverse[cc], skip); | |
6458 lea(rscratch1, dst); | |
6459 Assembler::jmp(rscratch1); | |
6460 bind(skip); | |
6461 } | |
6462 } | |
6463 | |
6464 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
6465 if (reachable(src)) { | |
6466 Assembler::ldmxcsr(as_Address(src)); | |
6467 } else { | |
6468 lea(rscratch1, src); | |
6469 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
6470 } | |
6471 } | |
6472 | |
6473 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
6474 int off; | |
6475 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6476 off = offset(); | |
6477 movsbl(dst, src); // movsxb | |
6478 } else { | |
6479 off = load_unsigned_byte(dst, src); | |
6480 shll(dst, 24); | |
6481 sarl(dst, 24); | |
6482 } | |
6483 return off; | |
6484 } | |
6485 | |
622
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6486 // Note: load_signed_short used to be called load_signed_word. |
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6487 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
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6488 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
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6489 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
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6490 int MacroAssembler::load_signed_short(Register dst, Address src) { |
304 | 6491 int off; |
6492 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6493 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
6494 // version but this is what 64bit has always done. This seems to imply | |
6495 // that users are only using 32bits worth. | |
6496 off = offset(); | |
6497 movswl(dst, src); // movsxw | |
6498 } else { | |
622
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6499 off = load_unsigned_short(dst, src); |
304 | 6500 shll(dst, 16); |
6501 sarl(dst, 16); | |
6502 } | |
6503 return off; | |
6504 } | |
6505 | |
6506 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
6507 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
6508 // and "3.9 Partial Register Penalties", p. 22). | |
6509 int off; | |
6510 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
6511 off = offset(); | |
6512 movzbl(dst, src); // movzxb | |
6513 } else { | |
6514 xorl(dst, dst); | |
6515 off = offset(); | |
6516 movb(dst, src); | |
6517 } | |
6518 return off; | |
6519 } | |
6520 | |
622
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6521 // Note: load_unsigned_short used to be called load_unsigned_word. |
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6522 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
304 | 6523 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
6524 // and "3.9 Partial Register Penalties", p. 22). | |
6525 int off; | |
6526 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
6527 off = offset(); | |
6528 movzwl(dst, src); // movzxw | |
6529 } else { | |
6530 xorl(dst, dst); | |
6531 off = offset(); | |
6532 movw(dst, src); | |
6533 } | |
6534 return off; | |
6535 } | |
6536 | |
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6537 void MacroAssembler::load_sized_value(Register dst, Address src, |
1503 | 6538 size_t size_in_bytes, bool is_signed) { |
6539 switch (size_in_bytes) { | |
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6540 #ifndef _LP64 |
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6541 // For case 8, caller is responsible for manually loading |
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6542 // the second word into another register. |
1503 | 6543 case 8: movl(dst, src); break; |
622
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6544 #else |
1503 | 6545 case 8: movq(dst, src); break; |
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6546 #endif |
1503 | 6547 case 4: movl(dst, src); break; |
6548 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; | |
6549 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; | |
6550 default: ShouldNotReachHere(); | |
622
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|
6551 } |
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|
6552 } |
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|
6553 |
304 | 6554 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
6555 if (reachable(dst)) { | |
6556 movl(as_Address(dst), src); | |
6557 } else { | |
6558 lea(rscratch1, dst); | |
6559 movl(Address(rscratch1, 0), src); | |
6560 } | |
6561 } | |
6562 | |
6563 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
6564 if (reachable(src)) { | |
6565 movl(dst, as_Address(src)); | |
6566 } else { | |
6567 lea(rscratch1, src); | |
6568 movl(dst, Address(rscratch1, 0)); | |
6569 } | |
0 | 6570 } |
6571 | |
6572 // C++ bool manipulation | |
6573 | |
6574 void MacroAssembler::movbool(Register dst, Address src) { | |
6575 if(sizeof(bool) == 1) | |
6576 movb(dst, src); | |
6577 else if(sizeof(bool) == 2) | |
6578 movw(dst, src); | |
6579 else if(sizeof(bool) == 4) | |
6580 movl(dst, src); | |
6581 else | |
6582 // unsupported | |
6583 ShouldNotReachHere(); | |
6584 } | |
6585 | |
6586 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
6587 if(sizeof(bool) == 1) | |
6588 movb(dst, (int) boolconst); | |
6589 else if(sizeof(bool) == 2) | |
6590 movw(dst, (int) boolconst); | |
6591 else if(sizeof(bool) == 4) | |
6592 movl(dst, (int) boolconst); | |
6593 else | |
6594 // unsupported | |
6595 ShouldNotReachHere(); | |
6596 } | |
6597 | |
6598 void MacroAssembler::movbool(Address dst, Register src) { | |
6599 if(sizeof(bool) == 1) | |
6600 movb(dst, src); | |
6601 else if(sizeof(bool) == 2) | |
6602 movw(dst, src); | |
6603 else if(sizeof(bool) == 4) | |
6604 movl(dst, src); | |
6605 else | |
6606 // unsupported | |
6607 ShouldNotReachHere(); | |
6608 } | |
6609 | |
304 | 6610 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
6611 movb(as_Address(dst), src); | |
6612 } | |
6613 | |
6614 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
6615 if (reachable(src)) { | |
6616 if (UseXmmLoadAndClearUpper) { | |
6617 movsd (dst, as_Address(src)); | |
6618 } else { | |
6619 movlpd(dst, as_Address(src)); | |
6620 } | |
6621 } else { | |
6622 lea(rscratch1, src); | |
6623 if (UseXmmLoadAndClearUpper) { | |
6624 movsd (dst, Address(rscratch1, 0)); | |
6625 } else { | |
6626 movlpd(dst, Address(rscratch1, 0)); | |
6627 } | |
6628 } | |
6629 } | |
6630 | |
6631 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
6632 if (reachable(src)) { | |
6633 movss(dst, as_Address(src)); | |
6634 } else { | |
6635 lea(rscratch1, src); | |
6636 movss(dst, Address(rscratch1, 0)); | |
6637 } | |
6638 } | |
6639 | |
6640 void MacroAssembler::movptr(Register dst, Register src) { | |
6641 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6642 } | |
6643 | |
6644 void MacroAssembler::movptr(Register dst, Address src) { | |
6645 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6646 } | |
6647 | |
6648 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
6649 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
6650 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
6651 } | |
6652 | |
6653 void MacroAssembler::movptr(Address dst, Register src) { | |
6654 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6655 } | |
6656 | |
6657 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
6658 if (reachable(src)) { | |
6659 movss(dst, as_Address(src)); | |
6660 } else { | |
6661 lea(rscratch1, src); | |
6662 movss(dst, Address(rscratch1, 0)); | |
6663 } | |
6664 } | |
6665 | |
6666 void MacroAssembler::null_check(Register reg, int offset) { | |
6667 if (needs_explicit_null_check(offset)) { | |
6668 // provoke OS NULL exception if reg = NULL by | |
6669 // accessing M[reg] w/o changing any (non-CC) registers | |
6670 // NOTE: cmpl is plenty here to provoke a segv | |
6671 cmpptr(rax, Address(reg, 0)); | |
6672 // Note: should probably use testl(rax, Address(reg, 0)); | |
6673 // may be shorter code (however, this version of | |
6674 // testl needs to be implemented first) | |
6675 } else { | |
6676 // nothing to do, (later) access of M[reg + offset] | |
6677 // will provoke OS NULL exception if reg = NULL | |
6678 } | |
6679 } | |
6680 | |
6681 void MacroAssembler::os_breakpoint() { | |
6682 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
6683 // (e.g., MSVC can't call ps() otherwise) | |
6684 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
6685 } | |
6686 | |
6687 void MacroAssembler::pop_CPU_state() { | |
6688 pop_FPU_state(); | |
6689 pop_IU_state(); | |
6690 } | |
6691 | |
6692 void MacroAssembler::pop_FPU_state() { | |
6693 NOT_LP64(frstor(Address(rsp, 0));) | |
6694 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
6695 addptr(rsp, FPUStateSizeInWords * wordSize); | |
6696 } | |
6697 | |
6698 void MacroAssembler::pop_IU_state() { | |
6699 popa(); | |
6700 LP64_ONLY(addq(rsp, 8)); | |
6701 popf(); | |
6702 } | |
6703 | |
6704 // Save Integer and Float state | |
6705 // Warning: Stack must be 16 byte aligned (64bit) | |
6706 void MacroAssembler::push_CPU_state() { | |
6707 push_IU_state(); | |
6708 push_FPU_state(); | |
6709 } | |
6710 | |
6711 void MacroAssembler::push_FPU_state() { | |
6712 subptr(rsp, FPUStateSizeInWords * wordSize); | |
6713 #ifndef _LP64 | |
6714 fnsave(Address(rsp, 0)); | |
6715 fwait(); | |
6716 #else | |
6717 fxsave(Address(rsp, 0)); | |
6718 #endif // LP64 | |
6719 } | |
6720 | |
6721 void MacroAssembler::push_IU_state() { | |
6722 // Push flags first because pusha kills them | |
6723 pushf(); | |
6724 // Make sure rsp stays 16-byte aligned | |
6725 LP64_ONLY(subq(rsp, 8)); | |
6726 pusha(); | |
6727 } | |
6728 | |
6729 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
6730 // determine java_thread register | |
6731 if (!java_thread->is_valid()) { | |
6732 java_thread = rdi; | |
6733 get_thread(java_thread); | |
6734 } | |
6735 // we must set sp to zero to clear frame | |
512
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|
6736 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
304 | 6737 if (clear_fp) { |
512
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|
6738 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
304 | 6739 } |
6740 | |
6741 if (clear_pc) | |
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|
6742 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
304 | 6743 |
6744 } | |
6745 | |
6746 void MacroAssembler::restore_rax(Register tmp) { | |
6747 if (tmp == noreg) pop(rax); | |
6748 else if (tmp != rax) mov(rax, tmp); | |
6749 } | |
6750 | |
6751 void MacroAssembler::round_to(Register reg, int modulus) { | |
6752 addptr(reg, modulus - 1); | |
6753 andptr(reg, -modulus); | |
6754 } | |
6755 | |
6756 void MacroAssembler::save_rax(Register tmp) { | |
6757 if (tmp == noreg) push(rax); | |
6758 else if (tmp != rax) mov(tmp, rax); | |
6759 } | |
6760 | |
6761 // Write serialization page so VM thread can do a pseudo remote membar. | |
6762 // We use the current thread pointer to calculate a thread specific | |
6763 // offset to write to within the page. This minimizes bus traffic | |
6764 // due to cache line collision. | |
6765 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
6766 movl(tmp, thread); | |
6767 shrl(tmp, os::get_serialize_page_shift_count()); | |
6768 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
6769 | |
6770 Address index(noreg, tmp, Address::times_1); | |
6771 ExternalAddress page(os::get_memory_serialize_page()); | |
6772 | |
606
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
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520
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|
6773 // Size of store must match masking code above |
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
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|
6774 movl(as_Address(ArrayAddress(page, index)), tmp); |
304 | 6775 } |
6776 | |
6777 // Calls to C land | |
6778 // | |
6779 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
6780 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
6781 // has to be reset to 0. This is required to allow proper stack traversal. | |
6782 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
6783 Register last_java_sp, | |
6784 Register last_java_fp, | |
6785 address last_java_pc) { | |
6786 // determine java_thread register | |
6787 if (!java_thread->is_valid()) { | |
6788 java_thread = rdi; | |
6789 get_thread(java_thread); | |
6790 } | |
6791 // determine last_java_sp register | |
6792 if (!last_java_sp->is_valid()) { | |
6793 last_java_sp = rsp; | |
6794 } | |
6795 | |
6796 // last_java_fp is optional | |
6797 | |
6798 if (last_java_fp->is_valid()) { | |
6799 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
6800 } | |
6801 | |
6802 // last_java_pc is optional | |
6803 | |
6804 if (last_java_pc != NULL) { | |
6805 lea(Address(java_thread, | |
6806 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
6807 InternalAddress(last_java_pc)); | |
6808 | |
6809 } | |
6810 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
6811 } | |
6812 | |
6813 void MacroAssembler::shlptr(Register dst, int imm8) { | |
6814 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
6815 } | |
6816 | |
6817 void MacroAssembler::shrptr(Register dst, int imm8) { | |
6818 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
6819 } | |
6820 | |
6821 void MacroAssembler::sign_extend_byte(Register reg) { | |
6822 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
6823 movsbl(reg, reg); // movsxb | |
6824 } else { | |
6825 shll(reg, 24); | |
6826 sarl(reg, 24); | |
6827 } | |
6828 } | |
6829 | |
6830 void MacroAssembler::sign_extend_short(Register reg) { | |
6831 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6832 movswl(reg, reg); // movsxw | |
6833 } else { | |
6834 shll(reg, 16); | |
6835 sarl(reg, 16); | |
6836 } | |
6837 } | |
6838 | |
362 | 6839 ////////////////////////////////////////////////////////////////////////////////// |
6840 #ifndef SERIALGC | |
6841 | |
6842 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
6843 #ifndef _LP64 | |
6844 Register thread, | |
6845 #endif | |
6846 Register tmp, | |
6847 Register tmp2, | |
6848 bool tosca_live) { | |
6849 LP64_ONLY(Register thread = r15_thread;) | |
6850 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6851 PtrQueue::byte_offset_of_active())); | |
6852 | |
6853 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6854 PtrQueue::byte_offset_of_index())); | |
6855 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6856 PtrQueue::byte_offset_of_buf())); | |
6857 | |
6858 | |
6859 Label done; | |
6860 Label runtime; | |
6861 | |
6862 // if (!marking_in_progress) goto done; | |
6863 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
6864 cmpl(in_progress, 0); | |
6865 } else { | |
6866 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
6867 cmpb(in_progress, 0); | |
6868 } | |
6869 jcc(Assembler::equal, done); | |
6870 | |
6871 // if (x.f == NULL) goto done; | |
845
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6700789: G1: Enable use of compressed oops with G1 heaps
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diff
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|
6872 #ifdef _LP64 |
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6700789: G1: Enable use of compressed oops with G1 heaps
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|
6873 load_heap_oop(tmp2, Address(obj, 0)); |
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6700789: G1: Enable use of compressed oops with G1 heaps
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|
6874 #else |
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
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|
6875 movptr(tmp2, Address(obj, 0)); |
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6700789: G1: Enable use of compressed oops with G1 heaps
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diff
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|
6876 #endif |
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|
6877 cmpptr(tmp2, (int32_t) NULL_WORD); |
362 | 6878 jcc(Assembler::equal, done); |
6879 | |
6880 // Can we store original value in the thread's buffer? | |
6881 | |
6882 #ifdef _LP64 | |
845
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6700789: G1: Enable use of compressed oops with G1 heaps
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775
diff
changeset
|
6883 movslq(tmp, index); |
362 | 6884 cmpq(tmp, 0); |
6885 #else | |
6886 cmpl(index, 0); | |
6887 #endif | |
6888 jcc(Assembler::equal, runtime); | |
6889 #ifdef _LP64 | |
6890 subq(tmp, wordSize); | |
6891 movl(index, tmp); | |
6892 addq(tmp, buffer); | |
6893 #else | |
6894 subl(index, wordSize); | |
6895 movl(tmp, buffer); | |
6896 addl(tmp, index); | |
6897 #endif | |
6898 movptr(Address(tmp, 0), tmp2); | |
6899 jmp(done); | |
6900 bind(runtime); | |
6901 // save the live input values | |
6902 if(tosca_live) push(rax); | |
6903 push(obj); | |
6904 #ifdef _LP64 | |
845
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diff
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|
6905 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread); |
362 | 6906 #else |
6907 push(thread); | |
6908 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); | |
6909 pop(thread); | |
6910 #endif | |
6911 pop(obj); | |
6912 if(tosca_live) pop(rax); | |
6913 bind(done); | |
6914 | |
6915 } | |
6916 | |
6917 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
6918 Register new_val, | |
6919 #ifndef _LP64 | |
6920 Register thread, | |
6921 #endif | |
6922 Register tmp, | |
6923 Register tmp2) { | |
6924 | |
6925 LP64_ONLY(Register thread = r15_thread;) | |
6926 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
6927 PtrQueue::byte_offset_of_index())); | |
6928 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
6929 PtrQueue::byte_offset_of_buf())); | |
6930 BarrierSet* bs = Universe::heap()->barrier_set(); | |
6931 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
6932 Label done; | |
6933 Label runtime; | |
6934 | |
6935 // Does store cross heap regions? | |
6936 | |
6937 movptr(tmp, store_addr); | |
6938 xorptr(tmp, new_val); | |
6939 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
6940 jcc(Assembler::equal, done); | |
6941 | |
6942 // crosses regions, storing NULL? | |
6943 | |
6944 cmpptr(new_val, (int32_t) NULL_WORD); | |
6945 jcc(Assembler::equal, done); | |
6946 | |
6947 // storing region crossing non-NULL, is card already dirty? | |
6948 | |
6949 ExternalAddress cardtable((address) ct->byte_map_base); | |
6950 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
6951 #ifdef _LP64 | |
6952 const Register card_addr = tmp; | |
6953 | |
6954 movq(card_addr, store_addr); | |
6955 shrq(card_addr, CardTableModRefBS::card_shift); | |
6956 | |
6957 lea(tmp2, cardtable); | |
6958 | |
6959 // get the address of the card | |
6960 addq(card_addr, tmp2); | |
6961 #else | |
6962 const Register card_index = tmp; | |
6963 | |
6964 movl(card_index, store_addr); | |
6965 shrl(card_index, CardTableModRefBS::card_shift); | |
6966 | |
6967 Address index(noreg, card_index, Address::times_1); | |
6968 const Register card_addr = tmp; | |
6969 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
6970 #endif | |
6971 cmpb(Address(card_addr, 0), 0); | |
6972 jcc(Assembler::equal, done); | |
6973 | |
6974 // storing a region crossing, non-NULL oop, card is clean. | |
6975 // dirty card and log. | |
6976 | |
6977 movb(Address(card_addr, 0), 0); | |
6978 | |
6979 cmpl(queue_index, 0); | |
6980 jcc(Assembler::equal, runtime); | |
6981 subl(queue_index, wordSize); | |
6982 movptr(tmp2, buffer); | |
6983 #ifdef _LP64 | |
6984 movslq(rscratch1, queue_index); | |
6985 addq(tmp2, rscratch1); | |
6986 movq(Address(tmp2, 0), card_addr); | |
6987 #else | |
6988 addl(tmp2, queue_index); | |
6989 movl(Address(tmp2, 0), card_index); | |
6990 #endif | |
6991 jmp(done); | |
6992 | |
6993 bind(runtime); | |
6994 // save the live input values | |
6995 push(store_addr); | |
6996 push(new_val); | |
6997 #ifdef _LP64 | |
6998 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
6999 #else | |
7000 push(thread); | |
7001 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
7002 pop(thread); | |
7003 #endif | |
7004 pop(new_val); | |
7005 pop(store_addr); | |
7006 | |
7007 bind(done); | |
7008 | |
7009 } | |
7010 | |
7011 #endif // SERIALGC | |
7012 ////////////////////////////////////////////////////////////////////////////////// | |
7013 | |
7014 | |
304 | 7015 void MacroAssembler::store_check(Register obj) { |
7016 // Does a store check for the oop in register obj. The content of | |
7017 // register obj is destroyed afterwards. | |
7018 store_check_part_1(obj); | |
7019 store_check_part_2(obj); | |
7020 } | |
7021 | |
7022 void MacroAssembler::store_check(Register obj, Address dst) { | |
7023 store_check(obj); | |
7024 } | |
7025 | |
7026 | |
7027 // split the store check operation so that other instructions can be scheduled inbetween | |
7028 void MacroAssembler::store_check_part_1(Register obj) { | |
7029 BarrierSet* bs = Universe::heap()->barrier_set(); | |
7030 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
7031 shrptr(obj, CardTableModRefBS::card_shift); | |
7032 } | |
7033 | |
7034 void MacroAssembler::store_check_part_2(Register obj) { | |
7035 BarrierSet* bs = Universe::heap()->barrier_set(); | |
7036 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
7037 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
7038 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
7039 | |
7040 // The calculation for byte_map_base is as follows: | |
7041 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
7042 // So this essentially converts an address to a displacement and | |
7043 // it will never need to be relocated. On 64bit however the value may be too | |
7044 // large for a 32bit displacement | |
7045 | |
7046 intptr_t disp = (intptr_t) ct->byte_map_base; | |
7047 if (is_simm32(disp)) { | |
7048 Address cardtable(noreg, obj, Address::times_1, disp); | |
7049 movb(cardtable, 0); | |
7050 } else { | |
7051 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
7052 // displacement and done in a single instruction given favorable mapping and | |
7053 // a smarter version of as_Address. Worst case it is two instructions which | |
7054 // is no worse off then loading disp into a register and doing as a simple | |
7055 // Address() as above. | |
7056 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
7057 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
7058 // in some cases we'll get a single instruction version. | |
7059 | |
7060 ExternalAddress cardtable((address)disp); | |
7061 Address index(noreg, obj, Address::times_1); | |
7062 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
7063 } | |
7064 } | |
7065 | |
7066 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
7067 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
7068 } | |
7069 | |
7070 void MacroAssembler::subptr(Register dst, Register src) { | |
7071 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
7072 } | |
7073 | |
7074 void MacroAssembler::test32(Register src1, AddressLiteral src2) { | |
7075 // src2 must be rval | |
7076 | |
7077 if (reachable(src2)) { | |
7078 testl(src1, as_Address(src2)); | |
7079 } else { | |
7080 lea(rscratch1, src2); | |
7081 testl(src1, Address(rscratch1, 0)); | |
7082 } | |
7083 } | |
7084 | |
7085 // C++ bool manipulation | |
0 | 7086 void MacroAssembler::testbool(Register dst) { |
7087 if(sizeof(bool) == 1) | |
304 | 7088 testb(dst, 0xff); |
0 | 7089 else if(sizeof(bool) == 2) { |
7090 // testw implementation needed for two byte bools | |
7091 ShouldNotReachHere(); | |
7092 } else if(sizeof(bool) == 4) | |
7093 testl(dst, dst); | |
7094 else | |
7095 // unsupported | |
7096 ShouldNotReachHere(); | |
7097 } | |
7098 | |
304 | 7099 void MacroAssembler::testptr(Register dst, Register src) { |
7100 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
7101 } | |
7102 | |
7103 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
7104 void MacroAssembler::tlab_allocate(Register obj, | |
7105 Register var_size_in_bytes, | |
7106 int con_size_in_bytes, | |
7107 Register t1, | |
7108 Register t2, | |
7109 Label& slow_case) { | |
7110 assert_different_registers(obj, t1, t2); | |
7111 assert_different_registers(obj, var_size_in_bytes, t1); | |
7112 Register end = t2; | |
7113 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
7114 | |
7115 verify_tlab(); | |
7116 | |
7117 NOT_LP64(get_thread(thread)); | |
7118 | |
7119 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
7120 if (var_size_in_bytes == noreg) { | |
7121 lea(end, Address(obj, con_size_in_bytes)); | |
7122 } else { | |
7123 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
7124 } | |
7125 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
7126 jcc(Assembler::above, slow_case); | |
7127 | |
7128 // update the tlab top pointer | |
7129 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
7130 | |
7131 // recover var_size_in_bytes if necessary | |
7132 if (var_size_in_bytes == end) { | |
7133 subptr(var_size_in_bytes, obj); | |
7134 } | |
7135 verify_tlab(); | |
7136 } | |
7137 | |
7138 // Preserves rbx, and rdx. | |
7139 void MacroAssembler::tlab_refill(Label& retry, | |
7140 Label& try_eden, | |
7141 Label& slow_case) { | |
7142 Register top = rax; | |
7143 Register t1 = rcx; | |
7144 Register t2 = rsi; | |
7145 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
7146 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
7147 Label do_refill, discard_tlab; | |
7148 | |
7149 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
7150 // No allocation in the shared eden. | |
7151 jmp(slow_case); | |
7152 } | |
7153 | |
7154 NOT_LP64(get_thread(thread_reg)); | |
7155 | |
7156 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7157 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
7158 | |
7159 // calculate amount of free space | |
7160 subptr(t1, top); | |
7161 shrptr(t1, LogHeapWordSize); | |
7162 | |
7163 // Retain tlab and allocate object in shared space if | |
7164 // the amount free in the tlab is too large to discard. | |
7165 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
7166 jcc(Assembler::lessEqual, discard_tlab); | |
7167 | |
7168 // Retain | |
7169 // %%% yuck as movptr... | |
7170 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
7171 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
7172 if (TLABStats) { | |
7173 // increment number of slow_allocations | |
7174 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
7175 } | |
7176 jmp(try_eden); | |
7177 | |
7178 bind(discard_tlab); | |
7179 if (TLABStats) { | |
7180 // increment number of refills | |
7181 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
7182 // accumulate wastage -- t1 is amount free in tlab | |
7183 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
7184 } | |
7185 | |
7186 // if tlab is currently allocated (top or end != null) then | |
7187 // fill [top, end + alignment_reserve) with array object | |
7188 testptr (top, top); | |
7189 jcc(Assembler::zero, do_refill); | |
7190 | |
7191 // set up the mark word | |
7192 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
7193 // set the length to the remaining space | |
7194 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
7195 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
7196 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
1690 | 7197 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
304 | 7198 // set klass to intArrayKlass |
7199 // dubious reloc why not an oop reloc? | |
7200 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr())); | |
7201 // store klass last. concurrent gcs assumes klass length is valid if | |
7202 // klass field is not null. | |
7203 store_klass(top, t1); | |
7204 | |
7205 // refill the tlab with an eden allocation | |
7206 bind(do_refill); | |
7207 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
7208 shlptr(t1, LogHeapWordSize); | |
7209 // add object_size ?? | |
7210 eden_allocate(top, t1, 0, t2, slow_case); | |
7211 | |
7212 // Check that t1 was preserved in eden_allocate. | |
7213 #ifdef ASSERT | |
7214 if (UseTLAB) { | |
7215 Label ok; | |
7216 Register tsize = rsi; | |
7217 assert_different_registers(tsize, thread_reg, t1); | |
7218 push(tsize); | |
7219 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
7220 shlptr(tsize, LogHeapWordSize); | |
7221 cmpptr(t1, tsize); | |
7222 jcc(Assembler::equal, ok); | |
7223 stop("assert(t1 != tlab size)"); | |
7224 should_not_reach_here(); | |
7225 | |
7226 bind(ok); | |
7227 pop(tsize); | |
7228 } | |
7229 #endif | |
7230 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
7231 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
7232 addptr(top, t1); | |
7233 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
7234 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
7235 verify_tlab(); | |
7236 jmp(retry); | |
7237 } | |
7238 | |
7239 static const double pi_4 = 0.7853981633974483; | |
7240 | |
7241 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
7242 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
7243 // was attempted in this code; unfortunately it appears that the | |
7244 // switch to 80-bit precision and back causes this to be | |
7245 // unprofitable compared with simply performing a runtime call if | |
7246 // the argument is out of the (-pi/4, pi/4) range. | |
7247 | |
7248 Register tmp = noreg; | |
7249 if (!VM_Version::supports_cmov()) { | |
7250 // fcmp needs a temporary so preserve rbx, | |
7251 tmp = rbx; | |
7252 push(tmp); | |
7253 } | |
7254 | |
7255 Label slow_case, done; | |
7256 | |
520
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7257 ExternalAddress pi4_adr = (address)&pi_4; |
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7258 if (reachable(pi4_adr)) { |
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7259 // x ?<= pi/4 |
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7260 fld_d(pi4_adr); |
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7261 fld_s(1); // Stack: X PI/4 X |
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7262 fabs(); // Stack: |X| PI/4 X |
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7263 fcmp(tmp); |
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7264 jcc(Assembler::above, slow_case); |
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7265 |
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7266 // fastest case: -pi/4 <= x <= pi/4 |
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|
7267 switch(trig) { |
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|
7268 case 's': |
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|
7269 fsin(); |
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|
7270 break; |
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|
7271 case 'c': |
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|
7272 fcos(); |
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|
7273 break; |
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|
7274 case 't': |
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|
7275 ftan(); |
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|
7276 break; |
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|
7277 default: |
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|
7278 assert(false, "bad intrinsic"); |
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|
7279 break; |
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|
7280 } |
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|
7281 jmp(done); |
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|
7282 } |
304 | 7283 |
7284 // slow case: runtime call | |
7285 bind(slow_case); | |
7286 // Preserve registers across runtime call | |
7287 pusha(); | |
7288 int incoming_argument_and_return_value_offset = -1; | |
7289 if (num_fpu_regs_in_use > 1) { | |
7290 // Must preserve all other FPU regs (could alternatively convert | |
7291 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
7292 // FPU state, but can not trust C compiler) | |
7293 NEEDS_CLEANUP; | |
7294 // NOTE that in this case we also push the incoming argument to | |
7295 // the stack and restore it later; we also use this stack slot to | |
7296 // hold the return value from dsin or dcos. | |
7297 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
7298 subptr(rsp, sizeof(jdouble)); | |
7299 fstp_d(Address(rsp, 0)); | |
7300 } | |
7301 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
7302 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
7303 } | |
7304 subptr(rsp, sizeof(jdouble)); | |
7305 fstp_d(Address(rsp, 0)); | |
7306 #ifdef _LP64 | |
7307 movdbl(xmm0, Address(rsp, 0)); | |
7308 #endif // _LP64 | |
7309 | |
7310 // NOTE: we must not use call_VM_leaf here because that requires a | |
7311 // complete interpreter frame in debug mode -- same bug as 4387334 | |
7312 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
7313 // do proper 64bit abi | |
7314 | |
7315 NEEDS_CLEANUP; | |
7316 // Need to add stack banging before this runtime call if it needs to | |
7317 // be taken; however, there is no generic stack banging routine at | |
7318 // the MacroAssembler level | |
7319 switch(trig) { | |
7320 case 's': | |
7321 { | |
7322 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
7323 } | |
7324 break; | |
7325 case 'c': | |
7326 { | |
7327 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
7328 } | |
7329 break; | |
7330 case 't': | |
7331 { | |
7332 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
7333 } | |
7334 break; | |
7335 default: | |
7336 assert(false, "bad intrinsic"); | |
7337 break; | |
7338 } | |
7339 #ifdef _LP64 | |
7340 movsd(Address(rsp, 0), xmm0); | |
7341 fld_d(Address(rsp, 0)); | |
7342 #endif // _LP64 | |
7343 addptr(rsp, sizeof(jdouble)); | |
7344 if (num_fpu_regs_in_use > 1) { | |
7345 // Must save return value to stack and then restore entire FPU stack | |
7346 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
7347 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
7348 fld_d(Address(rsp, 0)); | |
7349 addptr(rsp, sizeof(jdouble)); | |
7350 } | |
7351 } | |
7352 popa(); | |
7353 | |
7354 // Come here with result in F-TOS | |
7355 bind(done); | |
7356 | |
7357 if (tmp != noreg) { | |
7358 pop(tmp); | |
7359 } | |
7360 } | |
7361 | |
7362 | |
623
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7363 // Look up the method for a megamorphic invokeinterface call. |
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7364 // The target method is determined by <intf_klass, itable_index>. |
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7365 // The receiver klass is in recv_klass. |
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7366 // On success, the result will be in method_result, and execution falls through. |
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7367 // On failure, execution transfers to the given label. |
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7368 void MacroAssembler::lookup_interface_method(Register recv_klass, |
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7369 Register intf_klass, |
665
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|
7370 RegisterOrConstant itable_index, |
623
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7371 Register method_result, |
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7372 Register scan_temp, |
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7373 Label& L_no_such_interface) { |
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7374 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
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|
7375 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
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7376 "caller must use same register for non-constant itable index as for method"); |
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|
7377 |
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|
7378 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
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7379 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
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7380 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
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7381 int scan_step = itableOffsetEntry::size() * wordSize; |
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|
7382 int vte_size = vtableEntry::size() * wordSize; |
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|
7383 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
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|
7384 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
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|
7385 |
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|
7386 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
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|
7387 |
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|
7388 // %%% Could store the aligned, prescaled offset in the klassoop. |
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|
7389 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7390 if (HeapWordsPerLong > 1) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7391 // Round up to align_object_offset boundary |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7392 // see code for instanceKlass::start_of_itable! |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7393 round_to(scan_temp, BytesPerLong); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7394 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7395 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7396 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7397 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7398 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7399 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7400 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7401 // if (scan->interface() == intf) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7402 // result = (klass + scan->offset() + itable_index); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7403 // } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7404 // } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7405 Label search, found_method; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7406 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7407 for (int peel = 1; peel >= 0; peel--) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7408 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7409 cmpptr(intf_klass, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7410 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7411 if (peel) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7412 jccb(Assembler::equal, found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7413 } else { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7414 jccb(Assembler::notEqual, search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7415 // (invert the test to fall through to found_method...) |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7416 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7417 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7418 if (!peel) break; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7419 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7420 bind(search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7421 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7422 // Check that the previous entry is non-null. A null entry means that |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7423 // the receiver class doesn't implement the interface, and wasn't the |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7424 // same as when the caller was compiled. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7425 testptr(method_result, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7426 jcc(Assembler::zero, L_no_such_interface); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7427 addptr(scan_temp, scan_step); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7428 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7429 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7430 bind(found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7431 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7432 // Got a hit. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7433 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7434 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7435 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7436 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7437 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7438 void MacroAssembler::check_klass_subtype(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7439 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7440 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7441 Label& L_success) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7442 Label L_failure; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7443 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7444 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7445 bind(L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7446 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7447 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7448 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7449 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7450 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7451 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7452 Label* L_success, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7453 Label* L_failure, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7454 Label* L_slow_path, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7455 RegisterOrConstant super_check_offset) { |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7456 assert_different_registers(sub_klass, super_klass, temp_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7457 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7458 if (super_check_offset.is_register()) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7459 assert_different_registers(sub_klass, super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7460 super_check_offset.as_register()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7461 } else if (must_load_sco) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7462 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7463 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7464 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7465 Label L_fallthrough; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7466 int label_nulls = 0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7467 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7468 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7469 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7470 assert(label_nulls <= 1, "at most one NULL in the batch"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7471 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7472 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7473 Klass::secondary_super_cache_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7474 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7475 Klass::super_check_offset_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7476 Address super_check_offset_addr(super_klass, sco_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7477 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7478 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7479 // range of a jccb. If this routine grows larger, reconsider at |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7480 // least some of these. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7481 #define local_jcc(assembler_cond, label) \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7482 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7483 else jcc( assembler_cond, label) /*omit semi*/ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7484 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7485 // Hacked jmp, which may only be used just before L_fallthrough. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7486 #define final_jmp(label) \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7487 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7488 else jmp(label) /*omit semi*/ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7489 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7490 // If the pointers are equal, we are done (e.g., String[] elements). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7491 // This self-check enables sharing of secondary supertype arrays among |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7492 // non-primary types such as array-of-interface. Otherwise, each such |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7493 // type would need its own customized SSA. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7494 // We move this check to the front of the fast path because many |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7495 // type checks are in fact trivially successful in this manner, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7496 // so we get a nicely predicted branch right at the start of the check. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7497 cmpptr(sub_klass, super_klass); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7498 local_jcc(Assembler::equal, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7499 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7500 // Check the supertype display: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7501 if (must_load_sco) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7502 // Positive movl does right thing on LP64. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7503 movl(temp_reg, super_check_offset_addr); |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7504 super_check_offset = RegisterOrConstant(temp_reg); |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7505 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7506 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7507 cmpptr(super_klass, super_check_addr); // load displayed supertype |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7508 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7509 // This check has worked decisively for primary supers. |
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diff
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|
7510 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
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|
7511 // (Secondary supers are interfaces and very deeply nested subtypes.) |
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diff
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|
7512 // This works in the same check above because of a tricky aliasing |
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diff
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|
7513 // between the super_cache and the primary super display elements. |
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diff
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|
7514 // (The 'super_check_addr' can address either, as the case requires.) |
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diff
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|
7515 // Note that the cache is updated below if it does not help us find |
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diff
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|
7516 // what we need immediately. |
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diff
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|
7517 // So if it was a primary super, we can just fail immediately. |
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diff
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|
7518 // Otherwise, it's the slow path for us (no success at this point). |
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diff
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|
7519 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
7520 if (super_check_offset.is_register()) { |
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diff
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|
7521 local_jcc(Assembler::equal, *L_success); |
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diff
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|
7522 cmpl(super_check_offset.as_register(), sc_offset); |
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|
7523 if (L_failure == &L_fallthrough) { |
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diff
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|
7524 local_jcc(Assembler::equal, *L_slow_path); |
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diff
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|
7525 } else { |
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diff
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|
7526 local_jcc(Assembler::notEqual, *L_failure); |
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diff
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|
7527 final_jmp(*L_slow_path); |
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diff
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|
7528 } |
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diff
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|
7529 } else if (super_check_offset.as_constant() == sc_offset) { |
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diff
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|
7530 // Need a slow path; fast failure is impossible. |
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diff
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|
7531 if (L_slow_path == &L_fallthrough) { |
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diff
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|
7532 local_jcc(Assembler::equal, *L_success); |
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diff
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|
7533 } else { |
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diff
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|
7534 local_jcc(Assembler::notEqual, *L_slow_path); |
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643
diff
changeset
|
7535 final_jmp(*L_success); |
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diff
changeset
|
7536 } |
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diff
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|
7537 } else { |
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diff
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|
7538 // No slow path; it's a fast decision. |
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|
7539 if (L_failure == &L_fallthrough) { |
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|
7540 local_jcc(Assembler::equal, *L_success); |
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diff
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|
7541 } else { |
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643
diff
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|
7542 local_jcc(Assembler::notEqual, *L_failure); |
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diff
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|
7543 final_jmp(*L_success); |
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643
diff
changeset
|
7544 } |
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diff
changeset
|
7545 } |
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diff
changeset
|
7546 |
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643
diff
changeset
|
7547 bind(L_fallthrough); |
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parents:
643
diff
changeset
|
7548 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7549 #undef local_jcc |
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parents:
643
diff
changeset
|
7550 #undef final_jmp |
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parents:
643
diff
changeset
|
7551 } |
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643
diff
changeset
|
7552 |
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diff
changeset
|
7553 |
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diff
changeset
|
7554 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
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diff
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|
7555 Register super_klass, |
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diff
changeset
|
7556 Register temp_reg, |
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643
diff
changeset
|
7557 Register temp2_reg, |
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parents:
643
diff
changeset
|
7558 Label* L_success, |
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parents:
643
diff
changeset
|
7559 Label* L_failure, |
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parents:
643
diff
changeset
|
7560 bool set_cond_codes) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7561 assert_different_registers(sub_klass, super_klass, temp_reg); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7562 if (temp2_reg != noreg) |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7563 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
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diff
changeset
|
7564 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
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diff
changeset
|
7565 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7566 Label L_fallthrough; |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7567 int label_nulls = 0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7568 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7569 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
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643
diff
changeset
|
7570 assert(label_nulls <= 1, "at most one NULL in the batch"); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7571 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7572 // a couple of useful fields in sub_klass: |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7573 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7574 Klass::secondary_supers_offset_in_bytes()); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7575 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7576 Klass::secondary_super_cache_offset_in_bytes()); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7577 Address secondary_supers_addr(sub_klass, ss_offset); |
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643
diff
changeset
|
7578 Address super_cache_addr( sub_klass, sc_offset); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7579 |
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643
diff
changeset
|
7580 // Do a linear scan of the secondary super-klass chain. |
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643
diff
changeset
|
7581 // This code is rarely used, so simplicity is a virtue here. |
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643
diff
changeset
|
7582 // The repne_scan instruction uses fixed registers, which we must spill. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7583 // Don't worry too much about pre-existing connections with the input regs. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7584 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7585 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7586 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
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643
diff
changeset
|
7587 |
c517646eef23
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643
diff
changeset
|
7588 // Get super_klass value into rax (even if it was in rdi or rcx). |
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643
diff
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|
7589 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7590 if (super_klass != rax || UseCompressedOops) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7591 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
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jrose
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643
diff
changeset
|
7592 mov(rax, super_klass); |
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jrose
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643
diff
changeset
|
7593 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7594 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7595 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
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643
diff
changeset
|
7596 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7597 #ifndef PRODUCT |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7598 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7599 ExternalAddress pst_counter_addr((address) pst_counter); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7600 NOT_LP64( incrementl(pst_counter_addr) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7601 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7602 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7603 #endif //PRODUCT |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7604 |
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643
diff
changeset
|
7605 // We will consult the secondary-super array. |
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643
diff
changeset
|
7606 movptr(rdi, secondary_supers_addr); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7607 // Load the array length. (Positive movl does right thing on LP64.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7608 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7609 // Skip to start of data. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7610 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7611 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7612 // Scan RCX words at [RDI] for an occurrence of RAX. |
c517646eef23
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643
diff
changeset
|
7613 // Set NZ/Z based on last compare. |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7614 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7615 // not change flags (only scas instruction which is repeated sets flags). |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7616 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7617 #ifdef _LP64 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7618 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
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643
diff
changeset
|
7619 // and we store values in objArrays always encoded, thus we need to encode |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7620 // the value of rax before repne. Note that rax is dead after the repne. |
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643
diff
changeset
|
7621 if (UseCompressedOops) { |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7622 encode_heap_oop_not_null(rax); // Changes flags. |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7623 // The superclass is never null; it would be a basic system error if a null |
c517646eef23
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643
diff
changeset
|
7624 // pointer were to sneak in here. Note that we have already loaded the |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7625 // Klass::super_check_offset from the super_klass in the fast path, |
c517646eef23
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643
diff
changeset
|
7626 // so if there is a null in that register, we are already in the afterlife. |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7627 testl(rax,rax); // Set Z = 0 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7628 repne_scanl(); |
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|
7629 } else |
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|
7630 #endif // _LP64 |
1684
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6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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|
7631 { |
66c5dadb4d61
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parents:
1583
diff
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|
7632 testptr(rax,rax); // Set Z = 0 |
644
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|
7633 repne_scan(); |
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diff
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|
7634 } |
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7635 // Unspill the temp. registers: |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7636 if (pushed_rdi) pop(rdi); |
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|
7637 if (pushed_rcx) pop(rcx); |
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|
7638 if (pushed_rax) pop(rax); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7639 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
7640 if (set_cond_codes) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7641 // Special hack for the AD files: rdi is guaranteed non-zero. |
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|
7642 assert(!pushed_rdi, "rdi must be left non-NULL"); |
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diff
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|
7643 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7644 } |
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|
7645 |
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|
7646 if (L_failure == &L_fallthrough) |
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|
7647 jccb(Assembler::notEqual, *L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7648 else jcc(Assembler::notEqual, *L_failure); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7649 |
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|
7650 // Success. Cache the super we found and proceed in triumph. |
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|
7651 movptr(super_cache_addr, super_klass); |
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|
7652 |
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|
7653 if (L_success != &L_fallthrough) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7654 jmp(*L_success); |
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|
7655 } |
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|
7656 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7657 #undef IS_A_TEMP |
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|
7658 |
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|
7659 bind(L_fallthrough); |
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|
7660 } |
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|
7661 |
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|
7662 |
304 | 7663 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
7664 ucomisd(dst, as_Address(src)); | |
7665 } | |
7666 | |
7667 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7668 ucomiss(dst, as_Address(src)); | |
7669 } | |
7670 | |
7671 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7672 if (reachable(src)) { | |
7673 xorpd(dst, as_Address(src)); | |
7674 } else { | |
7675 lea(rscratch1, src); | |
7676 xorpd(dst, Address(rscratch1, 0)); | |
7677 } | |
7678 } | |
7679 | |
7680 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7681 if (reachable(src)) { | |
7682 xorps(dst, as_Address(src)); | |
7683 } else { | |
7684 lea(rscratch1, src); | |
7685 xorps(dst, Address(rscratch1, 0)); | |
7686 } | |
7687 } | |
7688 | |
0 | 7689 void MacroAssembler::verify_oop(Register reg, const char* s) { |
7690 if (!VerifyOops) return; | |
304 | 7691 |
0 | 7692 // Pass register number to verify_oop_subroutine |
7693 char* b = new char[strlen(s) + 50]; | |
7694 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
1583 | 7695 #ifdef _LP64 |
7696 push(rscratch1); // save r10, trashed by movptr() | |
7697 #endif | |
304 | 7698 push(rax); // save rax, |
7699 push(reg); // pass register argument | |
0 | 7700 ExternalAddress buffer((address) b); |
304 | 7701 // avoid using pushptr, as it modifies scratch registers |
7702 // and our contract is not to modify anything | |
7703 movptr(rax, buffer.addr()); | |
7704 push(rax); | |
0 | 7705 // call indirectly to solve generation ordering problem |
7706 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
7707 call(rax); | |
1583 | 7708 // Caller pops the arguments (oop, message) and restores rax, r10 |
0 | 7709 } |
7710 | |
7711 | |
665
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7712 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
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|
7713 Register tmp, |
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|
7714 int offset) { |
622
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7715 intptr_t value = *delayed_value_addr; |
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7716 if (value != 0) |
665
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7717 return RegisterOrConstant(value + offset); |
622
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|
7718 |
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|
7719 // load indirectly to solve generation ordering problem |
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|
7720 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
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7721 |
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|
7722 #ifdef ASSERT |
1793
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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|
7723 { Label L; |
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|
7724 testptr(tmp, tmp); |
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|
7725 if (WizardMode) { |
d257356e35f0
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|
7726 jcc(Assembler::notZero, L); |
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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|
7727 char* buf = new char[40]; |
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|
7728 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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|
7729 stop(buf); |
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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diff
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|
7730 } else { |
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|
7731 jccb(Assembler::notZero, L); |
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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parents:
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diff
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|
7732 hlt(); |
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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|
7733 } |
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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diff
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|
7734 bind(L); |
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|
7735 } |
622
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|
7736 #endif |
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|
7737 |
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|
7738 if (offset != 0) |
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|
7739 addptr(tmp, offset); |
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|
7740 |
665
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7741 return RegisterOrConstant(tmp); |
622
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|
7742 } |
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|
7743 |
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|
7744 |
710 | 7745 // registers on entry: |
7746 // - rax ('check' register): required MethodType | |
7747 // - rcx: method handle | |
7748 // - rdx, rsi, or ?: killable temp | |
7749 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
7750 Register temp_reg, | |
7751 Label& wrong_method_type) { | |
1846 | 7752 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)); |
710 | 7753 // compare method type against that of the receiver |
1846 | 7754 if (UseCompressedOops) { |
7755 load_heap_oop(temp_reg, type_addr); | |
7756 cmpptr(mtype_reg, temp_reg); | |
7757 } else { | |
7758 cmpptr(mtype_reg, type_addr); | |
7759 } | |
710 | 7760 jcc(Assembler::notEqual, wrong_method_type); |
7761 } | |
7762 | |
7763 | |
7764 // A method handle has a "vmslots" field which gives the size of its | |
7765 // argument list in JVM stack slots. This field is either located directly | |
7766 // in every method handle, or else is indirectly accessed through the | |
7767 // method handle's MethodType. This macro hides the distinction. | |
7768 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
7769 Register temp_reg) { | |
1503 | 7770 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
710 | 7771 // load mh.type.form.vmslots |
7772 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) { | |
7773 // hoist vmslots into every mh to avoid dependent load chain | |
7774 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg))); | |
7775 } else { | |
7776 Register temp2_reg = vmslots_reg; | |
1846 | 7777 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg))); |
7778 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg))); | |
710 | 7779 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); |
7780 } | |
7781 } | |
7782 | |
7783 | |
7784 // registers on entry: | |
7785 // - rcx: method handle | |
7786 // - rdx: killable temp (interpreted only) | |
7787 // - rax: killable temp (compiled only) | |
7788 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
7789 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
7790 assert_different_registers(mh_reg, temp_reg); | |
7791 | |
7792 // pick out the interpreted side of the handler | |
1846 | 7793 // NOTE: vmentry is not an oop! |
710 | 7794 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
7795 | |
7796 // off we go... | |
7797 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
7798 | |
7799 // for the various stubs which take control at this point, | |
7800 // see MethodHandles::generate_method_handle_stub | |
7801 } | |
7802 | |
7803 | |
7804 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
7805 int extra_slot_offset) { | |
7806 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
1506 | 7807 int stackElementSize = Interpreter::stackElementSize; |
710 | 7808 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
7809 #ifdef ASSERT | |
7810 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
7811 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
7812 #endif | |
7813 Register scale_reg = noreg; | |
7814 Address::ScaleFactor scale_factor = Address::no_scale; | |
7815 if (arg_slot.is_constant()) { | |
7816 offset += arg_slot.as_constant() * stackElementSize; | |
7817 } else { | |
7818 scale_reg = arg_slot.as_register(); | |
7819 scale_factor = Address::times(stackElementSize); | |
7820 } | |
7821 offset += wordSize; // return PC is on stack | |
7822 return Address(rsp, scale_reg, scale_factor, offset); | |
7823 } | |
7824 | |
7825 | |
0 | 7826 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
7827 if (!VerifyOops) return; | |
304 | 7828 |
0 | 7829 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
7830 // Pass register number to verify_oop_subroutine | |
7831 char* b = new char[strlen(s) + 50]; | |
7832 sprintf(b, "verify_oop_addr: %s", s); | |
304 | 7833 |
1583 | 7834 #ifdef _LP64 |
7835 push(rscratch1); // save r10, trashed by movptr() | |
7836 #endif | |
304 | 7837 push(rax); // save rax, |
0 | 7838 // addr may contain rsp so we will have to adjust it based on the push |
7839 // we just did | |
304 | 7840 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
7841 // stores rax into addr which is backwards of what was intended. | |
0 | 7842 if (addr.uses(rsp)) { |
304 | 7843 lea(rax, addr); |
7844 pushptr(Address(rax, BytesPerWord)); | |
0 | 7845 } else { |
304 | 7846 pushptr(addr); |
7847 } | |
7848 | |
0 | 7849 ExternalAddress buffer((address) b); |
7850 // pass msg argument | |
304 | 7851 // avoid using pushptr, as it modifies scratch registers |
7852 // and our contract is not to modify anything | |
7853 movptr(rax, buffer.addr()); | |
7854 push(rax); | |
7855 | |
0 | 7856 // call indirectly to solve generation ordering problem |
7857 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
7858 call(rax); | |
1583 | 7859 // Caller pops the arguments (addr, message) and restores rax, r10. |
0 | 7860 } |
7861 | |
304 | 7862 void MacroAssembler::verify_tlab() { |
7863 #ifdef ASSERT | |
7864 if (UseTLAB && VerifyOops) { | |
7865 Label next, ok; | |
7866 Register t1 = rsi; | |
7867 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
7868 | |
7869 push(t1); | |
7870 NOT_LP64(push(thread_reg)); | |
7871 NOT_LP64(get_thread(thread_reg)); | |
7872 | |
7873 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7874 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
7875 jcc(Assembler::aboveEqual, next); | |
7876 stop("assert(top >= start)"); | |
7877 should_not_reach_here(); | |
7878 | |
7879 bind(next); | |
7880 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
7881 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7882 jcc(Assembler::aboveEqual, ok); | |
7883 stop("assert(top <= end)"); | |
7884 should_not_reach_here(); | |
7885 | |
7886 bind(ok); | |
7887 NOT_LP64(pop(thread_reg)); | |
7888 pop(t1); | |
7889 } | |
7890 #endif | |
7891 } | |
0 | 7892 |
7893 class ControlWord { | |
7894 public: | |
7895 int32_t _value; | |
7896 | |
7897 int rounding_control() const { return (_value >> 10) & 3 ; } | |
7898 int precision_control() const { return (_value >> 8) & 3 ; } | |
7899 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
7900 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
7901 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
7902 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
7903 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
7904 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
7905 | |
7906 void print() const { | |
7907 // rounding control | |
7908 const char* rc; | |
7909 switch (rounding_control()) { | |
7910 case 0: rc = "round near"; break; | |
7911 case 1: rc = "round down"; break; | |
7912 case 2: rc = "round up "; break; | |
7913 case 3: rc = "chop "; break; | |
7914 }; | |
7915 // precision control | |
7916 const char* pc; | |
7917 switch (precision_control()) { | |
7918 case 0: pc = "24 bits "; break; | |
7919 case 1: pc = "reserved"; break; | |
7920 case 2: pc = "53 bits "; break; | |
7921 case 3: pc = "64 bits "; break; | |
7922 }; | |
7923 // flags | |
7924 char f[9]; | |
7925 f[0] = ' '; | |
7926 f[1] = ' '; | |
7927 f[2] = (precision ()) ? 'P' : 'p'; | |
7928 f[3] = (underflow ()) ? 'U' : 'u'; | |
7929 f[4] = (overflow ()) ? 'O' : 'o'; | |
7930 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
7931 f[6] = (denormalized()) ? 'D' : 'd'; | |
7932 f[7] = (invalid ()) ? 'I' : 'i'; | |
7933 f[8] = '\x0'; | |
7934 // output | |
7935 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
7936 } | |
7937 | |
7938 }; | |
7939 | |
7940 class StatusWord { | |
7941 public: | |
7942 int32_t _value; | |
7943 | |
7944 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
7945 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
7946 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
7947 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
7948 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
7949 int top() const { return (_value >> 11) & 7 ; } | |
7950 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
7951 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
7952 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
7953 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
7954 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
7955 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
7956 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
7957 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
7958 | |
7959 void print() const { | |
7960 // condition codes | |
7961 char c[5]; | |
7962 c[0] = (C3()) ? '3' : '-'; | |
7963 c[1] = (C2()) ? '2' : '-'; | |
7964 c[2] = (C1()) ? '1' : '-'; | |
7965 c[3] = (C0()) ? '0' : '-'; | |
7966 c[4] = '\x0'; | |
7967 // flags | |
7968 char f[9]; | |
7969 f[0] = (error_status()) ? 'E' : '-'; | |
7970 f[1] = (stack_fault ()) ? 'S' : '-'; | |
7971 f[2] = (precision ()) ? 'P' : '-'; | |
7972 f[3] = (underflow ()) ? 'U' : '-'; | |
7973 f[4] = (overflow ()) ? 'O' : '-'; | |
7974 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
7975 f[6] = (denormalized()) ? 'D' : '-'; | |
7976 f[7] = (invalid ()) ? 'I' : '-'; | |
7977 f[8] = '\x0'; | |
7978 // output | |
7979 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
7980 } | |
7981 | |
7982 }; | |
7983 | |
7984 class TagWord { | |
7985 public: | |
7986 int32_t _value; | |
7987 | |
7988 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
7989 | |
7990 void print() const { | |
7991 printf("%04x", _value & 0xFFFF); | |
7992 } | |
7993 | |
7994 }; | |
7995 | |
7996 class FPU_Register { | |
7997 public: | |
7998 int32_t _m0; | |
7999 int32_t _m1; | |
8000 int16_t _ex; | |
8001 | |
8002 bool is_indefinite() const { | |
8003 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
8004 } | |
8005 | |
8006 void print() const { | |
8007 char sign = (_ex < 0) ? '-' : '+'; | |
8008 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
8009 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
8010 }; | |
8011 | |
8012 }; | |
8013 | |
8014 class FPU_State { | |
8015 public: | |
8016 enum { | |
8017 register_size = 10, | |
8018 number_of_registers = 8, | |
8019 register_mask = 7 | |
8020 }; | |
8021 | |
8022 ControlWord _control_word; | |
8023 StatusWord _status_word; | |
8024 TagWord _tag_word; | |
8025 int32_t _error_offset; | |
8026 int32_t _error_selector; | |
8027 int32_t _data_offset; | |
8028 int32_t _data_selector; | |
8029 int8_t _register[register_size * number_of_registers]; | |
8030 | |
8031 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
8032 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
8033 | |
8034 const char* tag_as_string(int tag) const { | |
8035 switch (tag) { | |
8036 case 0: return "valid"; | |
8037 case 1: return "zero"; | |
8038 case 2: return "special"; | |
8039 case 3: return "empty"; | |
8040 } | |
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8041 ShouldNotReachHere(); |
0 | 8042 return NULL; |
8043 } | |
8044 | |
8045 void print() const { | |
8046 // print computation registers | |
8047 { int t = _status_word.top(); | |
8048 for (int i = 0; i < number_of_registers; i++) { | |
8049 int j = (i - t) & register_mask; | |
8050 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
8051 st(j)->print(); | |
8052 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
8053 } | |
8054 } | |
8055 printf("\n"); | |
8056 // print control registers | |
8057 printf("ctrl = "); _control_word.print(); printf("\n"); | |
8058 printf("stat = "); _status_word .print(); printf("\n"); | |
8059 printf("tags = "); _tag_word .print(); printf("\n"); | |
8060 } | |
8061 | |
8062 }; | |
8063 | |
8064 class Flag_Register { | |
8065 public: | |
8066 int32_t _value; | |
8067 | |
8068 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
8069 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
8070 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
8071 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
8072 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
8073 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
8074 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
8075 | |
8076 void print() const { | |
8077 // flags | |
8078 char f[8]; | |
8079 f[0] = (overflow ()) ? 'O' : '-'; | |
8080 f[1] = (direction ()) ? 'D' : '-'; | |
8081 f[2] = (sign ()) ? 'S' : '-'; | |
8082 f[3] = (zero ()) ? 'Z' : '-'; | |
8083 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
8084 f[5] = (parity ()) ? 'P' : '-'; | |
8085 f[6] = (carry ()) ? 'C' : '-'; | |
8086 f[7] = '\x0'; | |
8087 // output | |
8088 printf("%08x flags = %s", _value, f); | |
8089 } | |
8090 | |
8091 }; | |
8092 | |
8093 class IU_Register { | |
8094 public: | |
8095 int32_t _value; | |
8096 | |
8097 void print() const { | |
8098 printf("%08x %11d", _value, _value); | |
8099 } | |
8100 | |
8101 }; | |
8102 | |
8103 class IU_State { | |
8104 public: | |
8105 Flag_Register _eflags; | |
8106 IU_Register _rdi; | |
8107 IU_Register _rsi; | |
8108 IU_Register _rbp; | |
8109 IU_Register _rsp; | |
8110 IU_Register _rbx; | |
8111 IU_Register _rdx; | |
8112 IU_Register _rcx; | |
8113 IU_Register _rax; | |
8114 | |
8115 void print() const { | |
8116 // computation registers | |
8117 printf("rax, = "); _rax.print(); printf("\n"); | |
8118 printf("rbx, = "); _rbx.print(); printf("\n"); | |
8119 printf("rcx = "); _rcx.print(); printf("\n"); | |
8120 printf("rdx = "); _rdx.print(); printf("\n"); | |
8121 printf("rdi = "); _rdi.print(); printf("\n"); | |
8122 printf("rsi = "); _rsi.print(); printf("\n"); | |
8123 printf("rbp, = "); _rbp.print(); printf("\n"); | |
8124 printf("rsp = "); _rsp.print(); printf("\n"); | |
8125 printf("\n"); | |
8126 // control registers | |
8127 printf("flgs = "); _eflags.print(); printf("\n"); | |
8128 } | |
8129 }; | |
8130 | |
8131 | |
8132 class CPU_State { | |
8133 public: | |
8134 FPU_State _fpu_state; | |
8135 IU_State _iu_state; | |
8136 | |
8137 void print() const { | |
8138 printf("--------------------------------------------------\n"); | |
8139 _iu_state .print(); | |
8140 printf("\n"); | |
8141 _fpu_state.print(); | |
8142 printf("--------------------------------------------------\n"); | |
8143 } | |
8144 | |
8145 }; | |
8146 | |
8147 | |
8148 static void _print_CPU_state(CPU_State* state) { | |
8149 state->print(); | |
8150 }; | |
8151 | |
8152 | |
8153 void MacroAssembler::print_CPU_state() { | |
8154 push_CPU_state(); | |
304 | 8155 push(rsp); // pass CPU state |
0 | 8156 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
304 | 8157 addptr(rsp, wordSize); // discard argument |
0 | 8158 pop_CPU_state(); |
8159 } | |
8160 | |
8161 | |
8162 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
8163 static int counter = 0; | |
8164 FPU_State* fs = &state->_fpu_state; | |
8165 counter++; | |
8166 // For leaf calls, only verify that the top few elements remain empty. | |
8167 // We only need 1 empty at the top for C2 code. | |
8168 if( stack_depth < 0 ) { | |
8169 if( fs->tag_for_st(7) != 3 ) { | |
8170 printf("FPR7 not empty\n"); | |
8171 state->print(); | |
8172 assert(false, "error"); | |
8173 return false; | |
8174 } | |
8175 return true; // All other stack states do not matter | |
8176 } | |
8177 | |
8178 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
8179 "bad FPU control word"); | |
8180 | |
8181 // compute stack depth | |
8182 int i = 0; | |
8183 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
8184 int d = i; | |
8185 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
8186 // verify findings | |
8187 if (i != FPU_State::number_of_registers) { | |
8188 // stack not contiguous | |
8189 printf("%s: stack not contiguous at ST%d\n", s, i); | |
8190 state->print(); | |
8191 assert(false, "error"); | |
8192 return false; | |
8193 } | |
8194 // check if computed stack depth corresponds to expected stack depth | |
8195 if (stack_depth < 0) { | |
8196 // expected stack depth is -stack_depth or less | |
8197 if (d > -stack_depth) { | |
8198 // too many elements on the stack | |
8199 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
8200 state->print(); | |
8201 assert(false, "error"); | |
8202 return false; | |
8203 } | |
8204 } else { | |
8205 // expected stack depth is stack_depth | |
8206 if (d != stack_depth) { | |
8207 // wrong stack depth | |
8208 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
8209 state->print(); | |
8210 assert(false, "error"); | |
8211 return false; | |
8212 } | |
8213 } | |
8214 // everything is cool | |
8215 return true; | |
8216 } | |
8217 | |
8218 | |
8219 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
8220 if (!VerifyFPU) return; | |
8221 push_CPU_state(); | |
304 | 8222 push(rsp); // pass CPU state |
0 | 8223 ExternalAddress msg((address) s); |
8224 // pass message string s | |
8225 pushptr(msg.addr()); | |
304 | 8226 push(stack_depth); // pass stack depth |
0 | 8227 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
304 | 8228 addptr(rsp, 3 * wordSize); // discard arguments |
0 | 8229 // check for error |
8230 { Label L; | |
8231 testl(rax, rax); | |
8232 jcc(Assembler::notZero, L); | |
8233 int3(); // break if error condition | |
8234 bind(L); | |
8235 } | |
8236 pop_CPU_state(); | |
8237 } | |
8238 | |
304 | 8239 void MacroAssembler::load_klass(Register dst, Register src) { |
8240 #ifdef _LP64 | |
8241 if (UseCompressedOops) { | |
8242 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
8243 decode_heap_oop_not_null(dst); | |
8244 } else | |
8245 #endif | |
8246 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
8247 } | |
8248 | |
8249 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
8250 #ifdef _LP64 | |
8251 if (UseCompressedOops) { | |
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8252 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8253 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
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8254 if (Universe::narrow_oop_shift() != 0) { |
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8255 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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8256 if (LogMinObjAlignmentInBytes == Address::times_8) { |
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8257 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8258 } else { |
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8259 // OK to use shift since we don't need to preserve flags. |
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8260 shlq(dst, LogMinObjAlignmentInBytes); |
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8261 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8262 } |
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8263 } else { |
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8264 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8265 } |
304 | 8266 } else |
8267 #endif | |
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8268 { |
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8269 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
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8270 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8271 } |
304 | 8272 } |
8273 | |
8274 void MacroAssembler::store_klass(Register dst, Register src) { | |
8275 #ifdef _LP64 | |
8276 if (UseCompressedOops) { | |
8277 encode_heap_oop_not_null(src); | |
8278 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
8279 } else | |
8280 #endif | |
8281 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
8282 } | |
8283 | |
1846 | 8284 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
8285 #ifdef _LP64 | |
8286 if (UseCompressedOops) { | |
8287 movl(dst, src); | |
8288 decode_heap_oop(dst); | |
8289 } else | |
8290 #endif | |
8291 movptr(dst, src); | |
8292 } | |
8293 | |
8294 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
8295 #ifdef _LP64 | |
8296 if (UseCompressedOops) { | |
8297 assert(!dst.uses(src), "not enough registers"); | |
8298 encode_heap_oop(src); | |
8299 movl(dst, src); | |
8300 } else | |
8301 #endif | |
8302 movptr(dst, src); | |
8303 } | |
8304 | |
8305 // Used for storing NULLs. | |
8306 void MacroAssembler::store_heap_oop_null(Address dst) { | |
8307 #ifdef _LP64 | |
8308 if (UseCompressedOops) { | |
8309 movl(dst, (int32_t)NULL_WORD); | |
8310 } else { | |
8311 movslq(dst, (int32_t)NULL_WORD); | |
8312 } | |
8313 #else | |
8314 movl(dst, (int32_t)NULL_WORD); | |
8315 #endif | |
8316 } | |
8317 | |
304 | 8318 #ifdef _LP64 |
8319 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
8320 if (UseCompressedOops) { | |
8321 // Store to klass gap in destination | |
8322 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
8323 } | |
8324 } | |
8325 | |
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8326 #ifdef ASSERT |
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8327 void MacroAssembler::verify_heapbase(const char* msg) { |
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8328 assert (UseCompressedOops, "should be compressed"); |
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8329 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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8330 if (CheckCompressedOops) { |
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8331 Label ok; |
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8332 push(rscratch1); // cmpptr trashes rscratch1 |
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8333 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
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8334 jcc(Assembler::equal, ok); |
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8335 stop(msg); |
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8336 bind(ok); |
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8337 pop(rscratch1); |
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8338 } |
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8339 } |
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8340 #endif |
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8341 |
304 | 8342 // Algorithm must match oop.inline.hpp encode_heap_oop. |
8343 void MacroAssembler::encode_heap_oop(Register r) { | |
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8344 #ifdef ASSERT |
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changeset
|
8345 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8346 #endif |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8347 verify_oop(r, "broken oop in encode_heap_oop"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8348 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8349 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8350 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8351 shrq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8352 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8353 return; |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8354 } |
304 | 8355 testq(r, r); |
8356 cmovq(Assembler::equal, r, r12_heapbase); | |
8357 subq(r, r12_heapbase); | |
8358 shrq(r, LogMinObjAlignmentInBytes); | |
8359 } | |
8360 | |
8361 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
0 | 8362 #ifdef ASSERT |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8363 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
304 | 8364 if (CheckCompressedOops) { |
0 | 8365 Label ok; |
304 | 8366 testq(r, r); |
8367 jcc(Assembler::notEqual, ok); | |
8368 stop("null oop passed to encode_heap_oop_not_null"); | |
0 | 8369 bind(ok); |
304 | 8370 } |
8371 #endif | |
8372 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8373 if (Universe::narrow_oop_base() != NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8374 subq(r, r12_heapbase); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8375 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8376 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8377 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8378 shrq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
8379 } |
304 | 8380 } |
8381 | |
8382 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
8383 #ifdef ASSERT | |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8384 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
304 | 8385 if (CheckCompressedOops) { |
8386 Label ok; | |
8387 testq(src, src); | |
8388 jcc(Assembler::notEqual, ok); | |
8389 stop("null oop passed to encode_heap_oop_not_null2"); | |
8390 bind(ok); | |
0 | 8391 } |
8392 #endif | |
304 | 8393 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
8394 if (dst != src) { | |
8395 movq(dst, src); | |
8396 } | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8397 if (Universe::narrow_oop_base() != NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8398 subq(dst, r12_heapbase); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8399 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8400 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8401 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8402 shrq(dst, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8403 } |
304 | 8404 } |
8405 | |
8406 void MacroAssembler::decode_heap_oop(Register r) { | |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8407 #ifdef ASSERT |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8408 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8409 #endif |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8410 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8411 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8412 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8413 shlq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8414 } |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8415 } else { |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8416 Label done; |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8417 shlq(r, LogMinObjAlignmentInBytes); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8418 jccb(Assembler::equal, done); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8419 addq(r, r12_heapbase); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8420 bind(done); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8421 } |
304 | 8422 verify_oop(r, "broken oop in decode_heap_oop"); |
8423 } | |
8424 | |
8425 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8426 // Note: it will change flags |
304 | 8427 assert (UseCompressedOops, "should only be used for compressed headers"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8428 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8429 // Cannot assert, unverified entry point counts instructions (see .ad file) |
8430 // vtableStubs also counts instructions in pd_code_size_limit. | |
8431 // Also do not verify_oop as this is called by verify_oop. | |
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8432 if (Universe::narrow_oop_shift() != 0) { |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8433 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8434 shlq(r, LogMinObjAlignmentInBytes); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8435 if (Universe::narrow_oop_base() != NULL) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8436 addq(r, r12_heapbase); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8437 } |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8438 } else { |
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8439 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8440 } |
304 | 8441 } |
8442 | |
8443 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8444 // Note: it will change flags |
304 | 8445 assert (UseCompressedOops, "should only be used for compressed headers"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8446 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8447 // Cannot assert, unverified entry point counts instructions (see .ad file) |
8448 // vtableStubs also counts instructions in pd_code_size_limit. | |
8449 // Also do not verify_oop as this is called by verify_oop. | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8450 if (Universe::narrow_oop_shift() != 0) { |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8451 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8452 if (LogMinObjAlignmentInBytes == Address::times_8) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8453 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8454 } else { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8455 if (dst != src) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8456 movq(dst, src); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8457 } |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8458 shlq(dst, LogMinObjAlignmentInBytes); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8459 if (Universe::narrow_oop_base() != NULL) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8460 addq(dst, r12_heapbase); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8461 } |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8462 } |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8463 } else { |
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8464 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8465 if (dst != src) { |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8466 movq(dst, src); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8467 } |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8468 } |
304 | 8469 } |
8470 | |
8471 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8472 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8473 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8474 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8475 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8476 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8477 mov_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8478 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8479 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8480 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8481 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8482 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8483 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
304 | 8484 int oop_index = oop_recorder()->find_index(obj); |
8485 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8486 mov_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8487 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8488 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8489 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8490 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8491 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8492 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8493 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8494 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8495 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8496 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8497 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8498 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8499 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8500 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8501 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8502 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8503 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8504 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
304 | 8505 } |
8506 | |
8507 void MacroAssembler::reinit_heapbase() { | |
8508 if (UseCompressedOops) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
8509 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
304 | 8510 } |
8511 } | |
8512 #endif // _LP64 | |
0 | 8513 |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8514 // IndexOf substring. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8515 void MacroAssembler::string_indexof(Register str1, Register str2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8516 Register cnt1, Register cnt2, Register result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8517 XMMRegister vec, Register tmp) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8518 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8519 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8520 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8521 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8522 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8523 push(str1); // string addr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8524 push(str2); // substr addr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8525 push(cnt2); // substr count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8526 jmpb(PREP_FOR_SCAN); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8527 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8528 // Substr count saved at sp |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8529 // Substr saved at sp+1*wordSize |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8530 // String saved at sp+2*wordSize |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8531 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8532 // Reload substr for rescan |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8533 bind(RELOAD_SUBSTR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8534 movl(cnt2, Address(rsp, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8535 movptr(str2, Address(rsp, wordSize)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8536 // We came here after the beginninig of the substring was |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8537 // matched but the rest of it was not so we need to search |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8538 // again. Start from the next element after the previous match. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8539 subptr(str1, result); // Restore counter |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8540 shrl(str1, 1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8541 addl(cnt1, str1); |
1302
2484f4d6a54e
6935535: String.indexOf() returns incorrect result on x86 with SSE4.2
kvn
parents:
1108
diff
changeset
|
8542 decrementl(cnt1); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8543 lea(str1, Address(result, 2)); // Reload string |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8544 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8545 // Load substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8546 bind(PREP_FOR_SCAN); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8547 movdqu(vec, Address(str2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8548 addl(cnt1, 8); // prime the loop |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8549 subptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8550 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8551 // Scan string for substr in 16-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8552 bind(SCAN_TO_SUBSTR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8553 subl(cnt1, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8554 addptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8555 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8556 // pcmpestri |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8557 // inputs: |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8558 // xmm - substring |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8559 // rax - substring length (elements count) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8560 // mem - scaned string |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8561 // rdx - string length (elements count) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8562 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8563 // outputs: |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8564 // rcx - matched index in string |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8565 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8566 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8567 pcmpestri(vec, Address(str1, 0), 0x0d); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8568 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8569 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8570 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8571 // Fallthrough: found a potential substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8572 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8573 // Make sure string is still long enough |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8574 subl(cnt1, tmp); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8575 cmpl(cnt1, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8576 jccb(Assembler::negative, RET_NOT_FOUND); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8577 // Compute start addr of substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8578 lea(str1, Address(str1, tmp, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8579 movptr(result, str1); // save |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8580 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8581 // Compare potential substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8582 addl(cnt1, 8); // prime the loop |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8583 addl(cnt2, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8584 subptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8585 subptr(str2, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8586 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8587 // Scan 16-byte vectors of string and substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8588 bind(SCAN_SUBSTR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8589 subl(cnt1, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8590 subl(cnt2, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8591 addptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8592 addptr(str2, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8593 movdqu(vec, Address(str2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8594 pcmpestri(vec, Address(str1, 0), 0x0d); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8595 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8596 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8597 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8598 // Compute substr offset |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8599 subptr(result, Address(rsp, 2*wordSize)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8600 shrl(result, 1); // index |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8601 jmpb(CLEANUP); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8602 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8603 bind(RET_NOT_FOUND); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8604 movl(result, -1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8605 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8606 bind(CLEANUP); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8607 addptr(rsp, 3*wordSize); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8608 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8609 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8610 // Compare strings. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8611 void MacroAssembler::string_compare(Register str1, Register str2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8612 Register cnt1, Register cnt2, Register result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8613 XMMRegister vec1, XMMRegister vec2) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8614 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8615 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8616 // Compute the minimum of the string lengths and the |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8617 // difference of the string lengths (stack). |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8618 // Do the conditional move stuff |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8619 movl(result, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8620 subl(cnt1, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8621 push(cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8622 if (VM_Version::supports_cmov()) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8623 cmovl(Assembler::lessEqual, cnt2, result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8624 } else { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8625 Label GT_LABEL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8626 jccb(Assembler::greater, GT_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8627 movl(cnt2, result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8628 bind(GT_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8629 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8630 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8631 // Is the minimum length zero? |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8632 testl(cnt2, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8633 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8634 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8635 // Load first characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8636 load_unsigned_short(result, Address(str1, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8637 load_unsigned_short(cnt1, Address(str2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8638 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8639 // Compare first characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8640 subl(result, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8641 jcc(Assembler::notZero, POP_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8642 decrementl(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8643 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8644 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8645 { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8646 // Check after comparing first character to see if strings are equivalent |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8647 Label LSkip2; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8648 // Check if the strings start at same location |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8649 cmpptr(str1, str2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8650 jccb(Assembler::notEqual, LSkip2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8651 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8652 // Check if the length difference is zero (from stack) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8653 cmpl(Address(rsp, 0), 0x0); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8654 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8655 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8656 // Strings might not be equivalent |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8657 bind(LSkip2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8658 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8659 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8660 // Advance to next character |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8661 addptr(str1, 2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8662 addptr(str2, 2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8663 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8664 if (UseSSE42Intrinsics) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8665 // With SSE4.2, use double quad vector compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8666 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8667 // Setup to compare 16-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8668 movl(cnt1, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8669 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8670 andl(cnt1, 0x00000007); // cnt1 holds the tail count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8671 testl(cnt2, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8672 jccb(Assembler::zero, COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8673 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8674 lea(str2, Address(str2, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8675 lea(str1, Address(str1, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8676 negptr(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8677 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8678 bind(COMPARE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8679 movdqu(vec1, Address(str1, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8680 movdqu(vec2, Address(str2, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8681 pxor(vec1, vec2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8682 ptest(vec1, vec1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8683 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8684 addptr(cnt2, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8685 jcc(Assembler::notZero, COMPARE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8686 jmpb(COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8687 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8688 // Mismatched characters in the vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8689 bind(VECTOR_NOT_EQUAL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8690 lea(str1, Address(str1, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8691 lea(str2, Address(str2, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8692 movl(cnt1, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8693 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8694 // Compare tail (< 8 chars), or rescan last vectors to |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8695 // find 1st mismatched characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8696 bind(COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8697 testl(cnt1, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8698 jccb(Assembler::zero, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8699 movl(cnt2, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8700 // Fallthru to tail compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8701 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8702 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8703 // Shift str2 and str1 to the end of the arrays, negate min |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8704 lea(str1, Address(str1, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8705 lea(str2, Address(str2, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8706 negptr(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8707 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8708 // Compare the rest of the characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8709 bind(WHILE_HEAD_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8710 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8711 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8712 subl(result, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8713 jccb(Assembler::notZero, POP_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8714 increment(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8715 jcc(Assembler::notZero, WHILE_HEAD_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8716 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8717 // Strings are equal up to min length. Return the length difference. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8718 bind(LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8719 pop(result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8720 jmpb(DONE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8721 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8722 // Discard the stored length difference |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8723 bind(POP_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8724 addptr(rsp, wordSize); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8725 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8726 // That's it |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8727 bind(DONE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8728 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8729 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8730 // Compare char[] arrays aligned to 4 bytes or substrings. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8731 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8732 Register limit, Register result, Register chr, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8733 XMMRegister vec1, XMMRegister vec2) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8734 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8735 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8736 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8737 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8738 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8739 // Check the input args |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8740 cmpptr(ary1, ary2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8741 jcc(Assembler::equal, TRUE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8742 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8743 if (is_array_equ) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8744 // Need additional checks for arrays_equals. |
1016 | 8745 testptr(ary1, ary1); |
8746 jcc(Assembler::zero, FALSE_LABEL); | |
8747 testptr(ary2, ary2); | |
8748 jcc(Assembler::zero, FALSE_LABEL); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8749 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8750 // Check the lengths |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8751 movl(limit, Address(ary1, length_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8752 cmpl(limit, Address(ary2, length_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8753 jcc(Assembler::notEqual, FALSE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8754 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8755 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8756 // count == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8757 testl(limit, limit); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8758 jcc(Assembler::zero, TRUE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8759 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8760 if (is_array_equ) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8761 // Load array address |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8762 lea(ary1, Address(ary1, base_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8763 lea(ary2, Address(ary2, base_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8764 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8765 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8766 shll(limit, 1); // byte count != 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8767 movl(result, limit); // copy |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8768 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8769 if (UseSSE42Intrinsics) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8770 // With SSE4.2, use double quad vector compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8771 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8772 // Compare 16-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8773 andl(result, 0x0000000e); // tail count (in bytes) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8774 andl(limit, 0xfffffff0); // vector count (in bytes) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8775 jccb(Assembler::zero, COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8776 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8777 lea(ary1, Address(ary1, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8778 lea(ary2, Address(ary2, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8779 negptr(limit); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8780 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8781 bind(COMPARE_WIDE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8782 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8783 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8784 pxor(vec1, vec2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8785 ptest(vec1, vec1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8786 jccb(Assembler::notZero, FALSE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8787 addptr(limit, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8788 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8789 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8790 bind(COMPARE_TAIL); // limit is zero |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8791 movl(limit, result); |
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8792 // Fallthru to tail compare |
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8793 } |
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8794 |
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8795 // Compare 4-byte vectors |
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8796 andl(limit, 0xfffffffc); // vector count (in bytes) |
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8797 jccb(Assembler::zero, COMPARE_CHAR); |
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8798 |
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8799 lea(ary1, Address(ary1, limit, Address::times_1)); |
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8800 lea(ary2, Address(ary2, limit, Address::times_1)); |
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8801 negptr(limit); |
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8802 |
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8803 bind(COMPARE_VECTORS); |
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8804 movl(chr, Address(ary1, limit, Address::times_1)); |
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8805 cmpl(chr, Address(ary2, limit, Address::times_1)); |
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8806 jccb(Assembler::notEqual, FALSE_LABEL); |
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8807 addptr(limit, 4); |
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8808 jcc(Assembler::notZero, COMPARE_VECTORS); |
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8809 |
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8810 // Compare trailing char (final 2 bytes), if any |
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8811 bind(COMPARE_CHAR); |
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8812 testl(result, 0x2); // tail char |
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8813 jccb(Assembler::zero, TRUE_LABEL); |
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8814 load_unsigned_short(chr, Address(ary1, 0)); |
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8815 load_unsigned_short(limit, Address(ary2, 0)); |
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8816 cmpl(chr, limit); |
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8817 jccb(Assembler::notEqual, FALSE_LABEL); |
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8818 |
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8819 bind(TRUE_LABEL); |
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8820 movl(result, 1); // return true |
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8821 jmpb(DONE); |
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8822 |
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8823 bind(FALSE_LABEL); |
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8824 xorl(result, result); // return false |
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8825 |
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8826 // That's it |
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8827 bind(DONE); |
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8828 } |
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8829 |
1763 | 8830 #ifdef PRODUCT |
8831 #define BLOCK_COMMENT(str) /* nothing */ | |
8832 #else | |
8833 #define BLOCK_COMMENT(str) block_comment(str) | |
8834 #endif | |
8835 | |
8836 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
8837 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
8838 Register to, Register value, Register count, | |
8839 Register rtmp, XMMRegister xtmp) { | |
8840 assert_different_registers(to, value, count, rtmp); | |
8841 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
8842 Label L_fill_2_bytes, L_fill_4_bytes; | |
8843 | |
8844 int shift = -1; | |
8845 switch (t) { | |
8846 case T_BYTE: | |
8847 shift = 2; | |
8848 break; | |
8849 case T_SHORT: | |
8850 shift = 1; | |
8851 break; | |
8852 case T_INT: | |
8853 shift = 0; | |
8854 break; | |
8855 default: ShouldNotReachHere(); | |
8856 } | |
8857 | |
8858 if (t == T_BYTE) { | |
8859 andl(value, 0xff); | |
8860 movl(rtmp, value); | |
8861 shll(rtmp, 8); | |
8862 orl(value, rtmp); | |
8863 } | |
8864 if (t == T_SHORT) { | |
8865 andl(value, 0xffff); | |
8866 } | |
8867 if (t == T_BYTE || t == T_SHORT) { | |
8868 movl(rtmp, value); | |
8869 shll(rtmp, 16); | |
8870 orl(value, rtmp); | |
8871 } | |
8872 | |
8873 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
8874 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
8875 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
8876 // align source address at 4 bytes address boundary | |
8877 if (t == T_BYTE) { | |
8878 // One byte misalignment happens only for byte arrays | |
8879 testptr(to, 1); | |
8880 jccb(Assembler::zero, L_skip_align1); | |
8881 movb(Address(to, 0), value); | |
8882 increment(to); | |
8883 decrement(count); | |
8884 BIND(L_skip_align1); | |
8885 } | |
8886 // Two bytes misalignment happens only for byte and short (char) arrays | |
8887 testptr(to, 2); | |
8888 jccb(Assembler::zero, L_skip_align2); | |
8889 movw(Address(to, 0), value); | |
8890 addptr(to, 2); | |
8891 subl(count, 1<<(shift-1)); | |
8892 BIND(L_skip_align2); | |
8893 } | |
8894 if (UseSSE < 2) { | |
8895 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
8896 // Fill 32-byte chunks | |
8897 subl(count, 8 << shift); | |
8898 jcc(Assembler::less, L_check_fill_8_bytes); | |
8899 align(16); | |
8900 | |
8901 BIND(L_fill_32_bytes_loop); | |
8902 | |
8903 for (int i = 0; i < 32; i += 4) { | |
8904 movl(Address(to, i), value); | |
8905 } | |
8906 | |
8907 addptr(to, 32); | |
8908 subl(count, 8 << shift); | |
8909 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
8910 BIND(L_check_fill_8_bytes); | |
8911 addl(count, 8 << shift); | |
8912 jccb(Assembler::zero, L_exit); | |
8913 jmpb(L_fill_8_bytes); | |
8914 | |
8915 // | |
8916 // length is too short, just fill qwords | |
8917 // | |
8918 BIND(L_fill_8_bytes_loop); | |
8919 movl(Address(to, 0), value); | |
8920 movl(Address(to, 4), value); | |
8921 addptr(to, 8); | |
8922 BIND(L_fill_8_bytes); | |
8923 subl(count, 1 << (shift + 1)); | |
8924 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
8925 // fall through to fill 4 bytes | |
8926 } else { | |
8927 Label L_fill_32_bytes; | |
8928 if (!UseUnalignedLoadStores) { | |
8929 // align to 8 bytes, we know we are 4 byte aligned to start | |
8930 testptr(to, 4); | |
8931 jccb(Assembler::zero, L_fill_32_bytes); | |
8932 movl(Address(to, 0), value); | |
8933 addptr(to, 4); | |
8934 subl(count, 1<<shift); | |
8935 } | |
8936 BIND(L_fill_32_bytes); | |
8937 { | |
8938 assert( UseSSE >= 2, "supported cpu only" ); | |
8939 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
8940 // Fill 32-byte chunks | |
8941 movdl(xtmp, value); | |
8942 pshufd(xtmp, xtmp, 0); | |
8943 | |
8944 subl(count, 8 << shift); | |
8945 jcc(Assembler::less, L_check_fill_8_bytes); | |
8946 align(16); | |
8947 | |
8948 BIND(L_fill_32_bytes_loop); | |
8949 | |
8950 if (UseUnalignedLoadStores) { | |
8951 movdqu(Address(to, 0), xtmp); | |
8952 movdqu(Address(to, 16), xtmp); | |
8953 } else { | |
8954 movq(Address(to, 0), xtmp); | |
8955 movq(Address(to, 8), xtmp); | |
8956 movq(Address(to, 16), xtmp); | |
8957 movq(Address(to, 24), xtmp); | |
8958 } | |
8959 | |
8960 addptr(to, 32); | |
8961 subl(count, 8 << shift); | |
8962 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
8963 BIND(L_check_fill_8_bytes); | |
8964 addl(count, 8 << shift); | |
8965 jccb(Assembler::zero, L_exit); | |
8966 jmpb(L_fill_8_bytes); | |
8967 | |
8968 // | |
8969 // length is too short, just fill qwords | |
8970 // | |
8971 BIND(L_fill_8_bytes_loop); | |
8972 movq(Address(to, 0), xtmp); | |
8973 addptr(to, 8); | |
8974 BIND(L_fill_8_bytes); | |
8975 subl(count, 1 << (shift + 1)); | |
8976 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
8977 } | |
8978 } | |
8979 // fill trailing 4 bytes | |
8980 BIND(L_fill_4_bytes); | |
8981 testl(count, 1<<shift); | |
8982 jccb(Assembler::zero, L_fill_2_bytes); | |
8983 movl(Address(to, 0), value); | |
8984 if (t == T_BYTE || t == T_SHORT) { | |
8985 addptr(to, 4); | |
8986 BIND(L_fill_2_bytes); | |
8987 // fill trailing 2 bytes | |
8988 testl(count, 1<<(shift-1)); | |
8989 jccb(Assembler::zero, L_fill_byte); | |
8990 movw(Address(to, 0), value); | |
8991 if (t == T_BYTE) { | |
8992 addptr(to, 2); | |
8993 BIND(L_fill_byte); | |
8994 // fill trailing byte | |
8995 testl(count, 1); | |
8996 jccb(Assembler::zero, L_exit); | |
8997 movb(Address(to, 0), value); | |
8998 } else { | |
8999 BIND(L_fill_byte); | |
9000 } | |
9001 } else { | |
9002 BIND(L_fill_2_bytes); | |
9003 } | |
9004 BIND(L_exit); | |
9005 } | |
9006 #undef BIND | |
9007 #undef BLOCK_COMMENT | |
9008 | |
9009 | |
0 | 9010 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
9011 switch (cond) { | |
9012 // Note some conditions are synonyms for others | |
9013 case Assembler::zero: return Assembler::notZero; | |
9014 case Assembler::notZero: return Assembler::zero; | |
9015 case Assembler::less: return Assembler::greaterEqual; | |
9016 case Assembler::lessEqual: return Assembler::greater; | |
9017 case Assembler::greater: return Assembler::lessEqual; | |
9018 case Assembler::greaterEqual: return Assembler::less; | |
9019 case Assembler::below: return Assembler::aboveEqual; | |
9020 case Assembler::belowEqual: return Assembler::above; | |
9021 case Assembler::above: return Assembler::belowEqual; | |
9022 case Assembler::aboveEqual: return Assembler::below; | |
9023 case Assembler::overflow: return Assembler::noOverflow; | |
9024 case Assembler::noOverflow: return Assembler::overflow; | |
9025 case Assembler::negative: return Assembler::positive; | |
9026 case Assembler::positive: return Assembler::negative; | |
9027 case Assembler::parity: return Assembler::noParity; | |
9028 case Assembler::noParity: return Assembler::parity; | |
9029 } | |
9030 ShouldNotReachHere(); return Assembler::overflow; | |
9031 } | |
9032 | |
9033 SkipIfEqual::SkipIfEqual( | |
9034 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
9035 _masm = masm; | |
9036 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
9037 _masm->jcc(Assembler::equal, _label); | |
9038 } | |
9039 | |
9040 SkipIfEqual::~SkipIfEqual() { | |
9041 _masm->bind(_label); | |
9042 } |