Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 1122:dcb15a6f342d
Merge
author | dcubed |
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date | Mon, 14 Dec 2009 13:26:29 -0700 |
parents | f875b4f472f7 |
children | 97125851f396 |
rev | line source |
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0 | 1 // |
624 | 2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
21 // have any questions. | |
22 // | |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
429 %} | |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
463 // Macros to extract hi & lo halves from a long pair. | |
464 // G0 is not part of any long pair, so assert on that. | |
605 | 465 // Prevents accidentally using G1 instead of G0. |
0 | 466 #define LONG_HI_REG(x) (x) |
467 #define LONG_LO_REG(x) (x) | |
468 | |
469 %} | |
470 | |
471 source %{ | |
472 #define __ _masm. | |
473 | |
474 // tertiary op of a LoadP or StoreP encoding | |
475 #define REGP_OP true | |
476 | |
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
479 static Register reg_to_register_object(int register_encoding); | |
480 | |
481 // Used by the DFA in dfa_sparc.cpp. | |
482 // Check for being able to use a V9 branch-on-register. Requires a | |
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
484 // extended. Doesn't work following an integer ADD, for example, because of | |
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
487 // replace them with zero, which could become sign-extension in a different OS | |
488 // release. There's no obvious reason why an interrupt will ever fill these | |
489 // bits with non-zero junk (the registers are reloaded with standard LD | |
490 // instructions which either zero-fill or sign-fill). | |
491 bool can_branch_register( Node *bol, Node *cmp ) { | |
492 if( !BranchOnRegister ) return false; | |
493 #ifdef _LP64 | |
494 if( cmp->Opcode() == Op_CmpP ) | |
495 return true; // No problems with pointer compares | |
496 #endif | |
497 if( cmp->Opcode() == Op_CmpL ) | |
498 return true; // No problems with long compares | |
499 | |
500 if( !SparcV9RegsHiBitsZero ) return false; | |
501 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
502 bol->as_Bool()->_test._test != BoolTest::eq ) | |
503 return false; | |
504 | |
505 // Check for comparing against a 'safe' value. Any operation which | |
506 // clears out the high word is safe. Thus, loads and certain shifts | |
507 // are safe, as are non-negative constants. Any operation which | |
508 // preserves zero bits in the high word is safe as long as each of its | |
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
510 // inputs are safe. At present, the only important case to recognize | |
511 // seems to be loads. Constants should fold away, and shifts & | |
512 // logicals can use the 'cc' forms. | |
513 Node *x = cmp->in(1); | |
514 if( x->is_Load() ) return true; | |
515 if( x->is_Phi() ) { | |
516 for( uint i = 1; i < x->req(); i++ ) | |
517 if( !x->in(i)->is_Load() ) | |
518 return false; | |
519 return true; | |
520 } | |
521 return false; | |
522 } | |
523 | |
524 // **************************************************************************** | |
525 | |
526 // REQUIRED FUNCTIONALITY | |
527 | |
528 // !!!!! Special hack to get all type of calls to specify the byte offset | |
529 // from the start of the call to the point where the return address | |
530 // will point. | |
531 // The "return address" is the address of the call instruction, plus 8. | |
532 | |
533 int MachCallStaticJavaNode::ret_addr_offset() { | |
534 return NativeCall::instruction_size; // call; delay slot | |
535 } | |
536 | |
537 int MachCallDynamicJavaNode::ret_addr_offset() { | |
538 int vtable_index = this->_vtable_index; | |
539 if (vtable_index < 0) { | |
540 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
542 return (NativeMovConstReg::instruction_size + | |
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
544 } else { | |
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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548 int klass_load_size; |
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549 if (UseCompressedOops) { |
642
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550 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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551 if (Universe::narrow_oop_base() == NULL) |
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552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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553 else |
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554 klass_load_size = 3*BytesPerInstWord; |
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555 } else { |
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556 klass_load_size = 1*BytesPerInstWord; |
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557 } |
0 | 558 if( Assembler::is_simm13(v_off) ) { |
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559 return klass_load_size + |
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560 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 561 NativeCall::instruction_size); // call; delay slot |
562 } else { | |
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563 return klass_load_size + |
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564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 565 NativeCall::instruction_size); // call; delay slot |
566 } | |
567 } | |
568 } | |
569 | |
570 int MachCallRuntimeNode::ret_addr_offset() { | |
571 #ifdef _LP64 | |
572 return NativeFarCall::instruction_size; // farcall; delay slot | |
573 #else | |
574 return NativeCall::instruction_size; // call; delay slot | |
575 #endif | |
576 } | |
577 | |
578 // Indicate if the safepoint node needs the polling page as an input. | |
579 // Since Sparc does not have absolute addressing, it does. | |
580 bool SafePointNode::needs_polling_address_input() { | |
581 return true; | |
582 } | |
583 | |
584 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
585 void emit_break(CodeBuffer &cbuf) { | |
586 MacroAssembler _masm(&cbuf); | |
587 __ breakpoint_trap(); | |
588 } | |
589 | |
590 #ifndef PRODUCT | |
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
592 st->print("TA"); | |
593 } | |
594 #endif | |
595 | |
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
597 emit_break(cbuf); | |
598 } | |
599 | |
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
601 return MachNode::size(ra_); | |
602 } | |
603 | |
604 // Traceable jump | |
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
606 MacroAssembler _masm(&cbuf); | |
607 Register rdest = reg_to_register_object(jump_target); | |
608 __ JMP(rdest, 0); | |
609 __ delayed()->nop(); | |
610 } | |
611 | |
612 // Traceable jump and set exception pc | |
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
614 MacroAssembler _masm(&cbuf); | |
615 Register rdest = reg_to_register_object(jump_target); | |
616 __ JMP(rdest, 0); | |
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
618 } | |
619 | |
620 void emit_nop(CodeBuffer &cbuf) { | |
621 MacroAssembler _masm(&cbuf); | |
622 __ nop(); | |
623 } | |
624 | |
625 void emit_illtrap(CodeBuffer &cbuf) { | |
626 MacroAssembler _masm(&cbuf); | |
627 __ illtrap(0); | |
628 } | |
629 | |
630 | |
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
632 assert(n->rule() != loadUB_rule, ""); | |
633 | |
634 intptr_t offset = 0; | |
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
636 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
639 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
640 atype = atype->add_offset(offset); | |
641 assert(disp32 == offset, "wrong disp32"); | |
642 return atype->_offset; | |
643 } | |
644 | |
645 | |
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
647 assert(n->rule() != loadUB_rule, ""); | |
648 | |
649 intptr_t offset = 0; | |
650 Node* addr = n->in(2); | |
651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
653 Node* a = addr->in(2/*AddPNode::Address*/); | |
654 Node* o = addr->in(3/*AddPNode::Offset*/); | |
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
656 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
657 assert(atype->isa_oop_ptr(), "still an oop"); | |
658 } | |
659 offset = atype->is_ptr()->_offset; | |
660 if (offset != Type::OffsetBot) offset += disp32; | |
661 return offset; | |
662 } | |
663 | |
664 // Standard Sparc opcode form2 field breakdown | |
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
667 int op = (f30 << 30) | | |
668 (f29 << 29) | | |
669 (f25 << 25) | | |
670 (f22 << 22) | | |
671 (f20 << 20) | | |
672 (f19 << 19) | | |
673 (f0 << 0); | |
674 *((int*)(cbuf.code_end())) = op; | |
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
676 } | |
677 | |
678 // Standard Sparc opcode form2 field breakdown | |
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
680 f0 >>= 10; // Drop 10 bits | |
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
682 int op = (f30 << 30) | | |
683 (f25 << 25) | | |
684 (f22 << 22) | | |
685 (f0 << 0); | |
686 *((int*)(cbuf.code_end())) = op; | |
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
688 } | |
689 | |
690 // Standard Sparc opcode form3 field breakdown | |
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
692 int op = (f30 << 30) | | |
693 (f25 << 25) | | |
694 (f19 << 19) | | |
695 (f14 << 14) | | |
696 (f5 << 5) | | |
697 (f0 << 0); | |
698 *((int*)(cbuf.code_end())) = op; | |
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
700 } | |
701 | |
702 // Standard Sparc opcode form3 field breakdown | |
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
704 simm13 &= (1<<13)-1; // Mask to 13 bits | |
705 int op = (f30 << 30) | | |
706 (f25 << 25) | | |
707 (f19 << 19) | | |
708 (f14 << 14) | | |
709 (1 << 13) | // bit to indicate immediate-mode | |
710 (simm13<<0); | |
711 *((int*)(cbuf.code_end())) = op; | |
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
713 } | |
714 | |
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
716 simm10 &= (1<<10)-1; // Mask to 10 bits | |
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
718 } | |
719 | |
720 #ifdef ASSERT | |
721 // Helper function for VerifyOops in emit_form3_mem_reg | |
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
723 warning("VerifyOops encountered unexpected instruction:"); | |
724 n->dump(2); | |
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
726 } | |
727 #endif | |
728 | |
729 | |
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
731 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
732 | |
733 #ifdef ASSERT | |
734 // The following code implements the +VerifyOops feature. | |
735 // It verifies oop values which are loaded into or stored out of | |
736 // the current method activation. +VerifyOops complements techniques | |
737 // like ScavengeALot, because it eagerly inspects oops in transit, | |
738 // as they enter or leave the stack, as opposed to ScavengeALot, | |
739 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
740 // For this reason, +VerifyOops can sometimes detect bugs very close | |
741 // to their point of creation. It can also serve as a cross-check | |
742 // on the validity of oop maps, when used toegether with ScavengeALot. | |
743 | |
744 // It would be good to verify oops at other points, especially | |
745 // when an oop is used as a base pointer for a load or store. | |
746 // This is presently difficult, because it is hard to know when | |
747 // a base address is biased or not. (If we had such information, | |
748 // it would be easy and useful to make a two-argument version of | |
749 // verify_oop which unbiases the base, and performs verification.) | |
750 | |
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
752 bool is_verified_oop_base = false; | |
753 bool is_verified_oop_load = false; | |
754 bool is_verified_oop_store = false; | |
755 int tmp_enc = -1; | |
756 if (VerifyOops && src1_enc != R_SP_enc) { | |
757 // classify the op, mainly for an assert check | |
758 int st_op = 0, ld_op = 0; | |
759 switch (primary) { | |
760 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
761 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
763 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
764 case Assembler::std_op3: st_op = Op_StoreL; break; | |
765 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
766 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
767 | |
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
558
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6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
779 | |
780 default: ShouldNotReachHere(); | |
781 } | |
782 if (tertiary == REGP_OP) { | |
783 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
785 else ShouldNotReachHere(); | |
786 if (st_op) { | |
787 // a store | |
788 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
789 Node* n2 = n->in(3); | |
790 if (n2 != NULL) { | |
791 const Type* t = n2->bottom_type(); | |
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
793 } | |
794 } else { | |
795 // a load | |
796 const Type* t = n->bottom_type(); | |
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
798 } | |
799 } | |
800 | |
801 if (ld_op) { | |
802 // a Load | |
803 // inputs are (0:control, 1:memory, 2:address) | |
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
818 !(n->rule() == loadUB_rule)) { | |
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
820 } | |
821 } else if (st_op) { | |
822 // a Store | |
823 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { | |
830 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
831 } | |
832 } | |
833 | |
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
835 Node* addr = n->in(2); | |
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
838 if (atype != NULL) { | |
839 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
841 if (offset != offset_2) { | |
842 get_offset_from_base(n, atype, disp32); | |
843 get_offset_from_base_2(n, atype, disp32); | |
844 } | |
845 assert(offset == offset_2, "different offsets"); | |
846 if (offset == disp32) { | |
847 // we now know that src1 is a true oop pointer | |
848 is_verified_oop_base = true; | |
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
850 if( primary == Assembler::ldd_op3 ) { | |
851 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
852 } else { | |
853 tmp_enc = dst_enc; | |
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
855 assert(src1_enc != dst_enc, ""); | |
856 } | |
857 } | |
858 } | |
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
860 || offset == oopDesc::mark_offset_in_bytes())) { | |
861 // loading the mark should not be allowed either, but | |
862 // we don't check this since it conflicts with InlineObjectHash | |
863 // usage of LoadINode to get the mark. We could keep the | |
864 // check if we create a new LoadMarkNode | |
865 // but do not verify the object before its header is initialized | |
866 ShouldNotReachHere(); | |
867 } | |
868 } | |
869 } | |
870 } | |
871 } | |
872 #endif | |
873 | |
874 uint instr; | |
875 instr = (Assembler::ldst_op << 30) | |
876 | (dst_enc << 25) | |
877 | (primary << 19) | |
878 | (src1_enc << 14); | |
879 | |
880 uint index = src2_enc; | |
881 int disp = disp32; | |
882 | |
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
884 disp += STACK_BIAS; | |
885 | |
886 // We should have a compiler bailout here rather than a guarantee. | |
887 // Better yet would be some mechanism to handle variable-size matches correctly. | |
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
889 | |
890 if( disp == 0 ) { | |
891 // use reg-reg form | |
892 // bit 13 is already zero | |
893 instr |= index; | |
894 } else { | |
895 // use reg-imm form | |
896 instr |= 0x00002000; // set bit 13 to one | |
897 instr |= disp & 0x1FFF; | |
898 } | |
899 | |
900 uint *code = (uint*)cbuf.code_end(); | |
901 *code = instr; | |
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
903 | |
904 #ifdef ASSERT | |
905 { | |
906 MacroAssembler _masm(&cbuf); | |
907 if (is_verified_oop_base) { | |
908 __ verify_oop(reg_to_register_object(src1_enc)); | |
909 } | |
910 if (is_verified_oop_store) { | |
911 __ verify_oop(reg_to_register_object(dst_enc)); | |
912 } | |
913 if (tmp_enc != -1) { | |
914 __ mov(O7, reg_to_register_object(tmp_enc)); | |
915 } | |
916 if (is_verified_oop_load) { | |
917 __ verify_oop(reg_to_register_object(dst_enc)); | |
918 } | |
919 } | |
920 #endif | |
921 } | |
922 | |
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { | |
925 | |
926 uint instr; | |
927 instr = (Assembler::ldst_op << 30) | |
928 | (dst_enc << 25) | |
929 | (primary << 19) | |
930 | (src1_enc << 14); | |
931 | |
932 int disp = disp32; | |
933 int index = src2_enc; | |
934 | |
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
936 disp += STACK_BIAS; | |
937 | |
938 // We should have a compiler bailout here rather than a guarantee. | |
939 // Better yet would be some mechanism to handle variable-size matches correctly. | |
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
941 | |
942 if( disp != 0 ) { | |
943 // use reg-reg form | |
944 // set src2=R_O7 contains offset | |
945 index = R_O7_enc; | |
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); | |
947 } | |
948 instr |= (asi << 5); | |
949 instr |= index; | |
950 uint *code = (uint*)cbuf.code_end(); | |
951 *code = instr; | |
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
953 } | |
954 | |
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
956 // The method which records debug information at every safepoint | |
957 // expects the call to be the first instruction in the snippet as | |
958 // it creates a PcDesc structure which tracks the offset of a call | |
959 // from the start of the codeBlob. This offset is computed as | |
960 // code_end() - code_begin() of the code which has been emitted | |
961 // so far. | |
962 // In this particular case we have skirted around the problem by | |
963 // putting the "mov" instruction in the delay slot but the problem | |
964 // may bite us again at some other point and a cleaner/generic | |
965 // solution using relocations would be needed. | |
966 MacroAssembler _masm(&cbuf); | |
967 __ set_inst_mark(); | |
968 | |
969 // We flush the current window just so that there is a valid stack copy | |
970 // the fact that the current window becomes active again instantly is | |
971 // not a problem there is nothing live in it. | |
972 | |
973 #ifdef ASSERT | |
974 int startpos = __ offset(); | |
975 #endif /* ASSERT */ | |
976 | |
977 #ifdef _LP64 | |
978 // Calls to the runtime or native may not be reachable from compiled code, | |
979 // so we generate the far call sequence on 64 bit sparc. | |
980 // This code sequence is relocatable to any address, even on LP64. | |
981 if ( force_far_call ) { | |
982 __ relocate(rtype); | |
727 | 983 AddressLiteral dest(entry_point); |
984 __ jumpl_to(dest, O7, O7); | |
0 | 985 } |
986 else | |
987 #endif | |
988 { | |
989 __ call((address)entry_point, rtype); | |
990 } | |
991 | |
992 if (preserve_g2) __ delayed()->mov(G2, L7); | |
993 else __ delayed()->nop(); | |
994 | |
995 if (preserve_g2) __ mov(L7, G2); | |
996 | |
997 #ifdef ASSERT | |
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
999 #ifdef _LP64 | |
1000 // Trash argument dump slots. | |
1001 __ set(0xb0b8ac0db0b8ac0d, G1); | |
1002 __ mov(G1, G5); | |
1003 __ stx(G1, SP, STACK_BIAS + 0x80); | |
1004 __ stx(G1, SP, STACK_BIAS + 0x88); | |
1005 __ stx(G1, SP, STACK_BIAS + 0x90); | |
1006 __ stx(G1, SP, STACK_BIAS + 0x98); | |
1007 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
1008 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
1009 #else // _LP64 | |
1010 // this is also a native call, so smash the first 7 stack locations, | |
1011 // and the various registers | |
1012 | |
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
1014 // while [SP+0x44..0x58] are the argument dump slots. | |
1015 __ set((intptr_t)0xbaadf00d, G1); | |
1016 __ mov(G1, G5); | |
1017 __ sllx(G1, 32, G1); | |
1018 __ or3(G1, G5, G1); | |
1019 __ mov(G1, G5); | |
1020 __ stx(G1, SP, 0x40); | |
1021 __ stx(G1, SP, 0x48); | |
1022 __ stx(G1, SP, 0x50); | |
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1024 #endif // _LP64 | |
1025 } | |
1026 #endif /*ASSERT*/ | |
1027 } | |
1028 | |
1029 //============================================================================= | |
1030 // REQUIRED FUNCTIONALITY for encoding | |
1031 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1032 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1033 | |
1034 | |
1035 //============================================================================= | |
1036 | |
1037 #ifndef PRODUCT | |
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1039 Compile* C = ra_->C; | |
1040 | |
1041 for (int i = 0; i < OptoPrologueNops; i++) { | |
1042 st->print_cr("NOP"); st->print("\t"); | |
1043 } | |
1044 | |
1045 if( VerifyThread ) { | |
1046 st->print_cr("Verify_Thread"); st->print("\t"); | |
1047 } | |
1048 | |
1049 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1050 | |
1051 // Calls to C2R adapters often do not accept exceptional returns. | |
1052 // We require that their callers must bang for them. But be careful, because | |
1053 // some VM calls (such as call site linkage) can use several kilobytes of | |
1054 // stack. But the stack safety zone should account for that. | |
1055 // See bugs 4446381, 4468289, 4497237. | |
1056 if (C->need_stack_bang(framesize)) { | |
1057 st->print_cr("! stack bang"); st->print("\t"); | |
1058 } | |
1059 | |
1060 if (Assembler::is_simm13(-framesize)) { | |
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1062 } else { | |
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1065 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1066 } | |
1067 | |
1068 } | |
1069 #endif | |
1070 | |
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1072 Compile* C = ra_->C; | |
1073 MacroAssembler _masm(&cbuf); | |
1074 | |
1075 for (int i = 0; i < OptoPrologueNops; i++) { | |
1076 __ nop(); | |
1077 } | |
1078 | |
1079 __ verify_thread(); | |
1080 | |
1081 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1084 | |
1085 // Calls to C2R adapters often do not accept exceptional returns. | |
1086 // We require that their callers must bang for them. But be careful, because | |
1087 // some VM calls (such as call site linkage) can use several kilobytes of | |
1088 // stack. But the stack safety zone should account for that. | |
1089 // See bugs 4446381, 4468289, 4497237. | |
1090 if (C->need_stack_bang(framesize)) { | |
1091 __ generate_stack_overflow_check(framesize); | |
1092 } | |
1093 | |
1094 if (Assembler::is_simm13(-framesize)) { | |
1095 __ save(SP, -framesize, SP); | |
1096 } else { | |
1097 __ sethi(-framesize & ~0x3ff, G3); | |
1098 __ add(G3, -framesize & 0x3ff, G3); | |
1099 __ save(SP, G3, SP); | |
1100 } | |
1101 C->set_frame_complete( __ offset() ); | |
1102 } | |
1103 | |
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1105 return MachNode::size(ra_); | |
1106 } | |
1107 | |
1108 int MachPrologNode::reloc() const { | |
1109 return 10; // a large enough number | |
1110 } | |
1111 | |
1112 //============================================================================= | |
1113 #ifndef PRODUCT | |
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1115 Compile* C = ra_->C; | |
1116 | |
1117 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1119 #ifdef _LP64 | |
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1121 #else | |
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1123 #endif | |
1124 } | |
1125 | |
1126 if( do_polling() ) | |
1127 st->print("RET\n\t"); | |
1128 | |
1129 st->print("RESTORE"); | |
1130 } | |
1131 #endif | |
1132 | |
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1134 MacroAssembler _masm(&cbuf); | |
1135 Compile* C = ra_->C; | |
1136 | |
1137 __ verify_thread(); | |
1138 | |
1139 // If this does safepoint polling, then do it here | |
1140 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1141 AddressLiteral polling_page(os::get_polling_page()); |
1142 __ sethi(polling_page, L0); | |
0 | 1143 __ relocate(relocInfo::poll_return_type); |
1144 __ ld_ptr( L0, 0, G0 ); | |
1145 } | |
1146 | |
1147 // If this is a return, then stuff the restore in the delay slot | |
1148 if( do_polling() ) { | |
1149 __ ret(); | |
1150 __ delayed()->restore(); | |
1151 } else { | |
1152 __ restore(); | |
1153 } | |
1154 } | |
1155 | |
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1157 return MachNode::size(ra_); | |
1158 } | |
1159 | |
1160 int MachEpilogNode::reloc() const { | |
1161 return 16; // a large enough number | |
1162 } | |
1163 | |
1164 const Pipeline * MachEpilogNode::pipeline() const { | |
1165 return MachNode::pipeline_class(); | |
1166 } | |
1167 | |
1168 int MachEpilogNode::safepoint_offset() const { | |
1169 assert( do_polling(), "no return for this epilog node"); | |
1170 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
1171 } | |
1172 | |
1173 //============================================================================= | |
1174 | |
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1177 static enum RC rc_class( OptoReg::Name reg ) { | |
1178 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1179 if (OptoReg::is_stack(reg)) return rc_stack; | |
1180 VMReg r = OptoReg::as_VMReg(reg); | |
1181 if (r->is_Register()) return rc_int; | |
1182 assert(r->is_FloatRegister(), "must be"); | |
1183 return rc_float; | |
1184 } | |
1185 | |
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1187 if( cbuf ) { | |
1188 // Better yet would be some mechanism to handle variable-size matches correctly | |
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1191 } else { | |
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1193 } | |
1194 } | |
1195 #ifndef PRODUCT | |
1196 else if( !do_size ) { | |
1197 if( size != 0 ) st->print("\n\t"); | |
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1200 } | |
1201 #endif | |
1202 return size+4; | |
1203 } | |
1204 | |
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1207 #ifndef PRODUCT | |
1208 else if( !do_size ) { | |
1209 if( size != 0 ) st->print("\n\t"); | |
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1211 } | |
1212 #endif | |
1213 return size+4; | |
1214 } | |
1215 | |
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1217 PhaseRegAlloc *ra_, | |
1218 bool do_size, | |
1219 outputStream* st ) const { | |
1220 // Get registers to move | |
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1223 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1224 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1225 | |
1226 enum RC src_second_rc = rc_class(src_second); | |
1227 enum RC src_first_rc = rc_class(src_first); | |
1228 enum RC dst_second_rc = rc_class(dst_second); | |
1229 enum RC dst_first_rc = rc_class(dst_first); | |
1230 | |
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1232 | |
1233 // Generate spill code! | |
1234 int size = 0; | |
1235 | |
1236 if( src_first == dst_first && src_second == dst_second ) | |
1237 return size; // Self copy, no move | |
1238 | |
1239 // -------------------------------------- | |
1240 // Check for mem-mem move. Load into unused float registers and fall into | |
1241 // the float-store case. | |
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1243 int offset = ra_->reg2offset(src_first); | |
1244 // Further check for aligned-adjacent pair, so we can use a double load | |
1245 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1246 src_second = OptoReg::Name(R_F31_num); | |
1247 src_second_rc = rc_float; | |
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1249 } else { | |
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1251 } | |
1252 src_first = OptoReg::Name(R_F30_num); | |
1253 src_first_rc = rc_float; | |
1254 } | |
1255 | |
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1257 int offset = ra_->reg2offset(src_second); | |
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1259 src_second = OptoReg::Name(R_F31_num); | |
1260 src_second_rc = rc_float; | |
1261 } | |
1262 | |
1263 // -------------------------------------- | |
1264 // Check for float->int copy; requires a trip through memory | |
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
1266 int offset = frame::register_save_words*wordSize; | |
1267 if( cbuf ) { | |
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1272 } | |
1273 #ifndef PRODUCT | |
1274 else if( !do_size ) { | |
1275 if( size != 0 ) st->print("\n\t"); | |
1276 st->print( "SUB R_SP,16,R_SP\n"); | |
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1279 st->print("\tADD R_SP,16,R_SP\n"); | |
1280 } | |
1281 #endif | |
1282 size += 16; | |
1283 } | |
1284 | |
1285 // -------------------------------------- | |
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1288 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1289 // there. Misaligned sources only come from native-long-returns (handled | |
1290 // special below). | |
1291 #ifndef _LP64 | |
1292 if( src_first_rc == rc_int && // source is already big-endian | |
1293 src_second_rc != rc_bad && // 64-bit move | |
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1296 // Do the big-endian flop. | |
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1299 } | |
1300 #endif | |
1301 | |
1302 // -------------------------------------- | |
1303 // Check for integer reg-reg copy | |
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1305 #ifndef _LP64 | |
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1309 // operand contains the least significant word of the 64-bit value and vice versa. | |
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1313 if( cbuf ) { | |
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1317 #ifndef PRODUCT | |
1318 } else if( !do_size ) { | |
1319 if( size != 0 ) st->print("\n\t"); | |
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1323 #endif | |
1324 } | |
1325 return size+12; | |
1326 } | |
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1328 // returning a long value in I0/I1 | |
1329 // a SpillCopy must be able to target a return instruction's reg_class | |
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1332 // operand contains the least significant word of the 64-bit value and vice versa. | |
1333 OptoReg::Name tdest = dst_first; | |
1334 | |
1335 if (src_first == dst_first) { | |
1336 tdest = OptoReg::Name(R_O7_num); | |
1337 size += 4; | |
1338 } | |
1339 | |
1340 if( cbuf ) { | |
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1343 // ShrL_reg_imm6 | |
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1345 // ShrR_reg_imm6 src, 0, dst | |
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1347 if (tdest != dst_first) { | |
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1349 } | |
1350 } | |
1351 #ifndef PRODUCT | |
1352 else if( !do_size ) { | |
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1356 if (tdest != dst_first) { | |
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1358 } | |
1359 } | |
1360 #endif // PRODUCT | |
1361 return size+8; | |
1362 } | |
1363 #endif // !_LP64 | |
1364 // Else normal reg-reg copy | |
1365 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1368 // This moves an aligned adjacent pair. | |
1369 // See if we are done. | |
1370 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1371 return size; | |
1372 } | |
1373 | |
1374 // Check for integer store | |
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1376 int offset = ra_->reg2offset(dst_first); | |
1377 // Further check for aligned-adjacent pair, so we can use a double store | |
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1381 } | |
1382 | |
1383 // Check for integer load | |
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1385 int offset = ra_->reg2offset(src_first); | |
1386 // Further check for aligned-adjacent pair, so we can use a double load | |
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1390 } | |
1391 | |
1392 // Check for float reg-reg copy | |
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1394 // Further check for aligned-adjacent pair, so we can use a double move | |
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1398 } | |
1399 | |
1400 // Check for float store | |
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1402 int offset = ra_->reg2offset(dst_first); | |
1403 // Further check for aligned-adjacent pair, so we can use a double store | |
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1407 } | |
1408 | |
1409 // Check for float load | |
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1411 int offset = ra_->reg2offset(src_first); | |
1412 // Further check for aligned-adjacent pair, so we can use a double load | |
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1416 } | |
1417 | |
1418 // -------------------------------------------------------------------- | |
1419 // Check for hi bits still needing moving. Only happens for misaligned | |
1420 // arguments to native calls. | |
1421 if( src_second == dst_second ) | |
1422 return size; // Self copy; no move | |
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1424 | |
1425 #ifndef _LP64 | |
1426 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1427 // pairs, so there's never any need to move the high bits separately. |
0 | 1428 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1429 // all sorts of silly alignment problems. | |
1430 | |
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1432 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1433 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1434 // happened already as part of a 64-bit move) | |
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1438 // Shift src_second down to dst_second's low bits. | |
1439 if( cbuf ) { | |
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1441 #ifndef PRODUCT | |
1442 } else if( !do_size ) { | |
1443 if( size != 0 ) st->print("\n\t"); | |
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1445 #endif | |
1446 } | |
1447 return size+4; | |
1448 } | |
1449 | |
1450 // Check for high word integer store. Must down-shift the hi bits | |
1451 // into a temp register, then fall into the case of storing int bits. | |
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1453 // Shift src_second down to dst_second's low bits. | |
1454 if( cbuf ) { | |
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1456 #ifndef PRODUCT | |
1457 } else if( !do_size ) { | |
1458 if( size != 0 ) st->print("\n\t"); | |
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1460 #endif | |
1461 } | |
1462 size+=4; | |
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1464 } | |
1465 | |
1466 // Check for high word integer load | |
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1469 | |
1470 // Check for high word integer store | |
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1473 | |
1474 // Check for high word float store | |
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1477 | |
1478 #endif // !_LP64 | |
1479 | |
1480 Unimplemented(); | |
1481 } | |
1482 | |
1483 #ifndef PRODUCT | |
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1485 implementation( NULL, ra_, false, st ); | |
1486 } | |
1487 #endif | |
1488 | |
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1490 implementation( &cbuf, ra_, false, NULL ); | |
1491 } | |
1492 | |
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1494 return implementation( NULL, ra_, true, NULL ); | |
1495 } | |
1496 | |
1497 //============================================================================= | |
1498 #ifndef PRODUCT | |
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1501 } | |
1502 #endif | |
1503 | |
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1505 MacroAssembler _masm(&cbuf); | |
1506 for(int i = 0; i < _count; i += 1) { | |
1507 __ nop(); | |
1508 } | |
1509 } | |
1510 | |
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1512 return 4 * _count; | |
1513 } | |
1514 | |
1515 | |
1516 //============================================================================= | |
1517 #ifndef PRODUCT | |
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1520 int reg = ra_->get_reg_first(this); | |
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1522 } | |
1523 #endif | |
1524 | |
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1526 MacroAssembler _masm(&cbuf); | |
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1528 int reg = ra_->get_encode(this); | |
1529 | |
1530 if (Assembler::is_simm13(offset)) { | |
1531 __ add(SP, offset, reg_to_register_object(reg)); | |
1532 } else { | |
1533 __ set(offset, O7); | |
1534 __ add(SP, O7, reg_to_register_object(reg)); | |
1535 } | |
1536 } | |
1537 | |
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1540 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1541 return ra_->C->scratch_emit_size(this); | |
1542 } | |
1543 | |
1544 //============================================================================= | |
1545 | |
1546 // emit call stub, compiled java to interpretor | |
1547 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
1548 | |
1549 // Stub is fixed up when the corresponding call is converted from calling | |
1550 // compiled code to calling interpreted code. | |
1551 // set (empty), G5 | |
1552 // jmp -1 | |
1553 | |
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
1555 | |
1556 MacroAssembler _masm(&cbuf); | |
1557 | |
1558 address base = | |
1559 __ start_a_stub(Compile::MAX_stubs_size); | |
1560 if (base == NULL) return; // CodeBuffer::expand failed | |
1561 | |
1562 // static stub relocation stores the instruction address of the call | |
1563 __ relocate(static_stub_Relocation::spec(mark)); | |
1564 | |
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
1566 | |
1567 __ set_inst_mark(); | |
727 | 1568 AddressLiteral addrlit(-1); |
1569 __ JUMP(addrlit, G3, 0); | |
0 | 1570 |
1571 __ delayed()->nop(); | |
1572 | |
1573 // Update current stubs pointer and restore code_end. | |
1574 __ end_a_stub(); | |
1575 } | |
1576 | |
1577 // size of call stub, compiled java to interpretor | |
1578 uint size_java_to_interp() { | |
1579 // This doesn't need to be accurate but it must be larger or equal to | |
1580 // the real size of the stub. | |
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
1582 NativeJump::instruction_size + // sethi; jmp; nop | |
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
1584 } | |
1585 // relocation entries for call stub, compiled java to interpretor | |
1586 uint reloc_java_to_interp() { | |
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
1588 } | |
1589 | |
1590 | |
1591 //============================================================================= | |
1592 #ifndef PRODUCT | |
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1594 st->print_cr("\nUEP:"); | |
1595 #ifdef _LP64 | |
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1596 if (UseCompressedOops) { |
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1597 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1599 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1600 if (Universe::narrow_oop_base() != NULL) |
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1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1602 } else { |
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1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1604 } |
0 | 1605 st->print_cr("\tCMP R_G5,R_G3" ); |
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1607 #else // _LP64 | |
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1609 st->print_cr("\tCMP R_G5,R_G3" ); | |
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1611 #endif // _LP64 | |
1612 } | |
1613 #endif | |
1614 | |
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1616 MacroAssembler _masm(&cbuf); | |
1617 Label L; | |
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1619 Register temp_reg = G3; | |
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1621 | |
605 | 1622 // Load klass from receiver |
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1623 __ load_klass(O0, temp_reg); |
0 | 1624 // Compare against expected klass |
1625 __ cmp(temp_reg, G5_ic_reg); | |
1626 // Branch to miss code, checks xcc or icc depending | |
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1628 } | |
1629 | |
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1631 return MachNode::size(ra_); | |
1632 } | |
1633 | |
1634 | |
1635 //============================================================================= | |
1636 | |
1637 uint size_exception_handler() { | |
1638 if (TraceJumps) { | |
1639 return (400); // just a guess | |
1640 } | |
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1642 } | |
1643 | |
1644 uint size_deopt_handler() { | |
1645 if (TraceJumps) { | |
1646 return (400); // just a guess | |
1647 } | |
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1649 } | |
1650 | |
1651 // Emit exception handler code. | |
1652 int emit_exception_handler(CodeBuffer& cbuf) { | |
1653 Register temp_reg = G3; | |
727 | 1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); |
0 | 1655 MacroAssembler _masm(&cbuf); |
1656 | |
1657 address base = | |
1658 __ start_a_stub(size_exception_handler()); | |
1659 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1660 | |
1661 int offset = __ offset(); | |
1662 | |
727 | 1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1664 __ delayed()->nop(); |
1665 | |
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1667 | |
1668 __ end_a_stub(); | |
1669 | |
1670 return offset; | |
1671 } | |
1672 | |
1673 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1674 // Can't use any of the current frame's registers as we may have deopted | |
1675 // at a poll and everything (including G3) can be live. | |
1676 Register temp_reg = L0; | |
727 | 1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1678 MacroAssembler _masm(&cbuf); |
1679 | |
1680 address base = | |
1681 __ start_a_stub(size_deopt_handler()); | |
1682 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1683 | |
1684 int offset = __ offset(); | |
1685 __ save_frame(0); | |
727 | 1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1687 __ delayed()->restore(); |
1688 | |
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1690 | |
1691 __ end_a_stub(); | |
1692 return offset; | |
1693 | |
1694 } | |
1695 | |
1696 // Given a register encoding, produce a Integer Register object | |
1697 static Register reg_to_register_object(int register_encoding) { | |
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1699 return as_Register(register_encoding); | |
1700 } | |
1701 | |
1702 // Given a register encoding, produce a single-precision Float Register object | |
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1705 return as_SingleFloatRegister(register_encoding); | |
1706 } | |
1707 | |
1708 // Given a register encoding, produce a double-precision Float Register object | |
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1712 return as_DoubleFloatRegister(register_encoding); | |
1713 } | |
1714 | |
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1715 const bool Matcher::match_rule_supported(int opcode) { |
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1716 if (!has_match_rule(opcode)) |
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1717 return false; |
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1718 |
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1719 switch (opcode) { |
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1720 case Op_CountLeadingZerosI: |
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1721 case Op_CountLeadingZerosL: |
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1722 case Op_CountTrailingZerosI: |
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1723 case Op_CountTrailingZerosL: |
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1724 if (!UsePopCountInstruction) |
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1725 return false; |
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1726 break; |
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1727 } |
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1728 |
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1729 return true; // Per default match rules are supported. |
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1730 } |
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1731 |
0 | 1732 int Matcher::regnum_to_fpu_offset(int regnum) { |
1733 return regnum - 32; // The FP registers are in the second chunk | |
1734 } | |
1735 | |
1736 #ifdef ASSERT | |
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1738 #endif | |
1739 | |
1740 // Vector width in bytes | |
1741 const uint Matcher::vector_width_in_bytes(void) { | |
1742 return 8; | |
1743 } | |
1744 | |
1745 // Vector ideal reg | |
1746 const uint Matcher::vector_ideal_reg(void) { | |
1747 return Op_RegD; | |
1748 } | |
1749 | |
1750 // USII supports fxtof through the whole range of number, USIII doesn't | |
1751 const bool Matcher::convL2FSupported(void) { | |
1752 return VM_Version::has_fast_fxtof(); | |
1753 } | |
1754 | |
1755 // Is this branch offset short enough that a short branch can be used? | |
1756 // | |
1757 // NOTE: If the platform does not provide any short branch variants, then | |
1758 // this method should return false for offset 0. | |
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1759 bool Matcher::is_short_branch_offset(int rule, int offset) { |
0 | 1760 return false; |
1761 } | |
1762 | |
1763 const bool Matcher::isSimpleConstant64(jlong value) { | |
1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1765 // Depends on optimizations in MacroAssembler::setx. | |
1766 int hi = (int)(value >> 32); | |
1767 int lo = (int)(value & ~0); | |
1768 return (hi == 0) || (hi == -1) || (lo == 0); | |
1769 } | |
1770 | |
1771 // No scaling for the parameter the ClearArray node. | |
1772 const bool Matcher::init_array_count_is_in_bytes = true; | |
1773 | |
1774 // Threshold size for cleararray. | |
1775 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1776 | |
1777 // Should the Matcher clone shifts on addressing modes, expecting them to | |
1778 // be subsumed into complex addressing expressions or compute them into | |
1779 // registers? True for Intel but false for most RISCs | |
1780 const bool Matcher::clone_shift_expressions = false; | |
1781 | |
1782 // Is it better to copy float constants, or load them directly from memory? | |
1783 // Intel can load a float constant from a direct address, requiring no | |
1784 // extra registers. Most RISCs will have to materialize an address into a | |
1785 // register first, so they would do better to copy the constant from stack. | |
1786 const bool Matcher::rematerialize_float_constants = false; | |
1787 | |
1788 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1789 // needed. Else we split the double into 2 integer pieces and move it | |
1790 // piece-by-piece. Only happens when passing doubles into C code as the | |
1791 // Java calling convention forces doubles to be aligned. | |
1792 #ifdef _LP64 | |
1793 const bool Matcher::misaligned_doubles_ok = true; | |
1794 #else | |
1795 const bool Matcher::misaligned_doubles_ok = false; | |
1796 #endif | |
1797 | |
1798 // No-op on SPARC. | |
1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1800 } | |
1801 | |
1802 // Advertise here if the CPU requires explicit rounding operations | |
1803 // to implement the UseStrictFP mode. | |
1804 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1805 | |
1806 // Do floats take an entire double register or just half? | |
1807 const bool Matcher::float_in_double = false; | |
1808 | |
1809 // Do ints take an entire long register or just half? | |
1810 // Note that we if-def off of _LP64. | |
1811 // The relevant question is how the int is callee-saved. In _LP64 | |
1812 // the whole long is written but de-opt'ing will have to extract | |
1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1814 #ifdef _LP64 | |
1815 const bool Matcher::int_in_long = true; | |
1816 #else | |
1817 const bool Matcher::int_in_long = false; | |
1818 #endif | |
1819 | |
1820 // Return whether or not this register is ever used as an argument. This | |
1821 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1822 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1823 // arguments in those registers not be available to the callee. | |
1824 bool Matcher::can_be_java_arg( int reg ) { | |
1825 // Standard sparc 6 args in registers | |
1826 if( reg == R_I0_num || | |
1827 reg == R_I1_num || | |
1828 reg == R_I2_num || | |
1829 reg == R_I3_num || | |
1830 reg == R_I4_num || | |
1831 reg == R_I5_num ) return true; | |
1832 #ifdef _LP64 | |
1833 // 64-bit builds can pass 64-bit pointers and longs in | |
1834 // the high I registers | |
1835 if( reg == R_I0H_num || | |
1836 reg == R_I1H_num || | |
1837 reg == R_I2H_num || | |
1838 reg == R_I3H_num || | |
1839 reg == R_I4H_num || | |
1840 reg == R_I5H_num ) return true; | |
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1841 |
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1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1843 return true; |
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1844 } |
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1845 |
0 | 1846 #else |
1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1848 // Longs cannot be passed in O regs, because O regs become I regs | |
1849 // after a 'save' and I regs get their high bits chopped off on | |
1850 // interrupt. | |
1851 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1852 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1853 #endif | |
1854 // A few float args in registers | |
1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1856 | |
1857 return false; | |
1858 } | |
1859 | |
1860 bool Matcher::is_spillable_arg( int reg ) { | |
1861 return can_be_java_arg(reg); | |
1862 } | |
1863 | |
1864 // Register for DIVI projection of divmodI | |
1865 RegMask Matcher::divI_proj_mask() { | |
1866 ShouldNotReachHere(); | |
1867 return RegMask(); | |
1868 } | |
1869 | |
1870 // Register for MODI projection of divmodI | |
1871 RegMask Matcher::modI_proj_mask() { | |
1872 ShouldNotReachHere(); | |
1873 return RegMask(); | |
1874 } | |
1875 | |
1876 // Register for DIVL projection of divmodL | |
1877 RegMask Matcher::divL_proj_mask() { | |
1878 ShouldNotReachHere(); | |
1879 return RegMask(); | |
1880 } | |
1881 | |
1882 // Register for MODL projection of divmodL | |
1883 RegMask Matcher::modL_proj_mask() { | |
1884 ShouldNotReachHere(); | |
1885 return RegMask(); | |
1886 } | |
1887 | |
1888 %} | |
1889 | |
1890 | |
1891 // The intptr_t operand types, defined by textual substitution. | |
1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
1893 #ifdef _LP64 | |
824 | 1894 #define immX immL |
1895 #define immX13 immL13 | |
1896 #define immX13m7 immL13m7 | |
1897 #define iRegX iRegL | |
1898 #define g1RegX g1RegL | |
0 | 1899 #else |
824 | 1900 #define immX immI |
1901 #define immX13 immI13 | |
1902 #define immX13m7 immI13m7 | |
1903 #define iRegX iRegI | |
1904 #define g1RegX g1RegI | |
0 | 1905 #endif |
1906 | |
1907 //----------ENCODING BLOCK----------------------------------------------------- | |
1908 // This block specifies the encoding classes used by the compiler to output | |
1909 // byte streams. Encoding classes are parameterized macros used by | |
1910 // Machine Instruction Nodes in order to generate the bit encoding of the | |
1911 // instruction. Operands specify their base encoding interface with the | |
1912 // interface keyword. There are currently supported four interfaces, | |
1913 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
1914 // operand to generate a function which returns its register number when | |
1915 // queried. CONST_INTER causes an operand to generate a function which | |
1916 // returns the value of the constant when queried. MEMORY_INTER causes an | |
1917 // operand to generate four functions which return the Base Register, the | |
1918 // Index Register, the Scale Value, and the Offset Value of the operand when | |
1919 // queried. COND_INTER causes an operand to generate six functions which | |
1920 // return the encoding code (ie - encoding bits for the instruction) | |
1921 // associated with each basic boolean condition for a conditional instruction. | |
1922 // | |
1923 // Instructions specify two basic values for encoding. Again, a function | |
1924 // is available to check if the constant displacement is an oop. They use the | |
1925 // ins_encode keyword to specify their encoding classes (which must be | |
1926 // a sequence of enc_class names, and their parameters, specified in | |
1927 // the encoding block), and they use the | |
1928 // opcode keyword to specify, in order, their primary, secondary, and | |
1929 // tertiary opcode. Only the opcode sections which a particular instruction | |
1930 // needs for encoding need to be specified. | |
1931 encode %{ | |
1932 enc_class enc_untested %{ | |
1933 #ifdef ASSERT | |
1934 MacroAssembler _masm(&cbuf); | |
1935 __ untested("encoding"); | |
1936 #endif | |
1937 %} | |
1938 | |
1939 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
1940 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
1941 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
1942 %} | |
1943 | |
415
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1944 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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1945 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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1946 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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1947 %} |
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1948 |
0 | 1949 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ |
415
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1950 emit_form3_mem_reg_asi(cbuf, this, $primary, -1, |
0 | 1951 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); |
1952 %} | |
1953 | |
1954 enc_class form3_mem_prefetch_read( memory mem ) %{ | |
415
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1955 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1956 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
1957 %} | |
1958 | |
1959 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
415
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1960 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1961 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
1962 %} | |
1963 | |
1964 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
1965 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1966 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1967 guarantee($mem$$index == R_G0_enc, "double index?"); | |
415
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1968 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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1969 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 1970 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
1971 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
1972 %} | |
1973 | |
1974 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
1975 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1976 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1977 guarantee($mem$$index == R_G0_enc, "double index?"); | |
1978 // Load long with 2 instructions | |
415
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1979 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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1980 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 1981 %} |
1982 | |
1983 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
1984 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
1985 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
415
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1986 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 1987 %} |
1988 | |
1989 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
1990 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1991 if( $rs2$$reg != $rd$$reg ) | |
1992 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
1993 %} | |
1994 | |
1995 // Target lo half of long | |
1996 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
1997 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1998 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
1999 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2000 %} | |
2001 | |
2002 // Source lo half of long | |
2003 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2004 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2005 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2006 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2007 %} | |
2008 | |
2009 // Target hi half of long | |
2010 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2011 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2012 %} | |
2013 | |
2014 // Source lo half of long, and leave it sign extended. | |
2015 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2016 // Sign extend low half | |
2017 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2018 %} | |
2019 | |
2020 // Source hi half of long, and leave it sign extended. | |
2021 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2022 // Shift high half to low half | |
2023 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2024 %} | |
2025 | |
2026 // Source hi half of long | |
2027 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2028 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2029 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2030 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2031 %} | |
2032 | |
2033 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2034 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2035 %} | |
2036 | |
2037 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2038 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2039 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2040 %} | |
2041 | |
2042 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2043 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2044 // clear if nothing else is happening | |
2045 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2046 // blt,a,pn done | |
2047 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2048 // mov dst,-1 in delay slot | |
2049 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2050 %} | |
2051 | |
2052 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2053 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2054 %} | |
2055 | |
2056 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2057 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2058 %} | |
2059 | |
2060 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2061 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2062 %} | |
2063 | |
2064 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2065 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2066 %} | |
2067 | |
2068 enc_class move_return_pc_to_o1() %{ | |
2069 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2070 %} | |
2071 | |
2072 #ifdef _LP64 | |
2073 /* %%% merge with enc_to_bool */ | |
2074 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2075 MacroAssembler _masm(&cbuf); | |
2076 | |
2077 Register src_reg = reg_to_register_object($src$$reg); | |
2078 Register dst_reg = reg_to_register_object($dst$$reg); | |
2079 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2080 %} | |
2081 #endif | |
2082 | |
2083 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2084 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2085 MacroAssembler _masm(&cbuf); | |
2086 | |
2087 Register p_reg = reg_to_register_object($p$$reg); | |
2088 Register q_reg = reg_to_register_object($q$$reg); | |
2089 Register y_reg = reg_to_register_object($y$$reg); | |
2090 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2091 | |
2092 __ subcc( p_reg, q_reg, p_reg ); | |
2093 __ add ( p_reg, y_reg, tmp_reg ); | |
2094 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2095 %} | |
2096 | |
2097 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2098 // fcmp %fcc0,$src,$src | |
2099 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2100 // branch %fcc0 not-nan, predict taken | |
2101 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2102 // fdtoi $src,$dst | |
2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2104 // fitos $dst,$dst (if nan) | |
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2106 // clear $dst (if nan) | |
2107 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2108 // carry on here... | |
2109 %} | |
2110 | |
2111 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2112 // fcmp %fcc0,$src,$src check for NAN | |
2113 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2114 // branch %fcc0 not-nan, predict taken | |
2115 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2116 // fdtox $src,$dst convert in delay slot | |
2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2118 // fxtod $dst,$dst (if nan) | |
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2120 // clear $dst (if nan) | |
2121 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2122 // carry on here... | |
2123 %} | |
2124 | |
2125 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2126 // fcmps %fcc0,$src,$src | |
2127 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2128 // branch %fcc0 not-nan, predict taken | |
2129 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2130 // fstoi $src,$dst | |
2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2132 // fitos $dst,$dst (if nan) | |
2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2134 // clear $dst (if nan) | |
2135 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2136 // carry on here... | |
2137 %} | |
2138 | |
2139 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2140 // fcmps %fcc0,$src,$src | |
2141 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2142 // branch %fcc0 not-nan, predict taken | |
2143 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2144 // fstox $src,$dst | |
2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2146 // fxtod $dst,$dst (if nan) | |
2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2148 // clear $dst (if nan) | |
2149 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2150 // carry on here... | |
2151 %} | |
2152 | |
2153 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2154 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2155 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2156 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2157 | |
2158 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2159 | |
2160 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2161 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2162 | |
2163 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2164 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2165 %} | |
2166 | |
2167 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2168 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2169 %} | |
2170 | |
2171 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2172 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2173 %} | |
2174 | |
2175 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2176 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2177 %} | |
2178 | |
2179 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2180 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2181 %} | |
2182 | |
2183 // Encloding class for traceable jumps | |
2184 enc_class form_jmpl(g3RegP dest) %{ | |
2185 emit_jmpl(cbuf, $dest$$reg); | |
2186 %} | |
2187 | |
2188 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2189 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2190 %} | |
2191 | |
2192 enc_class form2_nop() %{ | |
2193 emit_nop(cbuf); | |
2194 %} | |
2195 | |
2196 enc_class form2_illtrap() %{ | |
2197 emit_illtrap(cbuf); | |
2198 %} | |
2199 | |
2200 | |
2201 // Compare longs and convert into -1, 0, 1. | |
2202 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2203 // CMP $src1,$src2 | |
2204 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2205 // blt,a,pn done | |
2206 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2207 // mov dst,-1 in delay slot | |
2208 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2209 // bgt,a,pn done | |
2210 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2211 // mov dst,1 in delay slot | |
2212 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2213 // CLR $dst | |
2214 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2215 %} | |
2216 | |
2217 enc_class enc_PartialSubtypeCheck() %{ | |
2218 MacroAssembler _masm(&cbuf); | |
2219 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2220 __ delayed()->nop(); | |
2221 %} | |
2222 | |
2223 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
2224 MacroAssembler _masm(&cbuf); | |
2225 Label &L = *($labl$$label); | |
2226 Assembler::Predict predict_taken = | |
2227 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2228 | |
2229 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
2230 __ delayed()->nop(); | |
2231 %} | |
2232 | |
2233 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
2234 MacroAssembler _masm(&cbuf); | |
2235 Label &L = *($labl$$label); | |
2236 Assembler::Predict predict_taken = | |
2237 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2238 | |
2239 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
2240 __ delayed()->nop(); | |
2241 %} | |
2242 | |
2243 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
2244 MacroAssembler _masm(&cbuf); | |
2245 Label &L = *($labl$$label); | |
2246 Assembler::Predict predict_taken = | |
2247 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2248 | |
2249 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
2250 __ delayed()->nop(); | |
2251 %} | |
2252 | |
2253 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
2254 MacroAssembler _masm(&cbuf); | |
2255 Label &L = *($labl$$label); | |
2256 Assembler::Predict predict_taken = | |
2257 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2258 | |
2259 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
2260 __ delayed()->nop(); | |
2261 %} | |
2262 | |
2263 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
2264 MacroAssembler _masm(&cbuf); | |
2265 | |
2266 Register switch_reg = as_Register($switch_val$$reg); | |
2267 Register table_reg = O7; | |
2268 | |
2269 address table_base = __ address_table_constant(_index2label); | |
2270 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
2271 | |
727 | 2272 // Move table address into a register. |
2273 __ set(table_base, table_reg, rspec); | |
0 | 2274 |
2275 // Jump to base address + switch value | |
2276 __ ld_ptr(table_reg, switch_reg, table_reg); | |
2277 __ jmp(table_reg, G0); | |
2278 __ delayed()->nop(); | |
2279 | |
2280 %} | |
2281 | |
2282 enc_class enc_ba( Label labl ) %{ | |
2283 MacroAssembler _masm(&cbuf); | |
2284 Label &L = *($labl$$label); | |
2285 __ ba(false, L); | |
2286 __ delayed()->nop(); | |
2287 %} | |
2288 | |
2289 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
2290 MacroAssembler _masm(&cbuf); | |
2291 Label &L = *$labl$$label; | |
2292 Assembler::Predict predict_taken = | |
2293 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2294 | |
2295 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
2296 __ delayed()->nop(); | |
2297 %} | |
2298 | |
2299 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2300 int op = (Assembler::arith_op << 30) | | |
2301 ($dst$$reg << 25) | | |
2302 (Assembler::movcc_op3 << 19) | | |
2303 (1 << 18) | // cc2 bit for 'icc' | |
2304 ($cmp$$cmpcode << 14) | | |
2305 (0 << 13) | // select register move | |
2306 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2307 ($src$$reg << 0); | |
2308 *((int*)(cbuf.code_end())) = op; | |
2309 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2310 %} | |
2311 | |
2312 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2313 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2314 int op = (Assembler::arith_op << 30) | | |
2315 ($dst$$reg << 25) | | |
2316 (Assembler::movcc_op3 << 19) | | |
2317 (1 << 18) | // cc2 bit for 'icc' | |
2318 ($cmp$$cmpcode << 14) | | |
2319 (1 << 13) | // select immediate move | |
2320 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2321 (simm11 << 0); | |
2322 *((int*)(cbuf.code_end())) = op; | |
2323 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2324 %} | |
2325 | |
2326 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2327 int op = (Assembler::arith_op << 30) | | |
2328 ($dst$$reg << 25) | | |
2329 (Assembler::movcc_op3 << 19) | | |
2330 (0 << 18) | // cc2 bit for 'fccX' | |
2331 ($cmp$$cmpcode << 14) | | |
2332 (0 << 13) | // select register move | |
2333 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2334 ($src$$reg << 0); | |
2335 *((int*)(cbuf.code_end())) = op; | |
2336 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2337 %} | |
2338 | |
2339 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2340 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2341 int op = (Assembler::arith_op << 30) | | |
2342 ($dst$$reg << 25) | | |
2343 (Assembler::movcc_op3 << 19) | | |
2344 (0 << 18) | // cc2 bit for 'fccX' | |
2345 ($cmp$$cmpcode << 14) | | |
2346 (1 << 13) | // select immediate move | |
2347 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2348 (simm11 << 0); | |
2349 *((int*)(cbuf.code_end())) = op; | |
2350 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2351 %} | |
2352 | |
2353 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2354 int op = (Assembler::arith_op << 30) | | |
2355 ($dst$$reg << 25) | | |
2356 (Assembler::fpop2_op3 << 19) | | |
2357 (0 << 18) | | |
2358 ($cmp$$cmpcode << 14) | | |
2359 (1 << 13) | // select register move | |
2360 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2361 ($primary << 5) | // select single, double or quad | |
2362 ($src$$reg << 0); | |
2363 *((int*)(cbuf.code_end())) = op; | |
2364 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2365 %} | |
2366 | |
2367 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2368 int op = (Assembler::arith_op << 30) | | |
2369 ($dst$$reg << 25) | | |
2370 (Assembler::fpop2_op3 << 19) | | |
2371 (0 << 18) | | |
2372 ($cmp$$cmpcode << 14) | | |
2373 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2374 ($primary << 5) | // select single, double or quad | |
2375 ($src$$reg << 0); | |
2376 *((int*)(cbuf.code_end())) = op; | |
2377 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2378 %} | |
2379 | |
2380 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2381 // the condition comes from opcode-field instead of an argument. | |
2382 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2383 int op = (Assembler::arith_op << 30) | | |
2384 ($dst$$reg << 25) | | |
2385 (Assembler::movcc_op3 << 19) | | |
2386 (1 << 18) | // cc2 bit for 'icc' | |
2387 ($primary << 14) | | |
2388 (0 << 13) | // select register move | |
2389 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2390 ($src$$reg << 0); | |
2391 *((int*)(cbuf.code_end())) = op; | |
2392 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2393 %} | |
2394 | |
2395 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2396 int op = (Assembler::arith_op << 30) | | |
2397 ($dst$$reg << 25) | | |
2398 (Assembler::movcc_op3 << 19) | | |
2399 (6 << 16) | // cc2 bit for 'xcc' | |
2400 ($primary << 14) | | |
2401 (0 << 13) | // select register move | |
2402 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2403 ($src$$reg << 0); | |
2404 *((int*)(cbuf.code_end())) = op; | |
2405 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2406 %} | |
2407 | |
2408 // Utility encoding for loading a 64 bit Pointer into a register | |
2409 // The 64 bit pointer is stored in the generated code stream | |
2410 enc_class SetPtr( immP src, iRegP rd ) %{ | |
2411 Register dest = reg_to_register_object($rd$$reg); | |
727 | 2412 MacroAssembler _masm(&cbuf); |
0 | 2413 // [RGV] This next line should be generated from ADLC |
2414 if ( _opnds[1]->constant_is_oop() ) { | |
2415 intptr_t val = $src$$constant; | |
2416 __ set_oop_constant((jobject)val, dest); | |
2417 } else { // non-oop pointers, e.g. card mark base, heap top | |
727 | 2418 __ set($src$$constant, dest); |
0 | 2419 } |
2420 %} | |
2421 | |
2422 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2423 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2424 %} | |
2425 | |
2426 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2427 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2428 %} | |
2429 | |
2430 enc_class Set32( immI src, iRegI rd ) %{ | |
2431 MacroAssembler _masm(&cbuf); | |
2432 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2433 %} | |
2434 | |
2435 enc_class SetNull( iRegI rd ) %{ | |
2436 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
2437 %} | |
2438 | |
2439 enc_class call_epilog %{ | |
2440 if( VerifyStackAtCalls ) { | |
2441 MacroAssembler _masm(&cbuf); | |
2442 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2443 Register temp_reg = G3; | |
2444 __ add(SP, framesize, temp_reg); | |
2445 __ cmp(temp_reg, FP); | |
2446 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2447 } | |
2448 %} | |
2449 | |
2450 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2451 // to G1 so the register allocator will not have to deal with the misaligned register | |
2452 // pair. | |
2453 enc_class adjust_long_from_native_call %{ | |
2454 #ifndef _LP64 | |
2455 if (returns_long()) { | |
2456 // sllx O0,32,O0 | |
2457 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2458 // srl O1,0,O1 | |
2459 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2460 // or O0,O1,G1 | |
2461 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2462 } | |
2463 #endif | |
2464 %} | |
2465 | |
2466 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2467 // CALL directly to the runtime | |
2468 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2469 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
2470 /*preserve_g2=*/true, /*force far call*/true); | |
2471 %} | |
2472 | |
2473 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
2474 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2475 // who we intended to call. | |
2476 if ( !_method ) { | |
2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
2478 } else if (_optimized_virtual) { | |
2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2480 } else { | |
2481 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2482 } | |
2483 if( _method ) { // Emit stub for static call | |
2484 emit_java_to_interp(cbuf); | |
2485 } | |
2486 %} | |
2487 | |
2488 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2489 MacroAssembler _masm(&cbuf); | |
2490 __ set_inst_mark(); | |
2491 int vtable_index = this->_vtable_index; | |
2492 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2493 if (vtable_index < 0) { | |
2494 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
2495 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
2496 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2497 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2498 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
2499 // !!!!! | |
2500 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
2501 // emit_call_dynamic_prologue( cbuf ); | |
2502 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
2503 | |
2504 address virtual_call_oop_addr = __ inst_mark(); | |
2505 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2506 // who we intended to call. | |
2507 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
2508 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
2509 } else { | |
2510 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2511 // Just go thru the vtable | |
2512 // get receiver klass (receiver already checked for non-null) | |
2513 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2514 int off = __ offset(); | |
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2515 __ load_klass(O0, G3_scratch); |
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2516 int klass_load_size; |
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2517 if (UseCompressedOops) { |
642
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2518 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2519 if (Universe::narrow_oop_base() == NULL) |
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2520 klass_load_size = 2*BytesPerInstWord; |
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2521 else |
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2522 klass_load_size = 3*BytesPerInstWord; |
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2523 } else { |
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2524 klass_load_size = 1*BytesPerInstWord; |
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2525 } |
0 | 2526 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
2527 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
2528 if( __ is_simm13(v_off) ) { | |
2529 __ ld_ptr(G3, v_off, G5_method); | |
2530 } else { | |
2531 // Generate 2 instructions | |
2532 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2533 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2534 // ld_ptr, set_hi, set | |
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2535 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2536 "Unexpected instruction size(s)"); |
0 | 2537 __ ld_ptr(G3, G5_method, G5_method); |
2538 } | |
2539 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2540 // However it may very well end up in handle_wrong_method if the | |
2541 // method is abstract for the particular class. | |
2542 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
2543 // jump to target (either compiled code or c2iadapter) | |
2544 __ jmpl(G3_scratch, G0, O7); | |
2545 __ delayed()->nop(); | |
2546 } | |
2547 %} | |
2548 | |
2549 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2550 MacroAssembler _masm(&cbuf); | |
2551 | |
2552 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2553 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2554 // we might be calling a C2I adapter which needs it. | |
2555 | |
2556 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2557 // Load nmethod | |
2558 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
2559 | |
2560 // CALL to compiled java, indirect the contents of G3 | |
2561 __ set_inst_mark(); | |
2562 __ callr(temp_reg, G0); | |
2563 __ delayed()->nop(); | |
2564 %} | |
2565 | |
2566 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2567 MacroAssembler _masm(&cbuf); | |
2568 Register Rdividend = reg_to_register_object($src1$$reg); | |
2569 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2570 Register Rresult = reg_to_register_object($dst$$reg); | |
2571 | |
2572 __ sra(Rdivisor, 0, Rdivisor); | |
2573 __ sra(Rdividend, 0, Rdividend); | |
2574 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2575 %} | |
2576 | |
2577 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2578 MacroAssembler _masm(&cbuf); | |
2579 | |
2580 Register Rdividend = reg_to_register_object($src1$$reg); | |
2581 int divisor = $imm$$constant; | |
2582 Register Rresult = reg_to_register_object($dst$$reg); | |
2583 | |
2584 __ sra(Rdividend, 0, Rdividend); | |
2585 __ sdivx(Rdividend, divisor, Rresult); | |
2586 %} | |
2587 | |
2588 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2589 MacroAssembler _masm(&cbuf); | |
2590 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2591 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2592 Register Rdst = reg_to_register_object($dst$$reg); | |
2593 | |
2594 __ sra( Rsrc1, 0, Rsrc1 ); | |
2595 __ sra( Rsrc2, 0, Rsrc2 ); | |
2596 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2597 __ srlx( Rdst, 32, Rdst ); | |
2598 %} | |
2599 | |
2600 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2601 MacroAssembler _masm(&cbuf); | |
2602 Register Rdividend = reg_to_register_object($src1$$reg); | |
2603 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2604 Register Rresult = reg_to_register_object($dst$$reg); | |
2605 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2606 | |
2607 assert(Rdividend != Rscratch, ""); | |
2608 assert(Rdivisor != Rscratch, ""); | |
2609 | |
2610 __ sra(Rdividend, 0, Rdividend); | |
2611 __ sra(Rdivisor, 0, Rdivisor); | |
2612 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2613 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2614 __ sub(Rdividend, Rscratch, Rresult); | |
2615 %} | |
2616 | |
2617 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2618 MacroAssembler _masm(&cbuf); | |
2619 | |
2620 Register Rdividend = reg_to_register_object($src1$$reg); | |
2621 int divisor = $imm$$constant; | |
2622 Register Rresult = reg_to_register_object($dst$$reg); | |
2623 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2624 | |
2625 assert(Rdividend != Rscratch, ""); | |
2626 | |
2627 __ sra(Rdividend, 0, Rdividend); | |
2628 __ sdivx(Rdividend, divisor, Rscratch); | |
2629 __ mulx(Rscratch, divisor, Rscratch); | |
2630 __ sub(Rdividend, Rscratch, Rresult); | |
2631 %} | |
2632 | |
2633 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2634 MacroAssembler _masm(&cbuf); | |
2635 | |
2636 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2637 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2638 | |
2639 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2640 %} | |
2641 | |
2642 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2643 MacroAssembler _masm(&cbuf); | |
2644 | |
2645 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2646 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2647 | |
2648 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2649 %} | |
2650 | |
2651 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2652 MacroAssembler _masm(&cbuf); | |
2653 | |
2654 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2655 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2656 | |
2657 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2658 %} | |
2659 | |
2660 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2661 MacroAssembler _masm(&cbuf); | |
2662 | |
2663 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2664 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2665 | |
2666 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2667 %} | |
2668 | |
2669 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2670 MacroAssembler _masm(&cbuf); | |
2671 | |
2672 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2673 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2674 | |
2675 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2676 %} | |
2677 | |
2678 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2679 MacroAssembler _masm(&cbuf); | |
2680 | |
2681 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2682 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2683 | |
2684 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2685 %} | |
2686 | |
2687 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2688 MacroAssembler _masm(&cbuf); | |
2689 | |
2690 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2691 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2692 | |
2693 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2694 %} | |
2695 | |
2696 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2697 MacroAssembler _masm(&cbuf); | |
2698 | |
2699 Register Roop = reg_to_register_object($oop$$reg); | |
2700 Register Rbox = reg_to_register_object($box$$reg); | |
2701 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2702 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2703 | |
2704 assert(Roop != Rscratch, ""); | |
2705 assert(Roop != Rmark, ""); | |
2706 assert(Rbox != Rscratch, ""); | |
2707 assert(Rbox != Rmark, ""); | |
2708 | |
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2709 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2710 %} |
2711 | |
2712 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2713 MacroAssembler _masm(&cbuf); | |
2714 | |
2715 Register Roop = reg_to_register_object($oop$$reg); | |
2716 Register Rbox = reg_to_register_object($box$$reg); | |
2717 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2718 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2719 | |
2720 assert(Roop != Rscratch, ""); | |
2721 assert(Roop != Rmark, ""); | |
2722 assert(Rbox != Rscratch, ""); | |
2723 assert(Rbox != Rmark, ""); | |
2724 | |
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2725 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2726 %} |
2727 | |
2728 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2729 MacroAssembler _masm(&cbuf); | |
2730 Register Rmem = reg_to_register_object($mem$$reg); | |
2731 Register Rold = reg_to_register_object($old$$reg); | |
2732 Register Rnew = reg_to_register_object($new$$reg); | |
2733 | |
2734 // casx_under_lock picks 1 of 3 encodings: | |
2735 // For 32-bit pointers you get a 32-bit CAS | |
2736 // For 64-bit pointers you get a 64-bit CASX | |
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2737 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2738 __ cmp( Rold, Rnew ); |
2739 %} | |
2740 | |
2741 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2742 Register Rmem = reg_to_register_object($mem$$reg); | |
2743 Register Rold = reg_to_register_object($old$$reg); | |
2744 Register Rnew = reg_to_register_object($new$$reg); | |
2745 | |
2746 MacroAssembler _masm(&cbuf); | |
2747 __ mov(Rnew, O7); | |
2748 __ casx(Rmem, Rold, O7); | |
2749 __ cmp( Rold, O7 ); | |
2750 %} | |
2751 | |
2752 // raw int cas, used for compareAndSwap | |
2753 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2754 Register Rmem = reg_to_register_object($mem$$reg); | |
2755 Register Rold = reg_to_register_object($old$$reg); | |
2756 Register Rnew = reg_to_register_object($new$$reg); | |
2757 | |
2758 MacroAssembler _masm(&cbuf); | |
2759 __ mov(Rnew, O7); | |
2760 __ cas(Rmem, Rold, O7); | |
2761 __ cmp( Rold, O7 ); | |
2762 %} | |
2763 | |
2764 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2765 Register Rres = reg_to_register_object($res$$reg); | |
2766 | |
2767 MacroAssembler _masm(&cbuf); | |
2768 __ mov(1, Rres); | |
2769 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2770 %} | |
2771 | |
2772 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2773 Register Rres = reg_to_register_object($res$$reg); | |
2774 | |
2775 MacroAssembler _masm(&cbuf); | |
2776 __ mov(1, Rres); | |
2777 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2778 %} | |
2779 | |
2780 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2781 MacroAssembler _masm(&cbuf); | |
2782 Register Rdst = reg_to_register_object($dst$$reg); | |
2783 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2784 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2785 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2786 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2787 | |
2788 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2789 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2790 %} | |
2791 | |
2792 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
2793 MacroAssembler _masm(&cbuf); | |
2794 Register dest = reg_to_register_object($dst$$reg); | |
2795 Register temp = reg_to_register_object($tmp$$reg); | |
2796 __ set64( $src$$constant, dest, temp ); | |
2797 %} | |
2798 | |
2799 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
2800 // Load a constant replicated "count" times with width "width" | |
2801 int bit_width = $width$$constant * 8; | |
2802 jlong elt_val = $src$$constant; | |
2803 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
2804 jlong val = elt_val; | |
2805 for (int i = 0; i < $count$$constant - 1; i++) { | |
2806 val <<= bit_width; | |
2807 val |= elt_val; | |
2808 } | |
2809 jdouble dval = *(jdouble*)&val; // coerce to double type | |
727 | 2810 MacroAssembler _masm(&cbuf); |
2811 address double_address = __ double_constant(dval); | |
0 | 2812 RelocationHolder rspec = internal_word_Relocation::spec(double_address); |
727 | 2813 AddressLiteral addrlit(double_address, rspec); |
2814 | |
2815 __ sethi(addrlit, $tmp$$Register); | |
732
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2816 // XXX This is a quick fix for 6833573. |
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2817 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
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2818 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
0 | 2819 %} |
2820 | |
2821 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
2822 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
2823 MacroAssembler _masm(&cbuf); | |
2824 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
2825 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
2826 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
2827 | |
2828 Label loop; | |
2829 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
2830 | |
2831 // Loop and clear, walking backwards through the array. | |
2832 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
2833 __ bind(loop); | |
2834 __ deccc(nof_bytes_tmp, 8); | |
2835 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
2836 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
2837 // %%%% this mini-loop must not cross a cache boundary! | |
2838 %} | |
2839 | |
2840 | |
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2841 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2842 Label Ldone, Lloop; |
2843 MacroAssembler _masm(&cbuf); | |
2844 | |
2845 Register str1_reg = reg_to_register_object($str1$$reg); | |
2846 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2847 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2848 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2849 Register result_reg = reg_to_register_object($result$$reg); |
2850 | |
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2851 assert(result_reg != str1_reg && |
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2852 result_reg != str2_reg && |
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2853 result_reg != cnt1_reg && |
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2854 result_reg != cnt2_reg , |
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|
2855 "need different registers"); |
0 | 2856 |
2857 // Compute the minimum of the string lengths(str1_reg) and the | |
2858 // difference of the string lengths (stack) | |
2859 | |
2860 // See if the lengths are different, and calculate min in str1_reg. | |
2861 // Stash diff in O7 in case we need it for a tie-breaker. | |
2862 Label Lskip; | |
986
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2863 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2864 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2865 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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2866 // cnt2 is shorter, so use its count: |
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2867 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2868 __ bind(Lskip); |
2869 | |
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2870 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2871 // Note: limit_reg holds the string length pre-scaled by 2 |
986
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2872 Register limit_reg = cnt1_reg; |
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2873 Register chr2_reg = cnt2_reg; |
0 | 2874 Register chr1_reg = result_reg; |
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2875 // str{12} are the base pointers |
0 | 2876 |
2877 // Is the minimum length zero? | |
2878 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2879 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2880 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2881 | |
2882 // Load first characters | |
986
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2883 __ lduh(str1_reg, 0, chr1_reg); |
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2884 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2885 |
2886 // Compare first characters | |
2887 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2888 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2889 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2890 __ delayed()->nop(); | |
2891 | |
2892 { | |
2893 // Check after comparing first character to see if strings are equivalent | |
2894 Label LSkip2; | |
2895 // Check if the strings start at same location | |
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2896 __ cmp(str1_reg, str2_reg); |
0 | 2897 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2898 __ delayed()->nop(); | |
2899 | |
2900 // Check if the length difference is zero (in O7) | |
2901 __ cmp(G0, O7); | |
2902 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2903 __ delayed()->mov(G0, result_reg); // result is zero | |
2904 | |
2905 // Strings might not be equal | |
2906 __ bind(LSkip2); | |
2907 } | |
2908 | |
2909 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2910 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2911 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2912 | |
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2913 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2914 __ add(str1_reg, limit_reg, str1_reg); |
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2915 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2916 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2917 | |
2918 // Compare the rest of the characters | |
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2919 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2920 __ bind(Lloop); |
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2921 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2922 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2923 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2924 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2925 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2926 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2927 // annul LDUH if branch is not taken to prevent access past end of string | |
2928 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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2929 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2930 |
2931 // If strings are equal up to min length, return the length difference. | |
2932 __ mov(O7, result_reg); | |
2933 | |
2934 // Otherwise, return the difference between the first mismatched chars. | |
2935 __ bind(Ldone); | |
2936 %} | |
2937 | |
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|
2938 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2939 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2940 MacroAssembler _masm(&cbuf); |
2941 | |
2942 Register str1_reg = reg_to_register_object($str1$$reg); | |
2943 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2944 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2945 Register tmp1_reg = O7; |
681 | 2946 Register result_reg = reg_to_register_object($result$$reg); |
2947 | |
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2948 assert(result_reg != str1_reg && |
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2949 result_reg != str2_reg && |
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2950 result_reg != cnt_reg && |
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2951 result_reg != tmp1_reg , |
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2952 "need different registers"); |
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2953 |
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2954 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2955 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2956 __ delayed()->add(G0, 1, result_reg); | |
2957 | |
986
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2958 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
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2959 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2960 |
681 | 2961 //rename registers |
986
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2962 Register limit_reg = cnt_reg; |
681 | 2963 Register chr1_reg = result_reg; |
986
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2964 Register chr2_reg = tmp1_reg; |
681 | 2965 |
2966 //check for alignment and position the pointers to the ends | |
986
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2967 __ or3(str1_reg, str2_reg, chr1_reg); |
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2968 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2969 // notZero means at least one not 4-byte aligned. |
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2970 // We could optimize the case when both arrays are not aligned |
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2971 // but it is not frequent case and it requires additional checks. |
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2972 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2973 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2974 |
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2975 // Compare char[] arrays aligned to 4 bytes. |
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2976 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2977 chr1_reg, chr2_reg, Ldone); |
681 | 2978 __ ba(false,Ldone); |
2979 __ delayed()->add(G0, 1, result_reg); | |
2980 | |
986
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2981 // char by char compare |
681 | 2982 __ bind(Lchar); |
986
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2983 __ add(str1_reg, limit_reg, str1_reg); |
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2984 __ add(str2_reg, limit_reg, str2_reg); |
681 | 2985 __ neg(limit_reg); //negate count |
2986 | |
986
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2987 __ lduh(str1_reg, limit_reg, chr1_reg); |
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2988 // Lchar_loop |
681 | 2989 __ bind(Lchar_loop); |
986
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2990 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 2991 __ cmp(chr1_reg, chr2_reg); |
2992 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
2993 __ delayed()->mov(G0, result_reg); //not equal | |
2994 __ inccc(limit_reg, sizeof(jchar)); | |
2995 // annul LDUH if branch is not taken to prevent access past end of string | |
986
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2996 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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2997 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 2998 |
2999 __ add(G0, 1, result_reg); //equal | |
3000 | |
3001 __ bind(Ldone); | |
3002 %} | |
3003 | |
986
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3004 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3005 Label Lvector, Ldone, Lloop; |
3006 MacroAssembler _masm(&cbuf); | |
3007 | |
3008 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3009 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3010 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
986
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3011 Register tmp2_reg = O7; |
681 | 3012 Register result_reg = reg_to_register_object($result$$reg); |
3013 | |
3014 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3015 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3016 | |
3017 // return true if the same array | |
3018 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3019 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3020 __ delayed()->add(G0, 1, result_reg); // equal |
3021 | |
3022 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3023 __ delayed()->mov(G0, result_reg); // not equal | |
3024 | |
3025 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3026 __ delayed()->mov(G0, result_reg); // not equal | |
3027 | |
3028 //load the lengths of arrays | |
727 | 3029 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3030 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3031 |
3032 // return false if the two arrays are not equal length | |
3033 __ cmp(tmp1_reg, tmp2_reg); | |
3034 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3035 __ delayed()->mov(G0, result_reg); // not equal | |
3036 | |
986
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3037 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
681 | 3038 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3039 | |
3040 // load array addresses | |
3041 __ add(ary1_reg, base_offset, ary1_reg); | |
3042 __ add(ary2_reg, base_offset, ary2_reg); | |
3043 | |
3044 // renaming registers | |
986
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3045 Register chr1_reg = result_reg; // for characters in ary1 |
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3046 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3047 Register limit_reg = tmp1_reg; // length |
3048 | |
3049 // set byte count | |
3050 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
986
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3051 |
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3052 // Compare char[] arrays aligned to 4 bytes. |
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3053 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3054 chr1_reg, chr2_reg, Ldone); |
681 | 3055 __ add(G0, 1, result_reg); // equals |
3056 | |
3057 __ bind(Ldone); | |
3058 %} | |
3059 | |
0 | 3060 enc_class enc_rethrow() %{ |
3061 cbuf.set_inst_mark(); | |
3062 Register temp_reg = G3; | |
727 | 3063 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3064 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3065 MacroAssembler _masm(&cbuf); | |
3066 #ifdef ASSERT | |
3067 __ save_frame(0); | |
727 | 3068 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3069 __ sethi(last_rethrow_addrlit, L1); | |
3070 Address addr(L1, last_rethrow_addrlit.low10()); | |
0 | 3071 __ get_pc(L2); |
3072 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
727 | 3073 __ st_ptr(L2, addr); |
0 | 3074 __ restore(); |
3075 #endif | |
727 | 3076 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3077 __ delayed()->nop(); |
3078 %} | |
3079 | |
3080 enc_class emit_mem_nop() %{ | |
3081 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
3082 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3083 *code = (unsigned int)0xc0839040; | |
3084 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3085 %} | |
3086 | |
3087 enc_class emit_fadd_nop() %{ | |
3088 // Generates the instruction FMOVS f31,f31 | |
3089 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3090 *code = (unsigned int)0xbfa0003f; | |
3091 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3092 %} | |
3093 | |
3094 enc_class emit_br_nop() %{ | |
3095 // Generates the instruction BPN,PN . | |
3096 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3097 *code = (unsigned int)0x00400000; | |
3098 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3099 %} | |
3100 | |
3101 enc_class enc_membar_acquire %{ | |
3102 MacroAssembler _masm(&cbuf); | |
3103 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3104 %} | |
3105 | |
3106 enc_class enc_membar_release %{ | |
3107 MacroAssembler _masm(&cbuf); | |
3108 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3109 %} | |
3110 | |
3111 enc_class enc_membar_volatile %{ | |
3112 MacroAssembler _masm(&cbuf); | |
3113 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3114 %} | |
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3115 |
0 | 3116 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
3117 MacroAssembler _masm(&cbuf); | |
3118 Register src_reg = reg_to_register_object($src$$reg); | |
3119 Register dst_reg = reg_to_register_object($dst$$reg); | |
3120 __ sllx(src_reg, 56, dst_reg); | |
3121 __ srlx(dst_reg, 8, O7); | |
3122 __ or3 (dst_reg, O7, dst_reg); | |
3123 __ srlx(dst_reg, 16, O7); | |
3124 __ or3 (dst_reg, O7, dst_reg); | |
3125 __ srlx(dst_reg, 32, O7); | |
3126 __ or3 (dst_reg, O7, dst_reg); | |
3127 %} | |
3128 | |
3129 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
3130 MacroAssembler _masm(&cbuf); | |
3131 Register src_reg = reg_to_register_object($src$$reg); | |
3132 Register dst_reg = reg_to_register_object($dst$$reg); | |
3133 __ sll(src_reg, 24, dst_reg); | |
3134 __ srl(dst_reg, 8, O7); | |
3135 __ or3(dst_reg, O7, dst_reg); | |
3136 __ srl(dst_reg, 16, O7); | |
3137 __ or3(dst_reg, O7, dst_reg); | |
3138 %} | |
3139 | |
3140 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
3141 MacroAssembler _masm(&cbuf); | |
3142 Register src_reg = reg_to_register_object($src$$reg); | |
3143 Register dst_reg = reg_to_register_object($dst$$reg); | |
3144 __ sllx(src_reg, 48, dst_reg); | |
3145 __ srlx(dst_reg, 16, O7); | |
3146 __ or3 (dst_reg, O7, dst_reg); | |
3147 __ srlx(dst_reg, 32, O7); | |
3148 __ or3 (dst_reg, O7, dst_reg); | |
3149 %} | |
3150 | |
3151 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
3152 MacroAssembler _masm(&cbuf); | |
3153 Register src_reg = reg_to_register_object($src$$reg); | |
3154 Register dst_reg = reg_to_register_object($dst$$reg); | |
3155 __ sllx(src_reg, 32, dst_reg); | |
3156 __ srlx(dst_reg, 32, O7); | |
3157 __ or3 (dst_reg, O7, dst_reg); | |
3158 %} | |
3159 | |
3160 %} | |
3161 | |
3162 //----------FRAME-------------------------------------------------------------- | |
3163 // Definition of frame structure and management information. | |
3164 // | |
3165 // S T A C K L A Y O U T Allocators stack-slot number | |
3166 // | (to get allocators register number | |
3167 // G Owned by | | v add VMRegImpl::stack0) | |
3168 // r CALLER | | | |
3169 // o | +--------+ pad to even-align allocators stack-slot | |
3170 // w V | pad0 | numbers; owned by CALLER | |
3171 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3172 // h ^ | in | 5 | |
3173 // | | args | 4 Holes in incoming args owned by SELF | |
3174 // | | | | 3 | |
3175 // | | +--------+ | |
3176 // V | | old out| Empty on Intel, window on Sparc | |
3177 // | old |preserve| Must be even aligned. | |
3178 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3179 // | | in | 3 area for Intel ret address | |
3180 // Owned by |preserve| Empty on Sparc. | |
3181 // SELF +--------+ | |
3182 // | | pad2 | 2 pad to align old SP | |
3183 // | +--------+ 1 | |
3184 // | | locks | 0 | |
3185 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3186 // | | pad1 | 11 pad to align new SP | |
3187 // | +--------+ | |
3188 // | | | 10 | |
3189 // | | spills | 9 spills | |
3190 // V | | 8 (pad0 slot for callee) | |
3191 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3192 // ^ | out | 7 | |
3193 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3194 // Owned by +--------+ | |
3195 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3196 // | new |preserve| Must be even-aligned. | |
3197 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3198 // | | | | |
3199 // | |
3200 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3201 // known from SELF's arguments and the Java calling convention. | |
3202 // Region 6-7 is determined per call site. | |
3203 // Note 2: If the calling convention leaves holes in the incoming argument | |
3204 // area, those holes are owned by SELF. Holes in the outgoing area | |
3205 // are owned by the CALLEE. Holes should not be nessecary in the | |
3206 // incoming area, as the Java calling convention is completely under | |
3207 // the control of the AD file. Doubles can be sorted and packed to | |
3208 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3209 // varargs C calling conventions. | |
3210 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3211 // even aligned with pad0 as needed. | |
3212 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3213 // region 6-11 is even aligned; it may be padded out more so that | |
3214 // the region from SP to FP meets the minimum stack alignment. | |
3215 | |
3216 frame %{ | |
3217 // What direction does stack grow in (assumed to be same for native & Java) | |
3218 stack_direction(TOWARDS_LOW); | |
3219 | |
3220 // These two registers define part of the calling convention | |
3221 // between compiled code and the interpreter. | |
3222 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
3223 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
3224 | |
3225 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3226 cisc_spilling_operand_name(indOffset); | |
3227 | |
3228 // Number of stack slots consumed by a Monitor enter | |
3229 #ifdef _LP64 | |
3230 sync_stack_slots(2); | |
3231 #else | |
3232 sync_stack_slots(1); | |
3233 #endif | |
3234 | |
3235 // Compiled code's Frame Pointer | |
3236 frame_pointer(R_SP); | |
3237 | |
3238 // Stack alignment requirement | |
3239 stack_alignment(StackAlignmentInBytes); | |
3240 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3241 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3242 | |
3243 // Number of stack slots between incoming argument block and the start of | |
3244 // a new frame. The PROLOG must add this many slots to the stack. The | |
3245 // EPILOG must remove this many slots. | |
3246 in_preserve_stack_slots(0); | |
3247 | |
3248 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3249 // for calls to C. Supports the var-args backing area for register parms. | |
3250 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3251 #ifdef _LP64 | |
3252 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3253 varargs_C_out_slots_killed(12); | |
3254 #else | |
3255 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3256 varargs_C_out_slots_killed( 7); | |
3257 #endif | |
3258 | |
3259 // The after-PROLOG location of the return address. Location of | |
3260 // return address specifies a type (REG or STACK) and a number | |
3261 // representing the register number (i.e. - use a register name) or | |
3262 // stack slot. | |
3263 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3264 | |
3265 // Body of function which returns an OptoRegs array locating | |
3266 // arguments either in registers or in stack slots for calling | |
3267 // java | |
3268 calling_convention %{ | |
3269 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3270 | |
3271 %} | |
3272 | |
3273 // Body of function which returns an OptoRegs array locating | |
3274 // arguments either in registers or in stack slots for callin | |
3275 // C. | |
3276 c_calling_convention %{ | |
3277 // This is obviously always outgoing | |
3278 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3279 %} | |
3280 | |
3281 // Location of native (C/C++) and interpreter return values. This is specified to | |
3282 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3283 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3284 // to and from the register pairs is done by the appropriate call and epilog | |
3285 // opcodes. This simplifies the register allocator. | |
3286 c_return_value %{ | |
3287 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3288 #ifdef _LP64 | |
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3289 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3290 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3291 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3292 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3293 #else // !_LP64 |
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3294 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3295 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3296 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3297 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3298 #endif |
3299 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3300 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3301 %} | |
3302 | |
3303 // Location of compiled Java return values. Same as C | |
3304 return_value %{ | |
3305 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3306 #ifdef _LP64 | |
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3307 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3308 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3309 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3310 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3311 #else // !_LP64 |
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3312 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3313 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3314 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3315 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3316 #endif |
3317 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3318 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3319 %} | |
3320 | |
3321 %} | |
3322 | |
3323 | |
3324 //----------ATTRIBUTES--------------------------------------------------------- | |
3325 //----------Operand Attributes------------------------------------------------- | |
3326 op_attrib op_cost(1); // Required cost attribute | |
3327 | |
3328 //----------Instruction Attributes--------------------------------------------- | |
3329 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3330 ins_attrib ins_size(32); // Required size attribute (in bits) | |
3331 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
3332 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
3333 // non-matching short branch variant of some | |
3334 // long branch? | |
3335 | |
3336 //----------OPERANDS----------------------------------------------------------- | |
3337 // Operand definitions must precede instruction definitions for correct parsing | |
3338 // in the ADLC because operands constitute user defined types which are used in | |
3339 // instruction definitions. | |
3340 | |
3341 //----------Simple Operands---------------------------------------------------- | |
3342 // Immediate Operands | |
3343 // Integer Immediate: 32-bit | |
3344 operand immI() %{ | |
3345 match(ConI); | |
3346 | |
3347 op_cost(0); | |
3348 // formats are generated automatically for constants and base registers | |
3349 format %{ %} | |
3350 interface(CONST_INTER); | |
3351 %} | |
3352 | |
824 | 3353 // Integer Immediate: 8-bit |
3354 operand immI8() %{ | |
3355 predicate(Assembler::is_simm(n->get_int(), 8)); | |
3356 match(ConI); | |
3357 op_cost(0); | |
3358 format %{ %} | |
3359 interface(CONST_INTER); | |
3360 %} | |
3361 | |
0 | 3362 // Integer Immediate: 13-bit |
3363 operand immI13() %{ | |
3364 predicate(Assembler::is_simm13(n->get_int())); | |
3365 match(ConI); | |
3366 op_cost(0); | |
3367 | |
3368 format %{ %} | |
3369 interface(CONST_INTER); | |
3370 %} | |
3371 | |
785 | 3372 // Integer Immediate: 13-bit minus 7 |
3373 operand immI13m7() %{ | |
3374 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3375 match(ConI); | |
3376 op_cost(0); | |
3377 | |
3378 format %{ %} | |
3379 interface(CONST_INTER); | |
3380 %} | |
3381 | |
824 | 3382 // Integer Immediate: 16-bit |
3383 operand immI16() %{ | |
3384 predicate(Assembler::is_simm(n->get_int(), 16)); | |
3385 match(ConI); | |
3386 op_cost(0); | |
3387 format %{ %} | |
3388 interface(CONST_INTER); | |
3389 %} | |
3390 | |
0 | 3391 // Unsigned (positive) Integer Immediate: 13-bit |
3392 operand immU13() %{ | |
3393 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3394 match(ConI); | |
3395 op_cost(0); | |
3396 | |
3397 format %{ %} | |
3398 interface(CONST_INTER); | |
3399 %} | |
3400 | |
3401 // Integer Immediate: 6-bit | |
3402 operand immU6() %{ | |
3403 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3404 match(ConI); | |
3405 op_cost(0); | |
3406 format %{ %} | |
3407 interface(CONST_INTER); | |
3408 %} | |
3409 | |
3410 // Integer Immediate: 11-bit | |
3411 operand immI11() %{ | |
3412 predicate(Assembler::is_simm(n->get_int(),11)); | |
3413 match(ConI); | |
3414 op_cost(0); | |
3415 format %{ %} | |
3416 interface(CONST_INTER); | |
3417 %} | |
3418 | |
3419 // Integer Immediate: 0-bit | |
3420 operand immI0() %{ | |
3421 predicate(n->get_int() == 0); | |
3422 match(ConI); | |
3423 op_cost(0); | |
3424 | |
3425 format %{ %} | |
3426 interface(CONST_INTER); | |
3427 %} | |
3428 | |
3429 // Integer Immediate: the value 10 | |
3430 operand immI10() %{ | |
3431 predicate(n->get_int() == 10); | |
3432 match(ConI); | |
3433 op_cost(0); | |
3434 | |
3435 format %{ %} | |
3436 interface(CONST_INTER); | |
3437 %} | |
3438 | |
3439 // Integer Immediate: the values 0-31 | |
3440 operand immU5() %{ | |
3441 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3442 match(ConI); | |
3443 op_cost(0); | |
3444 | |
3445 format %{ %} | |
3446 interface(CONST_INTER); | |
3447 %} | |
3448 | |
3449 // Integer Immediate: the values 1-31 | |
3450 operand immI_1_31() %{ | |
3451 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3452 match(ConI); | |
3453 op_cost(0); | |
3454 | |
3455 format %{ %} | |
3456 interface(CONST_INTER); | |
3457 %} | |
3458 | |
3459 // Integer Immediate: the values 32-63 | |
3460 operand immI_32_63() %{ | |
3461 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3462 match(ConI); | |
3463 op_cost(0); | |
3464 | |
3465 format %{ %} | |
3466 interface(CONST_INTER); | |
3467 %} | |
3468 | |
785 | 3469 // Immediates for special shifts (sign extend) |
3470 | |
3471 // Integer Immediate: the value 16 | |
3472 operand immI_16() %{ | |
3473 predicate(n->get_int() == 16); | |
3474 match(ConI); | |
3475 op_cost(0); | |
3476 | |
3477 format %{ %} | |
3478 interface(CONST_INTER); | |
3479 %} | |
3480 | |
3481 // Integer Immediate: the value 24 | |
3482 operand immI_24() %{ | |
3483 predicate(n->get_int() == 24); | |
3484 match(ConI); | |
3485 op_cost(0); | |
3486 | |
3487 format %{ %} | |
3488 interface(CONST_INTER); | |
3489 %} | |
3490 | |
0 | 3491 // Integer Immediate: the value 255 |
3492 operand immI_255() %{ | |
3493 predicate( n->get_int() == 255 ); | |
3494 match(ConI); | |
3495 op_cost(0); | |
3496 | |
3497 format %{ %} | |
3498 interface(CONST_INTER); | |
3499 %} | |
3500 | |
785 | 3501 // Integer Immediate: the value 65535 |
3502 operand immI_65535() %{ | |
3503 predicate(n->get_int() == 65535); | |
3504 match(ConI); | |
3505 op_cost(0); | |
3506 | |
3507 format %{ %} | |
3508 interface(CONST_INTER); | |
3509 %} | |
3510 | |
0 | 3511 // Long Immediate: the value FF |
3512 operand immL_FF() %{ | |
3513 predicate( n->get_long() == 0xFFL ); | |
3514 match(ConL); | |
3515 op_cost(0); | |
3516 | |
3517 format %{ %} | |
3518 interface(CONST_INTER); | |
3519 %} | |
3520 | |
3521 // Long Immediate: the value FFFF | |
3522 operand immL_FFFF() %{ | |
3523 predicate( n->get_long() == 0xFFFFL ); | |
3524 match(ConL); | |
3525 op_cost(0); | |
3526 | |
3527 format %{ %} | |
3528 interface(CONST_INTER); | |
3529 %} | |
3530 | |
3531 // Pointer Immediate: 32 or 64-bit | |
3532 operand immP() %{ | |
3533 match(ConP); | |
3534 | |
3535 op_cost(5); | |
3536 // formats are generated automatically for constants and base registers | |
3537 format %{ %} | |
3538 interface(CONST_INTER); | |
3539 %} | |
3540 | |
3541 operand immP13() %{ | |
3542 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3543 match(ConP); | |
3544 op_cost(0); | |
3545 | |
3546 format %{ %} | |
3547 interface(CONST_INTER); | |
3548 %} | |
3549 | |
3550 operand immP0() %{ | |
3551 predicate(n->get_ptr() == 0); | |
3552 match(ConP); | |
3553 op_cost(0); | |
3554 | |
3555 format %{ %} | |
3556 interface(CONST_INTER); | |
3557 %} | |
3558 | |
3559 operand immP_poll() %{ | |
3560 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3561 match(ConP); | |
3562 | |
3563 // formats are generated automatically for constants and base registers | |
3564 format %{ %} | |
3565 interface(CONST_INTER); | |
3566 %} | |
3567 | |
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3568 // Pointer Immediate |
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3569 operand immN() |
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3570 %{ |
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3571 match(ConN); |
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3572 |
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3573 op_cost(10); |
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3574 format %{ %} |
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3575 interface(CONST_INTER); |
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3576 %} |
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3577 |
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3578 // NULL Pointer Immediate |
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3579 operand immN0() |
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3580 %{ |
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3581 predicate(n->get_narrowcon() == 0); |
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3582 match(ConN); |
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3583 |
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3584 op_cost(0); |
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3585 format %{ %} |
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3586 interface(CONST_INTER); |
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3587 %} |
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3588 |
0 | 3589 operand immL() %{ |
3590 match(ConL); | |
3591 op_cost(40); | |
3592 // formats are generated automatically for constants and base registers | |
3593 format %{ %} | |
3594 interface(CONST_INTER); | |
3595 %} | |
3596 | |
3597 operand immL0() %{ | |
3598 predicate(n->get_long() == 0L); | |
3599 match(ConL); | |
3600 op_cost(0); | |
3601 // formats are generated automatically for constants and base registers | |
3602 format %{ %} | |
3603 interface(CONST_INTER); | |
3604 %} | |
3605 | |
3606 // Long Immediate: 13-bit | |
3607 operand immL13() %{ | |
3608 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3609 match(ConL); | |
3610 op_cost(0); | |
3611 | |
3612 format %{ %} | |
3613 interface(CONST_INTER); | |
3614 %} | |
3615 | |
785 | 3616 // Long Immediate: 13-bit minus 7 |
3617 operand immL13m7() %{ | |
3618 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3619 match(ConL); | |
3620 op_cost(0); | |
3621 | |
3622 format %{ %} | |
3623 interface(CONST_INTER); | |
3624 %} | |
3625 | |
0 | 3626 // Long Immediate: low 32-bit mask |
3627 operand immL_32bits() %{ | |
3628 predicate(n->get_long() == 0xFFFFFFFFL); | |
3629 match(ConL); | |
3630 op_cost(0); | |
3631 | |
3632 format %{ %} | |
3633 interface(CONST_INTER); | |
3634 %} | |
3635 | |
3636 // Double Immediate | |
3637 operand immD() %{ | |
3638 match(ConD); | |
3639 | |
3640 op_cost(40); | |
3641 format %{ %} | |
3642 interface(CONST_INTER); | |
3643 %} | |
3644 | |
3645 operand immD0() %{ | |
3646 #ifdef _LP64 | |
3647 // on 64-bit architectures this comparision is faster | |
3648 predicate(jlong_cast(n->getd()) == 0); | |
3649 #else | |
3650 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3651 #endif | |
3652 match(ConD); | |
3653 | |
3654 op_cost(0); | |
3655 format %{ %} | |
3656 interface(CONST_INTER); | |
3657 %} | |
3658 | |
3659 // Float Immediate | |
3660 operand immF() %{ | |
3661 match(ConF); | |
3662 | |
3663 op_cost(20); | |
3664 format %{ %} | |
3665 interface(CONST_INTER); | |
3666 %} | |
3667 | |
3668 // Float Immediate: 0 | |
3669 operand immF0() %{ | |
3670 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3671 match(ConF); | |
3672 | |
3673 op_cost(0); | |
3674 format %{ %} | |
3675 interface(CONST_INTER); | |
3676 %} | |
3677 | |
3678 // Integer Register Operands | |
3679 // Integer Register | |
3680 operand iRegI() %{ | |
3681 constraint(ALLOC_IN_RC(int_reg)); | |
3682 match(RegI); | |
3683 | |
3684 match(notemp_iRegI); | |
3685 match(g1RegI); | |
3686 match(o0RegI); | |
3687 match(iRegIsafe); | |
3688 | |
3689 format %{ %} | |
3690 interface(REG_INTER); | |
3691 %} | |
3692 | |
3693 operand notemp_iRegI() %{ | |
3694 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3695 match(RegI); | |
3696 | |
3697 match(o0RegI); | |
3698 | |
3699 format %{ %} | |
3700 interface(REG_INTER); | |
3701 %} | |
3702 | |
3703 operand o0RegI() %{ | |
3704 constraint(ALLOC_IN_RC(o0_regI)); | |
3705 match(iRegI); | |
3706 | |
3707 format %{ %} | |
3708 interface(REG_INTER); | |
3709 %} | |
3710 | |
3711 // Pointer Register | |
3712 operand iRegP() %{ | |
3713 constraint(ALLOC_IN_RC(ptr_reg)); | |
3714 match(RegP); | |
3715 | |
3716 match(lock_ptr_RegP); | |
3717 match(g1RegP); | |
3718 match(g2RegP); | |
3719 match(g3RegP); | |
3720 match(g4RegP); | |
3721 match(i0RegP); | |
3722 match(o0RegP); | |
3723 match(o1RegP); | |
3724 match(l7RegP); | |
3725 | |
3726 format %{ %} | |
3727 interface(REG_INTER); | |
3728 %} | |
3729 | |
3730 operand sp_ptr_RegP() %{ | |
3731 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3732 match(RegP); | |
3733 match(iRegP); | |
3734 | |
3735 format %{ %} | |
3736 interface(REG_INTER); | |
3737 %} | |
3738 | |
3739 operand lock_ptr_RegP() %{ | |
3740 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3741 match(RegP); | |
3742 match(i0RegP); | |
3743 match(o0RegP); | |
3744 match(o1RegP); | |
3745 match(l7RegP); | |
3746 | |
3747 format %{ %} | |
3748 interface(REG_INTER); | |
3749 %} | |
3750 | |
3751 operand g1RegP() %{ | |
3752 constraint(ALLOC_IN_RC(g1_regP)); | |
3753 match(iRegP); | |
3754 | |
3755 format %{ %} | |
3756 interface(REG_INTER); | |
3757 %} | |
3758 | |
3759 operand g2RegP() %{ | |
3760 constraint(ALLOC_IN_RC(g2_regP)); | |
3761 match(iRegP); | |
3762 | |
3763 format %{ %} | |
3764 interface(REG_INTER); | |
3765 %} | |
3766 | |
3767 operand g3RegP() %{ | |
3768 constraint(ALLOC_IN_RC(g3_regP)); | |
3769 match(iRegP); | |
3770 | |
3771 format %{ %} | |
3772 interface(REG_INTER); | |
3773 %} | |
3774 | |
3775 operand g1RegI() %{ | |
3776 constraint(ALLOC_IN_RC(g1_regI)); | |
3777 match(iRegI); | |
3778 | |
3779 format %{ %} | |
3780 interface(REG_INTER); | |
3781 %} | |
3782 | |
3783 operand g3RegI() %{ | |
3784 constraint(ALLOC_IN_RC(g3_regI)); | |
3785 match(iRegI); | |
3786 | |
3787 format %{ %} | |
3788 interface(REG_INTER); | |
3789 %} | |
3790 | |
3791 operand g4RegI() %{ | |
3792 constraint(ALLOC_IN_RC(g4_regI)); | |
3793 match(iRegI); | |
3794 | |
3795 format %{ %} | |
3796 interface(REG_INTER); | |
3797 %} | |
3798 | |
3799 operand g4RegP() %{ | |
3800 constraint(ALLOC_IN_RC(g4_regP)); | |
3801 match(iRegP); | |
3802 | |
3803 format %{ %} | |
3804 interface(REG_INTER); | |
3805 %} | |
3806 | |
3807 operand i0RegP() %{ | |
3808 constraint(ALLOC_IN_RC(i0_regP)); | |
3809 match(iRegP); | |
3810 | |
3811 format %{ %} | |
3812 interface(REG_INTER); | |
3813 %} | |
3814 | |
3815 operand o0RegP() %{ | |
3816 constraint(ALLOC_IN_RC(o0_regP)); | |
3817 match(iRegP); | |
3818 | |
3819 format %{ %} | |
3820 interface(REG_INTER); | |
3821 %} | |
3822 | |
3823 operand o1RegP() %{ | |
3824 constraint(ALLOC_IN_RC(o1_regP)); | |
3825 match(iRegP); | |
3826 | |
3827 format %{ %} | |
3828 interface(REG_INTER); | |
3829 %} | |
3830 | |
3831 operand o2RegP() %{ | |
3832 constraint(ALLOC_IN_RC(o2_regP)); | |
3833 match(iRegP); | |
3834 | |
3835 format %{ %} | |
3836 interface(REG_INTER); | |
3837 %} | |
3838 | |
3839 operand o7RegP() %{ | |
3840 constraint(ALLOC_IN_RC(o7_regP)); | |
3841 match(iRegP); | |
3842 | |
3843 format %{ %} | |
3844 interface(REG_INTER); | |
3845 %} | |
3846 | |
3847 operand l7RegP() %{ | |
3848 constraint(ALLOC_IN_RC(l7_regP)); | |
3849 match(iRegP); | |
3850 | |
3851 format %{ %} | |
3852 interface(REG_INTER); | |
3853 %} | |
3854 | |
3855 operand o7RegI() %{ | |
3856 constraint(ALLOC_IN_RC(o7_regI)); | |
3857 match(iRegI); | |
3858 | |
3859 format %{ %} | |
3860 interface(REG_INTER); | |
3861 %} | |
3862 | |
113
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3863 operand iRegN() %{ |
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3864 constraint(ALLOC_IN_RC(int_reg)); |
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3865 match(RegN); |
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3866 |
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3867 format %{ %} |
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3868 interface(REG_INTER); |
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3869 %} |
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3870 |
0 | 3871 // Long Register |
3872 operand iRegL() %{ | |
3873 constraint(ALLOC_IN_RC(long_reg)); | |
3874 match(RegL); | |
3875 | |
3876 format %{ %} | |
3877 interface(REG_INTER); | |
3878 %} | |
3879 | |
3880 operand o2RegL() %{ | |
3881 constraint(ALLOC_IN_RC(o2_regL)); | |
3882 match(iRegL); | |
3883 | |
3884 format %{ %} | |
3885 interface(REG_INTER); | |
3886 %} | |
3887 | |
3888 operand o7RegL() %{ | |
3889 constraint(ALLOC_IN_RC(o7_regL)); | |
3890 match(iRegL); | |
3891 | |
3892 format %{ %} | |
3893 interface(REG_INTER); | |
3894 %} | |
3895 | |
3896 operand g1RegL() %{ | |
3897 constraint(ALLOC_IN_RC(g1_regL)); | |
3898 match(iRegL); | |
3899 | |
3900 format %{ %} | |
3901 interface(REG_INTER); | |
3902 %} | |
3903 | |
420
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3904 operand g3RegL() %{ |
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3905 constraint(ALLOC_IN_RC(g3_regL)); |
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3906 match(iRegL); |
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3907 |
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3908 format %{ %} |
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3909 interface(REG_INTER); |
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3910 %} |
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3911 |
0 | 3912 // Int Register safe |
3913 // This is 64bit safe | |
3914 operand iRegIsafe() %{ | |
3915 constraint(ALLOC_IN_RC(long_reg)); | |
3916 | |
3917 match(iRegI); | |
3918 | |
3919 format %{ %} | |
3920 interface(REG_INTER); | |
3921 %} | |
3922 | |
3923 // Condition Code Flag Register | |
3924 operand flagsReg() %{ | |
3925 constraint(ALLOC_IN_RC(int_flags)); | |
3926 match(RegFlags); | |
3927 | |
3928 format %{ "ccr" %} // both ICC and XCC | |
3929 interface(REG_INTER); | |
3930 %} | |
3931 | |
3932 // Condition Code Register, unsigned comparisons. | |
3933 operand flagsRegU() %{ | |
3934 constraint(ALLOC_IN_RC(int_flags)); | |
3935 match(RegFlags); | |
3936 | |
3937 format %{ "icc_U" %} | |
3938 interface(REG_INTER); | |
3939 %} | |
3940 | |
3941 // Condition Code Register, pointer comparisons. | |
3942 operand flagsRegP() %{ | |
3943 constraint(ALLOC_IN_RC(int_flags)); | |
3944 match(RegFlags); | |
3945 | |
3946 #ifdef _LP64 | |
3947 format %{ "xcc_P" %} | |
3948 #else | |
3949 format %{ "icc_P" %} | |
3950 #endif | |
3951 interface(REG_INTER); | |
3952 %} | |
3953 | |
3954 // Condition Code Register, long comparisons. | |
3955 operand flagsRegL() %{ | |
3956 constraint(ALLOC_IN_RC(int_flags)); | |
3957 match(RegFlags); | |
3958 | |
3959 format %{ "xcc_L" %} | |
3960 interface(REG_INTER); | |
3961 %} | |
3962 | |
3963 // Condition Code Register, floating comparisons, unordered same as "less". | |
3964 operand flagsRegF() %{ | |
3965 constraint(ALLOC_IN_RC(float_flags)); | |
3966 match(RegFlags); | |
3967 match(flagsRegF0); | |
3968 | |
3969 format %{ %} | |
3970 interface(REG_INTER); | |
3971 %} | |
3972 | |
3973 operand flagsRegF0() %{ | |
3974 constraint(ALLOC_IN_RC(float_flag0)); | |
3975 match(RegFlags); | |
3976 | |
3977 format %{ %} | |
3978 interface(REG_INTER); | |
3979 %} | |
3980 | |
3981 | |
3982 // Condition Code Flag Register used by long compare | |
3983 operand flagsReg_long_LTGE() %{ | |
3984 constraint(ALLOC_IN_RC(int_flags)); | |
3985 match(RegFlags); | |
3986 format %{ "icc_LTGE" %} | |
3987 interface(REG_INTER); | |
3988 %} | |
3989 operand flagsReg_long_EQNE() %{ | |
3990 constraint(ALLOC_IN_RC(int_flags)); | |
3991 match(RegFlags); | |
3992 format %{ "icc_EQNE" %} | |
3993 interface(REG_INTER); | |
3994 %} | |
3995 operand flagsReg_long_LEGT() %{ | |
3996 constraint(ALLOC_IN_RC(int_flags)); | |
3997 match(RegFlags); | |
3998 format %{ "icc_LEGT" %} | |
3999 interface(REG_INTER); | |
4000 %} | |
4001 | |
4002 | |
4003 operand regD() %{ | |
4004 constraint(ALLOC_IN_RC(dflt_reg)); | |
4005 match(RegD); | |
4006 | |
551 | 4007 match(regD_low); |
4008 | |
0 | 4009 format %{ %} |
4010 interface(REG_INTER); | |
4011 %} | |
4012 | |
4013 operand regF() %{ | |
4014 constraint(ALLOC_IN_RC(sflt_reg)); | |
4015 match(RegF); | |
4016 | |
4017 format %{ %} | |
4018 interface(REG_INTER); | |
4019 %} | |
4020 | |
4021 operand regD_low() %{ | |
4022 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4023 match(regD); |
0 | 4024 |
4025 format %{ %} | |
4026 interface(REG_INTER); | |
4027 %} | |
4028 | |
4029 // Special Registers | |
4030 | |
4031 // Method Register | |
4032 operand inline_cache_regP(iRegP reg) %{ | |
4033 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4034 match(reg); | |
4035 format %{ %} | |
4036 interface(REG_INTER); | |
4037 %} | |
4038 | |
4039 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4040 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4041 match(reg); | |
4042 format %{ %} | |
4043 interface(REG_INTER); | |
4044 %} | |
4045 | |
4046 | |
4047 //----------Complex Operands--------------------------------------------------- | |
4048 // Indirect Memory Reference | |
4049 operand indirect(sp_ptr_RegP reg) %{ | |
4050 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4051 match(reg); | |
4052 | |
4053 op_cost(100); | |
4054 format %{ "[$reg]" %} | |
4055 interface(MEMORY_INTER) %{ | |
4056 base($reg); | |
4057 index(0x0); | |
4058 scale(0x0); | |
4059 disp(0x0); | |
4060 %} | |
4061 %} | |
4062 | |
785 | 4063 // Indirect with simm13 Offset |
0 | 4064 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4065 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4066 match(AddP reg offset); | |
4067 | |
4068 op_cost(100); | |
4069 format %{ "[$reg + $offset]" %} | |
4070 interface(MEMORY_INTER) %{ | |
4071 base($reg); | |
4072 index(0x0); | |
4073 scale(0x0); | |
4074 disp($offset); | |
4075 %} | |
4076 %} | |
4077 | |
785 | 4078 // Indirect with simm13 Offset minus 7 |
4079 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4080 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4081 match(AddP reg offset); | |
4082 | |
4083 op_cost(100); | |
4084 format %{ "[$reg + $offset]" %} | |
4085 interface(MEMORY_INTER) %{ | |
4086 base($reg); | |
4087 index(0x0); | |
4088 scale(0x0); | |
4089 disp($offset); | |
4090 %} | |
4091 %} | |
4092 | |
0 | 4093 // Note: Intel has a swapped version also, like this: |
4094 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4095 // constraint(ALLOC_IN_RC(int_reg)); | |
4096 // match(AddP offset reg); | |
4097 // | |
4098 // op_cost(100); | |
4099 // format %{ "[$reg + $offset]" %} | |
4100 // interface(MEMORY_INTER) %{ | |
4101 // base($reg); | |
4102 // index(0x0); | |
4103 // scale(0x0); | |
4104 // disp($offset); | |
4105 // %} | |
4106 //%} | |
4107 //// However, it doesn't make sense for SPARC, since | |
4108 // we have no particularly good way to embed oops in | |
4109 // single instructions. | |
4110 | |
4111 // Indirect with Register Index | |
4112 operand indIndex(iRegP addr, iRegX index) %{ | |
4113 constraint(ALLOC_IN_RC(ptr_reg)); | |
4114 match(AddP addr index); | |
4115 | |
4116 op_cost(100); | |
4117 format %{ "[$addr + $index]" %} | |
4118 interface(MEMORY_INTER) %{ | |
4119 base($addr); | |
4120 index($index); | |
4121 scale(0x0); | |
4122 disp(0x0); | |
4123 %} | |
4124 %} | |
4125 | |
4126 //----------Special Memory Operands-------------------------------------------- | |
4127 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4128 // values on the stack where a match requires a value to | |
4129 // flow through memory. | |
4130 operand stackSlotI(sRegI reg) %{ | |
4131 constraint(ALLOC_IN_RC(stack_slots)); | |
4132 op_cost(100); | |
4133 //match(RegI); | |
4134 format %{ "[$reg]" %} | |
4135 interface(MEMORY_INTER) %{ | |
4136 base(0xE); // R_SP | |
4137 index(0x0); | |
4138 scale(0x0); | |
4139 disp($reg); // Stack Offset | |
4140 %} | |
4141 %} | |
4142 | |
4143 operand stackSlotP(sRegP reg) %{ | |
4144 constraint(ALLOC_IN_RC(stack_slots)); | |
4145 op_cost(100); | |
4146 //match(RegP); | |
4147 format %{ "[$reg]" %} | |
4148 interface(MEMORY_INTER) %{ | |
4149 base(0xE); // R_SP | |
4150 index(0x0); | |
4151 scale(0x0); | |
4152 disp($reg); // Stack Offset | |
4153 %} | |
4154 %} | |
4155 | |
4156 operand stackSlotF(sRegF reg) %{ | |
4157 constraint(ALLOC_IN_RC(stack_slots)); | |
4158 op_cost(100); | |
4159 //match(RegF); | |
4160 format %{ "[$reg]" %} | |
4161 interface(MEMORY_INTER) %{ | |
4162 base(0xE); // R_SP | |
4163 index(0x0); | |
4164 scale(0x0); | |
4165 disp($reg); // Stack Offset | |
4166 %} | |
4167 %} | |
4168 operand stackSlotD(sRegD reg) %{ | |
4169 constraint(ALLOC_IN_RC(stack_slots)); | |
4170 op_cost(100); | |
4171 //match(RegD); | |
4172 format %{ "[$reg]" %} | |
4173 interface(MEMORY_INTER) %{ | |
4174 base(0xE); // R_SP | |
4175 index(0x0); | |
4176 scale(0x0); | |
4177 disp($reg); // Stack Offset | |
4178 %} | |
4179 %} | |
4180 operand stackSlotL(sRegL reg) %{ | |
4181 constraint(ALLOC_IN_RC(stack_slots)); | |
4182 op_cost(100); | |
4183 //match(RegL); | |
4184 format %{ "[$reg]" %} | |
4185 interface(MEMORY_INTER) %{ | |
4186 base(0xE); // R_SP | |
4187 index(0x0); | |
4188 scale(0x0); | |
4189 disp($reg); // Stack Offset | |
4190 %} | |
4191 %} | |
4192 | |
4193 // Operands for expressing Control Flow | |
4194 // NOTE: Label is a predefined operand which should not be redefined in | |
4195 // the AD file. It is generically handled within the ADLC. | |
4196 | |
4197 //----------Conditional Branch Operands---------------------------------------- | |
4198 // Comparison Op - This is the operation of the comparison, and is limited to | |
4199 // the following set of codes: | |
4200 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4201 // | |
4202 // Other attributes of the comparison, such as unsignedness, are specified | |
4203 // by the comparison instruction that sets a condition code flags register. | |
4204 // That result is represented by a flags operand whose subtype is appropriate | |
4205 // to the unsignedness (etc.) of the comparison. | |
4206 // | |
4207 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4208 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4209 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4210 | |
4211 operand cmpOp() %{ | |
4212 match(Bool); | |
4213 | |
4214 format %{ "" %} | |
4215 interface(COND_INTER) %{ | |
4216 equal(0x1); | |
4217 not_equal(0x9); | |
4218 less(0x3); | |
4219 greater_equal(0xB); | |
4220 less_equal(0x2); | |
4221 greater(0xA); | |
4222 %} | |
4223 %} | |
4224 | |
4225 // Comparison Op, unsigned | |
4226 operand cmpOpU() %{ | |
4227 match(Bool); | |
4228 | |
4229 format %{ "u" %} | |
4230 interface(COND_INTER) %{ | |
4231 equal(0x1); | |
4232 not_equal(0x9); | |
4233 less(0x5); | |
4234 greater_equal(0xD); | |
4235 less_equal(0x4); | |
4236 greater(0xC); | |
4237 %} | |
4238 %} | |
4239 | |
4240 // Comparison Op, pointer (same as unsigned) | |
4241 operand cmpOpP() %{ | |
4242 match(Bool); | |
4243 | |
4244 format %{ "p" %} | |
4245 interface(COND_INTER) %{ | |
4246 equal(0x1); | |
4247 not_equal(0x9); | |
4248 less(0x5); | |
4249 greater_equal(0xD); | |
4250 less_equal(0x4); | |
4251 greater(0xC); | |
4252 %} | |
4253 %} | |
4254 | |
4255 // Comparison Op, branch-register encoding | |
4256 operand cmpOp_reg() %{ | |
4257 match(Bool); | |
4258 | |
4259 format %{ "" %} | |
4260 interface(COND_INTER) %{ | |
4261 equal (0x1); | |
4262 not_equal (0x5); | |
4263 less (0x3); | |
4264 greater_equal(0x7); | |
4265 less_equal (0x2); | |
4266 greater (0x6); | |
4267 %} | |
4268 %} | |
4269 | |
4270 // Comparison Code, floating, unordered same as less | |
4271 operand cmpOpF() %{ | |
4272 match(Bool); | |
4273 | |
4274 format %{ "fl" %} | |
4275 interface(COND_INTER) %{ | |
4276 equal(0x9); | |
4277 not_equal(0x1); | |
4278 less(0x3); | |
4279 greater_equal(0xB); | |
4280 less_equal(0xE); | |
4281 greater(0x6); | |
4282 %} | |
4283 %} | |
4284 | |
4285 // Used by long compare | |
4286 operand cmpOp_commute() %{ | |
4287 match(Bool); | |
4288 | |
4289 format %{ "" %} | |
4290 interface(COND_INTER) %{ | |
4291 equal(0x1); | |
4292 not_equal(0x9); | |
4293 less(0xA); | |
4294 greater_equal(0x2); | |
4295 less_equal(0xB); | |
4296 greater(0x3); | |
4297 %} | |
4298 %} | |
4299 | |
4300 //----------OPERAND CLASSES---------------------------------------------------- | |
4301 // Operand Classes are groups of operands that are used to simplify | |
605 | 4302 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4303 // instructions for every form of operand when the instruction accepts |
4304 // multiple operand types with the same basic encoding and format. The classic | |
4305 // case of this is memory operands. | |
4306 // Indirect is not included since its use is limited to Compare & Swap | |
4307 opclass memory( indirect, indOffset13, indIndex ); | |
4308 | |
4309 //----------PIPELINE----------------------------------------------------------- | |
4310 pipeline %{ | |
4311 | |
4312 //----------ATTRIBUTES--------------------------------------------------------- | |
4313 attributes %{ | |
4314 fixed_size_instructions; // Fixed size instructions | |
4315 branch_has_delay_slot; // Branch has delay slot following | |
4316 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4317 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4318 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4319 instruction_fetch_units = 1; // of 16 bytes | |
4320 | |
4321 // List of nop instructions | |
4322 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4323 %} | |
4324 | |
4325 //----------RESOURCES---------------------------------------------------------- | |
4326 // Resources are the functional units available to the machine | |
4327 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4328 | |
4329 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4330 // Pipeline Description specifies the stages in the machine's pipeline | |
4331 | |
4332 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4333 | |
4334 //----------PIPELINE CLASSES--------------------------------------------------- | |
4335 // Pipeline Classes describe the stages in which input and output are | |
4336 // referenced by the hardware pipeline. | |
4337 | |
4338 // Integer ALU reg-reg operation | |
4339 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4340 single_instruction; | |
4341 dst : E(write); | |
4342 src1 : R(read); | |
4343 src2 : R(read); | |
4344 IALU : R; | |
4345 %} | |
4346 | |
4347 // Integer ALU reg-reg long operation | |
4348 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4349 instruction_count(2); | |
4350 dst : E(write); | |
4351 src1 : R(read); | |
4352 src2 : R(read); | |
4353 IALU : R; | |
4354 IALU : R; | |
4355 %} | |
4356 | |
4357 // Integer ALU reg-reg long dependent operation | |
4358 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4359 instruction_count(1); multiple_bundles; | |
4360 dst : E(write); | |
4361 src1 : R(read); | |
4362 src2 : R(read); | |
4363 cr : E(write); | |
4364 IALU : R(2); | |
4365 %} | |
4366 | |
4367 // Integer ALU reg-imm operaion | |
4368 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4369 single_instruction; | |
4370 dst : E(write); | |
4371 src1 : R(read); | |
4372 IALU : R; | |
4373 %} | |
4374 | |
4375 // Integer ALU reg-reg operation with condition code | |
4376 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4377 single_instruction; | |
4378 dst : E(write); | |
4379 cr : E(write); | |
4380 src1 : R(read); | |
4381 src2 : R(read); | |
4382 IALU : R; | |
4383 %} | |
4384 | |
4385 // Integer ALU reg-imm operation with condition code | |
4386 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4387 single_instruction; | |
4388 dst : E(write); | |
4389 cr : E(write); | |
4390 src1 : R(read); | |
4391 IALU : R; | |
4392 %} | |
4393 | |
4394 // Integer ALU zero-reg operation | |
4395 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4396 single_instruction; | |
4397 dst : E(write); | |
4398 src2 : R(read); | |
4399 IALU : R; | |
4400 %} | |
4401 | |
4402 // Integer ALU zero-reg operation with condition code only | |
4403 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4404 single_instruction; | |
4405 cr : E(write); | |
4406 src : R(read); | |
4407 IALU : R; | |
4408 %} | |
4409 | |
4410 // Integer ALU reg-reg operation with condition code only | |
4411 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4412 single_instruction; | |
4413 cr : E(write); | |
4414 src1 : R(read); | |
4415 src2 : R(read); | |
4416 IALU : R; | |
4417 %} | |
4418 | |
4419 // Integer ALU reg-imm operation with condition code only | |
4420 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4421 single_instruction; | |
4422 cr : E(write); | |
4423 src1 : R(read); | |
4424 IALU : R; | |
4425 %} | |
4426 | |
4427 // Integer ALU reg-reg-zero operation with condition code only | |
4428 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4429 single_instruction; | |
4430 cr : E(write); | |
4431 src1 : R(read); | |
4432 src2 : R(read); | |
4433 IALU : R; | |
4434 %} | |
4435 | |
4436 // Integer ALU reg-imm-zero operation with condition code only | |
4437 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4438 single_instruction; | |
4439 cr : E(write); | |
4440 src1 : R(read); | |
4441 IALU : R; | |
4442 %} | |
4443 | |
4444 // Integer ALU reg-reg operation with condition code, src1 modified | |
4445 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4446 single_instruction; | |
4447 cr : E(write); | |
4448 src1 : E(write); | |
4449 src1 : R(read); | |
4450 src2 : R(read); | |
4451 IALU : R; | |
4452 %} | |
4453 | |
4454 // Integer ALU reg-imm operation with condition code, src1 modified | |
4455 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4456 single_instruction; | |
4457 cr : E(write); | |
4458 src1 : E(write); | |
4459 src1 : R(read); | |
4460 IALU : R; | |
4461 %} | |
4462 | |
4463 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4464 multiple_bundles; | |
4465 dst : E(write)+4; | |
4466 cr : E(write); | |
4467 src1 : R(read); | |
4468 src2 : R(read); | |
4469 IALU : R(3); | |
4470 BR : R(2); | |
4471 %} | |
4472 | |
4473 // Integer ALU operation | |
4474 pipe_class ialu_none(iRegI dst) %{ | |
4475 single_instruction; | |
4476 dst : E(write); | |
4477 IALU : R; | |
4478 %} | |
4479 | |
4480 // Integer ALU reg operation | |
4481 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4482 single_instruction; may_have_no_code; | |
4483 dst : E(write); | |
4484 src : R(read); | |
4485 IALU : R; | |
4486 %} | |
4487 | |
4488 // Integer ALU reg conditional operation | |
4489 // This instruction has a 1 cycle stall, and cannot execute | |
4490 // in the same cycle as the instruction setting the condition | |
4491 // code. We kludge this by pretending to read the condition code | |
4492 // 1 cycle earlier, and by marking the functional units as busy | |
4493 // for 2 cycles with the result available 1 cycle later than | |
4494 // is really the case. | |
4495 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4496 single_instruction; | |
4497 op2_out : C(write); | |
4498 op1 : R(read); | |
4499 cr : R(read); // This is really E, with a 1 cycle stall | |
4500 BR : R(2); | |
4501 MS : R(2); | |
4502 %} | |
4503 | |
4504 #ifdef _LP64 | |
4505 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4506 instruction_count(1); multiple_bundles; | |
4507 dst : C(write)+1; | |
4508 src : R(read)+1; | |
4509 IALU : R(1); | |
4510 BR : E(2); | |
4511 MS : E(2); | |
4512 %} | |
4513 #endif | |
4514 | |
4515 // Integer ALU reg operation | |
4516 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4517 single_instruction; may_have_no_code; | |
4518 dst : E(write); | |
4519 src : R(read); | |
4520 IALU : R; | |
4521 %} | |
4522 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4523 single_instruction; may_have_no_code; | |
4524 dst : E(write); | |
4525 src : R(read); | |
4526 IALU : R; | |
4527 %} | |
4528 | |
4529 // Two integer ALU reg operations | |
4530 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4531 instruction_count(2); | |
4532 dst : E(write); | |
4533 src : R(read); | |
4534 A0 : R; | |
4535 A1 : R; | |
4536 %} | |
4537 | |
4538 // Two integer ALU reg operations | |
4539 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4540 instruction_count(2); may_have_no_code; | |
4541 dst : E(write); | |
4542 src : R(read); | |
4543 A0 : R; | |
4544 A1 : R; | |
4545 %} | |
4546 | |
4547 // Integer ALU imm operation | |
4548 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4549 single_instruction; | |
4550 dst : E(write); | |
4551 IALU : R; | |
4552 %} | |
4553 | |
4554 // Integer ALU reg-reg with carry operation | |
4555 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4556 single_instruction; | |
4557 dst : E(write); | |
4558 src1 : R(read); | |
4559 src2 : R(read); | |
4560 IALU : R; | |
4561 %} | |
4562 | |
4563 // Integer ALU cc operation | |
4564 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4565 single_instruction; | |
4566 dst : E(write); | |
4567 cc : R(read); | |
4568 IALU : R; | |
4569 %} | |
4570 | |
4571 // Integer ALU cc / second IALU operation | |
4572 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4573 instruction_count(1); multiple_bundles; | |
4574 dst : E(write)+1; | |
4575 src : R(read); | |
4576 IALU : R; | |
4577 %} | |
4578 | |
4579 // Integer ALU cc / second IALU operation | |
4580 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4581 instruction_count(1); multiple_bundles; | |
4582 dst : E(write)+1; | |
4583 p : R(read); | |
4584 q : R(read); | |
4585 IALU : R; | |
4586 %} | |
4587 | |
4588 // Integer ALU hi-lo-reg operation | |
4589 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4590 instruction_count(1); multiple_bundles; | |
4591 dst : E(write)+1; | |
4592 IALU : R(2); | |
4593 %} | |
4594 | |
4595 // Float ALU hi-lo-reg operation (with temp) | |
4596 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4597 instruction_count(1); multiple_bundles; | |
4598 dst : E(write)+1; | |
4599 IALU : R(2); | |
4600 %} | |
4601 | |
4602 // Long Constant | |
4603 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4604 instruction_count(2); multiple_bundles; | |
4605 dst : E(write)+1; | |
4606 IALU : R(2); | |
4607 IALU : R(2); | |
4608 %} | |
4609 | |
4610 // Pointer Constant | |
4611 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4612 instruction_count(0); multiple_bundles; | |
4613 fixed_latency(6); | |
4614 %} | |
4615 | |
4616 // Polling Address | |
4617 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4618 #ifdef _LP64 | |
4619 instruction_count(0); multiple_bundles; | |
4620 fixed_latency(6); | |
4621 #else | |
4622 dst : E(write); | |
4623 IALU : R; | |
4624 #endif | |
4625 %} | |
4626 | |
4627 // Long Constant small | |
4628 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4629 instruction_count(2); | |
4630 dst : E(write); | |
4631 IALU : R; | |
4632 IALU : R; | |
4633 %} | |
4634 | |
4635 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4636 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4637 instruction_count(1); multiple_bundles; | |
4638 src : R(read); | |
4639 dst : M(write)+1; | |
4640 IALU : R; | |
4641 MS : E; | |
4642 %} | |
4643 | |
4644 // Integer ALU nop operation | |
4645 pipe_class ialu_nop() %{ | |
4646 single_instruction; | |
4647 IALU : R; | |
4648 %} | |
4649 | |
4650 // Integer ALU nop operation | |
4651 pipe_class ialu_nop_A0() %{ | |
4652 single_instruction; | |
4653 A0 : R; | |
4654 %} | |
4655 | |
4656 // Integer ALU nop operation | |
4657 pipe_class ialu_nop_A1() %{ | |
4658 single_instruction; | |
4659 A1 : R; | |
4660 %} | |
4661 | |
4662 // Integer Multiply reg-reg operation | |
4663 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4664 single_instruction; | |
4665 dst : E(write); | |
4666 src1 : R(read); | |
4667 src2 : R(read); | |
4668 MS : R(5); | |
4669 %} | |
4670 | |
4671 // Integer Multiply reg-imm operation | |
4672 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4673 single_instruction; | |
4674 dst : E(write); | |
4675 src1 : R(read); | |
4676 MS : R(5); | |
4677 %} | |
4678 | |
4679 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4680 single_instruction; | |
4681 dst : E(write)+4; | |
4682 src1 : R(read); | |
4683 src2 : R(read); | |
4684 MS : R(6); | |
4685 %} | |
4686 | |
4687 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4688 single_instruction; | |
4689 dst : E(write)+4; | |
4690 src1 : R(read); | |
4691 MS : R(6); | |
4692 %} | |
4693 | |
4694 // Integer Divide reg-reg | |
4695 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4696 instruction_count(1); multiple_bundles; | |
4697 dst : E(write); | |
4698 temp : E(write); | |
4699 src1 : R(read); | |
4700 src2 : R(read); | |
4701 temp : R(read); | |
4702 MS : R(38); | |
4703 %} | |
4704 | |
4705 // Integer Divide reg-imm | |
4706 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4707 instruction_count(1); multiple_bundles; | |
4708 dst : E(write); | |
4709 temp : E(write); | |
4710 src1 : R(read); | |
4711 temp : R(read); | |
4712 MS : R(38); | |
4713 %} | |
4714 | |
4715 // Long Divide | |
4716 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4717 dst : E(write)+71; | |
4718 src1 : R(read); | |
4719 src2 : R(read)+1; | |
4720 MS : R(70); | |
4721 %} | |
4722 | |
4723 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4724 dst : E(write)+71; | |
4725 src1 : R(read); | |
4726 MS : R(70); | |
4727 %} | |
4728 | |
4729 // Floating Point Add Float | |
4730 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4731 single_instruction; | |
4732 dst : X(write); | |
4733 src1 : E(read); | |
4734 src2 : E(read); | |
4735 FA : R; | |
4736 %} | |
4737 | |
4738 // Floating Point Add Double | |
4739 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4740 single_instruction; | |
4741 dst : X(write); | |
4742 src1 : E(read); | |
4743 src2 : E(read); | |
4744 FA : R; | |
4745 %} | |
4746 | |
4747 // Floating Point Conditional Move based on integer flags | |
4748 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4749 single_instruction; | |
4750 dst : X(write); | |
4751 src : E(read); | |
4752 cr : R(read); | |
4753 FA : R(2); | |
4754 BR : R(2); | |
4755 %} | |
4756 | |
4757 // Floating Point Conditional Move based on integer flags | |
4758 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4759 single_instruction; | |
4760 dst : X(write); | |
4761 src : E(read); | |
4762 cr : R(read); | |
4763 FA : R(2); | |
4764 BR : R(2); | |
4765 %} | |
4766 | |
4767 // Floating Point Multiply Float | |
4768 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4769 single_instruction; | |
4770 dst : X(write); | |
4771 src1 : E(read); | |
4772 src2 : E(read); | |
4773 FM : R; | |
4774 %} | |
4775 | |
4776 // Floating Point Multiply Double | |
4777 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4778 single_instruction; | |
4779 dst : X(write); | |
4780 src1 : E(read); | |
4781 src2 : E(read); | |
4782 FM : R; | |
4783 %} | |
4784 | |
4785 // Floating Point Divide Float | |
4786 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4787 single_instruction; | |
4788 dst : X(write); | |
4789 src1 : E(read); | |
4790 src2 : E(read); | |
4791 FM : R; | |
4792 FDIV : C(14); | |
4793 %} | |
4794 | |
4795 // Floating Point Divide Double | |
4796 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4797 single_instruction; | |
4798 dst : X(write); | |
4799 src1 : E(read); | |
4800 src2 : E(read); | |
4801 FM : R; | |
4802 FDIV : C(17); | |
4803 %} | |
4804 | |
4805 // Floating Point Move/Negate/Abs Float | |
4806 pipe_class faddF_reg(regF dst, regF src) %{ | |
4807 single_instruction; | |
4808 dst : W(write); | |
4809 src : E(read); | |
4810 FA : R(1); | |
4811 %} | |
4812 | |
4813 // Floating Point Move/Negate/Abs Double | |
4814 pipe_class faddD_reg(regD dst, regD src) %{ | |
4815 single_instruction; | |
4816 dst : W(write); | |
4817 src : E(read); | |
4818 FA : R; | |
4819 %} | |
4820 | |
4821 // Floating Point Convert F->D | |
4822 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4823 single_instruction; | |
4824 dst : X(write); | |
4825 src : E(read); | |
4826 FA : R; | |
4827 %} | |
4828 | |
4829 // Floating Point Convert I->D | |
4830 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4831 single_instruction; | |
4832 dst : X(write); | |
4833 src : E(read); | |
4834 FA : R; | |
4835 %} | |
4836 | |
4837 // Floating Point Convert LHi->D | |
4838 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4839 single_instruction; | |
4840 dst : X(write); | |
4841 src : E(read); | |
4842 FA : R; | |
4843 %} | |
4844 | |
4845 // Floating Point Convert L->D | |
4846 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4847 single_instruction; | |
4848 dst : X(write); | |
4849 src : E(read); | |
4850 FA : R; | |
4851 %} | |
4852 | |
4853 // Floating Point Convert L->F | |
4854 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4855 single_instruction; | |
4856 dst : X(write); | |
4857 src : E(read); | |
4858 FA : R; | |
4859 %} | |
4860 | |
4861 // Floating Point Convert D->F | |
4862 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4863 single_instruction; | |
4864 dst : X(write); | |
4865 src : E(read); | |
4866 FA : R; | |
4867 %} | |
4868 | |
4869 // Floating Point Convert I->L | |
4870 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4871 single_instruction; | |
4872 dst : X(write); | |
4873 src : E(read); | |
4874 FA : R; | |
4875 %} | |
4876 | |
4877 // Floating Point Convert D->F | |
4878 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4879 instruction_count(1); multiple_bundles; | |
4880 dst : X(write)+6; | |
4881 src : E(read); | |
4882 FA : R; | |
4883 %} | |
4884 | |
4885 // Floating Point Convert D->L | |
4886 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4887 instruction_count(1); multiple_bundles; | |
4888 dst : X(write)+6; | |
4889 src : E(read); | |
4890 FA : R; | |
4891 %} | |
4892 | |
4893 // Floating Point Convert F->I | |
4894 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4895 instruction_count(1); multiple_bundles; | |
4896 dst : X(write)+6; | |
4897 src : E(read); | |
4898 FA : R; | |
4899 %} | |
4900 | |
4901 // Floating Point Convert F->L | |
4902 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4903 instruction_count(1); multiple_bundles; | |
4904 dst : X(write)+6; | |
4905 src : E(read); | |
4906 FA : R; | |
4907 %} | |
4908 | |
4909 // Floating Point Convert I->F | |
4910 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4911 single_instruction; | |
4912 dst : X(write); | |
4913 src : E(read); | |
4914 FA : R; | |
4915 %} | |
4916 | |
4917 // Floating Point Compare | |
4918 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4919 single_instruction; | |
4920 cr : X(write); | |
4921 src1 : E(read); | |
4922 src2 : E(read); | |
4923 FA : R; | |
4924 %} | |
4925 | |
4926 // Floating Point Compare | |
4927 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4928 single_instruction; | |
4929 cr : X(write); | |
4930 src1 : E(read); | |
4931 src2 : E(read); | |
4932 FA : R; | |
4933 %} | |
4934 | |
4935 // Floating Add Nop | |
4936 pipe_class fadd_nop() %{ | |
4937 single_instruction; | |
4938 FA : R; | |
4939 %} | |
4940 | |
4941 // Integer Store to Memory | |
4942 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
4943 single_instruction; | |
4944 mem : R(read); | |
4945 src : C(read); | |
4946 MS : R; | |
4947 %} | |
4948 | |
4949 // Integer Store to Memory | |
4950 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
4951 single_instruction; | |
4952 mem : R(read); | |
4953 src : C(read); | |
4954 MS : R; | |
4955 %} | |
4956 | |
4957 // Integer Store Zero to Memory | |
4958 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
4959 single_instruction; | |
4960 mem : R(read); | |
4961 MS : R; | |
4962 %} | |
4963 | |
4964 // Special Stack Slot Store | |
4965 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
4966 single_instruction; | |
4967 stkSlot : R(read); | |
4968 src : C(read); | |
4969 MS : R; | |
4970 %} | |
4971 | |
4972 // Special Stack Slot Store | |
4973 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
4974 instruction_count(2); multiple_bundles; | |
4975 stkSlot : R(read); | |
4976 src : C(read); | |
4977 MS : R(2); | |
4978 %} | |
4979 | |
4980 // Float Store | |
4981 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
4982 single_instruction; | |
4983 mem : R(read); | |
4984 src : C(read); | |
4985 MS : R; | |
4986 %} | |
4987 | |
4988 // Float Store | |
4989 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
4990 single_instruction; | |
4991 mem : R(read); | |
4992 MS : R; | |
4993 %} | |
4994 | |
4995 // Double Store | |
4996 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
4997 instruction_count(1); | |
4998 mem : R(read); | |
4999 src : C(read); | |
5000 MS : R; | |
5001 %} | |
5002 | |
5003 // Double Store | |
5004 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5005 single_instruction; | |
5006 mem : R(read); | |
5007 MS : R; | |
5008 %} | |
5009 | |
5010 // Special Stack Slot Float Store | |
5011 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5012 single_instruction; | |
5013 stkSlot : R(read); | |
5014 src : C(read); | |
5015 MS : R; | |
5016 %} | |
5017 | |
5018 // Special Stack Slot Double Store | |
5019 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5020 single_instruction; | |
5021 stkSlot : R(read); | |
5022 src : C(read); | |
5023 MS : R; | |
5024 %} | |
5025 | |
5026 // Integer Load (when sign bit propagation not needed) | |
5027 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5028 single_instruction; | |
5029 mem : R(read); | |
5030 dst : C(write); | |
5031 MS : R; | |
5032 %} | |
5033 | |
5034 // Integer Load from stack operand | |
5035 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5036 single_instruction; | |
5037 mem : R(read); | |
5038 dst : C(write); | |
5039 MS : R; | |
5040 %} | |
5041 | |
5042 // Integer Load (when sign bit propagation or masking is needed) | |
5043 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5044 single_instruction; | |
5045 mem : R(read); | |
5046 dst : M(write); | |
5047 MS : R; | |
5048 %} | |
5049 | |
5050 // Float Load | |
5051 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5052 single_instruction; | |
5053 mem : R(read); | |
5054 dst : M(write); | |
5055 MS : R; | |
5056 %} | |
5057 | |
5058 // Float Load | |
5059 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5060 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5061 mem : R(read); | |
5062 dst : M(write); | |
5063 MS : R; | |
5064 %} | |
5065 | |
5066 // Float Load | |
5067 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5068 single_instruction; | |
5069 stkSlot : R(read); | |
5070 dst : M(write); | |
5071 MS : R; | |
5072 %} | |
5073 | |
5074 // Float Load | |
5075 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5076 single_instruction; | |
5077 stkSlot : R(read); | |
5078 dst : M(write); | |
5079 MS : R; | |
5080 %} | |
5081 | |
5082 // Memory Nop | |
5083 pipe_class mem_nop() %{ | |
5084 single_instruction; | |
5085 MS : R; | |
5086 %} | |
5087 | |
5088 pipe_class sethi(iRegP dst, immI src) %{ | |
5089 single_instruction; | |
5090 dst : E(write); | |
5091 IALU : R; | |
5092 %} | |
5093 | |
5094 pipe_class loadPollP(iRegP poll) %{ | |
5095 single_instruction; | |
5096 poll : R(read); | |
5097 MS : R; | |
5098 %} | |
5099 | |
5100 pipe_class br(Universe br, label labl) %{ | |
5101 single_instruction_with_delay_slot; | |
5102 BR : R; | |
5103 %} | |
5104 | |
5105 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5106 single_instruction_with_delay_slot; | |
5107 cr : E(read); | |
5108 BR : R; | |
5109 %} | |
5110 | |
5111 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5112 single_instruction_with_delay_slot; | |
5113 op1 : E(read); | |
5114 BR : R; | |
5115 MS : R; | |
5116 %} | |
5117 | |
5118 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
5119 single_instruction_with_delay_slot; | |
5120 cr : E(read); | |
5121 BR : R; | |
5122 %} | |
5123 | |
5124 pipe_class br_nop() %{ | |
5125 single_instruction; | |
5126 BR : R; | |
5127 %} | |
5128 | |
5129 pipe_class simple_call(method meth) %{ | |
5130 instruction_count(2); multiple_bundles; force_serialization; | |
5131 fixed_latency(100); | |
5132 BR : R(1); | |
5133 MS : R(1); | |
5134 A0 : R(1); | |
5135 %} | |
5136 | |
5137 pipe_class compiled_call(method meth) %{ | |
5138 instruction_count(1); multiple_bundles; force_serialization; | |
5139 fixed_latency(100); | |
5140 MS : R(1); | |
5141 %} | |
5142 | |
5143 pipe_class call(method meth) %{ | |
5144 instruction_count(0); multiple_bundles; force_serialization; | |
5145 fixed_latency(100); | |
5146 %} | |
5147 | |
5148 pipe_class tail_call(Universe ignore, label labl) %{ | |
5149 single_instruction; has_delay_slot; | |
5150 fixed_latency(100); | |
5151 BR : R(1); | |
5152 MS : R(1); | |
5153 %} | |
5154 | |
5155 pipe_class ret(Universe ignore) %{ | |
5156 single_instruction; has_delay_slot; | |
5157 BR : R(1); | |
5158 MS : R(1); | |
5159 %} | |
5160 | |
5161 pipe_class ret_poll(g3RegP poll) %{ | |
5162 instruction_count(3); has_delay_slot; | |
5163 poll : E(read); | |
5164 MS : R; | |
5165 %} | |
5166 | |
5167 // The real do-nothing guy | |
5168 pipe_class empty( ) %{ | |
5169 instruction_count(0); | |
5170 %} | |
5171 | |
5172 pipe_class long_memory_op() %{ | |
5173 instruction_count(0); multiple_bundles; force_serialization; | |
5174 fixed_latency(25); | |
5175 MS : R(1); | |
5176 %} | |
5177 | |
5178 // Check-cast | |
5179 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5180 array : R(read); | |
5181 match : R(read); | |
5182 IALU : R(2); | |
5183 BR : R(2); | |
5184 MS : R; | |
5185 %} | |
5186 | |
5187 // Convert FPU flags into +1,0,-1 | |
5188 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5189 src1 : E(read); | |
5190 src2 : E(read); | |
5191 dst : E(write); | |
5192 FA : R; | |
5193 MS : R(2); | |
5194 BR : R(2); | |
5195 %} | |
5196 | |
5197 // Compare for p < q, and conditionally add y | |
5198 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5199 p : E(read); | |
5200 q : E(read); | |
5201 y : E(read); | |
5202 IALU : R(3) | |
5203 %} | |
5204 | |
5205 // Perform a compare, then move conditionally in a branch delay slot. | |
5206 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5207 src2 : E(read); | |
5208 srcdst : E(read); | |
5209 IALU : R; | |
5210 BR : R; | |
5211 %} | |
5212 | |
5213 // Define the class for the Nop node | |
5214 define %{ | |
5215 MachNop = ialu_nop; | |
5216 %} | |
5217 | |
5218 %} | |
5219 | |
5220 //----------INSTRUCTIONS------------------------------------------------------- | |
5221 | |
5222 //------------Special Stack Slot instructions - no match rules----------------- | |
5223 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5224 // No match rule to avoid chain rule match. | |
5225 effect(DEF dst, USE src); | |
5226 ins_cost(MEMORY_REF_COST); | |
5227 size(4); | |
5228 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5229 opcode(Assembler::ldf_op3); | |
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5230 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5231 ins_pipe(floadF_stk); |
5232 %} | |
5233 | |
5234 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5235 // No match rule to avoid chain rule match. | |
5236 effect(DEF dst, USE src); | |
5237 ins_cost(MEMORY_REF_COST); | |
5238 size(4); | |
5239 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5240 opcode(Assembler::lddf_op3); | |
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5241 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5242 ins_pipe(floadD_stk); |
5243 %} | |
5244 | |
5245 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5246 // No match rule to avoid chain rule match. | |
5247 effect(DEF dst, USE src); | |
5248 ins_cost(MEMORY_REF_COST); | |
5249 size(4); | |
5250 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5251 opcode(Assembler::stf_op3); | |
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5252 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5253 ins_pipe(fstoreF_stk_reg); |
5254 %} | |
5255 | |
5256 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5257 // No match rule to avoid chain rule match. | |
5258 effect(DEF dst, USE src); | |
5259 ins_cost(MEMORY_REF_COST); | |
5260 size(4); | |
5261 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5262 opcode(Assembler::stdf_op3); | |
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5263 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5264 ins_pipe(fstoreD_stk_reg); |
5265 %} | |
5266 | |
5267 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5268 effect(DEF dst, USE src); | |
5269 ins_cost(MEMORY_REF_COST*2); | |
5270 size(8); | |
5271 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5272 "STW R_G0,$dst.lo" %} | |
5273 opcode(Assembler::stw_op3); | |
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5274 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5275 ins_pipe(lstoreI_stk_reg); |
5276 %} | |
5277 | |
5278 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5279 // No match rule to avoid chain rule match. | |
5280 effect(DEF dst, USE src); | |
5281 ins_cost(MEMORY_REF_COST); | |
5282 size(4); | |
5283 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5284 opcode(Assembler::stx_op3); | |
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5285 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5286 ins_pipe(istore_stk_reg); |
5287 %} | |
5288 | |
5289 //---------- Chain stack slots between similar types -------- | |
5290 | |
5291 // Load integer from stack slot | |
5292 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5293 match(Set dst src); | |
5294 ins_cost(MEMORY_REF_COST); | |
5295 | |
5296 size(4); | |
5297 format %{ "LDUW $src,$dst\t!stk" %} | |
5298 opcode(Assembler::lduw_op3); | |
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5299 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5300 ins_pipe(iload_mem); |
5301 %} | |
5302 | |
5303 // Store integer to stack slot | |
5304 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5305 match(Set dst src); | |
5306 ins_cost(MEMORY_REF_COST); | |
5307 | |
5308 size(4); | |
5309 format %{ "STW $src,$dst\t!stk" %} | |
5310 opcode(Assembler::stw_op3); | |
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5311 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5312 ins_pipe(istore_mem_reg); |
5313 %} | |
5314 | |
5315 // Load long from stack slot | |
5316 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5317 match(Set dst src); | |
5318 | |
5319 ins_cost(MEMORY_REF_COST); | |
5320 size(4); | |
5321 format %{ "LDX $src,$dst\t! long" %} | |
5322 opcode(Assembler::ldx_op3); | |
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5323 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5324 ins_pipe(iload_mem); |
5325 %} | |
5326 | |
5327 // Store long to stack slot | |
5328 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5329 match(Set dst src); | |
5330 | |
5331 ins_cost(MEMORY_REF_COST); | |
5332 size(4); | |
5333 format %{ "STX $src,$dst\t! long" %} | |
5334 opcode(Assembler::stx_op3); | |
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5335 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5336 ins_pipe(istore_mem_reg); |
5337 %} | |
5338 | |
5339 #ifdef _LP64 | |
5340 // Load pointer from stack slot, 64-bit encoding | |
5341 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5342 match(Set dst src); | |
5343 ins_cost(MEMORY_REF_COST); | |
5344 size(4); | |
5345 format %{ "LDX $src,$dst\t!ptr" %} | |
5346 opcode(Assembler::ldx_op3); | |
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5347 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5348 ins_pipe(iload_mem); |
5349 %} | |
5350 | |
5351 // Store pointer to stack slot | |
5352 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5353 match(Set dst src); | |
5354 ins_cost(MEMORY_REF_COST); | |
5355 size(4); | |
5356 format %{ "STX $src,$dst\t!ptr" %} | |
5357 opcode(Assembler::stx_op3); | |
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5358 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5359 ins_pipe(istore_mem_reg); |
5360 %} | |
5361 #else // _LP64 | |
5362 // Load pointer from stack slot, 32-bit encoding | |
5363 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5364 match(Set dst src); | |
5365 ins_cost(MEMORY_REF_COST); | |
5366 format %{ "LDUW $src,$dst\t!ptr" %} | |
5367 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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5368 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5369 ins_pipe(iload_mem); |
5370 %} | |
5371 | |
5372 // Store pointer to stack slot | |
5373 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5374 match(Set dst src); | |
5375 ins_cost(MEMORY_REF_COST); | |
5376 format %{ "STW $src,$dst\t!ptr" %} | |
5377 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5378 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5379 ins_pipe(istore_mem_reg); |
5380 %} | |
5381 #endif // _LP64 | |
5382 | |
5383 //------------Special Nop instructions for bundling - no match rules----------- | |
5384 // Nop using the A0 functional unit | |
5385 instruct Nop_A0() %{ | |
5386 ins_cost(0); | |
5387 | |
5388 format %{ "NOP ! Alu Pipeline" %} | |
5389 opcode(Assembler::or_op3, Assembler::arith_op); | |
5390 ins_encode( form2_nop() ); | |
5391 ins_pipe(ialu_nop_A0); | |
5392 %} | |
5393 | |
5394 // Nop using the A1 functional unit | |
5395 instruct Nop_A1( ) %{ | |
5396 ins_cost(0); | |
5397 | |
5398 format %{ "NOP ! Alu Pipeline" %} | |
5399 opcode(Assembler::or_op3, Assembler::arith_op); | |
5400 ins_encode( form2_nop() ); | |
5401 ins_pipe(ialu_nop_A1); | |
5402 %} | |
5403 | |
5404 // Nop using the memory functional unit | |
5405 instruct Nop_MS( ) %{ | |
5406 ins_cost(0); | |
5407 | |
5408 format %{ "NOP ! Memory Pipeline" %} | |
5409 ins_encode( emit_mem_nop ); | |
5410 ins_pipe(mem_nop); | |
5411 %} | |
5412 | |
5413 // Nop using the floating add functional unit | |
5414 instruct Nop_FA( ) %{ | |
5415 ins_cost(0); | |
5416 | |
5417 format %{ "NOP ! Floating Add Pipeline" %} | |
5418 ins_encode( emit_fadd_nop ); | |
5419 ins_pipe(fadd_nop); | |
5420 %} | |
5421 | |
5422 // Nop using the branch functional unit | |
5423 instruct Nop_BR( ) %{ | |
5424 ins_cost(0); | |
5425 | |
5426 format %{ "NOP ! Branch Pipeline" %} | |
5427 ins_encode( emit_br_nop ); | |
5428 ins_pipe(br_nop); | |
5429 %} | |
5430 | |
5431 //----------Load/Store/Move Instructions--------------------------------------- | |
5432 //----------Load Instructions-------------------------------------------------- | |
5433 // Load Byte (8bit signed) | |
5434 instruct loadB(iRegI dst, memory mem) %{ | |
5435 match(Set dst (LoadB mem)); | |
5436 ins_cost(MEMORY_REF_COST); | |
5437 | |
5438 size(4); | |
624 | 5439 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5440 ins_encode %{ |
5441 __ ldsb($mem$$Address, $dst$$Register); | |
5442 %} | |
624 | 5443 ins_pipe(iload_mask_mem); |
5444 %} | |
5445 | |
5446 // Load Byte (8bit signed) into a Long Register | |
5447 instruct loadB2L(iRegL dst, memory mem) %{ | |
5448 match(Set dst (ConvI2L (LoadB mem))); | |
5449 ins_cost(MEMORY_REF_COST); | |
5450 | |
5451 size(4); | |
5452 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5453 ins_encode %{ |
5454 __ ldsb($mem$$Address, $dst$$Register); | |
5455 %} | |
0 | 5456 ins_pipe(iload_mask_mem); |
5457 %} | |
5458 | |
624 | 5459 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5460 instruct loadUB(iRegI dst, memory mem) %{ | |
5461 match(Set dst (LoadUB mem)); | |
0 | 5462 ins_cost(MEMORY_REF_COST); |
5463 | |
5464 size(4); | |
624 | 5465 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5466 ins_encode %{ |
5467 __ ldub($mem$$Address, $dst$$Register); | |
5468 %} | |
824 | 5469 ins_pipe(iload_mem); |
624 | 5470 %} |
5471 | |
5472 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5473 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5474 match(Set dst (ConvI2L (LoadUB mem))); | |
5475 ins_cost(MEMORY_REF_COST); | |
5476 | |
5477 size(4); | |
5478 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5479 ins_encode %{ |
5480 __ ldub($mem$$Address, $dst$$Register); | |
5481 %} | |
824 | 5482 ins_pipe(iload_mem); |
5483 %} | |
5484 | |
5485 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5486 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5487 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5488 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5489 | |
5490 size(2*4); | |
5491 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5492 "AND $dst,$mask,$dst" %} | |
5493 ins_encode %{ | |
5494 __ ldub($mem$$Address, $dst$$Register); | |
5495 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5496 %} | |
5497 ins_pipe(iload_mem); | |
0 | 5498 %} |
5499 | |
624 | 5500 // Load Short (16bit signed) |
5501 instruct loadS(iRegI dst, memory mem) %{ | |
5502 match(Set dst (LoadS mem)); | |
5503 ins_cost(MEMORY_REF_COST); | |
5504 | |
5505 size(4); | |
5506 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5507 ins_encode %{ |
5508 __ ldsh($mem$$Address, $dst$$Register); | |
5509 %} | |
624 | 5510 ins_pipe(iload_mask_mem); |
5511 %} | |
5512 | |
785 | 5513 // Load Short (16 bit signed) to Byte (8 bit signed) |
5514 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5515 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5516 ins_cost(MEMORY_REF_COST); | |
5517 | |
5518 size(4); | |
5519 | |
5520 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5521 ins_encode %{ | |
5522 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5523 %} | |
5524 ins_pipe(iload_mask_mem); | |
5525 %} | |
5526 | |
624 | 5527 // Load Short (16bit signed) into a Long Register |
5528 instruct loadS2L(iRegL dst, memory mem) %{ | |
5529 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5530 ins_cost(MEMORY_REF_COST); |
5531 | |
5532 size(4); | |
624 | 5533 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5534 ins_encode %{ |
5535 __ ldsh($mem$$Address, $dst$$Register); | |
5536 %} | |
624 | 5537 ins_pipe(iload_mask_mem); |
5538 %} | |
5539 | |
5540 // Load Unsigned Short/Char (16bit UNsigned) | |
5541 instruct loadUS(iRegI dst, memory mem) %{ | |
5542 match(Set dst (LoadUS mem)); | |
5543 ins_cost(MEMORY_REF_COST); | |
5544 | |
5545 size(4); | |
5546 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5547 ins_encode %{ |
5548 __ lduh($mem$$Address, $dst$$Register); | |
5549 %} | |
824 | 5550 ins_pipe(iload_mem); |
0 | 5551 %} |
5552 | |
785 | 5553 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5554 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5555 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5556 ins_cost(MEMORY_REF_COST); | |
5557 | |
5558 size(4); | |
5559 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5560 ins_encode %{ | |
5561 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5562 %} | |
5563 ins_pipe(iload_mask_mem); | |
5564 %} | |
5565 | |
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diff
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5566 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5567 instruct loadUS2L(iRegL dst, memory mem) %{ |
5568 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5569 ins_cost(MEMORY_REF_COST); |
5570 | |
5571 size(4); | |
624 | 5572 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5573 ins_encode %{ |
5574 __ lduh($mem$$Address, $dst$$Register); | |
5575 %} | |
824 | 5576 ins_pipe(iload_mem); |
5577 %} | |
5578 | |
5579 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5580 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5581 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5582 ins_cost(MEMORY_REF_COST); | |
5583 | |
5584 size(4); | |
5585 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5586 ins_encode %{ | |
5587 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5588 %} | |
5589 ins_pipe(iload_mem); | |
5590 %} | |
5591 | |
5592 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5593 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5594 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5595 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5596 | |
5597 size(2*4); | |
5598 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5599 "AND $dst,$mask,$dst" %} | |
5600 ins_encode %{ | |
5601 Register Rdst = $dst$$Register; | |
5602 __ lduh($mem$$Address, Rdst); | |
5603 __ and3(Rdst, $mask$$constant, Rdst); | |
5604 %} | |
5605 ins_pipe(iload_mem); | |
5606 %} | |
5607 | |
5608 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5609 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5610 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5611 effect(TEMP dst, TEMP tmp); | |
5612 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5613 | |
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1fbd5d696bf4
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|
5614 size((3+1)*4); // set may use two instructions. |
824 | 5615 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5616 "SET $mask,$tmp\n\t" | |
5617 "AND $dst,$tmp,$dst" %} | |
5618 ins_encode %{ | |
5619 Register Rdst = $dst$$Register; | |
5620 Register Rtmp = $tmp$$Register; | |
5621 __ lduh($mem$$Address, Rdst); | |
5622 __ set($mask$$constant, Rtmp); | |
5623 __ and3(Rdst, Rtmp, Rdst); | |
5624 %} | |
5625 ins_pipe(iload_mem); | |
0 | 5626 %} |
5627 | |
5628 // Load Integer | |
5629 instruct loadI(iRegI dst, memory mem) %{ | |
5630 match(Set dst (LoadI mem)); | |
5631 ins_cost(MEMORY_REF_COST); | |
624 | 5632 |
5633 size(4); | |
5634 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5635 ins_encode %{ |
5636 __ lduw($mem$$Address, $dst$$Register); | |
5637 %} | |
624 | 5638 ins_pipe(iload_mem); |
5639 %} | |
5640 | |
785 | 5641 // Load Integer to Byte (8 bit signed) |
5642 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5643 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5644 ins_cost(MEMORY_REF_COST); | |
5645 | |
5646 size(4); | |
5647 | |
5648 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5649 ins_encode %{ | |
5650 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5651 %} | |
5652 ins_pipe(iload_mask_mem); | |
5653 %} | |
5654 | |
5655 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5656 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5657 match(Set dst (AndI (LoadI mem) mask)); | |
5658 ins_cost(MEMORY_REF_COST); | |
5659 | |
5660 size(4); | |
5661 | |
5662 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5663 ins_encode %{ | |
5664 __ ldub($mem$$Address, $dst$$Register, 3); | |
5665 %} | |
5666 ins_pipe(iload_mask_mem); | |
5667 %} | |
5668 | |
5669 // Load Integer to Short (16 bit signed) | |
5670 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5671 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5672 ins_cost(MEMORY_REF_COST); | |
5673 | |
5674 size(4); | |
5675 | |
5676 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5677 ins_encode %{ | |
5678 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5679 %} | |
5680 ins_pipe(iload_mask_mem); | |
5681 %} | |
5682 | |
5683 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5684 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5685 match(Set dst (AndI (LoadI mem) mask)); | |
5686 ins_cost(MEMORY_REF_COST); | |
5687 | |
5688 size(4); | |
5689 | |
5690 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5691 ins_encode %{ | |
5692 __ lduh($mem$$Address, $dst$$Register, 2); | |
5693 %} | |
5694 ins_pipe(iload_mask_mem); | |
5695 %} | |
5696 | |
624 | 5697 // Load Integer into a Long Register |
5698 instruct loadI2L(iRegL dst, memory mem) %{ | |
5699 match(Set dst (ConvI2L (LoadI mem))); | |
5700 ins_cost(MEMORY_REF_COST); | |
5701 | |
5702 size(4); | |
5703 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5704 ins_encode %{ |
5705 __ ldsw($mem$$Address, $dst$$Register); | |
5706 %} | |
824 | 5707 ins_pipe(iload_mask_mem); |
5708 %} | |
5709 | |
5710 // Load Integer with mask 0xFF into a Long Register | |
5711 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5712 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5713 ins_cost(MEMORY_REF_COST); | |
5714 | |
5715 size(4); | |
5716 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5717 ins_encode %{ | |
5718 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5719 %} | |
5720 ins_pipe(iload_mem); | |
5721 %} | |
5722 | |
5723 // Load Integer with mask 0xFFFF into a Long Register | |
5724 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5725 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5726 ins_cost(MEMORY_REF_COST); | |
5727 | |
5728 size(4); | |
5729 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5730 ins_encode %{ | |
5731 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5732 %} | |
5733 ins_pipe(iload_mem); | |
5734 %} | |
5735 | |
5736 // Load Integer with a 13-bit mask into a Long Register | |
5737 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5738 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5739 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5740 | |
5741 size(2*4); | |
5742 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
5743 "AND $dst,$mask,$dst" %} | |
5744 ins_encode %{ | |
5745 Register Rdst = $dst$$Register; | |
5746 __ lduw($mem$$Address, Rdst); | |
5747 __ and3(Rdst, $mask$$constant, Rdst); | |
5748 %} | |
5749 ins_pipe(iload_mem); | |
5750 %} | |
5751 | |
5752 // Load Integer with a 32-bit mask into a Long Register | |
5753 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
5754 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5755 effect(TEMP dst, TEMP tmp); | |
5756 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5757 | |
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|
5758 size((3+1)*4); // set may use two instructions. |
824 | 5759 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
5760 "SET $mask,$tmp\n\t" | |
5761 "AND $dst,$tmp,$dst" %} | |
5762 ins_encode %{ | |
5763 Register Rdst = $dst$$Register; | |
5764 Register Rtmp = $tmp$$Register; | |
5765 __ lduw($mem$$Address, Rdst); | |
5766 __ set($mask$$constant, Rtmp); | |
5767 __ and3(Rdst, Rtmp, Rdst); | |
5768 %} | |
624 | 5769 ins_pipe(iload_mem); |
5770 %} | |
5771 | |
5772 // Load Unsigned Integer into a Long Register | |
5773 instruct loadUI2L(iRegL dst, memory mem) %{ | |
5774 match(Set dst (LoadUI2L mem)); | |
5775 ins_cost(MEMORY_REF_COST); | |
5776 | |
5777 size(4); | |
5778 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5779 ins_encode %{ |
5780 __ lduw($mem$$Address, $dst$$Register); | |
5781 %} | |
0 | 5782 ins_pipe(iload_mem); |
5783 %} | |
5784 | |
5785 // Load Long - aligned | |
5786 instruct loadL(iRegL dst, memory mem ) %{ | |
5787 match(Set dst (LoadL mem)); | |
5788 ins_cost(MEMORY_REF_COST); | |
624 | 5789 |
0 | 5790 size(4); |
5791 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5792 ins_encode %{ |
5793 __ ldx($mem$$Address, $dst$$Register); | |
5794 %} | |
0 | 5795 ins_pipe(iload_mem); |
5796 %} | |
5797 | |
5798 // Load Long - UNaligned | |
5799 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5800 match(Set dst (LoadL_unaligned mem)); | |
5801 effect(KILL tmp); | |
5802 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5803 size(16); | |
5804 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5805 "\tLDUW $mem ,$dst\n" | |
5806 "\tSLLX #32, $dst, $dst\n" | |
5807 "\tOR $dst, R_O7, $dst" %} | |
5808 opcode(Assembler::lduw_op3); | |
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|
5809 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5810 ins_pipe(iload_mem); |
5811 %} | |
5812 | |
5813 // Load Aligned Packed Byte into a Double Register | |
5814 instruct loadA8B(regD dst, memory mem) %{ | |
5815 match(Set dst (Load8B mem)); | |
5816 ins_cost(MEMORY_REF_COST); | |
5817 size(4); | |
5818 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
5819 opcode(Assembler::lddf_op3); | |
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|
5820 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5821 ins_pipe(floadD_mem); |
5822 %} | |
5823 | |
5824 // Load Aligned Packed Char into a Double Register | |
5825 instruct loadA4C(regD dst, memory mem) %{ | |
5826 match(Set dst (Load4C mem)); | |
5827 ins_cost(MEMORY_REF_COST); | |
5828 size(4); | |
5829 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
5830 opcode(Assembler::lddf_op3); | |
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|
5831 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5832 ins_pipe(floadD_mem); |
5833 %} | |
5834 | |
5835 // Load Aligned Packed Short into a Double Register | |
5836 instruct loadA4S(regD dst, memory mem) %{ | |
5837 match(Set dst (Load4S mem)); | |
5838 ins_cost(MEMORY_REF_COST); | |
5839 size(4); | |
5840 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
5841 opcode(Assembler::lddf_op3); | |
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|
5842 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5843 ins_pipe(floadD_mem); |
5844 %} | |
5845 | |
5846 // Load Aligned Packed Int into a Double Register | |
5847 instruct loadA2I(regD dst, memory mem) %{ | |
5848 match(Set dst (Load2I mem)); | |
5849 ins_cost(MEMORY_REF_COST); | |
5850 size(4); | |
5851 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
5852 opcode(Assembler::lddf_op3); | |
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|
5853 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5854 ins_pipe(floadD_mem); |
5855 %} | |
5856 | |
5857 // Load Range | |
5858 instruct loadRange(iRegI dst, memory mem) %{ | |
5859 match(Set dst (LoadRange mem)); | |
5860 ins_cost(MEMORY_REF_COST); | |
5861 | |
5862 size(4); | |
5863 format %{ "LDUW $mem,$dst\t! range" %} | |
5864 opcode(Assembler::lduw_op3); | |
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235
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|
5865 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5866 ins_pipe(iload_mem); |
5867 %} | |
5868 | |
5869 // Load Integer into %f register (for fitos/fitod) | |
5870 instruct loadI_freg(regF dst, memory mem) %{ | |
5871 match(Set dst (LoadI mem)); | |
5872 ins_cost(MEMORY_REF_COST); | |
5873 size(4); | |
5874 | |
5875 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5876 opcode(Assembler::ldf_op3); | |
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|
5877 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5878 ins_pipe(floadF_mem); |
5879 %} | |
5880 | |
5881 // Load Pointer | |
5882 instruct loadP(iRegP dst, memory mem) %{ | |
5883 match(Set dst (LoadP mem)); | |
5884 ins_cost(MEMORY_REF_COST); | |
5885 size(4); | |
5886 | |
5887 #ifndef _LP64 | |
5888 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5889 ins_encode %{ |
5890 __ lduw($mem$$Address, $dst$$Register); | |
5891 %} | |
0 | 5892 #else |
5893 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5894 ins_encode %{ |
5895 __ ldx($mem$$Address, $dst$$Register); | |
5896 %} | |
0 | 5897 #endif |
5898 ins_pipe(iload_mem); | |
5899 %} | |
5900 | |
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|
5901 // Load Compressed Pointer |
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5902 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5903 match(Set dst (LoadN mem)); |
5904 ins_cost(MEMORY_REF_COST); | |
5905 size(4); | |
5906 | |
5907 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5908 ins_encode %{ | |
5909 __ lduw($mem$$Address, $dst$$Register); | |
5910 %} | |
5911 ins_pipe(iload_mem); | |
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5912 %} |
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|
5913 |
0 | 5914 // Load Klass Pointer |
5915 instruct loadKlass(iRegP dst, memory mem) %{ | |
5916 match(Set dst (LoadKlass mem)); | |
5917 ins_cost(MEMORY_REF_COST); | |
5918 size(4); | |
5919 | |
5920 #ifndef _LP64 | |
5921 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5922 ins_encode %{ |
5923 __ lduw($mem$$Address, $dst$$Register); | |
5924 %} | |
0 | 5925 #else |
5926 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5927 ins_encode %{ |
5928 __ ldx($mem$$Address, $dst$$Register); | |
5929 %} | |
0 | 5930 #endif |
5931 ins_pipe(iload_mem); | |
5932 %} | |
5933 | |
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|
5934 // Load narrow Klass Pointer |
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5935 instruct loadNKlass(iRegN dst, memory mem) %{ |
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5936 match(Set dst (LoadNKlass mem)); |
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5937 ins_cost(MEMORY_REF_COST); |
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5938 size(4); |
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5939 |
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5940 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5941 ins_encode %{ |
727 | 5942 __ lduw($mem$$Address, $dst$$Register); |
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5943 %} |
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|
5944 ins_pipe(iload_mem); |
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|
5945 %} |
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5946 |
0 | 5947 // Load Double |
5948 instruct loadD(regD dst, memory mem) %{ | |
5949 match(Set dst (LoadD mem)); | |
5950 ins_cost(MEMORY_REF_COST); | |
5951 | |
5952 size(4); | |
5953 format %{ "LDDF $mem,$dst" %} | |
5954 opcode(Assembler::lddf_op3); | |
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5955 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5956 ins_pipe(floadD_mem); |
5957 %} | |
5958 | |
5959 // Load Double - UNaligned | |
5960 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
5961 match(Set dst (LoadD_unaligned mem)); | |
5962 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5963 size(8); | |
5964 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
5965 "\tLDF $mem+4,$dst.lo\t!" %} | |
5966 opcode(Assembler::ldf_op3); | |
5967 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
5968 ins_pipe(iload_mem); | |
5969 %} | |
5970 | |
5971 // Load Float | |
5972 instruct loadF(regF dst, memory mem) %{ | |
5973 match(Set dst (LoadF mem)); | |
5974 ins_cost(MEMORY_REF_COST); | |
5975 | |
5976 size(4); | |
5977 format %{ "LDF $mem,$dst" %} | |
5978 opcode(Assembler::ldf_op3); | |
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5979 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5980 ins_pipe(floadF_mem); |
5981 %} | |
5982 | |
5983 // Load Constant | |
5984 instruct loadConI( iRegI dst, immI src ) %{ | |
5985 match(Set dst src); | |
5986 ins_cost(DEFAULT_COST * 3/2); | |
5987 format %{ "SET $src,$dst" %} | |
5988 ins_encode( Set32(src, dst) ); | |
5989 ins_pipe(ialu_hi_lo_reg); | |
5990 %} | |
5991 | |
5992 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
5993 match(Set dst src); | |
5994 | |
5995 size(4); | |
5996 format %{ "MOV $src,$dst" %} | |
5997 ins_encode( Set13( src, dst ) ); | |
5998 ins_pipe(ialu_imm); | |
5999 %} | |
6000 | |
6001 instruct loadConP(iRegP dst, immP src) %{ | |
6002 match(Set dst src); | |
6003 ins_cost(DEFAULT_COST * 3/2); | |
6004 format %{ "SET $src,$dst\t!ptr" %} | |
6005 // This rule does not use "expand" unlike loadConI because then | |
6006 // the result type is not known to be an Oop. An ADLC | |
6007 // enhancement will be needed to make that work - not worth it! | |
6008 | |
6009 ins_encode( SetPtr( src, dst ) ); | |
6010 ins_pipe(loadConP); | |
6011 | |
6012 %} | |
6013 | |
6014 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6015 match(Set dst src); | |
6016 | |
6017 size(4); | |
6018 format %{ "CLR $dst\t!ptr" %} | |
6019 ins_encode( SetNull( dst ) ); | |
6020 ins_pipe(ialu_imm); | |
6021 %} | |
6022 | |
6023 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6024 match(Set dst src); | |
6025 ins_cost(DEFAULT_COST); | |
6026 format %{ "SET $src,$dst\t!ptr" %} | |
6027 ins_encode %{ | |
727 | 6028 AddressLiteral polling_page(os::get_polling_page()); |
6029 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6030 %} |
6031 ins_pipe(loadConP_poll); | |
6032 %} | |
6033 | |
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6034 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6035 match(Set dst src); |
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6036 |
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6037 size(4); |
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6038 format %{ "CLR $dst\t! compressed NULL ptr" %} |
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6039 ins_encode( SetNull( dst ) ); |
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6040 ins_pipe(ialu_imm); |
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6041 %} |
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6042 |
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6043 instruct loadConN(iRegN dst, immN src) %{ |
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6044 match(Set dst src); |
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6045 ins_cost(DEFAULT_COST * 3/2); |
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6046 format %{ "SET $src,$dst\t! compressed ptr" %} |
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6047 ins_encode %{ |
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6048 Register dst = $dst$$Register; |
164
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6049 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6050 %} |
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6051 ins_pipe(ialu_hi_lo_reg); |
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6052 %} |
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6053 |
0 | 6054 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
6055 // %%% maybe this should work like loadConD | |
6056 match(Set dst src); | |
6057 effect(KILL tmp); | |
6058 ins_cost(DEFAULT_COST * 4); | |
6059 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
6060 ins_encode( LdImmL(src, dst, tmp) ); | |
6061 ins_pipe(loadConL); | |
6062 %} | |
6063 | |
6064 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6065 match(Set dst src); | |
6066 ins_cost(DEFAULT_COST); | |
6067 size(4); | |
6068 format %{ "CLR $dst\t! long" %} | |
6069 ins_encode( Set13( src, dst ) ); | |
6070 ins_pipe(ialu_imm); | |
6071 %} | |
6072 | |
6073 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6074 match(Set dst src); | |
6075 ins_cost(DEFAULT_COST * 2); | |
6076 | |
6077 size(4); | |
6078 format %{ "MOV $src,$dst\t! long" %} | |
6079 ins_encode( Set13( src, dst ) ); | |
6080 ins_pipe(ialu_imm); | |
6081 %} | |
6082 | |
6083 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
6084 match(Set dst src); | |
6085 effect(KILL tmp); | |
6086 | |
6087 #ifdef _LP64 | |
727 | 6088 size(8*4); |
0 | 6089 #else |
727 | 6090 size(2*4); |
0 | 6091 #endif |
6092 | |
6093 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
6094 "LDF [$tmp+lo(&$src)],$dst" %} | |
727 | 6095 ins_encode %{ |
6096 address float_address = __ float_constant($src$$constant); | |
6097 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
6098 AddressLiteral addrlit(float_address, rspec); | |
6099 | |
6100 __ sethi(addrlit, $tmp$$Register); | |
6101 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); | |
6102 %} | |
0 | 6103 ins_pipe(loadConFD); |
6104 %} | |
6105 | |
6106 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
6107 match(Set dst src); | |
6108 effect(KILL tmp); | |
6109 | |
6110 #ifdef _LP64 | |
727 | 6111 size(8*4); |
0 | 6112 #else |
727 | 6113 size(2*4); |
0 | 6114 #endif |
6115 | |
6116 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
6117 "LDDF [$tmp+lo(&$src)],$dst" %} | |
727 | 6118 ins_encode %{ |
6119 address double_address = __ double_constant($src$$constant); | |
6120 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
6121 AddressLiteral addrlit(double_address, rspec); | |
6122 | |
6123 __ sethi(addrlit, $tmp$$Register); | |
732
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6124 // XXX This is a quick fix for 6833573. |
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6125 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
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6126 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
727 | 6127 %} |
0 | 6128 ins_pipe(loadConFD); |
6129 %} | |
6130 | |
6131 // Prefetch instructions. | |
6132 // Must be safe to execute with invalid address (cannot fault). | |
6133 | |
6134 instruct prefetchr( memory mem ) %{ | |
6135 match( PrefetchRead mem ); | |
6136 ins_cost(MEMORY_REF_COST); | |
6137 | |
6138 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6139 opcode(Assembler::prefetch_op3); | |
6140 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6141 ins_pipe(iload_mem); | |
6142 %} | |
6143 | |
6144 instruct prefetchw( memory mem ) %{ | |
6145 match( PrefetchWrite mem ); | |
6146 ins_cost(MEMORY_REF_COST); | |
6147 | |
6148 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6149 opcode(Assembler::prefetch_op3); | |
6150 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6151 ins_pipe(iload_mem); | |
6152 %} | |
6153 | |
6154 | |
6155 //----------Store Instructions------------------------------------------------- | |
6156 // Store Byte | |
6157 instruct storeB(memory mem, iRegI src) %{ | |
6158 match(Set mem (StoreB mem src)); | |
6159 ins_cost(MEMORY_REF_COST); | |
6160 | |
6161 size(4); | |
6162 format %{ "STB $src,$mem\t! byte" %} | |
6163 opcode(Assembler::stb_op3); | |
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6164 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6165 ins_pipe(istore_mem_reg); |
6166 %} | |
6167 | |
6168 instruct storeB0(memory mem, immI0 src) %{ | |
6169 match(Set mem (StoreB mem src)); | |
6170 ins_cost(MEMORY_REF_COST); | |
6171 | |
6172 size(4); | |
6173 format %{ "STB $src,$mem\t! byte" %} | |
6174 opcode(Assembler::stb_op3); | |
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6175 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6176 ins_pipe(istore_mem_zero); |
6177 %} | |
6178 | |
6179 instruct storeCM0(memory mem, immI0 src) %{ | |
6180 match(Set mem (StoreCM mem src)); | |
6181 ins_cost(MEMORY_REF_COST); | |
6182 | |
6183 size(4); | |
6184 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6185 opcode(Assembler::stb_op3); | |
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6186 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6187 ins_pipe(istore_mem_zero); |
6188 %} | |
6189 | |
6190 // Store Char/Short | |
6191 instruct storeC(memory mem, iRegI src) %{ | |
6192 match(Set mem (StoreC mem src)); | |
6193 ins_cost(MEMORY_REF_COST); | |
6194 | |
6195 size(4); | |
6196 format %{ "STH $src,$mem\t! short" %} | |
6197 opcode(Assembler::sth_op3); | |
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6198 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6199 ins_pipe(istore_mem_reg); |
6200 %} | |
6201 | |
6202 instruct storeC0(memory mem, immI0 src) %{ | |
6203 match(Set mem (StoreC mem src)); | |
6204 ins_cost(MEMORY_REF_COST); | |
6205 | |
6206 size(4); | |
6207 format %{ "STH $src,$mem\t! short" %} | |
6208 opcode(Assembler::sth_op3); | |
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6209 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6210 ins_pipe(istore_mem_zero); |
6211 %} | |
6212 | |
6213 // Store Integer | |
6214 instruct storeI(memory mem, iRegI src) %{ | |
6215 match(Set mem (StoreI mem src)); | |
6216 ins_cost(MEMORY_REF_COST); | |
6217 | |
6218 size(4); | |
6219 format %{ "STW $src,$mem" %} | |
6220 opcode(Assembler::stw_op3); | |
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6221 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6222 ins_pipe(istore_mem_reg); |
6223 %} | |
6224 | |
6225 // Store Long | |
6226 instruct storeL(memory mem, iRegL src) %{ | |
6227 match(Set mem (StoreL mem src)); | |
6228 ins_cost(MEMORY_REF_COST); | |
6229 size(4); | |
6230 format %{ "STX $src,$mem\t! long" %} | |
6231 opcode(Assembler::stx_op3); | |
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6232 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6233 ins_pipe(istore_mem_reg); |
6234 %} | |
6235 | |
6236 instruct storeI0(memory mem, immI0 src) %{ | |
6237 match(Set mem (StoreI mem src)); | |
6238 ins_cost(MEMORY_REF_COST); | |
6239 | |
6240 size(4); | |
6241 format %{ "STW $src,$mem" %} | |
6242 opcode(Assembler::stw_op3); | |
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6243 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6244 ins_pipe(istore_mem_zero); |
6245 %} | |
6246 | |
6247 instruct storeL0(memory mem, immL0 src) %{ | |
6248 match(Set mem (StoreL mem src)); | |
6249 ins_cost(MEMORY_REF_COST); | |
6250 | |
6251 size(4); | |
6252 format %{ "STX $src,$mem" %} | |
6253 opcode(Assembler::stx_op3); | |
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6254 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6255 ins_pipe(istore_mem_zero); |
6256 %} | |
6257 | |
6258 // Store Integer from float register (used after fstoi) | |
6259 instruct storeI_Freg(memory mem, regF src) %{ | |
6260 match(Set mem (StoreI mem src)); | |
6261 ins_cost(MEMORY_REF_COST); | |
6262 | |
6263 size(4); | |
6264 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6265 opcode(Assembler::stf_op3); | |
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6266 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6267 ins_pipe(fstoreF_mem_reg); |
6268 %} | |
6269 | |
6270 // Store Pointer | |
6271 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6272 match(Set dst (StoreP dst src)); | |
6273 ins_cost(MEMORY_REF_COST); | |
6274 size(4); | |
6275 | |
6276 #ifndef _LP64 | |
6277 format %{ "STW $src,$dst\t! ptr" %} | |
6278 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6279 #else | |
6280 format %{ "STX $src,$dst\t! ptr" %} | |
6281 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6282 #endif | |
6283 ins_encode( form3_mem_reg( dst, src ) ); | |
6284 ins_pipe(istore_mem_spORreg); | |
6285 %} | |
6286 | |
6287 instruct storeP0(memory dst, immP0 src) %{ | |
6288 match(Set dst (StoreP dst src)); | |
6289 ins_cost(MEMORY_REF_COST); | |
6290 size(4); | |
6291 | |
6292 #ifndef _LP64 | |
6293 format %{ "STW $src,$dst\t! ptr" %} | |
6294 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6295 #else | |
6296 format %{ "STX $src,$dst\t! ptr" %} | |
6297 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6298 #endif | |
6299 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6300 ins_pipe(istore_mem_zero); | |
6301 %} | |
6302 | |
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6303 // Store Compressed Pointer |
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6304 instruct storeN(memory dst, iRegN src) %{ |
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6305 match(Set dst (StoreN dst src)); |
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6306 ins_cost(MEMORY_REF_COST); |
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6307 size(4); |
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6308 |
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6309 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6310 ins_encode %{ |
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6311 Register base = as_Register($dst$$base); |
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6312 Register index = as_Register($dst$$index); |
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6313 Register src = $src$$Register; |
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6314 if (index != G0) { |
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6315 __ stw(src, base, index); |
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6316 } else { |
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6317 __ stw(src, base, $dst$$disp); |
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6318 } |
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6319 %} |
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6320 ins_pipe(istore_mem_spORreg); |
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6321 %} |
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6322 |
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6323 instruct storeN0(memory dst, immN0 src) %{ |
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6324 match(Set dst (StoreN dst src)); |
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6325 ins_cost(MEMORY_REF_COST); |
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6326 size(4); |
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6327 |
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6328 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6329 ins_encode %{ |
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6330 Register base = as_Register($dst$$base); |
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6331 Register index = as_Register($dst$$index); |
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6332 if (index != G0) { |
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6333 __ stw(0, base, index); |
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6334 } else { |
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6335 __ stw(0, base, $dst$$disp); |
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6336 } |
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6337 %} |
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6338 ins_pipe(istore_mem_zero); |
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6339 %} |
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6340 |
0 | 6341 // Store Double |
6342 instruct storeD( memory mem, regD src) %{ | |
6343 match(Set mem (StoreD mem src)); | |
6344 ins_cost(MEMORY_REF_COST); | |
6345 | |
6346 size(4); | |
6347 format %{ "STDF $src,$mem" %} | |
6348 opcode(Assembler::stdf_op3); | |
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6349 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6350 ins_pipe(fstoreD_mem_reg); |
6351 %} | |
6352 | |
6353 instruct storeD0( memory mem, immD0 src) %{ | |
6354 match(Set mem (StoreD mem src)); | |
6355 ins_cost(MEMORY_REF_COST); | |
6356 | |
6357 size(4); | |
6358 format %{ "STX $src,$mem" %} | |
6359 opcode(Assembler::stx_op3); | |
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6360 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6361 ins_pipe(fstoreD_mem_zero); |
6362 %} | |
6363 | |
6364 // Store Float | |
6365 instruct storeF( memory mem, regF src) %{ | |
6366 match(Set mem (StoreF mem src)); | |
6367 ins_cost(MEMORY_REF_COST); | |
6368 | |
6369 size(4); | |
6370 format %{ "STF $src,$mem" %} | |
6371 opcode(Assembler::stf_op3); | |
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6372 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6373 ins_pipe(fstoreF_mem_reg); |
6374 %} | |
6375 | |
6376 instruct storeF0( memory mem, immF0 src) %{ | |
6377 match(Set mem (StoreF mem src)); | |
6378 ins_cost(MEMORY_REF_COST); | |
6379 | |
6380 size(4); | |
6381 format %{ "STW $src,$mem\t! storeF0" %} | |
6382 opcode(Assembler::stw_op3); | |
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6383 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6384 ins_pipe(fstoreF_mem_zero); |
6385 %} | |
6386 | |
6387 // Store Aligned Packed Bytes in Double register to memory | |
6388 instruct storeA8B(memory mem, regD src) %{ | |
6389 match(Set mem (Store8B mem src)); | |
6390 ins_cost(MEMORY_REF_COST); | |
6391 size(4); | |
6392 format %{ "STDF $src,$mem\t! packed8B" %} | |
6393 opcode(Assembler::stdf_op3); | |
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6394 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6395 ins_pipe(fstoreD_mem_reg); |
6396 %} | |
6397 | |
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6398 // Convert oop pointer into compressed form |
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6399 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
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6400 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
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6401 match(Set dst (EncodeP src)); |
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6402 format %{ "encode_heap_oop $src, $dst" %} |
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6403 ins_encode %{ |
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6404 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6405 %} |
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6406 ins_pipe(ialu_reg); |
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6407 %} |
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6408 |
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6409 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
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6410 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
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6411 match(Set dst (EncodeP src)); |
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6412 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6413 ins_encode %{ |
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6414 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6415 %} |
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6416 ins_pipe(ialu_reg); |
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6417 %} |
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6418 |
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6419 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
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6420 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6421 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
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6422 match(Set dst (DecodeN src)); |
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6423 format %{ "decode_heap_oop $src, $dst" %} |
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6424 ins_encode %{ |
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6425 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6426 %} |
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6427 ins_pipe(ialu_reg); |
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6428 %} |
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6429 |
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6430 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
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6431 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
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6432 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
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6433 match(Set dst (DecodeN src)); |
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6434 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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6435 ins_encode %{ |
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6436 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6437 %} |
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6438 ins_pipe(ialu_reg); |
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6439 %} |
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6440 |
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6441 |
0 | 6442 // Store Zero into Aligned Packed Bytes |
6443 instruct storeA8B0(memory mem, immI0 zero) %{ | |
6444 match(Set mem (Store8B mem zero)); | |
6445 ins_cost(MEMORY_REF_COST); | |
6446 size(4); | |
6447 format %{ "STX $zero,$mem\t! packed8B" %} | |
6448 opcode(Assembler::stx_op3); | |
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6449 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6450 ins_pipe(fstoreD_mem_zero); |
6451 %} | |
6452 | |
6453 // Store Aligned Packed Chars/Shorts in Double register to memory | |
6454 instruct storeA4C(memory mem, regD src) %{ | |
6455 match(Set mem (Store4C mem src)); | |
6456 ins_cost(MEMORY_REF_COST); | |
6457 size(4); | |
6458 format %{ "STDF $src,$mem\t! packed4C" %} | |
6459 opcode(Assembler::stdf_op3); | |
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6460 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6461 ins_pipe(fstoreD_mem_reg); |
6462 %} | |
6463 | |
6464 // Store Zero into Aligned Packed Chars/Shorts | |
6465 instruct storeA4C0(memory mem, immI0 zero) %{ | |
6466 match(Set mem (Store4C mem (Replicate4C zero))); | |
6467 ins_cost(MEMORY_REF_COST); | |
6468 size(4); | |
6469 format %{ "STX $zero,$mem\t! packed4C" %} | |
6470 opcode(Assembler::stx_op3); | |
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6471 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6472 ins_pipe(fstoreD_mem_zero); |
6473 %} | |
6474 | |
6475 // Store Aligned Packed Ints in Double register to memory | |
6476 instruct storeA2I(memory mem, regD src) %{ | |
6477 match(Set mem (Store2I mem src)); | |
6478 ins_cost(MEMORY_REF_COST); | |
6479 size(4); | |
6480 format %{ "STDF $src,$mem\t! packed2I" %} | |
6481 opcode(Assembler::stdf_op3); | |
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6482 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6483 ins_pipe(fstoreD_mem_reg); |
6484 %} | |
6485 | |
6486 // Store Zero into Aligned Packed Ints | |
6487 instruct storeA2I0(memory mem, immI0 zero) %{ | |
6488 match(Set mem (Store2I mem zero)); | |
6489 ins_cost(MEMORY_REF_COST); | |
6490 size(4); | |
6491 format %{ "STX $zero,$mem\t! packed2I" %} | |
6492 opcode(Assembler::stx_op3); | |
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6493 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6494 ins_pipe(fstoreD_mem_zero); |
6495 %} | |
6496 | |
6497 | |
6498 //----------MemBar Instructions----------------------------------------------- | |
6499 // Memory barrier flavors | |
6500 | |
6501 instruct membar_acquire() %{ | |
6502 match(MemBarAcquire); | |
6503 ins_cost(4*MEMORY_REF_COST); | |
6504 | |
6505 size(0); | |
6506 format %{ "MEMBAR-acquire" %} | |
6507 ins_encode( enc_membar_acquire ); | |
6508 ins_pipe(long_memory_op); | |
6509 %} | |
6510 | |
6511 instruct membar_acquire_lock() %{ | |
6512 match(MemBarAcquire); | |
6513 predicate(Matcher::prior_fast_lock(n)); | |
6514 ins_cost(0); | |
6515 | |
6516 size(0); | |
6517 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6518 ins_encode( ); | |
6519 ins_pipe(empty); | |
6520 %} | |
6521 | |
6522 instruct membar_release() %{ | |
6523 match(MemBarRelease); | |
6524 ins_cost(4*MEMORY_REF_COST); | |
6525 | |
6526 size(0); | |
6527 format %{ "MEMBAR-release" %} | |
6528 ins_encode( enc_membar_release ); | |
6529 ins_pipe(long_memory_op); | |
6530 %} | |
6531 | |
6532 instruct membar_release_lock() %{ | |
6533 match(MemBarRelease); | |
6534 predicate(Matcher::post_fast_unlock(n)); | |
6535 ins_cost(0); | |
6536 | |
6537 size(0); | |
6538 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6539 ins_encode( ); | |
6540 ins_pipe(empty); | |
6541 %} | |
6542 | |
6543 instruct membar_volatile() %{ | |
6544 match(MemBarVolatile); | |
6545 ins_cost(4*MEMORY_REF_COST); | |
6546 | |
6547 size(4); | |
6548 format %{ "MEMBAR-volatile" %} | |
6549 ins_encode( enc_membar_volatile ); | |
6550 ins_pipe(long_memory_op); | |
6551 %} | |
6552 | |
6553 instruct unnecessary_membar_volatile() %{ | |
6554 match(MemBarVolatile); | |
6555 predicate(Matcher::post_store_load_barrier(n)); | |
6556 ins_cost(0); | |
6557 | |
6558 size(0); | |
6559 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6560 ins_encode( ); | |
6561 ins_pipe(empty); | |
6562 %} | |
6563 | |
6564 //----------Register Move Instructions----------------------------------------- | |
6565 instruct roundDouble_nop(regD dst) %{ | |
6566 match(Set dst (RoundDouble dst)); | |
6567 ins_cost(0); | |
6568 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6569 ins_encode( ); | |
6570 ins_pipe(empty); | |
6571 %} | |
6572 | |
6573 | |
6574 instruct roundFloat_nop(regF dst) %{ | |
6575 match(Set dst (RoundFloat dst)); | |
6576 ins_cost(0); | |
6577 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6578 ins_encode( ); | |
6579 ins_pipe(empty); | |
6580 %} | |
6581 | |
6582 | |
6583 // Cast Index to Pointer for unsafe natives | |
6584 instruct castX2P(iRegX src, iRegP dst) %{ | |
6585 match(Set dst (CastX2P src)); | |
6586 | |
6587 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6588 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6589 ins_pipe(ialu_reg); | |
6590 %} | |
6591 | |
6592 // Cast Pointer to Index for unsafe natives | |
6593 instruct castP2X(iRegP src, iRegX dst) %{ | |
6594 match(Set dst (CastP2X src)); | |
6595 | |
6596 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6597 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6598 ins_pipe(ialu_reg); | |
6599 %} | |
6600 | |
6601 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6602 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6603 match(Set stkSlot src); // chain rule | |
6604 ins_cost(MEMORY_REF_COST); | |
6605 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6606 opcode(Assembler::stdf_op3); | |
415
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|
6607 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6608 ins_pipe(fstoreD_stk_reg); |
6609 %} | |
6610 | |
6611 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6612 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6613 match(Set dst stkSlot); // chain rule | |
6614 ins_cost(MEMORY_REF_COST); | |
6615 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6616 opcode(Assembler::lddf_op3); | |
415
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diff
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|
6617 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6618 ins_pipe(floadD_stk); |
6619 %} | |
6620 | |
6621 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6622 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6623 match(Set stkSlot src); // chain rule | |
6624 ins_cost(MEMORY_REF_COST); | |
6625 format %{ "STF $src,$stkSlot\t!stk" %} | |
6626 opcode(Assembler::stf_op3); | |
415
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235
diff
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|
6627 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6628 ins_pipe(fstoreF_stk_reg); |
6629 %} | |
6630 | |
6631 //----------Conditional Move--------------------------------------------------- | |
6632 // Conditional move | |
6633 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6634 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6635 ins_cost(150); | |
6636 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6637 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6638 ins_pipe(ialu_reg); | |
6639 %} | |
6640 | |
6641 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6642 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6643 ins_cost(140); | |
6644 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6645 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6646 ins_pipe(ialu_imm); | |
6647 %} | |
6648 | |
6649 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6650 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6651 ins_cost(150); | |
6652 size(4); | |
6653 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6654 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6655 ins_pipe(ialu_reg); | |
6656 %} | |
6657 | |
6658 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6659 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6660 ins_cost(140); | |
6661 size(4); | |
6662 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6663 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6664 ins_pipe(ialu_imm); | |
6665 %} | |
6666 | |
81
dee7a3f3dc9d
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never
parents:
0
diff
changeset
|
6667 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6668 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6669 ins_cost(150); | |
6670 size(4); | |
6671 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6672 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6673 ins_pipe(ialu_reg); | |
6674 %} | |
6675 | |
81
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0
diff
changeset
|
6676 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6677 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6678 ins_cost(140); | |
6679 size(4); | |
6680 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6681 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6682 ins_pipe(ialu_imm); | |
6683 %} | |
6684 | |
6685 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6686 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6687 ins_cost(150); | |
6688 size(4); | |
6689 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6690 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6691 ins_pipe(ialu_reg); | |
6692 %} | |
6693 | |
6694 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6695 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6696 ins_cost(140); | |
6697 size(4); | |
6698 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6699 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6700 ins_pipe(ialu_imm); | |
6701 %} | |
6702 | |
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|
6703 // Conditional move for RegN. Only cmov(reg,reg). |
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|
6704 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
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|
6705 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
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|
6706 ins_cost(150); |
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diff
changeset
|
6707 format %{ "MOV$cmp $pcc,$src,$dst" %} |
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diff
changeset
|
6708 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
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diff
changeset
|
6709 ins_pipe(ialu_reg); |
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|
6710 %} |
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kvn
parents:
163
diff
changeset
|
6711 |
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parents:
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diff
changeset
|
6712 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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diff
changeset
|
6713 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
c436414a719e
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changeset
|
6714 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
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changeset
|
6715 ins_cost(150); |
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diff
changeset
|
6716 size(4); |
c436414a719e
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parents:
163
diff
changeset
|
6717 format %{ "MOV$cmp $icc,$src,$dst" %} |
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kvn
parents:
163
diff
changeset
|
6718 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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parents:
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diff
changeset
|
6719 ins_pipe(ialu_reg); |
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diff
changeset
|
6720 %} |
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kvn
parents:
163
diff
changeset
|
6721 |
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kvn
parents:
163
diff
changeset
|
6722 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
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diff
changeset
|
6723 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
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kvn
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changeset
|
6724 ins_cost(150); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6725 size(4); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6726 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6727 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
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kvn
parents:
163
diff
changeset
|
6728 ins_pipe(ialu_reg); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6729 %} |
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diff
changeset
|
6730 |
0 | 6731 // Conditional move |
6732 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6733 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6734 ins_cost(150); | |
6735 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6736 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6737 ins_pipe(ialu_reg); | |
6738 %} | |
6739 | |
6740 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6741 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6742 ins_cost(140); | |
6743 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6744 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6745 ins_pipe(ialu_imm); | |
6746 %} | |
6747 | |
164
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163
diff
changeset
|
6748 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6749 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6750 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6751 ins_cost(150); | |
6752 | |
6753 size(4); | |
6754 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6755 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6756 ins_pipe(ialu_reg); | |
6757 %} | |
6758 | |
6759 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ | |
6760 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6761 ins_cost(140); | |
6762 | |
6763 size(4); | |
6764 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6765 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6766 ins_pipe(ialu_imm); | |
6767 %} | |
6768 | |
6769 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ | |
6770 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6771 ins_cost(150); | |
6772 size(4); | |
6773 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6774 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6775 ins_pipe(ialu_imm); | |
6776 %} | |
6777 | |
6778 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6779 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6780 ins_cost(140); | |
6781 size(4); | |
6782 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6783 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6784 ins_pipe(ialu_imm); | |
6785 %} | |
6786 | |
6787 // Conditional move | |
6788 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6789 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6790 ins_cost(150); | |
6791 opcode(0x101); | |
6792 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6793 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6794 ins_pipe(int_conditional_float_move); | |
6795 %} | |
6796 | |
6797 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6798 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6799 ins_cost(150); | |
6800 | |
6801 size(4); | |
6802 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6803 opcode(0x101); | |
6804 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6805 ins_pipe(int_conditional_float_move); | |
6806 %} | |
6807 | |
6808 // Conditional move, | |
6809 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6810 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6811 ins_cost(150); | |
6812 size(4); | |
6813 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6814 opcode(0x1); | |
6815 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6816 ins_pipe(int_conditional_double_move); | |
6817 %} | |
6818 | |
6819 // Conditional move | |
6820 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6821 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
6822 ins_cost(150); | |
6823 size(4); | |
6824 opcode(0x102); | |
6825 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6826 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6827 ins_pipe(int_conditional_double_move); | |
6828 %} | |
6829 | |
6830 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
6831 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
6832 ins_cost(150); | |
6833 | |
6834 size(4); | |
6835 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
6836 opcode(0x102); | |
6837 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6838 ins_pipe(int_conditional_double_move); | |
6839 %} | |
6840 | |
6841 // Conditional move, | |
6842 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
6843 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
6844 ins_cost(150); | |
6845 size(4); | |
6846 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
6847 opcode(0x2); | |
6848 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6849 ins_pipe(int_conditional_double_move); | |
6850 %} | |
6851 | |
6852 // Conditional move | |
6853 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
6854 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6855 ins_cost(150); | |
6856 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6857 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6858 ins_pipe(ialu_reg); | |
6859 %} | |
6860 | |
6861 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
6862 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6863 ins_cost(140); | |
6864 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6865 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6866 ins_pipe(ialu_imm); | |
6867 %} | |
6868 | |
6869 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
6870 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
6871 ins_cost(150); | |
6872 | |
6873 size(4); | |
6874 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
6875 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6876 ins_pipe(ialu_reg); | |
6877 %} | |
6878 | |
6879 | |
6880 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ | |
6881 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
6882 ins_cost(150); | |
6883 | |
6884 size(4); | |
6885 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
6886 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6887 ins_pipe(ialu_reg); | |
6888 %} | |
6889 | |
6890 | |
6891 | |
6892 //----------OS and Locking Instructions---------------------------------------- | |
6893 | |
6894 // This name is KNOWN by the ADLC and cannot be changed. | |
6895 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
6896 // for this guy. | |
6897 instruct tlsLoadP(g2RegP dst) %{ | |
6898 match(Set dst (ThreadLocal)); | |
6899 | |
6900 size(0); | |
6901 ins_cost(0); | |
6902 format %{ "# TLS is in G2" %} | |
6903 ins_encode( /*empty encoding*/ ); | |
6904 ins_pipe(ialu_none); | |
6905 %} | |
6906 | |
6907 instruct checkCastPP( iRegP dst ) %{ | |
6908 match(Set dst (CheckCastPP dst)); | |
6909 | |
6910 size(0); | |
6911 format %{ "# checkcastPP of $dst" %} | |
6912 ins_encode( /*empty encoding*/ ); | |
6913 ins_pipe(empty); | |
6914 %} | |
6915 | |
6916 | |
6917 instruct castPP( iRegP dst ) %{ | |
6918 match(Set dst (CastPP dst)); | |
6919 format %{ "# castPP of $dst" %} | |
6920 ins_encode( /*empty encoding*/ ); | |
6921 ins_pipe(empty); | |
6922 %} | |
6923 | |
6924 instruct castII( iRegI dst ) %{ | |
6925 match(Set dst (CastII dst)); | |
6926 format %{ "# castII of $dst" %} | |
6927 ins_encode( /*empty encoding*/ ); | |
6928 ins_cost(0); | |
6929 ins_pipe(empty); | |
6930 %} | |
6931 | |
6932 //----------Arithmetic Instructions-------------------------------------------- | |
6933 // Addition Instructions | |
6934 // Register Addition | |
6935 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
6936 match(Set dst (AddI src1 src2)); | |
6937 | |
6938 size(4); | |
6939 format %{ "ADD $src1,$src2,$dst" %} | |
6940 ins_encode %{ | |
6941 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
6942 %} | |
6943 ins_pipe(ialu_reg_reg); | |
6944 %} | |
6945 | |
6946 // Immediate Addition | |
6947 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
6948 match(Set dst (AddI src1 src2)); | |
6949 | |
6950 size(4); | |
6951 format %{ "ADD $src1,$src2,$dst" %} | |
6952 opcode(Assembler::add_op3, Assembler::arith_op); | |
6953 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
6954 ins_pipe(ialu_reg_imm); | |
6955 %} | |
6956 | |
6957 // Pointer Register Addition | |
6958 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
6959 match(Set dst (AddP src1 src2)); | |
6960 | |
6961 size(4); | |
6962 format %{ "ADD $src1,$src2,$dst" %} | |
6963 opcode(Assembler::add_op3, Assembler::arith_op); | |
6964 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
6965 ins_pipe(ialu_reg_reg); | |
6966 %} | |
6967 | |
6968 // Pointer Immediate Addition | |
6969 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
6970 match(Set dst (AddP src1 src2)); | |
6971 | |
6972 size(4); | |
6973 format %{ "ADD $src1,$src2,$dst" %} | |
6974 opcode(Assembler::add_op3, Assembler::arith_op); | |
6975 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
6976 ins_pipe(ialu_reg_imm); | |
6977 %} | |
6978 | |
6979 // Long Addition | |
6980 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
6981 match(Set dst (AddL src1 src2)); | |
6982 | |
6983 size(4); | |
6984 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
6985 opcode(Assembler::add_op3, Assembler::arith_op); | |
6986 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
6987 ins_pipe(ialu_reg_reg); | |
6988 %} | |
6989 | |
6990 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
6991 match(Set dst (AddL src1 con)); | |
6992 | |
6993 size(4); | |
6994 format %{ "ADD $src1,$con,$dst" %} | |
6995 opcode(Assembler::add_op3, Assembler::arith_op); | |
6996 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
6997 ins_pipe(ialu_reg_imm); | |
6998 %} | |
6999 | |
7000 //----------Conditional_store-------------------------------------------------- | |
7001 // Conditional-store of the updated heap-top. | |
7002 // Used during allocation of the shared heap. | |
7003 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7004 | |
7005 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7006 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7007 match(Set dst (LoadPLocked mem)); | |
7008 ins_cost(MEMORY_REF_COST); | |
7009 | |
7010 #ifndef _LP64 | |
7011 size(4); | |
7012 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7013 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7014 #else | |
7015 format %{ "LDX $mem,$dst\t! ptr" %} | |
7016 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7017 #endif | |
7018 ins_encode( form3_mem_reg( mem, dst ) ); | |
7019 ins_pipe(iload_mem); | |
7020 %} | |
7021 | |
7022 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
7023 instruct loadLLocked(iRegL dst, memory mem) %{ | |
7024 match(Set dst (LoadLLocked mem)); | |
7025 ins_cost(MEMORY_REF_COST); | |
7026 size(4); | |
7027 format %{ "LDX $mem,$dst\t! long" %} | |
7028 opcode(Assembler::ldx_op3); | |
415
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7029 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 7030 ins_pipe(iload_mem); |
7031 %} | |
7032 | |
7033 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7034 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7035 effect( KILL newval ); | |
7036 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7037 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7038 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7039 ins_pipe( long_memory_op ); | |
7040 %} | |
7041 | |
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7042 // Conditional-store of an int value. |
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7043 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
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7044 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
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7045 effect( KILL newval ); |
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7046 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7047 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7048 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7049 ins_pipe( long_memory_op ); |
7050 %} | |
7051 | |
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7052 // Conditional-store of a long value. |
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7053 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
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7054 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
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7055 effect( KILL newval ); |
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7056 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7057 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7058 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7059 ins_pipe( long_memory_op ); |
7060 %} | |
7061 | |
7062 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7063 | |
7064 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7065 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
7066 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7067 format %{ | |
7068 "MOV $newval,O7\n\t" | |
7069 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7070 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7071 "MOV 1,$res\n\t" | |
7072 "MOVne xcc,R_G0,$res" | |
7073 %} | |
7074 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7075 enc_lflags_ne_to_boolean(res) ); | |
7076 ins_pipe( long_memory_op ); | |
7077 %} | |
7078 | |
7079 | |
7080 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7081 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7082 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7083 format %{ | |
7084 "MOV $newval,O7\n\t" | |
7085 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7086 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7087 "MOV 1,$res\n\t" | |
7088 "MOVne icc,R_G0,$res" | |
7089 %} | |
7090 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7091 enc_iflags_ne_to_boolean(res) ); | |
7092 ins_pipe( long_memory_op ); | |
7093 %} | |
7094 | |
7095 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7096 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
7097 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7098 format %{ | |
7099 "MOV $newval,O7\n\t" | |
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7100 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7101 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7102 "MOV 1,$res\n\t" | |
7103 "MOVne xcc,R_G0,$res" | |
7104 %} | |
113
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7105 #ifdef _LP64 |
0 | 7106 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7107 enc_lflags_ne_to_boolean(res) ); | |
7108 #else | |
113
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7109 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7110 enc_iflags_ne_to_boolean(res) ); |
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7111 #endif |
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7112 ins_pipe( long_memory_op ); |
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7113 %} |
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7114 |
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7115 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
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7116 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7117 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7118 format %{ |
7119 "MOV $newval,O7\n\t" | |
7120 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7121 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7122 "MOV 1,$res\n\t" | |
7123 "MOVne icc,R_G0,$res" | |
7124 %} | |
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7125 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7126 enc_iflags_ne_to_boolean(res) ); |
0 | 7127 ins_pipe( long_memory_op ); |
7128 %} | |
7129 | |
7130 //--------------------- | |
7131 // Subtraction Instructions | |
7132 // Register Subtraction | |
7133 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7134 match(Set dst (SubI src1 src2)); | |
7135 | |
7136 size(4); | |
7137 format %{ "SUB $src1,$src2,$dst" %} | |
7138 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7139 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7140 ins_pipe(ialu_reg_reg); | |
7141 %} | |
7142 | |
7143 // Immediate Subtraction | |
7144 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7145 match(Set dst (SubI src1 src2)); | |
7146 | |
7147 size(4); | |
7148 format %{ "SUB $src1,$src2,$dst" %} | |
7149 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7150 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7151 ins_pipe(ialu_reg_imm); | |
7152 %} | |
7153 | |
7154 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7155 match(Set dst (SubI zero src2)); | |
7156 | |
7157 size(4); | |
7158 format %{ "NEG $src2,$dst" %} | |
7159 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7160 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7161 ins_pipe(ialu_zero_reg); | |
7162 %} | |
7163 | |
7164 // Long subtraction | |
7165 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7166 match(Set dst (SubL src1 src2)); | |
7167 | |
7168 size(4); | |
7169 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7170 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7171 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7172 ins_pipe(ialu_reg_reg); | |
7173 %} | |
7174 | |
7175 // Immediate Subtraction | |
7176 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7177 match(Set dst (SubL src1 con)); | |
7178 | |
7179 size(4); | |
7180 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7181 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7182 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7183 ins_pipe(ialu_reg_imm); | |
7184 %} | |
7185 | |
7186 // Long negation | |
7187 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7188 match(Set dst (SubL zero src2)); | |
7189 | |
7190 size(4); | |
7191 format %{ "NEG $src2,$dst\t! long" %} | |
7192 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7193 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7194 ins_pipe(ialu_zero_reg); | |
7195 %} | |
7196 | |
7197 // Multiplication Instructions | |
7198 // Integer Multiplication | |
7199 // Register Multiplication | |
7200 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7201 match(Set dst (MulI src1 src2)); | |
7202 | |
7203 size(4); | |
7204 format %{ "MULX $src1,$src2,$dst" %} | |
7205 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7206 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7207 ins_pipe(imul_reg_reg); | |
7208 %} | |
7209 | |
7210 // Immediate Multiplication | |
7211 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7212 match(Set dst (MulI src1 src2)); | |
7213 | |
7214 size(4); | |
7215 format %{ "MULX $src1,$src2,$dst" %} | |
7216 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7217 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7218 ins_pipe(imul_reg_imm); | |
7219 %} | |
7220 | |
7221 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7222 match(Set dst (MulL src1 src2)); | |
7223 ins_cost(DEFAULT_COST * 5); | |
7224 size(4); | |
7225 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7226 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7227 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7228 ins_pipe(mulL_reg_reg); | |
7229 %} | |
7230 | |
7231 // Immediate Multiplication | |
7232 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7233 match(Set dst (MulL src1 src2)); | |
7234 ins_cost(DEFAULT_COST * 5); | |
7235 size(4); | |
7236 format %{ "MULX $src1,$src2,$dst" %} | |
7237 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7238 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7239 ins_pipe(mulL_reg_imm); | |
7240 %} | |
7241 | |
7242 // Integer Division | |
7243 // Register Division | |
7244 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7245 match(Set dst (DivI src1 src2)); | |
7246 ins_cost((2+71)*DEFAULT_COST); | |
7247 | |
7248 format %{ "SRA $src2,0,$src2\n\t" | |
7249 "SRA $src1,0,$src1\n\t" | |
7250 "SDIVX $src1,$src2,$dst" %} | |
7251 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7252 ins_pipe(sdiv_reg_reg); | |
7253 %} | |
7254 | |
7255 // Immediate Division | |
7256 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7257 match(Set dst (DivI src1 src2)); | |
7258 ins_cost((2+71)*DEFAULT_COST); | |
7259 | |
7260 format %{ "SRA $src1,0,$src1\n\t" | |
7261 "SDIVX $src1,$src2,$dst" %} | |
7262 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7263 ins_pipe(sdiv_reg_imm); | |
7264 %} | |
7265 | |
7266 //----------Div-By-10-Expansion------------------------------------------------ | |
7267 // Extract hi bits of a 32x32->64 bit multiply. | |
7268 // Expand rule only, not matched | |
7269 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7270 effect( DEF dst, USE src1, USE src2 ); | |
7271 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7272 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7273 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7274 ins_pipe(sdiv_reg_reg); | |
7275 %} | |
7276 | |
605 | 7277 // Magic constant, reciprocal of 10 |
0 | 7278 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7279 effect( DEF dst ); | |
7280 | |
7281 size(8); | |
7282 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7283 ins_encode( Set32(0x66666667, dst) ); | |
7284 ins_pipe(ialu_hi_lo_reg); | |
7285 %} | |
7286 | |
605 | 7287 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7288 instruct sra_31( iRegI dst, iRegI src ) %{ |
7289 effect( DEF dst, USE src ); | |
7290 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7291 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7292 ins_pipe(ialu_reg_reg); | |
7293 %} | |
7294 | |
7295 // Arithmetic Shift Right by 8-bit immediate | |
7296 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7297 effect( DEF dst, USE src ); | |
7298 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7299 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7300 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7301 ins_pipe(ialu_reg_imm); | |
7302 %} | |
7303 | |
7304 // Integer DIV with 10 | |
7305 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7306 match(Set dst (DivI src div)); | |
7307 ins_cost((6+6)*DEFAULT_COST); | |
7308 expand %{ | |
7309 iRegIsafe tmp1; // Killed temps; | |
7310 iRegIsafe tmp2; // Killed temps; | |
7311 iRegI tmp3; // Killed temps; | |
7312 iRegI tmp4; // Killed temps; | |
7313 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7314 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7315 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7316 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7317 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7318 %} | |
7319 %} | |
7320 | |
7321 // Register Long Division | |
7322 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7323 match(Set dst (DivL src1 src2)); | |
7324 ins_cost(DEFAULT_COST*71); | |
7325 size(4); | |
7326 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7327 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7328 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7329 ins_pipe(divL_reg_reg); | |
7330 %} | |
7331 | |
7332 // Register Long Division | |
7333 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7334 match(Set dst (DivL src1 src2)); | |
7335 ins_cost(DEFAULT_COST*71); | |
7336 size(4); | |
7337 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7338 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7339 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7340 ins_pipe(divL_reg_imm); | |
7341 %} | |
7342 | |
7343 // Integer Remainder | |
7344 // Register Remainder | |
7345 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7346 match(Set dst (ModI src1 src2)); | |
7347 effect( KILL ccr, KILL temp); | |
7348 | |
7349 format %{ "SREM $src1,$src2,$dst" %} | |
7350 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7351 ins_pipe(sdiv_reg_reg); | |
7352 %} | |
7353 | |
7354 // Immediate Remainder | |
7355 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7356 match(Set dst (ModI src1 src2)); | |
7357 effect( KILL ccr, KILL temp); | |
7358 | |
7359 format %{ "SREM $src1,$src2,$dst" %} | |
7360 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7361 ins_pipe(sdiv_reg_imm); | |
7362 %} | |
7363 | |
7364 // Register Long Remainder | |
7365 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7366 effect(DEF dst, USE src1, USE src2); | |
7367 size(4); | |
7368 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7369 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7370 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7371 ins_pipe(divL_reg_reg); | |
7372 %} | |
7373 | |
7374 // Register Long Division | |
7375 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7376 effect(DEF dst, USE src1, USE src2); | |
7377 size(4); | |
7378 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7379 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7380 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7381 ins_pipe(divL_reg_imm); | |
7382 %} | |
7383 | |
7384 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7385 effect(DEF dst, USE src1, USE src2); | |
7386 size(4); | |
7387 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7388 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7389 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7390 ins_pipe(mulL_reg_reg); | |
7391 %} | |
7392 | |
7393 // Immediate Multiplication | |
7394 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7395 effect(DEF dst, USE src1, USE src2); | |
7396 size(4); | |
7397 format %{ "MULX $src1,$src2,$dst" %} | |
7398 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7399 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7400 ins_pipe(mulL_reg_imm); | |
7401 %} | |
7402 | |
7403 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7404 effect(DEF dst, USE src1, USE src2); | |
7405 size(4); | |
7406 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7407 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7408 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7409 ins_pipe(ialu_reg_reg); | |
7410 %} | |
7411 | |
7412 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7413 effect(DEF dst, USE src1, USE src2); | |
7414 size(4); | |
7415 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7416 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7417 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7418 ins_pipe(ialu_reg_reg); | |
7419 %} | |
7420 | |
7421 // Register Long Remainder | |
7422 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7423 match(Set dst (ModL src1 src2)); | |
7424 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7425 expand %{ | |
7426 iRegL tmp1; | |
7427 iRegL tmp2; | |
7428 divL_reg_reg_1(tmp1, src1, src2); | |
7429 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7430 subL_reg_reg_1(dst, src1, tmp2); | |
7431 %} | |
7432 %} | |
7433 | |
7434 // Register Long Remainder | |
7435 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7436 match(Set dst (ModL src1 src2)); | |
7437 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7438 expand %{ | |
7439 iRegL tmp1; | |
7440 iRegL tmp2; | |
7441 divL_reg_imm13_1(tmp1, src1, src2); | |
7442 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7443 subL_reg_reg_2 (dst, src1, tmp2); | |
7444 %} | |
7445 %} | |
7446 | |
7447 // Integer Shift Instructions | |
7448 // Register Shift Left | |
7449 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7450 match(Set dst (LShiftI src1 src2)); | |
7451 | |
7452 size(4); | |
7453 format %{ "SLL $src1,$src2,$dst" %} | |
7454 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7455 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7456 ins_pipe(ialu_reg_reg); | |
7457 %} | |
7458 | |
7459 // Register Shift Left Immediate | |
7460 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7461 match(Set dst (LShiftI src1 src2)); | |
7462 | |
7463 size(4); | |
7464 format %{ "SLL $src1,$src2,$dst" %} | |
7465 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7466 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7467 ins_pipe(ialu_reg_imm); | |
7468 %} | |
7469 | |
7470 // Register Shift Left | |
7471 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7472 match(Set dst (LShiftL src1 src2)); | |
7473 | |
7474 size(4); | |
7475 format %{ "SLLX $src1,$src2,$dst" %} | |
7476 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7477 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7478 ins_pipe(ialu_reg_reg); | |
7479 %} | |
7480 | |
7481 // Register Shift Left Immediate | |
7482 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7483 match(Set dst (LShiftL src1 src2)); | |
7484 | |
7485 size(4); | |
7486 format %{ "SLLX $src1,$src2,$dst" %} | |
7487 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7488 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7489 ins_pipe(ialu_reg_imm); | |
7490 %} | |
7491 | |
7492 // Register Arithmetic Shift Right | |
7493 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7494 match(Set dst (RShiftI src1 src2)); | |
7495 size(4); | |
7496 format %{ "SRA $src1,$src2,$dst" %} | |
7497 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7498 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7499 ins_pipe(ialu_reg_reg); | |
7500 %} | |
7501 | |
7502 // Register Arithmetic Shift Right Immediate | |
7503 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7504 match(Set dst (RShiftI src1 src2)); | |
7505 | |
7506 size(4); | |
7507 format %{ "SRA $src1,$src2,$dst" %} | |
7508 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7509 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7510 ins_pipe(ialu_reg_imm); | |
7511 %} | |
7512 | |
7513 // Register Shift Right Arithmatic Long | |
7514 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7515 match(Set dst (RShiftL src1 src2)); | |
7516 | |
7517 size(4); | |
7518 format %{ "SRAX $src1,$src2,$dst" %} | |
7519 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7520 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7521 ins_pipe(ialu_reg_reg); | |
7522 %} | |
7523 | |
7524 // Register Shift Left Immediate | |
7525 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7526 match(Set dst (RShiftL src1 src2)); | |
7527 | |
7528 size(4); | |
7529 format %{ "SRAX $src1,$src2,$dst" %} | |
7530 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7531 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7532 ins_pipe(ialu_reg_imm); | |
7533 %} | |
7534 | |
7535 // Register Shift Right | |
7536 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7537 match(Set dst (URShiftI src1 src2)); | |
7538 | |
7539 size(4); | |
7540 format %{ "SRL $src1,$src2,$dst" %} | |
7541 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7542 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7543 ins_pipe(ialu_reg_reg); | |
7544 %} | |
7545 | |
7546 // Register Shift Right Immediate | |
7547 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7548 match(Set dst (URShiftI src1 src2)); | |
7549 | |
7550 size(4); | |
7551 format %{ "SRL $src1,$src2,$dst" %} | |
7552 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7553 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7554 ins_pipe(ialu_reg_imm); | |
7555 %} | |
7556 | |
7557 // Register Shift Right | |
7558 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7559 match(Set dst (URShiftL src1 src2)); | |
7560 | |
7561 size(4); | |
7562 format %{ "SRLX $src1,$src2,$dst" %} | |
7563 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7564 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7565 ins_pipe(ialu_reg_reg); | |
7566 %} | |
7567 | |
7568 // Register Shift Right Immediate | |
7569 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7570 match(Set dst (URShiftL src1 src2)); | |
7571 | |
7572 size(4); | |
7573 format %{ "SRLX $src1,$src2,$dst" %} | |
7574 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7575 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7576 ins_pipe(ialu_reg_imm); | |
7577 %} | |
7578 | |
7579 // Register Shift Right Immediate with a CastP2X | |
7580 #ifdef _LP64 | |
7581 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7582 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7583 size(4); | |
7584 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7585 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7586 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7587 ins_pipe(ialu_reg_imm); | |
7588 %} | |
7589 #else | |
7590 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7591 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7592 size(4); | |
7593 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7594 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7595 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7596 ins_pipe(ialu_reg_imm); | |
7597 %} | |
7598 #endif | |
7599 | |
7600 | |
7601 //----------Floating Point Arithmetic Instructions----------------------------- | |
7602 | |
7603 // Add float single precision | |
7604 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7605 match(Set dst (AddF src1 src2)); | |
7606 | |
7607 size(4); | |
7608 format %{ "FADDS $src1,$src2,$dst" %} | |
7609 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7610 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7611 ins_pipe(faddF_reg_reg); | |
7612 %} | |
7613 | |
7614 // Add float double precision | |
7615 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7616 match(Set dst (AddD src1 src2)); | |
7617 | |
7618 size(4); | |
7619 format %{ "FADDD $src1,$src2,$dst" %} | |
7620 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7621 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7622 ins_pipe(faddD_reg_reg); | |
7623 %} | |
7624 | |
7625 // Sub float single precision | |
7626 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7627 match(Set dst (SubF src1 src2)); | |
7628 | |
7629 size(4); | |
7630 format %{ "FSUBS $src1,$src2,$dst" %} | |
7631 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7632 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7633 ins_pipe(faddF_reg_reg); | |
7634 %} | |
7635 | |
7636 // Sub float double precision | |
7637 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7638 match(Set dst (SubD src1 src2)); | |
7639 | |
7640 size(4); | |
7641 format %{ "FSUBD $src1,$src2,$dst" %} | |
7642 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7643 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7644 ins_pipe(faddD_reg_reg); | |
7645 %} | |
7646 | |
7647 // Mul float single precision | |
7648 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7649 match(Set dst (MulF src1 src2)); | |
7650 | |
7651 size(4); | |
7652 format %{ "FMULS $src1,$src2,$dst" %} | |
7653 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7654 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7655 ins_pipe(fmulF_reg_reg); | |
7656 %} | |
7657 | |
7658 // Mul float double precision | |
7659 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7660 match(Set dst (MulD src1 src2)); | |
7661 | |
7662 size(4); | |
7663 format %{ "FMULD $src1,$src2,$dst" %} | |
7664 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7665 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7666 ins_pipe(fmulD_reg_reg); | |
7667 %} | |
7668 | |
7669 // Div float single precision | |
7670 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7671 match(Set dst (DivF src1 src2)); | |
7672 | |
7673 size(4); | |
7674 format %{ "FDIVS $src1,$src2,$dst" %} | |
7675 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7676 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7677 ins_pipe(fdivF_reg_reg); | |
7678 %} | |
7679 | |
7680 // Div float double precision | |
7681 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7682 match(Set dst (DivD src1 src2)); | |
7683 | |
7684 size(4); | |
7685 format %{ "FDIVD $src1,$src2,$dst" %} | |
7686 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7687 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7688 ins_pipe(fdivD_reg_reg); | |
7689 %} | |
7690 | |
7691 // Absolute float double precision | |
7692 instruct absD_reg(regD dst, regD src) %{ | |
7693 match(Set dst (AbsD src)); | |
7694 | |
7695 format %{ "FABSd $src,$dst" %} | |
7696 ins_encode(fabsd(dst, src)); | |
7697 ins_pipe(faddD_reg); | |
7698 %} | |
7699 | |
7700 // Absolute float single precision | |
7701 instruct absF_reg(regF dst, regF src) %{ | |
7702 match(Set dst (AbsF src)); | |
7703 | |
7704 format %{ "FABSs $src,$dst" %} | |
7705 ins_encode(fabss(dst, src)); | |
7706 ins_pipe(faddF_reg); | |
7707 %} | |
7708 | |
7709 instruct negF_reg(regF dst, regF src) %{ | |
7710 match(Set dst (NegF src)); | |
7711 | |
7712 size(4); | |
7713 format %{ "FNEGs $src,$dst" %} | |
7714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7715 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7716 ins_pipe(faddF_reg); | |
7717 %} | |
7718 | |
7719 instruct negD_reg(regD dst, regD src) %{ | |
7720 match(Set dst (NegD src)); | |
7721 | |
7722 format %{ "FNEGd $src,$dst" %} | |
7723 ins_encode(fnegd(dst, src)); | |
7724 ins_pipe(faddD_reg); | |
7725 %} | |
7726 | |
7727 // Sqrt float double precision | |
7728 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7729 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7730 | |
7731 size(4); | |
7732 format %{ "FSQRTS $src,$dst" %} | |
7733 ins_encode(fsqrts(dst, src)); | |
7734 ins_pipe(fdivF_reg_reg); | |
7735 %} | |
7736 | |
7737 // Sqrt float double precision | |
7738 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7739 match(Set dst (SqrtD src)); | |
7740 | |
7741 size(4); | |
7742 format %{ "FSQRTD $src,$dst" %} | |
7743 ins_encode(fsqrtd(dst, src)); | |
7744 ins_pipe(fdivD_reg_reg); | |
7745 %} | |
7746 | |
7747 //----------Logical Instructions----------------------------------------------- | |
7748 // And Instructions | |
7749 // Register And | |
7750 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7751 match(Set dst (AndI src1 src2)); | |
7752 | |
7753 size(4); | |
7754 format %{ "AND $src1,$src2,$dst" %} | |
7755 opcode(Assembler::and_op3, Assembler::arith_op); | |
7756 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7757 ins_pipe(ialu_reg_reg); | |
7758 %} | |
7759 | |
7760 // Immediate And | |
7761 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7762 match(Set dst (AndI src1 src2)); | |
7763 | |
7764 size(4); | |
7765 format %{ "AND $src1,$src2,$dst" %} | |
7766 opcode(Assembler::and_op3, Assembler::arith_op); | |
7767 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7768 ins_pipe(ialu_reg_imm); | |
7769 %} | |
7770 | |
7771 // Register And Long | |
7772 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7773 match(Set dst (AndL src1 src2)); | |
7774 | |
7775 ins_cost(DEFAULT_COST); | |
7776 size(4); | |
7777 format %{ "AND $src1,$src2,$dst\t! long" %} | |
7778 opcode(Assembler::and_op3, Assembler::arith_op); | |
7779 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7780 ins_pipe(ialu_reg_reg); | |
7781 %} | |
7782 | |
7783 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7784 match(Set dst (AndL src1 con)); | |
7785 | |
7786 ins_cost(DEFAULT_COST); | |
7787 size(4); | |
7788 format %{ "AND $src1,$con,$dst\t! long" %} | |
7789 opcode(Assembler::and_op3, Assembler::arith_op); | |
7790 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7791 ins_pipe(ialu_reg_imm); | |
7792 %} | |
7793 | |
7794 // Or Instructions | |
7795 // Register Or | |
7796 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7797 match(Set dst (OrI src1 src2)); | |
7798 | |
7799 size(4); | |
7800 format %{ "OR $src1,$src2,$dst" %} | |
7801 opcode(Assembler::or_op3, Assembler::arith_op); | |
7802 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7803 ins_pipe(ialu_reg_reg); | |
7804 %} | |
7805 | |
7806 // Immediate Or | |
7807 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7808 match(Set dst (OrI src1 src2)); | |
7809 | |
7810 size(4); | |
7811 format %{ "OR $src1,$src2,$dst" %} | |
7812 opcode(Assembler::or_op3, Assembler::arith_op); | |
7813 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7814 ins_pipe(ialu_reg_imm); | |
7815 %} | |
7816 | |
7817 // Register Or Long | |
7818 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7819 match(Set dst (OrL src1 src2)); | |
7820 | |
7821 ins_cost(DEFAULT_COST); | |
7822 size(4); | |
7823 format %{ "OR $src1,$src2,$dst\t! long" %} | |
7824 opcode(Assembler::or_op3, Assembler::arith_op); | |
7825 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7826 ins_pipe(ialu_reg_reg); | |
7827 %} | |
7828 | |
7829 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7830 match(Set dst (OrL src1 con)); | |
7831 ins_cost(DEFAULT_COST*2); | |
7832 | |
7833 ins_cost(DEFAULT_COST); | |
7834 size(4); | |
7835 format %{ "OR $src1,$con,$dst\t! long" %} | |
7836 opcode(Assembler::or_op3, Assembler::arith_op); | |
7837 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7838 ins_pipe(ialu_reg_imm); | |
7839 %} | |
7840 | |
420
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7841 #ifndef _LP64 |
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7842 |
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7843 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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7844 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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7845 match(Set dst (OrI src1 (CastP2X src2))); |
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7846 |
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7847 size(4); |
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7848 format %{ "OR $src1,$src2,$dst" %} |
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7849 opcode(Assembler::or_op3, Assembler::arith_op); |
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7850 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7851 ins_pipe(ialu_reg_reg); |
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7852 %} |
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7853 |
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7854 #else |
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7855 |
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7856 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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7857 match(Set dst (OrL src1 (CastP2X src2))); |
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7858 |
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7859 ins_cost(DEFAULT_COST); |
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7860 size(4); |
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7861 format %{ "OR $src1,$src2,$dst\t! long" %} |
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7862 opcode(Assembler::or_op3, Assembler::arith_op); |
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7863 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7864 ins_pipe(ialu_reg_reg); |
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7865 %} |
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7866 |
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7867 #endif |
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7868 |
0 | 7869 // Xor Instructions |
7870 // Register Xor | |
7871 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7872 match(Set dst (XorI src1 src2)); | |
7873 | |
7874 size(4); | |
7875 format %{ "XOR $src1,$src2,$dst" %} | |
7876 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7877 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7878 ins_pipe(ialu_reg_reg); | |
7879 %} | |
7880 | |
7881 // Immediate Xor | |
7882 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7883 match(Set dst (XorI src1 src2)); | |
7884 | |
7885 size(4); | |
7886 format %{ "XOR $src1,$src2,$dst" %} | |
7887 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7888 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7889 ins_pipe(ialu_reg_imm); | |
7890 %} | |
7891 | |
7892 // Register Xor Long | |
7893 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7894 match(Set dst (XorL src1 src2)); | |
7895 | |
7896 ins_cost(DEFAULT_COST); | |
7897 size(4); | |
7898 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
7899 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7900 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7901 ins_pipe(ialu_reg_reg); | |
7902 %} | |
7903 | |
7904 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7905 match(Set dst (XorL src1 con)); | |
7906 | |
7907 ins_cost(DEFAULT_COST); | |
7908 size(4); | |
7909 format %{ "XOR $src1,$con,$dst\t! long" %} | |
7910 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7911 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7912 ins_pipe(ialu_reg_imm); | |
7913 %} | |
7914 | |
7915 //----------Convert to Boolean------------------------------------------------- | |
7916 // Nice hack for 32-bit tests but doesn't work for | |
7917 // 64-bit pointers. | |
7918 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
7919 match(Set dst (Conv2B src)); | |
7920 effect( KILL ccr ); | |
7921 ins_cost(DEFAULT_COST*2); | |
7922 format %{ "CMP R_G0,$src\n\t" | |
7923 "ADDX R_G0,0,$dst" %} | |
7924 ins_encode( enc_to_bool( src, dst ) ); | |
7925 ins_pipe(ialu_reg_ialu); | |
7926 %} | |
7927 | |
7928 #ifndef _LP64 | |
7929 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
7930 match(Set dst (Conv2B src)); | |
7931 effect( KILL ccr ); | |
7932 ins_cost(DEFAULT_COST*2); | |
7933 format %{ "CMP R_G0,$src\n\t" | |
7934 "ADDX R_G0,0,$dst" %} | |
7935 ins_encode( enc_to_bool( src, dst ) ); | |
7936 ins_pipe(ialu_reg_ialu); | |
7937 %} | |
7938 #else | |
7939 instruct convP2B( iRegI dst, iRegP src ) %{ | |
7940 match(Set dst (Conv2B src)); | |
7941 ins_cost(DEFAULT_COST*2); | |
7942 format %{ "MOV $src,$dst\n\t" | |
7943 "MOVRNZ $src,1,$dst" %} | |
7944 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
7945 ins_pipe(ialu_clr_and_mover); | |
7946 %} | |
7947 #endif | |
7948 | |
7949 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
7950 match(Set dst (CmpLTMask p q)); | |
7951 effect( KILL ccr ); | |
7952 ins_cost(DEFAULT_COST*4); | |
7953 format %{ "CMP $p,$q\n\t" | |
7954 "MOV #0,$dst\n\t" | |
7955 "BLT,a .+8\n\t" | |
7956 "MOV #-1,$dst" %} | |
7957 ins_encode( enc_ltmask(p,q,dst) ); | |
7958 ins_pipe(ialu_reg_reg_ialu); | |
7959 %} | |
7960 | |
7961 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
7962 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
7963 effect(KILL ccr, TEMP tmp); | |
7964 ins_cost(DEFAULT_COST*3); | |
7965 | |
7966 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
7967 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
7968 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
7969 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
7970 ins_pipe( cadd_cmpltmask ); | |
7971 %} | |
7972 | |
7973 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
7974 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
7975 effect( KILL ccr, TEMP tmp); | |
7976 ins_cost(DEFAULT_COST*3); | |
7977 | |
7978 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
7979 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
7980 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
7981 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
7982 ins_pipe( cadd_cmpltmask ); | |
7983 %} | |
7984 | |
7985 //----------Arithmetic Conversion Instructions--------------------------------- | |
7986 // The conversions operations are all Alpha sorted. Please keep it that way! | |
7987 | |
7988 instruct convD2F_reg(regF dst, regD src) %{ | |
7989 match(Set dst (ConvD2F src)); | |
7990 size(4); | |
7991 format %{ "FDTOS $src,$dst" %} | |
7992 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
7993 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
7994 ins_pipe(fcvtD2F); | |
7995 %} | |
7996 | |
7997 | |
7998 // Convert a double to an int in a float register. | |
7999 // If the double is a NAN, stuff a zero in instead. | |
8000 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8001 effect(DEF dst, USE src, KILL fcc0); | |
8002 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8003 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8004 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8005 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8006 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8007 "skip:" %} | |
8008 ins_encode(form_d2i_helper(src,dst)); | |
8009 ins_pipe(fcvtD2I); | |
8010 %} | |
8011 | |
8012 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
8013 match(Set dst (ConvD2I src)); | |
8014 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8015 expand %{ | |
8016 regF tmp; | |
8017 convD2I_helper(tmp, src); | |
8018 regF_to_stkI(dst, tmp); | |
8019 %} | |
8020 %} | |
8021 | |
8022 // Convert a double to a long in a double register. | |
8023 // If the double is a NAN, stuff a zero in instead. | |
8024 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8025 effect(DEF dst, USE src, KILL fcc0); | |
8026 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8027 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8028 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8029 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8030 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8031 "skip:" %} | |
8032 ins_encode(form_d2l_helper(src,dst)); | |
8033 ins_pipe(fcvtD2L); | |
8034 %} | |
8035 | |
8036 | |
8037 // Double to Long conversion | |
8038 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
8039 match(Set dst (ConvD2L src)); | |
8040 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8041 expand %{ | |
8042 regD tmp; | |
8043 convD2L_helper(tmp, src); | |
8044 regD_to_stkL(dst, tmp); | |
8045 %} | |
8046 %} | |
8047 | |
8048 | |
8049 instruct convF2D_reg(regD dst, regF src) %{ | |
8050 match(Set dst (ConvF2D src)); | |
8051 format %{ "FSTOD $src,$dst" %} | |
8052 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8053 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8054 ins_pipe(fcvtF2D); | |
8055 %} | |
8056 | |
8057 | |
8058 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8059 effect(DEF dst, USE src, KILL fcc0); | |
8060 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8061 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8062 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8063 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8064 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8065 "skip:" %} | |
8066 ins_encode(form_f2i_helper(src,dst)); | |
8067 ins_pipe(fcvtF2I); | |
8068 %} | |
8069 | |
8070 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
8071 match(Set dst (ConvF2I src)); | |
8072 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8073 expand %{ | |
8074 regF tmp; | |
8075 convF2I_helper(tmp, src); | |
8076 regF_to_stkI(dst, tmp); | |
8077 %} | |
8078 %} | |
8079 | |
8080 | |
8081 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8082 effect(DEF dst, USE src, KILL fcc0); | |
8083 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8084 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8085 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8086 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8087 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8088 "skip:" %} | |
8089 ins_encode(form_f2l_helper(src,dst)); | |
8090 ins_pipe(fcvtF2L); | |
8091 %} | |
8092 | |
8093 // Float to Long conversion | |
8094 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
8095 match(Set dst (ConvF2L src)); | |
8096 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8097 expand %{ | |
8098 regD tmp; | |
8099 convF2L_helper(tmp, src); | |
8100 regD_to_stkL(dst, tmp); | |
8101 %} | |
8102 %} | |
8103 | |
8104 | |
8105 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8106 effect(USE tmp, DEF dst); | |
8107 format %{ "FITOD $tmp,$dst" %} | |
8108 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8109 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8110 ins_pipe(fcvtI2D); | |
8111 %} | |
8112 | |
8113 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
8114 match(Set dst (ConvI2D src)); | |
8115 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8116 expand %{ | |
8117 regF tmp; | |
8118 stkI_to_regF( tmp, src); | |
8119 convI2D_helper( dst, tmp); | |
8120 %} | |
8121 %} | |
8122 | |
8123 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
8124 match(Set dst (ConvI2D (LoadI mem))); | |
8125 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8126 size(8); | |
8127 format %{ "LDF $mem,$dst\n\t" | |
8128 "FITOD $dst,$dst" %} | |
8129 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
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8130 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8131 ins_pipe(floadF_mem); |
8132 %} | |
8133 | |
8134 | |
8135 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8136 effect(DEF dst, USE tmp); | |
8137 format %{ "FITOS $tmp,$dst" %} | |
8138 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8139 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8140 ins_pipe(fcvtI2F); | |
8141 %} | |
8142 | |
8143 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
8144 match(Set dst (ConvI2F src)); | |
8145 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8146 expand %{ | |
8147 regF tmp; | |
8148 stkI_to_regF(tmp,src); | |
8149 convI2F_helper(dst, tmp); | |
8150 %} | |
8151 %} | |
8152 | |
8153 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8154 match(Set dst (ConvI2F (LoadI mem))); | |
8155 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8156 size(8); | |
8157 format %{ "LDF $mem,$dst\n\t" | |
8158 "FITOS $dst,$dst" %} | |
8159 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
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8160 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8161 ins_pipe(floadF_mem); |
8162 %} | |
8163 | |
8164 | |
8165 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8166 match(Set dst (ConvI2L src)); | |
8167 size(4); | |
8168 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8169 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8170 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8171 ins_pipe(ialu_reg_reg); | |
8172 %} | |
8173 | |
8174 // Zero-extend convert int to long | |
8175 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8176 match(Set dst (AndL (ConvI2L src) mask) ); | |
8177 size(4); | |
8178 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8179 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8180 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8181 ins_pipe(ialu_reg_reg); | |
8182 %} | |
8183 | |
8184 // Zero-extend long | |
8185 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8186 match(Set dst (AndL src mask) ); | |
8187 size(4); | |
8188 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8189 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8190 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8191 ins_pipe(ialu_reg_reg); | |
8192 %} | |
8193 | |
8194 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
8195 match(Set dst (MoveF2I src)); | |
8196 effect(DEF dst, USE src); | |
8197 ins_cost(MEMORY_REF_COST); | |
8198 | |
8199 size(4); | |
8200 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8201 opcode(Assembler::lduw_op3); | |
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8202 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8203 ins_pipe(iload_mem); |
8204 %} | |
8205 | |
8206 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8207 match(Set dst (MoveI2F src)); | |
8208 effect(DEF dst, USE src); | |
8209 ins_cost(MEMORY_REF_COST); | |
8210 | |
8211 size(4); | |
8212 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8213 opcode(Assembler::ldf_op3); | |
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8214 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8215 ins_pipe(floadF_stk); |
8216 %} | |
8217 | |
8218 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8219 match(Set dst (MoveD2L src)); | |
8220 effect(DEF dst, USE src); | |
8221 ins_cost(MEMORY_REF_COST); | |
8222 | |
8223 size(4); | |
8224 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8225 opcode(Assembler::ldx_op3); | |
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8226 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8227 ins_pipe(iload_mem); |
8228 %} | |
8229 | |
8230 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8231 match(Set dst (MoveL2D src)); | |
8232 effect(DEF dst, USE src); | |
8233 ins_cost(MEMORY_REF_COST); | |
8234 | |
8235 size(4); | |
8236 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8237 opcode(Assembler::lddf_op3); | |
415
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8238 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8239 ins_pipe(floadD_stk); |
8240 %} | |
8241 | |
8242 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8243 match(Set dst (MoveF2I src)); | |
8244 effect(DEF dst, USE src); | |
8245 ins_cost(MEMORY_REF_COST); | |
8246 | |
8247 size(4); | |
8248 format %{ "STF $src,$dst\t!MoveF2I" %} | |
8249 opcode(Assembler::stf_op3); | |
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8250 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8251 ins_pipe(fstoreF_stk_reg); |
8252 %} | |
8253 | |
8254 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8255 match(Set dst (MoveI2F src)); | |
8256 effect(DEF dst, USE src); | |
8257 ins_cost(MEMORY_REF_COST); | |
8258 | |
8259 size(4); | |
8260 format %{ "STW $src,$dst\t!MoveI2F" %} | |
8261 opcode(Assembler::stw_op3); | |
415
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8262 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8263 ins_pipe(istore_mem_reg); |
8264 %} | |
8265 | |
8266 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8267 match(Set dst (MoveD2L src)); | |
8268 effect(DEF dst, USE src); | |
8269 ins_cost(MEMORY_REF_COST); | |
8270 | |
8271 size(4); | |
8272 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
8273 opcode(Assembler::stdf_op3); | |
415
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8274 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8275 ins_pipe(fstoreD_stk_reg); |
8276 %} | |
8277 | |
8278 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8279 match(Set dst (MoveL2D src)); | |
8280 effect(DEF dst, USE src); | |
8281 ins_cost(MEMORY_REF_COST); | |
8282 | |
8283 size(4); | |
8284 format %{ "STX $src,$dst\t!MoveL2D" %} | |
8285 opcode(Assembler::stx_op3); | |
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8286 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8287 ins_pipe(istore_mem_reg); |
8288 %} | |
8289 | |
8290 | |
8291 //----------- | |
8292 // Long to Double conversion using V8 opcodes. | |
8293 // Still useful because cheetah traps and becomes | |
8294 // amazingly slow for some common numbers. | |
8295 | |
8296 // Magic constant, 0x43300000 | |
8297 instruct loadConI_x43300000(iRegI dst) %{ | |
8298 effect(DEF dst); | |
8299 size(4); | |
8300 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8301 ins_encode(SetHi22(0x43300000, dst)); | |
8302 ins_pipe(ialu_none); | |
8303 %} | |
8304 | |
8305 // Magic constant, 0x41f00000 | |
8306 instruct loadConI_x41f00000(iRegI dst) %{ | |
8307 effect(DEF dst); | |
8308 size(4); | |
8309 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8310 ins_encode(SetHi22(0x41f00000, dst)); | |
8311 ins_pipe(ialu_none); | |
8312 %} | |
8313 | |
8314 // Construct a double from two float halves | |
8315 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8316 effect(DEF dst, USE src1, USE src2); | |
8317 size(8); | |
8318 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8319 "FMOVS $src2.lo,$dst.lo" %} | |
8320 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8321 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8322 ins_pipe(faddD_reg_reg); | |
8323 %} | |
8324 | |
8325 // Convert integer in high half of a double register (in the lower half of | |
8326 // the double register file) to double | |
8327 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8328 effect(DEF dst, USE src); | |
8329 size(4); | |
8330 format %{ "FITOD $src,$dst" %} | |
8331 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8332 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8333 ins_pipe(fcvtLHi2D); | |
8334 %} | |
8335 | |
8336 // Add float double precision | |
8337 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8338 effect(DEF dst, USE src1, USE src2); | |
8339 size(4); | |
8340 format %{ "FADDD $src1,$src2,$dst" %} | |
8341 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8342 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8343 ins_pipe(faddD_reg_reg); | |
8344 %} | |
8345 | |
8346 // Sub float double precision | |
8347 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8348 effect(DEF dst, USE src1, USE src2); | |
8349 size(4); | |
8350 format %{ "FSUBD $src1,$src2,$dst" %} | |
8351 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8352 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8353 ins_pipe(faddD_reg_reg); | |
8354 %} | |
8355 | |
8356 // Mul float double precision | |
8357 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8358 effect(DEF dst, USE src1, USE src2); | |
8359 size(4); | |
8360 format %{ "FMULD $src1,$src2,$dst" %} | |
8361 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8362 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8363 ins_pipe(fmulD_reg_reg); | |
8364 %} | |
8365 | |
8366 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8367 match(Set dst (ConvL2D src)); | |
8368 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8369 | |
8370 expand %{ | |
8371 regD_low tmpsrc; | |
8372 iRegI ix43300000; | |
8373 iRegI ix41f00000; | |
8374 stackSlotL lx43300000; | |
8375 stackSlotL lx41f00000; | |
8376 regD_low dx43300000; | |
8377 regD dx41f00000; | |
8378 regD tmp1; | |
8379 regD_low tmp2; | |
8380 regD tmp3; | |
8381 regD tmp4; | |
8382 | |
8383 stkL_to_regD(tmpsrc, src); | |
8384 | |
8385 loadConI_x43300000(ix43300000); | |
8386 loadConI_x41f00000(ix41f00000); | |
8387 regI_to_stkLHi(lx43300000, ix43300000); | |
8388 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8389 stkL_to_regD(dx43300000, lx43300000); | |
8390 stkL_to_regD(dx41f00000, lx41f00000); | |
8391 | |
8392 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8393 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8394 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8395 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8396 addD_regD_regD(dst, tmp3, tmp4); | |
8397 %} | |
8398 %} | |
8399 | |
8400 // Long to Double conversion using fast fxtof | |
8401 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8402 effect(DEF dst, USE tmp); | |
8403 size(4); | |
8404 format %{ "FXTOD $tmp,$dst" %} | |
8405 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8406 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8407 ins_pipe(fcvtL2D); | |
8408 %} | |
8409 | |
8410 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
8411 predicate(VM_Version::has_fast_fxtof()); | |
8412 match(Set dst (ConvL2D src)); | |
8413 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8414 expand %{ | |
8415 regD tmp; | |
8416 stkL_to_regD(tmp, src); | |
8417 convL2D_helper(dst, tmp); | |
8418 %} | |
8419 %} | |
8420 | |
8421 //----------- | |
8422 // Long to Float conversion using V8 opcodes. | |
8423 // Still useful because cheetah traps and becomes | |
8424 // amazingly slow for some common numbers. | |
8425 | |
8426 // Long to Float conversion using fast fxtof | |
8427 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8428 effect(DEF dst, USE tmp); | |
8429 size(4); | |
8430 format %{ "FXTOS $tmp,$dst" %} | |
8431 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8432 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8433 ins_pipe(fcvtL2F); | |
8434 %} | |
8435 | |
8436 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
8437 match(Set dst (ConvL2F src)); | |
8438 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8439 expand %{ | |
8440 regD tmp; | |
8441 stkL_to_regD(tmp, src); | |
8442 convL2F_helper(dst, tmp); | |
8443 %} | |
8444 %} | |
8445 //----------- | |
8446 | |
8447 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8448 match(Set dst (ConvL2I src)); | |
8449 #ifndef _LP64 | |
8450 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8451 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8452 ins_pipe(ialu_move_reg_I_to_L); | |
8453 #else | |
8454 size(4); | |
8455 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8456 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8457 ins_pipe(ialu_reg); | |
8458 #endif | |
8459 %} | |
8460 | |
8461 // Register Shift Right Immediate | |
8462 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8463 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8464 | |
8465 size(4); | |
8466 format %{ "SRAX $src,$cnt,$dst" %} | |
8467 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8468 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8469 ins_pipe(ialu_reg_imm); | |
8470 %} | |
8471 | |
8472 // Replicate scalar to packed byte values in Double register | |
8473 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
8474 effect(DEF dst, USE src); | |
8475 format %{ "SLLX $src,56,$dst\n\t" | |
8476 "SRLX $dst, 8,O7\n\t" | |
8477 "OR $dst,O7,$dst\n\t" | |
8478 "SRLX $dst,16,O7\n\t" | |
8479 "OR $dst,O7,$dst\n\t" | |
8480 "SRLX $dst,32,O7\n\t" | |
8481 "OR $dst,O7,$dst\t! replicate8B" %} | |
8482 ins_encode( enc_repl8b(src, dst)); | |
8483 ins_pipe(ialu_reg); | |
8484 %} | |
8485 | |
8486 // Replicate scalar to packed byte values in Double register | |
8487 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
8488 match(Set dst (Replicate8B src)); | |
8489 expand %{ | |
8490 iRegL tmp; | |
8491 Repl8B_reg_helper(tmp, src); | |
8492 regL_to_stkD(dst, tmp); | |
8493 %} | |
8494 %} | |
8495 | |
8496 // Replicate scalar constant to packed byte values in Double register | |
8497 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
8498 match(Set dst (Replicate8B src)); | |
8499 #ifdef _LP64 | |
8500 size(36); | |
8501 #else | |
8502 size(8); | |
8503 #endif | |
8504 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
8505 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
8506 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
8507 ins_pipe(loadConFD); | |
8508 %} | |
8509 | |
8510 // Replicate scalar to packed char values into stack slot | |
8511 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
8512 effect(DEF dst, USE src); | |
8513 format %{ "SLLX $src,48,$dst\n\t" | |
8514 "SRLX $dst,16,O7\n\t" | |
8515 "OR $dst,O7,$dst\n\t" | |
8516 "SRLX $dst,32,O7\n\t" | |
8517 "OR $dst,O7,$dst\t! replicate4C" %} | |
8518 ins_encode( enc_repl4s(src, dst) ); | |
8519 ins_pipe(ialu_reg); | |
8520 %} | |
8521 | |
8522 // Replicate scalar to packed char values into stack slot | |
8523 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
8524 match(Set dst (Replicate4C src)); | |
8525 expand %{ | |
8526 iRegL tmp; | |
8527 Repl4C_reg_helper(tmp, src); | |
8528 regL_to_stkD(dst, tmp); | |
8529 %} | |
8530 %} | |
8531 | |
8532 // Replicate scalar constant to packed char values in Double register | |
8533 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
8534 match(Set dst (Replicate4C src)); | |
8535 #ifdef _LP64 | |
8536 size(36); | |
8537 #else | |
8538 size(8); | |
8539 #endif | |
8540 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
8541 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8542 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8543 ins_pipe(loadConFD); | |
8544 %} | |
8545 | |
8546 // Replicate scalar to packed short values into stack slot | |
8547 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
8548 effect(DEF dst, USE src); | |
8549 format %{ "SLLX $src,48,$dst\n\t" | |
8550 "SRLX $dst,16,O7\n\t" | |
8551 "OR $dst,O7,$dst\n\t" | |
8552 "SRLX $dst,32,O7\n\t" | |
8553 "OR $dst,O7,$dst\t! replicate4S" %} | |
8554 ins_encode( enc_repl4s(src, dst) ); | |
8555 ins_pipe(ialu_reg); | |
8556 %} | |
8557 | |
8558 // Replicate scalar to packed short values into stack slot | |
8559 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
8560 match(Set dst (Replicate4S src)); | |
8561 expand %{ | |
8562 iRegL tmp; | |
8563 Repl4S_reg_helper(tmp, src); | |
8564 regL_to_stkD(dst, tmp); | |
8565 %} | |
8566 %} | |
8567 | |
8568 // Replicate scalar constant to packed short values in Double register | |
8569 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
8570 match(Set dst (Replicate4S src)); | |
8571 #ifdef _LP64 | |
8572 size(36); | |
8573 #else | |
8574 size(8); | |
8575 #endif | |
8576 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
8577 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8578 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8579 ins_pipe(loadConFD); | |
8580 %} | |
8581 | |
8582 // Replicate scalar to packed int values in Double register | |
8583 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
8584 effect(DEF dst, USE src); | |
8585 format %{ "SLLX $src,32,$dst\n\t" | |
8586 "SRLX $dst,32,O7\n\t" | |
8587 "OR $dst,O7,$dst\t! replicate2I" %} | |
8588 ins_encode( enc_repl2i(src, dst)); | |
8589 ins_pipe(ialu_reg); | |
8590 %} | |
8591 | |
8592 // Replicate scalar to packed int values in Double register | |
8593 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
8594 match(Set dst (Replicate2I src)); | |
8595 expand %{ | |
8596 iRegL tmp; | |
8597 Repl2I_reg_helper(tmp, src); | |
8598 regL_to_stkD(dst, tmp); | |
8599 %} | |
8600 %} | |
8601 | |
8602 // Replicate scalar zero constant to packed int values in Double register | |
8603 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
8604 match(Set dst (Replicate2I src)); | |
8605 #ifdef _LP64 | |
8606 size(36); | |
8607 #else | |
8608 size(8); | |
8609 #endif | |
8610 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
8611 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
8612 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
8613 ins_pipe(loadConFD); | |
8614 %} | |
8615 | |
8616 //----------Control Flow Instructions------------------------------------------ | |
8617 // Compare Instructions | |
8618 // Compare Integers | |
8619 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8620 match(Set icc (CmpI op1 op2)); | |
8621 effect( DEF icc, USE op1, USE op2 ); | |
8622 | |
8623 size(4); | |
8624 format %{ "CMP $op1,$op2" %} | |
8625 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8626 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8627 ins_pipe(ialu_cconly_reg_reg); | |
8628 %} | |
8629 | |
8630 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8631 match(Set icc (CmpU op1 op2)); | |
8632 | |
8633 size(4); | |
8634 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8635 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8636 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8637 ins_pipe(ialu_cconly_reg_reg); | |
8638 %} | |
8639 | |
8640 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8641 match(Set icc (CmpI op1 op2)); | |
8642 effect( DEF icc, USE op1 ); | |
8643 | |
8644 size(4); | |
8645 format %{ "CMP $op1,$op2" %} | |
8646 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8647 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8648 ins_pipe(ialu_cconly_reg_imm); | |
8649 %} | |
8650 | |
8651 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8652 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8653 | |
8654 size(4); | |
8655 format %{ "BTST $op2,$op1" %} | |
8656 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8657 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8658 ins_pipe(ialu_cconly_reg_reg_zero); | |
8659 %} | |
8660 | |
8661 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8662 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8663 | |
8664 size(4); | |
8665 format %{ "BTST $op2,$op1" %} | |
8666 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8667 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8668 ins_pipe(ialu_cconly_reg_imm_zero); | |
8669 %} | |
8670 | |
8671 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8672 match(Set xcc (CmpL op1 op2)); | |
8673 effect( DEF xcc, USE op1, USE op2 ); | |
8674 | |
8675 size(4); | |
8676 format %{ "CMP $op1,$op2\t\t! long" %} | |
8677 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8678 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8679 ins_pipe(ialu_cconly_reg_reg); | |
8680 %} | |
8681 | |
8682 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8683 match(Set xcc (CmpL op1 con)); | |
8684 effect( DEF xcc, USE op1, USE con ); | |
8685 | |
8686 size(4); | |
8687 format %{ "CMP $op1,$con\t\t! long" %} | |
8688 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8689 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8690 ins_pipe(ialu_cconly_reg_reg); | |
8691 %} | |
8692 | |
8693 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8694 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8695 effect( DEF xcc, USE op1, USE op2 ); | |
8696 | |
8697 size(4); | |
8698 format %{ "BTST $op1,$op2\t\t! long" %} | |
8699 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8700 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8701 ins_pipe(ialu_cconly_reg_reg); | |
8702 %} | |
8703 | |
8704 // useful for checking the alignment of a pointer: | |
8705 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8706 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8707 effect( DEF xcc, USE op1, USE con ); | |
8708 | |
8709 size(4); | |
8710 format %{ "BTST $op1,$con\t\t! long" %} | |
8711 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8712 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8713 ins_pipe(ialu_cconly_reg_reg); | |
8714 %} | |
8715 | |
8716 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8717 match(Set icc (CmpU op1 op2)); | |
8718 | |
8719 size(4); | |
8720 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8721 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8722 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8723 ins_pipe(ialu_cconly_reg_imm); | |
8724 %} | |
8725 | |
8726 // Compare Pointers | |
8727 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8728 match(Set pcc (CmpP op1 op2)); | |
8729 | |
8730 size(4); | |
8731 format %{ "CMP $op1,$op2\t! ptr" %} | |
8732 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8733 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8734 ins_pipe(ialu_cconly_reg_reg); | |
8735 %} | |
8736 | |
8737 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8738 match(Set pcc (CmpP op1 op2)); | |
8739 | |
8740 size(4); | |
8741 format %{ "CMP $op1,$op2\t! ptr" %} | |
8742 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8743 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8744 ins_pipe(ialu_cconly_reg_imm); | |
8745 %} | |
8746 | |
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8747 // Compare Narrow oops |
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8748 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8749 match(Set icc (CmpN op1 op2)); |
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8750 |
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8751 size(4); |
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8752 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8753 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8754 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8755 ins_pipe(ialu_cconly_reg_reg); |
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8756 %} |
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8757 |
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8758 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8759 match(Set icc (CmpN op1 op2)); |
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8760 |
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8761 size(4); |
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8762 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8763 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8764 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8765 ins_pipe(ialu_cconly_reg_imm); |
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8766 %} |
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8767 |
0 | 8768 //----------Max and Min-------------------------------------------------------- |
8769 // Min Instructions | |
8770 // Conditional move for min | |
8771 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8772 effect( USE_DEF op2, USE op1, USE icc ); | |
8773 | |
8774 size(4); | |
8775 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
8776 opcode(Assembler::less); | |
8777 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8778 ins_pipe(ialu_reg_flags); | |
8779 %} | |
8780 | |
8781 // Min Register with Register. | |
8782 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
8783 match(Set op2 (MinI op1 op2)); | |
8784 ins_cost(DEFAULT_COST*2); | |
8785 expand %{ | |
8786 flagsReg icc; | |
8787 compI_iReg(icc,op1,op2); | |
8788 cmovI_reg_lt(op2,op1,icc); | |
8789 %} | |
8790 %} | |
8791 | |
8792 // Max Instructions | |
8793 // Conditional move for max | |
8794 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8795 effect( USE_DEF op2, USE op1, USE icc ); | |
8796 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
8797 opcode(Assembler::greater); | |
8798 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8799 ins_pipe(ialu_reg_flags); | |
8800 %} | |
8801 | |
8802 // Max Register with Register | |
8803 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
8804 match(Set op2 (MaxI op1 op2)); | |
8805 ins_cost(DEFAULT_COST*2); | |
8806 expand %{ | |
8807 flagsReg icc; | |
8808 compI_iReg(icc,op1,op2); | |
8809 cmovI_reg_gt(op2,op1,icc); | |
8810 %} | |
8811 %} | |
8812 | |
8813 | |
8814 //----------Float Compares---------------------------------------------------- | |
8815 // Compare floating, generate condition code | |
8816 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
8817 match(Set fcc (CmpF src1 src2)); | |
8818 | |
8819 size(4); | |
8820 format %{ "FCMPs $fcc,$src1,$src2" %} | |
8821 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
8822 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
8823 ins_pipe(faddF_fcc_reg_reg_zero); | |
8824 %} | |
8825 | |
8826 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
8827 match(Set fcc (CmpD src1 src2)); | |
8828 | |
8829 size(4); | |
8830 format %{ "FCMPd $fcc,$src1,$src2" %} | |
8831 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
8832 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
8833 ins_pipe(faddD_fcc_reg_reg_zero); | |
8834 %} | |
8835 | |
8836 | |
8837 // Compare floating, generate -1,0,1 | |
8838 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
8839 match(Set dst (CmpF3 src1 src2)); | |
8840 effect(KILL fcc0); | |
8841 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8842 format %{ "fcmpl $dst,$src1,$src2" %} | |
8843 // Primary = float | |
8844 opcode( true ); | |
8845 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8846 ins_pipe( floating_cmp ); | |
8847 %} | |
8848 | |
8849 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
8850 match(Set dst (CmpD3 src1 src2)); | |
8851 effect(KILL fcc0); | |
8852 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8853 format %{ "dcmpl $dst,$src1,$src2" %} | |
8854 // Primary = double (not float) | |
8855 opcode( false ); | |
8856 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8857 ins_pipe( floating_cmp ); | |
8858 %} | |
8859 | |
8860 //----------Branches--------------------------------------------------------- | |
8861 // Jump | |
8862 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
8863 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
8864 match(Jump switch_val); | |
8865 | |
8866 ins_cost(350); | |
8867 | |
8868 format %{ "SETHI [hi(table_base)],O7\n\t" | |
8869 "ADD O7, lo(table_base), O7\n\t" | |
8870 "LD [O7+$switch_val], O7\n\t" | |
8871 "JUMP O7" | |
8872 %} | |
8873 ins_encode( jump_enc( switch_val, table) ); | |
8874 ins_pc_relative(1); | |
8875 ins_pipe(ialu_reg_reg); | |
8876 %} | |
8877 | |
8878 // Direct Branch. Use V8 version with longer range. | |
8879 instruct branch(label labl) %{ | |
8880 match(Goto); | |
8881 effect(USE labl); | |
8882 | |
8883 size(8); | |
8884 ins_cost(BRANCH_COST); | |
8885 format %{ "BA $labl" %} | |
8886 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
8887 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
8888 ins_encode( enc_ba( labl ) ); | |
8889 ins_pc_relative(1); | |
8890 ins_pipe(br); | |
8891 %} | |
8892 | |
8893 // Conditional Direct Branch | |
8894 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
8895 match(If cmp icc); | |
8896 effect(USE labl); | |
8897 | |
8898 size(8); | |
8899 ins_cost(BRANCH_COST); | |
8900 format %{ "BP$cmp $icc,$labl" %} | |
8901 // Prim = bits 24-22, Secnd = bits 31-30 | |
8902 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8903 ins_pc_relative(1); | |
8904 ins_pipe(br_cc); | |
8905 %} | |
8906 | |
8907 // Branch-on-register tests all 64 bits. We assume that values | |
8908 // in 64-bit registers always remains zero or sign extended | |
8909 // unless our code munges the high bits. Interrupts can chop | |
8910 // the high order bits to zero or sign at any time. | |
8911 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
8912 match(If cmp (CmpI op1 zero)); | |
8913 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8914 effect(USE labl); | |
8915 | |
8916 size(8); | |
8917 ins_cost(BRANCH_COST); | |
8918 format %{ "BR$cmp $op1,$labl" %} | |
8919 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8920 ins_pc_relative(1); | |
8921 ins_pipe(br_reg); | |
8922 %} | |
8923 | |
8924 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
8925 match(If cmp (CmpP op1 null)); | |
8926 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8927 effect(USE labl); | |
8928 | |
8929 size(8); | |
8930 ins_cost(BRANCH_COST); | |
8931 format %{ "BR$cmp $op1,$labl" %} | |
8932 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8933 ins_pc_relative(1); | |
8934 ins_pipe(br_reg); | |
8935 %} | |
8936 | |
8937 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
8938 match(If cmp (CmpL op1 zero)); | |
8939 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8940 effect(USE labl); | |
8941 | |
8942 size(8); | |
8943 ins_cost(BRANCH_COST); | |
8944 format %{ "BR$cmp $op1,$labl" %} | |
8945 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8946 ins_pc_relative(1); | |
8947 ins_pipe(br_reg); | |
8948 %} | |
8949 | |
8950 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
8951 match(If cmp icc); | |
8952 effect(USE labl); | |
8953 | |
8954 format %{ "BP$cmp $icc,$labl" %} | |
8955 // Prim = bits 24-22, Secnd = bits 31-30 | |
8956 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8957 ins_pc_relative(1); | |
8958 ins_pipe(br_cc); | |
8959 %} | |
8960 | |
8961 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
8962 match(If cmp pcc); | |
8963 effect(USE labl); | |
8964 | |
8965 size(8); | |
8966 ins_cost(BRANCH_COST); | |
8967 format %{ "BP$cmp $pcc,$labl" %} | |
8968 // Prim = bits 24-22, Secnd = bits 31-30 | |
8969 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
8970 ins_pc_relative(1); | |
8971 ins_pipe(br_cc); | |
8972 %} | |
8973 | |
8974 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
8975 match(If cmp fcc); | |
8976 effect(USE labl); | |
8977 | |
8978 size(8); | |
8979 ins_cost(BRANCH_COST); | |
8980 format %{ "FBP$cmp $fcc,$labl" %} | |
8981 // Prim = bits 24-22, Secnd = bits 31-30 | |
8982 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
8983 ins_pc_relative(1); | |
8984 ins_pipe(br_fcc); | |
8985 %} | |
8986 | |
8987 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
8988 match(CountedLoopEnd cmp icc); | |
8989 effect(USE labl); | |
8990 | |
8991 size(8); | |
8992 ins_cost(BRANCH_COST); | |
8993 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
8994 // Prim = bits 24-22, Secnd = bits 31-30 | |
8995 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8996 ins_pc_relative(1); | |
8997 ins_pipe(br_cc); | |
8998 %} | |
8999 | |
9000 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9001 match(CountedLoopEnd cmp icc); | |
9002 effect(USE labl); | |
9003 | |
9004 size(8); | |
9005 ins_cost(BRANCH_COST); | |
9006 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9007 // Prim = bits 24-22, Secnd = bits 31-30 | |
9008 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9009 ins_pc_relative(1); | |
9010 ins_pipe(br_cc); | |
9011 %} | |
9012 | |
9013 // ============================================================================ | |
9014 // Long Compare | |
9015 // | |
9016 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9017 // is tricky. The flavor of compare used depends on whether we are testing | |
9018 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9019 // The GE test is the negated LT test. The LE test can be had by commuting | |
9020 // the operands (yielding a GE test) and then negating; negate again for the | |
9021 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9022 // NE test is negated from that. | |
9023 | |
9024 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9025 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9026 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9027 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9028 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9029 // foo match ends up with the wrong leaf. One fix is to not match both | |
9030 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9031 // both forms beat the trinary form of long-compare and both are very useful | |
9032 // on Intel which has so few registers. | |
9033 | |
9034 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9035 match(If cmp xcc); | |
9036 effect(USE labl); | |
9037 | |
9038 size(8); | |
9039 ins_cost(BRANCH_COST); | |
9040 format %{ "BP$cmp $xcc,$labl" %} | |
9041 // Prim = bits 24-22, Secnd = bits 31-30 | |
9042 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
9043 ins_pc_relative(1); | |
9044 ins_pipe(br_cc); | |
9045 %} | |
9046 | |
9047 // Manifest a CmpL3 result in an integer register. Very painful. | |
9048 // This is the test to avoid. | |
9049 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9050 match(Set dst (CmpL3 src1 src2) ); | |
9051 effect( KILL ccr ); | |
9052 ins_cost(6*DEFAULT_COST); | |
9053 size(24); | |
9054 format %{ "CMP $src1,$src2\t\t! long\n" | |
9055 "\tBLT,a,pn done\n" | |
9056 "\tMOV -1,$dst\t! delay slot\n" | |
9057 "\tBGT,a,pn done\n" | |
9058 "\tMOV 1,$dst\t! delay slot\n" | |
9059 "\tCLR $dst\n" | |
9060 "done:" %} | |
9061 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9062 ins_pipe(cmpL_reg); | |
9063 %} | |
9064 | |
9065 // Conditional move | |
9066 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9067 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9068 ins_cost(150); | |
9069 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9070 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9071 ins_pipe(ialu_reg); | |
9072 %} | |
9073 | |
9074 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9075 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9076 ins_cost(140); | |
9077 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9078 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9079 ins_pipe(ialu_imm); | |
9080 %} | |
9081 | |
9082 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9083 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9084 ins_cost(150); | |
9085 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9086 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9087 ins_pipe(ialu_reg); | |
9088 %} | |
9089 | |
9090 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9091 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9092 ins_cost(140); | |
9093 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9094 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9095 ins_pipe(ialu_imm); | |
9096 %} | |
9097 | |
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9098 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9099 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9100 ins_cost(150); |
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9101 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9102 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9103 ins_pipe(ialu_reg); |
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9104 %} |
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9105 |
0 | 9106 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9107 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9108 ins_cost(150); | |
9109 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9110 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9111 ins_pipe(ialu_reg); | |
9112 %} | |
9113 | |
9114 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9115 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9116 ins_cost(140); | |
9117 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9118 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9119 ins_pipe(ialu_imm); | |
9120 %} | |
9121 | |
9122 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9123 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9124 ins_cost(150); | |
9125 opcode(0x101); | |
9126 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9127 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9128 ins_pipe(int_conditional_float_move); | |
9129 %} | |
9130 | |
9131 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9132 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9133 ins_cost(150); | |
9134 opcode(0x102); | |
9135 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9136 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9137 ins_pipe(int_conditional_float_move); | |
9138 %} | |
9139 | |
9140 // ============================================================================ | |
9141 // Safepoint Instruction | |
9142 instruct safePoint_poll(iRegP poll) %{ | |
9143 match(SafePoint poll); | |
9144 effect(USE poll); | |
9145 | |
9146 size(4); | |
9147 #ifdef _LP64 | |
9148 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9149 #else | |
9150 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9151 #endif | |
9152 ins_encode %{ | |
9153 __ relocate(relocInfo::poll_type); | |
9154 __ ld_ptr($poll$$Register, 0, G0); | |
9155 %} | |
9156 ins_pipe(loadPollP); | |
9157 %} | |
9158 | |
9159 // ============================================================================ | |
9160 // Call Instructions | |
9161 // Call Java Static Instruction | |
9162 instruct CallStaticJavaDirect( method meth ) %{ | |
9163 match(CallStaticJava); | |
9164 effect(USE meth); | |
9165 | |
9166 size(8); | |
9167 ins_cost(CALL_COST); | |
9168 format %{ "CALL,static ; NOP ==> " %} | |
9169 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9170 ins_pc_relative(1); | |
9171 ins_pipe(simple_call); | |
9172 %} | |
9173 | |
9174 // Call Java Dynamic Instruction | |
9175 instruct CallDynamicJavaDirect( method meth ) %{ | |
9176 match(CallDynamicJava); | |
9177 effect(USE meth); | |
9178 | |
9179 ins_cost(CALL_COST); | |
9180 format %{ "SET (empty),R_G5\n\t" | |
9181 "CALL,dynamic ; NOP ==> " %} | |
9182 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9183 ins_pc_relative(1); | |
9184 ins_pipe(call); | |
9185 %} | |
9186 | |
9187 // Call Runtime Instruction | |
9188 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9189 match(CallRuntime); | |
9190 effect(USE meth, KILL l7); | |
9191 ins_cost(CALL_COST); | |
9192 format %{ "CALL,runtime" %} | |
9193 ins_encode( Java_To_Runtime( meth ), | |
9194 call_epilog, adjust_long_from_native_call ); | |
9195 ins_pc_relative(1); | |
9196 ins_pipe(simple_call); | |
9197 %} | |
9198 | |
9199 // Call runtime without safepoint - same as CallRuntime | |
9200 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9201 match(CallLeaf); | |
9202 effect(USE meth, KILL l7); | |
9203 ins_cost(CALL_COST); | |
9204 format %{ "CALL,runtime leaf" %} | |
9205 ins_encode( Java_To_Runtime( meth ), | |
9206 call_epilog, | |
9207 adjust_long_from_native_call ); | |
9208 ins_pc_relative(1); | |
9209 ins_pipe(simple_call); | |
9210 %} | |
9211 | |
9212 // Call runtime without safepoint - same as CallLeaf | |
9213 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9214 match(CallLeafNoFP); | |
9215 effect(USE meth, KILL l7); | |
9216 ins_cost(CALL_COST); | |
9217 format %{ "CALL,runtime leaf nofp" %} | |
9218 ins_encode( Java_To_Runtime( meth ), | |
9219 call_epilog, | |
9220 adjust_long_from_native_call ); | |
9221 ins_pc_relative(1); | |
9222 ins_pipe(simple_call); | |
9223 %} | |
9224 | |
9225 // Tail Call; Jump from runtime stub to Java code. | |
9226 // Also known as an 'interprocedural jump'. | |
9227 // Target of jump will eventually return to caller. | |
9228 // TailJump below removes the return address. | |
9229 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9230 match(TailCall jump_target method_oop ); | |
9231 | |
9232 ins_cost(CALL_COST); | |
9233 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9234 ins_encode(form_jmpl(jump_target)); | |
9235 ins_pipe(tail_call); | |
9236 %} | |
9237 | |
9238 | |
9239 // Return Instruction | |
9240 instruct Ret() %{ | |
9241 match(Return); | |
9242 | |
9243 // The epilogue node did the ret already. | |
9244 size(0); | |
9245 format %{ "! return" %} | |
9246 ins_encode(); | |
9247 ins_pipe(empty); | |
9248 %} | |
9249 | |
9250 | |
9251 // Tail Jump; remove the return address; jump to target. | |
9252 // TailCall above leaves the return address around. | |
9253 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
9254 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
9255 // "restore" before this instruction (in Epilogue), we need to materialize it | |
9256 // in %i0. | |
9257 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
9258 match( TailJump jump_target ex_oop ); | |
9259 ins_cost(CALL_COST); | |
9260 format %{ "! discard R_O7\n\t" | |
9261 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
9262 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
9263 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
9264 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
9265 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
9266 ins_pipe(tail_call); | |
9267 %} | |
9268 | |
9269 // Create exception oop: created by stack-crawling runtime code. | |
9270 // Created exception is now available to this handler, and is setup | |
9271 // just prior to jumping to this handler. No code emitted. | |
9272 instruct CreateException( o0RegP ex_oop ) | |
9273 %{ | |
9274 match(Set ex_oop (CreateEx)); | |
9275 ins_cost(0); | |
9276 | |
9277 size(0); | |
9278 // use the following format syntax | |
9279 format %{ "! exception oop is in R_O0; no code emitted" %} | |
9280 ins_encode(); | |
9281 ins_pipe(empty); | |
9282 %} | |
9283 | |
9284 | |
9285 // Rethrow exception: | |
9286 // The exception oop will come in the first argument position. | |
9287 // Then JUMP (not call) to the rethrow stub code. | |
9288 instruct RethrowException() | |
9289 %{ | |
9290 match(Rethrow); | |
9291 ins_cost(CALL_COST); | |
9292 | |
9293 // use the following format syntax | |
9294 format %{ "Jmp rethrow_stub" %} | |
9295 ins_encode(enc_rethrow); | |
9296 ins_pipe(tail_call); | |
9297 %} | |
9298 | |
9299 | |
9300 // Die now | |
9301 instruct ShouldNotReachHere( ) | |
9302 %{ | |
9303 match(Halt); | |
9304 ins_cost(CALL_COST); | |
9305 | |
9306 size(4); | |
9307 // Use the following format syntax | |
9308 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
9309 ins_encode( form2_illtrap() ); | |
9310 ins_pipe(tail_call); | |
9311 %} | |
9312 | |
9313 // ============================================================================ | |
9314 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
9315 // array for an instance of the superklass. Set a hidden internal cache on a | |
9316 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
9317 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
9318 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
9319 match(Set index (PartialSubtypeCheck sub super)); | |
9320 effect( KILL pcc, KILL o7 ); | |
9321 ins_cost(DEFAULT_COST*10); | |
9322 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
9323 ins_encode( enc_PartialSubtypeCheck() ); | |
9324 ins_pipe(partial_subtype_check_pipe); | |
9325 %} | |
9326 | |
9327 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
9328 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
9329 effect( KILL idx, KILL o7 ); | |
9330 ins_cost(DEFAULT_COST*10); | |
9331 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
9332 ins_encode( enc_PartialSubtypeCheck() ); | |
9333 ins_pipe(partial_subtype_check_pipe); | |
9334 %} | |
9335 | |
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9336 |
0 | 9337 // ============================================================================ |
9338 // inlined locking and unlocking | |
9339 | |
9340 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9341 match(Set pcc (FastLock object box)); | |
9342 | |
9343 effect(KILL scratch, TEMP scratch2); | |
9344 ins_cost(100); | |
9345 | |
9346 size(4*112); // conservative overestimation ... | |
9347 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9348 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
9349 ins_pipe(long_memory_op); | |
9350 %} | |
9351 | |
9352 | |
9353 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9354 match(Set pcc (FastUnlock object box)); | |
9355 effect(KILL scratch, TEMP scratch2); | |
9356 ins_cost(100); | |
9357 | |
9358 size(4*120); // conservative overestimation ... | |
9359 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9360 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
9361 ins_pipe(long_memory_op); | |
9362 %} | |
9363 | |
9364 // Count and Base registers are fixed because the allocator cannot | |
9365 // kill unknown registers. The encodings are generic. | |
9366 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
9367 match(Set dummy (ClearArray cnt base)); | |
9368 effect(TEMP temp, KILL ccr); | |
9369 ins_cost(300); | |
9370 format %{ "MOV $cnt,$temp\n" | |
9371 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
9372 " BRge loop\t\t! Clearing loop\n" | |
9373 " STX G0,[$base+$temp]\t! delay slot" %} | |
9374 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
9375 ins_pipe(long_memory_op); | |
9376 %} | |
9377 | |
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9378 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
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9379 o7RegI tmp, flagsReg ccr) %{ |
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9380 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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9381 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 9382 ins_cost(300); |
986
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9383 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
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9384 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 9385 ins_pipe(long_memory_op); |
9386 %} | |
9387 | |
986
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9388 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
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9389 o7RegI tmp, flagsReg ccr) %{ |
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9390 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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9391 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 9392 ins_cost(300); |
986
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9393 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
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9394 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 9395 ins_pipe(long_memory_op); |
9396 %} | |
9397 | |
986
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9398 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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9399 o7RegI tmp2, flagsReg ccr) %{ |
681 | 9400 match(Set result (AryEq ary1 ary2)); |
9401 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
9402 ins_cost(300); | |
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9403 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
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9404 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 9405 ins_pipe(long_memory_op); |
9406 %} | |
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9407 |
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9408 |
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9409 //---------- Zeros Count Instructions ------------------------------------------ |
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9410 |
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9411 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
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9412 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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9413 match(Set dst (CountLeadingZerosI src)); |
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9414 effect(TEMP dst, TEMP tmp, KILL cr); |
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9415 |
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9416 // x |= (x >> 1); |
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9417 // x |= (x >> 2); |
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9418 // x |= (x >> 4); |
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|
9419 // x |= (x >> 8); |
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9420 // x |= (x >> 16); |
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9421 // return (WORDBITS - popc(x)); |
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9422 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
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twisti
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1016
diff
changeset
|
9423 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9424 "OR $dst,$tmp,$dst\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9425 "SRL $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9426 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9427 "SRL $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9428 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9429 "SRL $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9430 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9431 "SRL $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9432 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9433 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9434 "MOV 32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9435 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9436 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9437 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9438 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9439 Register Rtmp = $tmp$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9440 __ srl(Rsrc, 1, Rtmp); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9441 __ srl(Rsrc, 0, Rdst); |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9442 __ or3(Rdst, Rtmp, Rdst); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9443 __ srl(Rdst, 2, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9444 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9445 __ srl(Rdst, 4, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9446 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9447 __ srl(Rdst, 8, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9448 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9449 __ srl(Rdst, 16, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9450 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9451 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9452 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9453 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9454 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9455 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9456 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9457 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9458 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9459 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9460 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9461 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9462 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9463 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9464 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9465 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9466 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9467 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9468 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9469 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9470 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9471 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9472 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9473 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9474 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9475 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9476 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9477 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9478 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9479 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9480 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9481 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9482 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9483 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9484 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9485 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9486 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9487 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9488 Register Rtmp = $tmp$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9489 __ srlx(Rsrc, 1, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9490 __ or3(Rsrc, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9491 __ srlx(Rdst, 2, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9492 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9493 __ srlx(Rdst, 4, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9494 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9495 __ srlx(Rdst, 8, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9496 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9497 __ srlx(Rdst, 16, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9498 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9499 __ srlx(Rdst, 32, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9500 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9501 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9502 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9503 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9504 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9505 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9506 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9507 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9508 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9509 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9510 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9511 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9512 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9513 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9514 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9515 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9516 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9517 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9518 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9519 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9520 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9521 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9522 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9523 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9524 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9525 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9526 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9527 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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9528 |
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9529 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
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9530 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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9531 match(Set dst (CountTrailingZerosL src)); |
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9532 effect(TEMP dst, KILL cr); |
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9533 |
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9534 // return popc(~x & (x - 1)); |
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9535 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
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9536 "ANDN $dst,$src,$dst\n\t" |
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9537 "POPC $dst,$dst" %} |
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9538 ins_encode %{ |
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9539 Register Rdst = $dst$$Register; |
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9540 Register Rsrc = $src$$Register; |
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9541 __ sub(Rsrc, 1, Rdst); |
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9542 __ andn(Rdst, Rsrc, Rdst); |
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9543 __ popc(Rdst, Rdst); |
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9544 %} |
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9545 ins_pipe(ialu_reg); |
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9546 %} |
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9547 |
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9548 |
643
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9549 //---------- Population Count Instructions ------------------------------------- |
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9550 |
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9551 instruct popCountI(iRegI dst, iRegI src) %{ |
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9552 predicate(UsePopCountInstruction); |
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9553 match(Set dst (PopCountI src)); |
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9554 |
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9555 format %{ "POPC $src, $dst" %} |
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9556 ins_encode %{ |
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9557 __ popc($src$$Register, $dst$$Register); |
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9558 %} |
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9559 ins_pipe(ialu_reg); |
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9560 %} |
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9561 |
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9562 // Note: Long.bitCount(long) returns an int. |
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9563 instruct popCountL(iRegI dst, iRegL src) %{ |
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9564 predicate(UsePopCountInstruction); |
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9565 match(Set dst (PopCountL src)); |
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9566 |
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9567 format %{ "POPC $src, $dst" %} |
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9568 ins_encode %{ |
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9569 __ popc($src$$Register, $dst$$Register); |
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9570 %} |
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9571 ins_pipe(ialu_reg); |
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9572 %} |
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9573 |
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9574 |
0 | 9575 // ============================================================================ |
9576 //------------Bytes reverse-------------------------------------------------- | |
9577 | |
9578 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
9579 match(Set dst (ReverseBytesI src)); | |
9580 effect(DEF dst, USE src); | |
9581 | |
9582 // Op cost is artificially doubled to make sure that load or store | |
9583 // instructions are preferred over this one which requires a spill | |
9584 // onto a stack slot. | |
9585 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
9586 size(8); | |
9587 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
9588 opcode(Assembler::lduwa_op3); | |
9589 ins_encode( form3_mem_reg_little(src, dst) ); | |
9590 ins_pipe( iload_mem ); | |
9591 %} | |
9592 | |
9593 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ | |
9594 match(Set dst (ReverseBytesL src)); | |
9595 effect(DEF dst, USE src); | |
9596 | |
9597 // Op cost is artificially doubled to make sure that load or store | |
9598 // instructions are preferred over this one which requires a spill | |
9599 // onto a stack slot. | |
9600 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
9601 size(8); | |
9602 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
9603 | |
9604 opcode(Assembler::ldxa_op3); | |
9605 ins_encode( form3_mem_reg_little(src, dst) ); | |
9606 ins_pipe( iload_mem ); | |
9607 %} | |
9608 | |
9609 // Load Integer reversed byte order | |
9610 instruct loadI_reversed(iRegI dst, memory src) %{ | |
9611 match(Set dst (ReverseBytesI (LoadI src))); | |
9612 | |
9613 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
9614 size(8); | |
9615 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
9616 | |
9617 opcode(Assembler::lduwa_op3); | |
9618 ins_encode( form3_mem_reg_little( src, dst) ); | |
9619 ins_pipe(iload_mem); | |
9620 %} | |
9621 | |
9622 // Load Long - aligned and reversed | |
9623 instruct loadL_reversed(iRegL dst, memory src) %{ | |
9624 match(Set dst (ReverseBytesL (LoadL src))); | |
9625 | |
9626 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
9627 size(8); | |
9628 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
9629 | |
9630 opcode(Assembler::ldxa_op3); | |
9631 ins_encode( form3_mem_reg_little( src, dst ) ); | |
9632 ins_pipe(iload_mem); | |
9633 %} | |
9634 | |
9635 // Store Integer reversed byte order | |
9636 instruct storeI_reversed(memory dst, iRegI src) %{ | |
9637 match(Set dst (StoreI dst (ReverseBytesI src))); | |
9638 | |
9639 ins_cost(MEMORY_REF_COST); | |
9640 size(8); | |
9641 format %{ "STWA $src, $dst\t!asi=primary_little" %} | |
9642 | |
9643 opcode(Assembler::stwa_op3); | |
9644 ins_encode( form3_mem_reg_little( dst, src) ); | |
9645 ins_pipe(istore_mem_reg); | |
9646 %} | |
9647 | |
9648 // Store Long reversed byte order | |
9649 instruct storeL_reversed(memory dst, iRegL src) %{ | |
9650 match(Set dst (StoreL dst (ReverseBytesL src))); | |
9651 | |
9652 ins_cost(MEMORY_REF_COST); | |
9653 size(8); | |
9654 format %{ "STXA $src, $dst\t!asi=primary_little" %} | |
9655 | |
9656 opcode(Assembler::stxa_op3); | |
9657 ins_encode( form3_mem_reg_little( dst, src) ); | |
9658 ins_pipe(istore_mem_reg); | |
9659 %} | |
9660 | |
9661 //----------PEEPHOLE RULES----------------------------------------------------- | |
9662 // These must follow all instruction definitions as they use the names | |
9663 // defined in the instructions definitions. | |
9664 // | |
605 | 9665 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 9666 // |
9667 // peepconstraint %{ | |
9668 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
9669 // [, ...] ); | |
9670 // // instruction numbers are zero-based using left to right order in peepmatch | |
9671 // | |
9672 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
9673 // // provide an instruction_number.operand_name for each operand that appears | |
9674 // // in the replacement instruction's match rule | |
9675 // | |
9676 // ---------VM FLAGS--------------------------------------------------------- | |
9677 // | |
9678 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
9679 // | |
9680 // Each peephole rule is given an identifying number starting with zero and | |
9681 // increasing by one in the order seen by the parser. An individual peephole | |
9682 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
9683 // on the command-line. | |
9684 // | |
9685 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
9686 // | |
9687 // Only match adjacent instructions in same basic block | |
9688 // Only equality constraints | |
9689 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
9690 // Only one replacement instruction | |
9691 // | |
9692 // ---------EXAMPLE---------------------------------------------------------- | |
9693 // | |
9694 // // pertinent parts of existing instructions in architecture description | |
9695 // instruct movI(eRegI dst, eRegI src) %{ | |
9696 // match(Set dst (CopyI src)); | |
9697 // %} | |
9698 // | |
9699 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
9700 // match(Set dst (AddI dst src)); | |
9701 // effect(KILL cr); | |
9702 // %} | |
9703 // | |
9704 // // Change (inc mov) to lea | |
9705 // peephole %{ | |
9706 // // increment preceeded by register-register move | |
9707 // peepmatch ( incI_eReg movI ); | |
9708 // // require that the destination register of the increment | |
9709 // // match the destination register of the move | |
9710 // peepconstraint ( 0.dst == 1.dst ); | |
9711 // // construct a replacement instruction that sets | |
9712 // // the destination to ( move's source register + one ) | |
9713 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
9714 // %} | |
9715 // | |
9716 | |
9717 // // Change load of spilled value to only a spill | |
9718 // instruct storeI(memory mem, eRegI src) %{ | |
9719 // match(Set mem (StoreI mem src)); | |
9720 // %} | |
9721 // | |
9722 // instruct loadI(eRegI dst, memory mem) %{ | |
9723 // match(Set dst (LoadI mem)); | |
9724 // %} | |
9725 // | |
9726 // peephole %{ | |
9727 // peepmatch ( loadI storeI ); | |
9728 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
9729 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
9730 // %} | |
9731 | |
9732 //----------SMARTSPILL RULES--------------------------------------------------- | |
9733 // These must follow all instruction definitions as they use the names | |
9734 // defined in the instructions definitions. | |
9735 // | |
9736 // SPARC will probably not have any of these rules due to RISC instruction set. | |
9737 | |
9738 //----------PIPELINE----------------------------------------------------------- | |
9739 // Rules which define the behavior of the target architectures pipeline. |