Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 1571:2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
Summary: Added new product ObjectAlignmentInBytes flag to control object alignment.
Reviewed-by: twisti, ysr, iveresov
| author | kvn |
|---|---|
| date | Thu, 27 May 2010 18:01:56 -0700 |
| parents | 110501f54a99 |
| children | 3657cb01ffc5 |
| rev | line source |
|---|---|
| 0 | 1 // |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
2 // Copyright 1998-2010 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
| 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 // have any questions. | |
| 22 // | |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
|
1007
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
| 429 %} | |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 463 // Macros to extract hi & lo halves from a long pair. | |
| 464 // G0 is not part of any long pair, so assert on that. | |
| 605 | 465 // Prevents accidentally using G1 instead of G0. |
| 0 | 466 #define LONG_HI_REG(x) (x) |
| 467 #define LONG_LO_REG(x) (x) | |
| 468 | |
| 469 %} | |
| 470 | |
| 471 source %{ | |
| 472 #define __ _masm. | |
| 473 | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
474 // Block initializing store |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
476 |
| 0 | 477 // tertiary op of a LoadP or StoreP encoding |
| 478 #define REGP_OP true | |
| 479 | |
| 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 482 static Register reg_to_register_object(int register_encoding); | |
| 483 | |
| 484 // Used by the DFA in dfa_sparc.cpp. | |
| 485 // Check for being able to use a V9 branch-on-register. Requires a | |
| 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 487 // extended. Doesn't work following an integer ADD, for example, because of | |
| 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 490 // replace them with zero, which could become sign-extension in a different OS | |
| 491 // release. There's no obvious reason why an interrupt will ever fill these | |
| 492 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 493 // instructions which either zero-fill or sign-fill). | |
| 494 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 495 if( !BranchOnRegister ) return false; | |
| 496 #ifdef _LP64 | |
| 497 if( cmp->Opcode() == Op_CmpP ) | |
| 498 return true; // No problems with pointer compares | |
| 499 #endif | |
| 500 if( cmp->Opcode() == Op_CmpL ) | |
| 501 return true; // No problems with long compares | |
| 502 | |
| 503 if( !SparcV9RegsHiBitsZero ) return false; | |
| 504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 506 return false; | |
| 507 | |
| 508 // Check for comparing against a 'safe' value. Any operation which | |
| 509 // clears out the high word is safe. Thus, loads and certain shifts | |
| 510 // are safe, as are non-negative constants. Any operation which | |
| 511 // preserves zero bits in the high word is safe as long as each of its | |
| 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 513 // inputs are safe. At present, the only important case to recognize | |
| 514 // seems to be loads. Constants should fold away, and shifts & | |
| 515 // logicals can use the 'cc' forms. | |
| 516 Node *x = cmp->in(1); | |
| 517 if( x->is_Load() ) return true; | |
| 518 if( x->is_Phi() ) { | |
| 519 for( uint i = 1; i < x->req(); i++ ) | |
| 520 if( !x->in(i)->is_Load() ) | |
| 521 return false; | |
| 522 return true; | |
| 523 } | |
| 524 return false; | |
| 525 } | |
| 526 | |
| 527 // **************************************************************************** | |
| 528 | |
| 529 // REQUIRED FUNCTIONALITY | |
| 530 | |
| 531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 532 // from the start of the call to the point where the return address | |
| 533 // will point. | |
| 534 // The "return address" is the address of the call instruction, plus 8. | |
| 535 | |
| 536 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 537 int offset = NativeCall::instruction_size; // call; delay slot |
| 538 if (_method_handle_invoke) | |
| 539 offset += 4; // restore SP | |
| 540 return offset; | |
| 0 | 541 } |
| 542 | |
| 543 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 544 int vtable_index = this->_vtable_index; | |
| 545 if (vtable_index < 0) { | |
| 546 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 548 return (NativeMovConstReg::instruction_size + | |
| 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 550 } else { | |
| 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
554 int klass_load_size; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
555 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
556 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
557 if (Universe::narrow_oop_base() == NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
559 else |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
560 klass_load_size = 3*BytesPerInstWord; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
561 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
562 klass_load_size = 1*BytesPerInstWord; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
563 } |
| 0 | 564 if( Assembler::is_simm13(v_off) ) { |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
565 return klass_load_size + |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 567 NativeCall::instruction_size); // call; delay slot |
| 568 } else { | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
569 return klass_load_size + |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 571 NativeCall::instruction_size); // call; delay slot |
| 572 } | |
| 573 } | |
| 574 } | |
| 575 | |
| 576 int MachCallRuntimeNode::ret_addr_offset() { | |
| 577 #ifdef _LP64 | |
| 578 return NativeFarCall::instruction_size; // farcall; delay slot | |
| 579 #else | |
| 580 return NativeCall::instruction_size; // call; delay slot | |
| 581 #endif | |
| 582 } | |
| 583 | |
| 584 // Indicate if the safepoint node needs the polling page as an input. | |
| 585 // Since Sparc does not have absolute addressing, it does. | |
| 586 bool SafePointNode::needs_polling_address_input() { | |
| 587 return true; | |
| 588 } | |
| 589 | |
| 590 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 591 void emit_break(CodeBuffer &cbuf) { | |
| 592 MacroAssembler _masm(&cbuf); | |
| 593 __ breakpoint_trap(); | |
| 594 } | |
| 595 | |
| 596 #ifndef PRODUCT | |
| 597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 598 st->print("TA"); | |
| 599 } | |
| 600 #endif | |
| 601 | |
| 602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 603 emit_break(cbuf); | |
| 604 } | |
| 605 | |
| 606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 607 return MachNode::size(ra_); | |
| 608 } | |
| 609 | |
| 610 // Traceable jump | |
| 611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 612 MacroAssembler _masm(&cbuf); | |
| 613 Register rdest = reg_to_register_object(jump_target); | |
| 614 __ JMP(rdest, 0); | |
| 615 __ delayed()->nop(); | |
| 616 } | |
| 617 | |
| 618 // Traceable jump and set exception pc | |
| 619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 620 MacroAssembler _masm(&cbuf); | |
| 621 Register rdest = reg_to_register_object(jump_target); | |
| 622 __ JMP(rdest, 0); | |
| 623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 624 } | |
| 625 | |
| 626 void emit_nop(CodeBuffer &cbuf) { | |
| 627 MacroAssembler _masm(&cbuf); | |
| 628 __ nop(); | |
| 629 } | |
| 630 | |
| 631 void emit_illtrap(CodeBuffer &cbuf) { | |
| 632 MacroAssembler _masm(&cbuf); | |
| 633 __ illtrap(0); | |
| 634 } | |
| 635 | |
| 636 | |
| 637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 638 assert(n->rule() != loadUB_rule, ""); | |
| 639 | |
| 640 intptr_t offset = 0; | |
| 641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 642 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 644 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 645 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 646 atype = atype->add_offset(offset); | |
| 647 assert(disp32 == offset, "wrong disp32"); | |
| 648 return atype->_offset; | |
| 649 } | |
| 650 | |
| 651 | |
| 652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 653 assert(n->rule() != loadUB_rule, ""); | |
| 654 | |
| 655 intptr_t offset = 0; | |
| 656 Node* addr = n->in(2); | |
| 657 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 659 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 660 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 662 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 663 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 664 } | |
| 665 offset = atype->is_ptr()->_offset; | |
| 666 if (offset != Type::OffsetBot) offset += disp32; | |
| 667 return offset; | |
| 668 } | |
| 669 | |
| 670 // Standard Sparc opcode form2 field breakdown | |
| 671 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 672 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 673 int op = (f30 << 30) | | |
| 674 (f29 << 29) | | |
| 675 (f25 << 25) | | |
| 676 (f22 << 22) | | |
| 677 (f20 << 20) | | |
| 678 (f19 << 19) | | |
| 679 (f0 << 0); | |
| 680 *((int*)(cbuf.code_end())) = op; | |
| 681 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 682 } | |
| 683 | |
| 684 // Standard Sparc opcode form2 field breakdown | |
| 685 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 686 f0 >>= 10; // Drop 10 bits | |
| 687 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 688 int op = (f30 << 30) | | |
| 689 (f25 << 25) | | |
| 690 (f22 << 22) | | |
| 691 (f0 << 0); | |
| 692 *((int*)(cbuf.code_end())) = op; | |
| 693 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 694 } | |
| 695 | |
| 696 // Standard Sparc opcode form3 field breakdown | |
| 697 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 698 int op = (f30 << 30) | | |
| 699 (f25 << 25) | | |
| 700 (f19 << 19) | | |
| 701 (f14 << 14) | | |
| 702 (f5 << 5) | | |
| 703 (f0 << 0); | |
| 704 *((int*)(cbuf.code_end())) = op; | |
| 705 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 706 } | |
| 707 | |
| 708 // Standard Sparc opcode form3 field breakdown | |
| 709 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 710 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 711 int op = (f30 << 30) | | |
| 712 (f25 << 25) | | |
| 713 (f19 << 19) | | |
| 714 (f14 << 14) | | |
| 715 (1 << 13) | // bit to indicate immediate-mode | |
| 716 (simm13<<0); | |
| 717 *((int*)(cbuf.code_end())) = op; | |
| 718 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 719 } | |
| 720 | |
| 721 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 722 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 723 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 724 } | |
| 725 | |
| 726 #ifdef ASSERT | |
| 727 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 728 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 729 warning("VerifyOops encountered unexpected instruction:"); | |
| 730 n->dump(2); | |
| 731 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 732 } | |
| 733 #endif | |
| 734 | |
| 735 | |
| 736 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 737 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 738 | |
| 739 #ifdef ASSERT | |
| 740 // The following code implements the +VerifyOops feature. | |
| 741 // It verifies oop values which are loaded into or stored out of | |
| 742 // the current method activation. +VerifyOops complements techniques | |
| 743 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 744 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 745 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 746 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 747 // to their point of creation. It can also serve as a cross-check | |
| 748 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 749 | |
| 750 // It would be good to verify oops at other points, especially | |
| 751 // when an oop is used as a base pointer for a load or store. | |
| 752 // This is presently difficult, because it is hard to know when | |
| 753 // a base address is biased or not. (If we had such information, | |
| 754 // it would be easy and useful to make a two-argument version of | |
| 755 // verify_oop which unbiases the base, and performs verification.) | |
| 756 | |
| 757 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 758 bool is_verified_oop_base = false; | |
| 759 bool is_verified_oop_load = false; | |
| 760 bool is_verified_oop_store = false; | |
| 761 int tmp_enc = -1; | |
| 762 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 763 // classify the op, mainly for an assert check | |
| 764 int st_op = 0, ld_op = 0; | |
| 765 switch (primary) { | |
| 766 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 767 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 768 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 769 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 770 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 771 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 772 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 773 | |
| 774 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
775 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 776 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 777 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 778 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 779 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 780 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 781 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 782 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 783 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 784 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 785 | |
| 786 default: ShouldNotReachHere(); | |
| 787 } | |
| 788 if (tertiary == REGP_OP) { | |
| 789 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 790 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 791 else ShouldNotReachHere(); | |
| 792 if (st_op) { | |
| 793 // a store | |
| 794 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 795 Node* n2 = n->in(3); | |
| 796 if (n2 != NULL) { | |
| 797 const Type* t = n2->bottom_type(); | |
| 798 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 799 } | |
| 800 } else { | |
| 801 // a load | |
| 802 const Type* t = n->bottom_type(); | |
| 803 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 804 } | |
| 805 } | |
| 806 | |
| 807 if (ld_op) { | |
| 808 // a Load | |
| 809 // inputs are (0:control, 1:memory, 2:address) | |
| 810 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 811 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 812 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 813 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 814 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 815 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 816 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 817 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 818 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 819 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 820 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 821 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 822 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 823 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
824 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
825 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
826 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
827 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && |
| 0 | 828 !(n->rule() == loadUB_rule)) { |
| 829 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 830 } | |
| 831 } else if (st_op) { | |
| 832 // a Store | |
| 833 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 834 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 835 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 836 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 837 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 838 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
839 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
840 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
841 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && |
| 0 | 842 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 843 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 844 } | |
| 845 } | |
| 846 | |
| 847 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 848 Node* addr = n->in(2); | |
| 849 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 850 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 851 if (atype != NULL) { | |
| 852 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 853 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 854 if (offset != offset_2) { | |
| 855 get_offset_from_base(n, atype, disp32); | |
| 856 get_offset_from_base_2(n, atype, disp32); | |
| 857 } | |
| 858 assert(offset == offset_2, "different offsets"); | |
| 859 if (offset == disp32) { | |
| 860 // we now know that src1 is a true oop pointer | |
| 861 is_verified_oop_base = true; | |
| 862 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 863 if( primary == Assembler::ldd_op3 ) { | |
| 864 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 865 } else { | |
| 866 tmp_enc = dst_enc; | |
| 867 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 868 assert(src1_enc != dst_enc, ""); | |
| 869 } | |
| 870 } | |
| 871 } | |
| 872 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 873 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 874 // loading the mark should not be allowed either, but | |
| 875 // we don't check this since it conflicts with InlineObjectHash | |
| 876 // usage of LoadINode to get the mark. We could keep the | |
| 877 // check if we create a new LoadMarkNode | |
| 878 // but do not verify the object before its header is initialized | |
| 879 ShouldNotReachHere(); | |
| 880 } | |
| 881 } | |
| 882 } | |
| 883 } | |
| 884 } | |
| 885 #endif | |
| 886 | |
| 887 uint instr; | |
| 888 instr = (Assembler::ldst_op << 30) | |
| 889 | (dst_enc << 25) | |
| 890 | (primary << 19) | |
| 891 | (src1_enc << 14); | |
| 892 | |
| 893 uint index = src2_enc; | |
| 894 int disp = disp32; | |
| 895 | |
| 896 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 897 disp += STACK_BIAS; | |
| 898 | |
| 899 // We should have a compiler bailout here rather than a guarantee. | |
| 900 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 901 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 902 | |
| 903 if( disp == 0 ) { | |
| 904 // use reg-reg form | |
| 905 // bit 13 is already zero | |
| 906 instr |= index; | |
| 907 } else { | |
| 908 // use reg-imm form | |
| 909 instr |= 0x00002000; // set bit 13 to one | |
| 910 instr |= disp & 0x1FFF; | |
| 911 } | |
| 912 | |
| 913 uint *code = (uint*)cbuf.code_end(); | |
| 914 *code = instr; | |
| 915 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 916 | |
| 917 #ifdef ASSERT | |
| 918 { | |
| 919 MacroAssembler _masm(&cbuf); | |
| 920 if (is_verified_oop_base) { | |
| 921 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 922 } | |
| 923 if (is_verified_oop_store) { | |
| 924 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 925 } | |
| 926 if (tmp_enc != -1) { | |
| 927 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 928 } | |
| 929 if (is_verified_oop_load) { | |
| 930 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 931 } | |
| 932 } | |
| 933 #endif | |
| 934 } | |
| 935 | |
| 936 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
| 937 // The method which records debug information at every safepoint | |
| 938 // expects the call to be the first instruction in the snippet as | |
| 939 // it creates a PcDesc structure which tracks the offset of a call | |
| 940 // from the start of the codeBlob. This offset is computed as | |
| 941 // code_end() - code_begin() of the code which has been emitted | |
| 942 // so far. | |
| 943 // In this particular case we have skirted around the problem by | |
| 944 // putting the "mov" instruction in the delay slot but the problem | |
| 945 // may bite us again at some other point and a cleaner/generic | |
| 946 // solution using relocations would be needed. | |
| 947 MacroAssembler _masm(&cbuf); | |
| 948 __ set_inst_mark(); | |
| 949 | |
| 950 // We flush the current window just so that there is a valid stack copy | |
| 951 // the fact that the current window becomes active again instantly is | |
| 952 // not a problem there is nothing live in it. | |
| 953 | |
| 954 #ifdef ASSERT | |
| 955 int startpos = __ offset(); | |
| 956 #endif /* ASSERT */ | |
| 957 | |
| 958 #ifdef _LP64 | |
| 959 // Calls to the runtime or native may not be reachable from compiled code, | |
| 960 // so we generate the far call sequence on 64 bit sparc. | |
| 961 // This code sequence is relocatable to any address, even on LP64. | |
| 962 if ( force_far_call ) { | |
| 963 __ relocate(rtype); | |
| 727 | 964 AddressLiteral dest(entry_point); |
| 965 __ jumpl_to(dest, O7, O7); | |
| 0 | 966 } |
| 967 else | |
| 968 #endif | |
| 969 { | |
| 970 __ call((address)entry_point, rtype); | |
| 971 } | |
| 972 | |
| 973 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 974 else __ delayed()->nop(); | |
| 975 | |
| 976 if (preserve_g2) __ mov(L7, G2); | |
| 977 | |
| 978 #ifdef ASSERT | |
| 979 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 980 #ifdef _LP64 | |
| 981 // Trash argument dump slots. | |
| 982 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 983 __ mov(G1, G5); | |
| 984 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 985 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 986 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 987 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 988 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 989 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 990 #else // _LP64 | |
| 991 // this is also a native call, so smash the first 7 stack locations, | |
| 992 // and the various registers | |
| 993 | |
| 994 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 995 // while [SP+0x44..0x58] are the argument dump slots. | |
| 996 __ set((intptr_t)0xbaadf00d, G1); | |
| 997 __ mov(G1, G5); | |
| 998 __ sllx(G1, 32, G1); | |
| 999 __ or3(G1, G5, G1); | |
| 1000 __ mov(G1, G5); | |
| 1001 __ stx(G1, SP, 0x40); | |
| 1002 __ stx(G1, SP, 0x48); | |
| 1003 __ stx(G1, SP, 0x50); | |
| 1004 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1005 #endif // _LP64 | |
| 1006 } | |
| 1007 #endif /*ASSERT*/ | |
| 1008 } | |
| 1009 | |
| 1010 //============================================================================= | |
| 1011 // REQUIRED FUNCTIONALITY for encoding | |
| 1012 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1013 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1014 | |
| 1015 | |
| 1016 //============================================================================= | |
| 1017 | |
| 1018 #ifndef PRODUCT | |
| 1019 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1020 Compile* C = ra_->C; | |
| 1021 | |
| 1022 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1023 st->print_cr("NOP"); st->print("\t"); | |
| 1024 } | |
| 1025 | |
| 1026 if( VerifyThread ) { | |
| 1027 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1028 } | |
| 1029 | |
| 1030 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1031 | |
| 1032 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1033 // We require that their callers must bang for them. But be careful, because | |
| 1034 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1035 // stack. But the stack safety zone should account for that. | |
| 1036 // See bugs 4446381, 4468289, 4497237. | |
| 1037 if (C->need_stack_bang(framesize)) { | |
| 1038 st->print_cr("! stack bang"); st->print("\t"); | |
| 1039 } | |
| 1040 | |
| 1041 if (Assembler::is_simm13(-framesize)) { | |
| 1042 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1043 } else { | |
| 1044 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1045 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1046 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1047 } | |
| 1048 | |
| 1049 } | |
| 1050 #endif | |
| 1051 | |
| 1052 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1053 Compile* C = ra_->C; | |
| 1054 MacroAssembler _masm(&cbuf); | |
| 1055 | |
| 1056 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1057 __ nop(); | |
| 1058 } | |
| 1059 | |
| 1060 __ verify_thread(); | |
| 1061 | |
| 1062 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1063 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1064 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1065 | |
| 1066 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1067 // We require that their callers must bang for them. But be careful, because | |
| 1068 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1069 // stack. But the stack safety zone should account for that. | |
| 1070 // See bugs 4446381, 4468289, 4497237. | |
| 1071 if (C->need_stack_bang(framesize)) { | |
| 1072 __ generate_stack_overflow_check(framesize); | |
| 1073 } | |
| 1074 | |
| 1075 if (Assembler::is_simm13(-framesize)) { | |
| 1076 __ save(SP, -framesize, SP); | |
| 1077 } else { | |
| 1078 __ sethi(-framesize & ~0x3ff, G3); | |
| 1079 __ add(G3, -framesize & 0x3ff, G3); | |
| 1080 __ save(SP, G3, SP); | |
| 1081 } | |
| 1082 C->set_frame_complete( __ offset() ); | |
| 1083 } | |
| 1084 | |
| 1085 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1086 return MachNode::size(ra_); | |
| 1087 } | |
| 1088 | |
| 1089 int MachPrologNode::reloc() const { | |
| 1090 return 10; // a large enough number | |
| 1091 } | |
| 1092 | |
| 1093 //============================================================================= | |
| 1094 #ifndef PRODUCT | |
| 1095 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1096 Compile* C = ra_->C; | |
| 1097 | |
| 1098 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1099 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1100 #ifdef _LP64 | |
| 1101 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1102 #else | |
| 1103 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1104 #endif | |
| 1105 } | |
| 1106 | |
| 1107 if( do_polling() ) | |
| 1108 st->print("RET\n\t"); | |
| 1109 | |
| 1110 st->print("RESTORE"); | |
| 1111 } | |
| 1112 #endif | |
| 1113 | |
| 1114 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1115 MacroAssembler _masm(&cbuf); | |
| 1116 Compile* C = ra_->C; | |
| 1117 | |
| 1118 __ verify_thread(); | |
| 1119 | |
| 1120 // If this does safepoint polling, then do it here | |
| 1121 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1122 AddressLiteral polling_page(os::get_polling_page()); |
| 1123 __ sethi(polling_page, L0); | |
| 0 | 1124 __ relocate(relocInfo::poll_return_type); |
| 1125 __ ld_ptr( L0, 0, G0 ); | |
| 1126 } | |
| 1127 | |
| 1128 // If this is a return, then stuff the restore in the delay slot | |
| 1129 if( do_polling() ) { | |
| 1130 __ ret(); | |
| 1131 __ delayed()->restore(); | |
| 1132 } else { | |
| 1133 __ restore(); | |
| 1134 } | |
| 1135 } | |
| 1136 | |
| 1137 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1138 return MachNode::size(ra_); | |
| 1139 } | |
| 1140 | |
| 1141 int MachEpilogNode::reloc() const { | |
| 1142 return 16; // a large enough number | |
| 1143 } | |
| 1144 | |
| 1145 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1146 return MachNode::pipeline_class(); | |
| 1147 } | |
| 1148 | |
| 1149 int MachEpilogNode::safepoint_offset() const { | |
| 1150 assert( do_polling(), "no return for this epilog node"); | |
| 1151 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
| 1152 } | |
| 1153 | |
| 1154 //============================================================================= | |
| 1155 | |
| 1156 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1157 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1158 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1159 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1160 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1161 VMReg r = OptoReg::as_VMReg(reg); | |
| 1162 if (r->is_Register()) return rc_int; | |
| 1163 assert(r->is_FloatRegister(), "must be"); | |
| 1164 return rc_float; | |
| 1165 } | |
| 1166 | |
| 1167 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1168 if( cbuf ) { | |
| 1169 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1170 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1171 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1172 } else { | |
| 1173 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1174 } | |
| 1175 } | |
| 1176 #ifndef PRODUCT | |
| 1177 else if( !do_size ) { | |
| 1178 if( size != 0 ) st->print("\n\t"); | |
| 1179 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1180 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1181 } | |
| 1182 #endif | |
| 1183 return size+4; | |
| 1184 } | |
| 1185 | |
| 1186 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1187 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1188 #ifndef PRODUCT | |
| 1189 else if( !do_size ) { | |
| 1190 if( size != 0 ) st->print("\n\t"); | |
| 1191 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1192 } | |
| 1193 #endif | |
| 1194 return size+4; | |
| 1195 } | |
| 1196 | |
| 1197 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1198 PhaseRegAlloc *ra_, | |
| 1199 bool do_size, | |
| 1200 outputStream* st ) const { | |
| 1201 // Get registers to move | |
| 1202 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1203 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1204 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1205 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1206 | |
| 1207 enum RC src_second_rc = rc_class(src_second); | |
| 1208 enum RC src_first_rc = rc_class(src_first); | |
| 1209 enum RC dst_second_rc = rc_class(dst_second); | |
| 1210 enum RC dst_first_rc = rc_class(dst_first); | |
| 1211 | |
| 1212 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1213 | |
| 1214 // Generate spill code! | |
| 1215 int size = 0; | |
| 1216 | |
| 1217 if( src_first == dst_first && src_second == dst_second ) | |
| 1218 return size; // Self copy, no move | |
| 1219 | |
| 1220 // -------------------------------------- | |
| 1221 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1222 // the float-store case. | |
| 1223 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1224 int offset = ra_->reg2offset(src_first); | |
| 1225 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1226 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1227 src_second = OptoReg::Name(R_F31_num); | |
| 1228 src_second_rc = rc_float; | |
| 1229 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1230 } else { | |
| 1231 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1232 } | |
| 1233 src_first = OptoReg::Name(R_F30_num); | |
| 1234 src_first_rc = rc_float; | |
| 1235 } | |
| 1236 | |
| 1237 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1238 int offset = ra_->reg2offset(src_second); | |
| 1239 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1240 src_second = OptoReg::Name(R_F31_num); | |
| 1241 src_second_rc = rc_float; | |
| 1242 } | |
| 1243 | |
| 1244 // -------------------------------------- | |
| 1245 // Check for float->int copy; requires a trip through memory | |
| 1246 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
| 1247 int offset = frame::register_save_words*wordSize; | |
| 1248 if( cbuf ) { | |
| 1249 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
| 1250 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1251 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1252 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1253 } | |
| 1254 #ifndef PRODUCT | |
| 1255 else if( !do_size ) { | |
| 1256 if( size != 0 ) st->print("\n\t"); | |
| 1257 st->print( "SUB R_SP,16,R_SP\n"); | |
| 1258 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1259 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1260 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1261 } | |
| 1262 #endif | |
| 1263 size += 16; | |
| 1264 } | |
| 1265 | |
| 1266 // -------------------------------------- | |
| 1267 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1268 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1269 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1270 // there. Misaligned sources only come from native-long-returns (handled | |
| 1271 // special below). | |
| 1272 #ifndef _LP64 | |
| 1273 if( src_first_rc == rc_int && // source is already big-endian | |
| 1274 src_second_rc != rc_bad && // 64-bit move | |
| 1275 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1276 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1277 // Do the big-endian flop. | |
| 1278 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1279 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1280 } | |
| 1281 #endif | |
| 1282 | |
| 1283 // -------------------------------------- | |
| 1284 // Check for integer reg-reg copy | |
| 1285 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1286 #ifndef _LP64 | |
| 1287 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1288 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1289 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1290 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1291 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1292 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1293 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1294 if( cbuf ) { | |
| 1295 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1296 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1297 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1298 #ifndef PRODUCT | |
| 1299 } else if( !do_size ) { | |
| 1300 if( size != 0 ) st->print("\n\t"); | |
| 1301 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1302 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1303 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1304 #endif | |
| 1305 } | |
| 1306 return size+12; | |
| 1307 } | |
| 1308 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1309 // returning a long value in I0/I1 | |
| 1310 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1311 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1312 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1313 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1314 OptoReg::Name tdest = dst_first; | |
| 1315 | |
| 1316 if (src_first == dst_first) { | |
| 1317 tdest = OptoReg::Name(R_O7_num); | |
| 1318 size += 4; | |
| 1319 } | |
| 1320 | |
| 1321 if( cbuf ) { | |
| 1322 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1323 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1324 // ShrL_reg_imm6 | |
| 1325 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1326 // ShrR_reg_imm6 src, 0, dst | |
| 1327 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1328 if (tdest != dst_first) { | |
| 1329 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1330 } | |
| 1331 } | |
| 1332 #ifndef PRODUCT | |
| 1333 else if( !do_size ) { | |
| 1334 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1335 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1336 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1337 if (tdest != dst_first) { | |
| 1338 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1339 } | |
| 1340 } | |
| 1341 #endif // PRODUCT | |
| 1342 return size+8; | |
| 1343 } | |
| 1344 #endif // !_LP64 | |
| 1345 // Else normal reg-reg copy | |
| 1346 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1347 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1348 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1349 // This moves an aligned adjacent pair. | |
| 1350 // See if we are done. | |
| 1351 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1352 return size; | |
| 1353 } | |
| 1354 | |
| 1355 // Check for integer store | |
| 1356 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1357 int offset = ra_->reg2offset(dst_first); | |
| 1358 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1359 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1360 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1361 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1362 } | |
| 1363 | |
| 1364 // Check for integer load | |
| 1365 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1366 int offset = ra_->reg2offset(src_first); | |
| 1367 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1368 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1369 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1370 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1371 } | |
| 1372 | |
| 1373 // Check for float reg-reg copy | |
| 1374 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1375 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1376 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1377 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1378 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1379 } | |
| 1380 | |
| 1381 // Check for float store | |
| 1382 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1383 int offset = ra_->reg2offset(dst_first); | |
| 1384 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1385 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1386 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1387 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1388 } | |
| 1389 | |
| 1390 // Check for float load | |
| 1391 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1392 int offset = ra_->reg2offset(src_first); | |
| 1393 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1394 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1395 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1396 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1397 } | |
| 1398 | |
| 1399 // -------------------------------------------------------------------- | |
| 1400 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1401 // arguments to native calls. | |
| 1402 if( src_second == dst_second ) | |
| 1403 return size; // Self copy; no move | |
| 1404 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1405 | |
| 1406 #ifndef _LP64 | |
| 1407 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1408 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1409 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1410 // all sorts of silly alignment problems. | |
| 1411 | |
| 1412 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1413 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1414 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1415 // happened already as part of a 64-bit move) | |
| 1416 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1417 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1418 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1419 // Shift src_second down to dst_second's low bits. | |
| 1420 if( cbuf ) { | |
| 1421 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1422 #ifndef PRODUCT | |
| 1423 } else if( !do_size ) { | |
| 1424 if( size != 0 ) st->print("\n\t"); | |
| 1425 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1426 #endif | |
| 1427 } | |
| 1428 return size+4; | |
| 1429 } | |
| 1430 | |
| 1431 // Check for high word integer store. Must down-shift the hi bits | |
| 1432 // into a temp register, then fall into the case of storing int bits. | |
| 1433 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1434 // Shift src_second down to dst_second's low bits. | |
| 1435 if( cbuf ) { | |
| 1436 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1437 #ifndef PRODUCT | |
| 1438 } else if( !do_size ) { | |
| 1439 if( size != 0 ) st->print("\n\t"); | |
| 1440 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1441 #endif | |
| 1442 } | |
| 1443 size+=4; | |
| 1444 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1445 } | |
| 1446 | |
| 1447 // Check for high word integer load | |
| 1448 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1449 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1450 | |
| 1451 // Check for high word integer store | |
| 1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1453 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1454 | |
| 1455 // Check for high word float store | |
| 1456 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1457 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1458 | |
| 1459 #endif // !_LP64 | |
| 1460 | |
| 1461 Unimplemented(); | |
| 1462 } | |
| 1463 | |
| 1464 #ifndef PRODUCT | |
| 1465 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1466 implementation( NULL, ra_, false, st ); | |
| 1467 } | |
| 1468 #endif | |
| 1469 | |
| 1470 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1471 implementation( &cbuf, ra_, false, NULL ); | |
| 1472 } | |
| 1473 | |
| 1474 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1475 return implementation( NULL, ra_, true, NULL ); | |
| 1476 } | |
| 1477 | |
| 1478 //============================================================================= | |
| 1479 #ifndef PRODUCT | |
| 1480 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1481 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1482 } | |
| 1483 #endif | |
| 1484 | |
| 1485 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1486 MacroAssembler _masm(&cbuf); | |
| 1487 for(int i = 0; i < _count; i += 1) { | |
| 1488 __ nop(); | |
| 1489 } | |
| 1490 } | |
| 1491 | |
| 1492 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1493 return 4 * _count; | |
| 1494 } | |
| 1495 | |
| 1496 | |
| 1497 //============================================================================= | |
| 1498 #ifndef PRODUCT | |
| 1499 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1500 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1501 int reg = ra_->get_reg_first(this); | |
| 1502 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1503 } | |
| 1504 #endif | |
| 1505 | |
| 1506 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1507 MacroAssembler _masm(&cbuf); | |
| 1508 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1509 int reg = ra_->get_encode(this); | |
| 1510 | |
| 1511 if (Assembler::is_simm13(offset)) { | |
| 1512 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1513 } else { | |
| 1514 __ set(offset, O7); | |
| 1515 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1516 } | |
| 1517 } | |
| 1518 | |
| 1519 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1520 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1521 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1522 return ra_->C->scratch_emit_size(this); | |
| 1523 } | |
| 1524 | |
| 1525 //============================================================================= | |
| 1526 | |
| 1527 // emit call stub, compiled java to interpretor | |
| 1528 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1529 | |
| 1530 // Stub is fixed up when the corresponding call is converted from calling | |
| 1531 // compiled code to calling interpreted code. | |
| 1532 // set (empty), G5 | |
| 1533 // jmp -1 | |
| 1534 | |
| 1535 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1536 | |
| 1537 MacroAssembler _masm(&cbuf); | |
| 1538 | |
| 1539 address base = | |
| 1540 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1541 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1542 | |
| 1543 // static stub relocation stores the instruction address of the call | |
| 1544 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1545 | |
| 1546 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1547 | |
| 1548 __ set_inst_mark(); | |
| 727 | 1549 AddressLiteral addrlit(-1); |
| 1550 __ JUMP(addrlit, G3, 0); | |
| 0 | 1551 |
| 1552 __ delayed()->nop(); | |
| 1553 | |
| 1554 // Update current stubs pointer and restore code_end. | |
| 1555 __ end_a_stub(); | |
| 1556 } | |
| 1557 | |
| 1558 // size of call stub, compiled java to interpretor | |
| 1559 uint size_java_to_interp() { | |
| 1560 // This doesn't need to be accurate but it must be larger or equal to | |
| 1561 // the real size of the stub. | |
| 1562 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1563 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1564 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1565 } | |
| 1566 // relocation entries for call stub, compiled java to interpretor | |
| 1567 uint reloc_java_to_interp() { | |
| 1568 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1569 } | |
| 1570 | |
| 1571 | |
| 1572 //============================================================================= | |
| 1573 #ifndef PRODUCT | |
| 1574 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1575 st->print_cr("\nUEP:"); | |
| 1576 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1577 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1578 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1579 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1580 st->print_cr("\tSLL R_G5,3,R_G5"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1581 if (Universe::narrow_oop_base() != NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1582 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1583 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1584 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1585 } |
| 0 | 1586 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1587 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1588 #else // _LP64 | |
| 1589 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1590 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1591 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1592 #endif // _LP64 | |
| 1593 } | |
| 1594 #endif | |
| 1595 | |
| 1596 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1597 MacroAssembler _masm(&cbuf); | |
| 1598 Label L; | |
| 1599 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1600 Register temp_reg = G3; | |
| 1601 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1602 | |
| 605 | 1603 // Load klass from receiver |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1604 __ load_klass(O0, temp_reg); |
| 0 | 1605 // Compare against expected klass |
| 1606 __ cmp(temp_reg, G5_ic_reg); | |
| 1607 // Branch to miss code, checks xcc or icc depending | |
| 1608 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1609 } | |
| 1610 | |
| 1611 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1612 return MachNode::size(ra_); | |
| 1613 } | |
| 1614 | |
| 1615 | |
| 1616 //============================================================================= | |
| 1617 | |
| 1618 uint size_exception_handler() { | |
| 1619 if (TraceJumps) { | |
| 1620 return (400); // just a guess | |
| 1621 } | |
| 1622 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1623 } | |
| 1624 | |
| 1625 uint size_deopt_handler() { | |
| 1626 if (TraceJumps) { | |
| 1627 return (400); // just a guess | |
| 1628 } | |
| 1629 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1630 } | |
| 1631 | |
| 1632 // Emit exception handler code. | |
| 1633 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1634 Register temp_reg = G3; | |
| 727 | 1635 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); |
| 0 | 1636 MacroAssembler _masm(&cbuf); |
| 1637 | |
| 1638 address base = | |
| 1639 __ start_a_stub(size_exception_handler()); | |
| 1640 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1641 | |
| 1642 int offset = __ offset(); | |
| 1643 | |
| 727 | 1644 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1645 __ delayed()->nop(); |
| 1646 | |
| 1647 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1648 | |
| 1649 __ end_a_stub(); | |
| 1650 | |
| 1651 return offset; | |
| 1652 } | |
| 1653 | |
| 1654 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1655 // Can't use any of the current frame's registers as we may have deopted | |
| 1656 // at a poll and everything (including G3) can be live. | |
| 1657 Register temp_reg = L0; | |
| 727 | 1658 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1659 MacroAssembler _masm(&cbuf); |
| 1660 | |
| 1661 address base = | |
| 1662 __ start_a_stub(size_deopt_handler()); | |
| 1663 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1664 | |
| 1665 int offset = __ offset(); | |
| 1666 __ save_frame(0); | |
| 727 | 1667 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1668 __ delayed()->restore(); |
| 1669 | |
| 1670 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1671 | |
| 1672 __ end_a_stub(); | |
| 1673 return offset; | |
| 1674 | |
| 1675 } | |
| 1676 | |
| 1677 // Given a register encoding, produce a Integer Register object | |
| 1678 static Register reg_to_register_object(int register_encoding) { | |
| 1679 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1680 return as_Register(register_encoding); | |
| 1681 } | |
| 1682 | |
| 1683 // Given a register encoding, produce a single-precision Float Register object | |
| 1684 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1685 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1686 return as_SingleFloatRegister(register_encoding); | |
| 1687 } | |
| 1688 | |
| 1689 // Given a register encoding, produce a double-precision Float Register object | |
| 1690 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1691 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1692 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1693 return as_DoubleFloatRegister(register_encoding); | |
| 1694 } | |
| 1695 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1696 const bool Matcher::match_rule_supported(int opcode) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1697 if (!has_match_rule(opcode)) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1698 return false; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1699 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1700 switch (opcode) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1701 case Op_CountLeadingZerosI: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1702 case Op_CountLeadingZerosL: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1703 case Op_CountTrailingZerosI: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1704 case Op_CountTrailingZerosL: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1705 if (!UsePopCountInstruction) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1706 return false; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1707 break; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1708 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1709 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1710 return true; // Per default match rules are supported. |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1711 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1712 |
| 0 | 1713 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1714 return regnum - 32; // The FP registers are in the second chunk | |
| 1715 } | |
| 1716 | |
| 1717 #ifdef ASSERT | |
| 1718 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1719 #endif | |
| 1720 | |
| 1721 // Vector width in bytes | |
| 1722 const uint Matcher::vector_width_in_bytes(void) { | |
| 1723 return 8; | |
| 1724 } | |
| 1725 | |
| 1726 // Vector ideal reg | |
| 1727 const uint Matcher::vector_ideal_reg(void) { | |
| 1728 return Op_RegD; | |
| 1729 } | |
| 1730 | |
| 1731 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1732 const bool Matcher::convL2FSupported(void) { | |
| 1733 return VM_Version::has_fast_fxtof(); | |
| 1734 } | |
| 1735 | |
| 1736 // Is this branch offset short enough that a short branch can be used? | |
| 1737 // | |
| 1738 // NOTE: If the platform does not provide any short branch variants, then | |
| 1739 // this method should return false for offset 0. | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1740 bool Matcher::is_short_branch_offset(int rule, int offset) { |
| 0 | 1741 return false; |
| 1742 } | |
| 1743 | |
| 1744 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1745 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1746 // Depends on optimizations in MacroAssembler::setx. | |
| 1747 int hi = (int)(value >> 32); | |
| 1748 int lo = (int)(value & ~0); | |
| 1749 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1750 } | |
| 1751 | |
| 1752 // No scaling for the parameter the ClearArray node. | |
| 1753 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1754 | |
| 1755 // Threshold size for cleararray. | |
| 1756 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1757 | |
| 1758 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1759 // be subsumed into complex addressing expressions or compute them into | |
| 1760 // registers? True for Intel but false for most RISCs | |
| 1761 const bool Matcher::clone_shift_expressions = false; | |
| 1762 | |
| 1763 // Is it better to copy float constants, or load them directly from memory? | |
| 1764 // Intel can load a float constant from a direct address, requiring no | |
| 1765 // extra registers. Most RISCs will have to materialize an address into a | |
| 1766 // register first, so they would do better to copy the constant from stack. | |
| 1767 const bool Matcher::rematerialize_float_constants = false; | |
| 1768 | |
| 1769 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1770 // needed. Else we split the double into 2 integer pieces and move it | |
| 1771 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1772 // Java calling convention forces doubles to be aligned. | |
| 1773 #ifdef _LP64 | |
| 1774 const bool Matcher::misaligned_doubles_ok = true; | |
| 1775 #else | |
| 1776 const bool Matcher::misaligned_doubles_ok = false; | |
| 1777 #endif | |
| 1778 | |
| 1779 // No-op on SPARC. | |
| 1780 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1781 } | |
| 1782 | |
| 1783 // Advertise here if the CPU requires explicit rounding operations | |
| 1784 // to implement the UseStrictFP mode. | |
| 1785 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1786 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1787 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1788 // Sparc does not handle callee-save floats. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1789 bool Matcher::float_in_double() { return false; } |
| 0 | 1790 |
| 1791 // Do ints take an entire long register or just half? | |
| 1792 // Note that we if-def off of _LP64. | |
| 1793 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1794 // the whole long is written but de-opt'ing will have to extract | |
| 1795 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1796 #ifdef _LP64 | |
| 1797 const bool Matcher::int_in_long = true; | |
| 1798 #else | |
| 1799 const bool Matcher::int_in_long = false; | |
| 1800 #endif | |
| 1801 | |
| 1802 // Return whether or not this register is ever used as an argument. This | |
| 1803 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1804 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1805 // arguments in those registers not be available to the callee. | |
| 1806 bool Matcher::can_be_java_arg( int reg ) { | |
| 1807 // Standard sparc 6 args in registers | |
| 1808 if( reg == R_I0_num || | |
| 1809 reg == R_I1_num || | |
| 1810 reg == R_I2_num || | |
| 1811 reg == R_I3_num || | |
| 1812 reg == R_I4_num || | |
| 1813 reg == R_I5_num ) return true; | |
| 1814 #ifdef _LP64 | |
| 1815 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1816 // the high I registers | |
| 1817 if( reg == R_I0H_num || | |
| 1818 reg == R_I1H_num || | |
| 1819 reg == R_I2H_num || | |
| 1820 reg == R_I3H_num || | |
| 1821 reg == R_I4H_num || | |
| 1822 reg == R_I5H_num ) return true; | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1823 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1824 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1825 return true; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1826 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1827 |
| 0 | 1828 #else |
| 1829 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1830 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1831 // after a 'save' and I regs get their high bits chopped off on | |
| 1832 // interrupt. | |
| 1833 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1834 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1835 #endif | |
| 1836 // A few float args in registers | |
| 1837 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1838 | |
| 1839 return false; | |
| 1840 } | |
| 1841 | |
| 1842 bool Matcher::is_spillable_arg( int reg ) { | |
| 1843 return can_be_java_arg(reg); | |
| 1844 } | |
| 1845 | |
| 1846 // Register for DIVI projection of divmodI | |
| 1847 RegMask Matcher::divI_proj_mask() { | |
| 1848 ShouldNotReachHere(); | |
| 1849 return RegMask(); | |
| 1850 } | |
| 1851 | |
| 1852 // Register for MODI projection of divmodI | |
| 1853 RegMask Matcher::modI_proj_mask() { | |
| 1854 ShouldNotReachHere(); | |
| 1855 return RegMask(); | |
| 1856 } | |
| 1857 | |
| 1858 // Register for DIVL projection of divmodL | |
| 1859 RegMask Matcher::divL_proj_mask() { | |
| 1860 ShouldNotReachHere(); | |
| 1861 return RegMask(); | |
| 1862 } | |
| 1863 | |
| 1864 // Register for MODL projection of divmodL | |
| 1865 RegMask Matcher::modL_proj_mask() { | |
| 1866 ShouldNotReachHere(); | |
| 1867 return RegMask(); | |
| 1868 } | |
| 1869 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
1870 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
| 1567 | 1871 return L7_REGP_mask; |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
1872 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
1873 |
| 0 | 1874 %} |
| 1875 | |
| 1876 | |
| 1877 // The intptr_t operand types, defined by textual substitution. | |
| 1878 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1879 #ifdef _LP64 | |
| 824 | 1880 #define immX immL |
| 1881 #define immX13 immL13 | |
| 1882 #define immX13m7 immL13m7 | |
| 1883 #define iRegX iRegL | |
| 1884 #define g1RegX g1RegL | |
| 0 | 1885 #else |
| 824 | 1886 #define immX immI |
| 1887 #define immX13 immI13 | |
| 1888 #define immX13m7 immI13m7 | |
| 1889 #define iRegX iRegI | |
| 1890 #define g1RegX g1RegI | |
| 0 | 1891 #endif |
| 1892 | |
| 1893 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1894 // This block specifies the encoding classes used by the compiler to output | |
| 1895 // byte streams. Encoding classes are parameterized macros used by | |
| 1896 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1897 // instruction. Operands specify their base encoding interface with the | |
| 1898 // interface keyword. There are currently supported four interfaces, | |
| 1899 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1900 // operand to generate a function which returns its register number when | |
| 1901 // queried. CONST_INTER causes an operand to generate a function which | |
| 1902 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1903 // operand to generate four functions which return the Base Register, the | |
| 1904 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1905 // queried. COND_INTER causes an operand to generate six functions which | |
| 1906 // return the encoding code (ie - encoding bits for the instruction) | |
| 1907 // associated with each basic boolean condition for a conditional instruction. | |
| 1908 // | |
| 1909 // Instructions specify two basic values for encoding. Again, a function | |
| 1910 // is available to check if the constant displacement is an oop. They use the | |
| 1911 // ins_encode keyword to specify their encoding classes (which must be | |
| 1912 // a sequence of enc_class names, and their parameters, specified in | |
| 1913 // the encoding block), and they use the | |
| 1914 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1915 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1916 // needs for encoding need to be specified. | |
| 1917 encode %{ | |
| 1918 enc_class enc_untested %{ | |
| 1919 #ifdef ASSERT | |
| 1920 MacroAssembler _masm(&cbuf); | |
| 1921 __ untested("encoding"); | |
| 1922 #endif | |
| 1923 %} | |
| 1924 | |
| 1925 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 1926 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 1927 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 1928 %} | |
| 1929 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1930 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1931 emit_form3_mem_reg(cbuf, this, $primary, -1, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1932 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1933 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1934 |
| 0 | 1935 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1936 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 1937 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 1938 %} | |
| 1939 | |
| 1940 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1941 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 1942 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 1943 %} | |
| 1944 | |
| 1945 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 1946 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 1947 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 1948 guarantee($mem$$index == R_G0_enc, "double index?"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1949 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1950 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 1951 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 1952 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 1953 %} | |
| 1954 | |
| 1955 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 1956 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 1957 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 1958 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 1959 // Load long with 2 instructions | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 1962 %} |
| 1963 | |
| 1964 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 1965 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 1966 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 1968 %} |
| 1969 | |
| 1970 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 1971 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1972 if( $rs2$$reg != $rd$$reg ) | |
| 1973 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 1974 %} | |
| 1975 | |
| 1976 // Target lo half of long | |
| 1977 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 1978 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1979 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 1980 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 1981 %} | |
| 1982 | |
| 1983 // Source lo half of long | |
| 1984 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 1985 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1986 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 1987 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 1988 %} | |
| 1989 | |
| 1990 // Target hi half of long | |
| 1991 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 1992 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 1993 %} | |
| 1994 | |
| 1995 // Source lo half of long, and leave it sign extended. | |
| 1996 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 1997 // Sign extend low half | |
| 1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 1999 %} | |
| 2000 | |
| 2001 // Source hi half of long, and leave it sign extended. | |
| 2002 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2003 // Shift high half to low half | |
| 2004 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2005 %} | |
| 2006 | |
| 2007 // Source hi half of long | |
| 2008 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2009 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2010 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2011 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2012 %} | |
| 2013 | |
| 2014 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2015 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2016 %} | |
| 2017 | |
| 2018 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2019 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2020 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2021 %} | |
| 2022 | |
| 2023 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2024 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2025 // clear if nothing else is happening | |
| 2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2027 // blt,a,pn done | |
| 2028 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2029 // mov dst,-1 in delay slot | |
| 2030 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2031 %} | |
| 2032 | |
| 2033 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2034 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2035 %} | |
| 2036 | |
| 2037 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2038 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2039 %} | |
| 2040 | |
| 2041 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2042 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2043 %} | |
| 2044 | |
| 2045 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2046 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2047 %} | |
| 2048 | |
| 2049 enc_class move_return_pc_to_o1() %{ | |
| 2050 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2051 %} | |
| 2052 | |
| 2053 #ifdef _LP64 | |
| 2054 /* %%% merge with enc_to_bool */ | |
| 2055 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2056 MacroAssembler _masm(&cbuf); | |
| 2057 | |
| 2058 Register src_reg = reg_to_register_object($src$$reg); | |
| 2059 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2060 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2061 %} | |
| 2062 #endif | |
| 2063 | |
| 2064 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2065 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2066 MacroAssembler _masm(&cbuf); | |
| 2067 | |
| 2068 Register p_reg = reg_to_register_object($p$$reg); | |
| 2069 Register q_reg = reg_to_register_object($q$$reg); | |
| 2070 Register y_reg = reg_to_register_object($y$$reg); | |
| 2071 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2072 | |
| 2073 __ subcc( p_reg, q_reg, p_reg ); | |
| 2074 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2075 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2076 %} | |
| 2077 | |
| 2078 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2079 // fcmp %fcc0,$src,$src | |
| 2080 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2081 // branch %fcc0 not-nan, predict taken | |
| 2082 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2083 // fdtoi $src,$dst | |
| 2084 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2085 // fitos $dst,$dst (if nan) | |
| 2086 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2087 // clear $dst (if nan) | |
| 2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2089 // carry on here... | |
| 2090 %} | |
| 2091 | |
| 2092 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2093 // fcmp %fcc0,$src,$src check for NAN | |
| 2094 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2095 // branch %fcc0 not-nan, predict taken | |
| 2096 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2097 // fdtox $src,$dst convert in delay slot | |
| 2098 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2099 // fxtod $dst,$dst (if nan) | |
| 2100 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2101 // clear $dst (if nan) | |
| 2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2103 // carry on here... | |
| 2104 %} | |
| 2105 | |
| 2106 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2107 // fcmps %fcc0,$src,$src | |
| 2108 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2109 // branch %fcc0 not-nan, predict taken | |
| 2110 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2111 // fstoi $src,$dst | |
| 2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2113 // fitos $dst,$dst (if nan) | |
| 2114 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2115 // clear $dst (if nan) | |
| 2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2117 // carry on here... | |
| 2118 %} | |
| 2119 | |
| 2120 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2121 // fcmps %fcc0,$src,$src | |
| 2122 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2123 // branch %fcc0 not-nan, predict taken | |
| 2124 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2125 // fstox $src,$dst | |
| 2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2127 // fxtod $dst,$dst (if nan) | |
| 2128 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2129 // clear $dst (if nan) | |
| 2130 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2131 // carry on here... | |
| 2132 %} | |
| 2133 | |
| 2134 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2135 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2136 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2137 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2138 | |
| 2139 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2140 | |
| 2141 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2142 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2143 | |
| 2144 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2145 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2146 %} | |
| 2147 | |
| 2148 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2149 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2150 %} | |
| 2151 | |
| 2152 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2153 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2154 %} | |
| 2155 | |
| 2156 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2157 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2158 %} | |
| 2159 | |
| 2160 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2161 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2162 %} | |
| 2163 | |
| 2164 // Encloding class for traceable jumps | |
| 2165 enc_class form_jmpl(g3RegP dest) %{ | |
| 2166 emit_jmpl(cbuf, $dest$$reg); | |
| 2167 %} | |
| 2168 | |
| 2169 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2170 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2171 %} | |
| 2172 | |
| 2173 enc_class form2_nop() %{ | |
| 2174 emit_nop(cbuf); | |
| 2175 %} | |
| 2176 | |
| 2177 enc_class form2_illtrap() %{ | |
| 2178 emit_illtrap(cbuf); | |
| 2179 %} | |
| 2180 | |
| 2181 | |
| 2182 // Compare longs and convert into -1, 0, 1. | |
| 2183 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2184 // CMP $src1,$src2 | |
| 2185 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2186 // blt,a,pn done | |
| 2187 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2188 // mov dst,-1 in delay slot | |
| 2189 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2190 // bgt,a,pn done | |
| 2191 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2192 // mov dst,1 in delay slot | |
| 2193 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2194 // CLR $dst | |
| 2195 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2196 %} | |
| 2197 | |
| 2198 enc_class enc_PartialSubtypeCheck() %{ | |
| 2199 MacroAssembler _masm(&cbuf); | |
| 2200 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2201 __ delayed()->nop(); | |
| 2202 %} | |
| 2203 | |
| 2204 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
| 2205 MacroAssembler _masm(&cbuf); | |
| 2206 Label &L = *($labl$$label); | |
| 2207 Assembler::Predict predict_taken = | |
| 2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2209 | |
| 2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
| 2211 __ delayed()->nop(); | |
| 2212 %} | |
| 2213 | |
| 2214 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
| 2215 MacroAssembler _masm(&cbuf); | |
| 2216 Label &L = *($labl$$label); | |
| 2217 Assembler::Predict predict_taken = | |
| 2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2219 | |
| 2220 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
| 2221 __ delayed()->nop(); | |
| 2222 %} | |
| 2223 | |
| 2224 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
| 2225 MacroAssembler _masm(&cbuf); | |
| 2226 Label &L = *($labl$$label); | |
| 2227 Assembler::Predict predict_taken = | |
| 2228 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2229 | |
| 2230 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
| 2231 __ delayed()->nop(); | |
| 2232 %} | |
| 2233 | |
| 2234 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
| 2235 MacroAssembler _masm(&cbuf); | |
| 2236 Label &L = *($labl$$label); | |
| 2237 Assembler::Predict predict_taken = | |
| 2238 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2239 | |
| 2240 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
| 2241 __ delayed()->nop(); | |
| 2242 %} | |
| 2243 | |
| 2244 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
| 2245 MacroAssembler _masm(&cbuf); | |
| 2246 | |
| 2247 Register switch_reg = as_Register($switch_val$$reg); | |
| 2248 Register table_reg = O7; | |
| 2249 | |
| 2250 address table_base = __ address_table_constant(_index2label); | |
| 2251 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
| 2252 | |
| 727 | 2253 // Move table address into a register. |
| 2254 __ set(table_base, table_reg, rspec); | |
| 0 | 2255 |
| 2256 // Jump to base address + switch value | |
| 2257 __ ld_ptr(table_reg, switch_reg, table_reg); | |
| 2258 __ jmp(table_reg, G0); | |
| 2259 __ delayed()->nop(); | |
| 2260 | |
| 2261 %} | |
| 2262 | |
| 2263 enc_class enc_ba( Label labl ) %{ | |
| 2264 MacroAssembler _masm(&cbuf); | |
| 2265 Label &L = *($labl$$label); | |
| 2266 __ ba(false, L); | |
| 2267 __ delayed()->nop(); | |
| 2268 %} | |
| 2269 | |
| 2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
| 2271 MacroAssembler _masm(&cbuf); | |
| 2272 Label &L = *$labl$$label; | |
| 2273 Assembler::Predict predict_taken = | |
| 2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2275 | |
| 2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
| 2277 __ delayed()->nop(); | |
| 2278 %} | |
| 2279 | |
| 2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2281 int op = (Assembler::arith_op << 30) | | |
| 2282 ($dst$$reg << 25) | | |
| 2283 (Assembler::movcc_op3 << 19) | | |
| 2284 (1 << 18) | // cc2 bit for 'icc' | |
| 2285 ($cmp$$cmpcode << 14) | | |
| 2286 (0 << 13) | // select register move | |
| 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2288 ($src$$reg << 0); | |
| 2289 *((int*)(cbuf.code_end())) = op; | |
| 2290 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2291 %} | |
| 2292 | |
| 2293 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2294 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2295 int op = (Assembler::arith_op << 30) | | |
| 2296 ($dst$$reg << 25) | | |
| 2297 (Assembler::movcc_op3 << 19) | | |
| 2298 (1 << 18) | // cc2 bit for 'icc' | |
| 2299 ($cmp$$cmpcode << 14) | | |
| 2300 (1 << 13) | // select immediate move | |
| 2301 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2302 (simm11 << 0); | |
| 2303 *((int*)(cbuf.code_end())) = op; | |
| 2304 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2305 %} | |
| 2306 | |
| 2307 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2308 int op = (Assembler::arith_op << 30) | | |
| 2309 ($dst$$reg << 25) | | |
| 2310 (Assembler::movcc_op3 << 19) | | |
| 2311 (0 << 18) | // cc2 bit for 'fccX' | |
| 2312 ($cmp$$cmpcode << 14) | | |
| 2313 (0 << 13) | // select register move | |
| 2314 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2315 ($src$$reg << 0); | |
| 2316 *((int*)(cbuf.code_end())) = op; | |
| 2317 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2318 %} | |
| 2319 | |
| 2320 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2321 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2322 int op = (Assembler::arith_op << 30) | | |
| 2323 ($dst$$reg << 25) | | |
| 2324 (Assembler::movcc_op3 << 19) | | |
| 2325 (0 << 18) | // cc2 bit for 'fccX' | |
| 2326 ($cmp$$cmpcode << 14) | | |
| 2327 (1 << 13) | // select immediate move | |
| 2328 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2329 (simm11 << 0); | |
| 2330 *((int*)(cbuf.code_end())) = op; | |
| 2331 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2332 %} | |
| 2333 | |
| 2334 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2335 int op = (Assembler::arith_op << 30) | | |
| 2336 ($dst$$reg << 25) | | |
| 2337 (Assembler::fpop2_op3 << 19) | | |
| 2338 (0 << 18) | | |
| 2339 ($cmp$$cmpcode << 14) | | |
| 2340 (1 << 13) | // select register move | |
| 2341 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2342 ($primary << 5) | // select single, double or quad | |
| 2343 ($src$$reg << 0); | |
| 2344 *((int*)(cbuf.code_end())) = op; | |
| 2345 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2346 %} | |
| 2347 | |
| 2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2349 int op = (Assembler::arith_op << 30) | | |
| 2350 ($dst$$reg << 25) | | |
| 2351 (Assembler::fpop2_op3 << 19) | | |
| 2352 (0 << 18) | | |
| 2353 ($cmp$$cmpcode << 14) | | |
| 2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2355 ($primary << 5) | // select single, double or quad | |
| 2356 ($src$$reg << 0); | |
| 2357 *((int*)(cbuf.code_end())) = op; | |
| 2358 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2359 %} | |
| 2360 | |
| 2361 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2362 // the condition comes from opcode-field instead of an argument. | |
| 2363 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2364 int op = (Assembler::arith_op << 30) | | |
| 2365 ($dst$$reg << 25) | | |
| 2366 (Assembler::movcc_op3 << 19) | | |
| 2367 (1 << 18) | // cc2 bit for 'icc' | |
| 2368 ($primary << 14) | | |
| 2369 (0 << 13) | // select register move | |
| 2370 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2371 ($src$$reg << 0); | |
| 2372 *((int*)(cbuf.code_end())) = op; | |
| 2373 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2374 %} | |
| 2375 | |
| 2376 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2377 int op = (Assembler::arith_op << 30) | | |
| 2378 ($dst$$reg << 25) | | |
| 2379 (Assembler::movcc_op3 << 19) | | |
| 2380 (6 << 16) | // cc2 bit for 'xcc' | |
| 2381 ($primary << 14) | | |
| 2382 (0 << 13) | // select register move | |
| 2383 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2384 ($src$$reg << 0); | |
| 2385 *((int*)(cbuf.code_end())) = op; | |
| 2386 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2387 %} | |
| 2388 | |
| 2389 // Utility encoding for loading a 64 bit Pointer into a register | |
| 2390 // The 64 bit pointer is stored in the generated code stream | |
| 2391 enc_class SetPtr( immP src, iRegP rd ) %{ | |
| 2392 Register dest = reg_to_register_object($rd$$reg); | |
| 727 | 2393 MacroAssembler _masm(&cbuf); |
| 0 | 2394 // [RGV] This next line should be generated from ADLC |
| 2395 if ( _opnds[1]->constant_is_oop() ) { | |
| 2396 intptr_t val = $src$$constant; | |
| 2397 __ set_oop_constant((jobject)val, dest); | |
| 2398 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 727 | 2399 __ set($src$$constant, dest); |
| 0 | 2400 } |
| 2401 %} | |
| 2402 | |
| 2403 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2404 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2405 %} | |
| 2406 | |
| 2407 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2408 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2409 %} | |
| 2410 | |
| 2411 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2412 MacroAssembler _masm(&cbuf); | |
| 2413 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2414 %} | |
| 2415 | |
| 2416 enc_class SetNull( iRegI rd ) %{ | |
| 2417 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
| 2418 %} | |
| 2419 | |
| 2420 enc_class call_epilog %{ | |
| 2421 if( VerifyStackAtCalls ) { | |
| 2422 MacroAssembler _masm(&cbuf); | |
| 2423 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2424 Register temp_reg = G3; | |
| 2425 __ add(SP, framesize, temp_reg); | |
| 2426 __ cmp(temp_reg, FP); | |
| 2427 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2428 } | |
| 2429 %} | |
| 2430 | |
| 2431 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2432 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2433 // pair. | |
| 2434 enc_class adjust_long_from_native_call %{ | |
| 2435 #ifndef _LP64 | |
| 2436 if (returns_long()) { | |
| 2437 // sllx O0,32,O0 | |
| 2438 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2439 // srl O1,0,O1 | |
| 2440 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2441 // or O0,O1,G1 | |
| 2442 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2443 } | |
| 2444 #endif | |
| 2445 %} | |
| 2446 | |
| 2447 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2448 // CALL directly to the runtime | |
| 2449 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2450 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
| 2451 /*preserve_g2=*/true, /*force far call*/true); | |
| 2452 %} | |
| 2453 | |
| 1567 | 2454 enc_class preserve_SP %{ |
| 2455 MacroAssembler _masm(&cbuf); | |
| 2456 __ mov(SP, L7_mh_SP_save); | |
| 2457 %} | |
| 2458 | |
| 2459 enc_class restore_SP %{ | |
| 2460 MacroAssembler _masm(&cbuf); | |
| 2461 __ mov(L7_mh_SP_save, SP); | |
| 2462 %} | |
| 2463 | |
| 0 | 2464 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2465 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2466 // who we intended to call. | |
| 2467 if ( !_method ) { | |
| 2468 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2469 } else if (_optimized_virtual) { | |
| 2470 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2471 } else { | |
| 2472 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2473 } | |
| 2474 if( _method ) { // Emit stub for static call | |
| 2475 emit_java_to_interp(cbuf); | |
| 2476 } | |
| 2477 %} | |
| 2478 | |
| 2479 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2480 MacroAssembler _masm(&cbuf); | |
| 2481 __ set_inst_mark(); | |
| 2482 int vtable_index = this->_vtable_index; | |
| 2483 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2484 if (vtable_index < 0) { | |
| 2485 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2486 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2487 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2488 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2489 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2490 // !!!!! | |
| 2491 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2492 // emit_call_dynamic_prologue( cbuf ); | |
| 2493 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2494 | |
| 2495 address virtual_call_oop_addr = __ inst_mark(); | |
| 2496 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2497 // who we intended to call. | |
| 2498 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2499 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2500 } else { | |
| 2501 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2502 // Just go thru the vtable | |
| 2503 // get receiver klass (receiver already checked for non-null) | |
| 2504 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2505 int off = __ offset(); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2506 __ load_klass(O0, G3_scratch); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2507 int klass_load_size; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2508 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2509 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2510 if (Universe::narrow_oop_base() == NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2511 klass_load_size = 2*BytesPerInstWord; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2512 else |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2513 klass_load_size = 3*BytesPerInstWord; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2514 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2515 klass_load_size = 1*BytesPerInstWord; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2516 } |
| 0 | 2517 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2518 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2519 if( __ is_simm13(v_off) ) { | |
| 2520 __ ld_ptr(G3, v_off, G5_method); | |
| 2521 } else { | |
| 2522 // Generate 2 instructions | |
| 2523 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2524 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2525 // ld_ptr, set_hi, set | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2526 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2527 "Unexpected instruction size(s)"); |
| 0 | 2528 __ ld_ptr(G3, G5_method, G5_method); |
| 2529 } | |
| 2530 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2531 // However it may very well end up in handle_wrong_method if the | |
| 2532 // method is abstract for the particular class. | |
| 2533 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2534 // jump to target (either compiled code or c2iadapter) | |
| 2535 __ jmpl(G3_scratch, G0, O7); | |
| 2536 __ delayed()->nop(); | |
| 2537 } | |
| 2538 %} | |
| 2539 | |
| 2540 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2541 MacroAssembler _masm(&cbuf); | |
| 2542 | |
| 2543 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2544 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2545 // we might be calling a C2I adapter which needs it. | |
| 2546 | |
| 2547 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2548 // Load nmethod | |
| 2549 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2550 | |
| 2551 // CALL to compiled java, indirect the contents of G3 | |
| 2552 __ set_inst_mark(); | |
| 2553 __ callr(temp_reg, G0); | |
| 2554 __ delayed()->nop(); | |
| 2555 %} | |
| 2556 | |
| 2557 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2558 MacroAssembler _masm(&cbuf); | |
| 2559 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2560 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2561 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2562 | |
| 2563 __ sra(Rdivisor, 0, Rdivisor); | |
| 2564 __ sra(Rdividend, 0, Rdividend); | |
| 2565 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2566 %} | |
| 2567 | |
| 2568 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2569 MacroAssembler _masm(&cbuf); | |
| 2570 | |
| 2571 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2572 int divisor = $imm$$constant; | |
| 2573 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2574 | |
| 2575 __ sra(Rdividend, 0, Rdividend); | |
| 2576 __ sdivx(Rdividend, divisor, Rresult); | |
| 2577 %} | |
| 2578 | |
| 2579 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2580 MacroAssembler _masm(&cbuf); | |
| 2581 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2582 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2583 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2584 | |
| 2585 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2586 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2587 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2588 __ srlx( Rdst, 32, Rdst ); | |
| 2589 %} | |
| 2590 | |
| 2591 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2592 MacroAssembler _masm(&cbuf); | |
| 2593 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2594 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2595 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2596 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2597 | |
| 2598 assert(Rdividend != Rscratch, ""); | |
| 2599 assert(Rdivisor != Rscratch, ""); | |
| 2600 | |
| 2601 __ sra(Rdividend, 0, Rdividend); | |
| 2602 __ sra(Rdivisor, 0, Rdivisor); | |
| 2603 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2604 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2605 __ sub(Rdividend, Rscratch, Rresult); | |
| 2606 %} | |
| 2607 | |
| 2608 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2609 MacroAssembler _masm(&cbuf); | |
| 2610 | |
| 2611 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2612 int divisor = $imm$$constant; | |
| 2613 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2614 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2615 | |
| 2616 assert(Rdividend != Rscratch, ""); | |
| 2617 | |
| 2618 __ sra(Rdividend, 0, Rdividend); | |
| 2619 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2620 __ mulx(Rscratch, divisor, Rscratch); | |
| 2621 __ sub(Rdividend, Rscratch, Rresult); | |
| 2622 %} | |
| 2623 | |
| 2624 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2625 MacroAssembler _masm(&cbuf); | |
| 2626 | |
| 2627 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2628 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2629 | |
| 2630 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2631 %} | |
| 2632 | |
| 2633 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2634 MacroAssembler _masm(&cbuf); | |
| 2635 | |
| 2636 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2637 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2638 | |
| 2639 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2640 %} | |
| 2641 | |
| 2642 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2643 MacroAssembler _masm(&cbuf); | |
| 2644 | |
| 2645 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2646 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2647 | |
| 2648 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2649 %} | |
| 2650 | |
| 2651 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2652 MacroAssembler _masm(&cbuf); | |
| 2653 | |
| 2654 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2655 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2656 | |
| 2657 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2658 %} | |
| 2659 | |
| 2660 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2661 MacroAssembler _masm(&cbuf); | |
| 2662 | |
| 2663 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2664 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2665 | |
| 2666 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2667 %} | |
| 2668 | |
| 2669 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2670 MacroAssembler _masm(&cbuf); | |
| 2671 | |
| 2672 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2673 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2674 | |
| 2675 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2676 %} | |
| 2677 | |
| 2678 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2679 MacroAssembler _masm(&cbuf); | |
| 2680 | |
| 2681 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2682 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2683 | |
| 2684 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2685 %} | |
| 2686 | |
| 2687 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2688 MacroAssembler _masm(&cbuf); | |
| 2689 | |
| 2690 Register Roop = reg_to_register_object($oop$$reg); | |
| 2691 Register Rbox = reg_to_register_object($box$$reg); | |
| 2692 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2693 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2694 | |
| 2695 assert(Roop != Rscratch, ""); | |
| 2696 assert(Roop != Rmark, ""); | |
| 2697 assert(Rbox != Rscratch, ""); | |
| 2698 assert(Rbox != Rmark, ""); | |
| 2699 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2700 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2701 %} |
| 2702 | |
| 2703 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2704 MacroAssembler _masm(&cbuf); | |
| 2705 | |
| 2706 Register Roop = reg_to_register_object($oop$$reg); | |
| 2707 Register Rbox = reg_to_register_object($box$$reg); | |
| 2708 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2709 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2710 | |
| 2711 assert(Roop != Rscratch, ""); | |
| 2712 assert(Roop != Rmark, ""); | |
| 2713 assert(Rbox != Rscratch, ""); | |
| 2714 assert(Rbox != Rmark, ""); | |
| 2715 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2716 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2717 %} |
| 2718 | |
| 2719 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2720 MacroAssembler _masm(&cbuf); | |
| 2721 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2722 Register Rold = reg_to_register_object($old$$reg); | |
| 2723 Register Rnew = reg_to_register_object($new$$reg); | |
| 2724 | |
| 2725 // casx_under_lock picks 1 of 3 encodings: | |
| 2726 // For 32-bit pointers you get a 32-bit CAS | |
| 2727 // For 64-bit pointers you get a 64-bit CASX | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2728 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2729 __ cmp( Rold, Rnew ); |
| 2730 %} | |
| 2731 | |
| 2732 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2733 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2734 Register Rold = reg_to_register_object($old$$reg); | |
| 2735 Register Rnew = reg_to_register_object($new$$reg); | |
| 2736 | |
| 2737 MacroAssembler _masm(&cbuf); | |
| 2738 __ mov(Rnew, O7); | |
| 2739 __ casx(Rmem, Rold, O7); | |
| 2740 __ cmp( Rold, O7 ); | |
| 2741 %} | |
| 2742 | |
| 2743 // raw int cas, used for compareAndSwap | |
| 2744 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2745 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2746 Register Rold = reg_to_register_object($old$$reg); | |
| 2747 Register Rnew = reg_to_register_object($new$$reg); | |
| 2748 | |
| 2749 MacroAssembler _masm(&cbuf); | |
| 2750 __ mov(Rnew, O7); | |
| 2751 __ cas(Rmem, Rold, O7); | |
| 2752 __ cmp( Rold, O7 ); | |
| 2753 %} | |
| 2754 | |
| 2755 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2756 Register Rres = reg_to_register_object($res$$reg); | |
| 2757 | |
| 2758 MacroAssembler _masm(&cbuf); | |
| 2759 __ mov(1, Rres); | |
| 2760 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2761 %} | |
| 2762 | |
| 2763 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2764 Register Rres = reg_to_register_object($res$$reg); | |
| 2765 | |
| 2766 MacroAssembler _masm(&cbuf); | |
| 2767 __ mov(1, Rres); | |
| 2768 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2769 %} | |
| 2770 | |
| 2771 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2772 MacroAssembler _masm(&cbuf); | |
| 2773 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2774 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2775 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2776 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2777 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2778 | |
| 2779 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2780 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2781 %} | |
| 2782 | |
| 2783 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
| 2784 MacroAssembler _masm(&cbuf); | |
| 2785 Register dest = reg_to_register_object($dst$$reg); | |
| 2786 Register temp = reg_to_register_object($tmp$$reg); | |
| 2787 __ set64( $src$$constant, dest, temp ); | |
| 2788 %} | |
| 2789 | |
| 2790 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
| 2791 // Load a constant replicated "count" times with width "width" | |
| 2792 int bit_width = $width$$constant * 8; | |
| 2793 jlong elt_val = $src$$constant; | |
| 2794 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
| 2795 jlong val = elt_val; | |
| 2796 for (int i = 0; i < $count$$constant - 1; i++) { | |
| 2797 val <<= bit_width; | |
| 2798 val |= elt_val; | |
| 2799 } | |
| 2800 jdouble dval = *(jdouble*)&val; // coerce to double type | |
| 727 | 2801 MacroAssembler _masm(&cbuf); |
| 2802 address double_address = __ double_constant(dval); | |
| 0 | 2803 RelocationHolder rspec = internal_word_Relocation::spec(double_address); |
| 727 | 2804 AddressLiteral addrlit(double_address, rspec); |
| 2805 | |
| 2806 __ sethi(addrlit, $tmp$$Register); | |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
2807 // XXX This is a quick fix for 6833573. |
|
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
2808 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
|
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
2809 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
| 0 | 2810 %} |
| 2811 | |
| 2812 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2813 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2814 MacroAssembler _masm(&cbuf); | |
| 2815 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2816 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2817 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 2818 | |
| 2819 Label loop; | |
| 2820 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 2821 | |
| 2822 // Loop and clear, walking backwards through the array. | |
| 2823 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2824 __ bind(loop); | |
| 2825 __ deccc(nof_bytes_tmp, 8); | |
| 2826 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2827 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2828 // %%%% this mini-loop must not cross a cache boundary! | |
| 2829 %} | |
| 2830 | |
| 2831 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2832 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2833 Label Ldone, Lloop; |
| 2834 MacroAssembler _masm(&cbuf); | |
| 2835 | |
| 2836 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2837 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2838 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2839 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2840 Register result_reg = reg_to_register_object($result$$reg); |
| 2841 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2842 assert(result_reg != str1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2843 result_reg != str2_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2844 result_reg != cnt1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2845 result_reg != cnt2_reg , |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2846 "need different registers"); |
| 0 | 2847 |
| 2848 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2849 // difference of the string lengths (stack) | |
| 2850 | |
| 2851 // See if the lengths are different, and calculate min in str1_reg. | |
| 2852 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2853 Label Lskip; | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2854 __ subcc(cnt1_reg, cnt2_reg, O7); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2855 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2856 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2857 // cnt2 is shorter, so use its count: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2858 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2859 __ bind(Lskip); |
| 2860 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2861 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2862 // Note: limit_reg holds the string length pre-scaled by 2 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2863 Register limit_reg = cnt1_reg; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2864 Register chr2_reg = cnt2_reg; |
| 0 | 2865 Register chr1_reg = result_reg; |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2866 // str{12} are the base pointers |
| 0 | 2867 |
| 2868 // Is the minimum length zero? | |
| 2869 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2870 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2871 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2872 | |
| 2873 // Load first characters | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2874 __ lduh(str1_reg, 0, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2875 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2876 |
| 2877 // Compare first characters | |
| 2878 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2879 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2880 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2881 __ delayed()->nop(); | |
| 2882 | |
| 2883 { | |
| 2884 // Check after comparing first character to see if strings are equivalent | |
| 2885 Label LSkip2; | |
| 2886 // Check if the strings start at same location | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2887 __ cmp(str1_reg, str2_reg); |
| 0 | 2888 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2889 __ delayed()->nop(); | |
| 2890 | |
| 2891 // Check if the length difference is zero (in O7) | |
| 2892 __ cmp(G0, O7); | |
| 2893 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2894 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2895 | |
| 2896 // Strings might not be equal | |
| 2897 __ bind(LSkip2); | |
| 2898 } | |
| 2899 | |
| 2900 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2901 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2902 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2903 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2904 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2905 __ add(str1_reg, limit_reg, str1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2906 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2907 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2908 | |
| 2909 // Compare the rest of the characters | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2910 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2911 __ bind(Lloop); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2912 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2913 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2914 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2915 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2916 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2917 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2918 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2919 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2920 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2921 |
| 2922 // If strings are equal up to min length, return the length difference. | |
| 2923 __ mov(O7, result_reg); | |
| 2924 | |
| 2925 // Otherwise, return the difference between the first mismatched chars. | |
| 2926 __ bind(Ldone); | |
| 2927 %} | |
| 2928 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2929 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2930 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2931 MacroAssembler _masm(&cbuf); |
| 2932 | |
| 2933 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2934 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2935 Register cnt_reg = reg_to_register_object($cnt$$reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2936 Register tmp1_reg = O7; |
| 681 | 2937 Register result_reg = reg_to_register_object($result$$reg); |
| 2938 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2939 assert(result_reg != str1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2940 result_reg != str2_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2941 result_reg != cnt_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2942 result_reg != tmp1_reg , |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2943 "need different registers"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2944 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2945 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2946 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2947 __ delayed()->add(G0, 1, result_reg); | |
| 2948 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2949 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2950 __ delayed()->add(G0, 1, result_reg); // count == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2951 |
| 681 | 2952 //rename registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2953 Register limit_reg = cnt_reg; |
| 681 | 2954 Register chr1_reg = result_reg; |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2955 Register chr2_reg = tmp1_reg; |
| 681 | 2956 |
| 2957 //check for alignment and position the pointers to the ends | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2958 __ or3(str1_reg, str2_reg, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2959 __ andcc(chr1_reg, 0x3, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2960 // notZero means at least one not 4-byte aligned. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2961 // We could optimize the case when both arrays are not aligned |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2962 // but it is not frequent case and it requires additional checks. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2963 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2964 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2965 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2966 // Compare char[] arrays aligned to 4 bytes. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2967 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2968 chr1_reg, chr2_reg, Ldone); |
| 681 | 2969 __ ba(false,Ldone); |
| 2970 __ delayed()->add(G0, 1, result_reg); | |
| 2971 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2972 // char by char compare |
| 681 | 2973 __ bind(Lchar); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2974 __ add(str1_reg, limit_reg, str1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2975 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 2976 __ neg(limit_reg); //negate count |
| 2977 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2978 __ lduh(str1_reg, limit_reg, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2979 // Lchar_loop |
| 681 | 2980 __ bind(Lchar_loop); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2981 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 2982 __ cmp(chr1_reg, chr2_reg); |
| 2983 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 2984 __ delayed()->mov(G0, result_reg); //not equal | |
| 2985 __ inccc(limit_reg, sizeof(jchar)); | |
| 2986 // annul LDUH if branch is not taken to prevent access past end of string | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2987 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2988 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 2989 |
| 2990 __ add(G0, 1, result_reg); //equal | |
| 2991 | |
| 2992 __ bind(Ldone); | |
| 2993 %} | |
| 2994 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2995 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 2996 Label Lvector, Ldone, Lloop; |
| 2997 MacroAssembler _masm(&cbuf); | |
| 2998 | |
| 2999 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3000 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3001 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3002 Register tmp2_reg = O7; |
| 681 | 3003 Register result_reg = reg_to_register_object($result$$reg); |
| 3004 | |
| 3005 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3006 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3007 | |
| 3008 // return true if the same array | |
| 3009 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3010 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3011 __ delayed()->add(G0, 1, result_reg); // equal |
| 3012 | |
| 3013 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3014 __ delayed()->mov(G0, result_reg); // not equal | |
| 3015 | |
| 3016 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3017 __ delayed()->mov(G0, result_reg); // not equal | |
| 3018 | |
| 3019 //load the lengths of arrays | |
| 727 | 3020 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3021 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3022 |
| 3023 // return false if the two arrays are not equal length | |
| 3024 __ cmp(tmp1_reg, tmp2_reg); | |
| 3025 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3026 __ delayed()->mov(G0, result_reg); // not equal | |
| 3027 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3028 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
| 681 | 3029 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3030 | |
| 3031 // load array addresses | |
| 3032 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3033 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3034 | |
| 3035 // renaming registers | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3036 Register chr1_reg = result_reg; // for characters in ary1 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3037 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3038 Register limit_reg = tmp1_reg; // length |
| 3039 | |
| 3040 // set byte count | |
| 3041 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3042 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3043 // Compare char[] arrays aligned to 4 bytes. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3044 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3045 chr1_reg, chr2_reg, Ldone); |
| 681 | 3046 __ add(G0, 1, result_reg); // equals |
| 3047 | |
| 3048 __ bind(Ldone); | |
| 3049 %} | |
| 3050 | |
| 0 | 3051 enc_class enc_rethrow() %{ |
| 3052 cbuf.set_inst_mark(); | |
| 3053 Register temp_reg = G3; | |
| 727 | 3054 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3055 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3056 MacroAssembler _masm(&cbuf); | |
| 3057 #ifdef ASSERT | |
| 3058 __ save_frame(0); | |
| 727 | 3059 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3060 __ sethi(last_rethrow_addrlit, L1); | |
| 3061 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3062 __ get_pc(L2); |
| 3063 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3064 __ st_ptr(L2, addr); |
| 0 | 3065 __ restore(); |
| 3066 #endif | |
| 727 | 3067 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3068 __ delayed()->nop(); |
| 3069 %} | |
| 3070 | |
| 3071 enc_class emit_mem_nop() %{ | |
| 3072 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 3073 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3074 *code = (unsigned int)0xc0839040; | |
| 3075 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3076 %} | |
| 3077 | |
| 3078 enc_class emit_fadd_nop() %{ | |
| 3079 // Generates the instruction FMOVS f31,f31 | |
| 3080 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3081 *code = (unsigned int)0xbfa0003f; | |
| 3082 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3083 %} | |
| 3084 | |
| 3085 enc_class emit_br_nop() %{ | |
| 3086 // Generates the instruction BPN,PN . | |
| 3087 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3088 *code = (unsigned int)0x00400000; | |
| 3089 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3090 %} | |
| 3091 | |
| 3092 enc_class enc_membar_acquire %{ | |
| 3093 MacroAssembler _masm(&cbuf); | |
| 3094 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3095 %} | |
| 3096 | |
| 3097 enc_class enc_membar_release %{ | |
| 3098 MacroAssembler _masm(&cbuf); | |
| 3099 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3100 %} | |
| 3101 | |
| 3102 enc_class enc_membar_volatile %{ | |
| 3103 MacroAssembler _masm(&cbuf); | |
| 3104 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3105 %} | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3106 |
| 0 | 3107 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3108 MacroAssembler _masm(&cbuf); | |
| 3109 Register src_reg = reg_to_register_object($src$$reg); | |
| 3110 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3111 __ sllx(src_reg, 56, dst_reg); | |
| 3112 __ srlx(dst_reg, 8, O7); | |
| 3113 __ or3 (dst_reg, O7, dst_reg); | |
| 3114 __ srlx(dst_reg, 16, O7); | |
| 3115 __ or3 (dst_reg, O7, dst_reg); | |
| 3116 __ srlx(dst_reg, 32, O7); | |
| 3117 __ or3 (dst_reg, O7, dst_reg); | |
| 3118 %} | |
| 3119 | |
| 3120 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3121 MacroAssembler _masm(&cbuf); | |
| 3122 Register src_reg = reg_to_register_object($src$$reg); | |
| 3123 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3124 __ sll(src_reg, 24, dst_reg); | |
| 3125 __ srl(dst_reg, 8, O7); | |
| 3126 __ or3(dst_reg, O7, dst_reg); | |
| 3127 __ srl(dst_reg, 16, O7); | |
| 3128 __ or3(dst_reg, O7, dst_reg); | |
| 3129 %} | |
| 3130 | |
| 3131 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3132 MacroAssembler _masm(&cbuf); | |
| 3133 Register src_reg = reg_to_register_object($src$$reg); | |
| 3134 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3135 __ sllx(src_reg, 48, dst_reg); | |
| 3136 __ srlx(dst_reg, 16, O7); | |
| 3137 __ or3 (dst_reg, O7, dst_reg); | |
| 3138 __ srlx(dst_reg, 32, O7); | |
| 3139 __ or3 (dst_reg, O7, dst_reg); | |
| 3140 %} | |
| 3141 | |
| 3142 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3143 MacroAssembler _masm(&cbuf); | |
| 3144 Register src_reg = reg_to_register_object($src$$reg); | |
| 3145 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3146 __ sllx(src_reg, 32, dst_reg); | |
| 3147 __ srlx(dst_reg, 32, O7); | |
| 3148 __ or3 (dst_reg, O7, dst_reg); | |
| 3149 %} | |
| 3150 | |
| 3151 %} | |
| 3152 | |
| 3153 //----------FRAME-------------------------------------------------------------- | |
| 3154 // Definition of frame structure and management information. | |
| 3155 // | |
| 3156 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3157 // | (to get allocators register number | |
| 3158 // G Owned by | | v add VMRegImpl::stack0) | |
| 3159 // r CALLER | | | |
| 3160 // o | +--------+ pad to even-align allocators stack-slot | |
| 3161 // w V | pad0 | numbers; owned by CALLER | |
| 3162 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3163 // h ^ | in | 5 | |
| 3164 // | | args | 4 Holes in incoming args owned by SELF | |
| 3165 // | | | | 3 | |
| 3166 // | | +--------+ | |
| 3167 // V | | old out| Empty on Intel, window on Sparc | |
| 3168 // | old |preserve| Must be even aligned. | |
| 3169 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3170 // | | in | 3 area for Intel ret address | |
| 3171 // Owned by |preserve| Empty on Sparc. | |
| 3172 // SELF +--------+ | |
| 3173 // | | pad2 | 2 pad to align old SP | |
| 3174 // | +--------+ 1 | |
| 3175 // | | locks | 0 | |
| 3176 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3177 // | | pad1 | 11 pad to align new SP | |
| 3178 // | +--------+ | |
| 3179 // | | | 10 | |
| 3180 // | | spills | 9 spills | |
| 3181 // V | | 8 (pad0 slot for callee) | |
| 3182 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3183 // ^ | out | 7 | |
| 3184 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3185 // Owned by +--------+ | |
| 3186 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3187 // | new |preserve| Must be even-aligned. | |
| 3188 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3189 // | | | | |
| 3190 // | |
| 3191 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3192 // known from SELF's arguments and the Java calling convention. | |
| 3193 // Region 6-7 is determined per call site. | |
| 3194 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3195 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3196 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3197 // incoming area, as the Java calling convention is completely under | |
| 3198 // the control of the AD file. Doubles can be sorted and packed to | |
| 3199 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3200 // varargs C calling conventions. | |
| 3201 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3202 // even aligned with pad0 as needed. | |
| 3203 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3204 // region 6-11 is even aligned; it may be padded out more so that | |
| 3205 // the region from SP to FP meets the minimum stack alignment. | |
| 3206 | |
| 3207 frame %{ | |
| 3208 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3209 stack_direction(TOWARDS_LOW); | |
| 3210 | |
| 3211 // These two registers define part of the calling convention | |
| 3212 // between compiled code and the interpreter. | |
| 3213 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3214 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3215 | |
| 3216 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3217 cisc_spilling_operand_name(indOffset); | |
| 3218 | |
| 3219 // Number of stack slots consumed by a Monitor enter | |
| 3220 #ifdef _LP64 | |
| 3221 sync_stack_slots(2); | |
| 3222 #else | |
| 3223 sync_stack_slots(1); | |
| 3224 #endif | |
| 3225 | |
| 3226 // Compiled code's Frame Pointer | |
| 3227 frame_pointer(R_SP); | |
| 3228 | |
| 3229 // Stack alignment requirement | |
| 3230 stack_alignment(StackAlignmentInBytes); | |
| 3231 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3232 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3233 | |
| 3234 // Number of stack slots between incoming argument block and the start of | |
| 3235 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3236 // EPILOG must remove this many slots. | |
| 3237 in_preserve_stack_slots(0); | |
| 3238 | |
| 3239 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3240 // for calls to C. Supports the var-args backing area for register parms. | |
| 3241 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3242 #ifdef _LP64 | |
| 3243 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3244 varargs_C_out_slots_killed(12); | |
| 3245 #else | |
| 3246 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3247 varargs_C_out_slots_killed( 7); | |
| 3248 #endif | |
| 3249 | |
| 3250 // The after-PROLOG location of the return address. Location of | |
| 3251 // return address specifies a type (REG or STACK) and a number | |
| 3252 // representing the register number (i.e. - use a register name) or | |
| 3253 // stack slot. | |
| 3254 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3255 | |
| 3256 // Body of function which returns an OptoRegs array locating | |
| 3257 // arguments either in registers or in stack slots for calling | |
| 3258 // java | |
| 3259 calling_convention %{ | |
| 3260 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3261 | |
| 3262 %} | |
| 3263 | |
| 3264 // Body of function which returns an OptoRegs array locating | |
| 3265 // arguments either in registers or in stack slots for callin | |
| 3266 // C. | |
| 3267 c_calling_convention %{ | |
| 3268 // This is obviously always outgoing | |
| 3269 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3270 %} | |
| 3271 | |
| 3272 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3273 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3274 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3275 // to and from the register pairs is done by the appropriate call and epilog | |
| 3276 // opcodes. This simplifies the register allocator. | |
| 3277 c_return_value %{ | |
| 3278 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3279 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3280 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3281 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3282 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3283 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3284 #else // !_LP64 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3285 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3286 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3287 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3288 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3289 #endif |
| 3290 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3291 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3292 %} | |
| 3293 | |
| 3294 // Location of compiled Java return values. Same as C | |
| 3295 return_value %{ | |
| 3296 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3297 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3298 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3299 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3300 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3301 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3302 #else // !_LP64 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3303 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3304 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3305 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3306 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3307 #endif |
| 3308 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3309 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3310 %} | |
| 3311 | |
| 3312 %} | |
| 3313 | |
| 3314 | |
| 3315 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3316 //----------Operand Attributes------------------------------------------------- | |
| 3317 op_attrib op_cost(1); // Required cost attribute | |
| 3318 | |
| 3319 //----------Instruction Attributes--------------------------------------------- | |
| 3320 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3321 ins_attrib ins_size(32); // Required size attribute (in bits) | |
| 3322 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 3323 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3324 // non-matching short branch variant of some | |
| 3325 // long branch? | |
| 3326 | |
| 3327 //----------OPERANDS----------------------------------------------------------- | |
| 3328 // Operand definitions must precede instruction definitions for correct parsing | |
| 3329 // in the ADLC because operands constitute user defined types which are used in | |
| 3330 // instruction definitions. | |
| 3331 | |
| 3332 //----------Simple Operands---------------------------------------------------- | |
| 3333 // Immediate Operands | |
| 3334 // Integer Immediate: 32-bit | |
| 3335 operand immI() %{ | |
| 3336 match(ConI); | |
| 3337 | |
| 3338 op_cost(0); | |
| 3339 // formats are generated automatically for constants and base registers | |
| 3340 format %{ %} | |
| 3341 interface(CONST_INTER); | |
| 3342 %} | |
| 3343 | |
| 824 | 3344 // Integer Immediate: 8-bit |
| 3345 operand immI8() %{ | |
| 3346 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 3347 match(ConI); | |
| 3348 op_cost(0); | |
| 3349 format %{ %} | |
| 3350 interface(CONST_INTER); | |
| 3351 %} | |
| 3352 | |
| 0 | 3353 // Integer Immediate: 13-bit |
| 3354 operand immI13() %{ | |
| 3355 predicate(Assembler::is_simm13(n->get_int())); | |
| 3356 match(ConI); | |
| 3357 op_cost(0); | |
| 3358 | |
| 3359 format %{ %} | |
| 3360 interface(CONST_INTER); | |
| 3361 %} | |
| 3362 | |
| 785 | 3363 // Integer Immediate: 13-bit minus 7 |
| 3364 operand immI13m7() %{ | |
| 3365 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3366 match(ConI); | |
| 3367 op_cost(0); | |
| 3368 | |
| 3369 format %{ %} | |
| 3370 interface(CONST_INTER); | |
| 3371 %} | |
| 3372 | |
| 824 | 3373 // Integer Immediate: 16-bit |
| 3374 operand immI16() %{ | |
| 3375 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 3376 match(ConI); | |
| 3377 op_cost(0); | |
| 3378 format %{ %} | |
| 3379 interface(CONST_INTER); | |
| 3380 %} | |
| 3381 | |
| 0 | 3382 // Unsigned (positive) Integer Immediate: 13-bit |
| 3383 operand immU13() %{ | |
| 3384 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3385 match(ConI); | |
| 3386 op_cost(0); | |
| 3387 | |
| 3388 format %{ %} | |
| 3389 interface(CONST_INTER); | |
| 3390 %} | |
| 3391 | |
| 3392 // Integer Immediate: 6-bit | |
| 3393 operand immU6() %{ | |
| 3394 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3395 match(ConI); | |
| 3396 op_cost(0); | |
| 3397 format %{ %} | |
| 3398 interface(CONST_INTER); | |
| 3399 %} | |
| 3400 | |
| 3401 // Integer Immediate: 11-bit | |
| 3402 operand immI11() %{ | |
| 3403 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3404 match(ConI); | |
| 3405 op_cost(0); | |
| 3406 format %{ %} | |
| 3407 interface(CONST_INTER); | |
| 3408 %} | |
| 3409 | |
| 3410 // Integer Immediate: 0-bit | |
| 3411 operand immI0() %{ | |
| 3412 predicate(n->get_int() == 0); | |
| 3413 match(ConI); | |
| 3414 op_cost(0); | |
| 3415 | |
| 3416 format %{ %} | |
| 3417 interface(CONST_INTER); | |
| 3418 %} | |
| 3419 | |
| 3420 // Integer Immediate: the value 10 | |
| 3421 operand immI10() %{ | |
| 3422 predicate(n->get_int() == 10); | |
| 3423 match(ConI); | |
| 3424 op_cost(0); | |
| 3425 | |
| 3426 format %{ %} | |
| 3427 interface(CONST_INTER); | |
| 3428 %} | |
| 3429 | |
| 3430 // Integer Immediate: the values 0-31 | |
| 3431 operand immU5() %{ | |
| 3432 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3433 match(ConI); | |
| 3434 op_cost(0); | |
| 3435 | |
| 3436 format %{ %} | |
| 3437 interface(CONST_INTER); | |
| 3438 %} | |
| 3439 | |
| 3440 // Integer Immediate: the values 1-31 | |
| 3441 operand immI_1_31() %{ | |
| 3442 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3443 match(ConI); | |
| 3444 op_cost(0); | |
| 3445 | |
| 3446 format %{ %} | |
| 3447 interface(CONST_INTER); | |
| 3448 %} | |
| 3449 | |
| 3450 // Integer Immediate: the values 32-63 | |
| 3451 operand immI_32_63() %{ | |
| 3452 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3453 match(ConI); | |
| 3454 op_cost(0); | |
| 3455 | |
| 3456 format %{ %} | |
| 3457 interface(CONST_INTER); | |
| 3458 %} | |
| 3459 | |
| 785 | 3460 // Immediates for special shifts (sign extend) |
| 3461 | |
| 3462 // Integer Immediate: the value 16 | |
| 3463 operand immI_16() %{ | |
| 3464 predicate(n->get_int() == 16); | |
| 3465 match(ConI); | |
| 3466 op_cost(0); | |
| 3467 | |
| 3468 format %{ %} | |
| 3469 interface(CONST_INTER); | |
| 3470 %} | |
| 3471 | |
| 3472 // Integer Immediate: the value 24 | |
| 3473 operand immI_24() %{ | |
| 3474 predicate(n->get_int() == 24); | |
| 3475 match(ConI); | |
| 3476 op_cost(0); | |
| 3477 | |
| 3478 format %{ %} | |
| 3479 interface(CONST_INTER); | |
| 3480 %} | |
| 3481 | |
| 0 | 3482 // Integer Immediate: the value 255 |
| 3483 operand immI_255() %{ | |
| 3484 predicate( n->get_int() == 255 ); | |
| 3485 match(ConI); | |
| 3486 op_cost(0); | |
| 3487 | |
| 3488 format %{ %} | |
| 3489 interface(CONST_INTER); | |
| 3490 %} | |
| 3491 | |
| 785 | 3492 // Integer Immediate: the value 65535 |
| 3493 operand immI_65535() %{ | |
| 3494 predicate(n->get_int() == 65535); | |
| 3495 match(ConI); | |
| 3496 op_cost(0); | |
| 3497 | |
| 3498 format %{ %} | |
| 3499 interface(CONST_INTER); | |
| 3500 %} | |
| 3501 | |
| 0 | 3502 // Long Immediate: the value FF |
| 3503 operand immL_FF() %{ | |
| 3504 predicate( n->get_long() == 0xFFL ); | |
| 3505 match(ConL); | |
| 3506 op_cost(0); | |
| 3507 | |
| 3508 format %{ %} | |
| 3509 interface(CONST_INTER); | |
| 3510 %} | |
| 3511 | |
| 3512 // Long Immediate: the value FFFF | |
| 3513 operand immL_FFFF() %{ | |
| 3514 predicate( n->get_long() == 0xFFFFL ); | |
| 3515 match(ConL); | |
| 3516 op_cost(0); | |
| 3517 | |
| 3518 format %{ %} | |
| 3519 interface(CONST_INTER); | |
| 3520 %} | |
| 3521 | |
| 3522 // Pointer Immediate: 32 or 64-bit | |
| 3523 operand immP() %{ | |
| 3524 match(ConP); | |
| 3525 | |
| 3526 op_cost(5); | |
| 3527 // formats are generated automatically for constants and base registers | |
| 3528 format %{ %} | |
| 3529 interface(CONST_INTER); | |
| 3530 %} | |
| 3531 | |
| 3532 operand immP13() %{ | |
| 3533 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3534 match(ConP); | |
| 3535 op_cost(0); | |
| 3536 | |
| 3537 format %{ %} | |
| 3538 interface(CONST_INTER); | |
| 3539 %} | |
| 3540 | |
| 3541 operand immP0() %{ | |
| 3542 predicate(n->get_ptr() == 0); | |
| 3543 match(ConP); | |
| 3544 op_cost(0); | |
| 3545 | |
| 3546 format %{ %} | |
| 3547 interface(CONST_INTER); | |
| 3548 %} | |
| 3549 | |
| 3550 operand immP_poll() %{ | |
| 3551 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3552 match(ConP); | |
| 3553 | |
| 3554 // formats are generated automatically for constants and base registers | |
| 3555 format %{ %} | |
| 3556 interface(CONST_INTER); | |
| 3557 %} | |
| 3558 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3559 // Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3560 operand immN() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3561 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3562 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3563 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3564 op_cost(10); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3565 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3566 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3567 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3568 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3569 // NULL Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3570 operand immN0() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3571 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3572 predicate(n->get_narrowcon() == 0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3573 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3574 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3575 op_cost(0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3576 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3577 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3578 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3579 |
| 0 | 3580 operand immL() %{ |
| 3581 match(ConL); | |
| 3582 op_cost(40); | |
| 3583 // formats are generated automatically for constants and base registers | |
| 3584 format %{ %} | |
| 3585 interface(CONST_INTER); | |
| 3586 %} | |
| 3587 | |
| 3588 operand immL0() %{ | |
| 3589 predicate(n->get_long() == 0L); | |
| 3590 match(ConL); | |
| 3591 op_cost(0); | |
| 3592 // formats are generated automatically for constants and base registers | |
| 3593 format %{ %} | |
| 3594 interface(CONST_INTER); | |
| 3595 %} | |
| 3596 | |
| 3597 // Long Immediate: 13-bit | |
| 3598 operand immL13() %{ | |
| 3599 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3600 match(ConL); | |
| 3601 op_cost(0); | |
| 3602 | |
| 3603 format %{ %} | |
| 3604 interface(CONST_INTER); | |
| 3605 %} | |
| 3606 | |
| 785 | 3607 // Long Immediate: 13-bit minus 7 |
| 3608 operand immL13m7() %{ | |
| 3609 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3610 match(ConL); | |
| 3611 op_cost(0); | |
| 3612 | |
| 3613 format %{ %} | |
| 3614 interface(CONST_INTER); | |
| 3615 %} | |
| 3616 | |
| 0 | 3617 // Long Immediate: low 32-bit mask |
| 3618 operand immL_32bits() %{ | |
| 3619 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3620 match(ConL); | |
| 3621 op_cost(0); | |
| 3622 | |
| 3623 format %{ %} | |
| 3624 interface(CONST_INTER); | |
| 3625 %} | |
| 3626 | |
| 3627 // Double Immediate | |
| 3628 operand immD() %{ | |
| 3629 match(ConD); | |
| 3630 | |
| 3631 op_cost(40); | |
| 3632 format %{ %} | |
| 3633 interface(CONST_INTER); | |
| 3634 %} | |
| 3635 | |
| 3636 operand immD0() %{ | |
| 3637 #ifdef _LP64 | |
| 3638 // on 64-bit architectures this comparision is faster | |
| 3639 predicate(jlong_cast(n->getd()) == 0); | |
| 3640 #else | |
| 3641 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3642 #endif | |
| 3643 match(ConD); | |
| 3644 | |
| 3645 op_cost(0); | |
| 3646 format %{ %} | |
| 3647 interface(CONST_INTER); | |
| 3648 %} | |
| 3649 | |
| 3650 // Float Immediate | |
| 3651 operand immF() %{ | |
| 3652 match(ConF); | |
| 3653 | |
| 3654 op_cost(20); | |
| 3655 format %{ %} | |
| 3656 interface(CONST_INTER); | |
| 3657 %} | |
| 3658 | |
| 3659 // Float Immediate: 0 | |
| 3660 operand immF0() %{ | |
| 3661 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3662 match(ConF); | |
| 3663 | |
| 3664 op_cost(0); | |
| 3665 format %{ %} | |
| 3666 interface(CONST_INTER); | |
| 3667 %} | |
| 3668 | |
| 3669 // Integer Register Operands | |
| 3670 // Integer Register | |
| 3671 operand iRegI() %{ | |
| 3672 constraint(ALLOC_IN_RC(int_reg)); | |
| 3673 match(RegI); | |
| 3674 | |
| 3675 match(notemp_iRegI); | |
| 3676 match(g1RegI); | |
| 3677 match(o0RegI); | |
| 3678 match(iRegIsafe); | |
| 3679 | |
| 3680 format %{ %} | |
| 3681 interface(REG_INTER); | |
| 3682 %} | |
| 3683 | |
| 3684 operand notemp_iRegI() %{ | |
| 3685 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3686 match(RegI); | |
| 3687 | |
| 3688 match(o0RegI); | |
| 3689 | |
| 3690 format %{ %} | |
| 3691 interface(REG_INTER); | |
| 3692 %} | |
| 3693 | |
| 3694 operand o0RegI() %{ | |
| 3695 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3696 match(iRegI); | |
| 3697 | |
| 3698 format %{ %} | |
| 3699 interface(REG_INTER); | |
| 3700 %} | |
| 3701 | |
| 3702 // Pointer Register | |
| 3703 operand iRegP() %{ | |
| 3704 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3705 match(RegP); | |
| 3706 | |
| 3707 match(lock_ptr_RegP); | |
| 3708 match(g1RegP); | |
| 3709 match(g2RegP); | |
| 3710 match(g3RegP); | |
| 3711 match(g4RegP); | |
| 3712 match(i0RegP); | |
| 3713 match(o0RegP); | |
| 3714 match(o1RegP); | |
| 3715 match(l7RegP); | |
| 3716 | |
| 3717 format %{ %} | |
| 3718 interface(REG_INTER); | |
| 3719 %} | |
| 3720 | |
| 3721 operand sp_ptr_RegP() %{ | |
| 3722 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3723 match(RegP); | |
| 3724 match(iRegP); | |
| 3725 | |
| 3726 format %{ %} | |
| 3727 interface(REG_INTER); | |
| 3728 %} | |
| 3729 | |
| 3730 operand lock_ptr_RegP() %{ | |
| 3731 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3732 match(RegP); | |
| 3733 match(i0RegP); | |
| 3734 match(o0RegP); | |
| 3735 match(o1RegP); | |
| 3736 match(l7RegP); | |
| 3737 | |
| 3738 format %{ %} | |
| 3739 interface(REG_INTER); | |
| 3740 %} | |
| 3741 | |
| 3742 operand g1RegP() %{ | |
| 3743 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3744 match(iRegP); | |
| 3745 | |
| 3746 format %{ %} | |
| 3747 interface(REG_INTER); | |
| 3748 %} | |
| 3749 | |
| 3750 operand g2RegP() %{ | |
| 3751 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3752 match(iRegP); | |
| 3753 | |
| 3754 format %{ %} | |
| 3755 interface(REG_INTER); | |
| 3756 %} | |
| 3757 | |
| 3758 operand g3RegP() %{ | |
| 3759 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3760 match(iRegP); | |
| 3761 | |
| 3762 format %{ %} | |
| 3763 interface(REG_INTER); | |
| 3764 %} | |
| 3765 | |
| 3766 operand g1RegI() %{ | |
| 3767 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3768 match(iRegI); | |
| 3769 | |
| 3770 format %{ %} | |
| 3771 interface(REG_INTER); | |
| 3772 %} | |
| 3773 | |
| 3774 operand g3RegI() %{ | |
| 3775 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3776 match(iRegI); | |
| 3777 | |
| 3778 format %{ %} | |
| 3779 interface(REG_INTER); | |
| 3780 %} | |
| 3781 | |
| 3782 operand g4RegI() %{ | |
| 3783 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3784 match(iRegI); | |
| 3785 | |
| 3786 format %{ %} | |
| 3787 interface(REG_INTER); | |
| 3788 %} | |
| 3789 | |
| 3790 operand g4RegP() %{ | |
| 3791 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3792 match(iRegP); | |
| 3793 | |
| 3794 format %{ %} | |
| 3795 interface(REG_INTER); | |
| 3796 %} | |
| 3797 | |
| 3798 operand i0RegP() %{ | |
| 3799 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3800 match(iRegP); | |
| 3801 | |
| 3802 format %{ %} | |
| 3803 interface(REG_INTER); | |
| 3804 %} | |
| 3805 | |
| 3806 operand o0RegP() %{ | |
| 3807 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3808 match(iRegP); | |
| 3809 | |
| 3810 format %{ %} | |
| 3811 interface(REG_INTER); | |
| 3812 %} | |
| 3813 | |
| 3814 operand o1RegP() %{ | |
| 3815 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3816 match(iRegP); | |
| 3817 | |
| 3818 format %{ %} | |
| 3819 interface(REG_INTER); | |
| 3820 %} | |
| 3821 | |
| 3822 operand o2RegP() %{ | |
| 3823 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3824 match(iRegP); | |
| 3825 | |
| 3826 format %{ %} | |
| 3827 interface(REG_INTER); | |
| 3828 %} | |
| 3829 | |
| 3830 operand o7RegP() %{ | |
| 3831 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3832 match(iRegP); | |
| 3833 | |
| 3834 format %{ %} | |
| 3835 interface(REG_INTER); | |
| 3836 %} | |
| 3837 | |
| 3838 operand l7RegP() %{ | |
| 3839 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3840 match(iRegP); | |
| 3841 | |
| 3842 format %{ %} | |
| 3843 interface(REG_INTER); | |
| 3844 %} | |
| 3845 | |
| 3846 operand o7RegI() %{ | |
| 3847 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3848 match(iRegI); | |
| 3849 | |
| 3850 format %{ %} | |
| 3851 interface(REG_INTER); | |
| 3852 %} | |
| 3853 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3854 operand iRegN() %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3855 constraint(ALLOC_IN_RC(int_reg)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3856 match(RegN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3857 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3858 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3859 interface(REG_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3860 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3861 |
| 0 | 3862 // Long Register |
| 3863 operand iRegL() %{ | |
| 3864 constraint(ALLOC_IN_RC(long_reg)); | |
| 3865 match(RegL); | |
| 3866 | |
| 3867 format %{ %} | |
| 3868 interface(REG_INTER); | |
| 3869 %} | |
| 3870 | |
| 3871 operand o2RegL() %{ | |
| 3872 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3873 match(iRegL); | |
| 3874 | |
| 3875 format %{ %} | |
| 3876 interface(REG_INTER); | |
| 3877 %} | |
| 3878 | |
| 3879 operand o7RegL() %{ | |
| 3880 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3881 match(iRegL); | |
| 3882 | |
| 3883 format %{ %} | |
| 3884 interface(REG_INTER); | |
| 3885 %} | |
| 3886 | |
| 3887 operand g1RegL() %{ | |
| 3888 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3889 match(iRegL); | |
| 3890 | |
| 3891 format %{ %} | |
| 3892 interface(REG_INTER); | |
| 3893 %} | |
| 3894 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3895 operand g3RegL() %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3896 constraint(ALLOC_IN_RC(g3_regL)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3897 match(iRegL); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3898 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3899 format %{ %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3900 interface(REG_INTER); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3901 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3902 |
| 0 | 3903 // Int Register safe |
| 3904 // This is 64bit safe | |
| 3905 operand iRegIsafe() %{ | |
| 3906 constraint(ALLOC_IN_RC(long_reg)); | |
| 3907 | |
| 3908 match(iRegI); | |
| 3909 | |
| 3910 format %{ %} | |
| 3911 interface(REG_INTER); | |
| 3912 %} | |
| 3913 | |
| 3914 // Condition Code Flag Register | |
| 3915 operand flagsReg() %{ | |
| 3916 constraint(ALLOC_IN_RC(int_flags)); | |
| 3917 match(RegFlags); | |
| 3918 | |
| 3919 format %{ "ccr" %} // both ICC and XCC | |
| 3920 interface(REG_INTER); | |
| 3921 %} | |
| 3922 | |
| 3923 // Condition Code Register, unsigned comparisons. | |
| 3924 operand flagsRegU() %{ | |
| 3925 constraint(ALLOC_IN_RC(int_flags)); | |
| 3926 match(RegFlags); | |
| 3927 | |
| 3928 format %{ "icc_U" %} | |
| 3929 interface(REG_INTER); | |
| 3930 %} | |
| 3931 | |
| 3932 // Condition Code Register, pointer comparisons. | |
| 3933 operand flagsRegP() %{ | |
| 3934 constraint(ALLOC_IN_RC(int_flags)); | |
| 3935 match(RegFlags); | |
| 3936 | |
| 3937 #ifdef _LP64 | |
| 3938 format %{ "xcc_P" %} | |
| 3939 #else | |
| 3940 format %{ "icc_P" %} | |
| 3941 #endif | |
| 3942 interface(REG_INTER); | |
| 3943 %} | |
| 3944 | |
| 3945 // Condition Code Register, long comparisons. | |
| 3946 operand flagsRegL() %{ | |
| 3947 constraint(ALLOC_IN_RC(int_flags)); | |
| 3948 match(RegFlags); | |
| 3949 | |
| 3950 format %{ "xcc_L" %} | |
| 3951 interface(REG_INTER); | |
| 3952 %} | |
| 3953 | |
| 3954 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 3955 operand flagsRegF() %{ | |
| 3956 constraint(ALLOC_IN_RC(float_flags)); | |
| 3957 match(RegFlags); | |
| 3958 match(flagsRegF0); | |
| 3959 | |
| 3960 format %{ %} | |
| 3961 interface(REG_INTER); | |
| 3962 %} | |
| 3963 | |
| 3964 operand flagsRegF0() %{ | |
| 3965 constraint(ALLOC_IN_RC(float_flag0)); | |
| 3966 match(RegFlags); | |
| 3967 | |
| 3968 format %{ %} | |
| 3969 interface(REG_INTER); | |
| 3970 %} | |
| 3971 | |
| 3972 | |
| 3973 // Condition Code Flag Register used by long compare | |
| 3974 operand flagsReg_long_LTGE() %{ | |
| 3975 constraint(ALLOC_IN_RC(int_flags)); | |
| 3976 match(RegFlags); | |
| 3977 format %{ "icc_LTGE" %} | |
| 3978 interface(REG_INTER); | |
| 3979 %} | |
| 3980 operand flagsReg_long_EQNE() %{ | |
| 3981 constraint(ALLOC_IN_RC(int_flags)); | |
| 3982 match(RegFlags); | |
| 3983 format %{ "icc_EQNE" %} | |
| 3984 interface(REG_INTER); | |
| 3985 %} | |
| 3986 operand flagsReg_long_LEGT() %{ | |
| 3987 constraint(ALLOC_IN_RC(int_flags)); | |
| 3988 match(RegFlags); | |
| 3989 format %{ "icc_LEGT" %} | |
| 3990 interface(REG_INTER); | |
| 3991 %} | |
| 3992 | |
| 3993 | |
| 3994 operand regD() %{ | |
| 3995 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 3996 match(RegD); | |
| 3997 | |
| 551 | 3998 match(regD_low); |
| 3999 | |
| 0 | 4000 format %{ %} |
| 4001 interface(REG_INTER); | |
| 4002 %} | |
| 4003 | |
| 4004 operand regF() %{ | |
| 4005 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4006 match(RegF); | |
| 4007 | |
| 4008 format %{ %} | |
| 4009 interface(REG_INTER); | |
| 4010 %} | |
| 4011 | |
| 4012 operand regD_low() %{ | |
| 4013 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4014 match(regD); |
| 0 | 4015 |
| 4016 format %{ %} | |
| 4017 interface(REG_INTER); | |
| 4018 %} | |
| 4019 | |
| 4020 // Special Registers | |
| 4021 | |
| 4022 // Method Register | |
| 4023 operand inline_cache_regP(iRegP reg) %{ | |
| 4024 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4025 match(reg); | |
| 4026 format %{ %} | |
| 4027 interface(REG_INTER); | |
| 4028 %} | |
| 4029 | |
| 4030 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4031 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4032 match(reg); | |
| 4033 format %{ %} | |
| 4034 interface(REG_INTER); | |
| 4035 %} | |
| 4036 | |
| 4037 | |
| 4038 //----------Complex Operands--------------------------------------------------- | |
| 4039 // Indirect Memory Reference | |
| 4040 operand indirect(sp_ptr_RegP reg) %{ | |
| 4041 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4042 match(reg); | |
| 4043 | |
| 4044 op_cost(100); | |
| 4045 format %{ "[$reg]" %} | |
| 4046 interface(MEMORY_INTER) %{ | |
| 4047 base($reg); | |
| 4048 index(0x0); | |
| 4049 scale(0x0); | |
| 4050 disp(0x0); | |
| 4051 %} | |
| 4052 %} | |
| 4053 | |
| 785 | 4054 // Indirect with simm13 Offset |
| 0 | 4055 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4056 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4057 match(AddP reg offset); | |
| 4058 | |
| 4059 op_cost(100); | |
| 4060 format %{ "[$reg + $offset]" %} | |
| 4061 interface(MEMORY_INTER) %{ | |
| 4062 base($reg); | |
| 4063 index(0x0); | |
| 4064 scale(0x0); | |
| 4065 disp($offset); | |
| 4066 %} | |
| 4067 %} | |
| 4068 | |
| 785 | 4069 // Indirect with simm13 Offset minus 7 |
| 4070 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4071 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4072 match(AddP reg offset); | |
| 4073 | |
| 4074 op_cost(100); | |
| 4075 format %{ "[$reg + $offset]" %} | |
| 4076 interface(MEMORY_INTER) %{ | |
| 4077 base($reg); | |
| 4078 index(0x0); | |
| 4079 scale(0x0); | |
| 4080 disp($offset); | |
| 4081 %} | |
| 4082 %} | |
| 4083 | |
| 0 | 4084 // Note: Intel has a swapped version also, like this: |
| 4085 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4086 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4087 // match(AddP offset reg); | |
| 4088 // | |
| 4089 // op_cost(100); | |
| 4090 // format %{ "[$reg + $offset]" %} | |
| 4091 // interface(MEMORY_INTER) %{ | |
| 4092 // base($reg); | |
| 4093 // index(0x0); | |
| 4094 // scale(0x0); | |
| 4095 // disp($offset); | |
| 4096 // %} | |
| 4097 //%} | |
| 4098 //// However, it doesn't make sense for SPARC, since | |
| 4099 // we have no particularly good way to embed oops in | |
| 4100 // single instructions. | |
| 4101 | |
| 4102 // Indirect with Register Index | |
| 4103 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4104 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4105 match(AddP addr index); | |
| 4106 | |
| 4107 op_cost(100); | |
| 4108 format %{ "[$addr + $index]" %} | |
| 4109 interface(MEMORY_INTER) %{ | |
| 4110 base($addr); | |
| 4111 index($index); | |
| 4112 scale(0x0); | |
| 4113 disp(0x0); | |
| 4114 %} | |
| 4115 %} | |
| 4116 | |
| 4117 //----------Special Memory Operands-------------------------------------------- | |
| 4118 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4119 // values on the stack where a match requires a value to | |
| 4120 // flow through memory. | |
| 4121 operand stackSlotI(sRegI reg) %{ | |
| 4122 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4123 op_cost(100); | |
| 4124 //match(RegI); | |
| 4125 format %{ "[$reg]" %} | |
| 4126 interface(MEMORY_INTER) %{ | |
| 4127 base(0xE); // R_SP | |
| 4128 index(0x0); | |
| 4129 scale(0x0); | |
| 4130 disp($reg); // Stack Offset | |
| 4131 %} | |
| 4132 %} | |
| 4133 | |
| 4134 operand stackSlotP(sRegP reg) %{ | |
| 4135 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4136 op_cost(100); | |
| 4137 //match(RegP); | |
| 4138 format %{ "[$reg]" %} | |
| 4139 interface(MEMORY_INTER) %{ | |
| 4140 base(0xE); // R_SP | |
| 4141 index(0x0); | |
| 4142 scale(0x0); | |
| 4143 disp($reg); // Stack Offset | |
| 4144 %} | |
| 4145 %} | |
| 4146 | |
| 4147 operand stackSlotF(sRegF reg) %{ | |
| 4148 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4149 op_cost(100); | |
| 4150 //match(RegF); | |
| 4151 format %{ "[$reg]" %} | |
| 4152 interface(MEMORY_INTER) %{ | |
| 4153 base(0xE); // R_SP | |
| 4154 index(0x0); | |
| 4155 scale(0x0); | |
| 4156 disp($reg); // Stack Offset | |
| 4157 %} | |
| 4158 %} | |
| 4159 operand stackSlotD(sRegD reg) %{ | |
| 4160 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4161 op_cost(100); | |
| 4162 //match(RegD); | |
| 4163 format %{ "[$reg]" %} | |
| 4164 interface(MEMORY_INTER) %{ | |
| 4165 base(0xE); // R_SP | |
| 4166 index(0x0); | |
| 4167 scale(0x0); | |
| 4168 disp($reg); // Stack Offset | |
| 4169 %} | |
| 4170 %} | |
| 4171 operand stackSlotL(sRegL reg) %{ | |
| 4172 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4173 op_cost(100); | |
| 4174 //match(RegL); | |
| 4175 format %{ "[$reg]" %} | |
| 4176 interface(MEMORY_INTER) %{ | |
| 4177 base(0xE); // R_SP | |
| 4178 index(0x0); | |
| 4179 scale(0x0); | |
| 4180 disp($reg); // Stack Offset | |
| 4181 %} | |
| 4182 %} | |
| 4183 | |
| 4184 // Operands for expressing Control Flow | |
| 4185 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4186 // the AD file. It is generically handled within the ADLC. | |
| 4187 | |
| 4188 //----------Conditional Branch Operands---------------------------------------- | |
| 4189 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4190 // the following set of codes: | |
| 4191 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4192 // | |
| 4193 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4194 // by the comparison instruction that sets a condition code flags register. | |
| 4195 // That result is represented by a flags operand whose subtype is appropriate | |
| 4196 // to the unsignedness (etc.) of the comparison. | |
| 4197 // | |
| 4198 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4199 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4200 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4201 | |
| 4202 operand cmpOp() %{ | |
| 4203 match(Bool); | |
| 4204 | |
| 4205 format %{ "" %} | |
| 4206 interface(COND_INTER) %{ | |
| 4207 equal(0x1); | |
| 4208 not_equal(0x9); | |
| 4209 less(0x3); | |
| 4210 greater_equal(0xB); | |
| 4211 less_equal(0x2); | |
| 4212 greater(0xA); | |
| 4213 %} | |
| 4214 %} | |
| 4215 | |
| 4216 // Comparison Op, unsigned | |
| 4217 operand cmpOpU() %{ | |
| 4218 match(Bool); | |
| 4219 | |
| 4220 format %{ "u" %} | |
| 4221 interface(COND_INTER) %{ | |
| 4222 equal(0x1); | |
| 4223 not_equal(0x9); | |
| 4224 less(0x5); | |
| 4225 greater_equal(0xD); | |
| 4226 less_equal(0x4); | |
| 4227 greater(0xC); | |
| 4228 %} | |
| 4229 %} | |
| 4230 | |
| 4231 // Comparison Op, pointer (same as unsigned) | |
| 4232 operand cmpOpP() %{ | |
| 4233 match(Bool); | |
| 4234 | |
| 4235 format %{ "p" %} | |
| 4236 interface(COND_INTER) %{ | |
| 4237 equal(0x1); | |
| 4238 not_equal(0x9); | |
| 4239 less(0x5); | |
| 4240 greater_equal(0xD); | |
| 4241 less_equal(0x4); | |
| 4242 greater(0xC); | |
| 4243 %} | |
| 4244 %} | |
| 4245 | |
| 4246 // Comparison Op, branch-register encoding | |
| 4247 operand cmpOp_reg() %{ | |
| 4248 match(Bool); | |
| 4249 | |
| 4250 format %{ "" %} | |
| 4251 interface(COND_INTER) %{ | |
| 4252 equal (0x1); | |
| 4253 not_equal (0x5); | |
| 4254 less (0x3); | |
| 4255 greater_equal(0x7); | |
| 4256 less_equal (0x2); | |
| 4257 greater (0x6); | |
| 4258 %} | |
| 4259 %} | |
| 4260 | |
| 4261 // Comparison Code, floating, unordered same as less | |
| 4262 operand cmpOpF() %{ | |
| 4263 match(Bool); | |
| 4264 | |
| 4265 format %{ "fl" %} | |
| 4266 interface(COND_INTER) %{ | |
| 4267 equal(0x9); | |
| 4268 not_equal(0x1); | |
| 4269 less(0x3); | |
| 4270 greater_equal(0xB); | |
| 4271 less_equal(0xE); | |
| 4272 greater(0x6); | |
| 4273 %} | |
| 4274 %} | |
| 4275 | |
| 4276 // Used by long compare | |
| 4277 operand cmpOp_commute() %{ | |
| 4278 match(Bool); | |
| 4279 | |
| 4280 format %{ "" %} | |
| 4281 interface(COND_INTER) %{ | |
| 4282 equal(0x1); | |
| 4283 not_equal(0x9); | |
| 4284 less(0xA); | |
| 4285 greater_equal(0x2); | |
| 4286 less_equal(0xB); | |
| 4287 greater(0x3); | |
| 4288 %} | |
| 4289 %} | |
| 4290 | |
| 4291 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4292 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4293 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4294 // instructions for every form of operand when the instruction accepts |
| 4295 // multiple operand types with the same basic encoding and format. The classic | |
| 4296 // case of this is memory operands. | |
| 4297 opclass memory( indirect, indOffset13, indIndex ); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
4298 opclass indIndexMemory( indIndex ); |
| 0 | 4299 |
| 4300 //----------PIPELINE----------------------------------------------------------- | |
| 4301 pipeline %{ | |
| 4302 | |
| 4303 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4304 attributes %{ | |
| 4305 fixed_size_instructions; // Fixed size instructions | |
| 4306 branch_has_delay_slot; // Branch has delay slot following | |
| 4307 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4308 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4309 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4310 instruction_fetch_units = 1; // of 16 bytes | |
| 4311 | |
| 4312 // List of nop instructions | |
| 4313 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4314 %} | |
| 4315 | |
| 4316 //----------RESOURCES---------------------------------------------------------- | |
| 4317 // Resources are the functional units available to the machine | |
| 4318 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4319 | |
| 4320 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4321 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4322 | |
| 4323 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4324 | |
| 4325 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4326 // Pipeline Classes describe the stages in which input and output are | |
| 4327 // referenced by the hardware pipeline. | |
| 4328 | |
| 4329 // Integer ALU reg-reg operation | |
| 4330 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4331 single_instruction; | |
| 4332 dst : E(write); | |
| 4333 src1 : R(read); | |
| 4334 src2 : R(read); | |
| 4335 IALU : R; | |
| 4336 %} | |
| 4337 | |
| 4338 // Integer ALU reg-reg long operation | |
| 4339 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4340 instruction_count(2); | |
| 4341 dst : E(write); | |
| 4342 src1 : R(read); | |
| 4343 src2 : R(read); | |
| 4344 IALU : R; | |
| 4345 IALU : R; | |
| 4346 %} | |
| 4347 | |
| 4348 // Integer ALU reg-reg long dependent operation | |
| 4349 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4350 instruction_count(1); multiple_bundles; | |
| 4351 dst : E(write); | |
| 4352 src1 : R(read); | |
| 4353 src2 : R(read); | |
| 4354 cr : E(write); | |
| 4355 IALU : R(2); | |
| 4356 %} | |
| 4357 | |
| 4358 // Integer ALU reg-imm operaion | |
| 4359 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4360 single_instruction; | |
| 4361 dst : E(write); | |
| 4362 src1 : R(read); | |
| 4363 IALU : R; | |
| 4364 %} | |
| 4365 | |
| 4366 // Integer ALU reg-reg operation with condition code | |
| 4367 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4368 single_instruction; | |
| 4369 dst : E(write); | |
| 4370 cr : E(write); | |
| 4371 src1 : R(read); | |
| 4372 src2 : R(read); | |
| 4373 IALU : R; | |
| 4374 %} | |
| 4375 | |
| 4376 // Integer ALU reg-imm operation with condition code | |
| 4377 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4378 single_instruction; | |
| 4379 dst : E(write); | |
| 4380 cr : E(write); | |
| 4381 src1 : R(read); | |
| 4382 IALU : R; | |
| 4383 %} | |
| 4384 | |
| 4385 // Integer ALU zero-reg operation | |
| 4386 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4387 single_instruction; | |
| 4388 dst : E(write); | |
| 4389 src2 : R(read); | |
| 4390 IALU : R; | |
| 4391 %} | |
| 4392 | |
| 4393 // Integer ALU zero-reg operation with condition code only | |
| 4394 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4395 single_instruction; | |
| 4396 cr : E(write); | |
| 4397 src : R(read); | |
| 4398 IALU : R; | |
| 4399 %} | |
| 4400 | |
| 4401 // Integer ALU reg-reg operation with condition code only | |
| 4402 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4403 single_instruction; | |
| 4404 cr : E(write); | |
| 4405 src1 : R(read); | |
| 4406 src2 : R(read); | |
| 4407 IALU : R; | |
| 4408 %} | |
| 4409 | |
| 4410 // Integer ALU reg-imm operation with condition code only | |
| 4411 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4412 single_instruction; | |
| 4413 cr : E(write); | |
| 4414 src1 : R(read); | |
| 4415 IALU : R; | |
| 4416 %} | |
| 4417 | |
| 4418 // Integer ALU reg-reg-zero operation with condition code only | |
| 4419 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4420 single_instruction; | |
| 4421 cr : E(write); | |
| 4422 src1 : R(read); | |
| 4423 src2 : R(read); | |
| 4424 IALU : R; | |
| 4425 %} | |
| 4426 | |
| 4427 // Integer ALU reg-imm-zero operation with condition code only | |
| 4428 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4429 single_instruction; | |
| 4430 cr : E(write); | |
| 4431 src1 : R(read); | |
| 4432 IALU : R; | |
| 4433 %} | |
| 4434 | |
| 4435 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4436 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4437 single_instruction; | |
| 4438 cr : E(write); | |
| 4439 src1 : E(write); | |
| 4440 src1 : R(read); | |
| 4441 src2 : R(read); | |
| 4442 IALU : R; | |
| 4443 %} | |
| 4444 | |
| 4445 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4446 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4447 single_instruction; | |
| 4448 cr : E(write); | |
| 4449 src1 : E(write); | |
| 4450 src1 : R(read); | |
| 4451 IALU : R; | |
| 4452 %} | |
| 4453 | |
| 4454 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4455 multiple_bundles; | |
| 4456 dst : E(write)+4; | |
| 4457 cr : E(write); | |
| 4458 src1 : R(read); | |
| 4459 src2 : R(read); | |
| 4460 IALU : R(3); | |
| 4461 BR : R(2); | |
| 4462 %} | |
| 4463 | |
| 4464 // Integer ALU operation | |
| 4465 pipe_class ialu_none(iRegI dst) %{ | |
| 4466 single_instruction; | |
| 4467 dst : E(write); | |
| 4468 IALU : R; | |
| 4469 %} | |
| 4470 | |
| 4471 // Integer ALU reg operation | |
| 4472 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4473 single_instruction; may_have_no_code; | |
| 4474 dst : E(write); | |
| 4475 src : R(read); | |
| 4476 IALU : R; | |
| 4477 %} | |
| 4478 | |
| 4479 // Integer ALU reg conditional operation | |
| 4480 // This instruction has a 1 cycle stall, and cannot execute | |
| 4481 // in the same cycle as the instruction setting the condition | |
| 4482 // code. We kludge this by pretending to read the condition code | |
| 4483 // 1 cycle earlier, and by marking the functional units as busy | |
| 4484 // for 2 cycles with the result available 1 cycle later than | |
| 4485 // is really the case. | |
| 4486 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4487 single_instruction; | |
| 4488 op2_out : C(write); | |
| 4489 op1 : R(read); | |
| 4490 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4491 BR : R(2); | |
| 4492 MS : R(2); | |
| 4493 %} | |
| 4494 | |
| 4495 #ifdef _LP64 | |
| 4496 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4497 instruction_count(1); multiple_bundles; | |
| 4498 dst : C(write)+1; | |
| 4499 src : R(read)+1; | |
| 4500 IALU : R(1); | |
| 4501 BR : E(2); | |
| 4502 MS : E(2); | |
| 4503 %} | |
| 4504 #endif | |
| 4505 | |
| 4506 // Integer ALU reg operation | |
| 4507 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4508 single_instruction; may_have_no_code; | |
| 4509 dst : E(write); | |
| 4510 src : R(read); | |
| 4511 IALU : R; | |
| 4512 %} | |
| 4513 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4514 single_instruction; may_have_no_code; | |
| 4515 dst : E(write); | |
| 4516 src : R(read); | |
| 4517 IALU : R; | |
| 4518 %} | |
| 4519 | |
| 4520 // Two integer ALU reg operations | |
| 4521 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4522 instruction_count(2); | |
| 4523 dst : E(write); | |
| 4524 src : R(read); | |
| 4525 A0 : R; | |
| 4526 A1 : R; | |
| 4527 %} | |
| 4528 | |
| 4529 // Two integer ALU reg operations | |
| 4530 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4531 instruction_count(2); may_have_no_code; | |
| 4532 dst : E(write); | |
| 4533 src : R(read); | |
| 4534 A0 : R; | |
| 4535 A1 : R; | |
| 4536 %} | |
| 4537 | |
| 4538 // Integer ALU imm operation | |
| 4539 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4540 single_instruction; | |
| 4541 dst : E(write); | |
| 4542 IALU : R; | |
| 4543 %} | |
| 4544 | |
| 4545 // Integer ALU reg-reg with carry operation | |
| 4546 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4547 single_instruction; | |
| 4548 dst : E(write); | |
| 4549 src1 : R(read); | |
| 4550 src2 : R(read); | |
| 4551 IALU : R; | |
| 4552 %} | |
| 4553 | |
| 4554 // Integer ALU cc operation | |
| 4555 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4556 single_instruction; | |
| 4557 dst : E(write); | |
| 4558 cc : R(read); | |
| 4559 IALU : R; | |
| 4560 %} | |
| 4561 | |
| 4562 // Integer ALU cc / second IALU operation | |
| 4563 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4564 instruction_count(1); multiple_bundles; | |
| 4565 dst : E(write)+1; | |
| 4566 src : R(read); | |
| 4567 IALU : R; | |
| 4568 %} | |
| 4569 | |
| 4570 // Integer ALU cc / second IALU operation | |
| 4571 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4572 instruction_count(1); multiple_bundles; | |
| 4573 dst : E(write)+1; | |
| 4574 p : R(read); | |
| 4575 q : R(read); | |
| 4576 IALU : R; | |
| 4577 %} | |
| 4578 | |
| 4579 // Integer ALU hi-lo-reg operation | |
| 4580 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4581 instruction_count(1); multiple_bundles; | |
| 4582 dst : E(write)+1; | |
| 4583 IALU : R(2); | |
| 4584 %} | |
| 4585 | |
| 4586 // Float ALU hi-lo-reg operation (with temp) | |
| 4587 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4588 instruction_count(1); multiple_bundles; | |
| 4589 dst : E(write)+1; | |
| 4590 IALU : R(2); | |
| 4591 %} | |
| 4592 | |
| 4593 // Long Constant | |
| 4594 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4595 instruction_count(2); multiple_bundles; | |
| 4596 dst : E(write)+1; | |
| 4597 IALU : R(2); | |
| 4598 IALU : R(2); | |
| 4599 %} | |
| 4600 | |
| 4601 // Pointer Constant | |
| 4602 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4603 instruction_count(0); multiple_bundles; | |
| 4604 fixed_latency(6); | |
| 4605 %} | |
| 4606 | |
| 4607 // Polling Address | |
| 4608 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4609 #ifdef _LP64 | |
| 4610 instruction_count(0); multiple_bundles; | |
| 4611 fixed_latency(6); | |
| 4612 #else | |
| 4613 dst : E(write); | |
| 4614 IALU : R; | |
| 4615 #endif | |
| 4616 %} | |
| 4617 | |
| 4618 // Long Constant small | |
| 4619 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4620 instruction_count(2); | |
| 4621 dst : E(write); | |
| 4622 IALU : R; | |
| 4623 IALU : R; | |
| 4624 %} | |
| 4625 | |
| 4626 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4627 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4628 instruction_count(1); multiple_bundles; | |
| 4629 src : R(read); | |
| 4630 dst : M(write)+1; | |
| 4631 IALU : R; | |
| 4632 MS : E; | |
| 4633 %} | |
| 4634 | |
| 4635 // Integer ALU nop operation | |
| 4636 pipe_class ialu_nop() %{ | |
| 4637 single_instruction; | |
| 4638 IALU : R; | |
| 4639 %} | |
| 4640 | |
| 4641 // Integer ALU nop operation | |
| 4642 pipe_class ialu_nop_A0() %{ | |
| 4643 single_instruction; | |
| 4644 A0 : R; | |
| 4645 %} | |
| 4646 | |
| 4647 // Integer ALU nop operation | |
| 4648 pipe_class ialu_nop_A1() %{ | |
| 4649 single_instruction; | |
| 4650 A1 : R; | |
| 4651 %} | |
| 4652 | |
| 4653 // Integer Multiply reg-reg operation | |
| 4654 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4655 single_instruction; | |
| 4656 dst : E(write); | |
| 4657 src1 : R(read); | |
| 4658 src2 : R(read); | |
| 4659 MS : R(5); | |
| 4660 %} | |
| 4661 | |
| 4662 // Integer Multiply reg-imm operation | |
| 4663 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4664 single_instruction; | |
| 4665 dst : E(write); | |
| 4666 src1 : R(read); | |
| 4667 MS : R(5); | |
| 4668 %} | |
| 4669 | |
| 4670 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4671 single_instruction; | |
| 4672 dst : E(write)+4; | |
| 4673 src1 : R(read); | |
| 4674 src2 : R(read); | |
| 4675 MS : R(6); | |
| 4676 %} | |
| 4677 | |
| 4678 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4679 single_instruction; | |
| 4680 dst : E(write)+4; | |
| 4681 src1 : R(read); | |
| 4682 MS : R(6); | |
| 4683 %} | |
| 4684 | |
| 4685 // Integer Divide reg-reg | |
| 4686 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4687 instruction_count(1); multiple_bundles; | |
| 4688 dst : E(write); | |
| 4689 temp : E(write); | |
| 4690 src1 : R(read); | |
| 4691 src2 : R(read); | |
| 4692 temp : R(read); | |
| 4693 MS : R(38); | |
| 4694 %} | |
| 4695 | |
| 4696 // Integer Divide reg-imm | |
| 4697 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4698 instruction_count(1); multiple_bundles; | |
| 4699 dst : E(write); | |
| 4700 temp : E(write); | |
| 4701 src1 : R(read); | |
| 4702 temp : R(read); | |
| 4703 MS : R(38); | |
| 4704 %} | |
| 4705 | |
| 4706 // Long Divide | |
| 4707 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4708 dst : E(write)+71; | |
| 4709 src1 : R(read); | |
| 4710 src2 : R(read)+1; | |
| 4711 MS : R(70); | |
| 4712 %} | |
| 4713 | |
| 4714 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4715 dst : E(write)+71; | |
| 4716 src1 : R(read); | |
| 4717 MS : R(70); | |
| 4718 %} | |
| 4719 | |
| 4720 // Floating Point Add Float | |
| 4721 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4722 single_instruction; | |
| 4723 dst : X(write); | |
| 4724 src1 : E(read); | |
| 4725 src2 : E(read); | |
| 4726 FA : R; | |
| 4727 %} | |
| 4728 | |
| 4729 // Floating Point Add Double | |
| 4730 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4731 single_instruction; | |
| 4732 dst : X(write); | |
| 4733 src1 : E(read); | |
| 4734 src2 : E(read); | |
| 4735 FA : R; | |
| 4736 %} | |
| 4737 | |
| 4738 // Floating Point Conditional Move based on integer flags | |
| 4739 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4740 single_instruction; | |
| 4741 dst : X(write); | |
| 4742 src : E(read); | |
| 4743 cr : R(read); | |
| 4744 FA : R(2); | |
| 4745 BR : R(2); | |
| 4746 %} | |
| 4747 | |
| 4748 // Floating Point Conditional Move based on integer flags | |
| 4749 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4750 single_instruction; | |
| 4751 dst : X(write); | |
| 4752 src : E(read); | |
| 4753 cr : R(read); | |
| 4754 FA : R(2); | |
| 4755 BR : R(2); | |
| 4756 %} | |
| 4757 | |
| 4758 // Floating Point Multiply Float | |
| 4759 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4760 single_instruction; | |
| 4761 dst : X(write); | |
| 4762 src1 : E(read); | |
| 4763 src2 : E(read); | |
| 4764 FM : R; | |
| 4765 %} | |
| 4766 | |
| 4767 // Floating Point Multiply Double | |
| 4768 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4769 single_instruction; | |
| 4770 dst : X(write); | |
| 4771 src1 : E(read); | |
| 4772 src2 : E(read); | |
| 4773 FM : R; | |
| 4774 %} | |
| 4775 | |
| 4776 // Floating Point Divide Float | |
| 4777 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4778 single_instruction; | |
| 4779 dst : X(write); | |
| 4780 src1 : E(read); | |
| 4781 src2 : E(read); | |
| 4782 FM : R; | |
| 4783 FDIV : C(14); | |
| 4784 %} | |
| 4785 | |
| 4786 // Floating Point Divide Double | |
| 4787 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4788 single_instruction; | |
| 4789 dst : X(write); | |
| 4790 src1 : E(read); | |
| 4791 src2 : E(read); | |
| 4792 FM : R; | |
| 4793 FDIV : C(17); | |
| 4794 %} | |
| 4795 | |
| 4796 // Floating Point Move/Negate/Abs Float | |
| 4797 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4798 single_instruction; | |
| 4799 dst : W(write); | |
| 4800 src : E(read); | |
| 4801 FA : R(1); | |
| 4802 %} | |
| 4803 | |
| 4804 // Floating Point Move/Negate/Abs Double | |
| 4805 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4806 single_instruction; | |
| 4807 dst : W(write); | |
| 4808 src : E(read); | |
| 4809 FA : R; | |
| 4810 %} | |
| 4811 | |
| 4812 // Floating Point Convert F->D | |
| 4813 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4814 single_instruction; | |
| 4815 dst : X(write); | |
| 4816 src : E(read); | |
| 4817 FA : R; | |
| 4818 %} | |
| 4819 | |
| 4820 // Floating Point Convert I->D | |
| 4821 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4822 single_instruction; | |
| 4823 dst : X(write); | |
| 4824 src : E(read); | |
| 4825 FA : R; | |
| 4826 %} | |
| 4827 | |
| 4828 // Floating Point Convert LHi->D | |
| 4829 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4830 single_instruction; | |
| 4831 dst : X(write); | |
| 4832 src : E(read); | |
| 4833 FA : R; | |
| 4834 %} | |
| 4835 | |
| 4836 // Floating Point Convert L->D | |
| 4837 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4838 single_instruction; | |
| 4839 dst : X(write); | |
| 4840 src : E(read); | |
| 4841 FA : R; | |
| 4842 %} | |
| 4843 | |
| 4844 // Floating Point Convert L->F | |
| 4845 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4846 single_instruction; | |
| 4847 dst : X(write); | |
| 4848 src : E(read); | |
| 4849 FA : R; | |
| 4850 %} | |
| 4851 | |
| 4852 // Floating Point Convert D->F | |
| 4853 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4854 single_instruction; | |
| 4855 dst : X(write); | |
| 4856 src : E(read); | |
| 4857 FA : R; | |
| 4858 %} | |
| 4859 | |
| 4860 // Floating Point Convert I->L | |
| 4861 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4862 single_instruction; | |
| 4863 dst : X(write); | |
| 4864 src : E(read); | |
| 4865 FA : R; | |
| 4866 %} | |
| 4867 | |
| 4868 // Floating Point Convert D->F | |
| 4869 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4870 instruction_count(1); multiple_bundles; | |
| 4871 dst : X(write)+6; | |
| 4872 src : E(read); | |
| 4873 FA : R; | |
| 4874 %} | |
| 4875 | |
| 4876 // Floating Point Convert D->L | |
| 4877 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4878 instruction_count(1); multiple_bundles; | |
| 4879 dst : X(write)+6; | |
| 4880 src : E(read); | |
| 4881 FA : R; | |
| 4882 %} | |
| 4883 | |
| 4884 // Floating Point Convert F->I | |
| 4885 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4886 instruction_count(1); multiple_bundles; | |
| 4887 dst : X(write)+6; | |
| 4888 src : E(read); | |
| 4889 FA : R; | |
| 4890 %} | |
| 4891 | |
| 4892 // Floating Point Convert F->L | |
| 4893 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4894 instruction_count(1); multiple_bundles; | |
| 4895 dst : X(write)+6; | |
| 4896 src : E(read); | |
| 4897 FA : R; | |
| 4898 %} | |
| 4899 | |
| 4900 // Floating Point Convert I->F | |
| 4901 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4902 single_instruction; | |
| 4903 dst : X(write); | |
| 4904 src : E(read); | |
| 4905 FA : R; | |
| 4906 %} | |
| 4907 | |
| 4908 // Floating Point Compare | |
| 4909 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4910 single_instruction; | |
| 4911 cr : X(write); | |
| 4912 src1 : E(read); | |
| 4913 src2 : E(read); | |
| 4914 FA : R; | |
| 4915 %} | |
| 4916 | |
| 4917 // Floating Point Compare | |
| 4918 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 4919 single_instruction; | |
| 4920 cr : X(write); | |
| 4921 src1 : E(read); | |
| 4922 src2 : E(read); | |
| 4923 FA : R; | |
| 4924 %} | |
| 4925 | |
| 4926 // Floating Add Nop | |
| 4927 pipe_class fadd_nop() %{ | |
| 4928 single_instruction; | |
| 4929 FA : R; | |
| 4930 %} | |
| 4931 | |
| 4932 // Integer Store to Memory | |
| 4933 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 4934 single_instruction; | |
| 4935 mem : R(read); | |
| 4936 src : C(read); | |
| 4937 MS : R; | |
| 4938 %} | |
| 4939 | |
| 4940 // Integer Store to Memory | |
| 4941 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 4942 single_instruction; | |
| 4943 mem : R(read); | |
| 4944 src : C(read); | |
| 4945 MS : R; | |
| 4946 %} | |
| 4947 | |
| 4948 // Integer Store Zero to Memory | |
| 4949 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 4950 single_instruction; | |
| 4951 mem : R(read); | |
| 4952 MS : R; | |
| 4953 %} | |
| 4954 | |
| 4955 // Special Stack Slot Store | |
| 4956 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 4957 single_instruction; | |
| 4958 stkSlot : R(read); | |
| 4959 src : C(read); | |
| 4960 MS : R; | |
| 4961 %} | |
| 4962 | |
| 4963 // Special Stack Slot Store | |
| 4964 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 4965 instruction_count(2); multiple_bundles; | |
| 4966 stkSlot : R(read); | |
| 4967 src : C(read); | |
| 4968 MS : R(2); | |
| 4969 %} | |
| 4970 | |
| 4971 // Float Store | |
| 4972 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 4973 single_instruction; | |
| 4974 mem : R(read); | |
| 4975 src : C(read); | |
| 4976 MS : R; | |
| 4977 %} | |
| 4978 | |
| 4979 // Float Store | |
| 4980 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 4981 single_instruction; | |
| 4982 mem : R(read); | |
| 4983 MS : R; | |
| 4984 %} | |
| 4985 | |
| 4986 // Double Store | |
| 4987 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 4988 instruction_count(1); | |
| 4989 mem : R(read); | |
| 4990 src : C(read); | |
| 4991 MS : R; | |
| 4992 %} | |
| 4993 | |
| 4994 // Double Store | |
| 4995 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 4996 single_instruction; | |
| 4997 mem : R(read); | |
| 4998 MS : R; | |
| 4999 %} | |
| 5000 | |
| 5001 // Special Stack Slot Float Store | |
| 5002 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5003 single_instruction; | |
| 5004 stkSlot : R(read); | |
| 5005 src : C(read); | |
| 5006 MS : R; | |
| 5007 %} | |
| 5008 | |
| 5009 // Special Stack Slot Double Store | |
| 5010 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5011 single_instruction; | |
| 5012 stkSlot : R(read); | |
| 5013 src : C(read); | |
| 5014 MS : R; | |
| 5015 %} | |
| 5016 | |
| 5017 // Integer Load (when sign bit propagation not needed) | |
| 5018 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5019 single_instruction; | |
| 5020 mem : R(read); | |
| 5021 dst : C(write); | |
| 5022 MS : R; | |
| 5023 %} | |
| 5024 | |
| 5025 // Integer Load from stack operand | |
| 5026 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5027 single_instruction; | |
| 5028 mem : R(read); | |
| 5029 dst : C(write); | |
| 5030 MS : R; | |
| 5031 %} | |
| 5032 | |
| 5033 // Integer Load (when sign bit propagation or masking is needed) | |
| 5034 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5035 single_instruction; | |
| 5036 mem : R(read); | |
| 5037 dst : M(write); | |
| 5038 MS : R; | |
| 5039 %} | |
| 5040 | |
| 5041 // Float Load | |
| 5042 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5043 single_instruction; | |
| 5044 mem : R(read); | |
| 5045 dst : M(write); | |
| 5046 MS : R; | |
| 5047 %} | |
| 5048 | |
| 5049 // Float Load | |
| 5050 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5051 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5052 mem : R(read); | |
| 5053 dst : M(write); | |
| 5054 MS : R; | |
| 5055 %} | |
| 5056 | |
| 5057 // Float Load | |
| 5058 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5059 single_instruction; | |
| 5060 stkSlot : R(read); | |
| 5061 dst : M(write); | |
| 5062 MS : R; | |
| 5063 %} | |
| 5064 | |
| 5065 // Float Load | |
| 5066 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5067 single_instruction; | |
| 5068 stkSlot : R(read); | |
| 5069 dst : M(write); | |
| 5070 MS : R; | |
| 5071 %} | |
| 5072 | |
| 5073 // Memory Nop | |
| 5074 pipe_class mem_nop() %{ | |
| 5075 single_instruction; | |
| 5076 MS : R; | |
| 5077 %} | |
| 5078 | |
| 5079 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5080 single_instruction; | |
| 5081 dst : E(write); | |
| 5082 IALU : R; | |
| 5083 %} | |
| 5084 | |
| 5085 pipe_class loadPollP(iRegP poll) %{ | |
| 5086 single_instruction; | |
| 5087 poll : R(read); | |
| 5088 MS : R; | |
| 5089 %} | |
| 5090 | |
| 5091 pipe_class br(Universe br, label labl) %{ | |
| 5092 single_instruction_with_delay_slot; | |
| 5093 BR : R; | |
| 5094 %} | |
| 5095 | |
| 5096 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5097 single_instruction_with_delay_slot; | |
| 5098 cr : E(read); | |
| 5099 BR : R; | |
| 5100 %} | |
| 5101 | |
| 5102 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5103 single_instruction_with_delay_slot; | |
| 5104 op1 : E(read); | |
| 5105 BR : R; | |
| 5106 MS : R; | |
| 5107 %} | |
| 5108 | |
| 5109 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
| 5110 single_instruction_with_delay_slot; | |
| 5111 cr : E(read); | |
| 5112 BR : R; | |
| 5113 %} | |
| 5114 | |
| 5115 pipe_class br_nop() %{ | |
| 5116 single_instruction; | |
| 5117 BR : R; | |
| 5118 %} | |
| 5119 | |
| 5120 pipe_class simple_call(method meth) %{ | |
| 5121 instruction_count(2); multiple_bundles; force_serialization; | |
| 5122 fixed_latency(100); | |
| 5123 BR : R(1); | |
| 5124 MS : R(1); | |
| 5125 A0 : R(1); | |
| 5126 %} | |
| 5127 | |
| 5128 pipe_class compiled_call(method meth) %{ | |
| 5129 instruction_count(1); multiple_bundles; force_serialization; | |
| 5130 fixed_latency(100); | |
| 5131 MS : R(1); | |
| 5132 %} | |
| 5133 | |
| 5134 pipe_class call(method meth) %{ | |
| 5135 instruction_count(0); multiple_bundles; force_serialization; | |
| 5136 fixed_latency(100); | |
| 5137 %} | |
| 5138 | |
| 5139 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5140 single_instruction; has_delay_slot; | |
| 5141 fixed_latency(100); | |
| 5142 BR : R(1); | |
| 5143 MS : R(1); | |
| 5144 %} | |
| 5145 | |
| 5146 pipe_class ret(Universe ignore) %{ | |
| 5147 single_instruction; has_delay_slot; | |
| 5148 BR : R(1); | |
| 5149 MS : R(1); | |
| 5150 %} | |
| 5151 | |
| 5152 pipe_class ret_poll(g3RegP poll) %{ | |
| 5153 instruction_count(3); has_delay_slot; | |
| 5154 poll : E(read); | |
| 5155 MS : R; | |
| 5156 %} | |
| 5157 | |
| 5158 // The real do-nothing guy | |
| 5159 pipe_class empty( ) %{ | |
| 5160 instruction_count(0); | |
| 5161 %} | |
| 5162 | |
| 5163 pipe_class long_memory_op() %{ | |
| 5164 instruction_count(0); multiple_bundles; force_serialization; | |
| 5165 fixed_latency(25); | |
| 5166 MS : R(1); | |
| 5167 %} | |
| 5168 | |
| 5169 // Check-cast | |
| 5170 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5171 array : R(read); | |
| 5172 match : R(read); | |
| 5173 IALU : R(2); | |
| 5174 BR : R(2); | |
| 5175 MS : R; | |
| 5176 %} | |
| 5177 | |
| 5178 // Convert FPU flags into +1,0,-1 | |
| 5179 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5180 src1 : E(read); | |
| 5181 src2 : E(read); | |
| 5182 dst : E(write); | |
| 5183 FA : R; | |
| 5184 MS : R(2); | |
| 5185 BR : R(2); | |
| 5186 %} | |
| 5187 | |
| 5188 // Compare for p < q, and conditionally add y | |
| 5189 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5190 p : E(read); | |
| 5191 q : E(read); | |
| 5192 y : E(read); | |
| 5193 IALU : R(3) | |
| 5194 %} | |
| 5195 | |
| 5196 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5197 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5198 src2 : E(read); | |
| 5199 srcdst : E(read); | |
| 5200 IALU : R; | |
| 5201 BR : R; | |
| 5202 %} | |
| 5203 | |
| 5204 // Define the class for the Nop node | |
| 5205 define %{ | |
| 5206 MachNop = ialu_nop; | |
| 5207 %} | |
| 5208 | |
| 5209 %} | |
| 5210 | |
| 5211 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5212 | |
| 5213 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5214 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5215 // No match rule to avoid chain rule match. | |
| 5216 effect(DEF dst, USE src); | |
| 5217 ins_cost(MEMORY_REF_COST); | |
| 5218 size(4); | |
| 5219 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5220 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5221 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5222 ins_pipe(floadF_stk); |
| 5223 %} | |
| 5224 | |
| 5225 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5226 // No match rule to avoid chain rule match. | |
| 5227 effect(DEF dst, USE src); | |
| 5228 ins_cost(MEMORY_REF_COST); | |
| 5229 size(4); | |
| 5230 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5231 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5232 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5233 ins_pipe(floadD_stk); |
| 5234 %} | |
| 5235 | |
| 5236 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5237 // No match rule to avoid chain rule match. | |
| 5238 effect(DEF dst, USE src); | |
| 5239 ins_cost(MEMORY_REF_COST); | |
| 5240 size(4); | |
| 5241 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5242 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5243 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5244 ins_pipe(fstoreF_stk_reg); |
| 5245 %} | |
| 5246 | |
| 5247 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5248 // No match rule to avoid chain rule match. | |
| 5249 effect(DEF dst, USE src); | |
| 5250 ins_cost(MEMORY_REF_COST); | |
| 5251 size(4); | |
| 5252 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5253 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5254 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5255 ins_pipe(fstoreD_stk_reg); |
| 5256 %} | |
| 5257 | |
| 5258 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5259 effect(DEF dst, USE src); | |
| 5260 ins_cost(MEMORY_REF_COST*2); | |
| 5261 size(8); | |
| 5262 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5263 "STW R_G0,$dst.lo" %} | |
| 5264 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5265 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5266 ins_pipe(lstoreI_stk_reg); |
| 5267 %} | |
| 5268 | |
| 5269 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5270 // No match rule to avoid chain rule match. | |
| 5271 effect(DEF dst, USE src); | |
| 5272 ins_cost(MEMORY_REF_COST); | |
| 5273 size(4); | |
| 5274 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5275 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5276 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5277 ins_pipe(istore_stk_reg); |
| 5278 %} | |
| 5279 | |
| 5280 //---------- Chain stack slots between similar types -------- | |
| 5281 | |
| 5282 // Load integer from stack slot | |
| 5283 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5284 match(Set dst src); | |
| 5285 ins_cost(MEMORY_REF_COST); | |
| 5286 | |
| 5287 size(4); | |
| 5288 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5289 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5290 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5291 ins_pipe(iload_mem); |
| 5292 %} | |
| 5293 | |
| 5294 // Store integer to stack slot | |
| 5295 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5296 match(Set dst src); | |
| 5297 ins_cost(MEMORY_REF_COST); | |
| 5298 | |
| 5299 size(4); | |
| 5300 format %{ "STW $src,$dst\t!stk" %} | |
| 5301 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5302 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5303 ins_pipe(istore_mem_reg); |
| 5304 %} | |
| 5305 | |
| 5306 // Load long from stack slot | |
| 5307 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5308 match(Set dst src); | |
| 5309 | |
| 5310 ins_cost(MEMORY_REF_COST); | |
| 5311 size(4); | |
| 5312 format %{ "LDX $src,$dst\t! long" %} | |
| 5313 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5314 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5315 ins_pipe(iload_mem); |
| 5316 %} | |
| 5317 | |
| 5318 // Store long to stack slot | |
| 5319 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5320 match(Set dst src); | |
| 5321 | |
| 5322 ins_cost(MEMORY_REF_COST); | |
| 5323 size(4); | |
| 5324 format %{ "STX $src,$dst\t! long" %} | |
| 5325 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5326 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5327 ins_pipe(istore_mem_reg); |
| 5328 %} | |
| 5329 | |
| 5330 #ifdef _LP64 | |
| 5331 // Load pointer from stack slot, 64-bit encoding | |
| 5332 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5333 match(Set dst src); | |
| 5334 ins_cost(MEMORY_REF_COST); | |
| 5335 size(4); | |
| 5336 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5337 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5338 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5339 ins_pipe(iload_mem); |
| 5340 %} | |
| 5341 | |
| 5342 // Store pointer to stack slot | |
| 5343 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5344 match(Set dst src); | |
| 5345 ins_cost(MEMORY_REF_COST); | |
| 5346 size(4); | |
| 5347 format %{ "STX $src,$dst\t!ptr" %} | |
| 5348 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5349 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5350 ins_pipe(istore_mem_reg); |
| 5351 %} | |
| 5352 #else // _LP64 | |
| 5353 // Load pointer from stack slot, 32-bit encoding | |
| 5354 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5355 match(Set dst src); | |
| 5356 ins_cost(MEMORY_REF_COST); | |
| 5357 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5358 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5359 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5360 ins_pipe(iload_mem); |
| 5361 %} | |
| 5362 | |
| 5363 // Store pointer to stack slot | |
| 5364 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5365 match(Set dst src); | |
| 5366 ins_cost(MEMORY_REF_COST); | |
| 5367 format %{ "STW $src,$dst\t!ptr" %} | |
| 5368 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5369 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5370 ins_pipe(istore_mem_reg); |
| 5371 %} | |
| 5372 #endif // _LP64 | |
| 5373 | |
| 5374 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5375 // Nop using the A0 functional unit | |
| 5376 instruct Nop_A0() %{ | |
| 5377 ins_cost(0); | |
| 5378 | |
| 5379 format %{ "NOP ! Alu Pipeline" %} | |
| 5380 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5381 ins_encode( form2_nop() ); | |
| 5382 ins_pipe(ialu_nop_A0); | |
| 5383 %} | |
| 5384 | |
| 5385 // Nop using the A1 functional unit | |
| 5386 instruct Nop_A1( ) %{ | |
| 5387 ins_cost(0); | |
| 5388 | |
| 5389 format %{ "NOP ! Alu Pipeline" %} | |
| 5390 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5391 ins_encode( form2_nop() ); | |
| 5392 ins_pipe(ialu_nop_A1); | |
| 5393 %} | |
| 5394 | |
| 5395 // Nop using the memory functional unit | |
| 5396 instruct Nop_MS( ) %{ | |
| 5397 ins_cost(0); | |
| 5398 | |
| 5399 format %{ "NOP ! Memory Pipeline" %} | |
| 5400 ins_encode( emit_mem_nop ); | |
| 5401 ins_pipe(mem_nop); | |
| 5402 %} | |
| 5403 | |
| 5404 // Nop using the floating add functional unit | |
| 5405 instruct Nop_FA( ) %{ | |
| 5406 ins_cost(0); | |
| 5407 | |
| 5408 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5409 ins_encode( emit_fadd_nop ); | |
| 5410 ins_pipe(fadd_nop); | |
| 5411 %} | |
| 5412 | |
| 5413 // Nop using the branch functional unit | |
| 5414 instruct Nop_BR( ) %{ | |
| 5415 ins_cost(0); | |
| 5416 | |
| 5417 format %{ "NOP ! Branch Pipeline" %} | |
| 5418 ins_encode( emit_br_nop ); | |
| 5419 ins_pipe(br_nop); | |
| 5420 %} | |
| 5421 | |
| 5422 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5423 //----------Load Instructions-------------------------------------------------- | |
| 5424 // Load Byte (8bit signed) | |
| 5425 instruct loadB(iRegI dst, memory mem) %{ | |
| 5426 match(Set dst (LoadB mem)); | |
| 5427 ins_cost(MEMORY_REF_COST); | |
| 5428 | |
| 5429 size(4); | |
| 624 | 5430 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5431 ins_encode %{ |
| 5432 __ ldsb($mem$$Address, $dst$$Register); | |
| 5433 %} | |
| 624 | 5434 ins_pipe(iload_mask_mem); |
| 5435 %} | |
| 5436 | |
| 5437 // Load Byte (8bit signed) into a Long Register | |
| 5438 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5439 match(Set dst (ConvI2L (LoadB mem))); | |
| 5440 ins_cost(MEMORY_REF_COST); | |
| 5441 | |
| 5442 size(4); | |
| 5443 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5444 ins_encode %{ |
| 5445 __ ldsb($mem$$Address, $dst$$Register); | |
| 5446 %} | |
| 0 | 5447 ins_pipe(iload_mask_mem); |
| 5448 %} | |
| 5449 | |
| 624 | 5450 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5451 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5452 match(Set dst (LoadUB mem)); | |
| 0 | 5453 ins_cost(MEMORY_REF_COST); |
| 5454 | |
| 5455 size(4); | |
| 624 | 5456 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5457 ins_encode %{ |
| 5458 __ ldub($mem$$Address, $dst$$Register); | |
| 5459 %} | |
| 824 | 5460 ins_pipe(iload_mem); |
| 624 | 5461 %} |
| 5462 | |
| 5463 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5464 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5465 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5466 ins_cost(MEMORY_REF_COST); | |
| 5467 | |
| 5468 size(4); | |
| 5469 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5470 ins_encode %{ |
| 5471 __ ldub($mem$$Address, $dst$$Register); | |
| 5472 %} | |
| 824 | 5473 ins_pipe(iload_mem); |
| 5474 %} | |
| 5475 | |
| 5476 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5477 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5478 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5479 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5480 | |
| 5481 size(2*4); | |
| 5482 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5483 "AND $dst,$mask,$dst" %} | |
| 5484 ins_encode %{ | |
| 5485 __ ldub($mem$$Address, $dst$$Register); | |
| 5486 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5487 %} | |
| 5488 ins_pipe(iload_mem); | |
| 0 | 5489 %} |
| 5490 | |
| 624 | 5491 // Load Short (16bit signed) |
| 5492 instruct loadS(iRegI dst, memory mem) %{ | |
| 5493 match(Set dst (LoadS mem)); | |
| 5494 ins_cost(MEMORY_REF_COST); | |
| 5495 | |
| 5496 size(4); | |
| 5497 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5498 ins_encode %{ |
| 5499 __ ldsh($mem$$Address, $dst$$Register); | |
| 5500 %} | |
| 624 | 5501 ins_pipe(iload_mask_mem); |
| 5502 %} | |
| 5503 | |
| 785 | 5504 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5505 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5506 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5507 ins_cost(MEMORY_REF_COST); | |
| 5508 | |
| 5509 size(4); | |
| 5510 | |
| 5511 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5512 ins_encode %{ | |
| 5513 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5514 %} | |
| 5515 ins_pipe(iload_mask_mem); | |
| 5516 %} | |
| 5517 | |
| 624 | 5518 // Load Short (16bit signed) into a Long Register |
| 5519 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5520 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5521 ins_cost(MEMORY_REF_COST); |
| 5522 | |
| 5523 size(4); | |
| 624 | 5524 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5525 ins_encode %{ |
| 5526 __ ldsh($mem$$Address, $dst$$Register); | |
| 5527 %} | |
| 624 | 5528 ins_pipe(iload_mask_mem); |
| 5529 %} | |
| 5530 | |
| 5531 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5532 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5533 match(Set dst (LoadUS mem)); | |
| 5534 ins_cost(MEMORY_REF_COST); | |
| 5535 | |
| 5536 size(4); | |
| 5537 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5538 ins_encode %{ |
| 5539 __ lduh($mem$$Address, $dst$$Register); | |
| 5540 %} | |
| 824 | 5541 ins_pipe(iload_mem); |
| 0 | 5542 %} |
| 5543 | |
| 785 | 5544 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5545 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5546 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5547 ins_cost(MEMORY_REF_COST); | |
| 5548 | |
| 5549 size(4); | |
| 5550 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5551 ins_encode %{ | |
| 5552 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5553 %} | |
| 5554 ins_pipe(iload_mask_mem); | |
| 5555 %} | |
| 5556 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
5557 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5558 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5559 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5560 ins_cost(MEMORY_REF_COST); |
| 5561 | |
| 5562 size(4); | |
| 624 | 5563 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5564 ins_encode %{ |
| 5565 __ lduh($mem$$Address, $dst$$Register); | |
| 5566 %} | |
| 824 | 5567 ins_pipe(iload_mem); |
| 5568 %} | |
| 5569 | |
| 5570 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5571 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5572 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5573 ins_cost(MEMORY_REF_COST); | |
| 5574 | |
| 5575 size(4); | |
| 5576 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5577 ins_encode %{ | |
| 5578 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5579 %} | |
| 5580 ins_pipe(iload_mem); | |
| 5581 %} | |
| 5582 | |
| 5583 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5584 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5585 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5586 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5587 | |
| 5588 size(2*4); | |
| 5589 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5590 "AND $dst,$mask,$dst" %} | |
| 5591 ins_encode %{ | |
| 5592 Register Rdst = $dst$$Register; | |
| 5593 __ lduh($mem$$Address, Rdst); | |
| 5594 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5595 %} | |
| 5596 ins_pipe(iload_mem); | |
| 5597 %} | |
| 5598 | |
| 5599 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5600 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5601 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5602 effect(TEMP dst, TEMP tmp); | |
| 5603 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5604 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5605 size((3+1)*4); // set may use two instructions. |
| 824 | 5606 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5607 "SET $mask,$tmp\n\t" | |
| 5608 "AND $dst,$tmp,$dst" %} | |
| 5609 ins_encode %{ | |
| 5610 Register Rdst = $dst$$Register; | |
| 5611 Register Rtmp = $tmp$$Register; | |
| 5612 __ lduh($mem$$Address, Rdst); | |
| 5613 __ set($mask$$constant, Rtmp); | |
| 5614 __ and3(Rdst, Rtmp, Rdst); | |
| 5615 %} | |
| 5616 ins_pipe(iload_mem); | |
| 0 | 5617 %} |
| 5618 | |
| 5619 // Load Integer | |
| 5620 instruct loadI(iRegI dst, memory mem) %{ | |
| 5621 match(Set dst (LoadI mem)); | |
| 5622 ins_cost(MEMORY_REF_COST); | |
| 624 | 5623 |
| 5624 size(4); | |
| 5625 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5626 ins_encode %{ |
| 5627 __ lduw($mem$$Address, $dst$$Register); | |
| 5628 %} | |
| 624 | 5629 ins_pipe(iload_mem); |
| 5630 %} | |
| 5631 | |
| 785 | 5632 // Load Integer to Byte (8 bit signed) |
| 5633 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5634 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5635 ins_cost(MEMORY_REF_COST); | |
| 5636 | |
| 5637 size(4); | |
| 5638 | |
| 5639 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5640 ins_encode %{ | |
| 5641 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5642 %} | |
| 5643 ins_pipe(iload_mask_mem); | |
| 5644 %} | |
| 5645 | |
| 5646 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5647 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5648 match(Set dst (AndI (LoadI mem) mask)); | |
| 5649 ins_cost(MEMORY_REF_COST); | |
| 5650 | |
| 5651 size(4); | |
| 5652 | |
| 5653 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5654 ins_encode %{ | |
| 5655 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5656 %} | |
| 5657 ins_pipe(iload_mask_mem); | |
| 5658 %} | |
| 5659 | |
| 5660 // Load Integer to Short (16 bit signed) | |
| 5661 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5662 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5663 ins_cost(MEMORY_REF_COST); | |
| 5664 | |
| 5665 size(4); | |
| 5666 | |
| 5667 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5668 ins_encode %{ | |
| 5669 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5670 %} | |
| 5671 ins_pipe(iload_mask_mem); | |
| 5672 %} | |
| 5673 | |
| 5674 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5675 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5676 match(Set dst (AndI (LoadI mem) mask)); | |
| 5677 ins_cost(MEMORY_REF_COST); | |
| 5678 | |
| 5679 size(4); | |
| 5680 | |
| 5681 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5682 ins_encode %{ | |
| 5683 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5684 %} | |
| 5685 ins_pipe(iload_mask_mem); | |
| 5686 %} | |
| 5687 | |
| 624 | 5688 // Load Integer into a Long Register |
| 5689 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5690 match(Set dst (ConvI2L (LoadI mem))); | |
| 5691 ins_cost(MEMORY_REF_COST); | |
| 5692 | |
| 5693 size(4); | |
| 5694 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5695 ins_encode %{ |
| 5696 __ ldsw($mem$$Address, $dst$$Register); | |
| 5697 %} | |
| 824 | 5698 ins_pipe(iload_mask_mem); |
| 5699 %} | |
| 5700 | |
| 5701 // Load Integer with mask 0xFF into a Long Register | |
| 5702 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5703 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5704 ins_cost(MEMORY_REF_COST); | |
| 5705 | |
| 5706 size(4); | |
| 5707 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5708 ins_encode %{ | |
| 5709 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5710 %} | |
| 5711 ins_pipe(iload_mem); | |
| 5712 %} | |
| 5713 | |
| 5714 // Load Integer with mask 0xFFFF into a Long Register | |
| 5715 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5716 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5717 ins_cost(MEMORY_REF_COST); | |
| 5718 | |
| 5719 size(4); | |
| 5720 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5721 ins_encode %{ | |
| 5722 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5723 %} | |
| 5724 ins_pipe(iload_mem); | |
| 5725 %} | |
| 5726 | |
| 5727 // Load Integer with a 13-bit mask into a Long Register | |
| 5728 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5729 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5730 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5731 | |
| 5732 size(2*4); | |
| 5733 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5734 "AND $dst,$mask,$dst" %} | |
| 5735 ins_encode %{ | |
| 5736 Register Rdst = $dst$$Register; | |
| 5737 __ lduw($mem$$Address, Rdst); | |
| 5738 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5739 %} | |
| 5740 ins_pipe(iload_mem); | |
| 5741 %} | |
| 5742 | |
| 5743 // Load Integer with a 32-bit mask into a Long Register | |
| 5744 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5745 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5746 effect(TEMP dst, TEMP tmp); | |
| 5747 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5748 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5749 size((3+1)*4); // set may use two instructions. |
| 824 | 5750 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5751 "SET $mask,$tmp\n\t" | |
| 5752 "AND $dst,$tmp,$dst" %} | |
| 5753 ins_encode %{ | |
| 5754 Register Rdst = $dst$$Register; | |
| 5755 Register Rtmp = $tmp$$Register; | |
| 5756 __ lduw($mem$$Address, Rdst); | |
| 5757 __ set($mask$$constant, Rtmp); | |
| 5758 __ and3(Rdst, Rtmp, Rdst); | |
| 5759 %} | |
| 624 | 5760 ins_pipe(iload_mem); |
| 5761 %} | |
| 5762 | |
| 5763 // Load Unsigned Integer into a Long Register | |
| 5764 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5765 match(Set dst (LoadUI2L mem)); | |
| 5766 ins_cost(MEMORY_REF_COST); | |
| 5767 | |
| 5768 size(4); | |
| 5769 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5770 ins_encode %{ |
| 5771 __ lduw($mem$$Address, $dst$$Register); | |
| 5772 %} | |
| 0 | 5773 ins_pipe(iload_mem); |
| 5774 %} | |
| 5775 | |
| 5776 // Load Long - aligned | |
| 5777 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5778 match(Set dst (LoadL mem)); | |
| 5779 ins_cost(MEMORY_REF_COST); | |
| 624 | 5780 |
| 0 | 5781 size(4); |
| 5782 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5783 ins_encode %{ |
| 5784 __ ldx($mem$$Address, $dst$$Register); | |
| 5785 %} | |
| 0 | 5786 ins_pipe(iload_mem); |
| 5787 %} | |
| 5788 | |
| 5789 // Load Long - UNaligned | |
| 5790 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5791 match(Set dst (LoadL_unaligned mem)); | |
| 5792 effect(KILL tmp); | |
| 5793 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5794 size(16); | |
| 5795 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5796 "\tLDUW $mem ,$dst\n" | |
| 5797 "\tSLLX #32, $dst, $dst\n" | |
| 5798 "\tOR $dst, R_O7, $dst" %} | |
| 5799 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5800 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5801 ins_pipe(iload_mem); |
| 5802 %} | |
| 5803 | |
| 5804 // Load Aligned Packed Byte into a Double Register | |
| 5805 instruct loadA8B(regD dst, memory mem) %{ | |
| 5806 match(Set dst (Load8B mem)); | |
| 5807 ins_cost(MEMORY_REF_COST); | |
| 5808 size(4); | |
| 5809 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5810 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5811 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5812 ins_pipe(floadD_mem); |
| 5813 %} | |
| 5814 | |
| 5815 // Load Aligned Packed Char into a Double Register | |
| 5816 instruct loadA4C(regD dst, memory mem) %{ | |
| 5817 match(Set dst (Load4C mem)); | |
| 5818 ins_cost(MEMORY_REF_COST); | |
| 5819 size(4); | |
| 5820 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5821 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5822 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5823 ins_pipe(floadD_mem); |
| 5824 %} | |
| 5825 | |
| 5826 // Load Aligned Packed Short into a Double Register | |
| 5827 instruct loadA4S(regD dst, memory mem) %{ | |
| 5828 match(Set dst (Load4S mem)); | |
| 5829 ins_cost(MEMORY_REF_COST); | |
| 5830 size(4); | |
| 5831 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5832 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5833 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5834 ins_pipe(floadD_mem); |
| 5835 %} | |
| 5836 | |
| 5837 // Load Aligned Packed Int into a Double Register | |
| 5838 instruct loadA2I(regD dst, memory mem) %{ | |
| 5839 match(Set dst (Load2I mem)); | |
| 5840 ins_cost(MEMORY_REF_COST); | |
| 5841 size(4); | |
| 5842 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5843 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5844 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5845 ins_pipe(floadD_mem); |
| 5846 %} | |
| 5847 | |
| 5848 // Load Range | |
| 5849 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5850 match(Set dst (LoadRange mem)); | |
| 5851 ins_cost(MEMORY_REF_COST); | |
| 5852 | |
| 5853 size(4); | |
| 5854 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5855 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5856 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5857 ins_pipe(iload_mem); |
| 5858 %} | |
| 5859 | |
| 5860 // Load Integer into %f register (for fitos/fitod) | |
| 5861 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5862 match(Set dst (LoadI mem)); | |
| 5863 ins_cost(MEMORY_REF_COST); | |
| 5864 size(4); | |
| 5865 | |
| 5866 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5867 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5868 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5869 ins_pipe(floadF_mem); |
| 5870 %} | |
| 5871 | |
| 5872 // Load Pointer | |
| 5873 instruct loadP(iRegP dst, memory mem) %{ | |
| 5874 match(Set dst (LoadP mem)); | |
| 5875 ins_cost(MEMORY_REF_COST); | |
| 5876 size(4); | |
| 5877 | |
| 5878 #ifndef _LP64 | |
| 5879 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5880 ins_encode %{ |
| 5881 __ lduw($mem$$Address, $dst$$Register); | |
| 5882 %} | |
| 0 | 5883 #else |
| 5884 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5885 ins_encode %{ |
| 5886 __ ldx($mem$$Address, $dst$$Register); | |
| 5887 %} | |
| 0 | 5888 #endif |
| 5889 ins_pipe(iload_mem); | |
| 5890 %} | |
| 5891 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5892 // Load Compressed Pointer |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5893 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5894 match(Set dst (LoadN mem)); |
| 5895 ins_cost(MEMORY_REF_COST); | |
| 5896 size(4); | |
| 5897 | |
| 5898 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5899 ins_encode %{ | |
| 5900 __ lduw($mem$$Address, $dst$$Register); | |
| 5901 %} | |
| 5902 ins_pipe(iload_mem); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5903 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5904 |
| 0 | 5905 // Load Klass Pointer |
| 5906 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5907 match(Set dst (LoadKlass mem)); | |
| 5908 ins_cost(MEMORY_REF_COST); | |
| 5909 size(4); | |
| 5910 | |
| 5911 #ifndef _LP64 | |
| 5912 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 5913 ins_encode %{ |
| 5914 __ lduw($mem$$Address, $dst$$Register); | |
| 5915 %} | |
| 0 | 5916 #else |
| 5917 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 5918 ins_encode %{ |
| 5919 __ ldx($mem$$Address, $dst$$Register); | |
| 5920 %} | |
| 0 | 5921 #endif |
| 5922 ins_pipe(iload_mem); | |
| 5923 %} | |
| 5924 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5925 // Load narrow Klass Pointer |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5926 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5927 match(Set dst (LoadNKlass mem)); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5928 ins_cost(MEMORY_REF_COST); |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
164
diff
changeset
|
5929 size(4); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5930 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5931 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5932 ins_encode %{ |
| 727 | 5933 __ lduw($mem$$Address, $dst$$Register); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5934 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5935 ins_pipe(iload_mem); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5936 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5937 |
| 0 | 5938 // Load Double |
| 5939 instruct loadD(regD dst, memory mem) %{ | |
| 5940 match(Set dst (LoadD mem)); | |
| 5941 ins_cost(MEMORY_REF_COST); | |
| 5942 | |
| 5943 size(4); | |
| 5944 format %{ "LDDF $mem,$dst" %} | |
| 5945 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5946 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5947 ins_pipe(floadD_mem); |
| 5948 %} | |
| 5949 | |
| 5950 // Load Double - UNaligned | |
| 5951 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 5952 match(Set dst (LoadD_unaligned mem)); | |
| 5953 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5954 size(8); | |
| 5955 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 5956 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 5957 opcode(Assembler::ldf_op3); | |
| 5958 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 5959 ins_pipe(iload_mem); | |
| 5960 %} | |
| 5961 | |
| 5962 // Load Float | |
| 5963 instruct loadF(regF dst, memory mem) %{ | |
| 5964 match(Set dst (LoadF mem)); | |
| 5965 ins_cost(MEMORY_REF_COST); | |
| 5966 | |
| 5967 size(4); | |
| 5968 format %{ "LDF $mem,$dst" %} | |
| 5969 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5970 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5971 ins_pipe(floadF_mem); |
| 5972 %} | |
| 5973 | |
| 5974 // Load Constant | |
| 5975 instruct loadConI( iRegI dst, immI src ) %{ | |
| 5976 match(Set dst src); | |
| 5977 ins_cost(DEFAULT_COST * 3/2); | |
| 5978 format %{ "SET $src,$dst" %} | |
| 5979 ins_encode( Set32(src, dst) ); | |
| 5980 ins_pipe(ialu_hi_lo_reg); | |
| 5981 %} | |
| 5982 | |
| 5983 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 5984 match(Set dst src); | |
| 5985 | |
| 5986 size(4); | |
| 5987 format %{ "MOV $src,$dst" %} | |
| 5988 ins_encode( Set13( src, dst ) ); | |
| 5989 ins_pipe(ialu_imm); | |
| 5990 %} | |
| 5991 | |
| 5992 instruct loadConP(iRegP dst, immP src) %{ | |
| 5993 match(Set dst src); | |
| 5994 ins_cost(DEFAULT_COST * 3/2); | |
| 5995 format %{ "SET $src,$dst\t!ptr" %} | |
| 5996 // This rule does not use "expand" unlike loadConI because then | |
| 5997 // the result type is not known to be an Oop. An ADLC | |
| 5998 // enhancement will be needed to make that work - not worth it! | |
| 5999 | |
| 6000 ins_encode( SetPtr( src, dst ) ); | |
| 6001 ins_pipe(loadConP); | |
| 6002 | |
| 6003 %} | |
| 6004 | |
| 6005 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6006 match(Set dst src); | |
| 6007 | |
| 6008 size(4); | |
| 6009 format %{ "CLR $dst\t!ptr" %} | |
| 6010 ins_encode( SetNull( dst ) ); | |
| 6011 ins_pipe(ialu_imm); | |
| 6012 %} | |
| 6013 | |
| 6014 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6015 match(Set dst src); | |
| 6016 ins_cost(DEFAULT_COST); | |
| 6017 format %{ "SET $src,$dst\t!ptr" %} | |
| 6018 ins_encode %{ | |
| 727 | 6019 AddressLiteral polling_page(os::get_polling_page()); |
| 6020 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6021 %} |
| 6022 ins_pipe(loadConP_poll); | |
| 6023 %} | |
| 6024 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6025 instruct loadConN0(iRegN dst, immN0 src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6026 match(Set dst src); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6027 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6028 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6029 format %{ "CLR $dst\t! compressed NULL ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6030 ins_encode( SetNull( dst ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6031 ins_pipe(ialu_imm); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6032 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6033 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6034 instruct loadConN(iRegN dst, immN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6035 match(Set dst src); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6036 ins_cost(DEFAULT_COST * 3/2); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6037 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6038 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6039 Register dst = $dst$$Register; |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6040 __ set_narrow_oop((jobject)$src$$constant, dst); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6041 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6042 ins_pipe(ialu_hi_lo_reg); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6043 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6044 |
| 0 | 6045 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
| 6046 // %%% maybe this should work like loadConD | |
| 6047 match(Set dst src); | |
| 6048 effect(KILL tmp); | |
| 6049 ins_cost(DEFAULT_COST * 4); | |
| 6050 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
| 6051 ins_encode( LdImmL(src, dst, tmp) ); | |
| 6052 ins_pipe(loadConL); | |
| 6053 %} | |
| 6054 | |
| 6055 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6056 match(Set dst src); | |
| 6057 ins_cost(DEFAULT_COST); | |
| 6058 size(4); | |
| 6059 format %{ "CLR $dst\t! long" %} | |
| 6060 ins_encode( Set13( src, dst ) ); | |
| 6061 ins_pipe(ialu_imm); | |
| 6062 %} | |
| 6063 | |
| 6064 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6065 match(Set dst src); | |
| 6066 ins_cost(DEFAULT_COST * 2); | |
| 6067 | |
| 6068 size(4); | |
| 6069 format %{ "MOV $src,$dst\t! long" %} | |
| 6070 ins_encode( Set13( src, dst ) ); | |
| 6071 ins_pipe(ialu_imm); | |
| 6072 %} | |
| 6073 | |
| 6074 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
| 6075 match(Set dst src); | |
| 6076 effect(KILL tmp); | |
| 6077 | |
| 6078 #ifdef _LP64 | |
| 727 | 6079 size(8*4); |
| 0 | 6080 #else |
| 727 | 6081 size(2*4); |
| 0 | 6082 #endif |
| 6083 | |
| 6084 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
| 6085 "LDF [$tmp+lo(&$src)],$dst" %} | |
| 727 | 6086 ins_encode %{ |
| 6087 address float_address = __ float_constant($src$$constant); | |
| 6088 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
| 6089 AddressLiteral addrlit(float_address, rspec); | |
| 6090 | |
| 6091 __ sethi(addrlit, $tmp$$Register); | |
| 6092 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); | |
| 6093 %} | |
| 0 | 6094 ins_pipe(loadConFD); |
| 6095 %} | |
| 6096 | |
| 6097 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
| 6098 match(Set dst src); | |
| 6099 effect(KILL tmp); | |
| 6100 | |
| 6101 #ifdef _LP64 | |
| 727 | 6102 size(8*4); |
| 0 | 6103 #else |
| 727 | 6104 size(2*4); |
| 0 | 6105 #endif |
| 6106 | |
| 6107 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
| 6108 "LDDF [$tmp+lo(&$src)],$dst" %} | |
| 727 | 6109 ins_encode %{ |
| 6110 address double_address = __ double_constant($src$$constant); | |
| 6111 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
| 6112 AddressLiteral addrlit(double_address, rspec); | |
| 6113 | |
| 6114 __ sethi(addrlit, $tmp$$Register); | |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6115 // XXX This is a quick fix for 6833573. |
|
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6116 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
|
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6117 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
| 727 | 6118 %} |
| 0 | 6119 ins_pipe(loadConFD); |
| 6120 %} | |
| 6121 | |
| 6122 // Prefetch instructions. | |
| 6123 // Must be safe to execute with invalid address (cannot fault). | |
| 6124 | |
| 6125 instruct prefetchr( memory mem ) %{ | |
| 6126 match( PrefetchRead mem ); | |
| 6127 ins_cost(MEMORY_REF_COST); | |
| 6128 | |
| 6129 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6130 opcode(Assembler::prefetch_op3); | |
| 6131 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6132 ins_pipe(iload_mem); | |
| 6133 %} | |
| 6134 | |
| 6135 instruct prefetchw( memory mem ) %{ | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6136 predicate(AllocatePrefetchStyle != 3 ); |
| 0 | 6137 match( PrefetchWrite mem ); |
| 6138 ins_cost(MEMORY_REF_COST); | |
| 6139 | |
| 6140 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6141 opcode(Assembler::prefetch_op3); | |
| 6142 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6143 ins_pipe(iload_mem); | |
| 6144 %} | |
| 6145 | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6146 // Use BIS instruction to prefetch. |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6147 instruct prefetchw_bis( memory mem ) %{ |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6148 predicate(AllocatePrefetchStyle == 3); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6149 match( PrefetchWrite mem ); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6150 ins_cost(MEMORY_REF_COST); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6151 |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6152 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6153 ins_encode %{ |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6154 Register base = as_Register($mem$$base); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6155 int disp = $mem$$disp; |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6156 if (disp != 0) { |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6157 __ add(base, AllocatePrefetchStepSize, base); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6158 } |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6159 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6160 %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6161 ins_pipe(istore_mem_reg); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6162 %} |
| 0 | 6163 |
| 6164 //----------Store Instructions------------------------------------------------- | |
| 6165 // Store Byte | |
| 6166 instruct storeB(memory mem, iRegI src) %{ | |
| 6167 match(Set mem (StoreB mem src)); | |
| 6168 ins_cost(MEMORY_REF_COST); | |
| 6169 | |
| 6170 size(4); | |
| 6171 format %{ "STB $src,$mem\t! byte" %} | |
| 6172 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6173 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6174 ins_pipe(istore_mem_reg); |
| 6175 %} | |
| 6176 | |
| 6177 instruct storeB0(memory mem, immI0 src) %{ | |
| 6178 match(Set mem (StoreB mem src)); | |
| 6179 ins_cost(MEMORY_REF_COST); | |
| 6180 | |
| 6181 size(4); | |
| 6182 format %{ "STB $src,$mem\t! byte" %} | |
| 6183 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6184 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6185 ins_pipe(istore_mem_zero); |
| 6186 %} | |
| 6187 | |
| 6188 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6189 match(Set mem (StoreCM mem src)); | |
| 6190 ins_cost(MEMORY_REF_COST); | |
| 6191 | |
| 6192 size(4); | |
| 6193 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6194 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6195 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6196 ins_pipe(istore_mem_zero); |
| 6197 %} | |
| 6198 | |
| 6199 // Store Char/Short | |
| 6200 instruct storeC(memory mem, iRegI src) %{ | |
| 6201 match(Set mem (StoreC mem src)); | |
| 6202 ins_cost(MEMORY_REF_COST); | |
| 6203 | |
| 6204 size(4); | |
| 6205 format %{ "STH $src,$mem\t! short" %} | |
| 6206 opcode(Assembler::sth_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6207 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6208 ins_pipe(istore_mem_reg); |
| 6209 %} | |
| 6210 | |
| 6211 instruct storeC0(memory mem, immI0 src) %{ | |
| 6212 match(Set mem (StoreC mem src)); | |
| 6213 ins_cost(MEMORY_REF_COST); | |
| 6214 | |
| 6215 size(4); | |
| 6216 format %{ "STH $src,$mem\t! short" %} | |
| 6217 opcode(Assembler::sth_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6218 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6219 ins_pipe(istore_mem_zero); |
| 6220 %} | |
| 6221 | |
| 6222 // Store Integer | |
| 6223 instruct storeI(memory mem, iRegI src) %{ | |
| 6224 match(Set mem (StoreI mem src)); | |
| 6225 ins_cost(MEMORY_REF_COST); | |
| 6226 | |
| 6227 size(4); | |
| 6228 format %{ "STW $src,$mem" %} | |
| 6229 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6230 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6231 ins_pipe(istore_mem_reg); |
| 6232 %} | |
| 6233 | |
| 6234 // Store Long | |
| 6235 instruct storeL(memory mem, iRegL src) %{ | |
| 6236 match(Set mem (StoreL mem src)); | |
| 6237 ins_cost(MEMORY_REF_COST); | |
| 6238 size(4); | |
| 6239 format %{ "STX $src,$mem\t! long" %} | |
| 6240 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6241 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6242 ins_pipe(istore_mem_reg); |
| 6243 %} | |
| 6244 | |
| 6245 instruct storeI0(memory mem, immI0 src) %{ | |
| 6246 match(Set mem (StoreI mem src)); | |
| 6247 ins_cost(MEMORY_REF_COST); | |
| 6248 | |
| 6249 size(4); | |
| 6250 format %{ "STW $src,$mem" %} | |
| 6251 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6252 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6253 ins_pipe(istore_mem_zero); |
| 6254 %} | |
| 6255 | |
| 6256 instruct storeL0(memory mem, immL0 src) %{ | |
| 6257 match(Set mem (StoreL mem src)); | |
| 6258 ins_cost(MEMORY_REF_COST); | |
| 6259 | |
| 6260 size(4); | |
| 6261 format %{ "STX $src,$mem" %} | |
| 6262 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6263 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6264 ins_pipe(istore_mem_zero); |
| 6265 %} | |
| 6266 | |
| 6267 // Store Integer from float register (used after fstoi) | |
| 6268 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6269 match(Set mem (StoreI mem src)); | |
| 6270 ins_cost(MEMORY_REF_COST); | |
| 6271 | |
| 6272 size(4); | |
| 6273 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6274 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6275 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6276 ins_pipe(fstoreF_mem_reg); |
| 6277 %} | |
| 6278 | |
| 6279 // Store Pointer | |
| 6280 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6281 match(Set dst (StoreP dst src)); | |
| 6282 ins_cost(MEMORY_REF_COST); | |
| 6283 size(4); | |
| 6284 | |
| 6285 #ifndef _LP64 | |
| 6286 format %{ "STW $src,$dst\t! ptr" %} | |
| 6287 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6288 #else | |
| 6289 format %{ "STX $src,$dst\t! ptr" %} | |
| 6290 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6291 #endif | |
| 6292 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6293 ins_pipe(istore_mem_spORreg); | |
| 6294 %} | |
| 6295 | |
| 6296 instruct storeP0(memory dst, immP0 src) %{ | |
| 6297 match(Set dst (StoreP dst src)); | |
| 6298 ins_cost(MEMORY_REF_COST); | |
| 6299 size(4); | |
| 6300 | |
| 6301 #ifndef _LP64 | |
| 6302 format %{ "STW $src,$dst\t! ptr" %} | |
| 6303 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6304 #else | |
| 6305 format %{ "STX $src,$dst\t! ptr" %} | |
| 6306 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6307 #endif | |
| 6308 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6309 ins_pipe(istore_mem_zero); | |
| 6310 %} | |
| 6311 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6312 // Store Compressed Pointer |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6313 instruct storeN(memory dst, iRegN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6314 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6315 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6316 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6317 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6318 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6319 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6320 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6321 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6322 Register src = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6323 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6324 __ stw(src, base, index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6325 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6326 __ stw(src, base, $dst$$disp); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6327 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6328 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6329 ins_pipe(istore_mem_spORreg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6330 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6331 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6332 instruct storeN0(memory dst, immN0 src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6333 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6334 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6335 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6336 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6337 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6338 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6339 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6340 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6341 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6342 __ stw(0, base, index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6343 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6344 __ stw(0, base, $dst$$disp); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6345 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6346 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6347 ins_pipe(istore_mem_zero); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6348 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6349 |
| 0 | 6350 // Store Double |
| 6351 instruct storeD( memory mem, regD src) %{ | |
| 6352 match(Set mem (StoreD mem src)); | |
| 6353 ins_cost(MEMORY_REF_COST); | |
| 6354 | |
| 6355 size(4); | |
| 6356 format %{ "STDF $src,$mem" %} | |
| 6357 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6358 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6359 ins_pipe(fstoreD_mem_reg); |
| 6360 %} | |
| 6361 | |
| 6362 instruct storeD0( memory mem, immD0 src) %{ | |
| 6363 match(Set mem (StoreD mem src)); | |
| 6364 ins_cost(MEMORY_REF_COST); | |
| 6365 | |
| 6366 size(4); | |
| 6367 format %{ "STX $src,$mem" %} | |
| 6368 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6369 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6370 ins_pipe(fstoreD_mem_zero); |
| 6371 %} | |
| 6372 | |
| 6373 // Store Float | |
| 6374 instruct storeF( memory mem, regF src) %{ | |
| 6375 match(Set mem (StoreF mem src)); | |
| 6376 ins_cost(MEMORY_REF_COST); | |
| 6377 | |
| 6378 size(4); | |
| 6379 format %{ "STF $src,$mem" %} | |
| 6380 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6381 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6382 ins_pipe(fstoreF_mem_reg); |
| 6383 %} | |
| 6384 | |
| 6385 instruct storeF0( memory mem, immF0 src) %{ | |
| 6386 match(Set mem (StoreF mem src)); | |
| 6387 ins_cost(MEMORY_REF_COST); | |
| 6388 | |
| 6389 size(4); | |
| 6390 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6391 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6392 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6393 ins_pipe(fstoreF_mem_zero); |
| 6394 %} | |
| 6395 | |
| 6396 // Store Aligned Packed Bytes in Double register to memory | |
| 6397 instruct storeA8B(memory mem, regD src) %{ | |
| 6398 match(Set mem (Store8B mem src)); | |
| 6399 ins_cost(MEMORY_REF_COST); | |
| 6400 size(4); | |
| 6401 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 6402 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6403 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6404 ins_pipe(fstoreD_mem_reg); |
| 6405 %} | |
| 6406 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6407 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6408 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6409 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6410 match(Set dst (EncodeP src)); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6411 format %{ "encode_heap_oop $src, $dst" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6412 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6413 __ encode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6414 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6415 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6416 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6417 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6418 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6419 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6420 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6421 format %{ "encode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6422 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6423 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6424 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6425 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6426 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6427 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6428 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6429 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6430 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6431 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6432 format %{ "decode_heap_oop $src, $dst" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6433 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6434 __ decode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6435 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6436 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6437 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6438 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6439 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6440 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6441 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6442 match(Set dst (DecodeN src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6443 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6444 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6445 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6446 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6447 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6448 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6449 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6450 |
| 0 | 6451 // Store Zero into Aligned Packed Bytes |
| 6452 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6453 match(Set mem (Store8B mem zero)); | |
| 6454 ins_cost(MEMORY_REF_COST); | |
| 6455 size(4); | |
| 6456 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6457 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6458 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6459 ins_pipe(fstoreD_mem_zero); |
| 6460 %} | |
| 6461 | |
| 6462 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6463 instruct storeA4C(memory mem, regD src) %{ | |
| 6464 match(Set mem (Store4C mem src)); | |
| 6465 ins_cost(MEMORY_REF_COST); | |
| 6466 size(4); | |
| 6467 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6468 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6469 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6470 ins_pipe(fstoreD_mem_reg); |
| 6471 %} | |
| 6472 | |
| 6473 // Store Zero into Aligned Packed Chars/Shorts | |
| 6474 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6475 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6476 ins_cost(MEMORY_REF_COST); | |
| 6477 size(4); | |
| 6478 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6479 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6480 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6481 ins_pipe(fstoreD_mem_zero); |
| 6482 %} | |
| 6483 | |
| 6484 // Store Aligned Packed Ints in Double register to memory | |
| 6485 instruct storeA2I(memory mem, regD src) %{ | |
| 6486 match(Set mem (Store2I mem src)); | |
| 6487 ins_cost(MEMORY_REF_COST); | |
| 6488 size(4); | |
| 6489 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6490 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6491 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6492 ins_pipe(fstoreD_mem_reg); |
| 6493 %} | |
| 6494 | |
| 6495 // Store Zero into Aligned Packed Ints | |
| 6496 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6497 match(Set mem (Store2I mem zero)); | |
| 6498 ins_cost(MEMORY_REF_COST); | |
| 6499 size(4); | |
| 6500 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6501 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6502 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6503 ins_pipe(fstoreD_mem_zero); |
| 6504 %} | |
| 6505 | |
| 6506 | |
| 6507 //----------MemBar Instructions----------------------------------------------- | |
| 6508 // Memory barrier flavors | |
| 6509 | |
| 6510 instruct membar_acquire() %{ | |
| 6511 match(MemBarAcquire); | |
| 6512 ins_cost(4*MEMORY_REF_COST); | |
| 6513 | |
| 6514 size(0); | |
| 6515 format %{ "MEMBAR-acquire" %} | |
| 6516 ins_encode( enc_membar_acquire ); | |
| 6517 ins_pipe(long_memory_op); | |
| 6518 %} | |
| 6519 | |
| 6520 instruct membar_acquire_lock() %{ | |
| 6521 match(MemBarAcquire); | |
| 6522 predicate(Matcher::prior_fast_lock(n)); | |
| 6523 ins_cost(0); | |
| 6524 | |
| 6525 size(0); | |
| 6526 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6527 ins_encode( ); | |
| 6528 ins_pipe(empty); | |
| 6529 %} | |
| 6530 | |
| 6531 instruct membar_release() %{ | |
| 6532 match(MemBarRelease); | |
| 6533 ins_cost(4*MEMORY_REF_COST); | |
| 6534 | |
| 6535 size(0); | |
| 6536 format %{ "MEMBAR-release" %} | |
| 6537 ins_encode( enc_membar_release ); | |
| 6538 ins_pipe(long_memory_op); | |
| 6539 %} | |
| 6540 | |
| 6541 instruct membar_release_lock() %{ | |
| 6542 match(MemBarRelease); | |
| 6543 predicate(Matcher::post_fast_unlock(n)); | |
| 6544 ins_cost(0); | |
| 6545 | |
| 6546 size(0); | |
| 6547 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6548 ins_encode( ); | |
| 6549 ins_pipe(empty); | |
| 6550 %} | |
| 6551 | |
| 6552 instruct membar_volatile() %{ | |
| 6553 match(MemBarVolatile); | |
| 6554 ins_cost(4*MEMORY_REF_COST); | |
| 6555 | |
| 6556 size(4); | |
| 6557 format %{ "MEMBAR-volatile" %} | |
| 6558 ins_encode( enc_membar_volatile ); | |
| 6559 ins_pipe(long_memory_op); | |
| 6560 %} | |
| 6561 | |
| 6562 instruct unnecessary_membar_volatile() %{ | |
| 6563 match(MemBarVolatile); | |
| 6564 predicate(Matcher::post_store_load_barrier(n)); | |
| 6565 ins_cost(0); | |
| 6566 | |
| 6567 size(0); | |
| 6568 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6569 ins_encode( ); | |
| 6570 ins_pipe(empty); | |
| 6571 %} | |
| 6572 | |
| 6573 //----------Register Move Instructions----------------------------------------- | |
| 6574 instruct roundDouble_nop(regD dst) %{ | |
| 6575 match(Set dst (RoundDouble dst)); | |
| 6576 ins_cost(0); | |
| 6577 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6578 ins_encode( ); | |
| 6579 ins_pipe(empty); | |
| 6580 %} | |
| 6581 | |
| 6582 | |
| 6583 instruct roundFloat_nop(regF dst) %{ | |
| 6584 match(Set dst (RoundFloat dst)); | |
| 6585 ins_cost(0); | |
| 6586 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6587 ins_encode( ); | |
| 6588 ins_pipe(empty); | |
| 6589 %} | |
| 6590 | |
| 6591 | |
| 6592 // Cast Index to Pointer for unsafe natives | |
| 6593 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6594 match(Set dst (CastX2P src)); | |
| 6595 | |
| 6596 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6597 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6598 ins_pipe(ialu_reg); | |
| 6599 %} | |
| 6600 | |
| 6601 // Cast Pointer to Index for unsafe natives | |
| 6602 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6603 match(Set dst (CastP2X src)); | |
| 6604 | |
| 6605 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6606 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6607 ins_pipe(ialu_reg); | |
| 6608 %} | |
| 6609 | |
| 6610 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6611 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6612 match(Set stkSlot src); // chain rule | |
| 6613 ins_cost(MEMORY_REF_COST); | |
| 6614 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6615 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6616 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6617 ins_pipe(fstoreD_stk_reg); |
| 6618 %} | |
| 6619 | |
| 6620 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6621 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6622 match(Set dst stkSlot); // chain rule | |
| 6623 ins_cost(MEMORY_REF_COST); | |
| 6624 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6625 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6626 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6627 ins_pipe(floadD_stk); |
| 6628 %} | |
| 6629 | |
| 6630 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6631 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6632 match(Set stkSlot src); // chain rule | |
| 6633 ins_cost(MEMORY_REF_COST); | |
| 6634 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6635 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6636 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6637 ins_pipe(fstoreF_stk_reg); |
| 6638 %} | |
| 6639 | |
| 6640 //----------Conditional Move--------------------------------------------------- | |
| 6641 // Conditional move | |
| 6642 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6643 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6644 ins_cost(150); | |
| 6645 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6646 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6647 ins_pipe(ialu_reg); | |
| 6648 %} | |
| 6649 | |
| 6650 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6651 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6652 ins_cost(140); | |
| 6653 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6654 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6655 ins_pipe(ialu_imm); | |
| 6656 %} | |
| 6657 | |
| 6658 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6659 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6660 ins_cost(150); | |
| 6661 size(4); | |
| 6662 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6663 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6664 ins_pipe(ialu_reg); | |
| 6665 %} | |
| 6666 | |
| 6667 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6668 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6669 ins_cost(140); | |
| 6670 size(4); | |
| 6671 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6672 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6673 ins_pipe(ialu_imm); | |
| 6674 %} | |
| 6675 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6676 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6677 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6678 ins_cost(150); | |
| 6679 size(4); | |
| 6680 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6681 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6682 ins_pipe(ialu_reg); | |
| 6683 %} | |
| 6684 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6685 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6686 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6687 ins_cost(140); | |
| 6688 size(4); | |
| 6689 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6690 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6691 ins_pipe(ialu_imm); | |
| 6692 %} | |
| 6693 | |
| 6694 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6695 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6696 ins_cost(150); | |
| 6697 size(4); | |
| 6698 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6699 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6700 ins_pipe(ialu_reg); | |
| 6701 %} | |
| 6702 | |
| 6703 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6704 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6705 ins_cost(140); | |
| 6706 size(4); | |
| 6707 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6708 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6709 ins_pipe(ialu_imm); | |
| 6710 %} | |
| 6711 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6712 // Conditional move for RegN. Only cmov(reg,reg). |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6713 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6714 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6715 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6716 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6717 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6718 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6719 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6720 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6721 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6722 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6723 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6724 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6725 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6726 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6727 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6728 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6729 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6730 |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6731 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6732 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6733 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6734 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6735 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6736 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6737 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6738 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6739 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6740 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6741 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6742 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6743 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6744 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6745 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6746 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6747 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6748 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6749 |
| 0 | 6750 // Conditional move |
| 6751 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6752 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6753 ins_cost(150); | |
| 6754 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6755 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6756 ins_pipe(ialu_reg); | |
| 6757 %} | |
| 6758 | |
| 6759 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6760 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6761 ins_cost(140); | |
| 6762 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6763 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6764 ins_pipe(ialu_imm); | |
| 6765 %} | |
| 6766 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6767 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6768 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6769 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6770 ins_cost(150); | |
| 6771 | |
| 6772 size(4); | |
| 6773 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6774 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6775 ins_pipe(ialu_reg); | |
| 6776 %} | |
| 6777 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6778 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6779 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6780 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6781 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6782 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6783 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6784 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6785 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6786 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6787 |
| 0 | 6788 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6789 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6790 ins_cost(140); | |
| 6791 | |
| 6792 size(4); | |
| 6793 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6794 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6795 ins_pipe(ialu_imm); | |
| 6796 %} | |
| 6797 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6798 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6799 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6800 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6801 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6802 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6803 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6804 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6805 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6806 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6807 |
| 0 | 6808 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6809 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6810 ins_cost(150); | |
| 6811 size(4); | |
| 6812 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6813 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6814 ins_pipe(ialu_imm); | |
| 6815 %} | |
| 6816 | |
| 6817 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6818 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6819 ins_cost(140); | |
| 6820 size(4); | |
| 6821 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6822 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6823 ins_pipe(ialu_imm); | |
| 6824 %} | |
| 6825 | |
| 6826 // Conditional move | |
| 6827 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6828 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6829 ins_cost(150); | |
| 6830 opcode(0x101); | |
| 6831 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6832 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6833 ins_pipe(int_conditional_float_move); | |
| 6834 %} | |
| 6835 | |
| 6836 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6837 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6838 ins_cost(150); | |
| 6839 | |
| 6840 size(4); | |
| 6841 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6842 opcode(0x101); | |
| 6843 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6844 ins_pipe(int_conditional_float_move); | |
| 6845 %} | |
| 6846 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6847 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6848 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6849 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6850 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6851 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6852 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6853 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6854 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6855 ins_pipe(int_conditional_float_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6856 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6857 |
| 0 | 6858 // Conditional move, |
| 6859 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6860 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6861 ins_cost(150); | |
| 6862 size(4); | |
| 6863 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6864 opcode(0x1); | |
| 6865 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6866 ins_pipe(int_conditional_double_move); | |
| 6867 %} | |
| 6868 | |
| 6869 // Conditional move | |
| 6870 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6871 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6872 ins_cost(150); | |
| 6873 size(4); | |
| 6874 opcode(0x102); | |
| 6875 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6876 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6877 ins_pipe(int_conditional_double_move); | |
| 6878 %} | |
| 6879 | |
| 6880 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 6881 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 6882 ins_cost(150); | |
| 6883 | |
| 6884 size(4); | |
| 6885 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 6886 opcode(0x102); | |
| 6887 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6888 ins_pipe(int_conditional_double_move); | |
| 6889 %} | |
| 6890 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6891 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6892 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6893 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6894 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6895 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6896 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6897 opcode(0x102); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6898 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6899 ins_pipe(int_conditional_double_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6900 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6901 |
| 0 | 6902 // Conditional move, |
| 6903 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 6904 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 6905 ins_cost(150); | |
| 6906 size(4); | |
| 6907 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 6908 opcode(0x2); | |
| 6909 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6910 ins_pipe(int_conditional_double_move); | |
| 6911 %} | |
| 6912 | |
| 6913 // Conditional move | |
| 6914 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 6915 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 6916 ins_cost(150); | |
| 6917 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 6918 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6919 ins_pipe(ialu_reg); | |
| 6920 %} | |
| 6921 | |
| 6922 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 6923 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 6924 ins_cost(140); | |
| 6925 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 6926 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6927 ins_pipe(ialu_imm); | |
| 6928 %} | |
| 6929 | |
| 6930 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 6931 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 6932 ins_cost(150); | |
| 6933 | |
| 6934 size(4); | |
| 6935 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 6936 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6937 ins_pipe(ialu_reg); | |
| 6938 %} | |
| 6939 | |
| 6940 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6941 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6942 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6943 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6944 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6945 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6946 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6947 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6948 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6949 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6950 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6951 |
| 0 | 6952 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 6953 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 6954 ins_cost(150); | |
| 6955 | |
| 6956 size(4); | |
| 6957 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 6958 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6959 ins_pipe(ialu_reg); | |
| 6960 %} | |
| 6961 | |
| 6962 | |
| 6963 | |
| 6964 //----------OS and Locking Instructions---------------------------------------- | |
| 6965 | |
| 6966 // This name is KNOWN by the ADLC and cannot be changed. | |
| 6967 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 6968 // for this guy. | |
| 6969 instruct tlsLoadP(g2RegP dst) %{ | |
| 6970 match(Set dst (ThreadLocal)); | |
| 6971 | |
| 6972 size(0); | |
| 6973 ins_cost(0); | |
| 6974 format %{ "# TLS is in G2" %} | |
| 6975 ins_encode( /*empty encoding*/ ); | |
| 6976 ins_pipe(ialu_none); | |
| 6977 %} | |
| 6978 | |
| 6979 instruct checkCastPP( iRegP dst ) %{ | |
| 6980 match(Set dst (CheckCastPP dst)); | |
| 6981 | |
| 6982 size(0); | |
| 6983 format %{ "# checkcastPP of $dst" %} | |
| 6984 ins_encode( /*empty encoding*/ ); | |
| 6985 ins_pipe(empty); | |
| 6986 %} | |
| 6987 | |
| 6988 | |
| 6989 instruct castPP( iRegP dst ) %{ | |
| 6990 match(Set dst (CastPP dst)); | |
| 6991 format %{ "# castPP of $dst" %} | |
| 6992 ins_encode( /*empty encoding*/ ); | |
| 6993 ins_pipe(empty); | |
| 6994 %} | |
| 6995 | |
| 6996 instruct castII( iRegI dst ) %{ | |
| 6997 match(Set dst (CastII dst)); | |
| 6998 format %{ "# castII of $dst" %} | |
| 6999 ins_encode( /*empty encoding*/ ); | |
| 7000 ins_cost(0); | |
| 7001 ins_pipe(empty); | |
| 7002 %} | |
| 7003 | |
| 7004 //----------Arithmetic Instructions-------------------------------------------- | |
| 7005 // Addition Instructions | |
| 7006 // Register Addition | |
| 7007 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7008 match(Set dst (AddI src1 src2)); | |
| 7009 | |
| 7010 size(4); | |
| 7011 format %{ "ADD $src1,$src2,$dst" %} | |
| 7012 ins_encode %{ | |
| 7013 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7014 %} | |
| 7015 ins_pipe(ialu_reg_reg); | |
| 7016 %} | |
| 7017 | |
| 7018 // Immediate Addition | |
| 7019 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7020 match(Set dst (AddI src1 src2)); | |
| 7021 | |
| 7022 size(4); | |
| 7023 format %{ "ADD $src1,$src2,$dst" %} | |
| 7024 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7025 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7026 ins_pipe(ialu_reg_imm); | |
| 7027 %} | |
| 7028 | |
| 7029 // Pointer Register Addition | |
| 7030 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7031 match(Set dst (AddP src1 src2)); | |
| 7032 | |
| 7033 size(4); | |
| 7034 format %{ "ADD $src1,$src2,$dst" %} | |
| 7035 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7036 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7037 ins_pipe(ialu_reg_reg); | |
| 7038 %} | |
| 7039 | |
| 7040 // Pointer Immediate Addition | |
| 7041 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7042 match(Set dst (AddP src1 src2)); | |
| 7043 | |
| 7044 size(4); | |
| 7045 format %{ "ADD $src1,$src2,$dst" %} | |
| 7046 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7047 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7048 ins_pipe(ialu_reg_imm); | |
| 7049 %} | |
| 7050 | |
| 7051 // Long Addition | |
| 7052 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7053 match(Set dst (AddL src1 src2)); | |
| 7054 | |
| 7055 size(4); | |
| 7056 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7057 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7058 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7059 ins_pipe(ialu_reg_reg); | |
| 7060 %} | |
| 7061 | |
| 7062 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7063 match(Set dst (AddL src1 con)); | |
| 7064 | |
| 7065 size(4); | |
| 7066 format %{ "ADD $src1,$con,$dst" %} | |
| 7067 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7068 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7069 ins_pipe(ialu_reg_imm); | |
| 7070 %} | |
| 7071 | |
| 7072 //----------Conditional_store-------------------------------------------------- | |
| 7073 // Conditional-store of the updated heap-top. | |
| 7074 // Used during allocation of the shared heap. | |
| 7075 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7076 | |
| 7077 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7078 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7079 match(Set dst (LoadPLocked mem)); | |
| 7080 ins_cost(MEMORY_REF_COST); | |
| 7081 | |
| 7082 #ifndef _LP64 | |
| 7083 size(4); | |
| 7084 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7085 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7086 #else | |
| 7087 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7088 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7089 #endif | |
| 7090 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7091 ins_pipe(iload_mem); | |
| 7092 %} | |
| 7093 | |
| 7094 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 7095 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 7096 match(Set dst (LoadLLocked mem)); | |
| 7097 ins_cost(MEMORY_REF_COST); | |
| 7098 size(4); | |
| 7099 format %{ "LDX $mem,$dst\t! long" %} | |
| 7100 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
7101 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 7102 ins_pipe(iload_mem); |
| 7103 %} | |
| 7104 | |
| 7105 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7106 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7107 effect( KILL newval ); | |
| 7108 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7109 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7110 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7111 ins_pipe( long_memory_op ); | |
| 7112 %} | |
| 7113 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7114 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7115 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7116 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7117 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7118 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7119 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7120 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7121 ins_pipe( long_memory_op ); |
| 7122 %} | |
| 7123 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7124 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7125 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7126 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7127 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7128 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7129 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7130 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7131 ins_pipe( long_memory_op ); |
| 7132 %} | |
| 7133 | |
| 7134 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7135 | |
| 7136 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7137 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7138 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7139 format %{ | |
| 7140 "MOV $newval,O7\n\t" | |
| 7141 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7142 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7143 "MOV 1,$res\n\t" | |
| 7144 "MOVne xcc,R_G0,$res" | |
| 7145 %} | |
| 7146 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7147 enc_lflags_ne_to_boolean(res) ); | |
| 7148 ins_pipe( long_memory_op ); | |
| 7149 %} | |
| 7150 | |
| 7151 | |
| 7152 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7153 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7154 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7155 format %{ | |
| 7156 "MOV $newval,O7\n\t" | |
| 7157 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7158 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7159 "MOV 1,$res\n\t" | |
| 7160 "MOVne icc,R_G0,$res" | |
| 7161 %} | |
| 7162 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7163 enc_iflags_ne_to_boolean(res) ); | |
| 7164 ins_pipe( long_memory_op ); | |
| 7165 %} | |
| 7166 | |
| 7167 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7168 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7169 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7170 format %{ | |
| 7171 "MOV $newval,O7\n\t" | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7172 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7173 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7174 "MOV 1,$res\n\t" | |
| 7175 "MOVne xcc,R_G0,$res" | |
| 7176 %} | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7177 #ifdef _LP64 |
| 0 | 7178 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7179 enc_lflags_ne_to_boolean(res) ); | |
| 7180 #else | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7181 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7182 enc_iflags_ne_to_boolean(res) ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7183 #endif |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7184 ins_pipe( long_memory_op ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7185 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7186 |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7187 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7188 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7189 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7190 format %{ |
| 7191 "MOV $newval,O7\n\t" | |
| 7192 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7193 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7194 "MOV 1,$res\n\t" | |
| 7195 "MOVne icc,R_G0,$res" | |
| 7196 %} | |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7197 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7198 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7199 ins_pipe( long_memory_op ); |
| 7200 %} | |
| 7201 | |
| 7202 //--------------------- | |
| 7203 // Subtraction Instructions | |
| 7204 // Register Subtraction | |
| 7205 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7206 match(Set dst (SubI src1 src2)); | |
| 7207 | |
| 7208 size(4); | |
| 7209 format %{ "SUB $src1,$src2,$dst" %} | |
| 7210 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7211 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7212 ins_pipe(ialu_reg_reg); | |
| 7213 %} | |
| 7214 | |
| 7215 // Immediate Subtraction | |
| 7216 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7217 match(Set dst (SubI src1 src2)); | |
| 7218 | |
| 7219 size(4); | |
| 7220 format %{ "SUB $src1,$src2,$dst" %} | |
| 7221 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7222 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7223 ins_pipe(ialu_reg_imm); | |
| 7224 %} | |
| 7225 | |
| 7226 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7227 match(Set dst (SubI zero src2)); | |
| 7228 | |
| 7229 size(4); | |
| 7230 format %{ "NEG $src2,$dst" %} | |
| 7231 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7232 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7233 ins_pipe(ialu_zero_reg); | |
| 7234 %} | |
| 7235 | |
| 7236 // Long subtraction | |
| 7237 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7238 match(Set dst (SubL src1 src2)); | |
| 7239 | |
| 7240 size(4); | |
| 7241 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7242 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7243 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7244 ins_pipe(ialu_reg_reg); | |
| 7245 %} | |
| 7246 | |
| 7247 // Immediate Subtraction | |
| 7248 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7249 match(Set dst (SubL src1 con)); | |
| 7250 | |
| 7251 size(4); | |
| 7252 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7253 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7254 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7255 ins_pipe(ialu_reg_imm); | |
| 7256 %} | |
| 7257 | |
| 7258 // Long negation | |
| 7259 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7260 match(Set dst (SubL zero src2)); | |
| 7261 | |
| 7262 size(4); | |
| 7263 format %{ "NEG $src2,$dst\t! long" %} | |
| 7264 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7265 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7266 ins_pipe(ialu_zero_reg); | |
| 7267 %} | |
| 7268 | |
| 7269 // Multiplication Instructions | |
| 7270 // Integer Multiplication | |
| 7271 // Register Multiplication | |
| 7272 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7273 match(Set dst (MulI src1 src2)); | |
| 7274 | |
| 7275 size(4); | |
| 7276 format %{ "MULX $src1,$src2,$dst" %} | |
| 7277 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7278 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7279 ins_pipe(imul_reg_reg); | |
| 7280 %} | |
| 7281 | |
| 7282 // Immediate Multiplication | |
| 7283 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7284 match(Set dst (MulI src1 src2)); | |
| 7285 | |
| 7286 size(4); | |
| 7287 format %{ "MULX $src1,$src2,$dst" %} | |
| 7288 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7289 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7290 ins_pipe(imul_reg_imm); | |
| 7291 %} | |
| 7292 | |
| 7293 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7294 match(Set dst (MulL src1 src2)); | |
| 7295 ins_cost(DEFAULT_COST * 5); | |
| 7296 size(4); | |
| 7297 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7298 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7299 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7300 ins_pipe(mulL_reg_reg); | |
| 7301 %} | |
| 7302 | |
| 7303 // Immediate Multiplication | |
| 7304 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7305 match(Set dst (MulL src1 src2)); | |
| 7306 ins_cost(DEFAULT_COST * 5); | |
| 7307 size(4); | |
| 7308 format %{ "MULX $src1,$src2,$dst" %} | |
| 7309 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7310 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7311 ins_pipe(mulL_reg_imm); | |
| 7312 %} | |
| 7313 | |
| 7314 // Integer Division | |
| 7315 // Register Division | |
| 7316 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7317 match(Set dst (DivI src1 src2)); | |
| 7318 ins_cost((2+71)*DEFAULT_COST); | |
| 7319 | |
| 7320 format %{ "SRA $src2,0,$src2\n\t" | |
| 7321 "SRA $src1,0,$src1\n\t" | |
| 7322 "SDIVX $src1,$src2,$dst" %} | |
| 7323 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7324 ins_pipe(sdiv_reg_reg); | |
| 7325 %} | |
| 7326 | |
| 7327 // Immediate Division | |
| 7328 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7329 match(Set dst (DivI src1 src2)); | |
| 7330 ins_cost((2+71)*DEFAULT_COST); | |
| 7331 | |
| 7332 format %{ "SRA $src1,0,$src1\n\t" | |
| 7333 "SDIVX $src1,$src2,$dst" %} | |
| 7334 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7335 ins_pipe(sdiv_reg_imm); | |
| 7336 %} | |
| 7337 | |
| 7338 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7339 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7340 // Expand rule only, not matched | |
| 7341 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7342 effect( DEF dst, USE src1, USE src2 ); | |
| 7343 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7344 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7345 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7346 ins_pipe(sdiv_reg_reg); | |
| 7347 %} | |
| 7348 | |
| 605 | 7349 // Magic constant, reciprocal of 10 |
| 0 | 7350 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7351 effect( DEF dst ); | |
| 7352 | |
| 7353 size(8); | |
| 7354 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7355 ins_encode( Set32(0x66666667, dst) ); | |
| 7356 ins_pipe(ialu_hi_lo_reg); | |
| 7357 %} | |
| 7358 | |
| 605 | 7359 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7360 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7361 effect( DEF dst, USE src ); | |
| 7362 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7363 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7364 ins_pipe(ialu_reg_reg); | |
| 7365 %} | |
| 7366 | |
| 7367 // Arithmetic Shift Right by 8-bit immediate | |
| 7368 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7369 effect( DEF dst, USE src ); | |
| 7370 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7371 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7372 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7373 ins_pipe(ialu_reg_imm); | |
| 7374 %} | |
| 7375 | |
| 7376 // Integer DIV with 10 | |
| 7377 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7378 match(Set dst (DivI src div)); | |
| 7379 ins_cost((6+6)*DEFAULT_COST); | |
| 7380 expand %{ | |
| 7381 iRegIsafe tmp1; // Killed temps; | |
| 7382 iRegIsafe tmp2; // Killed temps; | |
| 7383 iRegI tmp3; // Killed temps; | |
| 7384 iRegI tmp4; // Killed temps; | |
| 7385 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7386 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7387 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7388 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7389 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7390 %} | |
| 7391 %} | |
| 7392 | |
| 7393 // Register Long Division | |
| 7394 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7395 match(Set dst (DivL src1 src2)); | |
| 7396 ins_cost(DEFAULT_COST*71); | |
| 7397 size(4); | |
| 7398 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7399 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7400 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7401 ins_pipe(divL_reg_reg); | |
| 7402 %} | |
| 7403 | |
| 7404 // Register Long Division | |
| 7405 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7406 match(Set dst (DivL src1 src2)); | |
| 7407 ins_cost(DEFAULT_COST*71); | |
| 7408 size(4); | |
| 7409 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7410 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7411 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7412 ins_pipe(divL_reg_imm); | |
| 7413 %} | |
| 7414 | |
| 7415 // Integer Remainder | |
| 7416 // Register Remainder | |
| 7417 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7418 match(Set dst (ModI src1 src2)); | |
| 7419 effect( KILL ccr, KILL temp); | |
| 7420 | |
| 7421 format %{ "SREM $src1,$src2,$dst" %} | |
| 7422 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7423 ins_pipe(sdiv_reg_reg); | |
| 7424 %} | |
| 7425 | |
| 7426 // Immediate Remainder | |
| 7427 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7428 match(Set dst (ModI src1 src2)); | |
| 7429 effect( KILL ccr, KILL temp); | |
| 7430 | |
| 7431 format %{ "SREM $src1,$src2,$dst" %} | |
| 7432 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7433 ins_pipe(sdiv_reg_imm); | |
| 7434 %} | |
| 7435 | |
| 7436 // Register Long Remainder | |
| 7437 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7438 effect(DEF dst, USE src1, USE src2); | |
| 7439 size(4); | |
| 7440 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7441 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7442 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7443 ins_pipe(divL_reg_reg); | |
| 7444 %} | |
| 7445 | |
| 7446 // Register Long Division | |
| 7447 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7448 effect(DEF dst, USE src1, USE src2); | |
| 7449 size(4); | |
| 7450 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7451 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7452 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7453 ins_pipe(divL_reg_imm); | |
| 7454 %} | |
| 7455 | |
| 7456 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7457 effect(DEF dst, USE src1, USE src2); | |
| 7458 size(4); | |
| 7459 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7460 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7461 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7462 ins_pipe(mulL_reg_reg); | |
| 7463 %} | |
| 7464 | |
| 7465 // Immediate Multiplication | |
| 7466 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7467 effect(DEF dst, USE src1, USE src2); | |
| 7468 size(4); | |
| 7469 format %{ "MULX $src1,$src2,$dst" %} | |
| 7470 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7471 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7472 ins_pipe(mulL_reg_imm); | |
| 7473 %} | |
| 7474 | |
| 7475 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7476 effect(DEF dst, USE src1, USE src2); | |
| 7477 size(4); | |
| 7478 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7479 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7480 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7481 ins_pipe(ialu_reg_reg); | |
| 7482 %} | |
| 7483 | |
| 7484 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7485 effect(DEF dst, USE src1, USE src2); | |
| 7486 size(4); | |
| 7487 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7488 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7489 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7490 ins_pipe(ialu_reg_reg); | |
| 7491 %} | |
| 7492 | |
| 7493 // Register Long Remainder | |
| 7494 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7495 match(Set dst (ModL src1 src2)); | |
| 7496 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7497 expand %{ | |
| 7498 iRegL tmp1; | |
| 7499 iRegL tmp2; | |
| 7500 divL_reg_reg_1(tmp1, src1, src2); | |
| 7501 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7502 subL_reg_reg_1(dst, src1, tmp2); | |
| 7503 %} | |
| 7504 %} | |
| 7505 | |
| 7506 // Register Long Remainder | |
| 7507 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7508 match(Set dst (ModL src1 src2)); | |
| 7509 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7510 expand %{ | |
| 7511 iRegL tmp1; | |
| 7512 iRegL tmp2; | |
| 7513 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7514 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7515 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7516 %} | |
| 7517 %} | |
| 7518 | |
| 7519 // Integer Shift Instructions | |
| 7520 // Register Shift Left | |
| 7521 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7522 match(Set dst (LShiftI src1 src2)); | |
| 7523 | |
| 7524 size(4); | |
| 7525 format %{ "SLL $src1,$src2,$dst" %} | |
| 7526 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7527 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7528 ins_pipe(ialu_reg_reg); | |
| 7529 %} | |
| 7530 | |
| 7531 // Register Shift Left Immediate | |
| 7532 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7533 match(Set dst (LShiftI src1 src2)); | |
| 7534 | |
| 7535 size(4); | |
| 7536 format %{ "SLL $src1,$src2,$dst" %} | |
| 7537 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7538 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7539 ins_pipe(ialu_reg_imm); | |
| 7540 %} | |
| 7541 | |
| 7542 // Register Shift Left | |
| 7543 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7544 match(Set dst (LShiftL src1 src2)); | |
| 7545 | |
| 7546 size(4); | |
| 7547 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7548 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7549 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7550 ins_pipe(ialu_reg_reg); | |
| 7551 %} | |
| 7552 | |
| 7553 // Register Shift Left Immediate | |
| 7554 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7555 match(Set dst (LShiftL src1 src2)); | |
| 7556 | |
| 7557 size(4); | |
| 7558 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7559 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7560 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7561 ins_pipe(ialu_reg_imm); | |
| 7562 %} | |
| 7563 | |
| 7564 // Register Arithmetic Shift Right | |
| 7565 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7566 match(Set dst (RShiftI src1 src2)); | |
| 7567 size(4); | |
| 7568 format %{ "SRA $src1,$src2,$dst" %} | |
| 7569 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7570 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7571 ins_pipe(ialu_reg_reg); | |
| 7572 %} | |
| 7573 | |
| 7574 // Register Arithmetic Shift Right Immediate | |
| 7575 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7576 match(Set dst (RShiftI src1 src2)); | |
| 7577 | |
| 7578 size(4); | |
| 7579 format %{ "SRA $src1,$src2,$dst" %} | |
| 7580 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7581 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7582 ins_pipe(ialu_reg_imm); | |
| 7583 %} | |
| 7584 | |
| 7585 // Register Shift Right Arithmatic Long | |
| 7586 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7587 match(Set dst (RShiftL src1 src2)); | |
| 7588 | |
| 7589 size(4); | |
| 7590 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7591 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7592 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7593 ins_pipe(ialu_reg_reg); | |
| 7594 %} | |
| 7595 | |
| 7596 // Register Shift Left Immediate | |
| 7597 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7598 match(Set dst (RShiftL src1 src2)); | |
| 7599 | |
| 7600 size(4); | |
| 7601 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7602 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7603 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7604 ins_pipe(ialu_reg_imm); | |
| 7605 %} | |
| 7606 | |
| 7607 // Register Shift Right | |
| 7608 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7609 match(Set dst (URShiftI src1 src2)); | |
| 7610 | |
| 7611 size(4); | |
| 7612 format %{ "SRL $src1,$src2,$dst" %} | |
| 7613 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7614 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7615 ins_pipe(ialu_reg_reg); | |
| 7616 %} | |
| 7617 | |
| 7618 // Register Shift Right Immediate | |
| 7619 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7620 match(Set dst (URShiftI src1 src2)); | |
| 7621 | |
| 7622 size(4); | |
| 7623 format %{ "SRL $src1,$src2,$dst" %} | |
| 7624 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7625 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7626 ins_pipe(ialu_reg_imm); | |
| 7627 %} | |
| 7628 | |
| 7629 // Register Shift Right | |
| 7630 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7631 match(Set dst (URShiftL src1 src2)); | |
| 7632 | |
| 7633 size(4); | |
| 7634 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7635 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7636 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7637 ins_pipe(ialu_reg_reg); | |
| 7638 %} | |
| 7639 | |
| 7640 // Register Shift Right Immediate | |
| 7641 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7642 match(Set dst (URShiftL src1 src2)); | |
| 7643 | |
| 7644 size(4); | |
| 7645 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7646 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7647 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7648 ins_pipe(ialu_reg_imm); | |
| 7649 %} | |
| 7650 | |
| 7651 // Register Shift Right Immediate with a CastP2X | |
| 7652 #ifdef _LP64 | |
| 7653 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7654 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7655 size(4); | |
| 7656 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7657 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7658 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7659 ins_pipe(ialu_reg_imm); | |
| 7660 %} | |
| 7661 #else | |
| 7662 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7663 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7664 size(4); | |
| 7665 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7666 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7667 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7668 ins_pipe(ialu_reg_imm); | |
| 7669 %} | |
| 7670 #endif | |
| 7671 | |
| 7672 | |
| 7673 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7674 | |
| 7675 // Add float single precision | |
| 7676 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7677 match(Set dst (AddF src1 src2)); | |
| 7678 | |
| 7679 size(4); | |
| 7680 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7681 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7682 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7683 ins_pipe(faddF_reg_reg); | |
| 7684 %} | |
| 7685 | |
| 7686 // Add float double precision | |
| 7687 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7688 match(Set dst (AddD src1 src2)); | |
| 7689 | |
| 7690 size(4); | |
| 7691 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7692 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7693 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7694 ins_pipe(faddD_reg_reg); | |
| 7695 %} | |
| 7696 | |
| 7697 // Sub float single precision | |
| 7698 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7699 match(Set dst (SubF src1 src2)); | |
| 7700 | |
| 7701 size(4); | |
| 7702 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7703 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7704 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7705 ins_pipe(faddF_reg_reg); | |
| 7706 %} | |
| 7707 | |
| 7708 // Sub float double precision | |
| 7709 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7710 match(Set dst (SubD src1 src2)); | |
| 7711 | |
| 7712 size(4); | |
| 7713 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7715 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7716 ins_pipe(faddD_reg_reg); | |
| 7717 %} | |
| 7718 | |
| 7719 // Mul float single precision | |
| 7720 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7721 match(Set dst (MulF src1 src2)); | |
| 7722 | |
| 7723 size(4); | |
| 7724 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7725 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7726 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7727 ins_pipe(fmulF_reg_reg); | |
| 7728 %} | |
| 7729 | |
| 7730 // Mul float double precision | |
| 7731 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7732 match(Set dst (MulD src1 src2)); | |
| 7733 | |
| 7734 size(4); | |
| 7735 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7736 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7737 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7738 ins_pipe(fmulD_reg_reg); | |
| 7739 %} | |
| 7740 | |
| 7741 // Div float single precision | |
| 7742 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7743 match(Set dst (DivF src1 src2)); | |
| 7744 | |
| 7745 size(4); | |
| 7746 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7747 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7748 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7749 ins_pipe(fdivF_reg_reg); | |
| 7750 %} | |
| 7751 | |
| 7752 // Div float double precision | |
| 7753 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7754 match(Set dst (DivD src1 src2)); | |
| 7755 | |
| 7756 size(4); | |
| 7757 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7758 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7759 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7760 ins_pipe(fdivD_reg_reg); | |
| 7761 %} | |
| 7762 | |
| 7763 // Absolute float double precision | |
| 7764 instruct absD_reg(regD dst, regD src) %{ | |
| 7765 match(Set dst (AbsD src)); | |
| 7766 | |
| 7767 format %{ "FABSd $src,$dst" %} | |
| 7768 ins_encode(fabsd(dst, src)); | |
| 7769 ins_pipe(faddD_reg); | |
| 7770 %} | |
| 7771 | |
| 7772 // Absolute float single precision | |
| 7773 instruct absF_reg(regF dst, regF src) %{ | |
| 7774 match(Set dst (AbsF src)); | |
| 7775 | |
| 7776 format %{ "FABSs $src,$dst" %} | |
| 7777 ins_encode(fabss(dst, src)); | |
| 7778 ins_pipe(faddF_reg); | |
| 7779 %} | |
| 7780 | |
| 7781 instruct negF_reg(regF dst, regF src) %{ | |
| 7782 match(Set dst (NegF src)); | |
| 7783 | |
| 7784 size(4); | |
| 7785 format %{ "FNEGs $src,$dst" %} | |
| 7786 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7787 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7788 ins_pipe(faddF_reg); | |
| 7789 %} | |
| 7790 | |
| 7791 instruct negD_reg(regD dst, regD src) %{ | |
| 7792 match(Set dst (NegD src)); | |
| 7793 | |
| 7794 format %{ "FNEGd $src,$dst" %} | |
| 7795 ins_encode(fnegd(dst, src)); | |
| 7796 ins_pipe(faddD_reg); | |
| 7797 %} | |
| 7798 | |
| 7799 // Sqrt float double precision | |
| 7800 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7801 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7802 | |
| 7803 size(4); | |
| 7804 format %{ "FSQRTS $src,$dst" %} | |
| 7805 ins_encode(fsqrts(dst, src)); | |
| 7806 ins_pipe(fdivF_reg_reg); | |
| 7807 %} | |
| 7808 | |
| 7809 // Sqrt float double precision | |
| 7810 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7811 match(Set dst (SqrtD src)); | |
| 7812 | |
| 7813 size(4); | |
| 7814 format %{ "FSQRTD $src,$dst" %} | |
| 7815 ins_encode(fsqrtd(dst, src)); | |
| 7816 ins_pipe(fdivD_reg_reg); | |
| 7817 %} | |
| 7818 | |
| 7819 //----------Logical Instructions----------------------------------------------- | |
| 7820 // And Instructions | |
| 7821 // Register And | |
| 7822 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7823 match(Set dst (AndI src1 src2)); | |
| 7824 | |
| 7825 size(4); | |
| 7826 format %{ "AND $src1,$src2,$dst" %} | |
| 7827 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7828 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7829 ins_pipe(ialu_reg_reg); | |
| 7830 %} | |
| 7831 | |
| 7832 // Immediate And | |
| 7833 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7834 match(Set dst (AndI src1 src2)); | |
| 7835 | |
| 7836 size(4); | |
| 7837 format %{ "AND $src1,$src2,$dst" %} | |
| 7838 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7839 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7840 ins_pipe(ialu_reg_imm); | |
| 7841 %} | |
| 7842 | |
| 7843 // Register And Long | |
| 7844 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7845 match(Set dst (AndL src1 src2)); | |
| 7846 | |
| 7847 ins_cost(DEFAULT_COST); | |
| 7848 size(4); | |
| 7849 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7850 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7851 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7852 ins_pipe(ialu_reg_reg); | |
| 7853 %} | |
| 7854 | |
| 7855 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7856 match(Set dst (AndL src1 con)); | |
| 7857 | |
| 7858 ins_cost(DEFAULT_COST); | |
| 7859 size(4); | |
| 7860 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7861 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7862 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7863 ins_pipe(ialu_reg_imm); | |
| 7864 %} | |
| 7865 | |
| 7866 // Or Instructions | |
| 7867 // Register Or | |
| 7868 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7869 match(Set dst (OrI src1 src2)); | |
| 7870 | |
| 7871 size(4); | |
| 7872 format %{ "OR $src1,$src2,$dst" %} | |
| 7873 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7874 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7875 ins_pipe(ialu_reg_reg); | |
| 7876 %} | |
| 7877 | |
| 7878 // Immediate Or | |
| 7879 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7880 match(Set dst (OrI src1 src2)); | |
| 7881 | |
| 7882 size(4); | |
| 7883 format %{ "OR $src1,$src2,$dst" %} | |
| 7884 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7885 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7886 ins_pipe(ialu_reg_imm); | |
| 7887 %} | |
| 7888 | |
| 7889 // Register Or Long | |
| 7890 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7891 match(Set dst (OrL src1 src2)); | |
| 7892 | |
| 7893 ins_cost(DEFAULT_COST); | |
| 7894 size(4); | |
| 7895 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 7896 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7897 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7898 ins_pipe(ialu_reg_reg); | |
| 7899 %} | |
| 7900 | |
| 7901 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7902 match(Set dst (OrL src1 con)); | |
| 7903 ins_cost(DEFAULT_COST*2); | |
| 7904 | |
| 7905 ins_cost(DEFAULT_COST); | |
| 7906 size(4); | |
| 7907 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 7908 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7909 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7910 ins_pipe(ialu_reg_imm); | |
| 7911 %} | |
| 7912 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7913 #ifndef _LP64 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7914 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7915 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7916 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7917 match(Set dst (OrI src1 (CastP2X src2))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7918 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7919 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7920 format %{ "OR $src1,$src2,$dst" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7921 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7922 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7923 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7924 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7925 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7926 #else |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7927 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7928 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7929 match(Set dst (OrL src1 (CastP2X src2))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7930 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7931 ins_cost(DEFAULT_COST); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7932 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7933 format %{ "OR $src1,$src2,$dst\t! long" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7934 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7936 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7937 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7938 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7939 #endif |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7940 |
| 0 | 7941 // Xor Instructions |
| 7942 // Register Xor | |
| 7943 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7944 match(Set dst (XorI src1 src2)); | |
| 7945 | |
| 7946 size(4); | |
| 7947 format %{ "XOR $src1,$src2,$dst" %} | |
| 7948 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7949 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7950 ins_pipe(ialu_reg_reg); | |
| 7951 %} | |
| 7952 | |
| 7953 // Immediate Xor | |
| 7954 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7955 match(Set dst (XorI src1 src2)); | |
| 7956 | |
| 7957 size(4); | |
| 7958 format %{ "XOR $src1,$src2,$dst" %} | |
| 7959 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7960 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7961 ins_pipe(ialu_reg_imm); | |
| 7962 %} | |
| 7963 | |
| 7964 // Register Xor Long | |
| 7965 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7966 match(Set dst (XorL src1 src2)); | |
| 7967 | |
| 7968 ins_cost(DEFAULT_COST); | |
| 7969 size(4); | |
| 7970 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 7971 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7972 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7973 ins_pipe(ialu_reg_reg); | |
| 7974 %} | |
| 7975 | |
| 7976 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7977 match(Set dst (XorL src1 con)); | |
| 7978 | |
| 7979 ins_cost(DEFAULT_COST); | |
| 7980 size(4); | |
| 7981 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 7982 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7983 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7984 ins_pipe(ialu_reg_imm); | |
| 7985 %} | |
| 7986 | |
| 7987 //----------Convert to Boolean------------------------------------------------- | |
| 7988 // Nice hack for 32-bit tests but doesn't work for | |
| 7989 // 64-bit pointers. | |
| 7990 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 7991 match(Set dst (Conv2B src)); | |
| 7992 effect( KILL ccr ); | |
| 7993 ins_cost(DEFAULT_COST*2); | |
| 7994 format %{ "CMP R_G0,$src\n\t" | |
| 7995 "ADDX R_G0,0,$dst" %} | |
| 7996 ins_encode( enc_to_bool( src, dst ) ); | |
| 7997 ins_pipe(ialu_reg_ialu); | |
| 7998 %} | |
| 7999 | |
| 8000 #ifndef _LP64 | |
| 8001 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8002 match(Set dst (Conv2B src)); | |
| 8003 effect( KILL ccr ); | |
| 8004 ins_cost(DEFAULT_COST*2); | |
| 8005 format %{ "CMP R_G0,$src\n\t" | |
| 8006 "ADDX R_G0,0,$dst" %} | |
| 8007 ins_encode( enc_to_bool( src, dst ) ); | |
| 8008 ins_pipe(ialu_reg_ialu); | |
| 8009 %} | |
| 8010 #else | |
| 8011 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8012 match(Set dst (Conv2B src)); | |
| 8013 ins_cost(DEFAULT_COST*2); | |
| 8014 format %{ "MOV $src,$dst\n\t" | |
| 8015 "MOVRNZ $src,1,$dst" %} | |
| 8016 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8017 ins_pipe(ialu_clr_and_mover); | |
| 8018 %} | |
| 8019 #endif | |
| 8020 | |
| 8021 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
| 8022 match(Set dst (CmpLTMask p q)); | |
| 8023 effect( KILL ccr ); | |
| 8024 ins_cost(DEFAULT_COST*4); | |
| 8025 format %{ "CMP $p,$q\n\t" | |
| 8026 "MOV #0,$dst\n\t" | |
| 8027 "BLT,a .+8\n\t" | |
| 8028 "MOV #-1,$dst" %} | |
| 8029 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8030 ins_pipe(ialu_reg_reg_ialu); | |
| 8031 %} | |
| 8032 | |
| 8033 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8034 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8035 effect(KILL ccr, TEMP tmp); | |
| 8036 ins_cost(DEFAULT_COST*3); | |
| 8037 | |
| 8038 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8039 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8040 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8041 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8042 ins_pipe( cadd_cmpltmask ); | |
| 8043 %} | |
| 8044 | |
| 8045 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8046 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
| 8047 effect( KILL ccr, TEMP tmp); | |
| 8048 ins_cost(DEFAULT_COST*3); | |
| 8049 | |
| 8050 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8051 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8052 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8053 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8054 ins_pipe( cadd_cmpltmask ); | |
| 8055 %} | |
| 8056 | |
| 8057 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 8058 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8059 | |
| 8060 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8061 match(Set dst (ConvD2F src)); | |
| 8062 size(4); | |
| 8063 format %{ "FDTOS $src,$dst" %} | |
| 8064 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8065 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8066 ins_pipe(fcvtD2F); | |
| 8067 %} | |
| 8068 | |
| 8069 | |
| 8070 // Convert a double to an int in a float register. | |
| 8071 // If the double is a NAN, stuff a zero in instead. | |
| 8072 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8073 effect(DEF dst, USE src, KILL fcc0); | |
| 8074 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8075 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8076 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8077 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8078 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8079 "skip:" %} | |
| 8080 ins_encode(form_d2i_helper(src,dst)); | |
| 8081 ins_pipe(fcvtD2I); | |
| 8082 %} | |
| 8083 | |
| 8084 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
| 8085 match(Set dst (ConvD2I src)); | |
| 8086 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8087 expand %{ | |
| 8088 regF tmp; | |
| 8089 convD2I_helper(tmp, src); | |
| 8090 regF_to_stkI(dst, tmp); | |
| 8091 %} | |
| 8092 %} | |
| 8093 | |
| 8094 // Convert a double to a long in a double register. | |
| 8095 // If the double is a NAN, stuff a zero in instead. | |
| 8096 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8097 effect(DEF dst, USE src, KILL fcc0); | |
| 8098 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8099 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8100 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8101 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8102 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8103 "skip:" %} | |
| 8104 ins_encode(form_d2l_helper(src,dst)); | |
| 8105 ins_pipe(fcvtD2L); | |
| 8106 %} | |
| 8107 | |
| 8108 | |
| 8109 // Double to Long conversion | |
| 8110 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
| 8111 match(Set dst (ConvD2L src)); | |
| 8112 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8113 expand %{ | |
| 8114 regD tmp; | |
| 8115 convD2L_helper(tmp, src); | |
| 8116 regD_to_stkL(dst, tmp); | |
| 8117 %} | |
| 8118 %} | |
| 8119 | |
| 8120 | |
| 8121 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8122 match(Set dst (ConvF2D src)); | |
| 8123 format %{ "FSTOD $src,$dst" %} | |
| 8124 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8125 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8126 ins_pipe(fcvtF2D); | |
| 8127 %} | |
| 8128 | |
| 8129 | |
| 8130 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8131 effect(DEF dst, USE src, KILL fcc0); | |
| 8132 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8133 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8134 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8135 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8136 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8137 "skip:" %} | |
| 8138 ins_encode(form_f2i_helper(src,dst)); | |
| 8139 ins_pipe(fcvtF2I); | |
| 8140 %} | |
| 8141 | |
| 8142 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
| 8143 match(Set dst (ConvF2I src)); | |
| 8144 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8145 expand %{ | |
| 8146 regF tmp; | |
| 8147 convF2I_helper(tmp, src); | |
| 8148 regF_to_stkI(dst, tmp); | |
| 8149 %} | |
| 8150 %} | |
| 8151 | |
| 8152 | |
| 8153 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8154 effect(DEF dst, USE src, KILL fcc0); | |
| 8155 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8156 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8157 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8158 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8159 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8160 "skip:" %} | |
| 8161 ins_encode(form_f2l_helper(src,dst)); | |
| 8162 ins_pipe(fcvtF2L); | |
| 8163 %} | |
| 8164 | |
| 8165 // Float to Long conversion | |
| 8166 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
| 8167 match(Set dst (ConvF2L src)); | |
| 8168 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8169 expand %{ | |
| 8170 regD tmp; | |
| 8171 convF2L_helper(tmp, src); | |
| 8172 regD_to_stkL(dst, tmp); | |
| 8173 %} | |
| 8174 %} | |
| 8175 | |
| 8176 | |
| 8177 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8178 effect(USE tmp, DEF dst); | |
| 8179 format %{ "FITOD $tmp,$dst" %} | |
| 8180 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8181 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8182 ins_pipe(fcvtI2D); | |
| 8183 %} | |
| 8184 | |
| 8185 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
| 8186 match(Set dst (ConvI2D src)); | |
| 8187 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8188 expand %{ | |
| 8189 regF tmp; | |
| 8190 stkI_to_regF( tmp, src); | |
| 8191 convI2D_helper( dst, tmp); | |
| 8192 %} | |
| 8193 %} | |
| 8194 | |
| 8195 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
| 8196 match(Set dst (ConvI2D (LoadI mem))); | |
| 8197 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8198 size(8); | |
| 8199 format %{ "LDF $mem,$dst\n\t" | |
| 8200 "FITOD $dst,$dst" %} | |
| 8201 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8202 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8203 ins_pipe(floadF_mem); |
| 8204 %} | |
| 8205 | |
| 8206 | |
| 8207 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8208 effect(DEF dst, USE tmp); | |
| 8209 format %{ "FITOS $tmp,$dst" %} | |
| 8210 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8211 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8212 ins_pipe(fcvtI2F); | |
| 8213 %} | |
| 8214 | |
| 8215 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
| 8216 match(Set dst (ConvI2F src)); | |
| 8217 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8218 expand %{ | |
| 8219 regF tmp; | |
| 8220 stkI_to_regF(tmp,src); | |
| 8221 convI2F_helper(dst, tmp); | |
| 8222 %} | |
| 8223 %} | |
| 8224 | |
| 8225 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8226 match(Set dst (ConvI2F (LoadI mem))); | |
| 8227 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8228 size(8); | |
| 8229 format %{ "LDF $mem,$dst\n\t" | |
| 8230 "FITOS $dst,$dst" %} | |
| 8231 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8232 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8233 ins_pipe(floadF_mem); |
| 8234 %} | |
| 8235 | |
| 8236 | |
| 8237 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8238 match(Set dst (ConvI2L src)); | |
| 8239 size(4); | |
| 8240 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8241 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8242 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8243 ins_pipe(ialu_reg_reg); | |
| 8244 %} | |
| 8245 | |
| 8246 // Zero-extend convert int to long | |
| 8247 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8248 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8249 size(4); | |
| 8250 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8251 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8252 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8253 ins_pipe(ialu_reg_reg); | |
| 8254 %} | |
| 8255 | |
| 8256 // Zero-extend long | |
| 8257 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8258 match(Set dst (AndL src mask) ); | |
| 8259 size(4); | |
| 8260 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8261 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8262 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8263 ins_pipe(ialu_reg_reg); | |
| 8264 %} | |
| 8265 | |
| 8266 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
| 8267 match(Set dst (MoveF2I src)); | |
| 8268 effect(DEF dst, USE src); | |
| 8269 ins_cost(MEMORY_REF_COST); | |
| 8270 | |
| 8271 size(4); | |
| 8272 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8273 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8274 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8275 ins_pipe(iload_mem); |
| 8276 %} | |
| 8277 | |
| 8278 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8279 match(Set dst (MoveI2F src)); | |
| 8280 effect(DEF dst, USE src); | |
| 8281 ins_cost(MEMORY_REF_COST); | |
| 8282 | |
| 8283 size(4); | |
| 8284 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8285 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8286 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8287 ins_pipe(floadF_stk); |
| 8288 %} | |
| 8289 | |
| 8290 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8291 match(Set dst (MoveD2L src)); | |
| 8292 effect(DEF dst, USE src); | |
| 8293 ins_cost(MEMORY_REF_COST); | |
| 8294 | |
| 8295 size(4); | |
| 8296 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8297 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8298 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8299 ins_pipe(iload_mem); |
| 8300 %} | |
| 8301 | |
| 8302 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8303 match(Set dst (MoveL2D src)); | |
| 8304 effect(DEF dst, USE src); | |
| 8305 ins_cost(MEMORY_REF_COST); | |
| 8306 | |
| 8307 size(4); | |
| 8308 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8309 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8310 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8311 ins_pipe(floadD_stk); |
| 8312 %} | |
| 8313 | |
| 8314 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8315 match(Set dst (MoveF2I src)); | |
| 8316 effect(DEF dst, USE src); | |
| 8317 ins_cost(MEMORY_REF_COST); | |
| 8318 | |
| 8319 size(4); | |
| 8320 format %{ "STF $src,$dst\t!MoveF2I" %} | |
| 8321 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8322 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8323 ins_pipe(fstoreF_stk_reg); |
| 8324 %} | |
| 8325 | |
| 8326 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8327 match(Set dst (MoveI2F src)); | |
| 8328 effect(DEF dst, USE src); | |
| 8329 ins_cost(MEMORY_REF_COST); | |
| 8330 | |
| 8331 size(4); | |
| 8332 format %{ "STW $src,$dst\t!MoveI2F" %} | |
| 8333 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8334 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8335 ins_pipe(istore_mem_reg); |
| 8336 %} | |
| 8337 | |
| 8338 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8339 match(Set dst (MoveD2L src)); | |
| 8340 effect(DEF dst, USE src); | |
| 8341 ins_cost(MEMORY_REF_COST); | |
| 8342 | |
| 8343 size(4); | |
| 8344 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
| 8345 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8346 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8347 ins_pipe(fstoreD_stk_reg); |
| 8348 %} | |
| 8349 | |
| 8350 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8351 match(Set dst (MoveL2D src)); | |
| 8352 effect(DEF dst, USE src); | |
| 8353 ins_cost(MEMORY_REF_COST); | |
| 8354 | |
| 8355 size(4); | |
| 8356 format %{ "STX $src,$dst\t!MoveL2D" %} | |
| 8357 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8358 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8359 ins_pipe(istore_mem_reg); |
| 8360 %} | |
| 8361 | |
| 8362 | |
| 8363 //----------- | |
| 8364 // Long to Double conversion using V8 opcodes. | |
| 8365 // Still useful because cheetah traps and becomes | |
| 8366 // amazingly slow for some common numbers. | |
| 8367 | |
| 8368 // Magic constant, 0x43300000 | |
| 8369 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8370 effect(DEF dst); | |
| 8371 size(4); | |
| 8372 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8373 ins_encode(SetHi22(0x43300000, dst)); | |
| 8374 ins_pipe(ialu_none); | |
| 8375 %} | |
| 8376 | |
| 8377 // Magic constant, 0x41f00000 | |
| 8378 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8379 effect(DEF dst); | |
| 8380 size(4); | |
| 8381 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8382 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8383 ins_pipe(ialu_none); | |
| 8384 %} | |
| 8385 | |
| 8386 // Construct a double from two float halves | |
| 8387 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8388 effect(DEF dst, USE src1, USE src2); | |
| 8389 size(8); | |
| 8390 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8391 "FMOVS $src2.lo,$dst.lo" %} | |
| 8392 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8393 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8394 ins_pipe(faddD_reg_reg); | |
| 8395 %} | |
| 8396 | |
| 8397 // Convert integer in high half of a double register (in the lower half of | |
| 8398 // the double register file) to double | |
| 8399 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8400 effect(DEF dst, USE src); | |
| 8401 size(4); | |
| 8402 format %{ "FITOD $src,$dst" %} | |
| 8403 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8404 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8405 ins_pipe(fcvtLHi2D); | |
| 8406 %} | |
| 8407 | |
| 8408 // Add float double precision | |
| 8409 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8410 effect(DEF dst, USE src1, USE src2); | |
| 8411 size(4); | |
| 8412 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8413 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8414 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8415 ins_pipe(faddD_reg_reg); | |
| 8416 %} | |
| 8417 | |
| 8418 // Sub float double precision | |
| 8419 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8420 effect(DEF dst, USE src1, USE src2); | |
| 8421 size(4); | |
| 8422 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8423 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8424 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8425 ins_pipe(faddD_reg_reg); | |
| 8426 %} | |
| 8427 | |
| 8428 // Mul float double precision | |
| 8429 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8430 effect(DEF dst, USE src1, USE src2); | |
| 8431 size(4); | |
| 8432 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8433 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8434 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8435 ins_pipe(fmulD_reg_reg); | |
| 8436 %} | |
| 8437 | |
| 8438 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8439 match(Set dst (ConvL2D src)); | |
| 8440 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8441 | |
| 8442 expand %{ | |
| 8443 regD_low tmpsrc; | |
| 8444 iRegI ix43300000; | |
| 8445 iRegI ix41f00000; | |
| 8446 stackSlotL lx43300000; | |
| 8447 stackSlotL lx41f00000; | |
| 8448 regD_low dx43300000; | |
| 8449 regD dx41f00000; | |
| 8450 regD tmp1; | |
| 8451 regD_low tmp2; | |
| 8452 regD tmp3; | |
| 8453 regD tmp4; | |
| 8454 | |
| 8455 stkL_to_regD(tmpsrc, src); | |
| 8456 | |
| 8457 loadConI_x43300000(ix43300000); | |
| 8458 loadConI_x41f00000(ix41f00000); | |
| 8459 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8460 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8461 stkL_to_regD(dx43300000, lx43300000); | |
| 8462 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8463 | |
| 8464 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8465 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8466 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8467 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8468 addD_regD_regD(dst, tmp3, tmp4); | |
| 8469 %} | |
| 8470 %} | |
| 8471 | |
| 8472 // Long to Double conversion using fast fxtof | |
| 8473 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8474 effect(DEF dst, USE tmp); | |
| 8475 size(4); | |
| 8476 format %{ "FXTOD $tmp,$dst" %} | |
| 8477 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8478 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8479 ins_pipe(fcvtL2D); | |
| 8480 %} | |
| 8481 | |
| 8482 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
| 8483 predicate(VM_Version::has_fast_fxtof()); | |
| 8484 match(Set dst (ConvL2D src)); | |
| 8485 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8486 expand %{ | |
| 8487 regD tmp; | |
| 8488 stkL_to_regD(tmp, src); | |
| 8489 convL2D_helper(dst, tmp); | |
| 8490 %} | |
| 8491 %} | |
| 8492 | |
| 8493 //----------- | |
| 8494 // Long to Float conversion using V8 opcodes. | |
| 8495 // Still useful because cheetah traps and becomes | |
| 8496 // amazingly slow for some common numbers. | |
| 8497 | |
| 8498 // Long to Float conversion using fast fxtof | |
| 8499 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8500 effect(DEF dst, USE tmp); | |
| 8501 size(4); | |
| 8502 format %{ "FXTOS $tmp,$dst" %} | |
| 8503 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8504 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8505 ins_pipe(fcvtL2F); | |
| 8506 %} | |
| 8507 | |
| 8508 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
| 8509 match(Set dst (ConvL2F src)); | |
| 8510 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8511 expand %{ | |
| 8512 regD tmp; | |
| 8513 stkL_to_regD(tmp, src); | |
| 8514 convL2F_helper(dst, tmp); | |
| 8515 %} | |
| 8516 %} | |
| 8517 //----------- | |
| 8518 | |
| 8519 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8520 match(Set dst (ConvL2I src)); | |
| 8521 #ifndef _LP64 | |
| 8522 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8523 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8524 ins_pipe(ialu_move_reg_I_to_L); | |
| 8525 #else | |
| 8526 size(4); | |
| 8527 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8528 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8529 ins_pipe(ialu_reg); | |
| 8530 #endif | |
| 8531 %} | |
| 8532 | |
| 8533 // Register Shift Right Immediate | |
| 8534 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8535 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8536 | |
| 8537 size(4); | |
| 8538 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8539 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8540 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8541 ins_pipe(ialu_reg_imm); | |
| 8542 %} | |
| 8543 | |
| 8544 // Replicate scalar to packed byte values in Double register | |
| 8545 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8546 effect(DEF dst, USE src); | |
| 8547 format %{ "SLLX $src,56,$dst\n\t" | |
| 8548 "SRLX $dst, 8,O7\n\t" | |
| 8549 "OR $dst,O7,$dst\n\t" | |
| 8550 "SRLX $dst,16,O7\n\t" | |
| 8551 "OR $dst,O7,$dst\n\t" | |
| 8552 "SRLX $dst,32,O7\n\t" | |
| 8553 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8554 ins_encode( enc_repl8b(src, dst)); | |
| 8555 ins_pipe(ialu_reg); | |
| 8556 %} | |
| 8557 | |
| 8558 // Replicate scalar to packed byte values in Double register | |
| 8559 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8560 match(Set dst (Replicate8B src)); | |
| 8561 expand %{ | |
| 8562 iRegL tmp; | |
| 8563 Repl8B_reg_helper(tmp, src); | |
| 8564 regL_to_stkD(dst, tmp); | |
| 8565 %} | |
| 8566 %} | |
| 8567 | |
| 8568 // Replicate scalar constant to packed byte values in Double register | |
| 8569 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
| 8570 match(Set dst (Replicate8B src)); | |
| 8571 #ifdef _LP64 | |
| 8572 size(36); | |
| 8573 #else | |
| 8574 size(8); | |
| 8575 #endif | |
| 8576 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
| 8577 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
| 8578 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
| 8579 ins_pipe(loadConFD); | |
| 8580 %} | |
| 8581 | |
| 8582 // Replicate scalar to packed char values into stack slot | |
| 8583 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8584 effect(DEF dst, USE src); | |
| 8585 format %{ "SLLX $src,48,$dst\n\t" | |
| 8586 "SRLX $dst,16,O7\n\t" | |
| 8587 "OR $dst,O7,$dst\n\t" | |
| 8588 "SRLX $dst,32,O7\n\t" | |
| 8589 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8590 ins_encode( enc_repl4s(src, dst) ); | |
| 8591 ins_pipe(ialu_reg); | |
| 8592 %} | |
| 8593 | |
| 8594 // Replicate scalar to packed char values into stack slot | |
| 8595 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8596 match(Set dst (Replicate4C src)); | |
| 8597 expand %{ | |
| 8598 iRegL tmp; | |
| 8599 Repl4C_reg_helper(tmp, src); | |
| 8600 regL_to_stkD(dst, tmp); | |
| 8601 %} | |
| 8602 %} | |
| 8603 | |
| 8604 // Replicate scalar constant to packed char values in Double register | |
| 8605 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8606 match(Set dst (Replicate4C src)); | |
| 8607 #ifdef _LP64 | |
| 8608 size(36); | |
| 8609 #else | |
| 8610 size(8); | |
| 8611 #endif | |
| 8612 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
| 8613 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
| 8614 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
| 8615 ins_pipe(loadConFD); | |
| 8616 %} | |
| 8617 | |
| 8618 // Replicate scalar to packed short values into stack slot | |
| 8619 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8620 effect(DEF dst, USE src); | |
| 8621 format %{ "SLLX $src,48,$dst\n\t" | |
| 8622 "SRLX $dst,16,O7\n\t" | |
| 8623 "OR $dst,O7,$dst\n\t" | |
| 8624 "SRLX $dst,32,O7\n\t" | |
| 8625 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8626 ins_encode( enc_repl4s(src, dst) ); | |
| 8627 ins_pipe(ialu_reg); | |
| 8628 %} | |
| 8629 | |
| 8630 // Replicate scalar to packed short values into stack slot | |
| 8631 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8632 match(Set dst (Replicate4S src)); | |
| 8633 expand %{ | |
| 8634 iRegL tmp; | |
| 8635 Repl4S_reg_helper(tmp, src); | |
| 8636 regL_to_stkD(dst, tmp); | |
| 8637 %} | |
| 8638 %} | |
| 8639 | |
| 8640 // Replicate scalar constant to packed short values in Double register | |
| 8641 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8642 match(Set dst (Replicate4S src)); | |
| 8643 #ifdef _LP64 | |
| 8644 size(36); | |
| 8645 #else | |
| 8646 size(8); | |
| 8647 #endif | |
| 8648 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
| 8649 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
| 8650 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
| 8651 ins_pipe(loadConFD); | |
| 8652 %} | |
| 8653 | |
| 8654 // Replicate scalar to packed int values in Double register | |
| 8655 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8656 effect(DEF dst, USE src); | |
| 8657 format %{ "SLLX $src,32,$dst\n\t" | |
| 8658 "SRLX $dst,32,O7\n\t" | |
| 8659 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8660 ins_encode( enc_repl2i(src, dst)); | |
| 8661 ins_pipe(ialu_reg); | |
| 8662 %} | |
| 8663 | |
| 8664 // Replicate scalar to packed int values in Double register | |
| 8665 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8666 match(Set dst (Replicate2I src)); | |
| 8667 expand %{ | |
| 8668 iRegL tmp; | |
| 8669 Repl2I_reg_helper(tmp, src); | |
| 8670 regL_to_stkD(dst, tmp); | |
| 8671 %} | |
| 8672 %} | |
| 8673 | |
| 8674 // Replicate scalar zero constant to packed int values in Double register | |
| 8675 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8676 match(Set dst (Replicate2I src)); | |
| 8677 #ifdef _LP64 | |
| 8678 size(36); | |
| 8679 #else | |
| 8680 size(8); | |
| 8681 #endif | |
| 8682 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
| 8683 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
| 8684 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
| 8685 ins_pipe(loadConFD); | |
| 8686 %} | |
| 8687 | |
| 8688 //----------Control Flow Instructions------------------------------------------ | |
| 8689 // Compare Instructions | |
| 8690 // Compare Integers | |
| 8691 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8692 match(Set icc (CmpI op1 op2)); | |
| 8693 effect( DEF icc, USE op1, USE op2 ); | |
| 8694 | |
| 8695 size(4); | |
| 8696 format %{ "CMP $op1,$op2" %} | |
| 8697 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8698 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8699 ins_pipe(ialu_cconly_reg_reg); | |
| 8700 %} | |
| 8701 | |
| 8702 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8703 match(Set icc (CmpU op1 op2)); | |
| 8704 | |
| 8705 size(4); | |
| 8706 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8707 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8708 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8709 ins_pipe(ialu_cconly_reg_reg); | |
| 8710 %} | |
| 8711 | |
| 8712 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8713 match(Set icc (CmpI op1 op2)); | |
| 8714 effect( DEF icc, USE op1 ); | |
| 8715 | |
| 8716 size(4); | |
| 8717 format %{ "CMP $op1,$op2" %} | |
| 8718 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8719 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8720 ins_pipe(ialu_cconly_reg_imm); | |
| 8721 %} | |
| 8722 | |
| 8723 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8724 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8725 | |
| 8726 size(4); | |
| 8727 format %{ "BTST $op2,$op1" %} | |
| 8728 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8729 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8730 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8731 %} | |
| 8732 | |
| 8733 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8734 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8735 | |
| 8736 size(4); | |
| 8737 format %{ "BTST $op2,$op1" %} | |
| 8738 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8739 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8740 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8741 %} | |
| 8742 | |
| 8743 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8744 match(Set xcc (CmpL op1 op2)); | |
| 8745 effect( DEF xcc, USE op1, USE op2 ); | |
| 8746 | |
| 8747 size(4); | |
| 8748 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8749 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8750 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8751 ins_pipe(ialu_cconly_reg_reg); | |
| 8752 %} | |
| 8753 | |
| 8754 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8755 match(Set xcc (CmpL op1 con)); | |
| 8756 effect( DEF xcc, USE op1, USE con ); | |
| 8757 | |
| 8758 size(4); | |
| 8759 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8760 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8761 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8762 ins_pipe(ialu_cconly_reg_reg); | |
| 8763 %} | |
| 8764 | |
| 8765 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8766 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8767 effect( DEF xcc, USE op1, USE op2 ); | |
| 8768 | |
| 8769 size(4); | |
| 8770 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8771 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8772 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8773 ins_pipe(ialu_cconly_reg_reg); | |
| 8774 %} | |
| 8775 | |
| 8776 // useful for checking the alignment of a pointer: | |
| 8777 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8778 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8779 effect( DEF xcc, USE op1, USE con ); | |
| 8780 | |
| 8781 size(4); | |
| 8782 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8783 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8784 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8785 ins_pipe(ialu_cconly_reg_reg); | |
| 8786 %} | |
| 8787 | |
| 8788 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8789 match(Set icc (CmpU op1 op2)); | |
| 8790 | |
| 8791 size(4); | |
| 8792 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8793 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8794 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8795 ins_pipe(ialu_cconly_reg_imm); | |
| 8796 %} | |
| 8797 | |
| 8798 // Compare Pointers | |
| 8799 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8800 match(Set pcc (CmpP op1 op2)); | |
| 8801 | |
| 8802 size(4); | |
| 8803 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8804 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8805 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8806 ins_pipe(ialu_cconly_reg_reg); | |
| 8807 %} | |
| 8808 | |
| 8809 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8810 match(Set pcc (CmpP op1 op2)); | |
| 8811 | |
| 8812 size(4); | |
| 8813 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8814 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8815 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8816 ins_pipe(ialu_cconly_reg_imm); | |
| 8817 %} | |
| 8818 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8819 // Compare Narrow oops |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8820 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8821 match(Set icc (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8822 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8823 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8824 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8825 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8826 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8827 ins_pipe(ialu_cconly_reg_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8828 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8829 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8830 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8831 match(Set icc (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8832 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8833 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8834 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8835 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8836 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8837 ins_pipe(ialu_cconly_reg_imm); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8838 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8839 |
| 0 | 8840 //----------Max and Min-------------------------------------------------------- |
| 8841 // Min Instructions | |
| 8842 // Conditional move for min | |
| 8843 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8844 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8845 | |
| 8846 size(4); | |
| 8847 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 8848 opcode(Assembler::less); | |
| 8849 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8850 ins_pipe(ialu_reg_flags); | |
| 8851 %} | |
| 8852 | |
| 8853 // Min Register with Register. | |
| 8854 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 8855 match(Set op2 (MinI op1 op2)); | |
| 8856 ins_cost(DEFAULT_COST*2); | |
| 8857 expand %{ | |
| 8858 flagsReg icc; | |
| 8859 compI_iReg(icc,op1,op2); | |
| 8860 cmovI_reg_lt(op2,op1,icc); | |
| 8861 %} | |
| 8862 %} | |
| 8863 | |
| 8864 // Max Instructions | |
| 8865 // Conditional move for max | |
| 8866 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8867 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8868 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 8869 opcode(Assembler::greater); | |
| 8870 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8871 ins_pipe(ialu_reg_flags); | |
| 8872 %} | |
| 8873 | |
| 8874 // Max Register with Register | |
| 8875 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 8876 match(Set op2 (MaxI op1 op2)); | |
| 8877 ins_cost(DEFAULT_COST*2); | |
| 8878 expand %{ | |
| 8879 flagsReg icc; | |
| 8880 compI_iReg(icc,op1,op2); | |
| 8881 cmovI_reg_gt(op2,op1,icc); | |
| 8882 %} | |
| 8883 %} | |
| 8884 | |
| 8885 | |
| 8886 //----------Float Compares---------------------------------------------------- | |
| 8887 // Compare floating, generate condition code | |
| 8888 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 8889 match(Set fcc (CmpF src1 src2)); | |
| 8890 | |
| 8891 size(4); | |
| 8892 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 8893 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 8894 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 8895 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 8896 %} | |
| 8897 | |
| 8898 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 8899 match(Set fcc (CmpD src1 src2)); | |
| 8900 | |
| 8901 size(4); | |
| 8902 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 8903 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 8904 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 8905 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 8906 %} | |
| 8907 | |
| 8908 | |
| 8909 // Compare floating, generate -1,0,1 | |
| 8910 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 8911 match(Set dst (CmpF3 src1 src2)); | |
| 8912 effect(KILL fcc0); | |
| 8913 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8914 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 8915 // Primary = float | |
| 8916 opcode( true ); | |
| 8917 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8918 ins_pipe( floating_cmp ); | |
| 8919 %} | |
| 8920 | |
| 8921 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 8922 match(Set dst (CmpD3 src1 src2)); | |
| 8923 effect(KILL fcc0); | |
| 8924 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8925 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 8926 // Primary = double (not float) | |
| 8927 opcode( false ); | |
| 8928 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8929 ins_pipe( floating_cmp ); | |
| 8930 %} | |
| 8931 | |
| 8932 //----------Branches--------------------------------------------------------- | |
| 8933 // Jump | |
| 8934 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 8935 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 8936 match(Jump switch_val); | |
| 8937 | |
| 8938 ins_cost(350); | |
| 8939 | |
| 8940 format %{ "SETHI [hi(table_base)],O7\n\t" | |
| 8941 "ADD O7, lo(table_base), O7\n\t" | |
| 8942 "LD [O7+$switch_val], O7\n\t" | |
| 8943 "JUMP O7" | |
| 8944 %} | |
| 8945 ins_encode( jump_enc( switch_val, table) ); | |
| 8946 ins_pc_relative(1); | |
| 8947 ins_pipe(ialu_reg_reg); | |
| 8948 %} | |
| 8949 | |
| 8950 // Direct Branch. Use V8 version with longer range. | |
| 8951 instruct branch(label labl) %{ | |
| 8952 match(Goto); | |
| 8953 effect(USE labl); | |
| 8954 | |
| 8955 size(8); | |
| 8956 ins_cost(BRANCH_COST); | |
| 8957 format %{ "BA $labl" %} | |
| 8958 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
| 8959 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
| 8960 ins_encode( enc_ba( labl ) ); | |
| 8961 ins_pc_relative(1); | |
| 8962 ins_pipe(br); | |
| 8963 %} | |
| 8964 | |
| 8965 // Conditional Direct Branch | |
| 8966 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 8967 match(If cmp icc); | |
| 8968 effect(USE labl); | |
| 8969 | |
| 8970 size(8); | |
| 8971 ins_cost(BRANCH_COST); | |
| 8972 format %{ "BP$cmp $icc,$labl" %} | |
| 8973 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8974 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 8975 ins_pc_relative(1); | |
| 8976 ins_pipe(br_cc); | |
| 8977 %} | |
| 8978 | |
| 8979 // Branch-on-register tests all 64 bits. We assume that values | |
| 8980 // in 64-bit registers always remains zero or sign extended | |
| 8981 // unless our code munges the high bits. Interrupts can chop | |
| 8982 // the high order bits to zero or sign at any time. | |
| 8983 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 8984 match(If cmp (CmpI op1 zero)); | |
| 8985 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8986 effect(USE labl); | |
| 8987 | |
| 8988 size(8); | |
| 8989 ins_cost(BRANCH_COST); | |
| 8990 format %{ "BR$cmp $op1,$labl" %} | |
| 8991 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8992 ins_pc_relative(1); | |
| 8993 ins_pipe(br_reg); | |
| 8994 %} | |
| 8995 | |
| 8996 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 8997 match(If cmp (CmpP op1 null)); | |
| 8998 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8999 effect(USE labl); | |
| 9000 | |
| 9001 size(8); | |
| 9002 ins_cost(BRANCH_COST); | |
| 9003 format %{ "BR$cmp $op1,$labl" %} | |
| 9004 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9005 ins_pc_relative(1); | |
| 9006 ins_pipe(br_reg); | |
| 9007 %} | |
| 9008 | |
| 9009 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9010 match(If cmp (CmpL op1 zero)); | |
| 9011 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9012 effect(USE labl); | |
| 9013 | |
| 9014 size(8); | |
| 9015 ins_cost(BRANCH_COST); | |
| 9016 format %{ "BR$cmp $op1,$labl" %} | |
| 9017 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9018 ins_pc_relative(1); | |
| 9019 ins_pipe(br_reg); | |
| 9020 %} | |
| 9021 | |
| 9022 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9023 match(If cmp icc); | |
| 9024 effect(USE labl); | |
| 9025 | |
| 9026 format %{ "BP$cmp $icc,$labl" %} | |
| 9027 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9028 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9029 ins_pc_relative(1); | |
| 9030 ins_pipe(br_cc); | |
| 9031 %} | |
| 9032 | |
| 9033 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9034 match(If cmp pcc); | |
| 9035 effect(USE labl); | |
| 9036 | |
| 9037 size(8); | |
| 9038 ins_cost(BRANCH_COST); | |
| 9039 format %{ "BP$cmp $pcc,$labl" %} | |
| 9040 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9041 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
| 9042 ins_pc_relative(1); | |
| 9043 ins_pipe(br_cc); | |
| 9044 %} | |
| 9045 | |
| 9046 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9047 match(If cmp fcc); | |
| 9048 effect(USE labl); | |
| 9049 | |
| 9050 size(8); | |
| 9051 ins_cost(BRANCH_COST); | |
| 9052 format %{ "FBP$cmp $fcc,$labl" %} | |
| 9053 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9054 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
| 9055 ins_pc_relative(1); | |
| 9056 ins_pipe(br_fcc); | |
| 9057 %} | |
| 9058 | |
| 9059 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9060 match(CountedLoopEnd cmp icc); | |
| 9061 effect(USE labl); | |
| 9062 | |
| 9063 size(8); | |
| 9064 ins_cost(BRANCH_COST); | |
| 9065 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9066 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9067 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9068 ins_pc_relative(1); | |
| 9069 ins_pipe(br_cc); | |
| 9070 %} | |
| 9071 | |
| 9072 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9073 match(CountedLoopEnd cmp icc); | |
| 9074 effect(USE labl); | |
| 9075 | |
| 9076 size(8); | |
| 9077 ins_cost(BRANCH_COST); | |
| 9078 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9079 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9080 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9081 ins_pc_relative(1); | |
| 9082 ins_pipe(br_cc); | |
| 9083 %} | |
| 9084 | |
| 9085 // ============================================================================ | |
| 9086 // Long Compare | |
| 9087 // | |
| 9088 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9089 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9090 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9091 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9092 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9093 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9094 // NE test is negated from that. | |
| 9095 | |
| 9096 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9097 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9098 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9099 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9100 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9101 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9102 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9103 // both forms beat the trinary form of long-compare and both are very useful | |
| 9104 // on Intel which has so few registers. | |
| 9105 | |
| 9106 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9107 match(If cmp xcc); | |
| 9108 effect(USE labl); | |
| 9109 | |
| 9110 size(8); | |
| 9111 ins_cost(BRANCH_COST); | |
| 9112 format %{ "BP$cmp $xcc,$labl" %} | |
| 9113 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9114 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
| 9115 ins_pc_relative(1); | |
| 9116 ins_pipe(br_cc); | |
| 9117 %} | |
| 9118 | |
| 9119 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9120 // This is the test to avoid. | |
| 9121 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9122 match(Set dst (CmpL3 src1 src2) ); | |
| 9123 effect( KILL ccr ); | |
| 9124 ins_cost(6*DEFAULT_COST); | |
| 9125 size(24); | |
| 9126 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9127 "\tBLT,a,pn done\n" | |
| 9128 "\tMOV -1,$dst\t! delay slot\n" | |
| 9129 "\tBGT,a,pn done\n" | |
| 9130 "\tMOV 1,$dst\t! delay slot\n" | |
| 9131 "\tCLR $dst\n" | |
| 9132 "done:" %} | |
| 9133 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9134 ins_pipe(cmpL_reg); | |
| 9135 %} | |
| 9136 | |
| 9137 // Conditional move | |
| 9138 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9139 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9140 ins_cost(150); | |
| 9141 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9142 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9143 ins_pipe(ialu_reg); | |
| 9144 %} | |
| 9145 | |
| 9146 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9147 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9148 ins_cost(140); | |
| 9149 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9150 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9151 ins_pipe(ialu_imm); | |
| 9152 %} | |
| 9153 | |
| 9154 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9155 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9156 ins_cost(150); | |
| 9157 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9158 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9159 ins_pipe(ialu_reg); | |
| 9160 %} | |
| 9161 | |
| 9162 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9163 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9164 ins_cost(140); | |
| 9165 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9166 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9167 ins_pipe(ialu_imm); | |
| 9168 %} | |
| 9169 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9170 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9171 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9172 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9173 format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9174 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9175 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9176 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9177 |
| 0 | 9178 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9179 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9180 ins_cost(150); | |
| 9181 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9182 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9183 ins_pipe(ialu_reg); | |
| 9184 %} | |
| 9185 | |
| 9186 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9187 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9188 ins_cost(140); | |
| 9189 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9190 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9191 ins_pipe(ialu_imm); | |
| 9192 %} | |
| 9193 | |
| 9194 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9195 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9196 ins_cost(150); | |
| 9197 opcode(0x101); | |
| 9198 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9199 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9200 ins_pipe(int_conditional_float_move); | |
| 9201 %} | |
| 9202 | |
| 9203 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9204 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9205 ins_cost(150); | |
| 9206 opcode(0x102); | |
| 9207 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9208 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9209 ins_pipe(int_conditional_float_move); | |
| 9210 %} | |
| 9211 | |
| 9212 // ============================================================================ | |
| 9213 // Safepoint Instruction | |
| 9214 instruct safePoint_poll(iRegP poll) %{ | |
| 9215 match(SafePoint poll); | |
| 9216 effect(USE poll); | |
| 9217 | |
| 9218 size(4); | |
| 9219 #ifdef _LP64 | |
| 9220 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9221 #else | |
| 9222 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9223 #endif | |
| 9224 ins_encode %{ | |
| 9225 __ relocate(relocInfo::poll_type); | |
| 9226 __ ld_ptr($poll$$Register, 0, G0); | |
| 9227 %} | |
| 9228 ins_pipe(loadPollP); | |
| 9229 %} | |
| 9230 | |
| 9231 // ============================================================================ | |
| 9232 // Call Instructions | |
| 9233 // Call Java Static Instruction | |
| 9234 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9235 match(CallStaticJava); | |
| 1567 | 9236 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9237 effect(USE meth); |
| 9238 | |
| 9239 size(8); | |
| 9240 ins_cost(CALL_COST); | |
| 9241 format %{ "CALL,static ; NOP ==> " %} | |
| 9242 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9243 ins_pc_relative(1); | |
| 9244 ins_pipe(simple_call); | |
| 9245 %} | |
| 9246 | |
| 1567 | 9247 // Call Java Static Instruction (method handle version) |
| 9248 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9249 match(CallStaticJava); | |
| 9250 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9251 effect(USE meth, KILL l7_mh_SP_save); | |
| 9252 | |
| 9253 size(8); | |
| 9254 ins_cost(CALL_COST); | |
| 9255 format %{ "CALL,static/MethodHandle" %} | |
| 9256 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9257 ins_pc_relative(1); | |
| 9258 ins_pipe(simple_call); | |
| 9259 %} | |
| 9260 | |
| 0 | 9261 // Call Java Dynamic Instruction |
| 9262 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9263 match(CallDynamicJava); | |
| 9264 effect(USE meth); | |
| 9265 | |
| 9266 ins_cost(CALL_COST); | |
| 9267 format %{ "SET (empty),R_G5\n\t" | |
| 9268 "CALL,dynamic ; NOP ==> " %} | |
| 9269 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9270 ins_pc_relative(1); | |
| 9271 ins_pipe(call); | |
| 9272 %} | |
| 9273 | |
| 9274 // Call Runtime Instruction | |
| 9275 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9276 match(CallRuntime); | |
| 9277 effect(USE meth, KILL l7); | |
| 9278 ins_cost(CALL_COST); | |
| 9279 format %{ "CALL,runtime" %} | |
| 9280 ins_encode( Java_To_Runtime( meth ), | |
| 9281 call_epilog, adjust_long_from_native_call ); | |
| 9282 ins_pc_relative(1); | |
| 9283 ins_pipe(simple_call); | |
| 9284 %} | |
| 9285 | |
| 9286 // Call runtime without safepoint - same as CallRuntime | |
| 9287 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9288 match(CallLeaf); | |
| 9289 effect(USE meth, KILL l7); | |
| 9290 ins_cost(CALL_COST); | |
| 9291 format %{ "CALL,runtime leaf" %} | |
| 9292 ins_encode( Java_To_Runtime( meth ), | |
| 9293 call_epilog, | |
| 9294 adjust_long_from_native_call ); | |
| 9295 ins_pc_relative(1); | |
| 9296 ins_pipe(simple_call); | |
| 9297 %} | |
| 9298 | |
| 9299 // Call runtime without safepoint - same as CallLeaf | |
| 9300 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9301 match(CallLeafNoFP); | |
| 9302 effect(USE meth, KILL l7); | |
| 9303 ins_cost(CALL_COST); | |
| 9304 format %{ "CALL,runtime leaf nofp" %} | |
| 9305 ins_encode( Java_To_Runtime( meth ), | |
| 9306 call_epilog, | |
| 9307 adjust_long_from_native_call ); | |
| 9308 ins_pc_relative(1); | |
| 9309 ins_pipe(simple_call); | |
| 9310 %} | |
| 9311 | |
| 9312 // Tail Call; Jump from runtime stub to Java code. | |
| 9313 // Also known as an 'interprocedural jump'. | |
| 9314 // Target of jump will eventually return to caller. | |
| 9315 // TailJump below removes the return address. | |
| 9316 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 9317 match(TailCall jump_target method_oop ); | |
| 9318 | |
| 9319 ins_cost(CALL_COST); | |
| 9320 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 9321 ins_encode(form_jmpl(jump_target)); | |
| 9322 ins_pipe(tail_call); | |
| 9323 %} | |
| 9324 | |
| 9325 | |
| 9326 // Return Instruction | |
| 9327 instruct Ret() %{ | |
| 9328 match(Return); | |
| 9329 | |
| 9330 // The epilogue node did the ret already. | |
| 9331 size(0); | |
| 9332 format %{ "! return" %} | |
| 9333 ins_encode(); | |
| 9334 ins_pipe(empty); | |
| 9335 %} | |
| 9336 | |
| 9337 | |
| 9338 // Tail Jump; remove the return address; jump to target. | |
| 9339 // TailCall above leaves the return address around. | |
| 9340 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 9341 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 9342 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 9343 // in %i0. | |
| 9344 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 9345 match( TailJump jump_target ex_oop ); | |
| 9346 ins_cost(CALL_COST); | |
| 9347 format %{ "! discard R_O7\n\t" | |
| 9348 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 9349 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 9350 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 9351 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 9352 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 9353 ins_pipe(tail_call); | |
| 9354 %} | |
| 9355 | |
| 9356 // Create exception oop: created by stack-crawling runtime code. | |
| 9357 // Created exception is now available to this handler, and is setup | |
| 9358 // just prior to jumping to this handler. No code emitted. | |
| 9359 instruct CreateException( o0RegP ex_oop ) | |
| 9360 %{ | |
| 9361 match(Set ex_oop (CreateEx)); | |
| 9362 ins_cost(0); | |
| 9363 | |
| 9364 size(0); | |
| 9365 // use the following format syntax | |
| 9366 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 9367 ins_encode(); | |
| 9368 ins_pipe(empty); | |
| 9369 %} | |
| 9370 | |
| 9371 | |
| 9372 // Rethrow exception: | |
| 9373 // The exception oop will come in the first argument position. | |
| 9374 // Then JUMP (not call) to the rethrow stub code. | |
| 9375 instruct RethrowException() | |
| 9376 %{ | |
| 9377 match(Rethrow); | |
| 9378 ins_cost(CALL_COST); | |
| 9379 | |
| 9380 // use the following format syntax | |
| 9381 format %{ "Jmp rethrow_stub" %} | |
| 9382 ins_encode(enc_rethrow); | |
| 9383 ins_pipe(tail_call); | |
| 9384 %} | |
| 9385 | |
| 9386 | |
| 9387 // Die now | |
| 9388 instruct ShouldNotReachHere( ) | |
| 9389 %{ | |
| 9390 match(Halt); | |
| 9391 ins_cost(CALL_COST); | |
| 9392 | |
| 9393 size(4); | |
| 9394 // Use the following format syntax | |
| 9395 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 9396 ins_encode( form2_illtrap() ); | |
| 9397 ins_pipe(tail_call); | |
| 9398 %} | |
| 9399 | |
| 9400 // ============================================================================ | |
| 9401 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 9402 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 9403 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 9404 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 9405 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 9406 match(Set index (PartialSubtypeCheck sub super)); | |
| 9407 effect( KILL pcc, KILL o7 ); | |
| 9408 ins_cost(DEFAULT_COST*10); | |
| 9409 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 9410 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9411 ins_pipe(partial_subtype_check_pipe); | |
| 9412 %} | |
| 9413 | |
| 9414 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 9415 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 9416 effect( KILL idx, KILL o7 ); | |
| 9417 ins_cost(DEFAULT_COST*10); | |
| 9418 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 9419 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9420 ins_pipe(partial_subtype_check_pipe); | |
| 9421 %} | |
| 9422 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9423 |
| 0 | 9424 // ============================================================================ |
| 9425 // inlined locking and unlocking | |
| 9426 | |
| 9427 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9428 match(Set pcc (FastLock object box)); | |
| 9429 | |
| 9430 effect(KILL scratch, TEMP scratch2); | |
| 9431 ins_cost(100); | |
| 9432 | |
| 9433 size(4*112); // conservative overestimation ... | |
| 9434 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9435 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 9436 ins_pipe(long_memory_op); | |
| 9437 %} | |
| 9438 | |
| 9439 | |
| 9440 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9441 match(Set pcc (FastUnlock object box)); | |
| 9442 effect(KILL scratch, TEMP scratch2); | |
| 9443 ins_cost(100); | |
| 9444 | |
| 9445 size(4*120); // conservative overestimation ... | |
| 9446 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9447 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 9448 ins_pipe(long_memory_op); | |
| 9449 %} | |
| 9450 | |
| 9451 // Count and Base registers are fixed because the allocator cannot | |
| 9452 // kill unknown registers. The encodings are generic. | |
| 9453 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 9454 match(Set dummy (ClearArray cnt base)); | |
| 9455 effect(TEMP temp, KILL ccr); | |
| 9456 ins_cost(300); | |
| 9457 format %{ "MOV $cnt,$temp\n" | |
| 9458 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 9459 " BRge loop\t\t! Clearing loop\n" | |
| 9460 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 9461 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 9462 ins_pipe(long_memory_op); | |
| 9463 %} | |
| 9464 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9465 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9466 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9467 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9468 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 9469 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9470 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9471 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 9472 ins_pipe(long_memory_op); |
| 9473 %} | |
| 9474 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9475 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9476 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9477 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9478 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 9479 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9480 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9481 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 9482 ins_pipe(long_memory_op); |
| 9483 %} | |
| 9484 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9485 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9486 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 9487 match(Set result (AryEq ary1 ary2)); |
| 9488 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 9489 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9490 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9491 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 9492 ins_pipe(long_memory_op); |
| 9493 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9494 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9495 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9496 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9497 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9498 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9499 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9500 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9501 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9502 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9503 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9504 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9505 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9506 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9507 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9508 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9509 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9510 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9511 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9512 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9513 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9514 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9515 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9516 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9517 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9518 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9519 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9520 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9521 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9522 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9523 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9524 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9525 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9526 Register Rtmp = $tmp$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9527 __ srl(Rsrc, 1, Rtmp); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9528 __ srl(Rsrc, 0, Rdst); |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9529 __ or3(Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9530 __ srl(Rdst, 2, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9531 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9532 __ srl(Rdst, 4, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9533 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9534 __ srl(Rdst, 8, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9535 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9536 __ srl(Rdst, 16, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9537 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9538 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9539 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9540 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9541 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9542 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9543 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9544 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9545 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9546 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9547 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9548 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9549 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9550 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9551 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9552 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9553 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9554 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9555 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9556 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9557 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9558 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9559 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9560 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9561 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9562 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9563 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9564 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9565 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9566 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9567 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9568 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9569 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9570 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9571 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9572 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9573 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9574 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9575 Register Rtmp = $tmp$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9576 __ srlx(Rsrc, 1, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9577 __ or3(Rsrc, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9578 __ srlx(Rdst, 2, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9579 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9580 __ srlx(Rdst, 4, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9581 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9582 __ srlx(Rdst, 8, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9583 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9584 __ srlx(Rdst, 16, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9585 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9586 __ srlx(Rdst, 32, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9587 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9588 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9589 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9590 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9591 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9592 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9593 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9594 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9595 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9596 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9597 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9598 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9599 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9600 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9601 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9602 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9603 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9604 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9605 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9606 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9607 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9608 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9609 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9610 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9611 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9612 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9613 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9614 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9615 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9616 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9617 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9618 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9619 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9620 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9621 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9622 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9623 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9624 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9625 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9626 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9627 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9628 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9629 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9630 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9631 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9632 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9633 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9634 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9635 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9636 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9637 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9638 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9639 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9640 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9641 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9642 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9643 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9644 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9645 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9646 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9647 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9648 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9649 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9650 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9651 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9652 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9653 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9654 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9655 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9656 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9657 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9658 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9659 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9660 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9661 |
| 0 | 9662 // ============================================================================ |
| 9663 //------------Bytes reverse-------------------------------------------------- | |
| 9664 | |
| 9665 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 9666 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9667 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9668 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9669 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9670 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9671 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9672 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9673 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9674 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9675 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9676 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9677 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9678 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9679 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9680 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9681 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9682 match(Set dst (ReverseBytesL src)); |
| 0 | 9683 |
| 9684 // Op cost is artificially doubled to make sure that load or store | |
| 9685 // instructions are preferred over this one which requires a spill | |
| 9686 // onto a stack slot. | |
| 9687 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9688 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9689 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9690 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9691 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9692 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9693 %} |
| 0 | 9694 ins_pipe( iload_mem ); |
| 9695 %} | |
| 9696 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9697 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9698 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9699 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9700 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9701 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9702 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9703 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9704 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9705 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9706 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9707 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9708 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9709 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9710 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9711 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9712 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9713 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9714 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9715 match(Set dst (ReverseBytesS src)); |
| 0 | 9716 |
| 9717 // Op cost is artificially doubled to make sure that load or store | |
| 9718 // instructions are preferred over this one which requires a spill | |
| 9719 // onto a stack slot. | |
| 9720 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9721 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9722 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9723 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9724 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9725 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9726 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9727 %} |
| 0 | 9728 ins_pipe( iload_mem ); |
| 9729 %} | |
| 9730 | |
| 9731 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9732 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 9733 match(Set dst (ReverseBytesI (LoadI src))); |
| 9734 | |
| 9735 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9736 size(4); |
| 0 | 9737 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 9738 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9739 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9740 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9741 %} |
| 0 | 9742 ins_pipe(iload_mem); |
| 9743 %} | |
| 9744 | |
| 9745 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9746 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 9747 match(Set dst (ReverseBytesL (LoadL src))); |
| 9748 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9749 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9750 size(4); |
| 0 | 9751 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 9752 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9753 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9754 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9755 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9756 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9757 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9758 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9759 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9760 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9761 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9762 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9763 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9764 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9765 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9766 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9767 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9768 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9769 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9770 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9771 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9772 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9773 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9774 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9775 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9776 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9777 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9778 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9779 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9780 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9781 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9782 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9783 %} |
| 0 | 9784 ins_pipe(iload_mem); |
| 9785 %} | |
| 9786 | |
| 9787 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9788 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 9789 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 9790 | |
| 9791 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9792 size(4); |
| 0 | 9793 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 9794 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9795 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9796 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9797 %} |
| 0 | 9798 ins_pipe(istore_mem_reg); |
| 9799 %} | |
| 9800 | |
| 9801 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9802 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 9803 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 9804 | |
| 9805 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9806 size(4); |
| 0 | 9807 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 9808 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9809 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9810 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9811 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9812 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9813 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9814 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9815 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9816 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9817 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9818 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9819 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9820 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9821 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9822 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9823 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9824 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9825 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9826 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9827 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9828 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9829 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9830 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9831 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9832 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9833 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9834 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9835 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9836 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9837 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9838 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9839 %} |
| 0 | 9840 ins_pipe(istore_mem_reg); |
| 9841 %} | |
| 9842 | |
| 9843 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 9844 // These must follow all instruction definitions as they use the names | |
| 9845 // defined in the instructions definitions. | |
| 9846 // | |
| 605 | 9847 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 9848 // |
| 9849 // peepconstraint %{ | |
| 9850 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 9851 // [, ...] ); | |
| 9852 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 9853 // | |
| 9854 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 9855 // // provide an instruction_number.operand_name for each operand that appears | |
| 9856 // // in the replacement instruction's match rule | |
| 9857 // | |
| 9858 // ---------VM FLAGS--------------------------------------------------------- | |
| 9859 // | |
| 9860 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 9861 // | |
| 9862 // Each peephole rule is given an identifying number starting with zero and | |
| 9863 // increasing by one in the order seen by the parser. An individual peephole | |
| 9864 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 9865 // on the command-line. | |
| 9866 // | |
| 9867 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 9868 // | |
| 9869 // Only match adjacent instructions in same basic block | |
| 9870 // Only equality constraints | |
| 9871 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 9872 // Only one replacement instruction | |
| 9873 // | |
| 9874 // ---------EXAMPLE---------------------------------------------------------- | |
| 9875 // | |
| 9876 // // pertinent parts of existing instructions in architecture description | |
| 9877 // instruct movI(eRegI dst, eRegI src) %{ | |
| 9878 // match(Set dst (CopyI src)); | |
| 9879 // %} | |
| 9880 // | |
| 9881 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 9882 // match(Set dst (AddI dst src)); | |
| 9883 // effect(KILL cr); | |
| 9884 // %} | |
| 9885 // | |
| 9886 // // Change (inc mov) to lea | |
| 9887 // peephole %{ | |
| 9888 // // increment preceeded by register-register move | |
| 9889 // peepmatch ( incI_eReg movI ); | |
| 9890 // // require that the destination register of the increment | |
| 9891 // // match the destination register of the move | |
| 9892 // peepconstraint ( 0.dst == 1.dst ); | |
| 9893 // // construct a replacement instruction that sets | |
| 9894 // // the destination to ( move's source register + one ) | |
| 9895 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 9896 // %} | |
| 9897 // | |
| 9898 | |
| 9899 // // Change load of spilled value to only a spill | |
| 9900 // instruct storeI(memory mem, eRegI src) %{ | |
| 9901 // match(Set mem (StoreI mem src)); | |
| 9902 // %} | |
| 9903 // | |
| 9904 // instruct loadI(eRegI dst, memory mem) %{ | |
| 9905 // match(Set dst (LoadI mem)); | |
| 9906 // %} | |
| 9907 // | |
| 9908 // peephole %{ | |
| 9909 // peepmatch ( loadI storeI ); | |
| 9910 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 9911 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 9912 // %} | |
| 9913 | |
| 9914 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 9915 // These must follow all instruction definitions as they use the names | |
| 9916 // defined in the instructions definitions. | |
| 9917 // | |
| 9918 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 9919 | |
| 9920 //----------PIPELINE----------------------------------------------------------- | |
| 9921 // Rules which define the behavior of the target architectures pipeline. |