Mercurial > hg > truffle
annotate src/share/vm/opto/chaitin.cpp @ 12355:cefad50507d8
Merge with hs25-b53
| author | Gilles Duboscq <duboscq@ssw.jku.at> |
|---|---|
| date | Fri, 11 Oct 2013 10:38:03 +0200 |
| parents | 8c83625e3a53 |
| children | 303c352ba1a8 15120a36272d |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
10999
693e4d04fd09
8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents:
10111
diff
changeset
|
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1012
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1012
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1012
diff
changeset
|
21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "compiler/compileLog.hpp" | |
| 27 #include "compiler/oopMap.hpp" | |
| 28 #include "memory/allocation.inline.hpp" | |
| 29 #include "opto/addnode.hpp" | |
| 30 #include "opto/block.hpp" | |
| 31 #include "opto/callnode.hpp" | |
| 32 #include "opto/cfgnode.hpp" | |
| 33 #include "opto/chaitin.hpp" | |
| 34 #include "opto/coalesce.hpp" | |
| 35 #include "opto/connode.hpp" | |
| 36 #include "opto/idealGraphPrinter.hpp" | |
| 37 #include "opto/indexSet.hpp" | |
| 38 #include "opto/machnode.hpp" | |
| 39 #include "opto/memnode.hpp" | |
| 40 #include "opto/opcodes.hpp" | |
| 41 #include "opto/rootnode.hpp" | |
| 0 | 42 |
| 43 #ifndef PRODUCT | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
44 void LRG::dump() const { |
| 0 | 45 ttyLocker ttyl; |
| 46 tty->print("%d ",num_regs()); | |
| 47 _mask.dump(); | |
| 48 if( _msize_valid ) { | |
| 49 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); | |
| 50 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size()); | |
| 51 } else { | |
| 52 tty->print(", #?(%d) ",_mask.Size()); | |
| 53 } | |
| 54 | |
| 55 tty->print("EffDeg: "); | |
| 56 if( _degree_valid ) tty->print( "%d ", _eff_degree ); | |
| 57 else tty->print("? "); | |
| 58 | |
|
295
ea18057223c4
6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents:
196
diff
changeset
|
59 if( is_multidef() ) { |
| 0 | 60 tty->print("MultiDef "); |
| 61 if (_defs != NULL) { | |
| 62 tty->print("("); | |
| 63 for (int i = 0; i < _defs->length(); i++) { | |
| 64 tty->print("N%d ", _defs->at(i)->_idx); | |
| 65 } | |
| 66 tty->print(") "); | |
| 67 } | |
| 68 } | |
| 69 else if( _def == 0 ) tty->print("Dead "); | |
| 70 else tty->print("Def: N%d ",_def->_idx); | |
| 71 | |
| 72 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); | |
| 73 // Flags | |
| 74 if( _is_oop ) tty->print("Oop "); | |
| 75 if( _is_float ) tty->print("Float "); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
76 if( _is_vector ) tty->print("Vector "); |
| 0 | 77 if( _was_spilled1 ) tty->print("Spilled "); |
| 78 if( _was_spilled2 ) tty->print("Spilled2 "); | |
| 79 if( _direct_conflict ) tty->print("Direct_conflict "); | |
| 80 if( _fat_proj ) tty->print("Fat "); | |
| 81 if( _was_lo ) tty->print("Lo "); | |
| 82 if( _has_copy ) tty->print("Copy "); | |
| 83 if( _at_risk ) tty->print("Risk "); | |
| 84 | |
| 85 if( _must_spill ) tty->print("Must_spill "); | |
| 86 if( _is_bound ) tty->print("Bound "); | |
| 87 if( _msize_valid ) { | |
| 88 if( _degree_valid && lo_degree() ) tty->print("Trivial "); | |
| 89 } | |
| 90 | |
| 91 tty->cr(); | |
| 92 } | |
| 93 #endif | |
| 94 | |
| 95 // Compute score from cost and area. Low score is best to spill. | |
| 96 static double raw_score( double cost, double area ) { | |
| 97 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; | |
| 98 } | |
| 99 | |
| 100 double LRG::score() const { | |
| 101 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost. | |
| 102 // Bigger area lowers score, encourages spilling this live range. | |
| 103 // Bigger cost raise score, prevents spilling this live range. | |
| 104 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer | |
| 105 // to turn a divide by a constant into a multiply by the reciprical). | |
| 106 double score = raw_score( _cost, _area); | |
| 107 | |
| 108 // Account for area. Basically, LRGs covering large areas are better | |
| 109 // to spill because more other LRGs get freed up. | |
| 110 if( _area == 0.0 ) // No area? Then no progress to spill | |
| 111 return 1e35; | |
| 112 | |
| 113 if( _was_spilled2 ) // If spilled once before, we are unlikely | |
| 114 return score + 1e30; // to make progress again. | |
| 115 | |
| 116 if( _cost >= _area*3.0 ) // Tiny area relative to cost | |
| 117 return score + 1e17; // Probably no progress to spill | |
| 118 | |
| 119 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost | |
| 120 return score + 1e10; // Likely no progress to spill | |
| 121 | |
| 122 return score; | |
| 123 } | |
| 124 | |
| 125 #define NUMBUCKS 3 | |
| 126 | |
| 10111 | 127 // Straight out of Tarjan's union-find algorithm |
| 128 uint LiveRangeMap::find_compress(uint lrg) { | |
| 129 uint cur = lrg; | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
130 uint next = _uf_map.at(cur); |
| 10111 | 131 while (next != cur) { // Scan chain of equivalences |
| 132 assert( next < cur, "always union smaller"); | |
| 133 cur = next; // until find a fixed-point | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
134 next = _uf_map.at(cur); |
| 10111 | 135 } |
| 136 | |
| 137 // Core of union-find algorithm: update chain of | |
| 138 // equivalences to be equal to the root. | |
| 139 while (lrg != next) { | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
140 uint tmp = _uf_map.at(lrg); |
|
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
141 _uf_map.at_put(lrg, next); |
| 10111 | 142 lrg = tmp; |
| 143 } | |
| 144 return lrg; | |
| 145 } | |
| 146 | |
| 147 // Reset the Union-Find map to identity | |
| 148 void LiveRangeMap::reset_uf_map(uint max_lrg_id) { | |
| 149 _max_lrg_id= max_lrg_id; | |
| 150 // Force the Union-Find mapping to be at least this large | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
151 _uf_map.at_put_grow(_max_lrg_id, 0); |
| 10111 | 152 // Initialize it to be the ID mapping. |
| 153 for (uint i = 0; i < _max_lrg_id; ++i) { | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
154 _uf_map.at_put(i, i); |
| 10111 | 155 } |
| 156 } | |
| 157 | |
| 158 // Make all Nodes map directly to their final live range; no need for | |
| 159 // the Union-Find mapping after this call. | |
| 160 void LiveRangeMap::compress_uf_map_for_nodes() { | |
| 161 // For all Nodes, compress mapping | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
162 uint unique = _names.length(); |
| 10111 | 163 for (uint i = 0; i < unique; ++i) { |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
164 uint lrg = _names.at(i); |
| 10111 | 165 uint compressed_lrg = find(lrg); |
| 166 if (lrg != compressed_lrg) { | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
167 _names.at_put(i, compressed_lrg); |
| 10111 | 168 } |
| 169 } | |
| 170 } | |
| 171 | |
| 172 // Like Find above, but no path compress, so bad asymptotic behavior | |
| 173 uint LiveRangeMap::find_const(uint lrg) const { | |
| 174 if (!lrg) { | |
| 175 return lrg; // Ignore the zero LRG | |
| 176 } | |
| 177 | |
| 178 // Off the end? This happens during debugging dumps when you got | |
| 179 // brand new live ranges but have not told the allocator yet. | |
| 180 if (lrg >= _max_lrg_id) { | |
| 181 return lrg; | |
| 182 } | |
| 183 | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
184 uint next = _uf_map.at(lrg); |
| 10111 | 185 while (next != lrg) { // Scan chain of equivalences |
| 186 assert(next < lrg, "always union smaller"); | |
| 187 lrg = next; // until find a fixed-point | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
188 next = _uf_map.at(lrg); |
| 10111 | 189 } |
| 190 return next; | |
| 191 } | |
| 192 | |
| 0 | 193 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) |
| 194 : PhaseRegAlloc(unique, cfg, matcher, | |
| 195 #ifndef PRODUCT | |
| 196 print_chaitin_statistics | |
| 197 #else | |
| 198 NULL | |
| 199 #endif | |
| 10111 | 200 ) |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
201 , _lrg_map(Thread::current()->resource_area(), unique) |
| 10111 | 202 , _live(0) |
| 203 , _spilled_once(Thread::current()->resource_area()) | |
| 204 , _spilled_twice(Thread::current()->resource_area()) | |
| 205 , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0) | |
| 206 , _oldphi(unique) | |
| 0 | 207 #ifndef PRODUCT |
| 208 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) | |
| 209 #endif | |
| 210 { | |
| 211 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) | |
| 673 | 212 |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
213 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); |
| 673 | 214 |
| 0 | 215 // Build a list of basic blocks, sorted by frequency |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
216 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
| 0 | 217 // Experiment with sorting strategies to speed compilation |
| 218 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket | |
| 219 Block **buckets[NUMBUCKS]; // Array of buckets | |
| 220 uint buckcnt[NUMBUCKS]; // Array of bucket counters | |
| 221 double buckval[NUMBUCKS]; // Array of bucket value cutoffs | |
| 10111 | 222 for (uint i = 0; i < NUMBUCKS; i++) { |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
223 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
| 0 | 224 buckcnt[i] = 0; |
| 225 // Bump by three orders of magnitude each time | |
| 226 cutoff *= 0.001; | |
| 227 buckval[i] = cutoff; | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
228 for (uint j = 0; j < _cfg.number_of_blocks(); j++) { |
| 0 | 229 buckets[i][j] = NULL; |
| 230 } | |
| 231 } | |
| 232 // Sort blocks into buckets | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
233 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
| 10111 | 234 for (uint j = 0; j < NUMBUCKS; j++) { |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
235 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) { |
| 0 | 236 // Assign block to end of list for appropriate bucket |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
237 buckets[j][buckcnt[j]++] = _cfg.get_block(i); |
| 10111 | 238 break; // kick out of inner loop |
| 0 | 239 } |
| 240 } | |
| 241 } | |
| 242 // Dump buckets into final block array | |
| 243 uint blkcnt = 0; | |
| 10111 | 244 for (uint i = 0; i < NUMBUCKS; i++) { |
| 245 for (uint j = 0; j < buckcnt[i]; j++) { | |
| 0 | 246 _blks[blkcnt++] = buckets[i][j]; |
| 247 } | |
| 248 } | |
| 249 | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
250 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled"); |
| 0 | 251 } |
| 252 | |
| 10111 | 253 // union 2 sets together. |
| 254 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { | |
| 255 uint src = _lrg_map.find(src_n); | |
| 256 uint dst = _lrg_map.find(dst_n); | |
| 257 assert(src, ""); | |
| 258 assert(dst, ""); | |
| 259 assert(src < _lrg_map.max_lrg_id(), "oob"); | |
| 260 assert(dst < _lrg_map.max_lrg_id(), "oob"); | |
| 261 assert(src < dst, "always union smaller"); | |
| 262 _lrg_map.uf_map(dst, src); | |
| 263 } | |
| 264 | |
| 265 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { | |
| 266 // Make the Node->LRG mapping | |
| 267 _lrg_map.extend(x->_idx,lrg); | |
| 268 // Make the Union-Find mapping an identity function | |
| 269 _lrg_map.uf_extend(lrg, lrg); | |
| 270 } | |
| 271 | |
| 272 | |
|
12075
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
273 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) { |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
274 assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections"); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
275 DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); ) |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
276 int found_projs = 0; |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
277 uint cnt = orig->outcnt(); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
278 for (uint i = 0; i < cnt; i++) { |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
279 Node* proj = orig->raw_out(i); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
280 if (proj->is_MachProj()) { |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
281 assert(proj->outcnt() == 0, "only kill projections are expected here"); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
282 assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections"); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
283 found_projs++; |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
284 // Copy kill projections after the cloned node |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
285 Node* kills = proj->clone(); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
286 kills->set_req(0, copy); |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
287 b->insert_node(kills, idx++); |
|
12075
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
288 _cfg.map_node_to_block(kills, b); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
289 new_lrg(kills, max_lrg_id++); |
|
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
290 } |
| 10111 | 291 } |
|
12075
4b2838704fd5
8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents:
12071
diff
changeset
|
292 return found_projs; |
| 10111 | 293 } |
| 294 | |
| 295 // Renumber the live ranges to compact them. Makes the IFG smaller. | |
| 296 void PhaseChaitin::compact() { | |
| 297 // Current the _uf_map contains a series of short chains which are headed | |
| 298 // by a self-cycle. All the chains run from big numbers to little numbers. | |
| 299 // The Find() call chases the chains & shortens them for the next Find call. | |
| 300 // We are going to change this structure slightly. Numbers above a moving | |
| 301 // wave 'i' are unchanged. Numbers below 'j' point directly to their | |
| 302 // compacted live range with no further chaining. There are no chains or | |
| 303 // cycles below 'i', so the Find call no longer works. | |
| 304 uint j=1; | |
| 305 uint i; | |
| 306 for (i = 1; i < _lrg_map.max_lrg_id(); i++) { | |
| 307 uint lr = _lrg_map.uf_live_range_id(i); | |
| 308 // Ignore unallocated live ranges | |
| 309 if (!lr) { | |
| 310 continue; | |
| 311 } | |
| 312 assert(lr <= i, ""); | |
| 313 _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr)); | |
| 314 } | |
| 315 // Now change the Node->LR mapping to reflect the compacted names | |
| 316 uint unique = _lrg_map.size(); | |
| 317 for (i = 0; i < unique; i++) { | |
| 318 uint lrg_id = _lrg_map.live_range_id(i); | |
| 319 _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id)); | |
| 320 } | |
| 321 | |
| 322 // Reset the Union-Find mapping | |
| 323 _lrg_map.reset_uf_map(j); | |
| 324 } | |
| 325 | |
| 0 | 326 void PhaseChaitin::Register_Allocate() { |
| 327 | |
| 328 // Above the OLD FP (and in registers) are the incoming arguments. Stack | |
| 329 // slots in this area are called "arg_slots". Above the NEW FP (and in | |
| 330 // registers) is the outgoing argument area; above that is the spill/temp | |
| 331 // area. These are all "frame_slots". Arg_slots start at the zero | |
| 332 // stack_slots and count up to the known arg_size. Frame_slots start at | |
| 333 // the stack_slot #arg_size and go up. After allocation I map stack | |
| 334 // slots to actual offsets. Stack-slots in the arg_slot area are biased | |
| 335 // by the frame_size; stack-slots in the frame_slot area are biased by 0. | |
| 336 | |
| 337 _trip_cnt = 0; | |
| 338 _alternate = 0; | |
| 339 _matcher._allocation_started = true; | |
| 340 | |
| 6632 | 341 ResourceArea split_arena; // Arena for Split local resources |
| 0 | 342 ResourceArea live_arena; // Arena for liveness & IFG info |
| 343 ResourceMark rm(&live_arena); | |
| 344 | |
| 345 // Need live-ness for the IFG; need the IFG for coalescing. If the | |
| 346 // liveness is JUST for coalescing, then I can get some mileage by renaming | |
| 347 // all copy-related live ranges low and then using the max copy-related | |
| 348 // live range as a cut-off for LIVE and the IFG. In other words, I can | |
| 349 // build a subset of LIVE and IFG just for copies. | |
| 10111 | 350 PhaseLive live(_cfg, _lrg_map.names(), &live_arena); |
| 0 | 351 |
| 352 // Need IFG for coalescing and coloring | |
| 10111 | 353 PhaseIFG ifg(&live_arena); |
| 0 | 354 _ifg = &ifg; |
| 355 | |
| 356 // Come out of SSA world to the Named world. Assign (virtual) registers to | |
| 357 // Nodes. Use the same register for all inputs and the output of PhiNodes | |
| 358 // - effectively ending SSA form. This requires either coalescing live | |
| 359 // ranges or inserting copies. For the moment, we insert "virtual copies" | |
| 360 // - we pretend there is a copy prior to each Phi in predecessor blocks. | |
| 361 // We will attempt to coalesce such "virtual copies" before we manifest | |
| 362 // them for real. | |
| 363 de_ssa(); | |
| 364 | |
|
566
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
365 #ifdef ASSERT |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
366 // Veify the graph before RA. |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
367 verify(&live_arena); |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
368 #endif |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
369 |
| 0 | 370 { |
| 371 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 372 _live = NULL; // Mark live as being not available | |
| 373 rm.reset_to_mark(); // Reclaim working storage | |
| 374 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 375 ifg.init(_lrg_map.max_lrg_id()); // Empty IFG |
| 0 | 376 gather_lrg_masks( false ); // Collect LRG masks |
| 10111 | 377 live.compute(_lrg_map.max_lrg_id()); // Compute liveness |
| 0 | 378 _live = &live; // Mark LIVE as being available |
| 379 } | |
| 380 | |
| 381 // Base pointers are currently "used" by instructions which define new | |
| 382 // derived pointers. This makes base pointers live up to the where the | |
| 383 // derived pointer is made, but not beyond. Really, they need to be live | |
| 384 // across any GC point where the derived value is live. So this code looks | |
| 385 // at all the GC points, and "stretches" the live range of any base pointer | |
| 386 // to the GC point. | |
| 10111 | 387 if (stretch_base_pointer_live_ranges(&live_arena)) { |
| 388 NOT_PRODUCT(Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler);) | |
| 0 | 389 // Since some live range stretched, I need to recompute live |
| 390 _live = NULL; | |
| 391 rm.reset_to_mark(); // Reclaim working storage | |
| 392 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 393 ifg.init(_lrg_map.max_lrg_id()); |
| 394 gather_lrg_masks(false); | |
| 395 live.compute(_lrg_map.max_lrg_id()); | |
| 0 | 396 _live = &live; |
| 397 } | |
| 398 // Create the interference graph using virtual copies | |
| 10111 | 399 build_ifg_virtual(); // Include stack slots this time |
| 0 | 400 |
| 401 // Aggressive (but pessimistic) copy coalescing. | |
| 402 // This pass works on virtual copies. Any virtual copies which are not | |
| 403 // coalesced get manifested as actual copies | |
| 404 { | |
| 405 // The IFG is/was triangular. I am 'squaring it up' so Union can run | |
| 406 // faster. Union requires a 'for all' operation which is slow on the | |
| 407 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' - | |
| 408 // meaning I can visit all the Nodes neighbors less than a Node in time | |
| 409 // O(# of neighbors), but I have to visit all the Nodes greater than a | |
| 410 // given Node and search them for an instance, i.e., time O(#MaxLRG)). | |
| 411 _ifg->SquareUp(); | |
| 412 | |
| 10111 | 413 PhaseAggressiveCoalesce coalesce(*this); |
| 414 coalesce.coalesce_driver(); | |
| 0 | 415 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do |
| 416 // not match the Phi itself, insert a copy. | |
| 417 coalesce.insert_copies(_matcher); | |
|
10999
693e4d04fd09
8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents:
10111
diff
changeset
|
418 if (C->failing()) { |
|
693e4d04fd09
8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents:
10111
diff
changeset
|
419 return; |
|
693e4d04fd09
8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
parents:
10111
diff
changeset
|
420 } |
| 0 | 421 } |
| 422 | |
| 423 // After aggressive coalesce, attempt a first cut at coloring. | |
| 424 // To color, we need the IFG and for that we need LIVE. | |
| 425 { | |
| 426 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 427 _live = NULL; | |
| 428 rm.reset_to_mark(); // Reclaim working storage | |
| 429 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 430 ifg.init(_lrg_map.max_lrg_id()); |
| 0 | 431 gather_lrg_masks( true ); |
| 10111 | 432 live.compute(_lrg_map.max_lrg_id()); |
| 0 | 433 _live = &live; |
| 434 } | |
| 435 | |
| 436 // Build physical interference graph | |
| 437 uint must_spill = 0; | |
| 10111 | 438 must_spill = build_ifg_physical(&live_arena); |
| 0 | 439 // If we have a guaranteed spill, might as well spill now |
| 10111 | 440 if (must_spill) { |
| 441 if(!_lrg_map.max_lrg_id()) { | |
| 442 return; | |
| 443 } | |
| 0 | 444 // Bail out if unique gets too large (ie - unique > MaxNodeLimit) |
| 445 C->check_node_count(10*must_spill, "out of nodes before split"); | |
| 10111 | 446 if (C->failing()) { |
| 447 return; | |
| 448 } | |
| 449 | |
| 450 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere | |
| 451 _lrg_map.set_max_lrg_id(new_max_lrg_id); | |
| 0 | 452 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) |
| 453 // or we failed to split | |
| 454 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split"); | |
| 10111 | 455 if (C->failing()) { |
| 456 return; | |
| 457 } | |
| 0 | 458 |
| 10111 | 459 NOT_PRODUCT(C->verify_graph_edges();) |
| 0 | 460 |
| 461 compact(); // Compact LRGs; return new lower max lrg | |
| 462 | |
| 463 { | |
| 464 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 465 _live = NULL; | |
| 466 rm.reset_to_mark(); // Reclaim working storage | |
| 467 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 468 ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph |
| 0 | 469 gather_lrg_masks( true ); // Collect intersect mask |
| 10111 | 470 live.compute(_lrg_map.max_lrg_id()); // Compute LIVE |
| 0 | 471 _live = &live; |
| 472 } | |
| 10111 | 473 build_ifg_physical(&live_arena); |
| 0 | 474 _ifg->SquareUp(); |
| 475 _ifg->Compute_Effective_Degree(); | |
| 476 // Only do conservative coalescing if requested | |
| 10111 | 477 if (OptoCoalesce) { |
| 0 | 478 // Conservative (and pessimistic) copy coalescing of those spills |
| 10111 | 479 PhaseConservativeCoalesce coalesce(*this); |
| 0 | 480 // If max live ranges greater than cutoff, don't color the stack. |
| 481 // This cutoff can be larger than below since it is only done once. | |
| 10111 | 482 coalesce.coalesce_driver(); |
| 0 | 483 } |
| 10111 | 484 _lrg_map.compress_uf_map_for_nodes(); |
| 0 | 485 |
| 486 #ifdef ASSERT | |
|
566
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
487 verify(&live_arena, true); |
| 0 | 488 #endif |
| 489 } else { | |
| 490 ifg.SquareUp(); | |
| 491 ifg.Compute_Effective_Degree(); | |
| 492 #ifdef ASSERT | |
| 493 set_was_low(); | |
| 494 #endif | |
| 495 } | |
| 496 | |
| 497 // Prepare for Simplify & Select | |
| 498 cache_lrg_info(); // Count degree of LRGs | |
| 499 | |
| 500 // Simplify the InterFerence Graph by removing LRGs of low degree. | |
| 501 // LRGs of low degree are trivially colorable. | |
| 502 Simplify(); | |
| 503 | |
| 504 // Select colors by re-inserting LRGs back into the IFG in reverse order. | |
| 505 // Return whether or not something spills. | |
| 506 uint spills = Select( ); | |
| 507 | |
| 508 // If we spill, split and recycle the entire thing | |
| 509 while( spills ) { | |
| 510 if( _trip_cnt++ > 24 ) { | |
| 511 DEBUG_ONLY( dump_for_spill_split_recycle(); ) | |
| 512 if( _trip_cnt > 27 ) { | |
| 513 C->record_method_not_compilable("failed spill-split-recycle sanity check"); | |
| 514 return; | |
| 515 } | |
| 516 } | |
| 517 | |
| 10111 | 518 if (!_lrg_map.max_lrg_id()) { |
| 519 return; | |
| 520 } | |
| 521 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere | |
| 522 _lrg_map.set_max_lrg_id(new_max_lrg_id); | |
| 0 | 523 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) |
| 10111 | 524 C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split"); |
| 525 if (C->failing()) { | |
| 526 return; | |
| 527 } | |
| 0 | 528 |
| 10111 | 529 compact(); // Compact LRGs; return new lower max lrg |
| 0 | 530 |
| 531 // Nuke the live-ness and interference graph and LiveRanGe info | |
| 532 { | |
| 533 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 534 _live = NULL; | |
| 535 rm.reset_to_mark(); // Reclaim working storage | |
| 536 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 537 ifg.init(_lrg_map.max_lrg_id()); |
| 0 | 538 |
| 539 // Create LiveRanGe array. | |
| 540 // Intersect register masks for all USEs and DEFs | |
| 10111 | 541 gather_lrg_masks(true); |
| 542 live.compute(_lrg_map.max_lrg_id()); | |
| 0 | 543 _live = &live; |
| 544 } | |
| 10111 | 545 must_spill = build_ifg_physical(&live_arena); |
| 0 | 546 _ifg->SquareUp(); |
| 547 _ifg->Compute_Effective_Degree(); | |
| 548 | |
| 549 // Only do conservative coalescing if requested | |
| 10111 | 550 if (OptoCoalesce) { |
| 0 | 551 // Conservative (and pessimistic) copy coalescing |
| 10111 | 552 PhaseConservativeCoalesce coalesce(*this); |
| 0 | 553 // Check for few live ranges determines how aggressive coalesce is. |
| 10111 | 554 coalesce.coalesce_driver(); |
| 0 | 555 } |
| 10111 | 556 _lrg_map.compress_uf_map_for_nodes(); |
| 0 | 557 #ifdef ASSERT |
|
566
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
558 verify(&live_arena, true); |
| 0 | 559 #endif |
| 560 cache_lrg_info(); // Count degree of LRGs | |
| 561 | |
| 562 // Simplify the InterFerence Graph by removing LRGs of low degree. | |
| 563 // LRGs of low degree are trivially colorable. | |
| 564 Simplify(); | |
| 565 | |
| 566 // Select colors by re-inserting LRGs back into the IFG in reverse order. | |
| 567 // Return whether or not something spills. | |
| 10111 | 568 spills = Select(); |
| 0 | 569 } |
| 570 | |
| 571 // Count number of Simplify-Select trips per coloring success. | |
| 572 _allocator_attempts += _trip_cnt + 1; | |
| 573 _allocator_successes += 1; | |
| 574 | |
| 575 // Peephole remove copies | |
| 576 post_allocate_copy_removal(); | |
| 577 | |
|
566
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
578 #ifdef ASSERT |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
579 // Veify the graph after RA. |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
580 verify(&live_arena); |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
581 #endif |
|
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
550
diff
changeset
|
582 |
| 0 | 583 // max_reg is past the largest *register* used. |
| 584 // Convert that to a frame_slot number. | |
| 10111 | 585 if (_max_reg <= _matcher._new_SP) { |
| 0 | 586 _framesize = C->out_preserve_stack_slots(); |
| 10111 | 587 } |
| 588 else { | |
| 589 _framesize = _max_reg -_matcher._new_SP; | |
| 590 } | |
| 0 | 591 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough"); |
| 592 | |
| 593 // This frame must preserve the required fp alignment | |
|
419
0bf25c4807f9
6761594: framesize rounding code rounds using wrong units leading to slightly oversized frames
never
parents:
295
diff
changeset
|
594 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots()); |
| 0 | 595 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" ); |
| 596 #ifndef PRODUCT | |
| 597 _total_framesize += _framesize; | |
| 10111 | 598 if ((int)_framesize > _max_framesize) { |
| 0 | 599 _max_framesize = _framesize; |
| 10111 | 600 } |
| 0 | 601 #endif |
| 602 | |
| 603 // Convert CISC spills | |
| 604 fixup_spills(); | |
| 605 | |
| 606 // Log regalloc results | |
| 607 CompileLog* log = Compile::current()->log(); | |
| 608 if (log != NULL) { | |
| 609 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing()); | |
| 610 } | |
| 611 | |
| 10111 | 612 if (C->failing()) { |
| 613 return; | |
| 614 } | |
| 0 | 615 |
| 10111 | 616 NOT_PRODUCT(C->verify_graph_edges();) |
| 0 | 617 |
| 618 // Move important info out of the live_arena to longer lasting storage. | |
| 10111 | 619 alloc_node_regs(_lrg_map.size()); |
| 620 for (uint i=0; i < _lrg_map.size(); i++) { | |
| 621 if (_lrg_map.live_range_id(i)) { // Live range associated with Node? | |
| 622 LRG &lrg = lrgs(_lrg_map.live_range_id(i)); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
623 if (!lrg.alive()) { |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
624 set_bad(i); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
625 } else if (lrg.num_regs() == 1) { |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
626 set1(i, lrg.reg()); |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
627 } else { // Must be a register-set |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
628 if (!lrg._fat_proj) { // Must be aligned adjacent register set |
| 0 | 629 // Live ranges record the highest register in their mask. |
| 630 // We want the low register for the AD file writer's convenience. | |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
631 OptoReg::Name hi = lrg.reg(); // Get hi register |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
632 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
633 // We have to use pair [lo,lo+1] even for wide vectors because |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
634 // the rest of code generation works only with pairs. It is safe |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
635 // since for registers encoding only 'lo' is used. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
636 // Second reg from pair is used in ScheduleAndBundle on SPARC where |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
637 // vector max size is 8 which corresponds to registers pair. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
638 // It is also used in BuildOopMaps but oop operations are not |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
639 // vectorized. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
640 set2(i, lo); |
| 0 | 641 } else { // Misaligned; extract 2 bits |
| 642 OptoReg::Name hi = lrg.reg(); // Get hi register | |
| 643 lrg.Remove(hi); // Yank from mask | |
| 644 int lo = lrg.mask().find_first_elem(); // Find lo | |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
645 set_pair(i, hi, lo); |
| 0 | 646 } |
| 647 } | |
| 648 if( lrg._is_oop ) _node_oops.set(i); | |
| 649 } else { | |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
650 set_bad(i); |
| 0 | 651 } |
| 652 } | |
| 653 | |
| 654 // Done! | |
| 655 _live = NULL; | |
| 656 _ifg = NULL; | |
| 657 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope | |
| 658 } | |
| 659 | |
| 660 void PhaseChaitin::de_ssa() { | |
| 661 // Set initial Names for all Nodes. Most Nodes get the virtual register | |
| 662 // number. A few get the ZERO live range number. These do not | |
| 663 // get allocated, but instead rely on correct scheduling to ensure that | |
| 664 // only one instance is simultaneously live at a time. | |
| 665 uint lr_counter = 1; | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
666 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
667 Block* block = _cfg.get_block(i); |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
668 uint cnt = block->number_of_nodes(); |
| 0 | 669 |
| 670 // Handle all the normal Nodes in the block | |
| 671 for( uint j = 0; j < cnt; j++ ) { | |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
672 Node *n = block->get_node(j); |
| 0 | 673 // Pre-color to the zero live range, or pick virtual register |
| 674 const RegMask &rm = n->out_RegMask(); | |
| 10111 | 675 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); |
| 0 | 676 } |
| 677 } | |
|
12254
8c83625e3a53
8024646: Remove LRG_List container, replace it with GrowableArray
adlertz
parents:
12167
diff
changeset
|
678 |
| 0 | 679 // Reset the Union-Find mapping to be identity |
| 10111 | 680 _lrg_map.reset_uf_map(lr_counter); |
| 0 | 681 } |
| 682 | |
| 683 | |
| 684 // Gather LiveRanGe information, including register masks. Modification of | |
| 685 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. | |
| 686 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { | |
| 687 | |
| 688 // Nail down the frame pointer live range | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
689 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr)); |
| 0 | 690 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite |
| 691 | |
| 692 // For all blocks | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
693 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
694 Block* block = _cfg.get_block(i); |
| 0 | 695 |
| 696 // For all instructions | |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
697 for (uint j = 1; j < block->number_of_nodes(); j++) { |
|
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
698 Node* n = block->get_node(j); |
| 0 | 699 uint input_edge_start =1; // Skip control most nodes |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
700 if (n->is_Mach()) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
701 input_edge_start = n->as_Mach()->oper_input_base(); |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
702 } |
| 0 | 703 uint idx = n->is_Copy(); |
| 704 | |
| 705 // Get virtual register number, same as LiveRanGe index | |
| 10111 | 706 uint vreg = _lrg_map.live_range_id(n); |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
707 LRG& lrg = lrgs(vreg); |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
708 if (vreg) { // No vreg means un-allocable (e.g. memory) |
| 0 | 709 |
| 710 // Collect has-copy bit | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
711 if (idx) { |
| 0 | 712 lrg._has_copy = 1; |
| 10111 | 713 uint clidx = _lrg_map.live_range_id(n->in(idx)); |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
714 LRG& copy_src = lrgs(clidx); |
| 0 | 715 copy_src._has_copy = 1; |
| 716 } | |
| 717 | |
| 718 // Check for float-vs-int live range (used in register-pressure | |
| 719 // calculations) | |
| 720 const Type *n_type = n->bottom_type(); | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
721 if (n_type->is_floatingpoint()) { |
| 0 | 722 lrg._is_float = 1; |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
723 } |
| 0 | 724 |
| 725 // Check for twice prior spilling. Once prior spilling might have | |
| 726 // spilled 'soft', 2nd prior spill should have spilled 'hard' and | |
| 727 // further spilling is unlikely to make progress. | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
728 if (_spilled_once.test(n->_idx)) { |
| 0 | 729 lrg._was_spilled1 = 1; |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
730 if (_spilled_twice.test(n->_idx)) { |
| 0 | 731 lrg._was_spilled2 = 1; |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
732 } |
| 0 | 733 } |
| 734 | |
| 735 #ifndef PRODUCT | |
| 736 if (trace_spilling() && lrg._def != NULL) { | |
| 737 // collect defs for MultiDef printing | |
| 738 if (lrg._defs == NULL) { | |
| 1685 | 739 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL); |
| 0 | 740 lrg._defs->append(lrg._def); |
| 741 } | |
| 742 lrg._defs->append(n); | |
| 743 } | |
| 744 #endif | |
| 745 | |
| 746 // Check for a single def LRG; these can spill nicely | |
| 747 // via rematerialization. Flag as NULL for no def found | |
| 748 // yet, or 'n' for single def or -1 for many defs. | |
| 749 lrg._def = lrg._def ? NodeSentinel : n; | |
| 750 | |
| 751 // Limit result register mask to acceptable registers | |
| 752 const RegMask &rm = n->out_RegMask(); | |
| 753 lrg.AND( rm ); | |
| 754 | |
| 755 int ireg = n->ideal_reg(); | |
| 756 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, | |
| 757 "oops must be in Op_RegP's" ); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
758 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
759 // Check for vector live range (only if vector register is used). |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
760 // On SPARC vector uses RegD which could be misaligned so it is not |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
761 // processes as vector in RA. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
762 if (RegMask::is_vector(ireg)) |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
763 lrg._is_vector = 1; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
764 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
765 "vector must be in vector registers"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
766 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
767 // Check for bound register masks |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
768 const RegMask &lrgmask = lrg.mask(); |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
769 if (lrgmask.is_bound(ireg)) { |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
770 lrg._is_bound = 1; |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
771 } |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
772 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
773 // Check for maximum frequency value |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
774 if (lrg._maxfreq < block->_freq) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
775 lrg._maxfreq = block->_freq; |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
776 } |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
777 |
| 0 | 778 // Check for oop-iness, or long/double |
| 779 // Check for multi-kill projection | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
780 switch (ireg) { |
| 0 | 781 case MachProjNode::fat_proj: |
| 782 // Fat projections have size equal to number of registers killed | |
| 783 lrg.set_num_regs(rm.Size()); | |
| 784 lrg.set_reg_pressure(lrg.num_regs()); | |
| 785 lrg._fat_proj = 1; | |
| 786 lrg._is_bound = 1; | |
| 787 break; | |
| 788 case Op_RegP: | |
| 789 #ifdef _LP64 | |
| 790 lrg.set_num_regs(2); // Size is 2 stack words | |
| 791 #else | |
| 792 lrg.set_num_regs(1); // Size is 1 stack word | |
| 793 #endif | |
| 794 // Register pressure is tracked relative to the maximum values | |
| 795 // suggested for that platform, INTPRESSURE and FLOATPRESSURE, | |
| 796 // and relative to other types which compete for the same regs. | |
| 797 // | |
| 798 // The following table contains suggested values based on the | |
| 799 // architectures as defined in each .ad file. | |
| 800 // INTPRESSURE and FLOATPRESSURE may be tuned differently for | |
| 801 // compile-speed or performance. | |
| 802 // Note1: | |
| 803 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1 | |
| 804 // since .ad registers are defined as high and low halves. | |
| 805 // These reg_pressure values remain compatible with the code | |
| 806 // in is_high_pressure() which relates get_invalid_mask_size(), | |
| 807 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE. | |
| 808 // Note2: | |
| 809 // SPARC -d32 has 24 registers available for integral values, | |
| 810 // but only 10 of these are safe for 64-bit longs. | |
| 811 // Using set_reg_pressure(2) for both int and long means | |
| 812 // the allocator will believe it can fit 26 longs into | |
| 813 // registers. Using 2 for longs and 1 for ints means the | |
| 814 // allocator will attempt to put 52 integers into registers. | |
| 815 // The settings below limit this problem to methods with | |
| 816 // many long values which are being run on 32-bit SPARC. | |
| 817 // | |
| 818 // ------------------- reg_pressure -------------------- | |
| 819 // Each entry is reg_pressure_per_value,number_of_regs | |
| 820 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE | |
| 821 // IA32 2 1 1 1 1 6 6 | |
| 822 // IA64 1 1 1 1 1 50 41 | |
| 823 // SPARC 2 2 2 2 2 48 (24) 52 (26) | |
| 824 // SPARCV9 2 2 2 2 2 48 (24) 52 (26) | |
| 825 // AMD64 1 1 1 1 1 14 15 | |
| 826 // ----------------------------------------------------- | |
| 827 #if defined(SPARC) | |
| 828 lrg.set_reg_pressure(2); // use for v9 as well | |
| 829 #else | |
| 830 lrg.set_reg_pressure(1); // normally one value per register | |
| 831 #endif | |
| 832 if( n_type->isa_oop_ptr() ) { | |
| 833 lrg._is_oop = 1; | |
| 834 } | |
| 835 break; | |
| 836 case Op_RegL: // Check for long or double | |
| 837 case Op_RegD: | |
| 838 lrg.set_num_regs(2); | |
| 839 // Define platform specific register pressure | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2016
diff
changeset
|
840 #if defined(SPARC) || defined(ARM) |
| 0 | 841 lrg.set_reg_pressure(2); |
| 842 #elif defined(IA32) | |
| 843 if( ireg == Op_RegL ) { | |
| 844 lrg.set_reg_pressure(2); | |
| 845 } else { | |
| 846 lrg.set_reg_pressure(1); | |
| 847 } | |
| 848 #else | |
| 849 lrg.set_reg_pressure(1); // normally one value per register | |
| 850 #endif | |
| 851 // If this def of a double forces a mis-aligned double, | |
| 852 // flag as '_fat_proj' - really flag as allowing misalignment | |
| 853 // AND changes how we count interferences. A mis-aligned | |
| 854 // double can interfere with TWO aligned pairs, or effectively | |
| 855 // FOUR registers! | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
856 if (rm.is_misaligned_pair()) { |
| 0 | 857 lrg._fat_proj = 1; |
| 858 lrg._is_bound = 1; | |
| 859 } | |
| 860 break; | |
| 861 case Op_RegF: | |
| 862 case Op_RegI: | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
863 case Op_RegN: |
| 0 | 864 case Op_RegFlags: |
| 865 case 0: // not an ideal register | |
| 866 lrg.set_num_regs(1); | |
| 867 #ifdef SPARC | |
| 868 lrg.set_reg_pressure(2); | |
| 869 #else | |
| 870 lrg.set_reg_pressure(1); | |
| 871 #endif | |
| 872 break; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
873 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
874 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
875 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
876 lrg.set_num_regs(RegMask::SlotsPerVecS); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
877 lrg.set_reg_pressure(1); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
878 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
879 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
880 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
881 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
882 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
883 lrg.set_num_regs(RegMask::SlotsPerVecD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
884 lrg.set_reg_pressure(1); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
885 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
886 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
887 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
888 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
889 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
890 lrg.set_num_regs(RegMask::SlotsPerVecX); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
891 lrg.set_reg_pressure(1); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
892 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
893 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
894 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
895 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
896 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
897 lrg.set_num_regs(RegMask::SlotsPerVecY); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
898 lrg.set_reg_pressure(1); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
899 break; |
| 0 | 900 default: |
| 901 ShouldNotReachHere(); | |
| 902 } | |
| 903 } | |
| 904 | |
| 905 // Now do the same for inputs | |
| 906 uint cnt = n->req(); | |
| 907 // Setup for CISC SPILLING | |
| 908 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable; | |
| 909 if( UseCISCSpill && after_aggressive ) { | |
| 910 inp = n->cisc_operand(); | |
| 911 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable ) | |
| 912 // Convert operand number to edge index number | |
| 913 inp = n->as_Mach()->operand_index(inp); | |
| 914 } | |
| 915 // Prepare register mask for each input | |
| 916 for( uint k = input_edge_start; k < cnt; k++ ) { | |
| 10111 | 917 uint vreg = _lrg_map.live_range_id(n->in(k)); |
| 918 if (!vreg) { | |
| 919 continue; | |
| 920 } | |
| 0 | 921 |
| 922 // If this instruction is CISC Spillable, add the flags | |
| 923 // bit to its appropriate input | |
| 924 if( UseCISCSpill && after_aggressive && inp == k ) { | |
| 925 #ifndef PRODUCT | |
| 926 if( TraceCISCSpill ) { | |
| 927 tty->print(" use_cisc_RegMask: "); | |
| 928 n->dump(); | |
| 929 } | |
| 930 #endif | |
| 931 n->as_Mach()->use_cisc_RegMask(); | |
| 932 } | |
| 933 | |
| 934 LRG &lrg = lrgs(vreg); | |
| 935 // // Testing for floating point code shape | |
| 936 // Node *test = n->in(k); | |
| 937 // if( test->is_Mach() ) { | |
| 938 // MachNode *m = test->as_Mach(); | |
| 939 // int op = m->ideal_Opcode(); | |
| 940 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) { | |
| 941 // int zzz = 1; | |
| 942 // } | |
| 943 // } | |
| 944 | |
| 945 // Limit result register mask to acceptable registers. | |
| 946 // Do not limit registers from uncommon uses before | |
| 947 // AggressiveCoalesce. This effectively pre-virtual-splits | |
| 948 // around uncommon uses of common defs. | |
| 949 const RegMask &rm = n->in_RegMask(k); | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
950 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) { |
| 0 | 951 // Since we are BEFORE aggressive coalesce, leave the register |
| 952 // mask untrimmed by the call. This encourages more coalescing. | |
| 953 // Later, AFTER aggressive, this live range will have to spill | |
| 954 // but the spiller handles slow-path calls very nicely. | |
| 955 } else { | |
| 956 lrg.AND( rm ); | |
| 957 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
958 |
| 0 | 959 // Check for bound register masks |
| 960 const RegMask &lrgmask = lrg.mask(); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
961 int kreg = n->in(k)->ideal_reg(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
962 bool is_vect = RegMask::is_vector(kreg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
963 assert(n->in(k)->bottom_type()->isa_vect() == NULL || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
964 is_vect || kreg == Op_RegD, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
965 "vector must be in vector registers"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
966 if (lrgmask.is_bound(kreg)) |
| 0 | 967 lrg._is_bound = 1; |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
968 |
| 0 | 969 // If this use of a double forces a mis-aligned double, |
| 970 // flag as '_fat_proj' - really flag as allowing misalignment | |
| 971 // AND changes how we count interferences. A mis-aligned | |
| 972 // double can interfere with TWO aligned pairs, or effectively | |
| 973 // FOUR registers! | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
974 #ifdef ASSERT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
975 if (is_vect) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
976 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
977 assert(!lrg._fat_proj, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
978 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
979 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
980 #endif |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
981 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) { |
| 0 | 982 lrg._fat_proj = 1; |
| 983 lrg._is_bound = 1; | |
| 984 } | |
| 985 // if the LRG is an unaligned pair, we will have to spill | |
| 986 // so clear the LRG's register mask if it is not already spilled | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
987 if (!is_vect && !n->is_SpillCopy() && |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
988 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
989 lrgmask.is_misaligned_pair()) { |
| 0 | 990 lrg.Clear(); |
| 991 } | |
| 992 | |
| 993 // Check for maximum frequency value | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
994 if (lrg._maxfreq < block->_freq) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
995 lrg._maxfreq = block->_freq; |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
996 } |
| 0 | 997 |
| 998 } // End for all allocated inputs | |
| 999 } // end for all instructions | |
| 1000 } // end for all blocks | |
| 1001 | |
| 1002 // Final per-liverange setup | |
| 10111 | 1003 for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) { |
| 0 | 1004 LRG &lrg = lrgs(i2); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1005 assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1006 if (lrg.num_regs() > 1 && !lrg._fat_proj) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1007 lrg.clear_to_sets(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1008 } |
| 0 | 1009 lrg.compute_set_mask_size(); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1010 if (lrg.not_free()) { // Handle case where we lose from the start |
| 0 | 1011 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
| 1012 lrg._direct_conflict = 1; | |
| 1013 } | |
| 1014 lrg.set_degree(0); // no neighbors in IFG yet | |
| 1015 } | |
| 1016 } | |
| 1017 | |
| 1018 // Set the was-lo-degree bit. Conservative coalescing should not change the | |
| 1019 // colorability of the graph. If any live range was of low-degree before | |
| 1020 // coalescing, it should Simplify. This call sets the was-lo-degree bit. | |
| 1021 // The bit is checked in Simplify. | |
| 1022 void PhaseChaitin::set_was_low() { | |
| 1023 #ifdef ASSERT | |
| 10111 | 1024 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
| 0 | 1025 int size = lrgs(i).num_regs(); |
| 1026 uint old_was_lo = lrgs(i)._was_lo; | |
| 1027 lrgs(i)._was_lo = 0; | |
| 1028 if( lrgs(i).lo_degree() ) { | |
| 1029 lrgs(i)._was_lo = 1; // Trivially of low degree | |
| 1030 } else { // Else check the Brigg's assertion | |
| 1031 // Brigg's observation is that the lo-degree neighbors of a | |
| 1032 // hi-degree live range will not interfere with the color choices | |
| 1033 // of said hi-degree live range. The Simplify reverse-stack-coloring | |
| 1034 // order takes care of the details. Hence you do not have to count | |
| 1035 // low-degree neighbors when determining if this guy colors. | |
| 1036 int briggs_degree = 0; | |
| 1037 IndexSet *s = _ifg->neighbors(i); | |
| 1038 IndexSetIterator elements(s); | |
| 1039 uint lidx; | |
| 1040 while((lidx = elements.next()) != 0) { | |
| 1041 if( !lrgs(lidx).lo_degree() ) | |
| 1042 briggs_degree += MAX2(size,lrgs(lidx).num_regs()); | |
| 1043 } | |
| 1044 if( briggs_degree < lrgs(i).degrees_of_freedom() ) | |
| 1045 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion | |
| 1046 } | |
| 1047 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease"); | |
| 1048 } | |
| 1049 #endif | |
| 1050 } | |
| 1051 | |
| 1052 #define REGISTER_CONSTRAINED 16 | |
| 1053 | |
| 1054 // Compute cost/area ratio, in case we spill. Build the lo-degree list. | |
| 1055 void PhaseChaitin::cache_lrg_info( ) { | |
| 1056 | |
| 10111 | 1057 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
| 0 | 1058 LRG &lrg = lrgs(i); |
| 1059 | |
| 1060 // Check for being of low degree: means we can be trivially colored. | |
| 1061 // Low degree, dead or must-spill guys just get to simplify right away | |
| 1062 if( lrg.lo_degree() || | |
| 1063 !lrg.alive() || | |
| 1064 lrg._must_spill ) { | |
| 1065 // Split low degree list into those guys that must get a | |
| 1066 // register and those that can go to register or stack. | |
| 1067 // The idea is LRGs that can go register or stack color first when | |
| 1068 // they have a good chance of getting a register. The register-only | |
| 1069 // lo-degree live ranges always get a register. | |
| 1070 OptoReg::Name hi_reg = lrg.mask().find_last_elem(); | |
| 1071 if( OptoReg::is_stack(hi_reg)) { // Can go to stack? | |
| 1072 lrg._next = _lo_stk_degree; | |
| 1073 _lo_stk_degree = i; | |
| 1074 } else { | |
| 1075 lrg._next = _lo_degree; | |
| 1076 _lo_degree = i; | |
| 1077 } | |
| 1078 } else { // Else high degree | |
| 1079 lrgs(_hi_degree)._prev = i; | |
| 1080 lrg._next = _hi_degree; | |
| 1081 lrg._prev = 0; | |
| 1082 _hi_degree = i; | |
| 1083 } | |
| 1084 } | |
| 1085 } | |
| 1086 | |
| 1087 // Simplify the IFG by removing LRGs of low degree that have NO copies | |
| 1088 void PhaseChaitin::Pre_Simplify( ) { | |
| 1089 | |
| 1090 // Warm up the lo-degree no-copy list | |
| 1091 int lo_no_copy = 0; | |
| 10111 | 1092 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
| 1093 if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) || | |
| 0 | 1094 !lrgs(i).alive() || |
| 10111 | 1095 lrgs(i)._must_spill) { |
| 0 | 1096 lrgs(i)._next = lo_no_copy; |
| 1097 lo_no_copy = i; | |
| 1098 } | |
| 1099 } | |
| 1100 | |
| 1101 while( lo_no_copy ) { | |
| 1102 uint lo = lo_no_copy; | |
| 1103 lo_no_copy = lrgs(lo)._next; | |
| 1104 int size = lrgs(lo).num_regs(); | |
| 1105 | |
| 1106 // Put the simplified guy on the simplified list. | |
| 1107 lrgs(lo)._next = _simplified; | |
| 1108 _simplified = lo; | |
| 1109 | |
| 1110 // Yank this guy from the IFG. | |
| 1111 IndexSet *adj = _ifg->remove_node( lo ); | |
| 1112 | |
| 1113 // If any neighbors' degrees fall below their number of | |
| 1114 // allowed registers, then put that neighbor on the low degree | |
| 1115 // list. Note that 'degree' can only fall and 'numregs' is | |
| 1116 // unchanged by this action. Thus the two are equal at most once, | |
| 1117 // so LRGs hit the lo-degree worklists at most once. | |
| 1118 IndexSetIterator elements(adj); | |
| 1119 uint neighbor; | |
| 1120 while ((neighbor = elements.next()) != 0) { | |
| 1121 LRG *n = &lrgs(neighbor); | |
| 1122 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); | |
| 1123 | |
| 1124 // Check for just becoming of-low-degree | |
| 1125 if( n->just_lo_degree() && !n->_has_copy ) { | |
| 1126 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); | |
| 1127 // Put on lo-degree list | |
| 1128 n->_next = lo_no_copy; | |
| 1129 lo_no_copy = neighbor; | |
| 1130 } | |
| 1131 } | |
| 1132 } // End of while lo-degree no_copy worklist not empty | |
| 1133 | |
| 1134 // No more lo-degree no-copy live ranges to simplify | |
| 1135 } | |
| 1136 | |
| 1137 // Simplify the IFG by removing LRGs of low degree. | |
| 1138 void PhaseChaitin::Simplify( ) { | |
| 1139 | |
| 1140 while( 1 ) { // Repeat till simplified it all | |
| 1141 // May want to explore simplifying lo_degree before _lo_stk_degree. | |
| 1142 // This might result in more spills coloring into registers during | |
| 1143 // Select(). | |
| 1144 while( _lo_degree || _lo_stk_degree ) { | |
| 1145 // If possible, pull from lo_stk first | |
| 1146 uint lo; | |
| 1147 if( _lo_degree ) { | |
| 1148 lo = _lo_degree; | |
| 1149 _lo_degree = lrgs(lo)._next; | |
| 1150 } else { | |
| 1151 lo = _lo_stk_degree; | |
| 1152 _lo_stk_degree = lrgs(lo)._next; | |
| 1153 } | |
| 1154 | |
| 1155 // Put the simplified guy on the simplified list. | |
| 1156 lrgs(lo)._next = _simplified; | |
| 1157 _simplified = lo; | |
| 1158 // If this guy is "at risk" then mark his current neighbors | |
| 1159 if( lrgs(lo)._at_risk ) { | |
| 1160 IndexSetIterator elements(_ifg->neighbors(lo)); | |
| 1161 uint datum; | |
| 1162 while ((datum = elements.next()) != 0) { | |
| 1163 lrgs(datum)._risk_bias = lo; | |
| 1164 } | |
| 1165 } | |
| 1166 | |
| 1167 // Yank this guy from the IFG. | |
| 1168 IndexSet *adj = _ifg->remove_node( lo ); | |
| 1169 | |
| 1170 // If any neighbors' degrees fall below their number of | |
| 1171 // allowed registers, then put that neighbor on the low degree | |
| 1172 // list. Note that 'degree' can only fall and 'numregs' is | |
| 1173 // unchanged by this action. Thus the two are equal at most once, | |
| 1174 // so LRGs hit the lo-degree worklist at most once. | |
| 1175 IndexSetIterator elements(adj); | |
| 1176 uint neighbor; | |
| 1177 while ((neighbor = elements.next()) != 0) { | |
| 1178 LRG *n = &lrgs(neighbor); | |
| 1179 #ifdef ASSERT | |
|
550
96964ebdb154
6782232: assert("CreateEx must be first instruction in block" )
kvn
parents:
419
diff
changeset
|
1180 if( VerifyOpto || VerifyRegisterAllocator ) { |
| 0 | 1181 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); |
| 1182 } | |
| 1183 #endif | |
| 1184 | |
| 1185 // Check for just becoming of-low-degree just counting registers. | |
| 1186 // _must_spill live ranges are already on the low degree list. | |
| 1187 if( n->just_lo_degree() && !n->_must_spill ) { | |
| 1188 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); | |
| 1189 // Pull from hi-degree list | |
| 1190 uint prev = n->_prev; | |
| 1191 uint next = n->_next; | |
| 1192 if( prev ) lrgs(prev)._next = next; | |
| 1193 else _hi_degree = next; | |
| 1194 lrgs(next)._prev = prev; | |
| 1195 n->_next = _lo_degree; | |
| 1196 _lo_degree = neighbor; | |
| 1197 } | |
| 1198 } | |
| 1199 } // End of while lo-degree/lo_stk_degree worklist not empty | |
| 1200 | |
| 1201 // Check for got everything: is hi-degree list empty? | |
| 1202 if( !_hi_degree ) break; | |
| 1203 | |
| 1204 // Time to pick a potential spill guy | |
| 1205 uint lo_score = _hi_degree; | |
| 1206 double score = lrgs(lo_score).score(); | |
| 1207 double area = lrgs(lo_score)._area; | |
|
1008
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1208 double cost = lrgs(lo_score)._cost; |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1209 bool bound = lrgs(lo_score)._is_bound; |
| 0 | 1210 |
| 1211 // Find cheapest guy | |
| 1212 debug_only( int lo_no_simplify=0; ); | |
|
1012
5f29a958a545
6889656: assert(lo_lrg->lo_degree() || !lo_no_simplify,"Live range was lo-degree before coalesce
kvn
parents:
1008
diff
changeset
|
1213 for( uint i = _hi_degree; i; i = lrgs(i)._next ) { |
| 0 | 1214 assert( !(*_ifg->_yanked)[i], "" ); |
| 1215 // It's just vaguely possible to move hi-degree to lo-degree without | |
| 1216 // going through a just-lo-degree stage: If you remove a double from | |
| 1217 // a float live range it's degree will drop by 2 and you can skip the | |
| 1218 // just-lo-degree stage. It's very rare (shows up after 5000+ methods | |
| 1219 // in -Xcomp of Java2Demo). So just choose this guy to simplify next. | |
| 1220 if( lrgs(i).lo_degree() ) { | |
| 1221 lo_score = i; | |
| 1222 break; | |
| 1223 } | |
| 1224 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; ); | |
| 1225 double iscore = lrgs(i).score(); | |
| 1226 double iarea = lrgs(i)._area; | |
|
1008
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1227 double icost = lrgs(i)._cost; |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1228 bool ibound = lrgs(i)._is_bound; |
| 0 | 1229 |
| 1230 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area | |
| 1231 // wins. Ties happen because all live ranges in question have spilled | |
| 1232 // a few times before and the spill-score adds a huge number which | |
| 1233 // washes out the low order bits. We are choosing the lesser of 2 | |
| 1234 // evils; in this case pick largest area to spill. | |
|
1008
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1235 // Ties also happen when live ranges are defined and used only inside |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1236 // one block. In which case their area is 0 and score set to max. |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1237 // In such case choose bound live range over unbound to free registers |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1238 // or with smaller cost to spill. |
| 0 | 1239 if( iscore < score || |
|
1008
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1240 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) || |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1241 (iscore == score && iarea == area && |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1242 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) { |
| 0 | 1243 lo_score = i; |
| 1244 score = iscore; | |
| 1245 area = iarea; | |
|
1008
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1246 cost = icost; |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
kvn
parents:
729
diff
changeset
|
1247 bound = ibound; |
| 0 | 1248 } |
| 1249 } | |
| 1250 LRG *lo_lrg = &lrgs(lo_score); | |
| 1251 // The live range we choose for spilling is either hi-degree, or very | |
| 1252 // rarely it can be low-degree. If we choose a hi-degree live range | |
| 1253 // there better not be any lo-degree choices. | |
| 1254 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" ); | |
| 1255 | |
| 1256 // Pull from hi-degree list | |
| 1257 uint prev = lo_lrg->_prev; | |
| 1258 uint next = lo_lrg->_next; | |
| 1259 if( prev ) lrgs(prev)._next = next; | |
| 1260 else _hi_degree = next; | |
| 1261 lrgs(next)._prev = prev; | |
| 1262 // Jam him on the lo-degree list, despite his high degree. | |
| 1263 // Maybe he'll get a color, and maybe he'll spill. | |
| 1264 // Only Select() will know. | |
| 1265 lrgs(lo_score)._at_risk = true; | |
| 1266 _lo_degree = lo_score; | |
| 1267 lo_lrg->_next = 0; | |
| 1268 | |
| 1269 } // End of while not simplified everything | |
| 1270 | |
| 1271 } | |
| 1272 | |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1273 // Is 'reg' register legal for 'lrg'? |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1274 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1275 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1276 lrg.mask().Member(OptoReg::add(reg,-chunk))) { |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1277 // RA uses OptoReg which represent the highest element of a registers set. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1278 // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1279 // in which XMMd is used by RA to represent such vectors. A double value |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1280 // uses [XMM,XMMb] pairs and XMMb is used by RA for it. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1281 // The register mask uses largest bits set of overlapping register sets. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1282 // On x86 with AVX it uses 8 bits for each XMM registers set. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1283 // |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1284 // The 'lrg' already has cleared-to-set register mask (done in Select() |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1285 // before calling choose_color()). Passing mask.Member(reg) check above |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1286 // indicates that the size (num_regs) of 'reg' set is less or equal to |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1287 // 'lrg' set size. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1288 // For set size 1 any register which is member of 'lrg' mask is legal. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1289 if (lrg.num_regs()==1) |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1290 return true; |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1291 // For larger sets only an aligned register with the same set size is legal. |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1292 int mask = lrg.num_regs()-1; |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1293 if ((reg&mask) == mask) |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1294 return true; |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1295 } |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1296 return false; |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1297 } |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1298 |
| 0 | 1299 // Choose a color using the biasing heuristic |
| 1300 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { | |
| 1301 | |
| 1302 // Check for "at_risk" LRG's | |
| 10111 | 1303 uint risk_lrg = _lrg_map.find(lrg._risk_bias); |
| 0 | 1304 if( risk_lrg != 0 ) { |
| 1305 // Walk the colored neighbors of the "at_risk" candidate | |
| 1306 // Choose a color which is both legal and already taken by a neighbor | |
| 1307 // of the "at_risk" candidate in order to improve the chances of the | |
| 1308 // "at_risk" candidate of coloring | |
| 1309 IndexSetIterator elements(_ifg->neighbors(risk_lrg)); | |
| 1310 uint datum; | |
| 1311 while ((datum = elements.next()) != 0) { | |
| 1312 OptoReg::Name reg = lrgs(datum).reg(); | |
| 1313 // If this LRG's register is legal for us, choose it | |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1314 if (is_legal_reg(lrg, reg, chunk)) |
| 0 | 1315 return reg; |
| 1316 } | |
| 1317 } | |
| 1318 | |
| 10111 | 1319 uint copy_lrg = _lrg_map.find(lrg._copy_bias); |
| 0 | 1320 if( copy_lrg != 0 ) { |
| 1321 // If he has a color, | |
| 1322 if( !(*(_ifg->_yanked))[copy_lrg] ) { | |
| 1323 OptoReg::Name reg = lrgs(copy_lrg).reg(); | |
| 1324 // And it is legal for you, | |
|
6620
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
kvn
parents:
6268
diff
changeset
|
1325 if (is_legal_reg(lrg, reg, chunk)) |
| 0 | 1326 return reg; |
| 1327 } else if( chunk == 0 ) { | |
| 1328 // Choose a color which is legal for him | |
| 1329 RegMask tempmask = lrg.mask(); | |
| 1330 tempmask.AND(lrgs(copy_lrg).mask()); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1331 tempmask.clear_to_sets(lrg.num_regs()); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1332 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1333 if (OptoReg::is_valid(reg)) |
| 0 | 1334 return reg; |
| 1335 } | |
| 1336 } | |
| 1337 | |
| 1338 // If no bias info exists, just go with the register selection ordering | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1339 if (lrg._is_vector || lrg.num_regs() == 2) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1340 // Find an aligned set |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1341 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); |
| 0 | 1342 } |
| 1343 | |
| 1344 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate | |
| 1345 // copy removal to remove many more copies, by preventing a just-assigned | |
| 1346 // register from being repeatedly assigned. | |
| 1347 OptoReg::Name reg = lrg.mask().find_first_elem(); | |
| 1348 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) { | |
| 1349 // This 'Remove; find; Insert' idiom is an expensive way to find the | |
| 1350 // SECOND element in the mask. | |
| 1351 lrg.Remove(reg); | |
| 1352 OptoReg::Name reg2 = lrg.mask().find_first_elem(); | |
| 1353 lrg.Insert(reg); | |
| 1354 if( OptoReg::is_reg(reg2)) | |
| 1355 reg = reg2; | |
| 1356 } | |
| 1357 return OptoReg::add( reg, chunk ); | |
| 1358 } | |
| 1359 | |
| 1360 // Choose a color in the current chunk | |
| 1361 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { | |
| 1362 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); | |
| 1363 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); | |
| 1364 | |
| 1365 if( lrg.num_regs() == 1 || // Common Case | |
| 1366 !lrg._fat_proj ) // Aligned+adjacent pairs ok | |
| 1367 // Use a heuristic to "bias" the color choice | |
| 1368 return bias_color(lrg, chunk); | |
| 1369 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1370 assert(!lrg._is_vector, "should be not vector here" ); |
| 0 | 1371 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); |
| 1372 | |
| 1373 // Fat-proj case or misaligned double argument. | |
| 1374 assert(lrg.compute_mask_size() == lrg.num_regs() || | |
| 1375 lrg.num_regs() == 2,"fat projs exactly color" ); | |
| 1376 assert( !chunk, "always color in 1st chunk" ); | |
| 1377 // Return the highest element in the set. | |
| 1378 return lrg.mask().find_last_elem(); | |
| 1379 } | |
| 1380 | |
| 1381 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted | |
| 1382 // in reverse order of removal. As long as nothing of hi-degree was yanked, | |
| 1383 // everything going back is guaranteed a color. Select that color. If some | |
| 1384 // hi-degree LRG cannot get a color then we record that we must spill. | |
| 1385 uint PhaseChaitin::Select( ) { | |
| 1386 uint spill_reg = LRG::SPILL_REG; | |
| 1387 _max_reg = OptoReg::Name(0); // Past max register used | |
| 1388 while( _simplified ) { | |
| 1389 // Pull next LRG from the simplified list - in reverse order of removal | |
| 1390 uint lidx = _simplified; | |
| 1391 LRG *lrg = &lrgs(lidx); | |
| 1392 _simplified = lrg->_next; | |
| 1393 | |
| 1394 | |
| 1395 #ifndef PRODUCT | |
| 1396 if (trace_spilling()) { | |
| 1397 ttyLocker ttyl; | |
| 1398 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(), | |
| 1399 lrg->degrees_of_freedom()); | |
| 1400 lrg->dump(); | |
| 1401 } | |
| 1402 #endif | |
| 1403 | |
| 1404 // Re-insert into the IFG | |
| 1405 _ifg->re_insert(lidx); | |
| 1406 if( !lrg->alive() ) continue; | |
| 1407 // capture allstackedness flag before mask is hacked | |
| 1408 const int is_allstack = lrg->mask().is_AllStack(); | |
| 1409 | |
| 1410 // Yeah, yeah, yeah, I know, I know. I can refactor this | |
| 1411 // to avoid the GOTO, although the refactored code will not | |
| 1412 // be much clearer. We arrive here IFF we have a stack-based | |
| 1413 // live range that cannot color in the current chunk, and it | |
| 1414 // has to move into the next free stack chunk. | |
| 1415 int chunk = 0; // Current chunk is first chunk | |
| 1416 retry_next_chunk: | |
| 1417 | |
| 1418 // Remove neighbor colors | |
| 1419 IndexSet *s = _ifg->neighbors(lidx); | |
| 1420 | |
| 1421 debug_only(RegMask orig_mask = lrg->mask();) | |
| 1422 IndexSetIterator elements(s); | |
| 1423 uint neighbor; | |
| 1424 while ((neighbor = elements.next()) != 0) { | |
| 1425 // Note that neighbor might be a spill_reg. In this case, exclusion | |
| 1426 // of its color will be a no-op, since the spill_reg chunk is in outer | |
| 1427 // space. Also, if neighbor is in a different chunk, this exclusion | |
| 1428 // will be a no-op. (Later on, if lrg runs out of possible colors in | |
| 1429 // its chunk, a new chunk of color may be tried, in which case | |
| 1430 // examination of neighbors is started again, at retry_next_chunk.) | |
| 1431 LRG &nlrg = lrgs(neighbor); | |
| 1432 OptoReg::Name nreg = nlrg.reg(); | |
| 1433 // Only subtract masks in the same chunk | |
| 1434 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) { | |
| 1435 #ifndef PRODUCT | |
| 1436 uint size = lrg->mask().Size(); | |
| 1437 RegMask rm = lrg->mask(); | |
| 1438 #endif | |
| 1439 lrg->SUBTRACT(nlrg.mask()); | |
| 1440 #ifndef PRODUCT | |
| 1441 if (trace_spilling() && lrg->mask().Size() != size) { | |
| 1442 ttyLocker ttyl; | |
| 1443 tty->print("L%d ", lidx); | |
| 1444 rm.dump(); | |
| 1445 tty->print(" intersected L%d ", neighbor); | |
| 1446 nlrg.mask().dump(); | |
| 1447 tty->print(" removed "); | |
| 1448 rm.SUBTRACT(lrg->mask()); | |
| 1449 rm.dump(); | |
| 1450 tty->print(" leaving "); | |
| 1451 lrg->mask().dump(); | |
| 1452 tty->cr(); | |
| 1453 } | |
| 1454 #endif | |
| 1455 } | |
| 1456 } | |
| 1457 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); | |
| 1458 // Aligned pairs need aligned masks | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1459 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1460 if (lrg->num_regs() > 1 && !lrg->_fat_proj) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1461 lrg->clear_to_sets(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1462 } |
| 0 | 1463 |
| 1464 // Check if a color is available and if so pick the color | |
| 1465 OptoReg::Name reg = choose_color( *lrg, chunk ); | |
| 1466 #ifdef SPARC | |
| 1467 debug_only(lrg->compute_set_mask_size()); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1468 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); |
| 0 | 1469 #endif |
| 1470 | |
| 1471 //--------------- | |
| 1472 // If we fail to color and the AllStack flag is set, trigger | |
| 1473 // a chunk-rollover event | |
| 1474 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) { | |
| 1475 // Bump register mask up to next stack chunk | |
| 1476 chunk += RegMask::CHUNK_SIZE; | |
| 1477 lrg->Set_All(); | |
| 1478 | |
| 1479 goto retry_next_chunk; | |
| 1480 } | |
| 1481 | |
| 1482 //--------------- | |
| 1483 // Did we get a color? | |
| 1484 else if( OptoReg::is_valid(reg)) { | |
| 1485 #ifndef PRODUCT | |
| 1486 RegMask avail_rm = lrg->mask(); | |
| 1487 #endif | |
| 1488 | |
| 1489 // Record selected register | |
| 1490 lrg->set_reg(reg); | |
| 1491 | |
| 1492 if( reg >= _max_reg ) // Compute max register limit | |
| 1493 _max_reg = OptoReg::add(reg,1); | |
| 1494 // Fold reg back into normal space | |
| 1495 reg = OptoReg::add(reg,-chunk); | |
| 1496 | |
| 1497 // If the live range is not bound, then we actually had some choices | |
| 1498 // to make. In this case, the mask has more bits in it than the colors | |
| 605 | 1499 // chosen. Restrict the mask to just what was picked. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1500 int n_regs = lrg->num_regs(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1501 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1502 if (n_regs == 1 || !lrg->_fat_proj) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1503 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity"); |
| 0 | 1504 lrg->Clear(); // Clear the mask |
| 1505 lrg->Insert(reg); // Set regmask to match selected reg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1506 // For vectors and pairs, also insert the low bit of the pair |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1507 for (int i = 1; i < n_regs; i++) |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1508 lrg->Insert(OptoReg::add(reg,-i)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
1509 lrg->set_mask_size(n_regs); |
| 0 | 1510 } else { // Else fatproj |
| 1511 // mask must be equal to fatproj bits, by definition | |
| 1512 } | |
| 1513 #ifndef PRODUCT | |
| 1514 if (trace_spilling()) { | |
| 1515 ttyLocker ttyl; | |
| 1516 tty->print("L%d selected ", lidx); | |
| 1517 lrg->mask().dump(); | |
| 1518 tty->print(" from "); | |
| 1519 avail_rm.dump(); | |
| 1520 tty->cr(); | |
| 1521 } | |
| 1522 #endif | |
| 1523 // Note that reg is the highest-numbered register in the newly-bound mask. | |
| 1524 } // end color available case | |
| 1525 | |
| 1526 //--------------- | |
| 1527 // Live range is live and no colors available | |
| 1528 else { | |
| 1529 assert( lrg->alive(), "" ); | |
|
295
ea18057223c4
6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents:
196
diff
changeset
|
1530 assert( !lrg->_fat_proj || lrg->is_multidef() || |
| 0 | 1531 lrg->_def->outcnt() > 0, "fat_proj cannot spill"); |
| 1532 assert( !orig_mask.is_AllStack(), "All Stack does not spill" ); | |
| 1533 | |
| 1534 // Assign the special spillreg register | |
| 1535 lrg->set_reg(OptoReg::Name(spill_reg++)); | |
| 1536 // Do not empty the regmask; leave mask_size lying around | |
| 1537 // for use during Spilling | |
| 1538 #ifndef PRODUCT | |
| 1539 if( trace_spilling() ) { | |
| 1540 ttyLocker ttyl; | |
| 1541 tty->print("L%d spilling with neighbors: ", lidx); | |
| 1542 s->dump(); | |
| 1543 debug_only(tty->print(" original mask: ")); | |
| 1544 debug_only(orig_mask.dump()); | |
| 1545 dump_lrg(lidx); | |
| 1546 } | |
| 1547 #endif | |
| 1548 } // end spill case | |
| 1549 | |
| 1550 } | |
| 1551 | |
| 1552 return spill_reg-LRG::SPILL_REG; // Return number of spills | |
| 1553 } | |
| 1554 | |
| 1555 // Copy 'was_spilled'-edness from the source Node to the dst Node. | |
| 1556 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { | |
| 1557 if( _spilled_once.test(src->_idx) ) { | |
| 1558 _spilled_once.set(dst->_idx); | |
| 10111 | 1559 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; |
| 0 | 1560 if( _spilled_twice.test(src->_idx) ) { |
| 1561 _spilled_twice.set(dst->_idx); | |
| 10111 | 1562 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; |
| 0 | 1563 } |
| 1564 } | |
| 1565 } | |
| 1566 | |
| 1567 // Set the 'spilled_once' or 'spilled_twice' flag on a node. | |
| 1568 void PhaseChaitin::set_was_spilled( Node *n ) { | |
| 1569 if( _spilled_once.test_set(n->_idx) ) | |
| 1570 _spilled_twice.set(n->_idx); | |
| 1571 } | |
| 1572 | |
| 1573 // Convert Ideal spill instructions into proper FramePtr + offset Loads and | |
| 1574 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. | |
| 1575 void PhaseChaitin::fixup_spills() { | |
| 1576 // This function does only cisc spill work. | |
| 1577 if( !UseCISCSpill ) return; | |
| 1578 | |
| 1579 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) | |
| 1580 | |
| 1581 // Grab the Frame Pointer | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1582 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr); |
| 0 | 1583 |
| 1584 // For all blocks | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1585 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1586 Block* block = _cfg.get_block(i); |
| 0 | 1587 |
| 1588 // For all instructions in block | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1589 uint last_inst = block->end_idx(); |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1590 for (uint j = 1; j <= last_inst; j++) { |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1591 Node* n = block->get_node(j); |
| 0 | 1592 |
| 1593 // Dead instruction??? | |
| 1594 assert( n->outcnt() != 0 ||// Nothing dead after post alloc | |
| 1595 C->top() == n || // Or the random TOP node | |
| 1596 n->is_Proj(), // Or a fat-proj kill node | |
| 1597 "No dead instructions after post-alloc" ); | |
| 1598 | |
| 1599 int inp = n->cisc_operand(); | |
| 1600 if( inp != AdlcVMDeps::Not_cisc_spillable ) { | |
| 1601 // Convert operand number to edge index number | |
| 1602 MachNode *mach = n->as_Mach(); | |
| 1603 inp = mach->operand_index(inp); | |
| 1604 Node *src = n->in(inp); // Value to load or store | |
| 10111 | 1605 LRG &lrg_cisc = lrgs(_lrg_map.find_const(src)); |
| 0 | 1606 OptoReg::Name src_reg = lrg_cisc.reg(); |
| 1607 // Doubles record the HIGH register of an adjacent pair. | |
| 1608 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs()); | |
| 1609 if( OptoReg::is_stack(src_reg) ) { // If input is on stack | |
| 1610 // This is a CISC Spill, get stack offset and construct new node | |
| 1611 #ifndef PRODUCT | |
| 1612 if( TraceCISCSpill ) { | |
| 1613 tty->print(" reg-instr: "); | |
| 1614 n->dump(); | |
| 1615 } | |
| 1616 #endif | |
| 1617 int stk_offset = reg2offset(src_reg); | |
| 1618 // Bailout if we might exceed node limit when spilling this instruction | |
| 1619 C->check_node_count(0, "out of nodes fixing spills"); | |
| 1620 if (C->failing()) return; | |
| 1621 // Transform node | |
| 1622 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach(); | |
| 1623 cisc->set_req(inp,fp); // Base register is frame pointer | |
| 1624 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { | |
| 1625 assert( cisc->oper_input_base() == 2, "Only adding one edge"); | |
| 1626 cisc->ins_req(1,src); // Requires a memory edge | |
| 1627 } | |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1628 block->map_node(cisc, j); // Insert into basic block |
|
7196
2aff40cb4703
7092905: C2: Keep track of the number of dead nodes
bharadwaj
parents:
6804
diff
changeset
|
1629 n->subsume_by(cisc, C); // Correct graph |
| 0 | 1630 // |
| 1631 ++_used_cisc_instructions; | |
| 1632 #ifndef PRODUCT | |
| 1633 if( TraceCISCSpill ) { | |
| 1634 tty->print(" cisc-instr: "); | |
| 1635 cisc->dump(); | |
| 1636 } | |
| 1637 #endif | |
| 1638 } else { | |
| 1639 #ifndef PRODUCT | |
| 1640 if( TraceCISCSpill ) { | |
| 1641 tty->print(" using reg-instr: "); | |
| 1642 n->dump(); | |
| 1643 } | |
| 1644 #endif | |
| 1645 ++_unused_cisc_instructions; // input can be on stack | |
| 1646 } | |
| 1647 } | |
| 1648 | |
| 1649 } // End of for all instructions | |
| 1650 | |
| 1651 } // End of for all blocks | |
| 1652 } | |
| 1653 | |
| 1654 // Helper to stretch above; recursively discover the base Node for a | |
| 1655 // given derived Node. Easy for AddP-related machine nodes, but needs | |
| 1656 // to be recursive for derived Phis. | |
| 1657 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { | |
| 1658 // See if already computed; if so return it | |
| 1659 if( derived_base_map[derived->_idx] ) | |
| 1660 return derived_base_map[derived->_idx]; | |
| 1661 | |
| 1662 // See if this happens to be a base. | |
| 1663 // NOTE: we use TypePtr instead of TypeOopPtr because we can have | |
| 1664 // pointers derived from NULL! These are always along paths that | |
| 1665 // can't happen at run-time but the optimizer cannot deduce it so | |
| 1666 // we have to handle it gracefully. | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1667 assert(!derived->bottom_type()->isa_narrowoop() || |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1668 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
| 0 | 1669 const TypePtr *tj = derived->bottom_type()->isa_ptr(); |
| 1670 // If its an OOP with a non-zero offset, then it is derived. | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1671 if( tj == NULL || tj->_offset == 0 ) { |
| 0 | 1672 derived_base_map[derived->_idx] = derived; |
| 1673 return derived; | |
| 1674 } | |
| 1675 // Derived is NULL+offset? Base is NULL! | |
| 1676 if( derived->is_Con() ) { | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1677 Node *base = _matcher.mach_null(); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1678 assert(base != NULL, "sanity"); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1679 if (base->in(0) == NULL) { |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1680 // Initialize it once and make it shared: |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1681 // set control to _root and place it into Start block |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1682 // (where top() node is placed). |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1683 base->init_req(0, _cfg.get_root_node()); |
|
12023
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1684 Block *startb = _cfg.get_block_for_node(C->top()); |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1685 startb->insert_node(base, startb->find_node(C->top())); |
|
12023
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1686 _cfg.map_node_to_block(base, startb); |
| 10111 | 1687 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1688 } |
| 10111 | 1689 if (_lrg_map.live_range_id(base) == 0) { |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1690 new_lrg(base, maxlrg++); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1691 } |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1692 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); |
| 0 | 1693 derived_base_map[derived->_idx] = base; |
| 1694 return base; | |
| 1695 } | |
| 1696 | |
| 1697 // Check for AddP-related opcodes | |
| 10111 | 1698 if (!derived->is_Phi()) { |
|
6268
6c5b7a6becc8
7187454: stack overflow in C2 compiler thread on Solaris x86
kvn
parents:
6182
diff
changeset
|
1699 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name())); |
| 0 | 1700 Node *base = derived->in(AddPNode::Base); |
| 1701 derived_base_map[derived->_idx] = base; | |
| 1702 return base; | |
| 1703 } | |
| 1704 | |
| 1705 // Recursively find bases for Phis. | |
| 1706 // First check to see if we can avoid a base Phi here. | |
| 1707 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg); | |
| 1708 uint i; | |
| 1709 for( i = 2; i < derived->req(); i++ ) | |
| 1710 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg)) | |
| 1711 break; | |
| 1712 // Went to the end without finding any different bases? | |
| 1713 if( i == derived->req() ) { // No need for a base Phi here | |
| 1714 derived_base_map[derived->_idx] = base; | |
| 1715 return base; | |
| 1716 } | |
| 1717 | |
| 1718 // Now we see we need a base-Phi here to merge the bases | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1719 const Type *t = base->bottom_type(); |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6632
diff
changeset
|
1720 base = new (C) PhiNode( derived->in(0), t ); |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1721 for( i = 1; i < derived->req(); i++ ) { |
| 0 | 1722 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg)); |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1723 t = t->meet(base->in(i)->bottom_type()); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1724 } |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1725 base->as_Phi()->set_type(t); |
| 0 | 1726 |
| 1727 // Search the current block for an existing base-Phi | |
|
12023
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1728 Block *b = _cfg.get_block_for_node(derived); |
| 0 | 1729 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1730 Node *phi = b->get_node(i); |
| 0 | 1731 if( !phi->is_Phi() ) { // Found end of Phis with no match? |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1732 b->insert_node(base, i); // Must insert created Phi here as base |
|
12023
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1733 _cfg.map_node_to_block(base, b); |
| 0 | 1734 new_lrg(base,maxlrg++); |
| 1735 break; | |
| 1736 } | |
| 1737 // See if Phi matches. | |
| 1738 uint j; | |
| 1739 for( j = 1; j < base->req(); j++ ) | |
| 1740 if( phi->in(j) != base->in(j) && | |
| 1741 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs | |
| 1742 break; | |
| 1743 if( j == base->req() ) { // All inputs match? | |
| 1744 base = phi; // Then use existing 'phi' and drop 'base' | |
| 1745 break; | |
| 1746 } | |
| 1747 } | |
| 1748 | |
| 1749 | |
| 1750 // Cache info for later passes | |
| 1751 derived_base_map[derived->_idx] = base; | |
| 1752 return base; | |
| 1753 } | |
| 1754 | |
| 1755 // At each Safepoint, insert extra debug edges for each pair of derived value/ | |
| 1756 // base pointer that is live across the Safepoint for oopmap building. The | |
| 1757 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the | |
| 1758 // required edge set. | |
| 10111 | 1759 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { |
| 0 | 1760 int must_recompute_live = false; |
| 10111 | 1761 uint maxlrg = _lrg_map.max_lrg_id(); |
| 0 | 1762 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); |
| 1763 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); | |
| 1764 | |
| 1765 // For all blocks in RPO do... | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1766 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1767 Block* block = _cfg.get_block(i); |
| 0 | 1768 // Note use of deep-copy constructor. I cannot hammer the original |
| 1769 // liveout bits, because they are needed by the following coalesce pass. | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1770 IndexSet liveout(_live->live(block)); |
| 0 | 1771 |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1772 for (uint j = block->end_idx() + 1; j > 1; j--) { |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1773 Node* n = block->get_node(j - 1); |
| 0 | 1774 |
| 1775 // Pre-split compares of loop-phis. Loop-phis form a cycle we would | |
| 1776 // like to see in the same register. Compare uses the loop-phi and so | |
| 1777 // extends its live range BUT cannot be part of the cycle. If this | |
| 1778 // extended live range overlaps with the update of the loop-phi value | |
| 1779 // we need both alive at the same time -- which requires at least 1 | |
| 1780 // copy. But because Intel has only 2-address registers we end up with | |
| 1781 // at least 2 copies, one before the loop-phi update instruction and | |
| 1782 // one after. Instead we split the input to the compare just after the | |
| 1783 // phi. | |
| 1784 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { | |
| 1785 Node *phi = n->in(1); | |
| 1786 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { | |
|
12023
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1787 Block *phi_block = _cfg.get_block_for_node(phi); |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1788 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { |
| 0 | 1789 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; |
| 1790 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); | |
| 1791 insert_proj( phi_block, 1, spill, maxlrg++ ); | |
| 1792 n->set_req(1,spill); | |
| 1793 must_recompute_live = true; | |
| 1794 } | |
| 1795 } | |
| 1796 } | |
| 1797 | |
| 1798 // Get value being defined | |
| 10111 | 1799 uint lidx = _lrg_map.live_range_id(n); |
| 1800 // Ignore the occasional brand-new live range | |
| 1801 if (lidx && lidx < _lrg_map.max_lrg_id()) { | |
| 0 | 1802 // Remove from live-out set |
| 1803 liveout.remove(lidx); | |
| 1804 | |
| 1805 // Copies do not define a new value and so do not interfere. | |
| 1806 // Remove the copies source from the liveout set before interfering. | |
| 1807 uint idx = n->is_Copy(); | |
| 10111 | 1808 if (idx) { |
| 1809 liveout.remove(_lrg_map.live_range_id(n->in(idx))); | |
| 1810 } | |
| 0 | 1811 } |
| 1812 | |
| 1813 // Found a safepoint? | |
| 1814 JVMState *jvms = n->jvms(); | |
| 1815 if( jvms ) { | |
| 1816 // Now scan for a live derived pointer | |
| 1817 IndexSetIterator elements(&liveout); | |
| 1818 uint neighbor; | |
| 1819 while ((neighbor = elements.next()) != 0) { | |
| 1820 // Find reaching DEF for base and derived values | |
| 1821 // This works because we are still in SSA during this call. | |
| 1822 Node *derived = lrgs(neighbor)._def; | |
| 1823 const TypePtr *tj = derived->bottom_type()->isa_ptr(); | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1824 assert(!derived->bottom_type()->isa_narrowoop() || |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
673
diff
changeset
|
1825 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
| 0 | 1826 // If its an OOP with a non-zero offset, then it is derived. |
| 1827 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) { | |
| 10111 | 1828 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg); |
| 1829 assert(base->_idx < _lrg_map.size(), ""); | |
| 0 | 1830 // Add reaching DEFs of derived pointer and base pointer as a |
| 1831 // pair of inputs | |
| 10111 | 1832 n->add_req(derived); |
| 1833 n->add_req(base); | |
| 0 | 1834 |
| 1835 // See if the base pointer is already live to this point. | |
| 1836 // Since I'm working on the SSA form, live-ness amounts to | |
| 1837 // reaching def's. So if I find the base's live range then | |
| 1838 // I know the base's def reaches here. | |
| 10111 | 1839 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or |
| 1840 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND | |
| 1841 (_lrg_map.live_range_id(base) > 0) && // not a constant | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1842 _cfg.get_block_for_node(base) != block) { // base not def'd in blk) |
| 0 | 1843 // Base pointer is not currently live. Since I stretched |
| 1844 // the base pointer to here and it crosses basic-block | |
| 1845 // boundaries, the global live info is now incorrect. | |
| 1846 // Recompute live. | |
| 1847 must_recompute_live = true; | |
| 1848 } // End of if base pointer is not live to debug info | |
| 1849 } | |
| 1850 } // End of scan all live data for derived ptrs crossing GC point | |
| 1851 } // End of if found a GC point | |
| 1852 | |
| 1853 // Make all inputs live | |
| 10111 | 1854 if (!n->is_Phi()) { // Phi function uses come from prior block |
| 1855 for (uint k = 1; k < n->req(); k++) { | |
| 1856 uint lidx = _lrg_map.live_range_id(n->in(k)); | |
| 1857 if (lidx < _lrg_map.max_lrg_id()) { | |
| 1858 liveout.insert(lidx); | |
| 1859 } | |
| 0 | 1860 } |
| 1861 } | |
| 1862 | |
| 1863 } // End of forall instructions in block | |
| 1864 liveout.clear(); // Free the memory used by liveout. | |
| 1865 | |
| 1866 } // End of forall blocks | |
| 10111 | 1867 _lrg_map.set_max_lrg_id(maxlrg); |
| 0 | 1868 |
| 1869 // If I created a new live range I need to recompute live | |
| 10111 | 1870 if (maxlrg != _ifg->_maxlrg) { |
| 0 | 1871 must_recompute_live = true; |
| 10111 | 1872 } |
| 0 | 1873 |
| 1874 return must_recompute_live != 0; | |
| 1875 } | |
| 1876 | |
| 1877 // Extend the node to LRG mapping | |
| 10111 | 1878 |
| 1879 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { | |
| 1880 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); | |
| 0 | 1881 } |
| 1882 | |
| 1883 #ifndef PRODUCT | |
| 10111 | 1884 void PhaseChaitin::dump(const Node *n) const { |
| 1885 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; | |
| 0 | 1886 tty->print("L%d",r); |
| 10111 | 1887 if (r && n->Opcode() != Op_Phi) { |
| 0 | 1888 if( _node_regs ) { // Got a post-allocation copy of allocation? |
| 1889 tty->print("["); | |
| 1890 OptoReg::Name second = get_reg_second(n); | |
| 1891 if( OptoReg::is_valid(second) ) { | |
| 1892 if( OptoReg::is_reg(second) ) | |
| 1893 tty->print("%s:",Matcher::regName[second]); | |
| 1894 else | |
| 1895 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second)); | |
| 1896 } | |
| 1897 OptoReg::Name first = get_reg_first(n); | |
| 1898 if( OptoReg::is_reg(first) ) | |
| 1899 tty->print("%s]",Matcher::regName[first]); | |
| 1900 else | |
| 1901 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first)); | |
| 1902 } else | |
| 1903 n->out_RegMask().dump(); | |
| 1904 } | |
| 1905 tty->print("/N%d\t",n->_idx); | |
| 1906 tty->print("%s === ", n->Name()); | |
| 1907 uint k; | |
| 10111 | 1908 for (k = 0; k < n->req(); k++) { |
| 0 | 1909 Node *m = n->in(k); |
| 10111 | 1910 if (!m) { |
| 1911 tty->print("_ "); | |
| 1912 } | |
| 0 | 1913 else { |
| 10111 | 1914 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; |
| 0 | 1915 tty->print("L%d",r); |
| 1916 // Data MultiNode's can have projections with no real registers. | |
| 1917 // Don't die while dumping them. | |
| 1918 int op = n->Opcode(); | |
| 1919 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) { | |
| 1920 if( _node_regs ) { | |
| 1921 tty->print("["); | |
| 1922 OptoReg::Name second = get_reg_second(n->in(k)); | |
| 1923 if( OptoReg::is_valid(second) ) { | |
| 1924 if( OptoReg::is_reg(second) ) | |
| 1925 tty->print("%s:",Matcher::regName[second]); | |
| 1926 else | |
| 1927 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1928 reg2offset_unchecked(second)); | |
| 1929 } | |
| 1930 OptoReg::Name first = get_reg_first(n->in(k)); | |
| 1931 if( OptoReg::is_reg(first) ) | |
| 1932 tty->print("%s]",Matcher::regName[first]); | |
| 1933 else | |
| 1934 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1935 reg2offset_unchecked(first)); | |
| 1936 } else | |
| 1937 n->in_RegMask(k).dump(); | |
| 1938 } | |
| 1939 tty->print("/N%d ",m->_idx); | |
| 1940 } | |
| 1941 } | |
| 1942 if( k < n->len() && n->in(k) ) tty->print("| "); | |
| 1943 for( ; k < n->len(); k++ ) { | |
| 1944 Node *m = n->in(k); | |
| 10111 | 1945 if(!m) { |
| 1946 break; | |
| 1947 } | |
| 1948 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; | |
| 0 | 1949 tty->print("L%d",r); |
| 1950 tty->print("/N%d ",m->_idx); | |
| 1951 } | |
| 1952 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty); | |
| 1953 else n->dump_spec(tty); | |
| 1954 if( _spilled_once.test(n->_idx ) ) { | |
| 1955 tty->print(" Spill_1"); | |
| 1956 if( _spilled_twice.test(n->_idx ) ) | |
| 1957 tty->print(" Spill_2"); | |
| 1958 } | |
| 1959 tty->print("\n"); | |
| 1960 } | |
| 1961 | |
|
12023
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1962 void PhaseChaitin::dump(const Block *b) const { |
|
d1034bd8cefc
8022284: Hide internal data structure in PhaseCFG
adlertz
parents:
10999
diff
changeset
|
1963 b->dump_head(&_cfg); |
| 0 | 1964 |
| 1965 // For all instructions | |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1966 for( uint j = 0; j < b->number_of_nodes(); j++ ) |
|
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
1967 dump(b->get_node(j)); |
| 0 | 1968 // Print live-out info at end of block |
| 1969 if( _live ) { | |
| 1970 tty->print("Liveout: "); | |
| 1971 IndexSet *live = _live->live(b); | |
| 1972 IndexSetIterator elements(live); | |
| 1973 tty->print("{"); | |
| 1974 uint i; | |
| 1975 while ((i = elements.next()) != 0) { | |
| 10111 | 1976 tty->print("L%d ", _lrg_map.find_const(i)); |
| 0 | 1977 } |
| 1978 tty->print_cr("}"); | |
| 1979 } | |
| 1980 tty->print("\n"); | |
| 1981 } | |
| 1982 | |
| 1983 void PhaseChaitin::dump() const { | |
| 1984 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", | |
| 1985 _matcher._new_SP, _framesize ); | |
| 1986 | |
| 1987 // For all blocks | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1988 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1989 dump(_cfg.get_block(i)); |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
1990 } |
| 0 | 1991 // End of per-block dump |
| 1992 tty->print("\n"); | |
| 1993 | |
| 1994 if (!_ifg) { | |
| 1995 tty->print("(No IFG.)\n"); | |
| 1996 return; | |
| 1997 } | |
| 1998 | |
| 1999 // Dump LRG array | |
| 2000 tty->print("--- Live RanGe Array ---\n"); | |
| 10111 | 2001 for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) { |
| 0 | 2002 tty->print("L%d: ",i2); |
| 10111 | 2003 if (i2 < _ifg->_maxlrg) { |
| 2004 lrgs(i2).dump(); | |
| 2005 } | |
| 2006 else { | |
| 2007 tty->print_cr("new LRG"); | |
| 2008 } | |
| 0 | 2009 } |
| 2010 tty->print_cr(""); | |
| 2011 | |
| 2012 // Dump lo-degree list | |
| 2013 tty->print("Lo degree: "); | |
| 2014 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next ) | |
| 2015 tty->print("L%d ",i3); | |
| 2016 tty->print_cr(""); | |
| 2017 | |
| 2018 // Dump lo-stk-degree list | |
| 2019 tty->print("Lo stk degree: "); | |
| 2020 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next ) | |
| 2021 tty->print("L%d ",i4); | |
| 2022 tty->print_cr(""); | |
| 2023 | |
| 2024 // Dump lo-degree list | |
| 2025 tty->print("Hi degree: "); | |
| 2026 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) | |
| 2027 tty->print("L%d ",i5); | |
| 2028 tty->print_cr(""); | |
| 2029 } | |
| 2030 | |
| 2031 void PhaseChaitin::dump_degree_lists() const { | |
| 2032 // Dump lo-degree list | |
| 2033 tty->print("Lo degree: "); | |
| 2034 for( uint i = _lo_degree; i; i = lrgs(i)._next ) | |
| 2035 tty->print("L%d ",i); | |
| 2036 tty->print_cr(""); | |
| 2037 | |
| 2038 // Dump lo-stk-degree list | |
| 2039 tty->print("Lo stk degree: "); | |
| 2040 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next ) | |
| 2041 tty->print("L%d ",i2); | |
| 2042 tty->print_cr(""); | |
| 2043 | |
| 2044 // Dump lo-degree list | |
| 2045 tty->print("Hi degree: "); | |
| 2046 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) | |
| 2047 tty->print("L%d ",i3); | |
| 2048 tty->print_cr(""); | |
| 2049 } | |
| 2050 | |
| 2051 void PhaseChaitin::dump_simplified() const { | |
| 2052 tty->print("Simplified: "); | |
| 2053 for( uint i = _simplified; i; i = lrgs(i)._next ) | |
| 2054 tty->print("L%d ",i); | |
| 2055 tty->print_cr(""); | |
| 2056 } | |
| 2057 | |
| 2058 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) { | |
| 2059 if ((int)reg < 0) | |
| 2060 sprintf(buf, "<OptoReg::%d>", (int)reg); | |
| 2061 else if (OptoReg::is_reg(reg)) | |
| 2062 strcpy(buf, Matcher::regName[reg]); | |
| 2063 else | |
| 2064 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 2065 pc->reg2offset(reg)); | |
| 2066 return buf+strlen(buf); | |
| 2067 } | |
| 2068 | |
| 2069 // Dump a register name into a buffer. Be intelligent if we get called | |
| 2070 // before allocation is complete. | |
| 2071 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { | |
| 2072 if( !this ) { // Not got anything? | |
| 2073 sprintf(buf,"N%d",n->_idx); // Then use Node index | |
| 2074 } else if( _node_regs ) { | |
| 2075 // Post allocation, use direct mappings, no LRG info available | |
| 2076 print_reg( get_reg_first(n), this, buf ); | |
| 2077 } else { | |
| 10111 | 2078 uint lidx = _lrg_map.find_const(n); // Grab LRG number |
| 0 | 2079 if( !_ifg ) { |
| 2080 sprintf(buf,"L%d",lidx); // No register binding yet | |
| 2081 } else if( !lidx ) { // Special, not allocated value | |
| 2082 strcpy(buf,"Special"); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2083 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2084 if (lrgs(lidx)._is_vector) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2085 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs())) |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2086 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2087 else |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2088 sprintf(buf,"L%d",lidx); // No register binding yet |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2089 } else if( (lrgs(lidx).num_regs() == 1) |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2090 ? lrgs(lidx).mask().is_bound1() |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2091 : lrgs(lidx).mask().is_bound_pair() ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2092 // Hah! We have a bound machine register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2093 print_reg( lrgs(lidx).reg(), this, buf ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2094 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2095 sprintf(buf,"L%d",lidx); // No register binding yet |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
2096 } |
| 0 | 2097 } |
| 2098 } | |
| 2099 return buf+strlen(buf); | |
| 2100 } | |
| 2101 | |
| 2102 void PhaseChaitin::dump_for_spill_split_recycle() const { | |
| 2103 if( WizardMode && (PrintCompilation || PrintOpto) ) { | |
| 2104 // Display which live ranges need to be split and the allocator's state | |
| 2105 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); | |
| 10111 | 2106 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { |
| 0 | 2107 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { |
| 2108 tty->print("L%d: ", bidx); | |
| 2109 lrgs(bidx).dump(); | |
| 2110 } | |
| 2111 } | |
| 2112 tty->cr(); | |
| 2113 dump(); | |
| 2114 } | |
| 2115 } | |
| 2116 | |
| 2117 void PhaseChaitin::dump_frame() const { | |
| 2118 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); | |
| 2119 const TypeTuple *domain = C->tf()->domain(); | |
| 2120 const int argcnt = domain->cnt() - TypeFunc::Parms; | |
| 2121 | |
| 2122 // Incoming arguments in registers dump | |
| 2123 for( int k = 0; k < argcnt; k++ ) { | |
| 2124 OptoReg::Name parmreg = _matcher._parm_regs[k].first(); | |
| 2125 if( OptoReg::is_reg(parmreg)) { | |
| 2126 const char *reg_name = OptoReg::regname(parmreg); | |
| 2127 tty->print("#r%3.3d %s", parmreg, reg_name); | |
| 2128 parmreg = _matcher._parm_regs[k].second(); | |
| 2129 if( OptoReg::is_reg(parmreg)) { | |
| 2130 tty->print(":%s", OptoReg::regname(parmreg)); | |
| 2131 } | |
| 2132 tty->print(" : parm %d: ", k); | |
| 2133 domain->field_at(k + TypeFunc::Parms)->dump(); | |
| 2134 tty->print_cr(""); | |
| 2135 } | |
| 2136 } | |
| 2137 | |
| 2138 // Check for un-owned padding above incoming args | |
| 2139 OptoReg::Name reg = _matcher._new_SP; | |
| 2140 if( reg > _matcher._in_arg_limit ) { | |
| 2141 reg = OptoReg::add(reg, -1); | |
| 2142 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg)); | |
| 2143 } | |
| 2144 | |
| 2145 // Incoming argument area dump | |
| 2146 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()); | |
| 2147 while( reg > begin_in_arg ) { | |
| 2148 reg = OptoReg::add(reg, -1); | |
| 2149 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); | |
| 2150 int j; | |
| 2151 for( j = 0; j < argcnt; j++) { | |
| 2152 if( _matcher._parm_regs[j].first() == reg || | |
| 2153 _matcher._parm_regs[j].second() == reg ) { | |
| 2154 tty->print("parm %d: ",j); | |
| 2155 domain->field_at(j + TypeFunc::Parms)->dump(); | |
| 2156 tty->print_cr(""); | |
| 2157 break; | |
| 2158 } | |
| 2159 } | |
| 2160 if( j >= argcnt ) | |
| 2161 tty->print_cr("HOLE, owned by SELF"); | |
| 2162 } | |
| 2163 | |
| 2164 // Old outgoing preserve area | |
| 2165 while( reg > _matcher._old_SP ) { | |
| 2166 reg = OptoReg::add(reg, -1); | |
| 2167 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg)); | |
| 2168 } | |
| 2169 | |
| 2170 // Old SP | |
| 2171 tty->print_cr("# -- Old %s -- Framesize: %d --",fp, | |
| 2172 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize); | |
| 2173 | |
| 2174 // Preserve area dump | |
| 4950 | 2175 int fixed_slots = C->fixed_slots(); |
| 2176 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots()); | |
| 2177 OptoReg::Name return_addr = _matcher.return_addr(); | |
| 2178 | |
| 0 | 2179 reg = OptoReg::add(reg, -1); |
| 4950 | 2180 while (OptoReg::is_stack(reg)) { |
| 0 | 2181 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); |
| 4950 | 2182 if (return_addr == reg) { |
| 0 | 2183 tty->print_cr("return address"); |
| 4950 | 2184 } else if (reg >= begin_in_preserve) { |
| 2185 // Preserved slots are present on x86 | |
| 2186 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word)) | |
| 2187 tty->print_cr("saved fp register"); | |
| 2188 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) && | |
| 2189 VerifyStackAtCalls) | |
| 2190 tty->print_cr("0xBADB100D +VerifyStackAtCalls"); | |
| 2191 else | |
| 2192 tty->print_cr("in_preserve"); | |
| 2193 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) { | |
| 0 | 2194 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg)); |
| 4950 | 2195 } else { |
| 2196 tty->print_cr("pad2, stack alignment"); | |
| 2197 } | |
| 0 | 2198 reg = OptoReg::add(reg, -1); |
| 2199 } | |
| 2200 | |
| 2201 // Spill area dump | |
| 2202 reg = OptoReg::add(_matcher._new_SP, _framesize ); | |
| 2203 while( reg > _matcher._out_arg_limit ) { | |
| 2204 reg = OptoReg::add(reg, -1); | |
| 2205 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg)); | |
| 2206 } | |
| 2207 | |
| 2208 // Outgoing argument area dump | |
| 2209 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) { | |
| 2210 reg = OptoReg::add(reg, -1); | |
| 2211 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg)); | |
| 2212 } | |
| 2213 | |
| 2214 // Outgoing new preserve area | |
| 2215 while( reg > _matcher._new_SP ) { | |
| 2216 reg = OptoReg::add(reg, -1); | |
| 2217 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); | |
| 2218 } | |
| 2219 tty->print_cr("#"); | |
| 2220 } | |
| 2221 | |
| 2222 void PhaseChaitin::dump_bb( uint pre_order ) const { | |
| 2223 tty->print_cr("---dump of B%d---",pre_order); | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2224 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2225 Block* block = _cfg.get_block(i); |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2226 if (block->_pre_order == pre_order) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2227 dump(block); |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2228 } |
| 0 | 2229 } |
| 2230 } | |
| 2231 | |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2232 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { |
| 0 | 2233 tty->print_cr("---dump of L%d---",lidx); |
| 2234 | |
| 10111 | 2235 if (_ifg) { |
| 2236 if (lidx >= _lrg_map.max_lrg_id()) { | |
| 0 | 2237 tty->print("Attempt to print live range index beyond max live range.\n"); |
| 2238 return; | |
| 2239 } | |
| 2240 tty->print("L%d: ",lidx); | |
| 10111 | 2241 if (lidx < _ifg->_maxlrg) { |
| 2242 lrgs(lidx).dump(); | |
| 2243 } else { | |
| 2244 tty->print_cr("new LRG"); | |
| 2245 } | |
| 0 | 2246 } |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2247 if( _ifg && lidx < _ifg->_maxlrg) { |
|
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2248 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); |
| 0 | 2249 _ifg->neighbors(lidx)->dump(); |
| 2250 tty->cr(); | |
| 2251 } | |
| 2252 // For all blocks | |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2253 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2254 Block* block = _cfg.get_block(i); |
| 0 | 2255 int dump_once = 0; |
| 2256 | |
| 2257 // For all instructions | |
|
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
2258 for( uint j = 0; j < block->number_of_nodes(); j++ ) { |
|
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12075
diff
changeset
|
2259 Node *n = block->get_node(j); |
| 10111 | 2260 if (_lrg_map.find_const(n) == lidx) { |
| 2261 if (!dump_once++) { | |
| 0 | 2262 tty->cr(); |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2263 block->dump_head(&_cfg); |
| 0 | 2264 } |
| 2265 dump(n); | |
| 2266 continue; | |
| 2267 } | |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2268 if (!defs_only) { |
|
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2269 uint cnt = n->req(); |
|
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2270 for( uint k = 1; k < cnt; k++ ) { |
|
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2271 Node *m = n->in(k); |
| 10111 | 2272 if (!m) { |
| 2273 continue; // be robust in the dumper | |
| 2274 } | |
| 2275 if (_lrg_map.find_const(m) == lidx) { | |
| 2276 if (!dump_once++) { | |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2277 tty->cr(); |
|
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
2278 block->dump_head(&_cfg); |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2279 } |
|
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
never
parents:
1972
diff
changeset
|
2280 dump(n); |
| 0 | 2281 } |
| 2282 } | |
| 2283 } | |
| 2284 } | |
| 2285 } // End of per-block dump | |
| 2286 tty->cr(); | |
| 2287 } | |
| 2288 #endif // not PRODUCT | |
| 2289 | |
| 2290 int PhaseChaitin::_final_loads = 0; | |
| 2291 int PhaseChaitin::_final_stores = 0; | |
| 2292 int PhaseChaitin::_final_memoves= 0; | |
| 2293 int PhaseChaitin::_final_copies = 0; | |
| 2294 double PhaseChaitin::_final_load_cost = 0; | |
| 2295 double PhaseChaitin::_final_store_cost = 0; | |
| 2296 double PhaseChaitin::_final_memove_cost= 0; | |
| 2297 double PhaseChaitin::_final_copy_cost = 0; | |
| 2298 int PhaseChaitin::_conserv_coalesce = 0; | |
| 2299 int PhaseChaitin::_conserv_coalesce_pair = 0; | |
| 2300 int PhaseChaitin::_conserv_coalesce_trie = 0; | |
| 2301 int PhaseChaitin::_conserv_coalesce_quad = 0; | |
| 2302 int PhaseChaitin::_post_alloc = 0; | |
| 2303 int PhaseChaitin::_lost_opp_pp_coalesce = 0; | |
| 2304 int PhaseChaitin::_lost_opp_cflow_coalesce = 0; | |
| 2305 int PhaseChaitin::_used_cisc_instructions = 0; | |
| 2306 int PhaseChaitin::_unused_cisc_instructions = 0; | |
| 2307 int PhaseChaitin::_allocator_attempts = 0; | |
| 2308 int PhaseChaitin::_allocator_successes = 0; | |
| 2309 | |
| 2310 #ifndef PRODUCT | |
| 2311 uint PhaseChaitin::_high_pressure = 0; | |
| 2312 uint PhaseChaitin::_low_pressure = 0; | |
| 2313 | |
| 2314 void PhaseChaitin::print_chaitin_statistics() { | |
| 2315 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies); | |
| 2316 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost); | |
| 2317 tty->print_cr("Adjusted spill cost = %7.0f.", | |
| 2318 _final_load_cost*4.0 + _final_store_cost * 2.0 + | |
| 2319 _final_copy_cost*1.0 + _final_memove_cost*12.0); | |
| 2320 tty->print("Conservatively coalesced %d copies, %d pairs", | |
| 2321 _conserv_coalesce, _conserv_coalesce_pair); | |
| 2322 if( _conserv_coalesce_trie || _conserv_coalesce_quad ) | |
| 2323 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad); | |
| 2324 tty->print_cr(", %d post alloc.", _post_alloc); | |
| 2325 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce ) | |
| 2326 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.", | |
| 2327 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce ); | |
| 2328 if( _used_cisc_instructions || _unused_cisc_instructions ) | |
| 2329 tty->print_cr("Used cisc instruction %d, remained in register %d", | |
| 2330 _used_cisc_instructions, _unused_cisc_instructions); | |
| 2331 if( _allocator_successes != 0 ) | |
| 2332 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes); | |
| 2333 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure); | |
| 2334 } | |
| 2335 #endif // not PRODUCT |