Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 2008:2f644f85485d
6961690: load oops from constant table on SPARC
Summary: oops should be loaded from the constant table of an nmethod instead of materializing them with a long code sequence.
Reviewed-by: never, kvn
| author | twisti |
|---|---|
| date | Fri, 03 Dec 2010 01:34:31 -0800 |
| parents | 885e464e1a40 |
| children | 5fe0781a8560 |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
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398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
| 429 %} | |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 463 // Macros to extract hi & lo halves from a long pair. | |
| 464 // G0 is not part of any long pair, so assert on that. | |
| 605 | 465 // Prevents accidentally using G1 instead of G0. |
| 0 | 466 #define LONG_HI_REG(x) (x) |
| 467 #define LONG_LO_REG(x) (x) | |
| 468 | |
| 469 %} | |
| 470 | |
| 471 source %{ | |
| 472 #define __ _masm. | |
| 473 | |
|
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474 // Block initializing store |
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475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
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476 |
| 0 | 477 // tertiary op of a LoadP or StoreP encoding |
| 478 #define REGP_OP true | |
| 479 | |
| 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 482 static Register reg_to_register_object(int register_encoding); | |
| 483 | |
| 484 // Used by the DFA in dfa_sparc.cpp. | |
| 485 // Check for being able to use a V9 branch-on-register. Requires a | |
| 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 487 // extended. Doesn't work following an integer ADD, for example, because of | |
| 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 490 // replace them with zero, which could become sign-extension in a different OS | |
| 491 // release. There's no obvious reason why an interrupt will ever fill these | |
| 492 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 493 // instructions which either zero-fill or sign-fill). | |
| 494 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 495 if( !BranchOnRegister ) return false; | |
| 496 #ifdef _LP64 | |
| 497 if( cmp->Opcode() == Op_CmpP ) | |
| 498 return true; // No problems with pointer compares | |
| 499 #endif | |
| 500 if( cmp->Opcode() == Op_CmpL ) | |
| 501 return true; // No problems with long compares | |
| 502 | |
| 503 if( !SparcV9RegsHiBitsZero ) return false; | |
| 504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 506 return false; | |
| 507 | |
| 508 // Check for comparing against a 'safe' value. Any operation which | |
| 509 // clears out the high word is safe. Thus, loads and certain shifts | |
| 510 // are safe, as are non-negative constants. Any operation which | |
| 511 // preserves zero bits in the high word is safe as long as each of its | |
| 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 513 // inputs are safe. At present, the only important case to recognize | |
| 514 // seems to be loads. Constants should fold away, and shifts & | |
| 515 // logicals can use the 'cc' forms. | |
| 516 Node *x = cmp->in(1); | |
| 517 if( x->is_Load() ) return true; | |
| 518 if( x->is_Phi() ) { | |
| 519 for( uint i = 1; i < x->req(); i++ ) | |
| 520 if( !x->in(i)->is_Load() ) | |
| 521 return false; | |
| 522 return true; | |
| 523 } | |
| 524 return false; | |
| 525 } | |
| 526 | |
| 527 // **************************************************************************** | |
| 528 | |
| 529 // REQUIRED FUNCTIONALITY | |
| 530 | |
| 531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 532 // from the start of the call to the point where the return address | |
| 533 // will point. | |
| 534 // The "return address" is the address of the call instruction, plus 8. | |
| 535 | |
| 536 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 537 int offset = NativeCall::instruction_size; // call; delay slot |
| 538 if (_method_handle_invoke) | |
| 539 offset += 4; // restore SP | |
| 540 return offset; | |
| 0 | 541 } |
| 542 | |
| 543 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 544 int vtable_index = this->_vtable_index; | |
| 545 if (vtable_index < 0) { | |
| 546 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 548 return (NativeMovConstReg::instruction_size + | |
| 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 550 } else { | |
| 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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554 int klass_load_size; |
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555 if (UseCompressedOops) { |
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556 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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557 if (Universe::narrow_oop_base() == NULL) |
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558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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559 else |
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560 klass_load_size = 3*BytesPerInstWord; |
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561 } else { |
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562 klass_load_size = 1*BytesPerInstWord; |
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563 } |
| 0 | 564 if( Assembler::is_simm13(v_off) ) { |
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565 return klass_load_size + |
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566 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 567 NativeCall::instruction_size); // call; delay slot |
| 568 } else { | |
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569 return klass_load_size + |
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570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 571 NativeCall::instruction_size); // call; delay slot |
| 572 } | |
| 573 } | |
| 574 } | |
| 575 | |
| 576 int MachCallRuntimeNode::ret_addr_offset() { | |
| 577 #ifdef _LP64 | |
| 578 return NativeFarCall::instruction_size; // farcall; delay slot | |
| 579 #else | |
| 580 return NativeCall::instruction_size; // call; delay slot | |
| 581 #endif | |
| 582 } | |
| 583 | |
| 584 // Indicate if the safepoint node needs the polling page as an input. | |
| 585 // Since Sparc does not have absolute addressing, it does. | |
| 586 bool SafePointNode::needs_polling_address_input() { | |
| 587 return true; | |
| 588 } | |
| 589 | |
| 590 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 591 void emit_break(CodeBuffer &cbuf) { | |
| 592 MacroAssembler _masm(&cbuf); | |
| 593 __ breakpoint_trap(); | |
| 594 } | |
| 595 | |
| 596 #ifndef PRODUCT | |
| 597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 598 st->print("TA"); | |
| 599 } | |
| 600 #endif | |
| 601 | |
| 602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 603 emit_break(cbuf); | |
| 604 } | |
| 605 | |
| 606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 607 return MachNode::size(ra_); | |
| 608 } | |
| 609 | |
| 610 // Traceable jump | |
| 611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 612 MacroAssembler _masm(&cbuf); | |
| 613 Register rdest = reg_to_register_object(jump_target); | |
| 614 __ JMP(rdest, 0); | |
| 615 __ delayed()->nop(); | |
| 616 } | |
| 617 | |
| 618 // Traceable jump and set exception pc | |
| 619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 620 MacroAssembler _masm(&cbuf); | |
| 621 Register rdest = reg_to_register_object(jump_target); | |
| 622 __ JMP(rdest, 0); | |
| 623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 624 } | |
| 625 | |
| 626 void emit_nop(CodeBuffer &cbuf) { | |
| 627 MacroAssembler _masm(&cbuf); | |
| 628 __ nop(); | |
| 629 } | |
| 630 | |
| 631 void emit_illtrap(CodeBuffer &cbuf) { | |
| 632 MacroAssembler _masm(&cbuf); | |
| 633 __ illtrap(0); | |
| 634 } | |
| 635 | |
| 636 | |
| 637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 638 assert(n->rule() != loadUB_rule, ""); | |
| 639 | |
| 640 intptr_t offset = 0; | |
| 641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 642 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 644 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 645 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 646 atype = atype->add_offset(offset); | |
| 647 assert(disp32 == offset, "wrong disp32"); | |
| 648 return atype->_offset; | |
| 649 } | |
| 650 | |
| 651 | |
| 652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 653 assert(n->rule() != loadUB_rule, ""); | |
| 654 | |
| 655 intptr_t offset = 0; | |
| 656 Node* addr = n->in(2); | |
| 657 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 659 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 660 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 662 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 663 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 664 } | |
| 665 offset = atype->is_ptr()->_offset; | |
| 666 if (offset != Type::OffsetBot) offset += disp32; | |
| 667 return offset; | |
| 668 } | |
| 669 | |
| 2008 | 670 static inline jdouble replicate_immI(int con, int count, int width) { |
| 671 // Load a constant replicated "count" times with width "width" | |
| 672 int bit_width = width * 8; | |
| 673 jlong elt_val = con; | |
| 674 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits | |
| 675 jlong val = elt_val; | |
| 676 for (int i = 0; i < count - 1; i++) { | |
| 677 val <<= bit_width; | |
| 678 val |= elt_val; | |
| 679 } | |
| 680 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 681 return dval; | |
| 682 } | |
| 683 | |
| 0 | 684 // Standard Sparc opcode form2 field breakdown |
| 685 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 686 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 687 int op = (f30 << 30) | | |
| 688 (f29 << 29) | | |
| 689 (f25 << 25) | | |
| 690 (f22 << 22) | | |
| 691 (f20 << 20) | | |
| 692 (f19 << 19) | | |
| 693 (f0 << 0); | |
| 1748 | 694 cbuf.insts()->emit_int32(op); |
| 0 | 695 } |
| 696 | |
| 697 // Standard Sparc opcode form2 field breakdown | |
| 698 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 699 f0 >>= 10; // Drop 10 bits | |
| 700 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 701 int op = (f30 << 30) | | |
| 702 (f25 << 25) | | |
| 703 (f22 << 22) | | |
| 704 (f0 << 0); | |
| 1748 | 705 cbuf.insts()->emit_int32(op); |
| 0 | 706 } |
| 707 | |
| 708 // Standard Sparc opcode form3 field breakdown | |
| 709 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 710 int op = (f30 << 30) | | |
| 711 (f25 << 25) | | |
| 712 (f19 << 19) | | |
| 713 (f14 << 14) | | |
| 714 (f5 << 5) | | |
| 715 (f0 << 0); | |
| 1748 | 716 cbuf.insts()->emit_int32(op); |
| 0 | 717 } |
| 718 | |
| 719 // Standard Sparc opcode form3 field breakdown | |
| 720 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 721 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 722 int op = (f30 << 30) | | |
| 723 (f25 << 25) | | |
| 724 (f19 << 19) | | |
| 725 (f14 << 14) | | |
| 726 (1 << 13) | // bit to indicate immediate-mode | |
| 727 (simm13<<0); | |
| 1748 | 728 cbuf.insts()->emit_int32(op); |
| 0 | 729 } |
| 730 | |
| 731 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 732 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 733 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 734 } | |
| 735 | |
| 736 #ifdef ASSERT | |
| 737 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 738 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 739 warning("VerifyOops encountered unexpected instruction:"); | |
| 740 n->dump(2); | |
| 741 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 742 } | |
| 743 #endif | |
| 744 | |
| 745 | |
| 746 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 747 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 748 | |
| 749 #ifdef ASSERT | |
| 750 // The following code implements the +VerifyOops feature. | |
| 751 // It verifies oop values which are loaded into or stored out of | |
| 752 // the current method activation. +VerifyOops complements techniques | |
| 753 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 754 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 755 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 756 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 757 // to their point of creation. It can also serve as a cross-check | |
| 758 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 759 | |
| 760 // It would be good to verify oops at other points, especially | |
| 761 // when an oop is used as a base pointer for a load or store. | |
| 762 // This is presently difficult, because it is hard to know when | |
| 763 // a base address is biased or not. (If we had such information, | |
| 764 // it would be easy and useful to make a two-argument version of | |
| 765 // verify_oop which unbiases the base, and performs verification.) | |
| 766 | |
| 767 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 768 bool is_verified_oop_base = false; | |
| 769 bool is_verified_oop_load = false; | |
| 770 bool is_verified_oop_store = false; | |
| 771 int tmp_enc = -1; | |
| 772 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 773 // classify the op, mainly for an assert check | |
| 774 int st_op = 0, ld_op = 0; | |
| 775 switch (primary) { | |
| 776 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 777 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 778 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 779 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 780 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 781 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 782 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 783 | |
| 784 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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785 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 786 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 787 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 788 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 789 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 790 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 791 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 792 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 793 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 794 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 795 | |
| 796 default: ShouldNotReachHere(); | |
| 797 } | |
| 798 if (tertiary == REGP_OP) { | |
| 799 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 800 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 801 else ShouldNotReachHere(); | |
| 802 if (st_op) { | |
| 803 // a store | |
| 804 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 805 Node* n2 = n->in(3); | |
| 806 if (n2 != NULL) { | |
| 807 const Type* t = n2->bottom_type(); | |
| 808 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 809 } | |
| 810 } else { | |
| 811 // a load | |
| 812 const Type* t = n->bottom_type(); | |
| 813 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 814 } | |
| 815 } | |
| 816 | |
| 817 if (ld_op) { | |
| 818 // a Load | |
| 819 // inputs are (0:control, 1:memory, 2:address) | |
| 820 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 821 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 822 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 823 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 824 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 825 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 826 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 827 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 828 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 829 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 830 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 831 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 832 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 833 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
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834 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && |
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835 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && |
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836 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && |
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837 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && |
| 0 | 838 !(n->rule() == loadUB_rule)) { |
| 839 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 840 } | |
| 841 } else if (st_op) { | |
| 842 // a Store | |
| 843 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 844 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 845 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 846 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 847 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 848 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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849 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && |
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850 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && |
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851 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && |
| 0 | 852 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 853 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 854 } | |
| 855 } | |
| 856 | |
| 857 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 858 Node* addr = n->in(2); | |
| 859 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 860 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 861 if (atype != NULL) { | |
| 862 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 863 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 864 if (offset != offset_2) { | |
| 865 get_offset_from_base(n, atype, disp32); | |
| 866 get_offset_from_base_2(n, atype, disp32); | |
| 867 } | |
| 868 assert(offset == offset_2, "different offsets"); | |
| 869 if (offset == disp32) { | |
| 870 // we now know that src1 is a true oop pointer | |
| 871 is_verified_oop_base = true; | |
| 872 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 873 if( primary == Assembler::ldd_op3 ) { | |
| 874 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 875 } else { | |
| 876 tmp_enc = dst_enc; | |
| 877 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 878 assert(src1_enc != dst_enc, ""); | |
| 879 } | |
| 880 } | |
| 881 } | |
| 882 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 883 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 884 // loading the mark should not be allowed either, but | |
| 885 // we don't check this since it conflicts with InlineObjectHash | |
| 886 // usage of LoadINode to get the mark. We could keep the | |
| 887 // check if we create a new LoadMarkNode | |
| 888 // but do not verify the object before its header is initialized | |
| 889 ShouldNotReachHere(); | |
| 890 } | |
| 891 } | |
| 892 } | |
| 893 } | |
| 894 } | |
| 895 #endif | |
| 896 | |
| 897 uint instr; | |
| 898 instr = (Assembler::ldst_op << 30) | |
| 899 | (dst_enc << 25) | |
| 900 | (primary << 19) | |
| 901 | (src1_enc << 14); | |
| 902 | |
| 903 uint index = src2_enc; | |
| 904 int disp = disp32; | |
| 905 | |
| 906 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 907 disp += STACK_BIAS; | |
| 908 | |
| 909 // We should have a compiler bailout here rather than a guarantee. | |
| 910 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 911 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 912 | |
| 913 if( disp == 0 ) { | |
| 914 // use reg-reg form | |
| 915 // bit 13 is already zero | |
| 916 instr |= index; | |
| 917 } else { | |
| 918 // use reg-imm form | |
| 919 instr |= 0x00002000; // set bit 13 to one | |
| 920 instr |= disp & 0x1FFF; | |
| 921 } | |
| 922 | |
| 1748 | 923 cbuf.insts()->emit_int32(instr); |
| 0 | 924 |
| 925 #ifdef ASSERT | |
| 926 { | |
| 927 MacroAssembler _masm(&cbuf); | |
| 928 if (is_verified_oop_base) { | |
| 929 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 930 } | |
| 931 if (is_verified_oop_store) { | |
| 932 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 933 } | |
| 934 if (tmp_enc != -1) { | |
| 935 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 936 } | |
| 937 if (is_verified_oop_load) { | |
| 938 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 939 } | |
| 940 } | |
| 941 #endif | |
| 942 } | |
| 943 | |
| 944 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
| 945 // The method which records debug information at every safepoint | |
| 946 // expects the call to be the first instruction in the snippet as | |
| 947 // it creates a PcDesc structure which tracks the offset of a call | |
| 948 // from the start of the codeBlob. This offset is computed as | |
| 949 // code_end() - code_begin() of the code which has been emitted | |
| 950 // so far. | |
| 951 // In this particular case we have skirted around the problem by | |
| 952 // putting the "mov" instruction in the delay slot but the problem | |
| 953 // may bite us again at some other point and a cleaner/generic | |
| 954 // solution using relocations would be needed. | |
| 955 MacroAssembler _masm(&cbuf); | |
| 956 __ set_inst_mark(); | |
| 957 | |
| 958 // We flush the current window just so that there is a valid stack copy | |
| 959 // the fact that the current window becomes active again instantly is | |
| 960 // not a problem there is nothing live in it. | |
| 961 | |
| 962 #ifdef ASSERT | |
| 963 int startpos = __ offset(); | |
| 964 #endif /* ASSERT */ | |
| 965 | |
| 966 #ifdef _LP64 | |
| 967 // Calls to the runtime or native may not be reachable from compiled code, | |
| 968 // so we generate the far call sequence on 64 bit sparc. | |
| 969 // This code sequence is relocatable to any address, even on LP64. | |
| 970 if ( force_far_call ) { | |
| 971 __ relocate(rtype); | |
| 727 | 972 AddressLiteral dest(entry_point); |
| 973 __ jumpl_to(dest, O7, O7); | |
| 0 | 974 } |
| 975 else | |
| 976 #endif | |
| 977 { | |
| 978 __ call((address)entry_point, rtype); | |
| 979 } | |
| 980 | |
| 981 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 982 else __ delayed()->nop(); | |
| 983 | |
| 984 if (preserve_g2) __ mov(L7, G2); | |
| 985 | |
| 986 #ifdef ASSERT | |
| 987 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 988 #ifdef _LP64 | |
| 989 // Trash argument dump slots. | |
| 990 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 991 __ mov(G1, G5); | |
| 992 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 993 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 994 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 995 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 996 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 997 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 998 #else // _LP64 | |
| 999 // this is also a native call, so smash the first 7 stack locations, | |
| 1000 // and the various registers | |
| 1001 | |
| 1002 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 1003 // while [SP+0x44..0x58] are the argument dump slots. | |
| 1004 __ set((intptr_t)0xbaadf00d, G1); | |
| 1005 __ mov(G1, G5); | |
| 1006 __ sllx(G1, 32, G1); | |
| 1007 __ or3(G1, G5, G1); | |
| 1008 __ mov(G1, G5); | |
| 1009 __ stx(G1, SP, 0x40); | |
| 1010 __ stx(G1, SP, 0x48); | |
| 1011 __ stx(G1, SP, 0x50); | |
| 1012 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1013 #endif // _LP64 | |
| 1014 } | |
| 1015 #endif /*ASSERT*/ | |
| 1016 } | |
| 1017 | |
| 1018 //============================================================================= | |
| 1019 // REQUIRED FUNCTIONALITY for encoding | |
| 1020 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1021 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1022 | |
| 1023 | |
| 1024 //============================================================================= | |
| 2008 | 1025 const bool Matcher::constant_table_absolute_addressing = false; |
| 1026 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; | |
| 1027 | |
| 1028 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 1029 Compile* C = ra_->C; | |
| 1030 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1031 MacroAssembler _masm(&cbuf); | |
| 1032 | |
| 1033 Register r = as_Register(ra_->get_encode(this)); | |
| 1034 CodeSection* cs = __ code()->consts(); | |
| 1035 int consts_size = cs->align_at_start(cs->size()); | |
| 1036 | |
| 1037 if (UseRDPCForConstantTableBase) { | |
| 1038 // For the following RDPC logic to work correctly the consts | |
| 1039 // section must be allocated right before the insts section. This | |
| 1040 // assert checks for that. The layout and the SECT_* constants | |
| 1041 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1042 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
| 1043 int offset = __ offset(); | |
| 1044 int disp; | |
| 1045 | |
| 1046 // If the displacement from the current PC to the constant table | |
| 1047 // base fits into simm13 we set the constant table base to the | |
| 1048 // current PC. | |
| 1049 if (__ is_simm13(-(consts_size + offset))) { | |
| 1050 constant_table.set_table_base_offset(-(consts_size + offset)); | |
| 1051 disp = 0; | |
| 1052 } else { | |
| 1053 // If the offset of the top constant (last entry in the table) | |
| 1054 // fits into simm13 we set the constant table base to the actual | |
| 1055 // table base. | |
| 1056 if (__ is_simm13(constant_table.top_offset())) { | |
| 1057 constant_table.set_table_base_offset(0); | |
| 1058 disp = consts_size + offset; | |
| 1059 } else { | |
| 1060 // Otherwise we set the constant table base in the middle of the | |
| 1061 // constant table. | |
| 1062 int half_consts_size = consts_size / 2; | |
| 1063 assert(half_consts_size * 2 == consts_size, "sanity"); | |
| 1064 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. | |
| 1065 disp = half_consts_size + offset; | |
| 1066 } | |
| 1067 } | |
| 1068 | |
| 1069 __ rdpc(r); | |
| 1070 | |
| 1071 if (disp != 0) { | |
| 1072 assert(r != O7, "need temporary"); | |
| 1073 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1074 } | |
| 1075 } | |
| 1076 else { | |
| 1077 // Materialize the constant table base. | |
| 1078 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | |
| 1079 address baseaddr = cs->start() + -(constant_table.table_base_offset()); | |
| 1080 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); | |
| 1081 AddressLiteral base(baseaddr, rspec); | |
| 1082 __ set(base, r); | |
| 1083 } | |
| 1084 } | |
| 1085 | |
| 1086 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1087 if (UseRDPCForConstantTableBase) { | |
| 1088 // This is really the worst case but generally it's only 1 instruction. | |
| 1089 return 4 /*rdpc*/ + 4 /*sub*/ + MacroAssembler::worst_case_size_of_set(); | |
| 1090 } else { | |
| 1091 return MacroAssembler::worst_case_size_of_set(); | |
| 1092 } | |
| 1093 } | |
| 1094 | |
| 1095 #ifndef PRODUCT | |
| 1096 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1097 char reg[128]; | |
| 1098 ra_->dump_register(this, reg); | |
| 1099 if (UseRDPCForConstantTableBase) { | |
| 1100 st->print("RDPC %s\t! constant table base", reg); | |
| 1101 } else { | |
| 1102 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1103 } | |
| 1104 } | |
| 1105 #endif | |
| 1106 | |
| 1107 | |
| 1108 //============================================================================= | |
| 0 | 1109 |
| 1110 #ifndef PRODUCT | |
| 1111 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1112 Compile* C = ra_->C; | |
| 1113 | |
| 1114 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1115 st->print_cr("NOP"); st->print("\t"); | |
| 1116 } | |
| 1117 | |
| 1118 if( VerifyThread ) { | |
| 1119 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1120 } | |
| 1121 | |
| 1122 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1123 | |
| 1124 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1125 // We require that their callers must bang for them. But be careful, because | |
| 1126 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1127 // stack. But the stack safety zone should account for that. | |
| 1128 // See bugs 4446381, 4468289, 4497237. | |
| 1129 if (C->need_stack_bang(framesize)) { | |
| 1130 st->print_cr("! stack bang"); st->print("\t"); | |
| 1131 } | |
| 1132 | |
| 1133 if (Assembler::is_simm13(-framesize)) { | |
| 1134 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1135 } else { | |
| 1136 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1137 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1138 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1139 } | |
| 1140 | |
| 1141 } | |
| 1142 #endif | |
| 1143 | |
| 1144 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1145 Compile* C = ra_->C; | |
| 1146 MacroAssembler _masm(&cbuf); | |
| 1147 | |
| 1148 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1149 __ nop(); | |
| 1150 } | |
| 1151 | |
| 1152 __ verify_thread(); | |
| 1153 | |
| 1154 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1155 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1156 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1157 | |
| 1158 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1159 // We require that their callers must bang for them. But be careful, because | |
| 1160 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1161 // stack. But the stack safety zone should account for that. | |
| 1162 // See bugs 4446381, 4468289, 4497237. | |
| 1163 if (C->need_stack_bang(framesize)) { | |
| 1164 __ generate_stack_overflow_check(framesize); | |
| 1165 } | |
| 1166 | |
| 1167 if (Assembler::is_simm13(-framesize)) { | |
| 1168 __ save(SP, -framesize, SP); | |
| 1169 } else { | |
| 1170 __ sethi(-framesize & ~0x3ff, G3); | |
| 1171 __ add(G3, -framesize & 0x3ff, G3); | |
| 1172 __ save(SP, G3, SP); | |
| 1173 } | |
| 1174 C->set_frame_complete( __ offset() ); | |
| 1175 } | |
| 1176 | |
| 1177 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1178 return MachNode::size(ra_); | |
| 1179 } | |
| 1180 | |
| 1181 int MachPrologNode::reloc() const { | |
| 1182 return 10; // a large enough number | |
| 1183 } | |
| 1184 | |
| 1185 //============================================================================= | |
| 1186 #ifndef PRODUCT | |
| 1187 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1188 Compile* C = ra_->C; | |
| 1189 | |
| 1190 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1191 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1192 #ifdef _LP64 | |
| 1193 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1194 #else | |
| 1195 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1196 #endif | |
| 1197 } | |
| 1198 | |
| 1199 if( do_polling() ) | |
| 1200 st->print("RET\n\t"); | |
| 1201 | |
| 1202 st->print("RESTORE"); | |
| 1203 } | |
| 1204 #endif | |
| 1205 | |
| 1206 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1207 MacroAssembler _masm(&cbuf); | |
| 1208 Compile* C = ra_->C; | |
| 1209 | |
| 1210 __ verify_thread(); | |
| 1211 | |
| 1212 // If this does safepoint polling, then do it here | |
| 1213 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1214 AddressLiteral polling_page(os::get_polling_page()); |
| 1215 __ sethi(polling_page, L0); | |
| 0 | 1216 __ relocate(relocInfo::poll_return_type); |
| 1217 __ ld_ptr( L0, 0, G0 ); | |
| 1218 } | |
| 1219 | |
| 1220 // If this is a return, then stuff the restore in the delay slot | |
| 1221 if( do_polling() ) { | |
| 1222 __ ret(); | |
| 1223 __ delayed()->restore(); | |
| 1224 } else { | |
| 1225 __ restore(); | |
| 1226 } | |
| 1227 } | |
| 1228 | |
| 1229 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1230 return MachNode::size(ra_); | |
| 1231 } | |
| 1232 | |
| 1233 int MachEpilogNode::reloc() const { | |
| 1234 return 16; // a large enough number | |
| 1235 } | |
| 1236 | |
| 1237 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1238 return MachNode::pipeline_class(); | |
| 1239 } | |
| 1240 | |
| 1241 int MachEpilogNode::safepoint_offset() const { | |
| 1242 assert( do_polling(), "no return for this epilog node"); | |
| 1243 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
| 1244 } | |
| 1245 | |
| 1246 //============================================================================= | |
| 1247 | |
| 1248 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1249 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1250 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1251 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1252 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1253 VMReg r = OptoReg::as_VMReg(reg); | |
| 1254 if (r->is_Register()) return rc_int; | |
| 1255 assert(r->is_FloatRegister(), "must be"); | |
| 1256 return rc_float; | |
| 1257 } | |
| 1258 | |
| 1259 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1260 if( cbuf ) { | |
| 1261 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1262 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1263 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1264 } else { | |
| 1265 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1266 } | |
| 1267 } | |
| 1268 #ifndef PRODUCT | |
| 1269 else if( !do_size ) { | |
| 1270 if( size != 0 ) st->print("\n\t"); | |
| 1271 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1272 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1273 } | |
| 1274 #endif | |
| 1275 return size+4; | |
| 1276 } | |
| 1277 | |
| 1278 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1279 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1280 #ifndef PRODUCT | |
| 1281 else if( !do_size ) { | |
| 1282 if( size != 0 ) st->print("\n\t"); | |
| 1283 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1284 } | |
| 1285 #endif | |
| 1286 return size+4; | |
| 1287 } | |
| 1288 | |
| 1289 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1290 PhaseRegAlloc *ra_, | |
| 1291 bool do_size, | |
| 1292 outputStream* st ) const { | |
| 1293 // Get registers to move | |
| 1294 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1295 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1296 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1297 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1298 | |
| 1299 enum RC src_second_rc = rc_class(src_second); | |
| 1300 enum RC src_first_rc = rc_class(src_first); | |
| 1301 enum RC dst_second_rc = rc_class(dst_second); | |
| 1302 enum RC dst_first_rc = rc_class(dst_first); | |
| 1303 | |
| 1304 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1305 | |
| 1306 // Generate spill code! | |
| 1307 int size = 0; | |
| 1308 | |
| 1309 if( src_first == dst_first && src_second == dst_second ) | |
| 1310 return size; // Self copy, no move | |
| 1311 | |
| 1312 // -------------------------------------- | |
| 1313 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1314 // the float-store case. | |
| 1315 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1316 int offset = ra_->reg2offset(src_first); | |
| 1317 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1318 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1319 src_second = OptoReg::Name(R_F31_num); | |
| 1320 src_second_rc = rc_float; | |
| 1321 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1322 } else { | |
| 1323 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1324 } | |
| 1325 src_first = OptoReg::Name(R_F30_num); | |
| 1326 src_first_rc = rc_float; | |
| 1327 } | |
| 1328 | |
| 1329 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1330 int offset = ra_->reg2offset(src_second); | |
| 1331 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1332 src_second = OptoReg::Name(R_F31_num); | |
| 1333 src_second_rc = rc_float; | |
| 1334 } | |
| 1335 | |
| 1336 // -------------------------------------- | |
| 1337 // Check for float->int copy; requires a trip through memory | |
| 1338 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
| 1339 int offset = frame::register_save_words*wordSize; | |
| 1340 if( cbuf ) { | |
| 1341 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
| 1342 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1343 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1344 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1345 } | |
| 1346 #ifndef PRODUCT | |
| 1347 else if( !do_size ) { | |
| 1348 if( size != 0 ) st->print("\n\t"); | |
| 1349 st->print( "SUB R_SP,16,R_SP\n"); | |
| 1350 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1351 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1352 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1353 } | |
| 1354 #endif | |
| 1355 size += 16; | |
| 1356 } | |
| 1357 | |
| 1358 // -------------------------------------- | |
| 1359 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1360 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1361 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1362 // there. Misaligned sources only come from native-long-returns (handled | |
| 1363 // special below). | |
| 1364 #ifndef _LP64 | |
| 1365 if( src_first_rc == rc_int && // source is already big-endian | |
| 1366 src_second_rc != rc_bad && // 64-bit move | |
| 1367 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1368 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1369 // Do the big-endian flop. | |
| 1370 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1371 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1372 } | |
| 1373 #endif | |
| 1374 | |
| 1375 // -------------------------------------- | |
| 1376 // Check for integer reg-reg copy | |
| 1377 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1378 #ifndef _LP64 | |
| 1379 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1380 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1381 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1382 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1383 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1384 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1385 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1386 if( cbuf ) { | |
| 1387 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1388 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1389 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1390 #ifndef PRODUCT | |
| 1391 } else if( !do_size ) { | |
| 1392 if( size != 0 ) st->print("\n\t"); | |
| 1393 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1394 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1395 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1396 #endif | |
| 1397 } | |
| 1398 return size+12; | |
| 1399 } | |
| 1400 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1401 // returning a long value in I0/I1 | |
| 1402 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1403 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1404 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1405 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1406 OptoReg::Name tdest = dst_first; | |
| 1407 | |
| 1408 if (src_first == dst_first) { | |
| 1409 tdest = OptoReg::Name(R_O7_num); | |
| 1410 size += 4; | |
| 1411 } | |
| 1412 | |
| 1413 if( cbuf ) { | |
| 1414 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1415 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1416 // ShrL_reg_imm6 | |
| 1417 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1418 // ShrR_reg_imm6 src, 0, dst | |
| 1419 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1420 if (tdest != dst_first) { | |
| 1421 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1422 } | |
| 1423 } | |
| 1424 #ifndef PRODUCT | |
| 1425 else if( !do_size ) { | |
| 1426 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1427 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1428 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1429 if (tdest != dst_first) { | |
| 1430 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1431 } | |
| 1432 } | |
| 1433 #endif // PRODUCT | |
| 1434 return size+8; | |
| 1435 } | |
| 1436 #endif // !_LP64 | |
| 1437 // Else normal reg-reg copy | |
| 1438 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1439 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1440 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1441 // This moves an aligned adjacent pair. | |
| 1442 // See if we are done. | |
| 1443 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1444 return size; | |
| 1445 } | |
| 1446 | |
| 1447 // Check for integer store | |
| 1448 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1449 int offset = ra_->reg2offset(dst_first); | |
| 1450 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1451 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1452 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1453 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1454 } | |
| 1455 | |
| 1456 // Check for integer load | |
| 1457 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1458 int offset = ra_->reg2offset(src_first); | |
| 1459 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1460 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1461 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1462 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1463 } | |
| 1464 | |
| 1465 // Check for float reg-reg copy | |
| 1466 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1467 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1468 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1469 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1470 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1471 } | |
| 1472 | |
| 1473 // Check for float store | |
| 1474 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1475 int offset = ra_->reg2offset(dst_first); | |
| 1476 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1477 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1478 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1479 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1480 } | |
| 1481 | |
| 1482 // Check for float load | |
| 1483 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1484 int offset = ra_->reg2offset(src_first); | |
| 1485 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1486 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1487 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1488 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1489 } | |
| 1490 | |
| 1491 // -------------------------------------------------------------------- | |
| 1492 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1493 // arguments to native calls. | |
| 1494 if( src_second == dst_second ) | |
| 1495 return size; // Self copy; no move | |
| 1496 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1497 | |
| 1498 #ifndef _LP64 | |
| 1499 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1500 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1501 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1502 // all sorts of silly alignment problems. | |
| 1503 | |
| 1504 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1505 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1506 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1507 // happened already as part of a 64-bit move) | |
| 1508 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1509 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1510 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1511 // Shift src_second down to dst_second's low bits. | |
| 1512 if( cbuf ) { | |
| 1513 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1514 #ifndef PRODUCT | |
| 1515 } else if( !do_size ) { | |
| 1516 if( size != 0 ) st->print("\n\t"); | |
| 1517 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1518 #endif | |
| 1519 } | |
| 1520 return size+4; | |
| 1521 } | |
| 1522 | |
| 1523 // Check for high word integer store. Must down-shift the hi bits | |
| 1524 // into a temp register, then fall into the case of storing int bits. | |
| 1525 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1526 // Shift src_second down to dst_second's low bits. | |
| 1527 if( cbuf ) { | |
| 1528 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1529 #ifndef PRODUCT | |
| 1530 } else if( !do_size ) { | |
| 1531 if( size != 0 ) st->print("\n\t"); | |
| 1532 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1533 #endif | |
| 1534 } | |
| 1535 size+=4; | |
| 1536 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1537 } | |
| 1538 | |
| 1539 // Check for high word integer load | |
| 1540 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1541 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1542 | |
| 1543 // Check for high word integer store | |
| 1544 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1545 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1546 | |
| 1547 // Check for high word float store | |
| 1548 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1549 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1550 | |
| 1551 #endif // !_LP64 | |
| 1552 | |
| 1553 Unimplemented(); | |
| 1554 } | |
| 1555 | |
| 1556 #ifndef PRODUCT | |
| 1557 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1558 implementation( NULL, ra_, false, st ); | |
| 1559 } | |
| 1560 #endif | |
| 1561 | |
| 1562 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1563 implementation( &cbuf, ra_, false, NULL ); | |
| 1564 } | |
| 1565 | |
| 1566 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1567 return implementation( NULL, ra_, true, NULL ); | |
| 1568 } | |
| 1569 | |
| 1570 //============================================================================= | |
| 1571 #ifndef PRODUCT | |
| 1572 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1573 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1574 } | |
| 1575 #endif | |
| 1576 | |
| 1577 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1578 MacroAssembler _masm(&cbuf); | |
| 1579 for(int i = 0; i < _count; i += 1) { | |
| 1580 __ nop(); | |
| 1581 } | |
| 1582 } | |
| 1583 | |
| 1584 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1585 return 4 * _count; | |
| 1586 } | |
| 1587 | |
| 1588 | |
| 1589 //============================================================================= | |
| 1590 #ifndef PRODUCT | |
| 1591 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1592 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1593 int reg = ra_->get_reg_first(this); | |
| 1594 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1595 } | |
| 1596 #endif | |
| 1597 | |
| 1598 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1599 MacroAssembler _masm(&cbuf); | |
| 1600 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1601 int reg = ra_->get_encode(this); | |
| 1602 | |
| 1603 if (Assembler::is_simm13(offset)) { | |
| 1604 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1605 } else { | |
| 1606 __ set(offset, O7); | |
| 1607 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1608 } | |
| 1609 } | |
| 1610 | |
| 1611 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1612 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1613 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1614 return ra_->C->scratch_emit_size(this); | |
| 1615 } | |
| 1616 | |
| 1617 //============================================================================= | |
| 1618 | |
| 1619 // emit call stub, compiled java to interpretor | |
| 1620 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1621 | |
| 1622 // Stub is fixed up when the corresponding call is converted from calling | |
| 1623 // compiled code to calling interpreted code. | |
| 1624 // set (empty), G5 | |
| 1625 // jmp -1 | |
| 1626 | |
| 1748 | 1627 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 0 | 1628 |
| 1629 MacroAssembler _masm(&cbuf); | |
| 1630 | |
| 1631 address base = | |
| 1632 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1633 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1634 | |
| 1635 // static stub relocation stores the instruction address of the call | |
| 1636 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1637 | |
| 1638 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1639 | |
| 1640 __ set_inst_mark(); | |
| 727 | 1641 AddressLiteral addrlit(-1); |
| 1642 __ JUMP(addrlit, G3, 0); | |
| 0 | 1643 |
| 1644 __ delayed()->nop(); | |
| 1645 | |
| 1646 // Update current stubs pointer and restore code_end. | |
| 1647 __ end_a_stub(); | |
| 1648 } | |
| 1649 | |
| 1650 // size of call stub, compiled java to interpretor | |
| 1651 uint size_java_to_interp() { | |
| 1652 // This doesn't need to be accurate but it must be larger or equal to | |
| 1653 // the real size of the stub. | |
| 1654 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1655 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1656 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1657 } | |
| 1658 // relocation entries for call stub, compiled java to interpretor | |
| 1659 uint reloc_java_to_interp() { | |
| 1660 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1661 } | |
| 1662 | |
| 1663 | |
| 1664 //============================================================================= | |
| 1665 #ifndef PRODUCT | |
| 1666 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1667 st->print_cr("\nUEP:"); | |
| 1668 #ifdef _LP64 | |
|
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1669 if (UseCompressedOops) { |
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1670 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1671 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1672 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1673 if (Universe::narrow_oop_base() != NULL) |
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1674 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1675 } else { |
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1676 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1677 } |
| 0 | 1678 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1679 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1680 #else // _LP64 | |
| 1681 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1682 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1683 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1684 #endif // _LP64 | |
| 1685 } | |
| 1686 #endif | |
| 1687 | |
| 1688 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1689 MacroAssembler _masm(&cbuf); | |
| 1690 Label L; | |
| 1691 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1692 Register temp_reg = G3; | |
| 1693 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1694 | |
| 605 | 1695 // Load klass from receiver |
|
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1696 __ load_klass(O0, temp_reg); |
| 0 | 1697 // Compare against expected klass |
| 1698 __ cmp(temp_reg, G5_ic_reg); | |
| 1699 // Branch to miss code, checks xcc or icc depending | |
| 1700 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1701 } | |
| 1702 | |
| 1703 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1704 return MachNode::size(ra_); | |
| 1705 } | |
| 1706 | |
| 1707 | |
| 1708 //============================================================================= | |
| 1709 | |
| 1710 uint size_exception_handler() { | |
| 1711 if (TraceJumps) { | |
| 1712 return (400); // just a guess | |
| 1713 } | |
| 1714 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1715 } | |
| 1716 | |
| 1717 uint size_deopt_handler() { | |
| 1718 if (TraceJumps) { | |
| 1719 return (400); // just a guess | |
| 1720 } | |
| 1721 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1722 } | |
| 1723 | |
| 1724 // Emit exception handler code. | |
| 1725 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1726 Register temp_reg = G3; | |
| 1748 | 1727 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1728 MacroAssembler _masm(&cbuf); |
| 1729 | |
| 1730 address base = | |
| 1731 __ start_a_stub(size_exception_handler()); | |
| 1732 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1733 | |
| 1734 int offset = __ offset(); | |
| 1735 | |
| 727 | 1736 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1737 __ delayed()->nop(); |
| 1738 | |
| 1739 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1740 | |
| 1741 __ end_a_stub(); | |
| 1742 | |
| 1743 return offset; | |
| 1744 } | |
| 1745 | |
| 1746 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1747 // Can't use any of the current frame's registers as we may have deopted | |
| 1748 // at a poll and everything (including G3) can be live. | |
| 1749 Register temp_reg = L0; | |
| 727 | 1750 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1751 MacroAssembler _masm(&cbuf); |
| 1752 | |
| 1753 address base = | |
| 1754 __ start_a_stub(size_deopt_handler()); | |
| 1755 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1756 | |
| 1757 int offset = __ offset(); | |
| 1758 __ save_frame(0); | |
| 727 | 1759 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1760 __ delayed()->restore(); |
| 1761 | |
| 1762 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1763 | |
| 1764 __ end_a_stub(); | |
| 1765 return offset; | |
| 1766 | |
| 1767 } | |
| 1768 | |
| 1769 // Given a register encoding, produce a Integer Register object | |
| 1770 static Register reg_to_register_object(int register_encoding) { | |
| 1771 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1772 return as_Register(register_encoding); | |
| 1773 } | |
| 1774 | |
| 1775 // Given a register encoding, produce a single-precision Float Register object | |
| 1776 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1777 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1778 return as_SingleFloatRegister(register_encoding); | |
| 1779 } | |
| 1780 | |
| 1781 // Given a register encoding, produce a double-precision Float Register object | |
| 1782 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1783 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1784 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1785 return as_DoubleFloatRegister(register_encoding); | |
| 1786 } | |
| 1787 | |
|
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1788 const bool Matcher::match_rule_supported(int opcode) { |
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1789 if (!has_match_rule(opcode)) |
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1790 return false; |
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1791 |
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1792 switch (opcode) { |
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1793 case Op_CountLeadingZerosI: |
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1794 case Op_CountLeadingZerosL: |
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1795 case Op_CountTrailingZerosI: |
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1796 case Op_CountTrailingZerosL: |
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1797 if (!UsePopCountInstruction) |
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1798 return false; |
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1799 break; |
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1800 } |
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1801 |
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1802 return true; // Per default match rules are supported. |
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1803 } |
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1804 |
| 0 | 1805 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1806 return regnum - 32; // The FP registers are in the second chunk | |
| 1807 } | |
| 1808 | |
| 1809 #ifdef ASSERT | |
| 1810 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1811 #endif | |
| 1812 | |
| 1813 // Vector width in bytes | |
| 1814 const uint Matcher::vector_width_in_bytes(void) { | |
| 1815 return 8; | |
| 1816 } | |
| 1817 | |
| 1818 // Vector ideal reg | |
| 1819 const uint Matcher::vector_ideal_reg(void) { | |
| 1820 return Op_RegD; | |
| 1821 } | |
| 1822 | |
| 1823 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1824 const bool Matcher::convL2FSupported(void) { | |
| 1825 return VM_Version::has_fast_fxtof(); | |
| 1826 } | |
| 1827 | |
| 1828 // Is this branch offset short enough that a short branch can be used? | |
| 1829 // | |
| 1830 // NOTE: If the platform does not provide any short branch variants, then | |
| 1831 // this method should return false for offset 0. | |
|
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1832 bool Matcher::is_short_branch_offset(int rule, int offset) { |
| 0 | 1833 return false; |
| 1834 } | |
| 1835 | |
| 1836 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1837 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1838 // Depends on optimizations in MacroAssembler::setx. | |
| 1839 int hi = (int)(value >> 32); | |
| 1840 int lo = (int)(value & ~0); | |
| 1841 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1842 } | |
| 1843 | |
| 1844 // No scaling for the parameter the ClearArray node. | |
| 1845 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1846 | |
| 1847 // Threshold size for cleararray. | |
| 1848 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1849 | |
| 1850 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1851 // be subsumed into complex addressing expressions or compute them into | |
| 1852 // registers? True for Intel but false for most RISCs | |
| 1853 const bool Matcher::clone_shift_expressions = false; | |
| 1854 | |
|
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1855 bool Matcher::narrow_oop_use_complex_address() { |
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1856 NOT_LP64(ShouldNotCallThis()); |
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1857 assert(UseCompressedOops, "only for compressed oops code"); |
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1858 return false; |
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1859 } |
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1860 |
| 0 | 1861 // Is it better to copy float constants, or load them directly from memory? |
| 1862 // Intel can load a float constant from a direct address, requiring no | |
| 1863 // extra registers. Most RISCs will have to materialize an address into a | |
| 1864 // register first, so they would do better to copy the constant from stack. | |
| 1865 const bool Matcher::rematerialize_float_constants = false; | |
| 1866 | |
| 1867 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1868 // needed. Else we split the double into 2 integer pieces and move it | |
| 1869 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1870 // Java calling convention forces doubles to be aligned. | |
| 1871 #ifdef _LP64 | |
| 1872 const bool Matcher::misaligned_doubles_ok = true; | |
| 1873 #else | |
| 1874 const bool Matcher::misaligned_doubles_ok = false; | |
| 1875 #endif | |
| 1876 | |
| 1877 // No-op on SPARC. | |
| 1878 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1879 } | |
| 1880 | |
| 1881 // Advertise here if the CPU requires explicit rounding operations | |
| 1882 // to implement the UseStrictFP mode. | |
| 1883 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1884 | |
|
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1885 // Are floats conerted to double when stored to stack during deoptimization? |
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1886 // Sparc does not handle callee-save floats. |
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1887 bool Matcher::float_in_double() { return false; } |
| 0 | 1888 |
| 1889 // Do ints take an entire long register or just half? | |
| 1890 // Note that we if-def off of _LP64. | |
| 1891 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1892 // the whole long is written but de-opt'ing will have to extract | |
| 1893 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1894 #ifdef _LP64 | |
| 1895 const bool Matcher::int_in_long = true; | |
| 1896 #else | |
| 1897 const bool Matcher::int_in_long = false; | |
| 1898 #endif | |
| 1899 | |
| 1900 // Return whether or not this register is ever used as an argument. This | |
| 1901 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1902 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1903 // arguments in those registers not be available to the callee. | |
| 1904 bool Matcher::can_be_java_arg( int reg ) { | |
| 1905 // Standard sparc 6 args in registers | |
| 1906 if( reg == R_I0_num || | |
| 1907 reg == R_I1_num || | |
| 1908 reg == R_I2_num || | |
| 1909 reg == R_I3_num || | |
| 1910 reg == R_I4_num || | |
| 1911 reg == R_I5_num ) return true; | |
| 1912 #ifdef _LP64 | |
| 1913 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1914 // the high I registers | |
| 1915 if( reg == R_I0H_num || | |
| 1916 reg == R_I1H_num || | |
| 1917 reg == R_I2H_num || | |
| 1918 reg == R_I3H_num || | |
| 1919 reg == R_I4H_num || | |
| 1920 reg == R_I5H_num ) return true; | |
|
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1921 |
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1922 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1923 return true; |
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1924 } |
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1925 |
| 0 | 1926 #else |
| 1927 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1928 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1929 // after a 'save' and I regs get their high bits chopped off on | |
| 1930 // interrupt. | |
| 1931 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1932 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1933 #endif | |
| 1934 // A few float args in registers | |
| 1935 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1936 | |
| 1937 return false; | |
| 1938 } | |
| 1939 | |
| 1940 bool Matcher::is_spillable_arg( int reg ) { | |
| 1941 return can_be_java_arg(reg); | |
| 1942 } | |
| 1943 | |
|
1914
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1944 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1945 // Use hardware SDIVX instruction when it is |
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1946 // faster than a code which use multiply. |
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1947 return VM_Version::has_fast_idiv(); |
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1948 } |
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1949 |
| 0 | 1950 // Register for DIVI projection of divmodI |
| 1951 RegMask Matcher::divI_proj_mask() { | |
| 1952 ShouldNotReachHere(); | |
| 1953 return RegMask(); | |
| 1954 } | |
| 1955 | |
| 1956 // Register for MODI projection of divmodI | |
| 1957 RegMask Matcher::modI_proj_mask() { | |
| 1958 ShouldNotReachHere(); | |
| 1959 return RegMask(); | |
| 1960 } | |
| 1961 | |
| 1962 // Register for DIVL projection of divmodL | |
| 1963 RegMask Matcher::divL_proj_mask() { | |
| 1964 ShouldNotReachHere(); | |
| 1965 return RegMask(); | |
| 1966 } | |
| 1967 | |
| 1968 // Register for MODL projection of divmodL | |
| 1969 RegMask Matcher::modL_proj_mask() { | |
| 1970 ShouldNotReachHere(); | |
| 1971 return RegMask(); | |
| 1972 } | |
| 1973 | |
|
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1974 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
| 1567 | 1975 return L7_REGP_mask; |
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1976 } |
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1977 |
| 0 | 1978 %} |
| 1979 | |
| 1980 | |
| 1981 // The intptr_t operand types, defined by textual substitution. | |
| 1982 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1983 #ifdef _LP64 | |
| 824 | 1984 #define immX immL |
| 1985 #define immX13 immL13 | |
| 1986 #define immX13m7 immL13m7 | |
| 1987 #define iRegX iRegL | |
| 1988 #define g1RegX g1RegL | |
| 0 | 1989 #else |
| 824 | 1990 #define immX immI |
| 1991 #define immX13 immI13 | |
| 1992 #define immX13m7 immI13m7 | |
| 1993 #define iRegX iRegI | |
| 1994 #define g1RegX g1RegI | |
| 0 | 1995 #endif |
| 1996 | |
| 1997 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1998 // This block specifies the encoding classes used by the compiler to output | |
| 1999 // byte streams. Encoding classes are parameterized macros used by | |
| 2000 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2001 // instruction. Operands specify their base encoding interface with the | |
| 2002 // interface keyword. There are currently supported four interfaces, | |
| 2003 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2004 // operand to generate a function which returns its register number when | |
| 2005 // queried. CONST_INTER causes an operand to generate a function which | |
| 2006 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2007 // operand to generate four functions which return the Base Register, the | |
| 2008 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2009 // queried. COND_INTER causes an operand to generate six functions which | |
| 2010 // return the encoding code (ie - encoding bits for the instruction) | |
| 2011 // associated with each basic boolean condition for a conditional instruction. | |
| 2012 // | |
| 2013 // Instructions specify two basic values for encoding. Again, a function | |
| 2014 // is available to check if the constant displacement is an oop. They use the | |
| 2015 // ins_encode keyword to specify their encoding classes (which must be | |
| 2016 // a sequence of enc_class names, and their parameters, specified in | |
| 2017 // the encoding block), and they use the | |
| 2018 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2019 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2020 // needs for encoding need to be specified. | |
| 2021 encode %{ | |
| 2022 enc_class enc_untested %{ | |
| 2023 #ifdef ASSERT | |
| 2024 MacroAssembler _masm(&cbuf); | |
| 2025 __ untested("encoding"); | |
| 2026 #endif | |
| 2027 %} | |
| 2028 | |
| 2029 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 2030 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 2031 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 2032 %} | |
| 2033 | |
|
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2034 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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2035 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2036 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2037 %} |
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2038 |
| 0 | 2039 enc_class form3_mem_prefetch_read( memory mem ) %{ |
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2040 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2041 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2042 %} | |
| 2043 | |
| 2044 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
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2045 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2046 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2047 %} | |
| 2048 | |
| 2049 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 2050 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2051 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2052 guarantee($mem$$index == R_G0_enc, "double index?"); | |
|
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2053 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2054 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2055 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2056 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2057 %} | |
| 2058 | |
| 2059 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 2060 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2061 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2062 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 2063 // Load long with 2 instructions | |
|
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2064 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
|
4d9884b01ba6
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|
2065 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2066 %} |
| 2067 | |
| 2068 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2069 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2070 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
415
4d9884b01ba6
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parents:
235
diff
changeset
|
2071 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2072 %} |
| 2073 | |
| 2074 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2075 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2076 if( $rs2$$reg != $rd$$reg ) | |
| 2077 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2078 %} | |
| 2079 | |
| 2080 // Target lo half of long | |
| 2081 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2082 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2083 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2084 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2085 %} | |
| 2086 | |
| 2087 // Source lo half of long | |
| 2088 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2089 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2090 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2091 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2092 %} | |
| 2093 | |
| 2094 // Target hi half of long | |
| 2095 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2096 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2097 %} | |
| 2098 | |
| 2099 // Source lo half of long, and leave it sign extended. | |
| 2100 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2101 // Sign extend low half | |
| 2102 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2103 %} | |
| 2104 | |
| 2105 // Source hi half of long, and leave it sign extended. | |
| 2106 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2107 // Shift high half to low half | |
| 2108 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2109 %} | |
| 2110 | |
| 2111 // Source hi half of long | |
| 2112 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2113 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2114 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2115 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2116 %} | |
| 2117 | |
| 2118 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2119 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2120 %} | |
| 2121 | |
| 2122 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2123 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2124 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2125 %} | |
| 2126 | |
| 2127 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2128 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2129 // clear if nothing else is happening | |
| 2130 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2131 // blt,a,pn done | |
| 2132 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2133 // mov dst,-1 in delay slot | |
| 2134 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2135 %} | |
| 2136 | |
| 2137 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2138 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2139 %} | |
| 2140 | |
| 2141 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2142 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2143 %} | |
| 2144 | |
| 2145 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2146 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2147 %} | |
| 2148 | |
| 2149 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2150 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2151 %} | |
| 2152 | |
| 2153 enc_class move_return_pc_to_o1() %{ | |
| 2154 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2155 %} | |
| 2156 | |
| 2157 #ifdef _LP64 | |
| 2158 /* %%% merge with enc_to_bool */ | |
| 2159 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2160 MacroAssembler _masm(&cbuf); | |
| 2161 | |
| 2162 Register src_reg = reg_to_register_object($src$$reg); | |
| 2163 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2164 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2165 %} | |
| 2166 #endif | |
| 2167 | |
| 2168 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2169 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2170 MacroAssembler _masm(&cbuf); | |
| 2171 | |
| 2172 Register p_reg = reg_to_register_object($p$$reg); | |
| 2173 Register q_reg = reg_to_register_object($q$$reg); | |
| 2174 Register y_reg = reg_to_register_object($y$$reg); | |
| 2175 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2176 | |
| 2177 __ subcc( p_reg, q_reg, p_reg ); | |
| 2178 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2179 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2180 %} | |
| 2181 | |
| 2182 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2183 // fcmp %fcc0,$src,$src | |
| 2184 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2185 // branch %fcc0 not-nan, predict taken | |
| 2186 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2187 // fdtoi $src,$dst | |
| 2188 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2189 // fitos $dst,$dst (if nan) | |
| 2190 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2191 // clear $dst (if nan) | |
| 2192 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2193 // carry on here... | |
| 2194 %} | |
| 2195 | |
| 2196 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2197 // fcmp %fcc0,$src,$src check for NAN | |
| 2198 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2199 // branch %fcc0 not-nan, predict taken | |
| 2200 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2201 // fdtox $src,$dst convert in delay slot | |
| 2202 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2203 // fxtod $dst,$dst (if nan) | |
| 2204 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2205 // clear $dst (if nan) | |
| 2206 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2207 // carry on here... | |
| 2208 %} | |
| 2209 | |
| 2210 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2211 // fcmps %fcc0,$src,$src | |
| 2212 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2213 // branch %fcc0 not-nan, predict taken | |
| 2214 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2215 // fstoi $src,$dst | |
| 2216 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2217 // fitos $dst,$dst (if nan) | |
| 2218 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2219 // clear $dst (if nan) | |
| 2220 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2221 // carry on here... | |
| 2222 %} | |
| 2223 | |
| 2224 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2225 // fcmps %fcc0,$src,$src | |
| 2226 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2227 // branch %fcc0 not-nan, predict taken | |
| 2228 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2229 // fstox $src,$dst | |
| 2230 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2231 // fxtod $dst,$dst (if nan) | |
| 2232 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2233 // clear $dst (if nan) | |
| 2234 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2235 // carry on here... | |
| 2236 %} | |
| 2237 | |
| 2238 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2239 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2240 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2241 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2242 | |
| 2243 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2244 | |
| 2245 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2246 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2247 | |
| 2248 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2249 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2250 %} | |
| 2251 | |
| 2252 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2253 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2254 %} | |
| 2255 | |
| 2256 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2257 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2258 %} | |
| 2259 | |
| 2260 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2261 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2262 %} | |
| 2263 | |
| 2264 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2265 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2266 %} | |
| 2267 | |
| 2268 // Encloding class for traceable jumps | |
| 2269 enc_class form_jmpl(g3RegP dest) %{ | |
| 2270 emit_jmpl(cbuf, $dest$$reg); | |
| 2271 %} | |
| 2272 | |
| 2273 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2274 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2275 %} | |
| 2276 | |
| 2277 enc_class form2_nop() %{ | |
| 2278 emit_nop(cbuf); | |
| 2279 %} | |
| 2280 | |
| 2281 enc_class form2_illtrap() %{ | |
| 2282 emit_illtrap(cbuf); | |
| 2283 %} | |
| 2284 | |
| 2285 | |
| 2286 // Compare longs and convert into -1, 0, 1. | |
| 2287 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2288 // CMP $src1,$src2 | |
| 2289 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2290 // blt,a,pn done | |
| 2291 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2292 // mov dst,-1 in delay slot | |
| 2293 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2294 // bgt,a,pn done | |
| 2295 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2296 // mov dst,1 in delay slot | |
| 2297 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2298 // CLR $dst | |
| 2299 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2300 %} | |
| 2301 | |
| 2302 enc_class enc_PartialSubtypeCheck() %{ | |
| 2303 MacroAssembler _masm(&cbuf); | |
| 2304 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2305 __ delayed()->nop(); | |
| 2306 %} | |
| 2307 | |
| 2308 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
| 2309 MacroAssembler _masm(&cbuf); | |
| 2310 Label &L = *($labl$$label); | |
| 2311 Assembler::Predict predict_taken = | |
| 2312 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2313 | |
| 2314 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
| 2315 __ delayed()->nop(); | |
| 2316 %} | |
| 2317 | |
| 2318 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
| 2319 MacroAssembler _masm(&cbuf); | |
| 2320 Label &L = *($labl$$label); | |
| 2321 Assembler::Predict predict_taken = | |
| 2322 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2323 | |
| 2324 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
| 2325 __ delayed()->nop(); | |
| 2326 %} | |
| 2327 | |
| 2328 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
| 2329 MacroAssembler _masm(&cbuf); | |
| 2330 Label &L = *($labl$$label); | |
| 2331 Assembler::Predict predict_taken = | |
| 2332 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2333 | |
| 2334 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
| 2335 __ delayed()->nop(); | |
| 2336 %} | |
| 2337 | |
| 2338 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
| 2339 MacroAssembler _masm(&cbuf); | |
| 2340 Label &L = *($labl$$label); | |
| 2341 Assembler::Predict predict_taken = | |
| 2342 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2343 | |
| 2344 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
| 2345 __ delayed()->nop(); | |
| 2346 %} | |
| 2347 | |
| 2348 enc_class enc_ba( Label labl ) %{ | |
| 2349 MacroAssembler _masm(&cbuf); | |
| 2350 Label &L = *($labl$$label); | |
| 2351 __ ba(false, L); | |
| 2352 __ delayed()->nop(); | |
| 2353 %} | |
| 2354 | |
| 2355 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
| 2356 MacroAssembler _masm(&cbuf); | |
| 2357 Label &L = *$labl$$label; | |
| 2358 Assembler::Predict predict_taken = | |
| 2359 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2360 | |
| 2361 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
| 2362 __ delayed()->nop(); | |
| 2363 %} | |
| 2364 | |
| 2365 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2366 int op = (Assembler::arith_op << 30) | | |
| 2367 ($dst$$reg << 25) | | |
| 2368 (Assembler::movcc_op3 << 19) | | |
| 2369 (1 << 18) | // cc2 bit for 'icc' | |
| 2370 ($cmp$$cmpcode << 14) | | |
| 2371 (0 << 13) | // select register move | |
| 2372 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2373 ($src$$reg << 0); | |
| 1748 | 2374 cbuf.insts()->emit_int32(op); |
| 0 | 2375 %} |
| 2376 | |
| 2377 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2378 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2379 int op = (Assembler::arith_op << 30) | | |
| 2380 ($dst$$reg << 25) | | |
| 2381 (Assembler::movcc_op3 << 19) | | |
| 2382 (1 << 18) | // cc2 bit for 'icc' | |
| 2383 ($cmp$$cmpcode << 14) | | |
| 2384 (1 << 13) | // select immediate move | |
| 2385 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2386 (simm11 << 0); | |
| 1748 | 2387 cbuf.insts()->emit_int32(op); |
| 0 | 2388 %} |
| 2389 | |
| 2390 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2391 int op = (Assembler::arith_op << 30) | | |
| 2392 ($dst$$reg << 25) | | |
| 2393 (Assembler::movcc_op3 << 19) | | |
| 2394 (0 << 18) | // cc2 bit for 'fccX' | |
| 2395 ($cmp$$cmpcode << 14) | | |
| 2396 (0 << 13) | // select register move | |
| 2397 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2398 ($src$$reg << 0); | |
| 1748 | 2399 cbuf.insts()->emit_int32(op); |
| 0 | 2400 %} |
| 2401 | |
| 2402 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2403 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2404 int op = (Assembler::arith_op << 30) | | |
| 2405 ($dst$$reg << 25) | | |
| 2406 (Assembler::movcc_op3 << 19) | | |
| 2407 (0 << 18) | // cc2 bit for 'fccX' | |
| 2408 ($cmp$$cmpcode << 14) | | |
| 2409 (1 << 13) | // select immediate move | |
| 2410 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2411 (simm11 << 0); | |
| 1748 | 2412 cbuf.insts()->emit_int32(op); |
| 0 | 2413 %} |
| 2414 | |
| 2415 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2416 int op = (Assembler::arith_op << 30) | | |
| 2417 ($dst$$reg << 25) | | |
| 2418 (Assembler::fpop2_op3 << 19) | | |
| 2419 (0 << 18) | | |
| 2420 ($cmp$$cmpcode << 14) | | |
| 2421 (1 << 13) | // select register move | |
| 2422 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2423 ($primary << 5) | // select single, double or quad | |
| 2424 ($src$$reg << 0); | |
| 1748 | 2425 cbuf.insts()->emit_int32(op); |
| 0 | 2426 %} |
| 2427 | |
| 2428 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2429 int op = (Assembler::arith_op << 30) | | |
| 2430 ($dst$$reg << 25) | | |
| 2431 (Assembler::fpop2_op3 << 19) | | |
| 2432 (0 << 18) | | |
| 2433 ($cmp$$cmpcode << 14) | | |
| 2434 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2435 ($primary << 5) | // select single, double or quad | |
| 2436 ($src$$reg << 0); | |
| 1748 | 2437 cbuf.insts()->emit_int32(op); |
| 0 | 2438 %} |
| 2439 | |
| 2440 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2441 // the condition comes from opcode-field instead of an argument. | |
| 2442 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2443 int op = (Assembler::arith_op << 30) | | |
| 2444 ($dst$$reg << 25) | | |
| 2445 (Assembler::movcc_op3 << 19) | | |
| 2446 (1 << 18) | // cc2 bit for 'icc' | |
| 2447 ($primary << 14) | | |
| 2448 (0 << 13) | // select register move | |
| 2449 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2450 ($src$$reg << 0); | |
| 1748 | 2451 cbuf.insts()->emit_int32(op); |
| 0 | 2452 %} |
| 2453 | |
| 2454 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2455 int op = (Assembler::arith_op << 30) | | |
| 2456 ($dst$$reg << 25) | | |
| 2457 (Assembler::movcc_op3 << 19) | | |
| 2458 (6 << 16) | // cc2 bit for 'xcc' | |
| 2459 ($primary << 14) | | |
| 2460 (0 << 13) | // select register move | |
| 2461 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2462 ($src$$reg << 0); | |
| 1748 | 2463 cbuf.insts()->emit_int32(op); |
| 0 | 2464 %} |
| 2465 | |
| 2466 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2467 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2468 %} | |
| 2469 | |
| 2470 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2471 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2472 %} | |
| 2473 | |
| 2474 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2475 MacroAssembler _masm(&cbuf); | |
| 2476 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2477 %} | |
| 2478 | |
| 2479 enc_class call_epilog %{ | |
| 2480 if( VerifyStackAtCalls ) { | |
| 2481 MacroAssembler _masm(&cbuf); | |
| 2482 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2483 Register temp_reg = G3; | |
| 2484 __ add(SP, framesize, temp_reg); | |
| 2485 __ cmp(temp_reg, FP); | |
| 2486 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2487 } | |
| 2488 %} | |
| 2489 | |
| 2490 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2491 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2492 // pair. | |
| 2493 enc_class adjust_long_from_native_call %{ | |
| 2494 #ifndef _LP64 | |
| 2495 if (returns_long()) { | |
| 2496 // sllx O0,32,O0 | |
| 2497 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2498 // srl O1,0,O1 | |
| 2499 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2500 // or O0,O1,G1 | |
| 2501 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2502 } | |
| 2503 #endif | |
| 2504 %} | |
| 2505 | |
| 2506 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2507 // CALL directly to the runtime | |
| 2508 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2509 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
| 2510 /*preserve_g2=*/true, /*force far call*/true); | |
| 2511 %} | |
| 2512 | |
| 1567 | 2513 enc_class preserve_SP %{ |
| 2514 MacroAssembler _masm(&cbuf); | |
| 2515 __ mov(SP, L7_mh_SP_save); | |
| 2516 %} | |
| 2517 | |
| 2518 enc_class restore_SP %{ | |
| 2519 MacroAssembler _masm(&cbuf); | |
| 2520 __ mov(L7_mh_SP_save, SP); | |
| 2521 %} | |
| 2522 | |
| 0 | 2523 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2524 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2525 // who we intended to call. | |
| 2526 if ( !_method ) { | |
| 2527 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2528 } else if (_optimized_virtual) { | |
| 2529 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2530 } else { | |
| 2531 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2532 } | |
| 2533 if( _method ) { // Emit stub for static call | |
| 2534 emit_java_to_interp(cbuf); | |
| 2535 } | |
| 2536 %} | |
| 2537 | |
| 2538 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2539 MacroAssembler _masm(&cbuf); | |
| 2540 __ set_inst_mark(); | |
| 2541 int vtable_index = this->_vtable_index; | |
| 2542 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2543 if (vtable_index < 0) { | |
| 2544 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2545 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2546 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2547 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2548 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2549 // !!!!! | |
| 2550 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2551 // emit_call_dynamic_prologue( cbuf ); | |
| 2552 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2553 | |
| 2554 address virtual_call_oop_addr = __ inst_mark(); | |
| 2555 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2556 // who we intended to call. | |
| 2557 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2558 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2559 } else { | |
| 2560 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2561 // Just go thru the vtable | |
| 2562 // get receiver klass (receiver already checked for non-null) | |
| 2563 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2564 int off = __ offset(); | |
|
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2565 __ load_klass(O0, G3_scratch); |
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2566 int klass_load_size; |
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2567 if (UseCompressedOops) { |
|
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2568 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2569 if (Universe::narrow_oop_base() == NULL) |
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2570 klass_load_size = 2*BytesPerInstWord; |
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2571 else |
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2572 klass_load_size = 3*BytesPerInstWord; |
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2573 } else { |
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2574 klass_load_size = 1*BytesPerInstWord; |
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2575 } |
| 0 | 2576 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2577 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2578 if( __ is_simm13(v_off) ) { | |
| 2579 __ ld_ptr(G3, v_off, G5_method); | |
| 2580 } else { | |
| 2581 // Generate 2 instructions | |
| 2582 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2583 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2584 // ld_ptr, set_hi, set | |
|
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2585 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2586 "Unexpected instruction size(s)"); |
| 0 | 2587 __ ld_ptr(G3, G5_method, G5_method); |
| 2588 } | |
| 2589 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2590 // However it may very well end up in handle_wrong_method if the | |
| 2591 // method is abstract for the particular class. | |
| 2592 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2593 // jump to target (either compiled code or c2iadapter) | |
| 2594 __ jmpl(G3_scratch, G0, O7); | |
| 2595 __ delayed()->nop(); | |
| 2596 } | |
| 2597 %} | |
| 2598 | |
| 2599 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2600 MacroAssembler _masm(&cbuf); | |
| 2601 | |
| 2602 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2603 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2604 // we might be calling a C2I adapter which needs it. | |
| 2605 | |
| 2606 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2607 // Load nmethod | |
| 2608 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2609 | |
| 2610 // CALL to compiled java, indirect the contents of G3 | |
| 2611 __ set_inst_mark(); | |
| 2612 __ callr(temp_reg, G0); | |
| 2613 __ delayed()->nop(); | |
| 2614 %} | |
| 2615 | |
| 2616 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2617 MacroAssembler _masm(&cbuf); | |
| 2618 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2619 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2620 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2621 | |
| 2622 __ sra(Rdivisor, 0, Rdivisor); | |
| 2623 __ sra(Rdividend, 0, Rdividend); | |
| 2624 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2625 %} | |
| 2626 | |
| 2627 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2628 MacroAssembler _masm(&cbuf); | |
| 2629 | |
| 2630 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2631 int divisor = $imm$$constant; | |
| 2632 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2633 | |
| 2634 __ sra(Rdividend, 0, Rdividend); | |
| 2635 __ sdivx(Rdividend, divisor, Rresult); | |
| 2636 %} | |
| 2637 | |
| 2638 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2639 MacroAssembler _masm(&cbuf); | |
| 2640 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2641 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2642 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2643 | |
| 2644 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2645 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2646 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2647 __ srlx( Rdst, 32, Rdst ); | |
| 2648 %} | |
| 2649 | |
| 2650 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2651 MacroAssembler _masm(&cbuf); | |
| 2652 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2653 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2654 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2655 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2656 | |
| 2657 assert(Rdividend != Rscratch, ""); | |
| 2658 assert(Rdivisor != Rscratch, ""); | |
| 2659 | |
| 2660 __ sra(Rdividend, 0, Rdividend); | |
| 2661 __ sra(Rdivisor, 0, Rdivisor); | |
| 2662 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2663 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2664 __ sub(Rdividend, Rscratch, Rresult); | |
| 2665 %} | |
| 2666 | |
| 2667 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2668 MacroAssembler _masm(&cbuf); | |
| 2669 | |
| 2670 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2671 int divisor = $imm$$constant; | |
| 2672 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2673 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2674 | |
| 2675 assert(Rdividend != Rscratch, ""); | |
| 2676 | |
| 2677 __ sra(Rdividend, 0, Rdividend); | |
| 2678 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2679 __ mulx(Rscratch, divisor, Rscratch); | |
| 2680 __ sub(Rdividend, Rscratch, Rresult); | |
| 2681 %} | |
| 2682 | |
| 2683 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2684 MacroAssembler _masm(&cbuf); | |
| 2685 | |
| 2686 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2687 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2688 | |
| 2689 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2690 %} | |
| 2691 | |
| 2692 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2693 MacroAssembler _masm(&cbuf); | |
| 2694 | |
| 2695 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2696 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2697 | |
| 2698 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2699 %} | |
| 2700 | |
| 2701 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2702 MacroAssembler _masm(&cbuf); | |
| 2703 | |
| 2704 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2705 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2706 | |
| 2707 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2708 %} | |
| 2709 | |
| 2710 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2711 MacroAssembler _masm(&cbuf); | |
| 2712 | |
| 2713 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2714 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2715 | |
| 2716 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2717 %} | |
| 2718 | |
| 2719 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2720 MacroAssembler _masm(&cbuf); | |
| 2721 | |
| 2722 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2723 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2724 | |
| 2725 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2726 %} | |
| 2727 | |
| 2728 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2729 MacroAssembler _masm(&cbuf); | |
| 2730 | |
| 2731 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2732 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2733 | |
| 2734 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2735 %} | |
| 2736 | |
| 2737 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2738 MacroAssembler _masm(&cbuf); | |
| 2739 | |
| 2740 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2741 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2742 | |
| 2743 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2744 %} | |
| 2745 | |
| 2746 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2747 MacroAssembler _masm(&cbuf); | |
| 2748 | |
| 2749 Register Roop = reg_to_register_object($oop$$reg); | |
| 2750 Register Rbox = reg_to_register_object($box$$reg); | |
| 2751 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2752 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2753 | |
| 2754 assert(Roop != Rscratch, ""); | |
| 2755 assert(Roop != Rmark, ""); | |
| 2756 assert(Rbox != Rscratch, ""); | |
| 2757 assert(Rbox != Rmark, ""); | |
| 2758 | |
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2759 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2760 %} |
| 2761 | |
| 2762 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2763 MacroAssembler _masm(&cbuf); | |
| 2764 | |
| 2765 Register Roop = reg_to_register_object($oop$$reg); | |
| 2766 Register Rbox = reg_to_register_object($box$$reg); | |
| 2767 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2768 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2769 | |
| 2770 assert(Roop != Rscratch, ""); | |
| 2771 assert(Roop != Rmark, ""); | |
| 2772 assert(Rbox != Rscratch, ""); | |
| 2773 assert(Rbox != Rmark, ""); | |
| 2774 | |
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2775 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2776 %} |
| 2777 | |
| 2778 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2779 MacroAssembler _masm(&cbuf); | |
| 2780 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2781 Register Rold = reg_to_register_object($old$$reg); | |
| 2782 Register Rnew = reg_to_register_object($new$$reg); | |
| 2783 | |
| 2784 // casx_under_lock picks 1 of 3 encodings: | |
| 2785 // For 32-bit pointers you get a 32-bit CAS | |
| 2786 // For 64-bit pointers you get a 64-bit CASX | |
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2787 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2788 __ cmp( Rold, Rnew ); |
| 2789 %} | |
| 2790 | |
| 2791 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2792 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2793 Register Rold = reg_to_register_object($old$$reg); | |
| 2794 Register Rnew = reg_to_register_object($new$$reg); | |
| 2795 | |
| 2796 MacroAssembler _masm(&cbuf); | |
| 2797 __ mov(Rnew, O7); | |
| 2798 __ casx(Rmem, Rold, O7); | |
| 2799 __ cmp( Rold, O7 ); | |
| 2800 %} | |
| 2801 | |
| 2802 // raw int cas, used for compareAndSwap | |
| 2803 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2804 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2805 Register Rold = reg_to_register_object($old$$reg); | |
| 2806 Register Rnew = reg_to_register_object($new$$reg); | |
| 2807 | |
| 2808 MacroAssembler _masm(&cbuf); | |
| 2809 __ mov(Rnew, O7); | |
| 2810 __ cas(Rmem, Rold, O7); | |
| 2811 __ cmp( Rold, O7 ); | |
| 2812 %} | |
| 2813 | |
| 2814 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2815 Register Rres = reg_to_register_object($res$$reg); | |
| 2816 | |
| 2817 MacroAssembler _masm(&cbuf); | |
| 2818 __ mov(1, Rres); | |
| 2819 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2820 %} | |
| 2821 | |
| 2822 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2823 Register Rres = reg_to_register_object($res$$reg); | |
| 2824 | |
| 2825 MacroAssembler _masm(&cbuf); | |
| 2826 __ mov(1, Rres); | |
| 2827 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2828 %} | |
| 2829 | |
| 2830 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2831 MacroAssembler _masm(&cbuf); | |
| 2832 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2833 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2834 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2835 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2836 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2837 | |
| 2838 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2839 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2840 %} | |
| 2841 | |
| 2842 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2843 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2844 MacroAssembler _masm(&cbuf); | |
| 2845 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2846 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2847 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 2848 | |
| 2849 Label loop; | |
| 2850 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 2851 | |
| 2852 // Loop and clear, walking backwards through the array. | |
| 2853 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2854 __ bind(loop); | |
| 2855 __ deccc(nof_bytes_tmp, 8); | |
| 2856 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2857 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2858 // %%%% this mini-loop must not cross a cache boundary! | |
| 2859 %} | |
| 2860 | |
| 2861 | |
|
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2862 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2863 Label Ldone, Lloop; |
| 2864 MacroAssembler _masm(&cbuf); | |
| 2865 | |
| 2866 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2867 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2868 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2869 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2870 Register result_reg = reg_to_register_object($result$$reg); |
| 2871 | |
|
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2872 assert(result_reg != str1_reg && |
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2873 result_reg != str2_reg && |
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2874 result_reg != cnt1_reg && |
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2875 result_reg != cnt2_reg , |
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2876 "need different registers"); |
| 0 | 2877 |
| 2878 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2879 // difference of the string lengths (stack) | |
| 2880 | |
| 2881 // See if the lengths are different, and calculate min in str1_reg. | |
| 2882 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2883 Label Lskip; | |
|
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2884 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2885 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2886 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
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2887 // cnt2 is shorter, so use its count: |
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2888 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2889 __ bind(Lskip); |
| 2890 | |
|
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2891 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2892 // Note: limit_reg holds the string length pre-scaled by 2 |
|
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2893 Register limit_reg = cnt1_reg; |
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2894 Register chr2_reg = cnt2_reg; |
| 0 | 2895 Register chr1_reg = result_reg; |
|
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2896 // str{12} are the base pointers |
| 0 | 2897 |
| 2898 // Is the minimum length zero? | |
| 2899 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2900 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2901 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2902 | |
| 2903 // Load first characters | |
|
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2904 __ lduh(str1_reg, 0, chr1_reg); |
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2905 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2906 |
| 2907 // Compare first characters | |
| 2908 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2909 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2910 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2911 __ delayed()->nop(); | |
| 2912 | |
| 2913 { | |
| 2914 // Check after comparing first character to see if strings are equivalent | |
| 2915 Label LSkip2; | |
| 2916 // Check if the strings start at same location | |
|
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2917 __ cmp(str1_reg, str2_reg); |
| 0 | 2918 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2919 __ delayed()->nop(); | |
| 2920 | |
| 2921 // Check if the length difference is zero (in O7) | |
| 2922 __ cmp(G0, O7); | |
| 2923 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2924 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2925 | |
| 2926 // Strings might not be equal | |
| 2927 __ bind(LSkip2); | |
| 2928 } | |
| 2929 | |
| 2930 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2931 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2932 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2933 | |
|
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2934 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2935 __ add(str1_reg, limit_reg, str1_reg); |
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2936 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2937 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2938 | |
| 2939 // Compare the rest of the characters | |
|
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2940 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2941 __ bind(Lloop); |
|
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2942 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2943 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2944 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2945 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2946 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2947 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2948 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2949 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
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2950 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2951 |
| 2952 // If strings are equal up to min length, return the length difference. | |
| 2953 __ mov(O7, result_reg); | |
| 2954 | |
| 2955 // Otherwise, return the difference between the first mismatched chars. | |
| 2956 __ bind(Ldone); | |
| 2957 %} | |
| 2958 | |
|
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2959 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2960 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2961 MacroAssembler _masm(&cbuf); |
| 2962 | |
| 2963 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2964 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2965 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2966 Register tmp1_reg = O7; |
| 681 | 2967 Register result_reg = reg_to_register_object($result$$reg); |
| 2968 | |
|
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2969 assert(result_reg != str1_reg && |
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2970 result_reg != str2_reg && |
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2971 result_reg != cnt_reg && |
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2972 result_reg != tmp1_reg , |
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2973 "need different registers"); |
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2974 |
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2975 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2976 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2977 __ delayed()->add(G0, 1, result_reg); | |
| 2978 | |
|
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2979 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
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2980 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2981 |
| 681 | 2982 //rename registers |
|
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2983 Register limit_reg = cnt_reg; |
| 681 | 2984 Register chr1_reg = result_reg; |
|
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2985 Register chr2_reg = tmp1_reg; |
| 681 | 2986 |
| 2987 //check for alignment and position the pointers to the ends | |
|
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2988 __ or3(str1_reg, str2_reg, chr1_reg); |
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2989 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2990 // notZero means at least one not 4-byte aligned. |
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2991 // We could optimize the case when both arrays are not aligned |
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2992 // but it is not frequent case and it requires additional checks. |
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2993 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2994 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2995 |
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2996 // Compare char[] arrays aligned to 4 bytes. |
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2997 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2998 chr1_reg, chr2_reg, Ldone); |
| 681 | 2999 __ ba(false,Ldone); |
| 3000 __ delayed()->add(G0, 1, result_reg); | |
| 3001 | |
|
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3002 // char by char compare |
| 681 | 3003 __ bind(Lchar); |
|
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3004 __ add(str1_reg, limit_reg, str1_reg); |
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3005 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 3006 __ neg(limit_reg); //negate count |
| 3007 | |
|
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3008 __ lduh(str1_reg, limit_reg, chr1_reg); |
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3009 // Lchar_loop |
| 681 | 3010 __ bind(Lchar_loop); |
|
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3011 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 3012 __ cmp(chr1_reg, chr2_reg); |
| 3013 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 3014 __ delayed()->mov(G0, result_reg); //not equal | |
| 3015 __ inccc(limit_reg, sizeof(jchar)); | |
| 3016 // annul LDUH if branch is not taken to prevent access past end of string | |
|
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3017 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3018 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 3019 |
| 3020 __ add(G0, 1, result_reg); //equal | |
| 3021 | |
| 3022 __ bind(Ldone); | |
| 3023 %} | |
| 3024 | |
|
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3025 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 3026 Label Lvector, Ldone, Lloop; |
| 3027 MacroAssembler _masm(&cbuf); | |
| 3028 | |
| 3029 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3030 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3031 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
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3032 Register tmp2_reg = O7; |
| 681 | 3033 Register result_reg = reg_to_register_object($result$$reg); |
| 3034 | |
| 3035 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3036 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3037 | |
| 3038 // return true if the same array | |
| 3039 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3040 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3041 __ delayed()->add(G0, 1, result_reg); // equal |
| 3042 | |
| 3043 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3044 __ delayed()->mov(G0, result_reg); // not equal | |
| 3045 | |
| 3046 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3047 __ delayed()->mov(G0, result_reg); // not equal | |
| 3048 | |
| 3049 //load the lengths of arrays | |
| 727 | 3050 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3051 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3052 |
| 3053 // return false if the two arrays are not equal length | |
| 3054 __ cmp(tmp1_reg, tmp2_reg); | |
| 3055 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3056 __ delayed()->mov(G0, result_reg); // not equal | |
| 3057 | |
|
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3058 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
| 681 | 3059 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3060 | |
| 3061 // load array addresses | |
| 3062 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3063 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3064 | |
| 3065 // renaming registers | |
|
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3066 Register chr1_reg = result_reg; // for characters in ary1 |
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3067 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3068 Register limit_reg = tmp1_reg; // length |
| 3069 | |
| 3070 // set byte count | |
| 3071 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3072 |
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3073 // Compare char[] arrays aligned to 4 bytes. |
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3074 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3075 chr1_reg, chr2_reg, Ldone); |
| 681 | 3076 __ add(G0, 1, result_reg); // equals |
| 3077 | |
| 3078 __ bind(Ldone); | |
| 3079 %} | |
| 3080 | |
| 0 | 3081 enc_class enc_rethrow() %{ |
| 1748 | 3082 cbuf.set_insts_mark(); |
| 0 | 3083 Register temp_reg = G3; |
| 727 | 3084 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3085 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3086 MacroAssembler _masm(&cbuf); | |
| 3087 #ifdef ASSERT | |
| 3088 __ save_frame(0); | |
| 727 | 3089 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3090 __ sethi(last_rethrow_addrlit, L1); | |
| 3091 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3092 __ get_pc(L2); |
| 3093 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3094 __ st_ptr(L2, addr); |
| 0 | 3095 __ restore(); |
| 3096 #endif | |
| 727 | 3097 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3098 __ delayed()->nop(); |
| 3099 %} | |
| 3100 | |
| 3101 enc_class emit_mem_nop() %{ | |
| 3102 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3103 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3104 %} |
| 3105 | |
| 3106 enc_class emit_fadd_nop() %{ | |
| 3107 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3108 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3109 %} |
| 3110 | |
| 3111 enc_class emit_br_nop() %{ | |
| 3112 // Generates the instruction BPN,PN . | |
| 1748 | 3113 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3114 %} |
| 3115 | |
| 3116 enc_class enc_membar_acquire %{ | |
| 3117 MacroAssembler _masm(&cbuf); | |
| 3118 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3119 %} | |
| 3120 | |
| 3121 enc_class enc_membar_release %{ | |
| 3122 MacroAssembler _masm(&cbuf); | |
| 3123 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3124 %} | |
| 3125 | |
| 3126 enc_class enc_membar_volatile %{ | |
| 3127 MacroAssembler _masm(&cbuf); | |
| 3128 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3129 %} | |
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3130 |
| 0 | 3131 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3132 MacroAssembler _masm(&cbuf); | |
| 3133 Register src_reg = reg_to_register_object($src$$reg); | |
| 3134 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3135 __ sllx(src_reg, 56, dst_reg); | |
| 3136 __ srlx(dst_reg, 8, O7); | |
| 3137 __ or3 (dst_reg, O7, dst_reg); | |
| 3138 __ srlx(dst_reg, 16, O7); | |
| 3139 __ or3 (dst_reg, O7, dst_reg); | |
| 3140 __ srlx(dst_reg, 32, O7); | |
| 3141 __ or3 (dst_reg, O7, dst_reg); | |
| 3142 %} | |
| 3143 | |
| 3144 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3145 MacroAssembler _masm(&cbuf); | |
| 3146 Register src_reg = reg_to_register_object($src$$reg); | |
| 3147 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3148 __ sll(src_reg, 24, dst_reg); | |
| 3149 __ srl(dst_reg, 8, O7); | |
| 3150 __ or3(dst_reg, O7, dst_reg); | |
| 3151 __ srl(dst_reg, 16, O7); | |
| 3152 __ or3(dst_reg, O7, dst_reg); | |
| 3153 %} | |
| 3154 | |
| 3155 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3156 MacroAssembler _masm(&cbuf); | |
| 3157 Register src_reg = reg_to_register_object($src$$reg); | |
| 3158 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3159 __ sllx(src_reg, 48, dst_reg); | |
| 3160 __ srlx(dst_reg, 16, O7); | |
| 3161 __ or3 (dst_reg, O7, dst_reg); | |
| 3162 __ srlx(dst_reg, 32, O7); | |
| 3163 __ or3 (dst_reg, O7, dst_reg); | |
| 3164 %} | |
| 3165 | |
| 3166 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3167 MacroAssembler _masm(&cbuf); | |
| 3168 Register src_reg = reg_to_register_object($src$$reg); | |
| 3169 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3170 __ sllx(src_reg, 32, dst_reg); | |
| 3171 __ srlx(dst_reg, 32, O7); | |
| 3172 __ or3 (dst_reg, O7, dst_reg); | |
| 3173 %} | |
| 3174 | |
| 3175 %} | |
| 3176 | |
| 3177 //----------FRAME-------------------------------------------------------------- | |
| 3178 // Definition of frame structure and management information. | |
| 3179 // | |
| 3180 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3181 // | (to get allocators register number | |
| 3182 // G Owned by | | v add VMRegImpl::stack0) | |
| 3183 // r CALLER | | | |
| 3184 // o | +--------+ pad to even-align allocators stack-slot | |
| 3185 // w V | pad0 | numbers; owned by CALLER | |
| 3186 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3187 // h ^ | in | 5 | |
| 3188 // | | args | 4 Holes in incoming args owned by SELF | |
| 3189 // | | | | 3 | |
| 3190 // | | +--------+ | |
| 3191 // V | | old out| Empty on Intel, window on Sparc | |
| 3192 // | old |preserve| Must be even aligned. | |
| 3193 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3194 // | | in | 3 area for Intel ret address | |
| 3195 // Owned by |preserve| Empty on Sparc. | |
| 3196 // SELF +--------+ | |
| 3197 // | | pad2 | 2 pad to align old SP | |
| 3198 // | +--------+ 1 | |
| 3199 // | | locks | 0 | |
| 3200 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3201 // | | pad1 | 11 pad to align new SP | |
| 3202 // | +--------+ | |
| 3203 // | | | 10 | |
| 3204 // | | spills | 9 spills | |
| 3205 // V | | 8 (pad0 slot for callee) | |
| 3206 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3207 // ^ | out | 7 | |
| 3208 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3209 // Owned by +--------+ | |
| 3210 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3211 // | new |preserve| Must be even-aligned. | |
| 3212 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3213 // | | | | |
| 3214 // | |
| 3215 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3216 // known from SELF's arguments and the Java calling convention. | |
| 3217 // Region 6-7 is determined per call site. | |
| 3218 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3219 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3220 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3221 // incoming area, as the Java calling convention is completely under | |
| 3222 // the control of the AD file. Doubles can be sorted and packed to | |
| 3223 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3224 // varargs C calling conventions. | |
| 3225 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3226 // even aligned with pad0 as needed. | |
| 3227 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3228 // region 6-11 is even aligned; it may be padded out more so that | |
| 3229 // the region from SP to FP meets the minimum stack alignment. | |
| 3230 | |
| 3231 frame %{ | |
| 3232 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3233 stack_direction(TOWARDS_LOW); | |
| 3234 | |
| 3235 // These two registers define part of the calling convention | |
| 3236 // between compiled code and the interpreter. | |
| 3237 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3238 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3239 | |
| 3240 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3241 cisc_spilling_operand_name(indOffset); | |
| 3242 | |
| 3243 // Number of stack slots consumed by a Monitor enter | |
| 3244 #ifdef _LP64 | |
| 3245 sync_stack_slots(2); | |
| 3246 #else | |
| 3247 sync_stack_slots(1); | |
| 3248 #endif | |
| 3249 | |
| 3250 // Compiled code's Frame Pointer | |
| 3251 frame_pointer(R_SP); | |
| 3252 | |
| 3253 // Stack alignment requirement | |
| 3254 stack_alignment(StackAlignmentInBytes); | |
| 3255 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3256 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3257 | |
| 3258 // Number of stack slots between incoming argument block and the start of | |
| 3259 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3260 // EPILOG must remove this many slots. | |
| 3261 in_preserve_stack_slots(0); | |
| 3262 | |
| 3263 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3264 // for calls to C. Supports the var-args backing area for register parms. | |
| 3265 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3266 #ifdef _LP64 | |
| 3267 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3268 varargs_C_out_slots_killed(12); | |
| 3269 #else | |
| 3270 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3271 varargs_C_out_slots_killed( 7); | |
| 3272 #endif | |
| 3273 | |
| 3274 // The after-PROLOG location of the return address. Location of | |
| 3275 // return address specifies a type (REG or STACK) and a number | |
| 3276 // representing the register number (i.e. - use a register name) or | |
| 3277 // stack slot. | |
| 3278 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3279 | |
| 3280 // Body of function which returns an OptoRegs array locating | |
| 3281 // arguments either in registers or in stack slots for calling | |
| 3282 // java | |
| 3283 calling_convention %{ | |
| 3284 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3285 | |
| 3286 %} | |
| 3287 | |
| 3288 // Body of function which returns an OptoRegs array locating | |
| 3289 // arguments either in registers or in stack slots for callin | |
| 3290 // C. | |
| 3291 c_calling_convention %{ | |
| 3292 // This is obviously always outgoing | |
| 3293 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3294 %} | |
| 3295 | |
| 3296 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3297 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3298 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3299 // to and from the register pairs is done by the appropriate call and epilog | |
| 3300 // opcodes. This simplifies the register allocator. | |
| 3301 c_return_value %{ | |
| 3302 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3303 #ifdef _LP64 | |
|
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3304 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3305 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3306 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3307 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3308 #else // !_LP64 |
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3309 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3310 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3311 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3312 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3313 #endif |
| 3314 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3315 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3316 %} | |
| 3317 | |
| 3318 // Location of compiled Java return values. Same as C | |
| 3319 return_value %{ | |
| 3320 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3321 #ifdef _LP64 | |
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3322 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3323 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3324 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3325 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3326 #else // !_LP64 |
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3327 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3328 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3329 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3330 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3331 #endif |
| 3332 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3333 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3334 %} | |
| 3335 | |
| 3336 %} | |
| 3337 | |
| 3338 | |
| 3339 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3340 //----------Operand Attributes------------------------------------------------- | |
| 3341 op_attrib op_cost(1); // Required cost attribute | |
| 3342 | |
| 3343 //----------Instruction Attributes--------------------------------------------- | |
| 3344 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3345 ins_attrib ins_size(32); // Required size attribute (in bits) | |
| 3346 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 3347 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3348 // non-matching short branch variant of some | |
| 3349 // long branch? | |
| 3350 | |
| 3351 //----------OPERANDS----------------------------------------------------------- | |
| 3352 // Operand definitions must precede instruction definitions for correct parsing | |
| 3353 // in the ADLC because operands constitute user defined types which are used in | |
| 3354 // instruction definitions. | |
| 3355 | |
| 3356 //----------Simple Operands---------------------------------------------------- | |
| 3357 // Immediate Operands | |
| 3358 // Integer Immediate: 32-bit | |
| 3359 operand immI() %{ | |
| 3360 match(ConI); | |
| 3361 | |
| 3362 op_cost(0); | |
| 3363 // formats are generated automatically for constants and base registers | |
| 3364 format %{ %} | |
| 3365 interface(CONST_INTER); | |
| 3366 %} | |
| 3367 | |
| 824 | 3368 // Integer Immediate: 8-bit |
| 3369 operand immI8() %{ | |
| 3370 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 3371 match(ConI); | |
| 3372 op_cost(0); | |
| 3373 format %{ %} | |
| 3374 interface(CONST_INTER); | |
| 3375 %} | |
| 3376 | |
| 0 | 3377 // Integer Immediate: 13-bit |
| 3378 operand immI13() %{ | |
| 3379 predicate(Assembler::is_simm13(n->get_int())); | |
| 3380 match(ConI); | |
| 3381 op_cost(0); | |
| 3382 | |
| 3383 format %{ %} | |
| 3384 interface(CONST_INTER); | |
| 3385 %} | |
| 3386 | |
| 785 | 3387 // Integer Immediate: 13-bit minus 7 |
| 3388 operand immI13m7() %{ | |
| 3389 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3390 match(ConI); | |
| 3391 op_cost(0); | |
| 3392 | |
| 3393 format %{ %} | |
| 3394 interface(CONST_INTER); | |
| 3395 %} | |
| 3396 | |
| 824 | 3397 // Integer Immediate: 16-bit |
| 3398 operand immI16() %{ | |
| 3399 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 3400 match(ConI); | |
| 3401 op_cost(0); | |
| 3402 format %{ %} | |
| 3403 interface(CONST_INTER); | |
| 3404 %} | |
| 3405 | |
| 0 | 3406 // Unsigned (positive) Integer Immediate: 13-bit |
| 3407 operand immU13() %{ | |
| 3408 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3409 match(ConI); | |
| 3410 op_cost(0); | |
| 3411 | |
| 3412 format %{ %} | |
| 3413 interface(CONST_INTER); | |
| 3414 %} | |
| 3415 | |
| 3416 // Integer Immediate: 6-bit | |
| 3417 operand immU6() %{ | |
| 3418 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3419 match(ConI); | |
| 3420 op_cost(0); | |
| 3421 format %{ %} | |
| 3422 interface(CONST_INTER); | |
| 3423 %} | |
| 3424 | |
| 3425 // Integer Immediate: 11-bit | |
| 3426 operand immI11() %{ | |
| 3427 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3428 match(ConI); | |
| 3429 op_cost(0); | |
| 3430 format %{ %} | |
| 3431 interface(CONST_INTER); | |
| 3432 %} | |
| 3433 | |
| 3434 // Integer Immediate: 0-bit | |
| 3435 operand immI0() %{ | |
| 3436 predicate(n->get_int() == 0); | |
| 3437 match(ConI); | |
| 3438 op_cost(0); | |
| 3439 | |
| 3440 format %{ %} | |
| 3441 interface(CONST_INTER); | |
| 3442 %} | |
| 3443 | |
| 3444 // Integer Immediate: the value 10 | |
| 3445 operand immI10() %{ | |
| 3446 predicate(n->get_int() == 10); | |
| 3447 match(ConI); | |
| 3448 op_cost(0); | |
| 3449 | |
| 3450 format %{ %} | |
| 3451 interface(CONST_INTER); | |
| 3452 %} | |
| 3453 | |
| 3454 // Integer Immediate: the values 0-31 | |
| 3455 operand immU5() %{ | |
| 3456 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3457 match(ConI); | |
| 3458 op_cost(0); | |
| 3459 | |
| 3460 format %{ %} | |
| 3461 interface(CONST_INTER); | |
| 3462 %} | |
| 3463 | |
| 3464 // Integer Immediate: the values 1-31 | |
| 3465 operand immI_1_31() %{ | |
| 3466 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3467 match(ConI); | |
| 3468 op_cost(0); | |
| 3469 | |
| 3470 format %{ %} | |
| 3471 interface(CONST_INTER); | |
| 3472 %} | |
| 3473 | |
| 3474 // Integer Immediate: the values 32-63 | |
| 3475 operand immI_32_63() %{ | |
| 3476 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3477 match(ConI); | |
| 3478 op_cost(0); | |
| 3479 | |
| 3480 format %{ %} | |
| 3481 interface(CONST_INTER); | |
| 3482 %} | |
| 3483 | |
| 785 | 3484 // Immediates for special shifts (sign extend) |
| 3485 | |
| 3486 // Integer Immediate: the value 16 | |
| 3487 operand immI_16() %{ | |
| 3488 predicate(n->get_int() == 16); | |
| 3489 match(ConI); | |
| 3490 op_cost(0); | |
| 3491 | |
| 3492 format %{ %} | |
| 3493 interface(CONST_INTER); | |
| 3494 %} | |
| 3495 | |
| 3496 // Integer Immediate: the value 24 | |
| 3497 operand immI_24() %{ | |
| 3498 predicate(n->get_int() == 24); | |
| 3499 match(ConI); | |
| 3500 op_cost(0); | |
| 3501 | |
| 3502 format %{ %} | |
| 3503 interface(CONST_INTER); | |
| 3504 %} | |
| 3505 | |
| 0 | 3506 // Integer Immediate: the value 255 |
| 3507 operand immI_255() %{ | |
| 3508 predicate( n->get_int() == 255 ); | |
| 3509 match(ConI); | |
| 3510 op_cost(0); | |
| 3511 | |
| 3512 format %{ %} | |
| 3513 interface(CONST_INTER); | |
| 3514 %} | |
| 3515 | |
| 785 | 3516 // Integer Immediate: the value 65535 |
| 3517 operand immI_65535() %{ | |
| 3518 predicate(n->get_int() == 65535); | |
| 3519 match(ConI); | |
| 3520 op_cost(0); | |
| 3521 | |
| 3522 format %{ %} | |
| 3523 interface(CONST_INTER); | |
| 3524 %} | |
| 3525 | |
| 0 | 3526 // Long Immediate: the value FF |
| 3527 operand immL_FF() %{ | |
| 3528 predicate( n->get_long() == 0xFFL ); | |
| 3529 match(ConL); | |
| 3530 op_cost(0); | |
| 3531 | |
| 3532 format %{ %} | |
| 3533 interface(CONST_INTER); | |
| 3534 %} | |
| 3535 | |
| 3536 // Long Immediate: the value FFFF | |
| 3537 operand immL_FFFF() %{ | |
| 3538 predicate( n->get_long() == 0xFFFFL ); | |
| 3539 match(ConL); | |
| 3540 op_cost(0); | |
| 3541 | |
| 3542 format %{ %} | |
| 3543 interface(CONST_INTER); | |
| 3544 %} | |
| 3545 | |
| 3546 // Pointer Immediate: 32 or 64-bit | |
| 3547 operand immP() %{ | |
| 3548 match(ConP); | |
| 3549 | |
| 3550 op_cost(5); | |
| 3551 // formats are generated automatically for constants and base registers | |
| 3552 format %{ %} | |
| 3553 interface(CONST_INTER); | |
| 3554 %} | |
| 3555 | |
| 2008 | 3556 // Pointer Immediate: 32 or 64-bit |
| 3557 operand immP_set() %{ | |
| 3558 predicate(!VM_Version::is_niagara1_plus()); | |
| 3559 match(ConP); | |
| 3560 | |
| 3561 op_cost(5); | |
| 3562 // formats are generated automatically for constants and base registers | |
| 3563 format %{ %} | |
| 3564 interface(CONST_INTER); | |
| 3565 %} | |
| 3566 | |
| 3567 // Pointer Immediate: 32 or 64-bit | |
| 3568 // From Niagara2 processors on a load should be better than materializing. | |
| 3569 operand immP_load() %{ | |
| 3570 predicate(VM_Version::is_niagara1_plus()); | |
| 3571 match(ConP); | |
| 3572 | |
| 3573 op_cost(5); | |
| 3574 // formats are generated automatically for constants and base registers | |
| 3575 format %{ %} | |
| 3576 interface(CONST_INTER); | |
| 3577 %} | |
| 3578 | |
| 0 | 3579 operand immP13() %{ |
| 3580 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3581 match(ConP); | |
| 3582 op_cost(0); | |
| 3583 | |
| 3584 format %{ %} | |
| 3585 interface(CONST_INTER); | |
| 3586 %} | |
| 3587 | |
| 3588 operand immP0() %{ | |
| 3589 predicate(n->get_ptr() == 0); | |
| 3590 match(ConP); | |
| 3591 op_cost(0); | |
| 3592 | |
| 3593 format %{ %} | |
| 3594 interface(CONST_INTER); | |
| 3595 %} | |
| 3596 | |
| 3597 operand immP_poll() %{ | |
| 3598 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3599 match(ConP); | |
| 3600 | |
| 3601 // formats are generated automatically for constants and base registers | |
| 3602 format %{ %} | |
| 3603 interface(CONST_INTER); | |
| 3604 %} | |
| 3605 | |
|
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3606 // Pointer Immediate |
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3607 operand immN() |
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3608 %{ |
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3609 match(ConN); |
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3610 |
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3611 op_cost(10); |
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3612 format %{ %} |
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3613 interface(CONST_INTER); |
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3614 %} |
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3615 |
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3616 // NULL Pointer Immediate |
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3617 operand immN0() |
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3618 %{ |
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3619 predicate(n->get_narrowcon() == 0); |
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3620 match(ConN); |
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3621 |
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3622 op_cost(0); |
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3623 format %{ %} |
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3624 interface(CONST_INTER); |
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3625 %} |
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3626 |
| 0 | 3627 operand immL() %{ |
| 3628 match(ConL); | |
| 3629 op_cost(40); | |
| 3630 // formats are generated automatically for constants and base registers | |
| 3631 format %{ %} | |
| 3632 interface(CONST_INTER); | |
| 3633 %} | |
| 3634 | |
| 3635 operand immL0() %{ | |
| 3636 predicate(n->get_long() == 0L); | |
| 3637 match(ConL); | |
| 3638 op_cost(0); | |
| 3639 // formats are generated automatically for constants and base registers | |
| 3640 format %{ %} | |
| 3641 interface(CONST_INTER); | |
| 3642 %} | |
| 3643 | |
| 3644 // Long Immediate: 13-bit | |
| 3645 operand immL13() %{ | |
| 3646 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3647 match(ConL); | |
| 3648 op_cost(0); | |
| 3649 | |
| 3650 format %{ %} | |
| 3651 interface(CONST_INTER); | |
| 3652 %} | |
| 3653 | |
| 785 | 3654 // Long Immediate: 13-bit minus 7 |
| 3655 operand immL13m7() %{ | |
| 3656 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3657 match(ConL); | |
| 3658 op_cost(0); | |
| 3659 | |
| 3660 format %{ %} | |
| 3661 interface(CONST_INTER); | |
| 3662 %} | |
| 3663 | |
| 0 | 3664 // Long Immediate: low 32-bit mask |
| 3665 operand immL_32bits() %{ | |
| 3666 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3667 match(ConL); | |
| 3668 op_cost(0); | |
| 3669 | |
| 3670 format %{ %} | |
| 3671 interface(CONST_INTER); | |
| 3672 %} | |
| 3673 | |
| 2008 | 3674 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3675 operand immL_cheap() %{ | |
| 3676 predicate(!VM_Version::is_niagara1_plus() || MacroAssembler::size_of_set64(n->get_long()) <= 3); | |
| 3677 match(ConL); | |
| 3678 op_cost(0); | |
| 3679 | |
| 3680 format %{ %} | |
| 3681 interface(CONST_INTER); | |
| 3682 %} | |
| 3683 | |
| 3684 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3685 operand immL_expensive() %{ | |
| 3686 predicate(VM_Version::is_niagara1_plus() && MacroAssembler::size_of_set64(n->get_long()) > 3); | |
| 3687 match(ConL); | |
| 3688 op_cost(0); | |
| 3689 | |
| 3690 format %{ %} | |
| 3691 interface(CONST_INTER); | |
| 3692 %} | |
| 3693 | |
| 0 | 3694 // Double Immediate |
| 3695 operand immD() %{ | |
| 3696 match(ConD); | |
| 3697 | |
| 3698 op_cost(40); | |
| 3699 format %{ %} | |
| 3700 interface(CONST_INTER); | |
| 3701 %} | |
| 3702 | |
| 3703 operand immD0() %{ | |
| 3704 #ifdef _LP64 | |
| 3705 // on 64-bit architectures this comparision is faster | |
| 3706 predicate(jlong_cast(n->getd()) == 0); | |
| 3707 #else | |
| 3708 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3709 #endif | |
| 3710 match(ConD); | |
| 3711 | |
| 3712 op_cost(0); | |
| 3713 format %{ %} | |
| 3714 interface(CONST_INTER); | |
| 3715 %} | |
| 3716 | |
| 3717 // Float Immediate | |
| 3718 operand immF() %{ | |
| 3719 match(ConF); | |
| 3720 | |
| 3721 op_cost(20); | |
| 3722 format %{ %} | |
| 3723 interface(CONST_INTER); | |
| 3724 %} | |
| 3725 | |
| 3726 // Float Immediate: 0 | |
| 3727 operand immF0() %{ | |
| 3728 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3729 match(ConF); | |
| 3730 | |
| 3731 op_cost(0); | |
| 3732 format %{ %} | |
| 3733 interface(CONST_INTER); | |
| 3734 %} | |
| 3735 | |
| 3736 // Integer Register Operands | |
| 3737 // Integer Register | |
| 3738 operand iRegI() %{ | |
| 3739 constraint(ALLOC_IN_RC(int_reg)); | |
| 3740 match(RegI); | |
| 3741 | |
| 3742 match(notemp_iRegI); | |
| 3743 match(g1RegI); | |
| 3744 match(o0RegI); | |
| 3745 match(iRegIsafe); | |
| 3746 | |
| 3747 format %{ %} | |
| 3748 interface(REG_INTER); | |
| 3749 %} | |
| 3750 | |
| 3751 operand notemp_iRegI() %{ | |
| 3752 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3753 match(RegI); | |
| 3754 | |
| 3755 match(o0RegI); | |
| 3756 | |
| 3757 format %{ %} | |
| 3758 interface(REG_INTER); | |
| 3759 %} | |
| 3760 | |
| 3761 operand o0RegI() %{ | |
| 3762 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3763 match(iRegI); | |
| 3764 | |
| 3765 format %{ %} | |
| 3766 interface(REG_INTER); | |
| 3767 %} | |
| 3768 | |
| 3769 // Pointer Register | |
| 3770 operand iRegP() %{ | |
| 3771 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3772 match(RegP); | |
| 3773 | |
| 3774 match(lock_ptr_RegP); | |
| 3775 match(g1RegP); | |
| 3776 match(g2RegP); | |
| 3777 match(g3RegP); | |
| 3778 match(g4RegP); | |
| 3779 match(i0RegP); | |
| 3780 match(o0RegP); | |
| 3781 match(o1RegP); | |
| 3782 match(l7RegP); | |
| 3783 | |
| 3784 format %{ %} | |
| 3785 interface(REG_INTER); | |
| 3786 %} | |
| 3787 | |
| 3788 operand sp_ptr_RegP() %{ | |
| 3789 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3790 match(RegP); | |
| 3791 match(iRegP); | |
| 3792 | |
| 3793 format %{ %} | |
| 3794 interface(REG_INTER); | |
| 3795 %} | |
| 3796 | |
| 3797 operand lock_ptr_RegP() %{ | |
| 3798 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3799 match(RegP); | |
| 3800 match(i0RegP); | |
| 3801 match(o0RegP); | |
| 3802 match(o1RegP); | |
| 3803 match(l7RegP); | |
| 3804 | |
| 3805 format %{ %} | |
| 3806 interface(REG_INTER); | |
| 3807 %} | |
| 3808 | |
| 3809 operand g1RegP() %{ | |
| 3810 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3811 match(iRegP); | |
| 3812 | |
| 3813 format %{ %} | |
| 3814 interface(REG_INTER); | |
| 3815 %} | |
| 3816 | |
| 3817 operand g2RegP() %{ | |
| 3818 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3819 match(iRegP); | |
| 3820 | |
| 3821 format %{ %} | |
| 3822 interface(REG_INTER); | |
| 3823 %} | |
| 3824 | |
| 3825 operand g3RegP() %{ | |
| 3826 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3827 match(iRegP); | |
| 3828 | |
| 3829 format %{ %} | |
| 3830 interface(REG_INTER); | |
| 3831 %} | |
| 3832 | |
| 3833 operand g1RegI() %{ | |
| 3834 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3835 match(iRegI); | |
| 3836 | |
| 3837 format %{ %} | |
| 3838 interface(REG_INTER); | |
| 3839 %} | |
| 3840 | |
| 3841 operand g3RegI() %{ | |
| 3842 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3843 match(iRegI); | |
| 3844 | |
| 3845 format %{ %} | |
| 3846 interface(REG_INTER); | |
| 3847 %} | |
| 3848 | |
| 3849 operand g4RegI() %{ | |
| 3850 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3851 match(iRegI); | |
| 3852 | |
| 3853 format %{ %} | |
| 3854 interface(REG_INTER); | |
| 3855 %} | |
| 3856 | |
| 3857 operand g4RegP() %{ | |
| 3858 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3859 match(iRegP); | |
| 3860 | |
| 3861 format %{ %} | |
| 3862 interface(REG_INTER); | |
| 3863 %} | |
| 3864 | |
| 3865 operand i0RegP() %{ | |
| 3866 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3867 match(iRegP); | |
| 3868 | |
| 3869 format %{ %} | |
| 3870 interface(REG_INTER); | |
| 3871 %} | |
| 3872 | |
| 3873 operand o0RegP() %{ | |
| 3874 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3875 match(iRegP); | |
| 3876 | |
| 3877 format %{ %} | |
| 3878 interface(REG_INTER); | |
| 3879 %} | |
| 3880 | |
| 3881 operand o1RegP() %{ | |
| 3882 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3883 match(iRegP); | |
| 3884 | |
| 3885 format %{ %} | |
| 3886 interface(REG_INTER); | |
| 3887 %} | |
| 3888 | |
| 3889 operand o2RegP() %{ | |
| 3890 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3891 match(iRegP); | |
| 3892 | |
| 3893 format %{ %} | |
| 3894 interface(REG_INTER); | |
| 3895 %} | |
| 3896 | |
| 3897 operand o7RegP() %{ | |
| 3898 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3899 match(iRegP); | |
| 3900 | |
| 3901 format %{ %} | |
| 3902 interface(REG_INTER); | |
| 3903 %} | |
| 3904 | |
| 3905 operand l7RegP() %{ | |
| 3906 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3907 match(iRegP); | |
| 3908 | |
| 3909 format %{ %} | |
| 3910 interface(REG_INTER); | |
| 3911 %} | |
| 3912 | |
| 3913 operand o7RegI() %{ | |
| 3914 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3915 match(iRegI); | |
| 3916 | |
| 3917 format %{ %} | |
| 3918 interface(REG_INTER); | |
| 3919 %} | |
| 3920 | |
|
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3921 operand iRegN() %{ |
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3922 constraint(ALLOC_IN_RC(int_reg)); |
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3923 match(RegN); |
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3924 |
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3925 format %{ %} |
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3926 interface(REG_INTER); |
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3927 %} |
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3928 |
| 0 | 3929 // Long Register |
| 3930 operand iRegL() %{ | |
| 3931 constraint(ALLOC_IN_RC(long_reg)); | |
| 3932 match(RegL); | |
| 3933 | |
| 3934 format %{ %} | |
| 3935 interface(REG_INTER); | |
| 3936 %} | |
| 3937 | |
| 3938 operand o2RegL() %{ | |
| 3939 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3940 match(iRegL); | |
| 3941 | |
| 3942 format %{ %} | |
| 3943 interface(REG_INTER); | |
| 3944 %} | |
| 3945 | |
| 3946 operand o7RegL() %{ | |
| 3947 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3948 match(iRegL); | |
| 3949 | |
| 3950 format %{ %} | |
| 3951 interface(REG_INTER); | |
| 3952 %} | |
| 3953 | |
| 3954 operand g1RegL() %{ | |
| 3955 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3956 match(iRegL); | |
| 3957 | |
| 3958 format %{ %} | |
| 3959 interface(REG_INTER); | |
| 3960 %} | |
| 3961 | |
|
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3962 operand g3RegL() %{ |
|
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3963 constraint(ALLOC_IN_RC(g3_regL)); |
|
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|
3964 match(iRegL); |
|
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|
3965 |
|
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|
3966 format %{ %} |
|
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|
3967 interface(REG_INTER); |
|
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|
3968 %} |
|
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|
3969 |
| 0 | 3970 // Int Register safe |
| 3971 // This is 64bit safe | |
| 3972 operand iRegIsafe() %{ | |
| 3973 constraint(ALLOC_IN_RC(long_reg)); | |
| 3974 | |
| 3975 match(iRegI); | |
| 3976 | |
| 3977 format %{ %} | |
| 3978 interface(REG_INTER); | |
| 3979 %} | |
| 3980 | |
| 3981 // Condition Code Flag Register | |
| 3982 operand flagsReg() %{ | |
| 3983 constraint(ALLOC_IN_RC(int_flags)); | |
| 3984 match(RegFlags); | |
| 3985 | |
| 3986 format %{ "ccr" %} // both ICC and XCC | |
| 3987 interface(REG_INTER); | |
| 3988 %} | |
| 3989 | |
| 3990 // Condition Code Register, unsigned comparisons. | |
| 3991 operand flagsRegU() %{ | |
| 3992 constraint(ALLOC_IN_RC(int_flags)); | |
| 3993 match(RegFlags); | |
| 3994 | |
| 3995 format %{ "icc_U" %} | |
| 3996 interface(REG_INTER); | |
| 3997 %} | |
| 3998 | |
| 3999 // Condition Code Register, pointer comparisons. | |
| 4000 operand flagsRegP() %{ | |
| 4001 constraint(ALLOC_IN_RC(int_flags)); | |
| 4002 match(RegFlags); | |
| 4003 | |
| 4004 #ifdef _LP64 | |
| 4005 format %{ "xcc_P" %} | |
| 4006 #else | |
| 4007 format %{ "icc_P" %} | |
| 4008 #endif | |
| 4009 interface(REG_INTER); | |
| 4010 %} | |
| 4011 | |
| 4012 // Condition Code Register, long comparisons. | |
| 4013 operand flagsRegL() %{ | |
| 4014 constraint(ALLOC_IN_RC(int_flags)); | |
| 4015 match(RegFlags); | |
| 4016 | |
| 4017 format %{ "xcc_L" %} | |
| 4018 interface(REG_INTER); | |
| 4019 %} | |
| 4020 | |
| 4021 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4022 operand flagsRegF() %{ | |
| 4023 constraint(ALLOC_IN_RC(float_flags)); | |
| 4024 match(RegFlags); | |
| 4025 match(flagsRegF0); | |
| 4026 | |
| 4027 format %{ %} | |
| 4028 interface(REG_INTER); | |
| 4029 %} | |
| 4030 | |
| 4031 operand flagsRegF0() %{ | |
| 4032 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4033 match(RegFlags); | |
| 4034 | |
| 4035 format %{ %} | |
| 4036 interface(REG_INTER); | |
| 4037 %} | |
| 4038 | |
| 4039 | |
| 4040 // Condition Code Flag Register used by long compare | |
| 4041 operand flagsReg_long_LTGE() %{ | |
| 4042 constraint(ALLOC_IN_RC(int_flags)); | |
| 4043 match(RegFlags); | |
| 4044 format %{ "icc_LTGE" %} | |
| 4045 interface(REG_INTER); | |
| 4046 %} | |
| 4047 operand flagsReg_long_EQNE() %{ | |
| 4048 constraint(ALLOC_IN_RC(int_flags)); | |
| 4049 match(RegFlags); | |
| 4050 format %{ "icc_EQNE" %} | |
| 4051 interface(REG_INTER); | |
| 4052 %} | |
| 4053 operand flagsReg_long_LEGT() %{ | |
| 4054 constraint(ALLOC_IN_RC(int_flags)); | |
| 4055 match(RegFlags); | |
| 4056 format %{ "icc_LEGT" %} | |
| 4057 interface(REG_INTER); | |
| 4058 %} | |
| 4059 | |
| 4060 | |
| 4061 operand regD() %{ | |
| 4062 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4063 match(RegD); | |
| 4064 | |
| 551 | 4065 match(regD_low); |
| 4066 | |
| 0 | 4067 format %{ %} |
| 4068 interface(REG_INTER); | |
| 4069 %} | |
| 4070 | |
| 4071 operand regF() %{ | |
| 4072 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4073 match(RegF); | |
| 4074 | |
| 4075 format %{ %} | |
| 4076 interface(REG_INTER); | |
| 4077 %} | |
| 4078 | |
| 4079 operand regD_low() %{ | |
| 4080 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4081 match(regD); |
| 0 | 4082 |
| 4083 format %{ %} | |
| 4084 interface(REG_INTER); | |
| 4085 %} | |
| 4086 | |
| 4087 // Special Registers | |
| 4088 | |
| 4089 // Method Register | |
| 4090 operand inline_cache_regP(iRegP reg) %{ | |
| 4091 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4092 match(reg); | |
| 4093 format %{ %} | |
| 4094 interface(REG_INTER); | |
| 4095 %} | |
| 4096 | |
| 4097 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4098 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4099 match(reg); | |
| 4100 format %{ %} | |
| 4101 interface(REG_INTER); | |
| 4102 %} | |
| 4103 | |
| 4104 | |
| 4105 //----------Complex Operands--------------------------------------------------- | |
| 4106 // Indirect Memory Reference | |
| 4107 operand indirect(sp_ptr_RegP reg) %{ | |
| 4108 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4109 match(reg); | |
| 4110 | |
| 4111 op_cost(100); | |
| 4112 format %{ "[$reg]" %} | |
| 4113 interface(MEMORY_INTER) %{ | |
| 4114 base($reg); | |
| 4115 index(0x0); | |
| 4116 scale(0x0); | |
| 4117 disp(0x0); | |
| 4118 %} | |
| 4119 %} | |
| 4120 | |
| 785 | 4121 // Indirect with simm13 Offset |
| 0 | 4122 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4123 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4124 match(AddP reg offset); | |
| 4125 | |
| 4126 op_cost(100); | |
| 4127 format %{ "[$reg + $offset]" %} | |
| 4128 interface(MEMORY_INTER) %{ | |
| 4129 base($reg); | |
| 4130 index(0x0); | |
| 4131 scale(0x0); | |
| 4132 disp($offset); | |
| 4133 %} | |
| 4134 %} | |
| 4135 | |
| 785 | 4136 // Indirect with simm13 Offset minus 7 |
| 4137 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4138 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4139 match(AddP reg offset); | |
| 4140 | |
| 4141 op_cost(100); | |
| 4142 format %{ "[$reg + $offset]" %} | |
| 4143 interface(MEMORY_INTER) %{ | |
| 4144 base($reg); | |
| 4145 index(0x0); | |
| 4146 scale(0x0); | |
| 4147 disp($offset); | |
| 4148 %} | |
| 4149 %} | |
| 4150 | |
| 0 | 4151 // Note: Intel has a swapped version also, like this: |
| 4152 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4153 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4154 // match(AddP offset reg); | |
| 4155 // | |
| 4156 // op_cost(100); | |
| 4157 // format %{ "[$reg + $offset]" %} | |
| 4158 // interface(MEMORY_INTER) %{ | |
| 4159 // base($reg); | |
| 4160 // index(0x0); | |
| 4161 // scale(0x0); | |
| 4162 // disp($offset); | |
| 4163 // %} | |
| 4164 //%} | |
| 4165 //// However, it doesn't make sense for SPARC, since | |
| 4166 // we have no particularly good way to embed oops in | |
| 4167 // single instructions. | |
| 4168 | |
| 4169 // Indirect with Register Index | |
| 4170 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4171 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4172 match(AddP addr index); | |
| 4173 | |
| 4174 op_cost(100); | |
| 4175 format %{ "[$addr + $index]" %} | |
| 4176 interface(MEMORY_INTER) %{ | |
| 4177 base($addr); | |
| 4178 index($index); | |
| 4179 scale(0x0); | |
| 4180 disp(0x0); | |
| 4181 %} | |
| 4182 %} | |
| 4183 | |
| 4184 //----------Special Memory Operands-------------------------------------------- | |
| 4185 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4186 // values on the stack where a match requires a value to | |
| 4187 // flow through memory. | |
| 4188 operand stackSlotI(sRegI reg) %{ | |
| 4189 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4190 op_cost(100); | |
| 4191 //match(RegI); | |
| 4192 format %{ "[$reg]" %} | |
| 4193 interface(MEMORY_INTER) %{ | |
| 4194 base(0xE); // R_SP | |
| 4195 index(0x0); | |
| 4196 scale(0x0); | |
| 4197 disp($reg); // Stack Offset | |
| 4198 %} | |
| 4199 %} | |
| 4200 | |
| 4201 operand stackSlotP(sRegP reg) %{ | |
| 4202 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4203 op_cost(100); | |
| 4204 //match(RegP); | |
| 4205 format %{ "[$reg]" %} | |
| 4206 interface(MEMORY_INTER) %{ | |
| 4207 base(0xE); // R_SP | |
| 4208 index(0x0); | |
| 4209 scale(0x0); | |
| 4210 disp($reg); // Stack Offset | |
| 4211 %} | |
| 4212 %} | |
| 4213 | |
| 4214 operand stackSlotF(sRegF reg) %{ | |
| 4215 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4216 op_cost(100); | |
| 4217 //match(RegF); | |
| 4218 format %{ "[$reg]" %} | |
| 4219 interface(MEMORY_INTER) %{ | |
| 4220 base(0xE); // R_SP | |
| 4221 index(0x0); | |
| 4222 scale(0x0); | |
| 4223 disp($reg); // Stack Offset | |
| 4224 %} | |
| 4225 %} | |
| 4226 operand stackSlotD(sRegD reg) %{ | |
| 4227 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4228 op_cost(100); | |
| 4229 //match(RegD); | |
| 4230 format %{ "[$reg]" %} | |
| 4231 interface(MEMORY_INTER) %{ | |
| 4232 base(0xE); // R_SP | |
| 4233 index(0x0); | |
| 4234 scale(0x0); | |
| 4235 disp($reg); // Stack Offset | |
| 4236 %} | |
| 4237 %} | |
| 4238 operand stackSlotL(sRegL reg) %{ | |
| 4239 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4240 op_cost(100); | |
| 4241 //match(RegL); | |
| 4242 format %{ "[$reg]" %} | |
| 4243 interface(MEMORY_INTER) %{ | |
| 4244 base(0xE); // R_SP | |
| 4245 index(0x0); | |
| 4246 scale(0x0); | |
| 4247 disp($reg); // Stack Offset | |
| 4248 %} | |
| 4249 %} | |
| 4250 | |
| 4251 // Operands for expressing Control Flow | |
| 4252 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4253 // the AD file. It is generically handled within the ADLC. | |
| 4254 | |
| 4255 //----------Conditional Branch Operands---------------------------------------- | |
| 4256 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4257 // the following set of codes: | |
| 4258 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4259 // | |
| 4260 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4261 // by the comparison instruction that sets a condition code flags register. | |
| 4262 // That result is represented by a flags operand whose subtype is appropriate | |
| 4263 // to the unsignedness (etc.) of the comparison. | |
| 4264 // | |
| 4265 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4266 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4267 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4268 | |
| 4269 operand cmpOp() %{ | |
| 4270 match(Bool); | |
| 4271 | |
| 4272 format %{ "" %} | |
| 4273 interface(COND_INTER) %{ | |
| 4274 equal(0x1); | |
| 4275 not_equal(0x9); | |
| 4276 less(0x3); | |
| 4277 greater_equal(0xB); | |
| 4278 less_equal(0x2); | |
| 4279 greater(0xA); | |
| 4280 %} | |
| 4281 %} | |
| 4282 | |
| 4283 // Comparison Op, unsigned | |
| 4284 operand cmpOpU() %{ | |
| 4285 match(Bool); | |
| 4286 | |
| 4287 format %{ "u" %} | |
| 4288 interface(COND_INTER) %{ | |
| 4289 equal(0x1); | |
| 4290 not_equal(0x9); | |
| 4291 less(0x5); | |
| 4292 greater_equal(0xD); | |
| 4293 less_equal(0x4); | |
| 4294 greater(0xC); | |
| 4295 %} | |
| 4296 %} | |
| 4297 | |
| 4298 // Comparison Op, pointer (same as unsigned) | |
| 4299 operand cmpOpP() %{ | |
| 4300 match(Bool); | |
| 4301 | |
| 4302 format %{ "p" %} | |
| 4303 interface(COND_INTER) %{ | |
| 4304 equal(0x1); | |
| 4305 not_equal(0x9); | |
| 4306 less(0x5); | |
| 4307 greater_equal(0xD); | |
| 4308 less_equal(0x4); | |
| 4309 greater(0xC); | |
| 4310 %} | |
| 4311 %} | |
| 4312 | |
| 4313 // Comparison Op, branch-register encoding | |
| 4314 operand cmpOp_reg() %{ | |
| 4315 match(Bool); | |
| 4316 | |
| 4317 format %{ "" %} | |
| 4318 interface(COND_INTER) %{ | |
| 4319 equal (0x1); | |
| 4320 not_equal (0x5); | |
| 4321 less (0x3); | |
| 4322 greater_equal(0x7); | |
| 4323 less_equal (0x2); | |
| 4324 greater (0x6); | |
| 4325 %} | |
| 4326 %} | |
| 4327 | |
| 4328 // Comparison Code, floating, unordered same as less | |
| 4329 operand cmpOpF() %{ | |
| 4330 match(Bool); | |
| 4331 | |
| 4332 format %{ "fl" %} | |
| 4333 interface(COND_INTER) %{ | |
| 4334 equal(0x9); | |
| 4335 not_equal(0x1); | |
| 4336 less(0x3); | |
| 4337 greater_equal(0xB); | |
| 4338 less_equal(0xE); | |
| 4339 greater(0x6); | |
| 4340 %} | |
| 4341 %} | |
| 4342 | |
| 4343 // Used by long compare | |
| 4344 operand cmpOp_commute() %{ | |
| 4345 match(Bool); | |
| 4346 | |
| 4347 format %{ "" %} | |
| 4348 interface(COND_INTER) %{ | |
| 4349 equal(0x1); | |
| 4350 not_equal(0x9); | |
| 4351 less(0xA); | |
| 4352 greater_equal(0x2); | |
| 4353 less_equal(0xB); | |
| 4354 greater(0x3); | |
| 4355 %} | |
| 4356 %} | |
| 4357 | |
| 4358 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4359 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4360 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4361 // instructions for every form of operand when the instruction accepts |
| 4362 // multiple operand types with the same basic encoding and format. The classic | |
| 4363 // case of this is memory operands. | |
| 4364 opclass memory( indirect, indOffset13, indIndex ); | |
|
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|
4365 opclass indIndexMemory( indIndex ); |
| 0 | 4366 |
| 4367 //----------PIPELINE----------------------------------------------------------- | |
| 4368 pipeline %{ | |
| 4369 | |
| 4370 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4371 attributes %{ | |
| 4372 fixed_size_instructions; // Fixed size instructions | |
| 4373 branch_has_delay_slot; // Branch has delay slot following | |
| 4374 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4375 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4376 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4377 instruction_fetch_units = 1; // of 16 bytes | |
| 4378 | |
| 4379 // List of nop instructions | |
| 4380 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4381 %} | |
| 4382 | |
| 4383 //----------RESOURCES---------------------------------------------------------- | |
| 4384 // Resources are the functional units available to the machine | |
| 4385 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4386 | |
| 4387 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4388 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4389 | |
| 4390 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4391 | |
| 4392 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4393 // Pipeline Classes describe the stages in which input and output are | |
| 4394 // referenced by the hardware pipeline. | |
| 4395 | |
| 4396 // Integer ALU reg-reg operation | |
| 4397 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4398 single_instruction; | |
| 4399 dst : E(write); | |
| 4400 src1 : R(read); | |
| 4401 src2 : R(read); | |
| 4402 IALU : R; | |
| 4403 %} | |
| 4404 | |
| 4405 // Integer ALU reg-reg long operation | |
| 4406 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4407 instruction_count(2); | |
| 4408 dst : E(write); | |
| 4409 src1 : R(read); | |
| 4410 src2 : R(read); | |
| 4411 IALU : R; | |
| 4412 IALU : R; | |
| 4413 %} | |
| 4414 | |
| 4415 // Integer ALU reg-reg long dependent operation | |
| 4416 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4417 instruction_count(1); multiple_bundles; | |
| 4418 dst : E(write); | |
| 4419 src1 : R(read); | |
| 4420 src2 : R(read); | |
| 4421 cr : E(write); | |
| 4422 IALU : R(2); | |
| 4423 %} | |
| 4424 | |
| 4425 // Integer ALU reg-imm operaion | |
| 4426 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4427 single_instruction; | |
| 4428 dst : E(write); | |
| 4429 src1 : R(read); | |
| 4430 IALU : R; | |
| 4431 %} | |
| 4432 | |
| 4433 // Integer ALU reg-reg operation with condition code | |
| 4434 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4435 single_instruction; | |
| 4436 dst : E(write); | |
| 4437 cr : E(write); | |
| 4438 src1 : R(read); | |
| 4439 src2 : R(read); | |
| 4440 IALU : R; | |
| 4441 %} | |
| 4442 | |
| 4443 // Integer ALU reg-imm operation with condition code | |
| 4444 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4445 single_instruction; | |
| 4446 dst : E(write); | |
| 4447 cr : E(write); | |
| 4448 src1 : R(read); | |
| 4449 IALU : R; | |
| 4450 %} | |
| 4451 | |
| 4452 // Integer ALU zero-reg operation | |
| 4453 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4454 single_instruction; | |
| 4455 dst : E(write); | |
| 4456 src2 : R(read); | |
| 4457 IALU : R; | |
| 4458 %} | |
| 4459 | |
| 4460 // Integer ALU zero-reg operation with condition code only | |
| 4461 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4462 single_instruction; | |
| 4463 cr : E(write); | |
| 4464 src : R(read); | |
| 4465 IALU : R; | |
| 4466 %} | |
| 4467 | |
| 4468 // Integer ALU reg-reg operation with condition code only | |
| 4469 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4470 single_instruction; | |
| 4471 cr : E(write); | |
| 4472 src1 : R(read); | |
| 4473 src2 : R(read); | |
| 4474 IALU : R; | |
| 4475 %} | |
| 4476 | |
| 4477 // Integer ALU reg-imm operation with condition code only | |
| 4478 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4479 single_instruction; | |
| 4480 cr : E(write); | |
| 4481 src1 : R(read); | |
| 4482 IALU : R; | |
| 4483 %} | |
| 4484 | |
| 4485 // Integer ALU reg-reg-zero operation with condition code only | |
| 4486 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4487 single_instruction; | |
| 4488 cr : E(write); | |
| 4489 src1 : R(read); | |
| 4490 src2 : R(read); | |
| 4491 IALU : R; | |
| 4492 %} | |
| 4493 | |
| 4494 // Integer ALU reg-imm-zero operation with condition code only | |
| 4495 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4496 single_instruction; | |
| 4497 cr : E(write); | |
| 4498 src1 : R(read); | |
| 4499 IALU : R; | |
| 4500 %} | |
| 4501 | |
| 4502 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4503 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4504 single_instruction; | |
| 4505 cr : E(write); | |
| 4506 src1 : E(write); | |
| 4507 src1 : R(read); | |
| 4508 src2 : R(read); | |
| 4509 IALU : R; | |
| 4510 %} | |
| 4511 | |
| 4512 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4513 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4514 single_instruction; | |
| 4515 cr : E(write); | |
| 4516 src1 : E(write); | |
| 4517 src1 : R(read); | |
| 4518 IALU : R; | |
| 4519 %} | |
| 4520 | |
| 4521 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4522 multiple_bundles; | |
| 4523 dst : E(write)+4; | |
| 4524 cr : E(write); | |
| 4525 src1 : R(read); | |
| 4526 src2 : R(read); | |
| 4527 IALU : R(3); | |
| 4528 BR : R(2); | |
| 4529 %} | |
| 4530 | |
| 4531 // Integer ALU operation | |
| 4532 pipe_class ialu_none(iRegI dst) %{ | |
| 4533 single_instruction; | |
| 4534 dst : E(write); | |
| 4535 IALU : R; | |
| 4536 %} | |
| 4537 | |
| 4538 // Integer ALU reg operation | |
| 4539 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4540 single_instruction; may_have_no_code; | |
| 4541 dst : E(write); | |
| 4542 src : R(read); | |
| 4543 IALU : R; | |
| 4544 %} | |
| 4545 | |
| 4546 // Integer ALU reg conditional operation | |
| 4547 // This instruction has a 1 cycle stall, and cannot execute | |
| 4548 // in the same cycle as the instruction setting the condition | |
| 4549 // code. We kludge this by pretending to read the condition code | |
| 4550 // 1 cycle earlier, and by marking the functional units as busy | |
| 4551 // for 2 cycles with the result available 1 cycle later than | |
| 4552 // is really the case. | |
| 4553 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4554 single_instruction; | |
| 4555 op2_out : C(write); | |
| 4556 op1 : R(read); | |
| 4557 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4558 BR : R(2); | |
| 4559 MS : R(2); | |
| 4560 %} | |
| 4561 | |
| 4562 #ifdef _LP64 | |
| 4563 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4564 instruction_count(1); multiple_bundles; | |
| 4565 dst : C(write)+1; | |
| 4566 src : R(read)+1; | |
| 4567 IALU : R(1); | |
| 4568 BR : E(2); | |
| 4569 MS : E(2); | |
| 4570 %} | |
| 4571 #endif | |
| 4572 | |
| 4573 // Integer ALU reg operation | |
| 4574 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4575 single_instruction; may_have_no_code; | |
| 4576 dst : E(write); | |
| 4577 src : R(read); | |
| 4578 IALU : R; | |
| 4579 %} | |
| 4580 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4581 single_instruction; may_have_no_code; | |
| 4582 dst : E(write); | |
| 4583 src : R(read); | |
| 4584 IALU : R; | |
| 4585 %} | |
| 4586 | |
| 4587 // Two integer ALU reg operations | |
| 4588 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4589 instruction_count(2); | |
| 4590 dst : E(write); | |
| 4591 src : R(read); | |
| 4592 A0 : R; | |
| 4593 A1 : R; | |
| 4594 %} | |
| 4595 | |
| 4596 // Two integer ALU reg operations | |
| 4597 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4598 instruction_count(2); may_have_no_code; | |
| 4599 dst : E(write); | |
| 4600 src : R(read); | |
| 4601 A0 : R; | |
| 4602 A1 : R; | |
| 4603 %} | |
| 4604 | |
| 4605 // Integer ALU imm operation | |
| 4606 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4607 single_instruction; | |
| 4608 dst : E(write); | |
| 4609 IALU : R; | |
| 4610 %} | |
| 4611 | |
| 4612 // Integer ALU reg-reg with carry operation | |
| 4613 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4614 single_instruction; | |
| 4615 dst : E(write); | |
| 4616 src1 : R(read); | |
| 4617 src2 : R(read); | |
| 4618 IALU : R; | |
| 4619 %} | |
| 4620 | |
| 4621 // Integer ALU cc operation | |
| 4622 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4623 single_instruction; | |
| 4624 dst : E(write); | |
| 4625 cc : R(read); | |
| 4626 IALU : R; | |
| 4627 %} | |
| 4628 | |
| 4629 // Integer ALU cc / second IALU operation | |
| 4630 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4631 instruction_count(1); multiple_bundles; | |
| 4632 dst : E(write)+1; | |
| 4633 src : R(read); | |
| 4634 IALU : R; | |
| 4635 %} | |
| 4636 | |
| 4637 // Integer ALU cc / second IALU operation | |
| 4638 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4639 instruction_count(1); multiple_bundles; | |
| 4640 dst : E(write)+1; | |
| 4641 p : R(read); | |
| 4642 q : R(read); | |
| 4643 IALU : R; | |
| 4644 %} | |
| 4645 | |
| 4646 // Integer ALU hi-lo-reg operation | |
| 4647 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4648 instruction_count(1); multiple_bundles; | |
| 4649 dst : E(write)+1; | |
| 4650 IALU : R(2); | |
| 4651 %} | |
| 4652 | |
| 4653 // Float ALU hi-lo-reg operation (with temp) | |
| 4654 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4655 instruction_count(1); multiple_bundles; | |
| 4656 dst : E(write)+1; | |
| 4657 IALU : R(2); | |
| 4658 %} | |
| 4659 | |
| 4660 // Long Constant | |
| 4661 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4662 instruction_count(2); multiple_bundles; | |
| 4663 dst : E(write)+1; | |
| 4664 IALU : R(2); | |
| 4665 IALU : R(2); | |
| 4666 %} | |
| 4667 | |
| 4668 // Pointer Constant | |
| 4669 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4670 instruction_count(0); multiple_bundles; | |
| 4671 fixed_latency(6); | |
| 4672 %} | |
| 4673 | |
| 4674 // Polling Address | |
| 4675 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4676 #ifdef _LP64 | |
| 4677 instruction_count(0); multiple_bundles; | |
| 4678 fixed_latency(6); | |
| 4679 #else | |
| 4680 dst : E(write); | |
| 4681 IALU : R; | |
| 4682 #endif | |
| 4683 %} | |
| 4684 | |
| 4685 // Long Constant small | |
| 4686 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4687 instruction_count(2); | |
| 4688 dst : E(write); | |
| 4689 IALU : R; | |
| 4690 IALU : R; | |
| 4691 %} | |
| 4692 | |
| 4693 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4694 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4695 instruction_count(1); multiple_bundles; | |
| 4696 src : R(read); | |
| 4697 dst : M(write)+1; | |
| 4698 IALU : R; | |
| 4699 MS : E; | |
| 4700 %} | |
| 4701 | |
| 4702 // Integer ALU nop operation | |
| 4703 pipe_class ialu_nop() %{ | |
| 4704 single_instruction; | |
| 4705 IALU : R; | |
| 4706 %} | |
| 4707 | |
| 4708 // Integer ALU nop operation | |
| 4709 pipe_class ialu_nop_A0() %{ | |
| 4710 single_instruction; | |
| 4711 A0 : R; | |
| 4712 %} | |
| 4713 | |
| 4714 // Integer ALU nop operation | |
| 4715 pipe_class ialu_nop_A1() %{ | |
| 4716 single_instruction; | |
| 4717 A1 : R; | |
| 4718 %} | |
| 4719 | |
| 4720 // Integer Multiply reg-reg operation | |
| 4721 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4722 single_instruction; | |
| 4723 dst : E(write); | |
| 4724 src1 : R(read); | |
| 4725 src2 : R(read); | |
| 4726 MS : R(5); | |
| 4727 %} | |
| 4728 | |
| 4729 // Integer Multiply reg-imm operation | |
| 4730 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4731 single_instruction; | |
| 4732 dst : E(write); | |
| 4733 src1 : R(read); | |
| 4734 MS : R(5); | |
| 4735 %} | |
| 4736 | |
| 4737 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4738 single_instruction; | |
| 4739 dst : E(write)+4; | |
| 4740 src1 : R(read); | |
| 4741 src2 : R(read); | |
| 4742 MS : R(6); | |
| 4743 %} | |
| 4744 | |
| 4745 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4746 single_instruction; | |
| 4747 dst : E(write)+4; | |
| 4748 src1 : R(read); | |
| 4749 MS : R(6); | |
| 4750 %} | |
| 4751 | |
| 4752 // Integer Divide reg-reg | |
| 4753 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4754 instruction_count(1); multiple_bundles; | |
| 4755 dst : E(write); | |
| 4756 temp : E(write); | |
| 4757 src1 : R(read); | |
| 4758 src2 : R(read); | |
| 4759 temp : R(read); | |
| 4760 MS : R(38); | |
| 4761 %} | |
| 4762 | |
| 4763 // Integer Divide reg-imm | |
| 4764 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4765 instruction_count(1); multiple_bundles; | |
| 4766 dst : E(write); | |
| 4767 temp : E(write); | |
| 4768 src1 : R(read); | |
| 4769 temp : R(read); | |
| 4770 MS : R(38); | |
| 4771 %} | |
| 4772 | |
| 4773 // Long Divide | |
| 4774 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4775 dst : E(write)+71; | |
| 4776 src1 : R(read); | |
| 4777 src2 : R(read)+1; | |
| 4778 MS : R(70); | |
| 4779 %} | |
| 4780 | |
| 4781 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4782 dst : E(write)+71; | |
| 4783 src1 : R(read); | |
| 4784 MS : R(70); | |
| 4785 %} | |
| 4786 | |
| 4787 // Floating Point Add Float | |
| 4788 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4789 single_instruction; | |
| 4790 dst : X(write); | |
| 4791 src1 : E(read); | |
| 4792 src2 : E(read); | |
| 4793 FA : R; | |
| 4794 %} | |
| 4795 | |
| 4796 // Floating Point Add Double | |
| 4797 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4798 single_instruction; | |
| 4799 dst : X(write); | |
| 4800 src1 : E(read); | |
| 4801 src2 : E(read); | |
| 4802 FA : R; | |
| 4803 %} | |
| 4804 | |
| 4805 // Floating Point Conditional Move based on integer flags | |
| 4806 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4807 single_instruction; | |
| 4808 dst : X(write); | |
| 4809 src : E(read); | |
| 4810 cr : R(read); | |
| 4811 FA : R(2); | |
| 4812 BR : R(2); | |
| 4813 %} | |
| 4814 | |
| 4815 // Floating Point Conditional Move based on integer flags | |
| 4816 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4817 single_instruction; | |
| 4818 dst : X(write); | |
| 4819 src : E(read); | |
| 4820 cr : R(read); | |
| 4821 FA : R(2); | |
| 4822 BR : R(2); | |
| 4823 %} | |
| 4824 | |
| 4825 // Floating Point Multiply Float | |
| 4826 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4827 single_instruction; | |
| 4828 dst : X(write); | |
| 4829 src1 : E(read); | |
| 4830 src2 : E(read); | |
| 4831 FM : R; | |
| 4832 %} | |
| 4833 | |
| 4834 // Floating Point Multiply Double | |
| 4835 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4836 single_instruction; | |
| 4837 dst : X(write); | |
| 4838 src1 : E(read); | |
| 4839 src2 : E(read); | |
| 4840 FM : R; | |
| 4841 %} | |
| 4842 | |
| 4843 // Floating Point Divide Float | |
| 4844 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4845 single_instruction; | |
| 4846 dst : X(write); | |
| 4847 src1 : E(read); | |
| 4848 src2 : E(read); | |
| 4849 FM : R; | |
| 4850 FDIV : C(14); | |
| 4851 %} | |
| 4852 | |
| 4853 // Floating Point Divide Double | |
| 4854 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4855 single_instruction; | |
| 4856 dst : X(write); | |
| 4857 src1 : E(read); | |
| 4858 src2 : E(read); | |
| 4859 FM : R; | |
| 4860 FDIV : C(17); | |
| 4861 %} | |
| 4862 | |
| 4863 // Floating Point Move/Negate/Abs Float | |
| 4864 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4865 single_instruction; | |
| 4866 dst : W(write); | |
| 4867 src : E(read); | |
| 4868 FA : R(1); | |
| 4869 %} | |
| 4870 | |
| 4871 // Floating Point Move/Negate/Abs Double | |
| 4872 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4873 single_instruction; | |
| 4874 dst : W(write); | |
| 4875 src : E(read); | |
| 4876 FA : R; | |
| 4877 %} | |
| 4878 | |
| 4879 // Floating Point Convert F->D | |
| 4880 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4881 single_instruction; | |
| 4882 dst : X(write); | |
| 4883 src : E(read); | |
| 4884 FA : R; | |
| 4885 %} | |
| 4886 | |
| 4887 // Floating Point Convert I->D | |
| 4888 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4889 single_instruction; | |
| 4890 dst : X(write); | |
| 4891 src : E(read); | |
| 4892 FA : R; | |
| 4893 %} | |
| 4894 | |
| 4895 // Floating Point Convert LHi->D | |
| 4896 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4897 single_instruction; | |
| 4898 dst : X(write); | |
| 4899 src : E(read); | |
| 4900 FA : R; | |
| 4901 %} | |
| 4902 | |
| 4903 // Floating Point Convert L->D | |
| 4904 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4905 single_instruction; | |
| 4906 dst : X(write); | |
| 4907 src : E(read); | |
| 4908 FA : R; | |
| 4909 %} | |
| 4910 | |
| 4911 // Floating Point Convert L->F | |
| 4912 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4913 single_instruction; | |
| 4914 dst : X(write); | |
| 4915 src : E(read); | |
| 4916 FA : R; | |
| 4917 %} | |
| 4918 | |
| 4919 // Floating Point Convert D->F | |
| 4920 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4921 single_instruction; | |
| 4922 dst : X(write); | |
| 4923 src : E(read); | |
| 4924 FA : R; | |
| 4925 %} | |
| 4926 | |
| 4927 // Floating Point Convert I->L | |
| 4928 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4929 single_instruction; | |
| 4930 dst : X(write); | |
| 4931 src : E(read); | |
| 4932 FA : R; | |
| 4933 %} | |
| 4934 | |
| 4935 // Floating Point Convert D->F | |
| 4936 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4937 instruction_count(1); multiple_bundles; | |
| 4938 dst : X(write)+6; | |
| 4939 src : E(read); | |
| 4940 FA : R; | |
| 4941 %} | |
| 4942 | |
| 4943 // Floating Point Convert D->L | |
| 4944 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4945 instruction_count(1); multiple_bundles; | |
| 4946 dst : X(write)+6; | |
| 4947 src : E(read); | |
| 4948 FA : R; | |
| 4949 %} | |
| 4950 | |
| 4951 // Floating Point Convert F->I | |
| 4952 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4953 instruction_count(1); multiple_bundles; | |
| 4954 dst : X(write)+6; | |
| 4955 src : E(read); | |
| 4956 FA : R; | |
| 4957 %} | |
| 4958 | |
| 4959 // Floating Point Convert F->L | |
| 4960 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4961 instruction_count(1); multiple_bundles; | |
| 4962 dst : X(write)+6; | |
| 4963 src : E(read); | |
| 4964 FA : R; | |
| 4965 %} | |
| 4966 | |
| 4967 // Floating Point Convert I->F | |
| 4968 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4969 single_instruction; | |
| 4970 dst : X(write); | |
| 4971 src : E(read); | |
| 4972 FA : R; | |
| 4973 %} | |
| 4974 | |
| 4975 // Floating Point Compare | |
| 4976 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4977 single_instruction; | |
| 4978 cr : X(write); | |
| 4979 src1 : E(read); | |
| 4980 src2 : E(read); | |
| 4981 FA : R; | |
| 4982 %} | |
| 4983 | |
| 4984 // Floating Point Compare | |
| 4985 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 4986 single_instruction; | |
| 4987 cr : X(write); | |
| 4988 src1 : E(read); | |
| 4989 src2 : E(read); | |
| 4990 FA : R; | |
| 4991 %} | |
| 4992 | |
| 4993 // Floating Add Nop | |
| 4994 pipe_class fadd_nop() %{ | |
| 4995 single_instruction; | |
| 4996 FA : R; | |
| 4997 %} | |
| 4998 | |
| 4999 // Integer Store to Memory | |
| 5000 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5001 single_instruction; | |
| 5002 mem : R(read); | |
| 5003 src : C(read); | |
| 5004 MS : R; | |
| 5005 %} | |
| 5006 | |
| 5007 // Integer Store to Memory | |
| 5008 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5009 single_instruction; | |
| 5010 mem : R(read); | |
| 5011 src : C(read); | |
| 5012 MS : R; | |
| 5013 %} | |
| 5014 | |
| 5015 // Integer Store Zero to Memory | |
| 5016 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5017 single_instruction; | |
| 5018 mem : R(read); | |
| 5019 MS : R; | |
| 5020 %} | |
| 5021 | |
| 5022 // Special Stack Slot Store | |
| 5023 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5024 single_instruction; | |
| 5025 stkSlot : R(read); | |
| 5026 src : C(read); | |
| 5027 MS : R; | |
| 5028 %} | |
| 5029 | |
| 5030 // Special Stack Slot Store | |
| 5031 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5032 instruction_count(2); multiple_bundles; | |
| 5033 stkSlot : R(read); | |
| 5034 src : C(read); | |
| 5035 MS : R(2); | |
| 5036 %} | |
| 5037 | |
| 5038 // Float Store | |
| 5039 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5040 single_instruction; | |
| 5041 mem : R(read); | |
| 5042 src : C(read); | |
| 5043 MS : R; | |
| 5044 %} | |
| 5045 | |
| 5046 // Float Store | |
| 5047 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5048 single_instruction; | |
| 5049 mem : R(read); | |
| 5050 MS : R; | |
| 5051 %} | |
| 5052 | |
| 5053 // Double Store | |
| 5054 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5055 instruction_count(1); | |
| 5056 mem : R(read); | |
| 5057 src : C(read); | |
| 5058 MS : R; | |
| 5059 %} | |
| 5060 | |
| 5061 // Double Store | |
| 5062 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5063 single_instruction; | |
| 5064 mem : R(read); | |
| 5065 MS : R; | |
| 5066 %} | |
| 5067 | |
| 5068 // Special Stack Slot Float Store | |
| 5069 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5070 single_instruction; | |
| 5071 stkSlot : R(read); | |
| 5072 src : C(read); | |
| 5073 MS : R; | |
| 5074 %} | |
| 5075 | |
| 5076 // Special Stack Slot Double Store | |
| 5077 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5078 single_instruction; | |
| 5079 stkSlot : R(read); | |
| 5080 src : C(read); | |
| 5081 MS : R; | |
| 5082 %} | |
| 5083 | |
| 5084 // Integer Load (when sign bit propagation not needed) | |
| 5085 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5086 single_instruction; | |
| 5087 mem : R(read); | |
| 5088 dst : C(write); | |
| 5089 MS : R; | |
| 5090 %} | |
| 5091 | |
| 5092 // Integer Load from stack operand | |
| 5093 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5094 single_instruction; | |
| 5095 mem : R(read); | |
| 5096 dst : C(write); | |
| 5097 MS : R; | |
| 5098 %} | |
| 5099 | |
| 5100 // Integer Load (when sign bit propagation or masking is needed) | |
| 5101 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5102 single_instruction; | |
| 5103 mem : R(read); | |
| 5104 dst : M(write); | |
| 5105 MS : R; | |
| 5106 %} | |
| 5107 | |
| 5108 // Float Load | |
| 5109 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5110 single_instruction; | |
| 5111 mem : R(read); | |
| 5112 dst : M(write); | |
| 5113 MS : R; | |
| 5114 %} | |
| 5115 | |
| 5116 // Float Load | |
| 5117 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5118 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5119 mem : R(read); | |
| 5120 dst : M(write); | |
| 5121 MS : R; | |
| 5122 %} | |
| 5123 | |
| 5124 // Float Load | |
| 5125 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5126 single_instruction; | |
| 5127 stkSlot : R(read); | |
| 5128 dst : M(write); | |
| 5129 MS : R; | |
| 5130 %} | |
| 5131 | |
| 5132 // Float Load | |
| 5133 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5134 single_instruction; | |
| 5135 stkSlot : R(read); | |
| 5136 dst : M(write); | |
| 5137 MS : R; | |
| 5138 %} | |
| 5139 | |
| 5140 // Memory Nop | |
| 5141 pipe_class mem_nop() %{ | |
| 5142 single_instruction; | |
| 5143 MS : R; | |
| 5144 %} | |
| 5145 | |
| 5146 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5147 single_instruction; | |
| 5148 dst : E(write); | |
| 5149 IALU : R; | |
| 5150 %} | |
| 5151 | |
| 5152 pipe_class loadPollP(iRegP poll) %{ | |
| 5153 single_instruction; | |
| 5154 poll : R(read); | |
| 5155 MS : R; | |
| 5156 %} | |
| 5157 | |
| 5158 pipe_class br(Universe br, label labl) %{ | |
| 5159 single_instruction_with_delay_slot; | |
| 5160 BR : R; | |
| 5161 %} | |
| 5162 | |
| 5163 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5164 single_instruction_with_delay_slot; | |
| 5165 cr : E(read); | |
| 5166 BR : R; | |
| 5167 %} | |
| 5168 | |
| 5169 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5170 single_instruction_with_delay_slot; | |
| 5171 op1 : E(read); | |
| 5172 BR : R; | |
| 5173 MS : R; | |
| 5174 %} | |
| 5175 | |
| 5176 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
| 5177 single_instruction_with_delay_slot; | |
| 5178 cr : E(read); | |
| 5179 BR : R; | |
| 5180 %} | |
| 5181 | |
| 5182 pipe_class br_nop() %{ | |
| 5183 single_instruction; | |
| 5184 BR : R; | |
| 5185 %} | |
| 5186 | |
| 5187 pipe_class simple_call(method meth) %{ | |
| 5188 instruction_count(2); multiple_bundles; force_serialization; | |
| 5189 fixed_latency(100); | |
| 5190 BR : R(1); | |
| 5191 MS : R(1); | |
| 5192 A0 : R(1); | |
| 5193 %} | |
| 5194 | |
| 5195 pipe_class compiled_call(method meth) %{ | |
| 5196 instruction_count(1); multiple_bundles; force_serialization; | |
| 5197 fixed_latency(100); | |
| 5198 MS : R(1); | |
| 5199 %} | |
| 5200 | |
| 5201 pipe_class call(method meth) %{ | |
| 5202 instruction_count(0); multiple_bundles; force_serialization; | |
| 5203 fixed_latency(100); | |
| 5204 %} | |
| 5205 | |
| 5206 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5207 single_instruction; has_delay_slot; | |
| 5208 fixed_latency(100); | |
| 5209 BR : R(1); | |
| 5210 MS : R(1); | |
| 5211 %} | |
| 5212 | |
| 5213 pipe_class ret(Universe ignore) %{ | |
| 5214 single_instruction; has_delay_slot; | |
| 5215 BR : R(1); | |
| 5216 MS : R(1); | |
| 5217 %} | |
| 5218 | |
| 5219 pipe_class ret_poll(g3RegP poll) %{ | |
| 5220 instruction_count(3); has_delay_slot; | |
| 5221 poll : E(read); | |
| 5222 MS : R; | |
| 5223 %} | |
| 5224 | |
| 5225 // The real do-nothing guy | |
| 5226 pipe_class empty( ) %{ | |
| 5227 instruction_count(0); | |
| 5228 %} | |
| 5229 | |
| 5230 pipe_class long_memory_op() %{ | |
| 5231 instruction_count(0); multiple_bundles; force_serialization; | |
| 5232 fixed_latency(25); | |
| 5233 MS : R(1); | |
| 5234 %} | |
| 5235 | |
| 5236 // Check-cast | |
| 5237 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5238 array : R(read); | |
| 5239 match : R(read); | |
| 5240 IALU : R(2); | |
| 5241 BR : R(2); | |
| 5242 MS : R; | |
| 5243 %} | |
| 5244 | |
| 5245 // Convert FPU flags into +1,0,-1 | |
| 5246 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5247 src1 : E(read); | |
| 5248 src2 : E(read); | |
| 5249 dst : E(write); | |
| 5250 FA : R; | |
| 5251 MS : R(2); | |
| 5252 BR : R(2); | |
| 5253 %} | |
| 5254 | |
| 5255 // Compare for p < q, and conditionally add y | |
| 5256 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5257 p : E(read); | |
| 5258 q : E(read); | |
| 5259 y : E(read); | |
| 5260 IALU : R(3) | |
| 5261 %} | |
| 5262 | |
| 5263 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5264 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5265 src2 : E(read); | |
| 5266 srcdst : E(read); | |
| 5267 IALU : R; | |
| 5268 BR : R; | |
| 5269 %} | |
| 5270 | |
| 5271 // Define the class for the Nop node | |
| 5272 define %{ | |
| 5273 MachNop = ialu_nop; | |
| 5274 %} | |
| 5275 | |
| 5276 %} | |
| 5277 | |
| 5278 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5279 | |
| 5280 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5281 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5282 // No match rule to avoid chain rule match. | |
| 5283 effect(DEF dst, USE src); | |
| 5284 ins_cost(MEMORY_REF_COST); | |
| 5285 size(4); | |
| 5286 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5287 opcode(Assembler::ldf_op3); | |
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5288 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5289 ins_pipe(floadF_stk); |
| 5290 %} | |
| 5291 | |
| 5292 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5293 // No match rule to avoid chain rule match. | |
| 5294 effect(DEF dst, USE src); | |
| 5295 ins_cost(MEMORY_REF_COST); | |
| 5296 size(4); | |
| 5297 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5298 opcode(Assembler::lddf_op3); | |
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5299 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5300 ins_pipe(floadD_stk); |
| 5301 %} | |
| 5302 | |
| 5303 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5304 // No match rule to avoid chain rule match. | |
| 5305 effect(DEF dst, USE src); | |
| 5306 ins_cost(MEMORY_REF_COST); | |
| 5307 size(4); | |
| 5308 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5309 opcode(Assembler::stf_op3); | |
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5310 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5311 ins_pipe(fstoreF_stk_reg); |
| 5312 %} | |
| 5313 | |
| 5314 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5315 // No match rule to avoid chain rule match. | |
| 5316 effect(DEF dst, USE src); | |
| 5317 ins_cost(MEMORY_REF_COST); | |
| 5318 size(4); | |
| 5319 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5320 opcode(Assembler::stdf_op3); | |
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5321 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5322 ins_pipe(fstoreD_stk_reg); |
| 5323 %} | |
| 5324 | |
| 5325 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5326 effect(DEF dst, USE src); | |
| 5327 ins_cost(MEMORY_REF_COST*2); | |
| 5328 size(8); | |
| 5329 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5330 "STW R_G0,$dst.lo" %} | |
| 5331 opcode(Assembler::stw_op3); | |
|
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5332 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5333 ins_pipe(lstoreI_stk_reg); |
| 5334 %} | |
| 5335 | |
| 5336 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5337 // No match rule to avoid chain rule match. | |
| 5338 effect(DEF dst, USE src); | |
| 5339 ins_cost(MEMORY_REF_COST); | |
| 5340 size(4); | |
| 5341 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5342 opcode(Assembler::stx_op3); | |
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5343 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5344 ins_pipe(istore_stk_reg); |
| 5345 %} | |
| 5346 | |
| 5347 //---------- Chain stack slots between similar types -------- | |
| 5348 | |
| 5349 // Load integer from stack slot | |
| 5350 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5351 match(Set dst src); | |
| 5352 ins_cost(MEMORY_REF_COST); | |
| 5353 | |
| 5354 size(4); | |
| 5355 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5356 opcode(Assembler::lduw_op3); | |
|
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5357 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5358 ins_pipe(iload_mem); |
| 5359 %} | |
| 5360 | |
| 5361 // Store integer to stack slot | |
| 5362 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5363 match(Set dst src); | |
| 5364 ins_cost(MEMORY_REF_COST); | |
| 5365 | |
| 5366 size(4); | |
| 5367 format %{ "STW $src,$dst\t!stk" %} | |
| 5368 opcode(Assembler::stw_op3); | |
|
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5369 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5370 ins_pipe(istore_mem_reg); |
| 5371 %} | |
| 5372 | |
| 5373 // Load long from stack slot | |
| 5374 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5375 match(Set dst src); | |
| 5376 | |
| 5377 ins_cost(MEMORY_REF_COST); | |
| 5378 size(4); | |
| 5379 format %{ "LDX $src,$dst\t! long" %} | |
| 5380 opcode(Assembler::ldx_op3); | |
|
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5381 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5382 ins_pipe(iload_mem); |
| 5383 %} | |
| 5384 | |
| 5385 // Store long to stack slot | |
| 5386 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5387 match(Set dst src); | |
| 5388 | |
| 5389 ins_cost(MEMORY_REF_COST); | |
| 5390 size(4); | |
| 5391 format %{ "STX $src,$dst\t! long" %} | |
| 5392 opcode(Assembler::stx_op3); | |
|
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5393 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5394 ins_pipe(istore_mem_reg); |
| 5395 %} | |
| 5396 | |
| 5397 #ifdef _LP64 | |
| 5398 // Load pointer from stack slot, 64-bit encoding | |
| 5399 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5400 match(Set dst src); | |
| 5401 ins_cost(MEMORY_REF_COST); | |
| 5402 size(4); | |
| 5403 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5404 opcode(Assembler::ldx_op3); | |
|
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5405 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5406 ins_pipe(iload_mem); |
| 5407 %} | |
| 5408 | |
| 5409 // Store pointer to stack slot | |
| 5410 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5411 match(Set dst src); | |
| 5412 ins_cost(MEMORY_REF_COST); | |
| 5413 size(4); | |
| 5414 format %{ "STX $src,$dst\t!ptr" %} | |
| 5415 opcode(Assembler::stx_op3); | |
|
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5416 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5417 ins_pipe(istore_mem_reg); |
| 5418 %} | |
| 5419 #else // _LP64 | |
| 5420 // Load pointer from stack slot, 32-bit encoding | |
| 5421 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5422 match(Set dst src); | |
| 5423 ins_cost(MEMORY_REF_COST); | |
| 5424 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5425 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
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5426 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5427 ins_pipe(iload_mem); |
| 5428 %} | |
| 5429 | |
| 5430 // Store pointer to stack slot | |
| 5431 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5432 match(Set dst src); | |
| 5433 ins_cost(MEMORY_REF_COST); | |
| 5434 format %{ "STW $src,$dst\t!ptr" %} | |
| 5435 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
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5436 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5437 ins_pipe(istore_mem_reg); |
| 5438 %} | |
| 5439 #endif // _LP64 | |
| 5440 | |
| 5441 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5442 // Nop using the A0 functional unit | |
| 5443 instruct Nop_A0() %{ | |
| 5444 ins_cost(0); | |
| 5445 | |
| 5446 format %{ "NOP ! Alu Pipeline" %} | |
| 5447 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5448 ins_encode( form2_nop() ); | |
| 5449 ins_pipe(ialu_nop_A0); | |
| 5450 %} | |
| 5451 | |
| 5452 // Nop using the A1 functional unit | |
| 5453 instruct Nop_A1( ) %{ | |
| 5454 ins_cost(0); | |
| 5455 | |
| 5456 format %{ "NOP ! Alu Pipeline" %} | |
| 5457 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5458 ins_encode( form2_nop() ); | |
| 5459 ins_pipe(ialu_nop_A1); | |
| 5460 %} | |
| 5461 | |
| 5462 // Nop using the memory functional unit | |
| 5463 instruct Nop_MS( ) %{ | |
| 5464 ins_cost(0); | |
| 5465 | |
| 5466 format %{ "NOP ! Memory Pipeline" %} | |
| 5467 ins_encode( emit_mem_nop ); | |
| 5468 ins_pipe(mem_nop); | |
| 5469 %} | |
| 5470 | |
| 5471 // Nop using the floating add functional unit | |
| 5472 instruct Nop_FA( ) %{ | |
| 5473 ins_cost(0); | |
| 5474 | |
| 5475 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5476 ins_encode( emit_fadd_nop ); | |
| 5477 ins_pipe(fadd_nop); | |
| 5478 %} | |
| 5479 | |
| 5480 // Nop using the branch functional unit | |
| 5481 instruct Nop_BR( ) %{ | |
| 5482 ins_cost(0); | |
| 5483 | |
| 5484 format %{ "NOP ! Branch Pipeline" %} | |
| 5485 ins_encode( emit_br_nop ); | |
| 5486 ins_pipe(br_nop); | |
| 5487 %} | |
| 5488 | |
| 5489 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5490 //----------Load Instructions-------------------------------------------------- | |
| 5491 // Load Byte (8bit signed) | |
| 5492 instruct loadB(iRegI dst, memory mem) %{ | |
| 5493 match(Set dst (LoadB mem)); | |
| 5494 ins_cost(MEMORY_REF_COST); | |
| 5495 | |
| 5496 size(4); | |
| 624 | 5497 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5498 ins_encode %{ |
| 5499 __ ldsb($mem$$Address, $dst$$Register); | |
| 5500 %} | |
| 624 | 5501 ins_pipe(iload_mask_mem); |
| 5502 %} | |
| 5503 | |
| 5504 // Load Byte (8bit signed) into a Long Register | |
| 5505 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5506 match(Set dst (ConvI2L (LoadB mem))); | |
| 5507 ins_cost(MEMORY_REF_COST); | |
| 5508 | |
| 5509 size(4); | |
| 5510 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5511 ins_encode %{ |
| 5512 __ ldsb($mem$$Address, $dst$$Register); | |
| 5513 %} | |
| 0 | 5514 ins_pipe(iload_mask_mem); |
| 5515 %} | |
| 5516 | |
| 624 | 5517 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5518 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5519 match(Set dst (LoadUB mem)); | |
| 0 | 5520 ins_cost(MEMORY_REF_COST); |
| 5521 | |
| 5522 size(4); | |
| 624 | 5523 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5524 ins_encode %{ |
| 5525 __ ldub($mem$$Address, $dst$$Register); | |
| 5526 %} | |
| 824 | 5527 ins_pipe(iload_mem); |
| 624 | 5528 %} |
| 5529 | |
| 5530 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5531 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5532 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5533 ins_cost(MEMORY_REF_COST); | |
| 5534 | |
| 5535 size(4); | |
| 5536 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5537 ins_encode %{ |
| 5538 __ ldub($mem$$Address, $dst$$Register); | |
| 5539 %} | |
| 824 | 5540 ins_pipe(iload_mem); |
| 5541 %} | |
| 5542 | |
| 5543 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5544 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5545 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5546 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5547 | |
| 5548 size(2*4); | |
| 5549 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5550 "AND $dst,$mask,$dst" %} | |
| 5551 ins_encode %{ | |
| 5552 __ ldub($mem$$Address, $dst$$Register); | |
| 5553 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5554 %} | |
| 5555 ins_pipe(iload_mem); | |
| 0 | 5556 %} |
| 5557 | |
| 624 | 5558 // Load Short (16bit signed) |
| 5559 instruct loadS(iRegI dst, memory mem) %{ | |
| 5560 match(Set dst (LoadS mem)); | |
| 5561 ins_cost(MEMORY_REF_COST); | |
| 5562 | |
| 5563 size(4); | |
| 5564 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5565 ins_encode %{ |
| 5566 __ ldsh($mem$$Address, $dst$$Register); | |
| 5567 %} | |
| 624 | 5568 ins_pipe(iload_mask_mem); |
| 5569 %} | |
| 5570 | |
| 785 | 5571 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5572 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5573 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5574 ins_cost(MEMORY_REF_COST); | |
| 5575 | |
| 5576 size(4); | |
| 5577 | |
| 5578 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5579 ins_encode %{ | |
| 5580 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5581 %} | |
| 5582 ins_pipe(iload_mask_mem); | |
| 5583 %} | |
| 5584 | |
| 624 | 5585 // Load Short (16bit signed) into a Long Register |
| 5586 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5587 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5588 ins_cost(MEMORY_REF_COST); |
| 5589 | |
| 5590 size(4); | |
| 624 | 5591 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5592 ins_encode %{ |
| 5593 __ ldsh($mem$$Address, $dst$$Register); | |
| 5594 %} | |
| 624 | 5595 ins_pipe(iload_mask_mem); |
| 5596 %} | |
| 5597 | |
| 5598 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5599 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5600 match(Set dst (LoadUS mem)); | |
| 5601 ins_cost(MEMORY_REF_COST); | |
| 5602 | |
| 5603 size(4); | |
| 5604 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5605 ins_encode %{ |
| 5606 __ lduh($mem$$Address, $dst$$Register); | |
| 5607 %} | |
| 824 | 5608 ins_pipe(iload_mem); |
| 0 | 5609 %} |
| 5610 | |
| 785 | 5611 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5612 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5613 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5614 ins_cost(MEMORY_REF_COST); | |
| 5615 | |
| 5616 size(4); | |
| 5617 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5618 ins_encode %{ | |
| 5619 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5620 %} | |
| 5621 ins_pipe(iload_mask_mem); | |
| 5622 %} | |
| 5623 | |
|
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diff
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|
5624 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5625 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5626 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5627 ins_cost(MEMORY_REF_COST); |
| 5628 | |
| 5629 size(4); | |
| 624 | 5630 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5631 ins_encode %{ |
| 5632 __ lduh($mem$$Address, $dst$$Register); | |
| 5633 %} | |
| 824 | 5634 ins_pipe(iload_mem); |
| 5635 %} | |
| 5636 | |
| 5637 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5638 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5639 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5640 ins_cost(MEMORY_REF_COST); | |
| 5641 | |
| 5642 size(4); | |
| 5643 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5644 ins_encode %{ | |
| 5645 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5646 %} | |
| 5647 ins_pipe(iload_mem); | |
| 5648 %} | |
| 5649 | |
| 5650 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5651 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5652 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5653 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5654 | |
| 5655 size(2*4); | |
| 5656 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5657 "AND $dst,$mask,$dst" %} | |
| 5658 ins_encode %{ | |
| 5659 Register Rdst = $dst$$Register; | |
| 5660 __ lduh($mem$$Address, Rdst); | |
| 5661 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5662 %} | |
| 5663 ins_pipe(iload_mem); | |
| 5664 %} | |
| 5665 | |
| 5666 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5667 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5668 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5669 effect(TEMP dst, TEMP tmp); | |
| 5670 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5671 | |
|
951
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diff
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|
5672 size((3+1)*4); // set may use two instructions. |
| 824 | 5673 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5674 "SET $mask,$tmp\n\t" | |
| 5675 "AND $dst,$tmp,$dst" %} | |
| 5676 ins_encode %{ | |
| 5677 Register Rdst = $dst$$Register; | |
| 5678 Register Rtmp = $tmp$$Register; | |
| 5679 __ lduh($mem$$Address, Rdst); | |
| 5680 __ set($mask$$constant, Rtmp); | |
| 5681 __ and3(Rdst, Rtmp, Rdst); | |
| 5682 %} | |
| 5683 ins_pipe(iload_mem); | |
| 0 | 5684 %} |
| 5685 | |
| 5686 // Load Integer | |
| 5687 instruct loadI(iRegI dst, memory mem) %{ | |
| 5688 match(Set dst (LoadI mem)); | |
| 5689 ins_cost(MEMORY_REF_COST); | |
| 624 | 5690 |
| 5691 size(4); | |
| 5692 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5693 ins_encode %{ |
| 5694 __ lduw($mem$$Address, $dst$$Register); | |
| 5695 %} | |
| 624 | 5696 ins_pipe(iload_mem); |
| 5697 %} | |
| 5698 | |
| 785 | 5699 // Load Integer to Byte (8 bit signed) |
| 5700 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5701 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5702 ins_cost(MEMORY_REF_COST); | |
| 5703 | |
| 5704 size(4); | |
| 5705 | |
| 5706 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5707 ins_encode %{ | |
| 5708 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5709 %} | |
| 5710 ins_pipe(iload_mask_mem); | |
| 5711 %} | |
| 5712 | |
| 5713 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5714 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5715 match(Set dst (AndI (LoadI mem) mask)); | |
| 5716 ins_cost(MEMORY_REF_COST); | |
| 5717 | |
| 5718 size(4); | |
| 5719 | |
| 5720 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5721 ins_encode %{ | |
| 5722 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5723 %} | |
| 5724 ins_pipe(iload_mask_mem); | |
| 5725 %} | |
| 5726 | |
| 5727 // Load Integer to Short (16 bit signed) | |
| 5728 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5729 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5730 ins_cost(MEMORY_REF_COST); | |
| 5731 | |
| 5732 size(4); | |
| 5733 | |
| 5734 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5735 ins_encode %{ | |
| 5736 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5737 %} | |
| 5738 ins_pipe(iload_mask_mem); | |
| 5739 %} | |
| 5740 | |
| 5741 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5742 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5743 match(Set dst (AndI (LoadI mem) mask)); | |
| 5744 ins_cost(MEMORY_REF_COST); | |
| 5745 | |
| 5746 size(4); | |
| 5747 | |
| 5748 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5749 ins_encode %{ | |
| 5750 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5751 %} | |
| 5752 ins_pipe(iload_mask_mem); | |
| 5753 %} | |
| 5754 | |
| 624 | 5755 // Load Integer into a Long Register |
| 5756 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5757 match(Set dst (ConvI2L (LoadI mem))); | |
| 5758 ins_cost(MEMORY_REF_COST); | |
| 5759 | |
| 5760 size(4); | |
| 5761 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5762 ins_encode %{ |
| 5763 __ ldsw($mem$$Address, $dst$$Register); | |
| 5764 %} | |
| 824 | 5765 ins_pipe(iload_mask_mem); |
| 5766 %} | |
| 5767 | |
| 5768 // Load Integer with mask 0xFF into a Long Register | |
| 5769 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5770 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5771 ins_cost(MEMORY_REF_COST); | |
| 5772 | |
| 5773 size(4); | |
| 5774 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5775 ins_encode %{ | |
| 5776 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5777 %} | |
| 5778 ins_pipe(iload_mem); | |
| 5779 %} | |
| 5780 | |
| 5781 // Load Integer with mask 0xFFFF into a Long Register | |
| 5782 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5783 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5784 ins_cost(MEMORY_REF_COST); | |
| 5785 | |
| 5786 size(4); | |
| 5787 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5788 ins_encode %{ | |
| 5789 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5790 %} | |
| 5791 ins_pipe(iload_mem); | |
| 5792 %} | |
| 5793 | |
| 5794 // Load Integer with a 13-bit mask into a Long Register | |
| 5795 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5796 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5797 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5798 | |
| 5799 size(2*4); | |
| 5800 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5801 "AND $dst,$mask,$dst" %} | |
| 5802 ins_encode %{ | |
| 5803 Register Rdst = $dst$$Register; | |
| 5804 __ lduw($mem$$Address, Rdst); | |
| 5805 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5806 %} | |
| 5807 ins_pipe(iload_mem); | |
| 5808 %} | |
| 5809 | |
| 5810 // Load Integer with a 32-bit mask into a Long Register | |
| 5811 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5812 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5813 effect(TEMP dst, TEMP tmp); | |
| 5814 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5815 | |
|
951
1fbd5d696bf4
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diff
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|
5816 size((3+1)*4); // set may use two instructions. |
| 824 | 5817 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5818 "SET $mask,$tmp\n\t" | |
| 5819 "AND $dst,$tmp,$dst" %} | |
| 5820 ins_encode %{ | |
| 5821 Register Rdst = $dst$$Register; | |
| 5822 Register Rtmp = $tmp$$Register; | |
| 5823 __ lduw($mem$$Address, Rdst); | |
| 5824 __ set($mask$$constant, Rtmp); | |
| 5825 __ and3(Rdst, Rtmp, Rdst); | |
| 5826 %} | |
| 624 | 5827 ins_pipe(iload_mem); |
| 5828 %} | |
| 5829 | |
| 5830 // Load Unsigned Integer into a Long Register | |
| 5831 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5832 match(Set dst (LoadUI2L mem)); | |
| 5833 ins_cost(MEMORY_REF_COST); | |
| 5834 | |
| 5835 size(4); | |
| 5836 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5837 ins_encode %{ |
| 5838 __ lduw($mem$$Address, $dst$$Register); | |
| 5839 %} | |
| 0 | 5840 ins_pipe(iload_mem); |
| 5841 %} | |
| 5842 | |
| 5843 // Load Long - aligned | |
| 5844 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5845 match(Set dst (LoadL mem)); | |
| 5846 ins_cost(MEMORY_REF_COST); | |
| 624 | 5847 |
| 0 | 5848 size(4); |
| 5849 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5850 ins_encode %{ |
| 5851 __ ldx($mem$$Address, $dst$$Register); | |
| 5852 %} | |
| 0 | 5853 ins_pipe(iload_mem); |
| 5854 %} | |
| 5855 | |
| 5856 // Load Long - UNaligned | |
| 5857 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5858 match(Set dst (LoadL_unaligned mem)); | |
| 5859 effect(KILL tmp); | |
| 5860 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5861 size(16); | |
| 5862 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5863 "\tLDUW $mem ,$dst\n" | |
| 5864 "\tSLLX #32, $dst, $dst\n" | |
| 5865 "\tOR $dst, R_O7, $dst" %} | |
| 5866 opcode(Assembler::lduw_op3); | |
|
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235
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|
5867 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5868 ins_pipe(iload_mem); |
| 5869 %} | |
| 5870 | |
| 5871 // Load Aligned Packed Byte into a Double Register | |
| 5872 instruct loadA8B(regD dst, memory mem) %{ | |
| 5873 match(Set dst (Load8B mem)); | |
| 5874 ins_cost(MEMORY_REF_COST); | |
| 5875 size(4); | |
| 5876 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5877 opcode(Assembler::lddf_op3); | |
|
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|
5878 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5879 ins_pipe(floadD_mem); |
| 5880 %} | |
| 5881 | |
| 5882 // Load Aligned Packed Char into a Double Register | |
| 5883 instruct loadA4C(regD dst, memory mem) %{ | |
| 5884 match(Set dst (Load4C mem)); | |
| 5885 ins_cost(MEMORY_REF_COST); | |
| 5886 size(4); | |
| 5887 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5888 opcode(Assembler::lddf_op3); | |
|
415
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|
5889 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5890 ins_pipe(floadD_mem); |
| 5891 %} | |
| 5892 | |
| 5893 // Load Aligned Packed Short into a Double Register | |
| 5894 instruct loadA4S(regD dst, memory mem) %{ | |
| 5895 match(Set dst (Load4S mem)); | |
| 5896 ins_cost(MEMORY_REF_COST); | |
| 5897 size(4); | |
| 5898 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5899 opcode(Assembler::lddf_op3); | |
|
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235
diff
changeset
|
5900 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5901 ins_pipe(floadD_mem); |
| 5902 %} | |
| 5903 | |
| 5904 // Load Aligned Packed Int into a Double Register | |
| 5905 instruct loadA2I(regD dst, memory mem) %{ | |
| 5906 match(Set dst (Load2I mem)); | |
| 5907 ins_cost(MEMORY_REF_COST); | |
| 5908 size(4); | |
| 5909 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5910 opcode(Assembler::lddf_op3); | |
|
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235
diff
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|
5911 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5912 ins_pipe(floadD_mem); |
| 5913 %} | |
| 5914 | |
| 5915 // Load Range | |
| 5916 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5917 match(Set dst (LoadRange mem)); | |
| 5918 ins_cost(MEMORY_REF_COST); | |
| 5919 | |
| 5920 size(4); | |
| 5921 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5922 opcode(Assembler::lduw_op3); | |
|
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|
5923 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5924 ins_pipe(iload_mem); |
| 5925 %} | |
| 5926 | |
| 5927 // Load Integer into %f register (for fitos/fitod) | |
| 5928 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5929 match(Set dst (LoadI mem)); | |
| 5930 ins_cost(MEMORY_REF_COST); | |
| 5931 size(4); | |
| 5932 | |
| 5933 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5934 opcode(Assembler::ldf_op3); | |
|
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|
5935 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5936 ins_pipe(floadF_mem); |
| 5937 %} | |
| 5938 | |
| 5939 // Load Pointer | |
| 5940 instruct loadP(iRegP dst, memory mem) %{ | |
| 5941 match(Set dst (LoadP mem)); | |
| 5942 ins_cost(MEMORY_REF_COST); | |
| 5943 size(4); | |
| 5944 | |
| 5945 #ifndef _LP64 | |
| 5946 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5947 ins_encode %{ |
| 5948 __ lduw($mem$$Address, $dst$$Register); | |
| 5949 %} | |
| 0 | 5950 #else |
| 5951 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5952 ins_encode %{ |
| 5953 __ ldx($mem$$Address, $dst$$Register); | |
| 5954 %} | |
| 0 | 5955 #endif |
| 5956 ins_pipe(iload_mem); | |
| 5957 %} | |
| 5958 | |
|
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diff
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|
5959 // Load Compressed Pointer |
|
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|
5960 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5961 match(Set dst (LoadN mem)); |
| 5962 ins_cost(MEMORY_REF_COST); | |
| 5963 size(4); | |
| 5964 | |
| 5965 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5966 ins_encode %{ | |
| 5967 __ lduw($mem$$Address, $dst$$Register); | |
| 5968 %} | |
| 5969 ins_pipe(iload_mem); | |
|
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|
5970 %} |
|
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|
5971 |
| 0 | 5972 // Load Klass Pointer |
| 5973 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5974 match(Set dst (LoadKlass mem)); | |
| 5975 ins_cost(MEMORY_REF_COST); | |
| 5976 size(4); | |
| 5977 | |
| 5978 #ifndef _LP64 | |
| 5979 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 5980 ins_encode %{ |
| 5981 __ lduw($mem$$Address, $dst$$Register); | |
| 5982 %} | |
| 0 | 5983 #else |
| 5984 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 5985 ins_encode %{ |
| 5986 __ ldx($mem$$Address, $dst$$Register); | |
| 5987 %} | |
| 0 | 5988 #endif |
| 5989 ins_pipe(iload_mem); | |
| 5990 %} | |
| 5991 | |
|
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|
5992 // Load narrow Klass Pointer |
|
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|
5993 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
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|
5994 match(Set dst (LoadNKlass mem)); |
|
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|
5995 ins_cost(MEMORY_REF_COST); |
|
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|
5996 size(4); |
|
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|
5997 |
|
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5998 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5999 ins_encode %{ |
| 727 | 6000 __ lduw($mem$$Address, $dst$$Register); |
|
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6001 %} |
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6002 ins_pipe(iload_mem); |
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6003 %} |
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6004 |
| 0 | 6005 // Load Double |
| 6006 instruct loadD(regD dst, memory mem) %{ | |
| 6007 match(Set dst (LoadD mem)); | |
| 6008 ins_cost(MEMORY_REF_COST); | |
| 6009 | |
| 6010 size(4); | |
| 6011 format %{ "LDDF $mem,$dst" %} | |
| 6012 opcode(Assembler::lddf_op3); | |
|
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6013 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6014 ins_pipe(floadD_mem); |
| 6015 %} | |
| 6016 | |
| 6017 // Load Double - UNaligned | |
| 6018 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6019 match(Set dst (LoadD_unaligned mem)); | |
| 6020 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6021 size(8); | |
| 6022 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6023 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6024 opcode(Assembler::ldf_op3); | |
| 6025 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6026 ins_pipe(iload_mem); | |
| 6027 %} | |
| 6028 | |
| 6029 // Load Float | |
| 6030 instruct loadF(regF dst, memory mem) %{ | |
| 6031 match(Set dst (LoadF mem)); | |
| 6032 ins_cost(MEMORY_REF_COST); | |
| 6033 | |
| 6034 size(4); | |
| 6035 format %{ "LDF $mem,$dst" %} | |
| 6036 opcode(Assembler::ldf_op3); | |
|
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6037 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6038 ins_pipe(floadF_mem); |
| 6039 %} | |
| 6040 | |
| 6041 // Load Constant | |
| 6042 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6043 match(Set dst src); | |
| 6044 ins_cost(DEFAULT_COST * 3/2); | |
| 6045 format %{ "SET $src,$dst" %} | |
| 6046 ins_encode( Set32(src, dst) ); | |
| 6047 ins_pipe(ialu_hi_lo_reg); | |
| 6048 %} | |
| 6049 | |
| 6050 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6051 match(Set dst src); | |
| 6052 | |
| 6053 size(4); | |
| 6054 format %{ "MOV $src,$dst" %} | |
| 6055 ins_encode( Set13( src, dst ) ); | |
| 6056 ins_pipe(ialu_imm); | |
| 6057 %} | |
| 6058 | |
| 2008 | 6059 #ifndef _LP64 |
| 6060 instruct loadConP(iRegP dst, immP con) %{ | |
| 6061 match(Set dst con); | |
| 6062 ins_cost(DEFAULT_COST * 3/2); | |
| 6063 format %{ "SET $con,$dst\t!ptr" %} | |
| 6064 ins_encode %{ | |
| 6065 // [RGV] This next line should be generated from ADLC | |
| 6066 if (_opnds[1]->constant_is_oop()) { | |
| 6067 intptr_t val = $con$$constant; | |
| 6068 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6069 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6070 __ set($con$$constant, $dst$$Register); | |
| 6071 } | |
| 6072 %} | |
| 6073 ins_pipe(loadConP); | |
| 6074 %} | |
| 6075 #else | |
| 6076 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6077 match(Set dst con); | |
| 0 | 6078 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6079 format %{ "SET $con,$dst\t! ptr" %} |
| 6080 ins_encode %{ | |
| 6081 // [RGV] This next line should be generated from ADLC | |
| 6082 if (_opnds[1]->constant_is_oop()) { | |
| 6083 intptr_t val = $con$$constant; | |
| 6084 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6085 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6086 __ set($con$$constant, $dst$$Register); | |
| 6087 } | |
| 6088 %} | |
| 0 | 6089 ins_pipe(loadConP); |
| 2008 | 6090 %} |
| 6091 | |
| 6092 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6093 match(Set dst con); | |
| 6094 ins_cost(MEMORY_REF_COST); | |
| 6095 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6096 ins_encode %{ | |
| 6097 __ ld_ptr($constanttablebase, $constantoffset($con), $dst$$Register); | |
| 6098 %} | |
| 6099 ins_pipe(loadConP); | |
| 6100 %} | |
| 6101 #endif // _LP64 | |
| 0 | 6102 |
| 6103 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6104 match(Set dst src); | |
| 6105 | |
| 6106 size(4); | |
| 6107 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6108 ins_encode %{ |
| 6109 __ clr($dst$$Register); | |
| 6110 %} | |
| 0 | 6111 ins_pipe(ialu_imm); |
| 6112 %} | |
| 6113 | |
| 6114 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6115 match(Set dst src); | |
| 6116 ins_cost(DEFAULT_COST); | |
| 6117 format %{ "SET $src,$dst\t!ptr" %} | |
| 6118 ins_encode %{ | |
| 727 | 6119 AddressLiteral polling_page(os::get_polling_page()); |
| 6120 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6121 %} |
| 6122 ins_pipe(loadConP_poll); | |
| 6123 %} | |
| 6124 | |
|
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6125 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6126 match(Set dst src); |
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6127 |
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6128 size(4); |
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6129 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6130 ins_encode %{ |
| 6131 __ clr($dst$$Register); | |
| 6132 %} | |
|
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6133 ins_pipe(ialu_imm); |
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6134 %} |
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6135 |
|
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6136 instruct loadConN(iRegN dst, immN src) %{ |
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6137 match(Set dst src); |
|
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6138 ins_cost(DEFAULT_COST * 3/2); |
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6139 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
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6140 ins_encode %{ |
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6141 Register dst = $dst$$Register; |
|
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6142 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6143 %} |
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6144 ins_pipe(ialu_hi_lo_reg); |
|
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6145 %} |
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6146 |
| 2008 | 6147 // Materialize long value (predicated by immL_cheap). |
| 6148 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6149 match(Set dst con); | |
| 0 | 6150 effect(KILL tmp); |
| 2008 | 6151 ins_cost(DEFAULT_COST * 3); |
| 6152 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6153 ins_encode %{ | |
| 6154 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6155 %} | |
| 6156 ins_pipe(loadConL); | |
| 6157 %} | |
| 6158 | |
| 6159 // Load long value from constant table (predicated by immL_expensive). | |
| 6160 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6161 match(Set dst con); | |
| 6162 ins_cost(MEMORY_REF_COST); | |
| 6163 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6164 ins_encode %{ | |
| 6165 __ ldx($constanttablebase, $constantoffset($con), $dst$$Register); | |
| 6166 %} | |
| 0 | 6167 ins_pipe(loadConL); |
| 6168 %} | |
| 6169 | |
| 6170 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6171 match(Set dst src); | |
| 6172 ins_cost(DEFAULT_COST); | |
| 6173 size(4); | |
| 6174 format %{ "CLR $dst\t! long" %} | |
| 6175 ins_encode( Set13( src, dst ) ); | |
| 6176 ins_pipe(ialu_imm); | |
| 6177 %} | |
| 6178 | |
| 6179 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6180 match(Set dst src); | |
| 6181 ins_cost(DEFAULT_COST * 2); | |
| 6182 | |
| 6183 size(4); | |
| 6184 format %{ "MOV $src,$dst\t! long" %} | |
| 6185 ins_encode( Set13( src, dst ) ); | |
| 6186 ins_pipe(ialu_imm); | |
| 6187 %} | |
| 6188 | |
| 2008 | 6189 instruct loadConF(regF dst, immF con) %{ |
| 6190 match(Set dst con); | |
| 6191 size(4); | |
| 6192 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} | |
| 727 | 6193 ins_encode %{ |
| 2008 | 6194 __ ldf(FloatRegisterImpl::S, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
| 727 | 6195 %} |
| 0 | 6196 ins_pipe(loadConFD); |
| 6197 %} | |
| 6198 | |
| 2008 | 6199 instruct loadConD(regD dst, immD con) %{ |
| 6200 match(Set dst con); | |
| 6201 size(4); | |
| 6202 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} | |
| 727 | 6203 ins_encode %{ |
|
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6204 // XXX This is a quick fix for 6833573. |
| 2008 | 6205 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
| 6206 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), as_DoubleFloatRegister($dst$$reg)); | |
| 727 | 6207 %} |
| 0 | 6208 ins_pipe(loadConFD); |
| 6209 %} | |
| 6210 | |
| 6211 // Prefetch instructions. | |
| 6212 // Must be safe to execute with invalid address (cannot fault). | |
| 6213 | |
| 6214 instruct prefetchr( memory mem ) %{ | |
| 6215 match( PrefetchRead mem ); | |
| 6216 ins_cost(MEMORY_REF_COST); | |
| 6217 | |
| 6218 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6219 opcode(Assembler::prefetch_op3); | |
| 6220 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6221 ins_pipe(iload_mem); | |
| 6222 %} | |
| 6223 | |
| 6224 instruct prefetchw( memory mem ) %{ | |
|
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6225 predicate(AllocatePrefetchStyle != 3 ); |
| 0 | 6226 match( PrefetchWrite mem ); |
| 6227 ins_cost(MEMORY_REF_COST); | |
| 6228 | |
| 6229 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6230 opcode(Assembler::prefetch_op3); | |
| 6231 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6232 ins_pipe(iload_mem); | |
| 6233 %} | |
| 6234 | |
|
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6235 // Use BIS instruction to prefetch. |
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6236 instruct prefetchw_bis( memory mem ) %{ |
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6237 predicate(AllocatePrefetchStyle == 3); |
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6238 match( PrefetchWrite mem ); |
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6239 ins_cost(MEMORY_REF_COST); |
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6240 |
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6241 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
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6242 ins_encode %{ |
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6243 Register base = as_Register($mem$$base); |
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6244 int disp = $mem$$disp; |
|
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6245 if (disp != 0) { |
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6246 __ add(base, AllocatePrefetchStepSize, base); |
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6247 } |
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6248 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
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6249 %} |
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6250 ins_pipe(istore_mem_reg); |
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6251 %} |
| 0 | 6252 |
| 6253 //----------Store Instructions------------------------------------------------- | |
| 6254 // Store Byte | |
| 6255 instruct storeB(memory mem, iRegI src) %{ | |
| 6256 match(Set mem (StoreB mem src)); | |
| 6257 ins_cost(MEMORY_REF_COST); | |
| 6258 | |
| 6259 size(4); | |
| 6260 format %{ "STB $src,$mem\t! byte" %} | |
| 6261 opcode(Assembler::stb_op3); | |
|
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6262 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6263 ins_pipe(istore_mem_reg); |
| 6264 %} | |
| 6265 | |
| 6266 instruct storeB0(memory mem, immI0 src) %{ | |
| 6267 match(Set mem (StoreB mem src)); | |
| 6268 ins_cost(MEMORY_REF_COST); | |
| 6269 | |
| 6270 size(4); | |
| 6271 format %{ "STB $src,$mem\t! byte" %} | |
| 6272 opcode(Assembler::stb_op3); | |
|
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6273 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6274 ins_pipe(istore_mem_zero); |
| 6275 %} | |
| 6276 | |
| 6277 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6278 match(Set mem (StoreCM mem src)); | |
| 6279 ins_cost(MEMORY_REF_COST); | |
| 6280 | |
| 6281 size(4); | |
| 6282 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6283 opcode(Assembler::stb_op3); | |
|
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6284 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6285 ins_pipe(istore_mem_zero); |
| 6286 %} | |
| 6287 | |
| 6288 // Store Char/Short | |
| 6289 instruct storeC(memory mem, iRegI src) %{ | |
| 6290 match(Set mem (StoreC mem src)); | |
| 6291 ins_cost(MEMORY_REF_COST); | |
| 6292 | |
| 6293 size(4); | |
| 6294 format %{ "STH $src,$mem\t! short" %} | |
| 6295 opcode(Assembler::sth_op3); | |
|
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6296 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6297 ins_pipe(istore_mem_reg); |
| 6298 %} | |
| 6299 | |
| 6300 instruct storeC0(memory mem, immI0 src) %{ | |
| 6301 match(Set mem (StoreC mem src)); | |
| 6302 ins_cost(MEMORY_REF_COST); | |
| 6303 | |
| 6304 size(4); | |
| 6305 format %{ "STH $src,$mem\t! short" %} | |
| 6306 opcode(Assembler::sth_op3); | |
|
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6307 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6308 ins_pipe(istore_mem_zero); |
| 6309 %} | |
| 6310 | |
| 6311 // Store Integer | |
| 6312 instruct storeI(memory mem, iRegI src) %{ | |
| 6313 match(Set mem (StoreI mem src)); | |
| 6314 ins_cost(MEMORY_REF_COST); | |
| 6315 | |
| 6316 size(4); | |
| 6317 format %{ "STW $src,$mem" %} | |
| 6318 opcode(Assembler::stw_op3); | |
|
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6319 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6320 ins_pipe(istore_mem_reg); |
| 6321 %} | |
| 6322 | |
| 6323 // Store Long | |
| 6324 instruct storeL(memory mem, iRegL src) %{ | |
| 6325 match(Set mem (StoreL mem src)); | |
| 6326 ins_cost(MEMORY_REF_COST); | |
| 6327 size(4); | |
| 6328 format %{ "STX $src,$mem\t! long" %} | |
| 6329 opcode(Assembler::stx_op3); | |
|
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6330 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6331 ins_pipe(istore_mem_reg); |
| 6332 %} | |
| 6333 | |
| 6334 instruct storeI0(memory mem, immI0 src) %{ | |
| 6335 match(Set mem (StoreI mem src)); | |
| 6336 ins_cost(MEMORY_REF_COST); | |
| 6337 | |
| 6338 size(4); | |
| 6339 format %{ "STW $src,$mem" %} | |
| 6340 opcode(Assembler::stw_op3); | |
|
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6341 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6342 ins_pipe(istore_mem_zero); |
| 6343 %} | |
| 6344 | |
| 6345 instruct storeL0(memory mem, immL0 src) %{ | |
| 6346 match(Set mem (StoreL mem src)); | |
| 6347 ins_cost(MEMORY_REF_COST); | |
| 6348 | |
| 6349 size(4); | |
| 6350 format %{ "STX $src,$mem" %} | |
| 6351 opcode(Assembler::stx_op3); | |
|
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6352 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6353 ins_pipe(istore_mem_zero); |
| 6354 %} | |
| 6355 | |
| 6356 // Store Integer from float register (used after fstoi) | |
| 6357 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6358 match(Set mem (StoreI mem src)); | |
| 6359 ins_cost(MEMORY_REF_COST); | |
| 6360 | |
| 6361 size(4); | |
| 6362 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6363 opcode(Assembler::stf_op3); | |
|
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6364 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6365 ins_pipe(fstoreF_mem_reg); |
| 6366 %} | |
| 6367 | |
| 6368 // Store Pointer | |
| 6369 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6370 match(Set dst (StoreP dst src)); | |
| 6371 ins_cost(MEMORY_REF_COST); | |
| 6372 size(4); | |
| 6373 | |
| 6374 #ifndef _LP64 | |
| 6375 format %{ "STW $src,$dst\t! ptr" %} | |
| 6376 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6377 #else | |
| 6378 format %{ "STX $src,$dst\t! ptr" %} | |
| 6379 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6380 #endif | |
| 6381 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6382 ins_pipe(istore_mem_spORreg); | |
| 6383 %} | |
| 6384 | |
| 6385 instruct storeP0(memory dst, immP0 src) %{ | |
| 6386 match(Set dst (StoreP dst src)); | |
| 6387 ins_cost(MEMORY_REF_COST); | |
| 6388 size(4); | |
| 6389 | |
| 6390 #ifndef _LP64 | |
| 6391 format %{ "STW $src,$dst\t! ptr" %} | |
| 6392 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6393 #else | |
| 6394 format %{ "STX $src,$dst\t! ptr" %} | |
| 6395 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6396 #endif | |
| 6397 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6398 ins_pipe(istore_mem_zero); | |
| 6399 %} | |
| 6400 | |
|
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6401 // Store Compressed Pointer |
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6402 instruct storeN(memory dst, iRegN src) %{ |
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6403 match(Set dst (StoreN dst src)); |
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6404 ins_cost(MEMORY_REF_COST); |
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6405 size(4); |
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6406 |
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6407 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6408 ins_encode %{ |
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6409 Register base = as_Register($dst$$base); |
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6410 Register index = as_Register($dst$$index); |
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6411 Register src = $src$$Register; |
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6412 if (index != G0) { |
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6413 __ stw(src, base, index); |
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6414 } else { |
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6415 __ stw(src, base, $dst$$disp); |
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6416 } |
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6417 %} |
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6418 ins_pipe(istore_mem_spORreg); |
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6419 %} |
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6420 |
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6421 instruct storeN0(memory dst, immN0 src) %{ |
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6422 match(Set dst (StoreN dst src)); |
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6423 ins_cost(MEMORY_REF_COST); |
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6424 size(4); |
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6425 |
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6426 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6427 ins_encode %{ |
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6428 Register base = as_Register($dst$$base); |
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6429 Register index = as_Register($dst$$index); |
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6430 if (index != G0) { |
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6431 __ stw(0, base, index); |
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6432 } else { |
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6433 __ stw(0, base, $dst$$disp); |
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6434 } |
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6435 %} |
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6436 ins_pipe(istore_mem_zero); |
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6437 %} |
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6438 |
| 0 | 6439 // Store Double |
| 6440 instruct storeD( memory mem, regD src) %{ | |
| 6441 match(Set mem (StoreD mem src)); | |
| 6442 ins_cost(MEMORY_REF_COST); | |
| 6443 | |
| 6444 size(4); | |
| 6445 format %{ "STDF $src,$mem" %} | |
| 6446 opcode(Assembler::stdf_op3); | |
|
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6447 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6448 ins_pipe(fstoreD_mem_reg); |
| 6449 %} | |
| 6450 | |
| 6451 instruct storeD0( memory mem, immD0 src) %{ | |
| 6452 match(Set mem (StoreD mem src)); | |
| 6453 ins_cost(MEMORY_REF_COST); | |
| 6454 | |
| 6455 size(4); | |
| 6456 format %{ "STX $src,$mem" %} | |
| 6457 opcode(Assembler::stx_op3); | |
|
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|
6458 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6459 ins_pipe(fstoreD_mem_zero); |
| 6460 %} | |
| 6461 | |
| 6462 // Store Float | |
| 6463 instruct storeF( memory mem, regF src) %{ | |
| 6464 match(Set mem (StoreF mem src)); | |
| 6465 ins_cost(MEMORY_REF_COST); | |
| 6466 | |
| 6467 size(4); | |
| 6468 format %{ "STF $src,$mem" %} | |
| 6469 opcode(Assembler::stf_op3); | |
|
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|
6470 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6471 ins_pipe(fstoreF_mem_reg); |
| 6472 %} | |
| 6473 | |
| 6474 instruct storeF0( memory mem, immF0 src) %{ | |
| 6475 match(Set mem (StoreF mem src)); | |
| 6476 ins_cost(MEMORY_REF_COST); | |
| 6477 | |
| 6478 size(4); | |
| 6479 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6480 opcode(Assembler::stw_op3); | |
|
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|
6481 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6482 ins_pipe(fstoreF_mem_zero); |
| 6483 %} | |
| 6484 | |
| 6485 // Store Aligned Packed Bytes in Double register to memory | |
| 6486 instruct storeA8B(memory mem, regD src) %{ | |
| 6487 match(Set mem (Store8B mem src)); | |
| 6488 ins_cost(MEMORY_REF_COST); | |
| 6489 size(4); | |
| 6490 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 6491 opcode(Assembler::stdf_op3); | |
|
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|
6492 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6493 ins_pipe(fstoreD_mem_reg); |
| 6494 %} | |
| 6495 | |
|
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|
6496 // Convert oop pointer into compressed form |
|
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|
6497 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
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6498 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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6499 match(Set dst (EncodeP src)); |
|
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6500 format %{ "encode_heap_oop $src, $dst" %} |
|
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|
6501 ins_encode %{ |
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6502 __ encode_heap_oop($src$$Register, $dst$$Register); |
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|
6503 %} |
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|
6504 ins_pipe(ialu_reg); |
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|
6505 %} |
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|
6506 |
|
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6507 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
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6508 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
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6509 match(Set dst (EncodeP src)); |
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|
6510 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6511 ins_encode %{ |
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|
6512 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6513 %} |
|
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|
6514 ins_pipe(ialu_reg); |
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|
6515 %} |
|
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|
6516 |
|
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6517 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
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6518 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6519 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
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6520 match(Set dst (DecodeN src)); |
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6521 format %{ "decode_heap_oop $src, $dst" %} |
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6522 ins_encode %{ |
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6523 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6524 %} |
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|
6525 ins_pipe(ialu_reg); |
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6526 %} |
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|
6527 |
|
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6528 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
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6529 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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|
6530 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
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6531 match(Set dst (DecodeN src)); |
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|
6532 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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|
6533 ins_encode %{ |
|
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|
6534 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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|
6535 %} |
|
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|
6536 ins_pipe(ialu_reg); |
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6537 %} |
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6538 |
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6539 |
| 0 | 6540 // Store Zero into Aligned Packed Bytes |
| 6541 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6542 match(Set mem (Store8B mem zero)); | |
| 6543 ins_cost(MEMORY_REF_COST); | |
| 6544 size(4); | |
| 6545 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6546 opcode(Assembler::stx_op3); | |
|
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6547 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6548 ins_pipe(fstoreD_mem_zero); |
| 6549 %} | |
| 6550 | |
| 6551 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6552 instruct storeA4C(memory mem, regD src) %{ | |
| 6553 match(Set mem (Store4C mem src)); | |
| 6554 ins_cost(MEMORY_REF_COST); | |
| 6555 size(4); | |
| 6556 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6557 opcode(Assembler::stdf_op3); | |
|
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6558 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6559 ins_pipe(fstoreD_mem_reg); |
| 6560 %} | |
| 6561 | |
| 6562 // Store Zero into Aligned Packed Chars/Shorts | |
| 6563 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6564 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6565 ins_cost(MEMORY_REF_COST); | |
| 6566 size(4); | |
| 6567 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6568 opcode(Assembler::stx_op3); | |
|
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6569 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6570 ins_pipe(fstoreD_mem_zero); |
| 6571 %} | |
| 6572 | |
| 6573 // Store Aligned Packed Ints in Double register to memory | |
| 6574 instruct storeA2I(memory mem, regD src) %{ | |
| 6575 match(Set mem (Store2I mem src)); | |
| 6576 ins_cost(MEMORY_REF_COST); | |
| 6577 size(4); | |
| 6578 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6579 opcode(Assembler::stdf_op3); | |
|
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6580 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6581 ins_pipe(fstoreD_mem_reg); |
| 6582 %} | |
| 6583 | |
| 6584 // Store Zero into Aligned Packed Ints | |
| 6585 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6586 match(Set mem (Store2I mem zero)); | |
| 6587 ins_cost(MEMORY_REF_COST); | |
| 6588 size(4); | |
| 6589 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6590 opcode(Assembler::stx_op3); | |
|
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6591 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6592 ins_pipe(fstoreD_mem_zero); |
| 6593 %} | |
| 6594 | |
| 6595 | |
| 6596 //----------MemBar Instructions----------------------------------------------- | |
| 6597 // Memory barrier flavors | |
| 6598 | |
| 6599 instruct membar_acquire() %{ | |
| 6600 match(MemBarAcquire); | |
| 6601 ins_cost(4*MEMORY_REF_COST); | |
| 6602 | |
| 6603 size(0); | |
| 6604 format %{ "MEMBAR-acquire" %} | |
| 6605 ins_encode( enc_membar_acquire ); | |
| 6606 ins_pipe(long_memory_op); | |
| 6607 %} | |
| 6608 | |
| 6609 instruct membar_acquire_lock() %{ | |
| 6610 match(MemBarAcquire); | |
| 6611 predicate(Matcher::prior_fast_lock(n)); | |
| 6612 ins_cost(0); | |
| 6613 | |
| 6614 size(0); | |
| 6615 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6616 ins_encode( ); | |
| 6617 ins_pipe(empty); | |
| 6618 %} | |
| 6619 | |
| 6620 instruct membar_release() %{ | |
| 6621 match(MemBarRelease); | |
| 6622 ins_cost(4*MEMORY_REF_COST); | |
| 6623 | |
| 6624 size(0); | |
| 6625 format %{ "MEMBAR-release" %} | |
| 6626 ins_encode( enc_membar_release ); | |
| 6627 ins_pipe(long_memory_op); | |
| 6628 %} | |
| 6629 | |
| 6630 instruct membar_release_lock() %{ | |
| 6631 match(MemBarRelease); | |
| 6632 predicate(Matcher::post_fast_unlock(n)); | |
| 6633 ins_cost(0); | |
| 6634 | |
| 6635 size(0); | |
| 6636 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6637 ins_encode( ); | |
| 6638 ins_pipe(empty); | |
| 6639 %} | |
| 6640 | |
| 6641 instruct membar_volatile() %{ | |
| 6642 match(MemBarVolatile); | |
| 6643 ins_cost(4*MEMORY_REF_COST); | |
| 6644 | |
| 6645 size(4); | |
| 6646 format %{ "MEMBAR-volatile" %} | |
| 6647 ins_encode( enc_membar_volatile ); | |
| 6648 ins_pipe(long_memory_op); | |
| 6649 %} | |
| 6650 | |
| 6651 instruct unnecessary_membar_volatile() %{ | |
| 6652 match(MemBarVolatile); | |
| 6653 predicate(Matcher::post_store_load_barrier(n)); | |
| 6654 ins_cost(0); | |
| 6655 | |
| 6656 size(0); | |
| 6657 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6658 ins_encode( ); | |
| 6659 ins_pipe(empty); | |
| 6660 %} | |
| 6661 | |
| 6662 //----------Register Move Instructions----------------------------------------- | |
| 6663 instruct roundDouble_nop(regD dst) %{ | |
| 6664 match(Set dst (RoundDouble dst)); | |
| 6665 ins_cost(0); | |
| 6666 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6667 ins_encode( ); | |
| 6668 ins_pipe(empty); | |
| 6669 %} | |
| 6670 | |
| 6671 | |
| 6672 instruct roundFloat_nop(regF dst) %{ | |
| 6673 match(Set dst (RoundFloat dst)); | |
| 6674 ins_cost(0); | |
| 6675 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6676 ins_encode( ); | |
| 6677 ins_pipe(empty); | |
| 6678 %} | |
| 6679 | |
| 6680 | |
| 6681 // Cast Index to Pointer for unsafe natives | |
| 6682 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6683 match(Set dst (CastX2P src)); | |
| 6684 | |
| 6685 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6686 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6687 ins_pipe(ialu_reg); | |
| 6688 %} | |
| 6689 | |
| 6690 // Cast Pointer to Index for unsafe natives | |
| 6691 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6692 match(Set dst (CastP2X src)); | |
| 6693 | |
| 6694 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6695 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6696 ins_pipe(ialu_reg); | |
| 6697 %} | |
| 6698 | |
| 6699 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6700 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6701 match(Set stkSlot src); // chain rule | |
| 6702 ins_cost(MEMORY_REF_COST); | |
| 6703 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6704 opcode(Assembler::stdf_op3); | |
|
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6705 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6706 ins_pipe(fstoreD_stk_reg); |
| 6707 %} | |
| 6708 | |
| 6709 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6710 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6711 match(Set dst stkSlot); // chain rule | |
| 6712 ins_cost(MEMORY_REF_COST); | |
| 6713 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6714 opcode(Assembler::lddf_op3); | |
|
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6715 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6716 ins_pipe(floadD_stk); |
| 6717 %} | |
| 6718 | |
| 6719 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6720 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6721 match(Set stkSlot src); // chain rule | |
| 6722 ins_cost(MEMORY_REF_COST); | |
| 6723 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6724 opcode(Assembler::stf_op3); | |
|
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6725 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6726 ins_pipe(fstoreF_stk_reg); |
| 6727 %} | |
| 6728 | |
| 6729 //----------Conditional Move--------------------------------------------------- | |
| 6730 // Conditional move | |
| 6731 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6732 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6733 ins_cost(150); | |
| 6734 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6735 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6736 ins_pipe(ialu_reg); | |
| 6737 %} | |
| 6738 | |
| 6739 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6740 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6741 ins_cost(140); | |
| 6742 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6743 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6744 ins_pipe(ialu_imm); | |
| 6745 %} | |
| 6746 | |
| 6747 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6748 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6749 ins_cost(150); | |
| 6750 size(4); | |
| 6751 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6752 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6753 ins_pipe(ialu_reg); | |
| 6754 %} | |
| 6755 | |
| 6756 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6757 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6758 ins_cost(140); | |
| 6759 size(4); | |
| 6760 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6761 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6762 ins_pipe(ialu_imm); | |
| 6763 %} | |
| 6764 | |
|
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6765 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6766 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6767 ins_cost(150); | |
| 6768 size(4); | |
| 6769 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6771 ins_pipe(ialu_reg); | |
| 6772 %} | |
| 6773 | |
|
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6774 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6775 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6776 ins_cost(140); | |
| 6777 size(4); | |
| 6778 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6779 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6780 ins_pipe(ialu_imm); | |
| 6781 %} | |
| 6782 | |
| 6783 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6784 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6785 ins_cost(150); | |
| 6786 size(4); | |
| 6787 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6788 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6789 ins_pipe(ialu_reg); | |
| 6790 %} | |
| 6791 | |
| 6792 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6793 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6794 ins_cost(140); | |
| 6795 size(4); | |
| 6796 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6797 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6798 ins_pipe(ialu_imm); | |
| 6799 %} | |
| 6800 | |
|
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6801 // Conditional move for RegN. Only cmov(reg,reg). |
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6802 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
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6803 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
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6804 ins_cost(150); |
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6805 format %{ "MOV$cmp $pcc,$src,$dst" %} |
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6806 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
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6807 ins_pipe(ialu_reg); |
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6808 %} |
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6809 |
|
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6810 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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6811 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
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6812 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
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6813 ins_cost(150); |
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6814 size(4); |
|
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6815 format %{ "MOV$cmp $icc,$src,$dst" %} |
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6816 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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6817 ins_pipe(ialu_reg); |
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6818 %} |
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6819 |
|
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6820 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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6821 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
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6822 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
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6823 ins_cost(150); |
|
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6824 size(4); |
|
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6825 format %{ "MOV$cmp $icc,$src,$dst" %} |
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6826 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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6827 ins_pipe(ialu_reg); |
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6828 %} |
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6829 |
|
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6830 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
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6831 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
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6832 ins_cost(150); |
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6833 size(4); |
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6834 format %{ "MOV$cmp $fcc,$src,$dst" %} |
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6835 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
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6836 ins_pipe(ialu_reg); |
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6837 %} |
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6838 |
| 0 | 6839 // Conditional move |
| 6840 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6841 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6842 ins_cost(150); | |
| 6843 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6844 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6845 ins_pipe(ialu_reg); | |
| 6846 %} | |
| 6847 | |
| 6848 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6849 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6850 ins_cost(140); | |
| 6851 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6852 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6853 ins_pipe(ialu_imm); | |
| 6854 %} | |
| 6855 | |
|
164
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163
diff
changeset
|
6856 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6857 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6858 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6859 ins_cost(150); | |
| 6860 | |
| 6861 size(4); | |
| 6862 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6863 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6864 ins_pipe(ialu_reg); | |
| 6865 %} | |
| 6866 | |
|
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6867 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6868 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6869 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6870 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6871 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6872 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6873 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6874 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6875 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6876 |
| 0 | 6877 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6878 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6879 ins_cost(140); | |
| 6880 | |
| 6881 size(4); | |
| 6882 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6883 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6884 ins_pipe(ialu_imm); | |
| 6885 %} | |
| 6886 | |
|
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6887 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6888 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6889 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6890 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6891 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6892 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6893 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6894 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6895 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6896 |
| 0 | 6897 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6898 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6899 ins_cost(150); | |
| 6900 size(4); | |
| 6901 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6902 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6903 ins_pipe(ialu_imm); | |
| 6904 %} | |
| 6905 | |
| 6906 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6907 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6908 ins_cost(140); | |
| 6909 size(4); | |
| 6910 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6911 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6912 ins_pipe(ialu_imm); | |
| 6913 %} | |
| 6914 | |
| 6915 // Conditional move | |
| 6916 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6917 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6918 ins_cost(150); | |
| 6919 opcode(0x101); | |
| 6920 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6921 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6922 ins_pipe(int_conditional_float_move); | |
| 6923 %} | |
| 6924 | |
| 6925 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6926 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6927 ins_cost(150); | |
| 6928 | |
| 6929 size(4); | |
| 6930 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6931 opcode(0x101); | |
| 6932 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6933 ins_pipe(int_conditional_float_move); | |
| 6934 %} | |
| 6935 | |
|
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6936 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6937 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6938 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6939 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6940 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6941 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6942 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6943 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6944 ins_pipe(int_conditional_float_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6945 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6946 |
| 0 | 6947 // Conditional move, |
| 6948 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6949 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6950 ins_cost(150); | |
| 6951 size(4); | |
| 6952 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6953 opcode(0x1); | |
| 6954 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6955 ins_pipe(int_conditional_double_move); | |
| 6956 %} | |
| 6957 | |
| 6958 // Conditional move | |
| 6959 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6960 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6961 ins_cost(150); | |
| 6962 size(4); | |
| 6963 opcode(0x102); | |
| 6964 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6965 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6966 ins_pipe(int_conditional_double_move); | |
| 6967 %} | |
| 6968 | |
| 6969 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 6970 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 6971 ins_cost(150); | |
| 6972 | |
| 6973 size(4); | |
| 6974 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 6975 opcode(0x102); | |
| 6976 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6977 ins_pipe(int_conditional_double_move); | |
| 6978 %} | |
| 6979 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6980 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6981 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6982 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6983 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6984 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6985 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6986 opcode(0x102); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6987 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6988 ins_pipe(int_conditional_double_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6989 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6990 |
| 0 | 6991 // Conditional move, |
| 6992 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 6993 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 6994 ins_cost(150); | |
| 6995 size(4); | |
| 6996 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 6997 opcode(0x2); | |
| 6998 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6999 ins_pipe(int_conditional_double_move); | |
| 7000 %} | |
| 7001 | |
| 7002 // Conditional move | |
| 7003 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7004 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7005 ins_cost(150); | |
| 7006 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7007 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7008 ins_pipe(ialu_reg); | |
| 7009 %} | |
| 7010 | |
| 7011 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7012 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7013 ins_cost(140); | |
| 7014 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7015 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7016 ins_pipe(ialu_imm); | |
| 7017 %} | |
| 7018 | |
| 7019 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7020 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7021 ins_cost(150); | |
| 7022 | |
| 7023 size(4); | |
| 7024 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7025 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7026 ins_pipe(ialu_reg); | |
| 7027 %} | |
| 7028 | |
| 7029 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
7030 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7031 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7032 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7033 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7034 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7035 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7036 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7037 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7038 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7039 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
7040 |
| 0 | 7041 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7042 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7043 ins_cost(150); | |
| 7044 | |
| 7045 size(4); | |
| 7046 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7047 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7048 ins_pipe(ialu_reg); | |
| 7049 %} | |
| 7050 | |
| 7051 | |
| 7052 | |
| 7053 //----------OS and Locking Instructions---------------------------------------- | |
| 7054 | |
| 7055 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7056 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7057 // for this guy. | |
| 7058 instruct tlsLoadP(g2RegP dst) %{ | |
| 7059 match(Set dst (ThreadLocal)); | |
| 7060 | |
| 7061 size(0); | |
| 7062 ins_cost(0); | |
| 7063 format %{ "# TLS is in G2" %} | |
| 7064 ins_encode( /*empty encoding*/ ); | |
| 7065 ins_pipe(ialu_none); | |
| 7066 %} | |
| 7067 | |
| 7068 instruct checkCastPP( iRegP dst ) %{ | |
| 7069 match(Set dst (CheckCastPP dst)); | |
| 7070 | |
| 7071 size(0); | |
| 7072 format %{ "# checkcastPP of $dst" %} | |
| 7073 ins_encode( /*empty encoding*/ ); | |
| 7074 ins_pipe(empty); | |
| 7075 %} | |
| 7076 | |
| 7077 | |
| 7078 instruct castPP( iRegP dst ) %{ | |
| 7079 match(Set dst (CastPP dst)); | |
| 7080 format %{ "# castPP of $dst" %} | |
| 7081 ins_encode( /*empty encoding*/ ); | |
| 7082 ins_pipe(empty); | |
| 7083 %} | |
| 7084 | |
| 7085 instruct castII( iRegI dst ) %{ | |
| 7086 match(Set dst (CastII dst)); | |
| 7087 format %{ "# castII of $dst" %} | |
| 7088 ins_encode( /*empty encoding*/ ); | |
| 7089 ins_cost(0); | |
| 7090 ins_pipe(empty); | |
| 7091 %} | |
| 7092 | |
| 7093 //----------Arithmetic Instructions-------------------------------------------- | |
| 7094 // Addition Instructions | |
| 7095 // Register Addition | |
| 7096 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7097 match(Set dst (AddI src1 src2)); | |
| 7098 | |
| 7099 size(4); | |
| 7100 format %{ "ADD $src1,$src2,$dst" %} | |
| 7101 ins_encode %{ | |
| 7102 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7103 %} | |
| 7104 ins_pipe(ialu_reg_reg); | |
| 7105 %} | |
| 7106 | |
| 7107 // Immediate Addition | |
| 7108 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7109 match(Set dst (AddI src1 src2)); | |
| 7110 | |
| 7111 size(4); | |
| 7112 format %{ "ADD $src1,$src2,$dst" %} | |
| 7113 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7114 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7115 ins_pipe(ialu_reg_imm); | |
| 7116 %} | |
| 7117 | |
| 7118 // Pointer Register Addition | |
| 7119 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7120 match(Set dst (AddP src1 src2)); | |
| 7121 | |
| 7122 size(4); | |
| 7123 format %{ "ADD $src1,$src2,$dst" %} | |
| 7124 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7125 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7126 ins_pipe(ialu_reg_reg); | |
| 7127 %} | |
| 7128 | |
| 7129 // Pointer Immediate Addition | |
| 7130 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7131 match(Set dst (AddP src1 src2)); | |
| 7132 | |
| 7133 size(4); | |
| 7134 format %{ "ADD $src1,$src2,$dst" %} | |
| 7135 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7136 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7137 ins_pipe(ialu_reg_imm); | |
| 7138 %} | |
| 7139 | |
| 7140 // Long Addition | |
| 7141 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7142 match(Set dst (AddL src1 src2)); | |
| 7143 | |
| 7144 size(4); | |
| 7145 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7146 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7147 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7148 ins_pipe(ialu_reg_reg); | |
| 7149 %} | |
| 7150 | |
| 7151 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7152 match(Set dst (AddL src1 con)); | |
| 7153 | |
| 7154 size(4); | |
| 7155 format %{ "ADD $src1,$con,$dst" %} | |
| 7156 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7157 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7158 ins_pipe(ialu_reg_imm); | |
| 7159 %} | |
| 7160 | |
| 7161 //----------Conditional_store-------------------------------------------------- | |
| 7162 // Conditional-store of the updated heap-top. | |
| 7163 // Used during allocation of the shared heap. | |
| 7164 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7165 | |
| 7166 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7167 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7168 match(Set dst (LoadPLocked mem)); | |
| 7169 ins_cost(MEMORY_REF_COST); | |
| 7170 | |
| 7171 #ifndef _LP64 | |
| 7172 size(4); | |
| 7173 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7174 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7175 #else | |
| 7176 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7177 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7178 #endif | |
| 7179 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7180 ins_pipe(iload_mem); | |
| 7181 %} | |
| 7182 | |
| 7183 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 7184 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 7185 match(Set dst (LoadLLocked mem)); | |
| 7186 ins_cost(MEMORY_REF_COST); | |
| 7187 size(4); | |
| 7188 format %{ "LDX $mem,$dst\t! long" %} | |
| 7189 opcode(Assembler::ldx_op3); | |
|
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7190 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 7191 ins_pipe(iload_mem); |
| 7192 %} | |
| 7193 | |
| 7194 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7195 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7196 effect( KILL newval ); | |
| 7197 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7198 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7199 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7200 ins_pipe( long_memory_op ); | |
| 7201 %} | |
| 7202 | |
|
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7203 // Conditional-store of an int value. |
|
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7204 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
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7205 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
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7206 effect( KILL newval ); |
|
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7207 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7208 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7209 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7210 ins_pipe( long_memory_op ); |
| 7211 %} | |
| 7212 | |
|
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7213 // Conditional-store of a long value. |
|
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7214 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
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7215 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
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7216 effect( KILL newval ); |
|
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7217 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7218 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7219 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7220 ins_pipe( long_memory_op ); |
| 7221 %} | |
| 7222 | |
| 7223 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7224 | |
| 7225 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7226 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7227 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7228 format %{ | |
| 7229 "MOV $newval,O7\n\t" | |
| 7230 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7231 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7232 "MOV 1,$res\n\t" | |
| 7233 "MOVne xcc,R_G0,$res" | |
| 7234 %} | |
| 7235 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7236 enc_lflags_ne_to_boolean(res) ); | |
| 7237 ins_pipe( long_memory_op ); | |
| 7238 %} | |
| 7239 | |
| 7240 | |
| 7241 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7242 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7243 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7244 format %{ | |
| 7245 "MOV $newval,O7\n\t" | |
| 7246 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7247 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7248 "MOV 1,$res\n\t" | |
| 7249 "MOVne icc,R_G0,$res" | |
| 7250 %} | |
| 7251 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7252 enc_iflags_ne_to_boolean(res) ); | |
| 7253 ins_pipe( long_memory_op ); | |
| 7254 %} | |
| 7255 | |
| 7256 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7257 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7258 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7259 format %{ | |
| 7260 "MOV $newval,O7\n\t" | |
|
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7261 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7262 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7263 "MOV 1,$res\n\t" | |
| 7264 "MOVne xcc,R_G0,$res" | |
| 7265 %} | |
|
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7266 #ifdef _LP64 |
| 0 | 7267 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7268 enc_lflags_ne_to_boolean(res) ); | |
| 7269 #else | |
|
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7270 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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7271 enc_iflags_ne_to_boolean(res) ); |
|
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7272 #endif |
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7273 ins_pipe( long_memory_op ); |
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7274 %} |
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7275 |
|
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7276 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
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7277 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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7278 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7279 format %{ |
| 7280 "MOV $newval,O7\n\t" | |
| 7281 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7282 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7283 "MOV 1,$res\n\t" | |
| 7284 "MOVne icc,R_G0,$res" | |
| 7285 %} | |
|
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7286 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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7287 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7288 ins_pipe( long_memory_op ); |
| 7289 %} | |
| 7290 | |
| 7291 //--------------------- | |
| 7292 // Subtraction Instructions | |
| 7293 // Register Subtraction | |
| 7294 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7295 match(Set dst (SubI src1 src2)); | |
| 7296 | |
| 7297 size(4); | |
| 7298 format %{ "SUB $src1,$src2,$dst" %} | |
| 7299 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7300 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7301 ins_pipe(ialu_reg_reg); | |
| 7302 %} | |
| 7303 | |
| 7304 // Immediate Subtraction | |
| 7305 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7306 match(Set dst (SubI src1 src2)); | |
| 7307 | |
| 7308 size(4); | |
| 7309 format %{ "SUB $src1,$src2,$dst" %} | |
| 7310 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7311 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7312 ins_pipe(ialu_reg_imm); | |
| 7313 %} | |
| 7314 | |
| 7315 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7316 match(Set dst (SubI zero src2)); | |
| 7317 | |
| 7318 size(4); | |
| 7319 format %{ "NEG $src2,$dst" %} | |
| 7320 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7321 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7322 ins_pipe(ialu_zero_reg); | |
| 7323 %} | |
| 7324 | |
| 7325 // Long subtraction | |
| 7326 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7327 match(Set dst (SubL src1 src2)); | |
| 7328 | |
| 7329 size(4); | |
| 7330 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7331 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7332 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7333 ins_pipe(ialu_reg_reg); | |
| 7334 %} | |
| 7335 | |
| 7336 // Immediate Subtraction | |
| 7337 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7338 match(Set dst (SubL src1 con)); | |
| 7339 | |
| 7340 size(4); | |
| 7341 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7342 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7343 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7344 ins_pipe(ialu_reg_imm); | |
| 7345 %} | |
| 7346 | |
| 7347 // Long negation | |
| 7348 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7349 match(Set dst (SubL zero src2)); | |
| 7350 | |
| 7351 size(4); | |
| 7352 format %{ "NEG $src2,$dst\t! long" %} | |
| 7353 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7354 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7355 ins_pipe(ialu_zero_reg); | |
| 7356 %} | |
| 7357 | |
| 7358 // Multiplication Instructions | |
| 7359 // Integer Multiplication | |
| 7360 // Register Multiplication | |
| 7361 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7362 match(Set dst (MulI src1 src2)); | |
| 7363 | |
| 7364 size(4); | |
| 7365 format %{ "MULX $src1,$src2,$dst" %} | |
| 7366 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7367 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7368 ins_pipe(imul_reg_reg); | |
| 7369 %} | |
| 7370 | |
| 7371 // Immediate Multiplication | |
| 7372 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7373 match(Set dst (MulI src1 src2)); | |
| 7374 | |
| 7375 size(4); | |
| 7376 format %{ "MULX $src1,$src2,$dst" %} | |
| 7377 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7378 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7379 ins_pipe(imul_reg_imm); | |
| 7380 %} | |
| 7381 | |
| 7382 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7383 match(Set dst (MulL src1 src2)); | |
| 7384 ins_cost(DEFAULT_COST * 5); | |
| 7385 size(4); | |
| 7386 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7387 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7388 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7389 ins_pipe(mulL_reg_reg); | |
| 7390 %} | |
| 7391 | |
| 7392 // Immediate Multiplication | |
| 7393 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7394 match(Set dst (MulL src1 src2)); | |
| 7395 ins_cost(DEFAULT_COST * 5); | |
| 7396 size(4); | |
| 7397 format %{ "MULX $src1,$src2,$dst" %} | |
| 7398 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7399 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7400 ins_pipe(mulL_reg_imm); | |
| 7401 %} | |
| 7402 | |
| 7403 // Integer Division | |
| 7404 // Register Division | |
| 7405 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7406 match(Set dst (DivI src1 src2)); | |
| 7407 ins_cost((2+71)*DEFAULT_COST); | |
| 7408 | |
| 7409 format %{ "SRA $src2,0,$src2\n\t" | |
| 7410 "SRA $src1,0,$src1\n\t" | |
| 7411 "SDIVX $src1,$src2,$dst" %} | |
| 7412 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7413 ins_pipe(sdiv_reg_reg); | |
| 7414 %} | |
| 7415 | |
| 7416 // Immediate Division | |
| 7417 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7418 match(Set dst (DivI src1 src2)); | |
| 7419 ins_cost((2+71)*DEFAULT_COST); | |
| 7420 | |
| 7421 format %{ "SRA $src1,0,$src1\n\t" | |
| 7422 "SDIVX $src1,$src2,$dst" %} | |
| 7423 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7424 ins_pipe(sdiv_reg_imm); | |
| 7425 %} | |
| 7426 | |
| 7427 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7428 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7429 // Expand rule only, not matched | |
| 7430 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7431 effect( DEF dst, USE src1, USE src2 ); | |
| 7432 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7433 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7434 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7435 ins_pipe(sdiv_reg_reg); | |
| 7436 %} | |
| 7437 | |
| 605 | 7438 // Magic constant, reciprocal of 10 |
| 0 | 7439 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7440 effect( DEF dst ); | |
| 7441 | |
| 7442 size(8); | |
| 7443 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7444 ins_encode( Set32(0x66666667, dst) ); | |
| 7445 ins_pipe(ialu_hi_lo_reg); | |
| 7446 %} | |
| 7447 | |
| 605 | 7448 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7449 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7450 effect( DEF dst, USE src ); | |
| 7451 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7452 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7453 ins_pipe(ialu_reg_reg); | |
| 7454 %} | |
| 7455 | |
| 7456 // Arithmetic Shift Right by 8-bit immediate | |
| 7457 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7458 effect( DEF dst, USE src ); | |
| 7459 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7460 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7461 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7462 ins_pipe(ialu_reg_imm); | |
| 7463 %} | |
| 7464 | |
| 7465 // Integer DIV with 10 | |
| 7466 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7467 match(Set dst (DivI src div)); | |
| 7468 ins_cost((6+6)*DEFAULT_COST); | |
| 7469 expand %{ | |
| 7470 iRegIsafe tmp1; // Killed temps; | |
| 7471 iRegIsafe tmp2; // Killed temps; | |
| 7472 iRegI tmp3; // Killed temps; | |
| 7473 iRegI tmp4; // Killed temps; | |
| 7474 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7475 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7476 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7477 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7478 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7479 %} | |
| 7480 %} | |
| 7481 | |
| 7482 // Register Long Division | |
| 7483 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7484 match(Set dst (DivL src1 src2)); | |
| 7485 ins_cost(DEFAULT_COST*71); | |
| 7486 size(4); | |
| 7487 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7488 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7489 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7490 ins_pipe(divL_reg_reg); | |
| 7491 %} | |
| 7492 | |
| 7493 // Register Long Division | |
| 7494 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7495 match(Set dst (DivL src1 src2)); | |
| 7496 ins_cost(DEFAULT_COST*71); | |
| 7497 size(4); | |
| 7498 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7499 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7500 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7501 ins_pipe(divL_reg_imm); | |
| 7502 %} | |
| 7503 | |
| 7504 // Integer Remainder | |
| 7505 // Register Remainder | |
| 7506 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7507 match(Set dst (ModI src1 src2)); | |
| 7508 effect( KILL ccr, KILL temp); | |
| 7509 | |
| 7510 format %{ "SREM $src1,$src2,$dst" %} | |
| 7511 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7512 ins_pipe(sdiv_reg_reg); | |
| 7513 %} | |
| 7514 | |
| 7515 // Immediate Remainder | |
| 7516 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7517 match(Set dst (ModI src1 src2)); | |
| 7518 effect( KILL ccr, KILL temp); | |
| 7519 | |
| 7520 format %{ "SREM $src1,$src2,$dst" %} | |
| 7521 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7522 ins_pipe(sdiv_reg_imm); | |
| 7523 %} | |
| 7524 | |
| 7525 // Register Long Remainder | |
| 7526 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7527 effect(DEF dst, USE src1, USE src2); | |
| 7528 size(4); | |
| 7529 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7530 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7531 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7532 ins_pipe(divL_reg_reg); | |
| 7533 %} | |
| 7534 | |
| 7535 // Register Long Division | |
| 7536 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7537 effect(DEF dst, USE src1, USE src2); | |
| 7538 size(4); | |
| 7539 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7540 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7541 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7542 ins_pipe(divL_reg_imm); | |
| 7543 %} | |
| 7544 | |
| 7545 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7546 effect(DEF dst, USE src1, USE src2); | |
| 7547 size(4); | |
| 7548 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7549 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7550 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7551 ins_pipe(mulL_reg_reg); | |
| 7552 %} | |
| 7553 | |
| 7554 // Immediate Multiplication | |
| 7555 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7556 effect(DEF dst, USE src1, USE src2); | |
| 7557 size(4); | |
| 7558 format %{ "MULX $src1,$src2,$dst" %} | |
| 7559 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7560 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7561 ins_pipe(mulL_reg_imm); | |
| 7562 %} | |
| 7563 | |
| 7564 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7565 effect(DEF dst, USE src1, USE src2); | |
| 7566 size(4); | |
| 7567 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7568 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7569 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7570 ins_pipe(ialu_reg_reg); | |
| 7571 %} | |
| 7572 | |
| 7573 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7574 effect(DEF dst, USE src1, USE src2); | |
| 7575 size(4); | |
| 7576 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7577 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7578 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7579 ins_pipe(ialu_reg_reg); | |
| 7580 %} | |
| 7581 | |
| 7582 // Register Long Remainder | |
| 7583 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7584 match(Set dst (ModL src1 src2)); | |
| 7585 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7586 expand %{ | |
| 7587 iRegL tmp1; | |
| 7588 iRegL tmp2; | |
| 7589 divL_reg_reg_1(tmp1, src1, src2); | |
| 7590 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7591 subL_reg_reg_1(dst, src1, tmp2); | |
| 7592 %} | |
| 7593 %} | |
| 7594 | |
| 7595 // Register Long Remainder | |
| 7596 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7597 match(Set dst (ModL src1 src2)); | |
| 7598 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7599 expand %{ | |
| 7600 iRegL tmp1; | |
| 7601 iRegL tmp2; | |
| 7602 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7603 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7604 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7605 %} | |
| 7606 %} | |
| 7607 | |
| 7608 // Integer Shift Instructions | |
| 7609 // Register Shift Left | |
| 7610 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7611 match(Set dst (LShiftI src1 src2)); | |
| 7612 | |
| 7613 size(4); | |
| 7614 format %{ "SLL $src1,$src2,$dst" %} | |
| 7615 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7616 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7617 ins_pipe(ialu_reg_reg); | |
| 7618 %} | |
| 7619 | |
| 7620 // Register Shift Left Immediate | |
| 7621 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7622 match(Set dst (LShiftI src1 src2)); | |
| 7623 | |
| 7624 size(4); | |
| 7625 format %{ "SLL $src1,$src2,$dst" %} | |
| 7626 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7627 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7628 ins_pipe(ialu_reg_imm); | |
| 7629 %} | |
| 7630 | |
| 7631 // Register Shift Left | |
| 7632 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7633 match(Set dst (LShiftL src1 src2)); | |
| 7634 | |
| 7635 size(4); | |
| 7636 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7637 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7638 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7639 ins_pipe(ialu_reg_reg); | |
| 7640 %} | |
| 7641 | |
| 7642 // Register Shift Left Immediate | |
| 7643 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7644 match(Set dst (LShiftL src1 src2)); | |
| 7645 | |
| 7646 size(4); | |
| 7647 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7648 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7649 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7650 ins_pipe(ialu_reg_imm); | |
| 7651 %} | |
| 7652 | |
| 7653 // Register Arithmetic Shift Right | |
| 7654 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7655 match(Set dst (RShiftI src1 src2)); | |
| 7656 size(4); | |
| 7657 format %{ "SRA $src1,$src2,$dst" %} | |
| 7658 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7659 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7660 ins_pipe(ialu_reg_reg); | |
| 7661 %} | |
| 7662 | |
| 7663 // Register Arithmetic Shift Right Immediate | |
| 7664 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7665 match(Set dst (RShiftI src1 src2)); | |
| 7666 | |
| 7667 size(4); | |
| 7668 format %{ "SRA $src1,$src2,$dst" %} | |
| 7669 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7670 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7671 ins_pipe(ialu_reg_imm); | |
| 7672 %} | |
| 7673 | |
| 7674 // Register Shift Right Arithmatic Long | |
| 7675 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7676 match(Set dst (RShiftL src1 src2)); | |
| 7677 | |
| 7678 size(4); | |
| 7679 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7680 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7681 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7682 ins_pipe(ialu_reg_reg); | |
| 7683 %} | |
| 7684 | |
| 7685 // Register Shift Left Immediate | |
| 7686 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7687 match(Set dst (RShiftL src1 src2)); | |
| 7688 | |
| 7689 size(4); | |
| 7690 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7691 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7692 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7693 ins_pipe(ialu_reg_imm); | |
| 7694 %} | |
| 7695 | |
| 7696 // Register Shift Right | |
| 7697 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7698 match(Set dst (URShiftI src1 src2)); | |
| 7699 | |
| 7700 size(4); | |
| 7701 format %{ "SRL $src1,$src2,$dst" %} | |
| 7702 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7704 ins_pipe(ialu_reg_reg); | |
| 7705 %} | |
| 7706 | |
| 7707 // Register Shift Right Immediate | |
| 7708 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7709 match(Set dst (URShiftI src1 src2)); | |
| 7710 | |
| 7711 size(4); | |
| 7712 format %{ "SRL $src1,$src2,$dst" %} | |
| 7713 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7714 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7715 ins_pipe(ialu_reg_imm); | |
| 7716 %} | |
| 7717 | |
| 7718 // Register Shift Right | |
| 7719 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7720 match(Set dst (URShiftL src1 src2)); | |
| 7721 | |
| 7722 size(4); | |
| 7723 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7724 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7725 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7726 ins_pipe(ialu_reg_reg); | |
| 7727 %} | |
| 7728 | |
| 7729 // Register Shift Right Immediate | |
| 7730 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7731 match(Set dst (URShiftL src1 src2)); | |
| 7732 | |
| 7733 size(4); | |
| 7734 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7735 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7736 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7737 ins_pipe(ialu_reg_imm); | |
| 7738 %} | |
| 7739 | |
| 7740 // Register Shift Right Immediate with a CastP2X | |
| 7741 #ifdef _LP64 | |
| 7742 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7743 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7744 size(4); | |
| 7745 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7746 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7747 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7748 ins_pipe(ialu_reg_imm); | |
| 7749 %} | |
| 7750 #else | |
| 7751 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7752 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7753 size(4); | |
| 7754 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7755 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7756 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7757 ins_pipe(ialu_reg_imm); | |
| 7758 %} | |
| 7759 #endif | |
| 7760 | |
| 7761 | |
| 7762 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7763 | |
| 7764 // Add float single precision | |
| 7765 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7766 match(Set dst (AddF src1 src2)); | |
| 7767 | |
| 7768 size(4); | |
| 7769 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7770 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7771 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7772 ins_pipe(faddF_reg_reg); | |
| 7773 %} | |
| 7774 | |
| 7775 // Add float double precision | |
| 7776 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7777 match(Set dst (AddD src1 src2)); | |
| 7778 | |
| 7779 size(4); | |
| 7780 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7781 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7782 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7783 ins_pipe(faddD_reg_reg); | |
| 7784 %} | |
| 7785 | |
| 7786 // Sub float single precision | |
| 7787 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7788 match(Set dst (SubF src1 src2)); | |
| 7789 | |
| 7790 size(4); | |
| 7791 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7792 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7793 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7794 ins_pipe(faddF_reg_reg); | |
| 7795 %} | |
| 7796 | |
| 7797 // Sub float double precision | |
| 7798 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7799 match(Set dst (SubD src1 src2)); | |
| 7800 | |
| 7801 size(4); | |
| 7802 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7803 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7804 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7805 ins_pipe(faddD_reg_reg); | |
| 7806 %} | |
| 7807 | |
| 7808 // Mul float single precision | |
| 7809 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7810 match(Set dst (MulF src1 src2)); | |
| 7811 | |
| 7812 size(4); | |
| 7813 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7814 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7815 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7816 ins_pipe(fmulF_reg_reg); | |
| 7817 %} | |
| 7818 | |
| 7819 // Mul float double precision | |
| 7820 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7821 match(Set dst (MulD src1 src2)); | |
| 7822 | |
| 7823 size(4); | |
| 7824 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7825 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7826 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7827 ins_pipe(fmulD_reg_reg); | |
| 7828 %} | |
| 7829 | |
| 7830 // Div float single precision | |
| 7831 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7832 match(Set dst (DivF src1 src2)); | |
| 7833 | |
| 7834 size(4); | |
| 7835 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7836 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7837 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7838 ins_pipe(fdivF_reg_reg); | |
| 7839 %} | |
| 7840 | |
| 7841 // Div float double precision | |
| 7842 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7843 match(Set dst (DivD src1 src2)); | |
| 7844 | |
| 7845 size(4); | |
| 7846 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7847 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7848 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7849 ins_pipe(fdivD_reg_reg); | |
| 7850 %} | |
| 7851 | |
| 7852 // Absolute float double precision | |
| 7853 instruct absD_reg(regD dst, regD src) %{ | |
| 7854 match(Set dst (AbsD src)); | |
| 7855 | |
| 7856 format %{ "FABSd $src,$dst" %} | |
| 7857 ins_encode(fabsd(dst, src)); | |
| 7858 ins_pipe(faddD_reg); | |
| 7859 %} | |
| 7860 | |
| 7861 // Absolute float single precision | |
| 7862 instruct absF_reg(regF dst, regF src) %{ | |
| 7863 match(Set dst (AbsF src)); | |
| 7864 | |
| 7865 format %{ "FABSs $src,$dst" %} | |
| 7866 ins_encode(fabss(dst, src)); | |
| 7867 ins_pipe(faddF_reg); | |
| 7868 %} | |
| 7869 | |
| 7870 instruct negF_reg(regF dst, regF src) %{ | |
| 7871 match(Set dst (NegF src)); | |
| 7872 | |
| 7873 size(4); | |
| 7874 format %{ "FNEGs $src,$dst" %} | |
| 7875 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7876 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7877 ins_pipe(faddF_reg); | |
| 7878 %} | |
| 7879 | |
| 7880 instruct negD_reg(regD dst, regD src) %{ | |
| 7881 match(Set dst (NegD src)); | |
| 7882 | |
| 7883 format %{ "FNEGd $src,$dst" %} | |
| 7884 ins_encode(fnegd(dst, src)); | |
| 7885 ins_pipe(faddD_reg); | |
| 7886 %} | |
| 7887 | |
| 7888 // Sqrt float double precision | |
| 7889 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7890 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7891 | |
| 7892 size(4); | |
| 7893 format %{ "FSQRTS $src,$dst" %} | |
| 7894 ins_encode(fsqrts(dst, src)); | |
| 7895 ins_pipe(fdivF_reg_reg); | |
| 7896 %} | |
| 7897 | |
| 7898 // Sqrt float double precision | |
| 7899 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7900 match(Set dst (SqrtD src)); | |
| 7901 | |
| 7902 size(4); | |
| 7903 format %{ "FSQRTD $src,$dst" %} | |
| 7904 ins_encode(fsqrtd(dst, src)); | |
| 7905 ins_pipe(fdivD_reg_reg); | |
| 7906 %} | |
| 7907 | |
| 7908 //----------Logical Instructions----------------------------------------------- | |
| 7909 // And Instructions | |
| 7910 // Register And | |
| 7911 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7912 match(Set dst (AndI src1 src2)); | |
| 7913 | |
| 7914 size(4); | |
| 7915 format %{ "AND $src1,$src2,$dst" %} | |
| 7916 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7917 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7918 ins_pipe(ialu_reg_reg); | |
| 7919 %} | |
| 7920 | |
| 7921 // Immediate And | |
| 7922 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7923 match(Set dst (AndI src1 src2)); | |
| 7924 | |
| 7925 size(4); | |
| 7926 format %{ "AND $src1,$src2,$dst" %} | |
| 7927 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7928 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7929 ins_pipe(ialu_reg_imm); | |
| 7930 %} | |
| 7931 | |
| 7932 // Register And Long | |
| 7933 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7934 match(Set dst (AndL src1 src2)); | |
| 7935 | |
| 7936 ins_cost(DEFAULT_COST); | |
| 7937 size(4); | |
| 7938 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7939 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7940 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7941 ins_pipe(ialu_reg_reg); | |
| 7942 %} | |
| 7943 | |
| 7944 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7945 match(Set dst (AndL src1 con)); | |
| 7946 | |
| 7947 ins_cost(DEFAULT_COST); | |
| 7948 size(4); | |
| 7949 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7950 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7951 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7952 ins_pipe(ialu_reg_imm); | |
| 7953 %} | |
| 7954 | |
| 7955 // Or Instructions | |
| 7956 // Register Or | |
| 7957 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7958 match(Set dst (OrI src1 src2)); | |
| 7959 | |
| 7960 size(4); | |
| 7961 format %{ "OR $src1,$src2,$dst" %} | |
| 7962 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7963 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7964 ins_pipe(ialu_reg_reg); | |
| 7965 %} | |
| 7966 | |
| 7967 // Immediate Or | |
| 7968 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7969 match(Set dst (OrI src1 src2)); | |
| 7970 | |
| 7971 size(4); | |
| 7972 format %{ "OR $src1,$src2,$dst" %} | |
| 7973 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7974 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7975 ins_pipe(ialu_reg_imm); | |
| 7976 %} | |
| 7977 | |
| 7978 // Register Or Long | |
| 7979 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7980 match(Set dst (OrL src1 src2)); | |
| 7981 | |
| 7982 ins_cost(DEFAULT_COST); | |
| 7983 size(4); | |
| 7984 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 7985 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7986 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7987 ins_pipe(ialu_reg_reg); | |
| 7988 %} | |
| 7989 | |
| 7990 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7991 match(Set dst (OrL src1 con)); | |
| 7992 ins_cost(DEFAULT_COST*2); | |
| 7993 | |
| 7994 ins_cost(DEFAULT_COST); | |
| 7995 size(4); | |
| 7996 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 7997 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7998 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7999 ins_pipe(ialu_reg_imm); | |
| 8000 %} | |
| 8001 | |
|
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8002 #ifndef _LP64 |
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8003 |
|
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8004 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8005 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8006 match(Set dst (OrI src1 (CastP2X src2))); |
|
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8007 |
|
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8008 size(4); |
|
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8009 format %{ "OR $src1,$src2,$dst" %} |
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8010 opcode(Assembler::or_op3, Assembler::arith_op); |
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8011 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8012 ins_pipe(ialu_reg_reg); |
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8013 %} |
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8014 |
|
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8015 #else |
|
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8016 |
|
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8017 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8018 match(Set dst (OrL src1 (CastP2X src2))); |
|
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8019 |
|
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8020 ins_cost(DEFAULT_COST); |
|
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8021 size(4); |
|
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8022 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8023 opcode(Assembler::or_op3, Assembler::arith_op); |
|
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8024 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
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8025 ins_pipe(ialu_reg_reg); |
|
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8026 %} |
|
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8027 |
|
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8028 #endif |
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8029 |
| 0 | 8030 // Xor Instructions |
| 8031 // Register Xor | |
| 8032 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8033 match(Set dst (XorI src1 src2)); | |
| 8034 | |
| 8035 size(4); | |
| 8036 format %{ "XOR $src1,$src2,$dst" %} | |
| 8037 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8038 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8039 ins_pipe(ialu_reg_reg); | |
| 8040 %} | |
| 8041 | |
| 8042 // Immediate Xor | |
| 8043 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8044 match(Set dst (XorI src1 src2)); | |
| 8045 | |
| 8046 size(4); | |
| 8047 format %{ "XOR $src1,$src2,$dst" %} | |
| 8048 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8049 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8050 ins_pipe(ialu_reg_imm); | |
| 8051 %} | |
| 8052 | |
| 8053 // Register Xor Long | |
| 8054 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8055 match(Set dst (XorL src1 src2)); | |
| 8056 | |
| 8057 ins_cost(DEFAULT_COST); | |
| 8058 size(4); | |
| 8059 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8060 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8061 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8062 ins_pipe(ialu_reg_reg); | |
| 8063 %} | |
| 8064 | |
| 8065 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8066 match(Set dst (XorL src1 con)); | |
| 8067 | |
| 8068 ins_cost(DEFAULT_COST); | |
| 8069 size(4); | |
| 8070 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8071 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8072 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8073 ins_pipe(ialu_reg_imm); | |
| 8074 %} | |
| 8075 | |
| 8076 //----------Convert to Boolean------------------------------------------------- | |
| 8077 // Nice hack for 32-bit tests but doesn't work for | |
| 8078 // 64-bit pointers. | |
| 8079 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8080 match(Set dst (Conv2B src)); | |
| 8081 effect( KILL ccr ); | |
| 8082 ins_cost(DEFAULT_COST*2); | |
| 8083 format %{ "CMP R_G0,$src\n\t" | |
| 8084 "ADDX R_G0,0,$dst" %} | |
| 8085 ins_encode( enc_to_bool( src, dst ) ); | |
| 8086 ins_pipe(ialu_reg_ialu); | |
| 8087 %} | |
| 8088 | |
| 8089 #ifndef _LP64 | |
| 8090 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8091 match(Set dst (Conv2B src)); | |
| 8092 effect( KILL ccr ); | |
| 8093 ins_cost(DEFAULT_COST*2); | |
| 8094 format %{ "CMP R_G0,$src\n\t" | |
| 8095 "ADDX R_G0,0,$dst" %} | |
| 8096 ins_encode( enc_to_bool( src, dst ) ); | |
| 8097 ins_pipe(ialu_reg_ialu); | |
| 8098 %} | |
| 8099 #else | |
| 8100 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8101 match(Set dst (Conv2B src)); | |
| 8102 ins_cost(DEFAULT_COST*2); | |
| 8103 format %{ "MOV $src,$dst\n\t" | |
| 8104 "MOVRNZ $src,1,$dst" %} | |
| 8105 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8106 ins_pipe(ialu_clr_and_mover); | |
| 8107 %} | |
| 8108 #endif | |
| 8109 | |
| 8110 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
| 8111 match(Set dst (CmpLTMask p q)); | |
| 8112 effect( KILL ccr ); | |
| 8113 ins_cost(DEFAULT_COST*4); | |
| 8114 format %{ "CMP $p,$q\n\t" | |
| 8115 "MOV #0,$dst\n\t" | |
| 8116 "BLT,a .+8\n\t" | |
| 8117 "MOV #-1,$dst" %} | |
| 8118 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8119 ins_pipe(ialu_reg_reg_ialu); | |
| 8120 %} | |
| 8121 | |
| 8122 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8123 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8124 effect(KILL ccr, TEMP tmp); | |
| 8125 ins_cost(DEFAULT_COST*3); | |
| 8126 | |
| 8127 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8128 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8129 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8130 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8131 ins_pipe( cadd_cmpltmask ); | |
| 8132 %} | |
| 8133 | |
| 8134 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8135 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
| 8136 effect( KILL ccr, TEMP tmp); | |
| 8137 ins_cost(DEFAULT_COST*3); | |
| 8138 | |
| 8139 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8140 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8141 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8142 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8143 ins_pipe( cadd_cmpltmask ); | |
| 8144 %} | |
| 8145 | |
| 8146 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 8147 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8148 | |
| 8149 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8150 match(Set dst (ConvD2F src)); | |
| 8151 size(4); | |
| 8152 format %{ "FDTOS $src,$dst" %} | |
| 8153 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8154 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8155 ins_pipe(fcvtD2F); | |
| 8156 %} | |
| 8157 | |
| 8158 | |
| 8159 // Convert a double to an int in a float register. | |
| 8160 // If the double is a NAN, stuff a zero in instead. | |
| 8161 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8162 effect(DEF dst, USE src, KILL fcc0); | |
| 8163 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8164 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8165 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8166 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8167 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8168 "skip:" %} | |
| 8169 ins_encode(form_d2i_helper(src,dst)); | |
| 8170 ins_pipe(fcvtD2I); | |
| 8171 %} | |
| 8172 | |
| 8173 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
| 8174 match(Set dst (ConvD2I src)); | |
| 8175 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8176 expand %{ | |
| 8177 regF tmp; | |
| 8178 convD2I_helper(tmp, src); | |
| 8179 regF_to_stkI(dst, tmp); | |
| 8180 %} | |
| 8181 %} | |
| 8182 | |
| 8183 // Convert a double to a long in a double register. | |
| 8184 // If the double is a NAN, stuff a zero in instead. | |
| 8185 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8186 effect(DEF dst, USE src, KILL fcc0); | |
| 8187 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8188 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8189 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8190 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8191 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8192 "skip:" %} | |
| 8193 ins_encode(form_d2l_helper(src,dst)); | |
| 8194 ins_pipe(fcvtD2L); | |
| 8195 %} | |
| 8196 | |
| 8197 | |
| 8198 // Double to Long conversion | |
| 8199 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
| 8200 match(Set dst (ConvD2L src)); | |
| 8201 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8202 expand %{ | |
| 8203 regD tmp; | |
| 8204 convD2L_helper(tmp, src); | |
| 8205 regD_to_stkL(dst, tmp); | |
| 8206 %} | |
| 8207 %} | |
| 8208 | |
| 8209 | |
| 8210 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8211 match(Set dst (ConvF2D src)); | |
| 8212 format %{ "FSTOD $src,$dst" %} | |
| 8213 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8214 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8215 ins_pipe(fcvtF2D); | |
| 8216 %} | |
| 8217 | |
| 8218 | |
| 8219 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8220 effect(DEF dst, USE src, KILL fcc0); | |
| 8221 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8222 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8223 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8224 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8225 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8226 "skip:" %} | |
| 8227 ins_encode(form_f2i_helper(src,dst)); | |
| 8228 ins_pipe(fcvtF2I); | |
| 8229 %} | |
| 8230 | |
| 8231 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
| 8232 match(Set dst (ConvF2I src)); | |
| 8233 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8234 expand %{ | |
| 8235 regF tmp; | |
| 8236 convF2I_helper(tmp, src); | |
| 8237 regF_to_stkI(dst, tmp); | |
| 8238 %} | |
| 8239 %} | |
| 8240 | |
| 8241 | |
| 8242 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8243 effect(DEF dst, USE src, KILL fcc0); | |
| 8244 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8245 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8246 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8247 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8248 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8249 "skip:" %} | |
| 8250 ins_encode(form_f2l_helper(src,dst)); | |
| 8251 ins_pipe(fcvtF2L); | |
| 8252 %} | |
| 8253 | |
| 8254 // Float to Long conversion | |
| 8255 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
| 8256 match(Set dst (ConvF2L src)); | |
| 8257 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8258 expand %{ | |
| 8259 regD tmp; | |
| 8260 convF2L_helper(tmp, src); | |
| 8261 regD_to_stkL(dst, tmp); | |
| 8262 %} | |
| 8263 %} | |
| 8264 | |
| 8265 | |
| 8266 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8267 effect(USE tmp, DEF dst); | |
| 8268 format %{ "FITOD $tmp,$dst" %} | |
| 8269 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8270 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8271 ins_pipe(fcvtI2D); | |
| 8272 %} | |
| 8273 | |
| 8274 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
| 8275 match(Set dst (ConvI2D src)); | |
| 8276 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8277 expand %{ | |
| 8278 regF tmp; | |
| 8279 stkI_to_regF( tmp, src); | |
| 8280 convI2D_helper( dst, tmp); | |
| 8281 %} | |
| 8282 %} | |
| 8283 | |
| 8284 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
| 8285 match(Set dst (ConvI2D (LoadI mem))); | |
| 8286 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8287 size(8); | |
| 8288 format %{ "LDF $mem,$dst\n\t" | |
| 8289 "FITOD $dst,$dst" %} | |
| 8290 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
|
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8291 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8292 ins_pipe(floadF_mem); |
| 8293 %} | |
| 8294 | |
| 8295 | |
| 8296 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8297 effect(DEF dst, USE tmp); | |
| 8298 format %{ "FITOS $tmp,$dst" %} | |
| 8299 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8300 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8301 ins_pipe(fcvtI2F); | |
| 8302 %} | |
| 8303 | |
| 8304 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
| 8305 match(Set dst (ConvI2F src)); | |
| 8306 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8307 expand %{ | |
| 8308 regF tmp; | |
| 8309 stkI_to_regF(tmp,src); | |
| 8310 convI2F_helper(dst, tmp); | |
| 8311 %} | |
| 8312 %} | |
| 8313 | |
| 8314 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8315 match(Set dst (ConvI2F (LoadI mem))); | |
| 8316 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8317 size(8); | |
| 8318 format %{ "LDF $mem,$dst\n\t" | |
| 8319 "FITOS $dst,$dst" %} | |
| 8320 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
|
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8321 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8322 ins_pipe(floadF_mem); |
| 8323 %} | |
| 8324 | |
| 8325 | |
| 8326 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8327 match(Set dst (ConvI2L src)); | |
| 8328 size(4); | |
| 8329 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8330 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8331 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8332 ins_pipe(ialu_reg_reg); | |
| 8333 %} | |
| 8334 | |
| 8335 // Zero-extend convert int to long | |
| 8336 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8337 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8338 size(4); | |
| 8339 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8340 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8341 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8342 ins_pipe(ialu_reg_reg); | |
| 8343 %} | |
| 8344 | |
| 8345 // Zero-extend long | |
| 8346 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8347 match(Set dst (AndL src mask) ); | |
| 8348 size(4); | |
| 8349 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8350 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8351 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8352 ins_pipe(ialu_reg_reg); | |
| 8353 %} | |
| 8354 | |
| 8355 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
| 8356 match(Set dst (MoveF2I src)); | |
| 8357 effect(DEF dst, USE src); | |
| 8358 ins_cost(MEMORY_REF_COST); | |
| 8359 | |
| 8360 size(4); | |
| 8361 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8362 opcode(Assembler::lduw_op3); | |
|
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8363 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8364 ins_pipe(iload_mem); |
| 8365 %} | |
| 8366 | |
| 8367 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8368 match(Set dst (MoveI2F src)); | |
| 8369 effect(DEF dst, USE src); | |
| 8370 ins_cost(MEMORY_REF_COST); | |
| 8371 | |
| 8372 size(4); | |
| 8373 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8374 opcode(Assembler::ldf_op3); | |
|
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8375 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8376 ins_pipe(floadF_stk); |
| 8377 %} | |
| 8378 | |
| 8379 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8380 match(Set dst (MoveD2L src)); | |
| 8381 effect(DEF dst, USE src); | |
| 8382 ins_cost(MEMORY_REF_COST); | |
| 8383 | |
| 8384 size(4); | |
| 8385 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8386 opcode(Assembler::ldx_op3); | |
|
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8387 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8388 ins_pipe(iload_mem); |
| 8389 %} | |
| 8390 | |
| 8391 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8392 match(Set dst (MoveL2D src)); | |
| 8393 effect(DEF dst, USE src); | |
| 8394 ins_cost(MEMORY_REF_COST); | |
| 8395 | |
| 8396 size(4); | |
| 8397 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8398 opcode(Assembler::lddf_op3); | |
|
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8399 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8400 ins_pipe(floadD_stk); |
| 8401 %} | |
| 8402 | |
| 8403 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8404 match(Set dst (MoveF2I src)); | |
| 8405 effect(DEF dst, USE src); | |
| 8406 ins_cost(MEMORY_REF_COST); | |
| 8407 | |
| 8408 size(4); | |
| 8409 format %{ "STF $src,$dst\t!MoveF2I" %} | |
| 8410 opcode(Assembler::stf_op3); | |
|
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8411 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8412 ins_pipe(fstoreF_stk_reg); |
| 8413 %} | |
| 8414 | |
| 8415 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8416 match(Set dst (MoveI2F src)); | |
| 8417 effect(DEF dst, USE src); | |
| 8418 ins_cost(MEMORY_REF_COST); | |
| 8419 | |
| 8420 size(4); | |
| 8421 format %{ "STW $src,$dst\t!MoveI2F" %} | |
| 8422 opcode(Assembler::stw_op3); | |
|
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8423 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8424 ins_pipe(istore_mem_reg); |
| 8425 %} | |
| 8426 | |
| 8427 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8428 match(Set dst (MoveD2L src)); | |
| 8429 effect(DEF dst, USE src); | |
| 8430 ins_cost(MEMORY_REF_COST); | |
| 8431 | |
| 8432 size(4); | |
| 8433 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
| 8434 opcode(Assembler::stdf_op3); | |
|
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8435 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8436 ins_pipe(fstoreD_stk_reg); |
| 8437 %} | |
| 8438 | |
| 8439 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8440 match(Set dst (MoveL2D src)); | |
| 8441 effect(DEF dst, USE src); | |
| 8442 ins_cost(MEMORY_REF_COST); | |
| 8443 | |
| 8444 size(4); | |
| 8445 format %{ "STX $src,$dst\t!MoveL2D" %} | |
| 8446 opcode(Assembler::stx_op3); | |
|
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8447 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8448 ins_pipe(istore_mem_reg); |
| 8449 %} | |
| 8450 | |
| 8451 | |
| 8452 //----------- | |
| 8453 // Long to Double conversion using V8 opcodes. | |
| 8454 // Still useful because cheetah traps and becomes | |
| 8455 // amazingly slow for some common numbers. | |
| 8456 | |
| 8457 // Magic constant, 0x43300000 | |
| 8458 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8459 effect(DEF dst); | |
| 8460 size(4); | |
| 8461 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8462 ins_encode(SetHi22(0x43300000, dst)); | |
| 8463 ins_pipe(ialu_none); | |
| 8464 %} | |
| 8465 | |
| 8466 // Magic constant, 0x41f00000 | |
| 8467 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8468 effect(DEF dst); | |
| 8469 size(4); | |
| 8470 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8471 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8472 ins_pipe(ialu_none); | |
| 8473 %} | |
| 8474 | |
| 8475 // Construct a double from two float halves | |
| 8476 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8477 effect(DEF dst, USE src1, USE src2); | |
| 8478 size(8); | |
| 8479 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8480 "FMOVS $src2.lo,$dst.lo" %} | |
| 8481 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8482 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8483 ins_pipe(faddD_reg_reg); | |
| 8484 %} | |
| 8485 | |
| 8486 // Convert integer in high half of a double register (in the lower half of | |
| 8487 // the double register file) to double | |
| 8488 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8489 effect(DEF dst, USE src); | |
| 8490 size(4); | |
| 8491 format %{ "FITOD $src,$dst" %} | |
| 8492 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8493 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8494 ins_pipe(fcvtLHi2D); | |
| 8495 %} | |
| 8496 | |
| 8497 // Add float double precision | |
| 8498 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8499 effect(DEF dst, USE src1, USE src2); | |
| 8500 size(4); | |
| 8501 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8502 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8503 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8504 ins_pipe(faddD_reg_reg); | |
| 8505 %} | |
| 8506 | |
| 8507 // Sub float double precision | |
| 8508 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8509 effect(DEF dst, USE src1, USE src2); | |
| 8510 size(4); | |
| 8511 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8512 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8513 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8514 ins_pipe(faddD_reg_reg); | |
| 8515 %} | |
| 8516 | |
| 8517 // Mul float double precision | |
| 8518 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8519 effect(DEF dst, USE src1, USE src2); | |
| 8520 size(4); | |
| 8521 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8522 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8523 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8524 ins_pipe(fmulD_reg_reg); | |
| 8525 %} | |
| 8526 | |
| 8527 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8528 match(Set dst (ConvL2D src)); | |
| 8529 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8530 | |
| 8531 expand %{ | |
| 8532 regD_low tmpsrc; | |
| 8533 iRegI ix43300000; | |
| 8534 iRegI ix41f00000; | |
| 8535 stackSlotL lx43300000; | |
| 8536 stackSlotL lx41f00000; | |
| 8537 regD_low dx43300000; | |
| 8538 regD dx41f00000; | |
| 8539 regD tmp1; | |
| 8540 regD_low tmp2; | |
| 8541 regD tmp3; | |
| 8542 regD tmp4; | |
| 8543 | |
| 8544 stkL_to_regD(tmpsrc, src); | |
| 8545 | |
| 8546 loadConI_x43300000(ix43300000); | |
| 8547 loadConI_x41f00000(ix41f00000); | |
| 8548 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8549 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8550 stkL_to_regD(dx43300000, lx43300000); | |
| 8551 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8552 | |
| 8553 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8554 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8555 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8556 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8557 addD_regD_regD(dst, tmp3, tmp4); | |
| 8558 %} | |
| 8559 %} | |
| 8560 | |
| 8561 // Long to Double conversion using fast fxtof | |
| 8562 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8563 effect(DEF dst, USE tmp); | |
| 8564 size(4); | |
| 8565 format %{ "FXTOD $tmp,$dst" %} | |
| 8566 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8567 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8568 ins_pipe(fcvtL2D); | |
| 8569 %} | |
| 8570 | |
| 8571 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
| 8572 predicate(VM_Version::has_fast_fxtof()); | |
| 8573 match(Set dst (ConvL2D src)); | |
| 8574 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8575 expand %{ | |
| 8576 regD tmp; | |
| 8577 stkL_to_regD(tmp, src); | |
| 8578 convL2D_helper(dst, tmp); | |
| 8579 %} | |
| 8580 %} | |
| 8581 | |
| 8582 //----------- | |
| 8583 // Long to Float conversion using V8 opcodes. | |
| 8584 // Still useful because cheetah traps and becomes | |
| 8585 // amazingly slow for some common numbers. | |
| 8586 | |
| 8587 // Long to Float conversion using fast fxtof | |
| 8588 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8589 effect(DEF dst, USE tmp); | |
| 8590 size(4); | |
| 8591 format %{ "FXTOS $tmp,$dst" %} | |
| 8592 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8593 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8594 ins_pipe(fcvtL2F); | |
| 8595 %} | |
| 8596 | |
| 8597 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
| 8598 match(Set dst (ConvL2F src)); | |
| 8599 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8600 expand %{ | |
| 8601 regD tmp; | |
| 8602 stkL_to_regD(tmp, src); | |
| 8603 convL2F_helper(dst, tmp); | |
| 8604 %} | |
| 8605 %} | |
| 8606 //----------- | |
| 8607 | |
| 8608 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8609 match(Set dst (ConvL2I src)); | |
| 8610 #ifndef _LP64 | |
| 8611 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8612 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8613 ins_pipe(ialu_move_reg_I_to_L); | |
| 8614 #else | |
| 8615 size(4); | |
| 8616 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8617 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8618 ins_pipe(ialu_reg); | |
| 8619 #endif | |
| 8620 %} | |
| 8621 | |
| 8622 // Register Shift Right Immediate | |
| 8623 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8624 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8625 | |
| 8626 size(4); | |
| 8627 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8628 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8629 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8630 ins_pipe(ialu_reg_imm); | |
| 8631 %} | |
| 8632 | |
| 8633 // Replicate scalar to packed byte values in Double register | |
| 8634 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8635 effect(DEF dst, USE src); | |
| 8636 format %{ "SLLX $src,56,$dst\n\t" | |
| 8637 "SRLX $dst, 8,O7\n\t" | |
| 8638 "OR $dst,O7,$dst\n\t" | |
| 8639 "SRLX $dst,16,O7\n\t" | |
| 8640 "OR $dst,O7,$dst\n\t" | |
| 8641 "SRLX $dst,32,O7\n\t" | |
| 8642 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8643 ins_encode( enc_repl8b(src, dst)); | |
| 8644 ins_pipe(ialu_reg); | |
| 8645 %} | |
| 8646 | |
| 8647 // Replicate scalar to packed byte values in Double register | |
| 8648 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8649 match(Set dst (Replicate8B src)); | |
| 8650 expand %{ | |
| 8651 iRegL tmp; | |
| 8652 Repl8B_reg_helper(tmp, src); | |
| 8653 regL_to_stkD(dst, tmp); | |
| 8654 %} | |
| 8655 %} | |
| 8656 | |
| 8657 // Replicate scalar constant to packed byte values in Double register | |
| 2008 | 8658 instruct Repl8B_immI(regD dst, immI13 con) %{ |
| 8659 match(Set dst (Replicate8B con)); | |
| 8660 size(4); | |
| 8661 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} | |
| 8662 ins_encode %{ | |
| 8663 // XXX This is a quick fix for 6833573. | |
| 8664 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); | |
| 8665 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), as_DoubleFloatRegister($dst$$reg)); | |
| 8666 %} | |
| 0 | 8667 ins_pipe(loadConFD); |
| 8668 %} | |
| 8669 | |
| 8670 // Replicate scalar to packed char values into stack slot | |
| 8671 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8672 effect(DEF dst, USE src); | |
| 8673 format %{ "SLLX $src,48,$dst\n\t" | |
| 8674 "SRLX $dst,16,O7\n\t" | |
| 8675 "OR $dst,O7,$dst\n\t" | |
| 8676 "SRLX $dst,32,O7\n\t" | |
| 8677 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8678 ins_encode( enc_repl4s(src, dst) ); | |
| 8679 ins_pipe(ialu_reg); | |
| 8680 %} | |
| 8681 | |
| 8682 // Replicate scalar to packed char values into stack slot | |
| 8683 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8684 match(Set dst (Replicate4C src)); | |
| 8685 expand %{ | |
| 8686 iRegL tmp; | |
| 8687 Repl4C_reg_helper(tmp, src); | |
| 8688 regL_to_stkD(dst, tmp); | |
| 8689 %} | |
| 8690 %} | |
| 8691 | |
| 8692 // Replicate scalar constant to packed char values in Double register | |
| 2008 | 8693 instruct Repl4C_immI(regD dst, immI con) %{ |
| 8694 match(Set dst (Replicate4C con)); | |
| 8695 size(4); | |
| 8696 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} | |
| 8697 ins_encode %{ | |
| 8698 // XXX This is a quick fix for 6833573. | |
| 8699 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
| 8700 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg)); | |
| 8701 %} | |
| 0 | 8702 ins_pipe(loadConFD); |
| 8703 %} | |
| 8704 | |
| 8705 // Replicate scalar to packed short values into stack slot | |
| 8706 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8707 effect(DEF dst, USE src); | |
| 8708 format %{ "SLLX $src,48,$dst\n\t" | |
| 8709 "SRLX $dst,16,O7\n\t" | |
| 8710 "OR $dst,O7,$dst\n\t" | |
| 8711 "SRLX $dst,32,O7\n\t" | |
| 8712 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8713 ins_encode( enc_repl4s(src, dst) ); | |
| 8714 ins_pipe(ialu_reg); | |
| 8715 %} | |
| 8716 | |
| 8717 // Replicate scalar to packed short values into stack slot | |
| 8718 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8719 match(Set dst (Replicate4S src)); | |
| 8720 expand %{ | |
| 8721 iRegL tmp; | |
| 8722 Repl4S_reg_helper(tmp, src); | |
| 8723 regL_to_stkD(dst, tmp); | |
| 8724 %} | |
| 8725 %} | |
| 8726 | |
| 8727 // Replicate scalar constant to packed short values in Double register | |
| 2008 | 8728 instruct Repl4S_immI(regD dst, immI con) %{ |
| 8729 match(Set dst (Replicate4S con)); | |
| 8730 size(4); | |
| 8731 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} | |
| 8732 ins_encode %{ | |
| 8733 // XXX This is a quick fix for 6833573. | |
| 8734 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
| 8735 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), as_DoubleFloatRegister($dst$$reg)); | |
| 8736 %} | |
| 0 | 8737 ins_pipe(loadConFD); |
| 8738 %} | |
| 8739 | |
| 8740 // Replicate scalar to packed int values in Double register | |
| 8741 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8742 effect(DEF dst, USE src); | |
| 8743 format %{ "SLLX $src,32,$dst\n\t" | |
| 8744 "SRLX $dst,32,O7\n\t" | |
| 8745 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8746 ins_encode( enc_repl2i(src, dst)); | |
| 8747 ins_pipe(ialu_reg); | |
| 8748 %} | |
| 8749 | |
| 8750 // Replicate scalar to packed int values in Double register | |
| 8751 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8752 match(Set dst (Replicate2I src)); | |
| 8753 expand %{ | |
| 8754 iRegL tmp; | |
| 8755 Repl2I_reg_helper(tmp, src); | |
| 8756 regL_to_stkD(dst, tmp); | |
| 8757 %} | |
| 8758 %} | |
| 8759 | |
| 8760 // Replicate scalar zero constant to packed int values in Double register | |
| 2008 | 8761 instruct Repl2I_immI(regD dst, immI con) %{ |
| 8762 match(Set dst (Replicate2I con)); | |
| 8763 size(4); | |
| 8764 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} | |
| 8765 ins_encode %{ | |
| 8766 // XXX This is a quick fix for 6833573. | |
| 8767 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); | |
| 8768 __ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), as_DoubleFloatRegister($dst$$reg)); | |
| 8769 %} | |
| 0 | 8770 ins_pipe(loadConFD); |
| 8771 %} | |
| 8772 | |
| 8773 //----------Control Flow Instructions------------------------------------------ | |
| 8774 // Compare Instructions | |
| 8775 // Compare Integers | |
| 8776 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8777 match(Set icc (CmpI op1 op2)); | |
| 8778 effect( DEF icc, USE op1, USE op2 ); | |
| 8779 | |
| 8780 size(4); | |
| 8781 format %{ "CMP $op1,$op2" %} | |
| 8782 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8783 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8784 ins_pipe(ialu_cconly_reg_reg); | |
| 8785 %} | |
| 8786 | |
| 8787 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8788 match(Set icc (CmpU op1 op2)); | |
| 8789 | |
| 8790 size(4); | |
| 8791 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8792 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8793 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8794 ins_pipe(ialu_cconly_reg_reg); | |
| 8795 %} | |
| 8796 | |
| 8797 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8798 match(Set icc (CmpI op1 op2)); | |
| 8799 effect( DEF icc, USE op1 ); | |
| 8800 | |
| 8801 size(4); | |
| 8802 format %{ "CMP $op1,$op2" %} | |
| 8803 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8804 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8805 ins_pipe(ialu_cconly_reg_imm); | |
| 8806 %} | |
| 8807 | |
| 8808 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8809 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8810 | |
| 8811 size(4); | |
| 8812 format %{ "BTST $op2,$op1" %} | |
| 8813 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8814 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8815 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8816 %} | |
| 8817 | |
| 8818 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8819 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8820 | |
| 8821 size(4); | |
| 8822 format %{ "BTST $op2,$op1" %} | |
| 8823 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8824 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8825 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8826 %} | |
| 8827 | |
| 8828 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8829 match(Set xcc (CmpL op1 op2)); | |
| 8830 effect( DEF xcc, USE op1, USE op2 ); | |
| 8831 | |
| 8832 size(4); | |
| 8833 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8834 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8835 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8836 ins_pipe(ialu_cconly_reg_reg); | |
| 8837 %} | |
| 8838 | |
| 8839 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8840 match(Set xcc (CmpL op1 con)); | |
| 8841 effect( DEF xcc, USE op1, USE con ); | |
| 8842 | |
| 8843 size(4); | |
| 8844 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8845 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8846 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8847 ins_pipe(ialu_cconly_reg_reg); | |
| 8848 %} | |
| 8849 | |
| 8850 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8851 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8852 effect( DEF xcc, USE op1, USE op2 ); | |
| 8853 | |
| 8854 size(4); | |
| 8855 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8856 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8857 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8858 ins_pipe(ialu_cconly_reg_reg); | |
| 8859 %} | |
| 8860 | |
| 8861 // useful for checking the alignment of a pointer: | |
| 8862 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8863 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8864 effect( DEF xcc, USE op1, USE con ); | |
| 8865 | |
| 8866 size(4); | |
| 8867 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8868 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8869 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8870 ins_pipe(ialu_cconly_reg_reg); | |
| 8871 %} | |
| 8872 | |
| 8873 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8874 match(Set icc (CmpU op1 op2)); | |
| 8875 | |
| 8876 size(4); | |
| 8877 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8878 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8879 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8880 ins_pipe(ialu_cconly_reg_imm); | |
| 8881 %} | |
| 8882 | |
| 8883 // Compare Pointers | |
| 8884 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8885 match(Set pcc (CmpP op1 op2)); | |
| 8886 | |
| 8887 size(4); | |
| 8888 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8889 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8890 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8891 ins_pipe(ialu_cconly_reg_reg); | |
| 8892 %} | |
| 8893 | |
| 8894 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8895 match(Set pcc (CmpP op1 op2)); | |
| 8896 | |
| 8897 size(4); | |
| 8898 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8899 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8900 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8901 ins_pipe(ialu_cconly_reg_imm); | |
| 8902 %} | |
| 8903 | |
|
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8904 // Compare Narrow oops |
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8905 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8906 match(Set icc (CmpN op1 op2)); |
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8907 |
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8908 size(4); |
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8909 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8910 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8911 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8912 ins_pipe(ialu_cconly_reg_reg); |
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8913 %} |
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8914 |
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8915 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8916 match(Set icc (CmpN op1 op2)); |
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8917 |
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8918 size(4); |
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8919 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8920 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8921 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8922 ins_pipe(ialu_cconly_reg_imm); |
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8923 %} |
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8924 |
| 0 | 8925 //----------Max and Min-------------------------------------------------------- |
| 8926 // Min Instructions | |
| 8927 // Conditional move for min | |
| 8928 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8929 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8930 | |
| 8931 size(4); | |
| 8932 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 8933 opcode(Assembler::less); | |
| 8934 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8935 ins_pipe(ialu_reg_flags); | |
| 8936 %} | |
| 8937 | |
| 8938 // Min Register with Register. | |
| 8939 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 8940 match(Set op2 (MinI op1 op2)); | |
| 8941 ins_cost(DEFAULT_COST*2); | |
| 8942 expand %{ | |
| 8943 flagsReg icc; | |
| 8944 compI_iReg(icc,op1,op2); | |
| 8945 cmovI_reg_lt(op2,op1,icc); | |
| 8946 %} | |
| 8947 %} | |
| 8948 | |
| 8949 // Max Instructions | |
| 8950 // Conditional move for max | |
| 8951 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8952 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8953 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 8954 opcode(Assembler::greater); | |
| 8955 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8956 ins_pipe(ialu_reg_flags); | |
| 8957 %} | |
| 8958 | |
| 8959 // Max Register with Register | |
| 8960 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 8961 match(Set op2 (MaxI op1 op2)); | |
| 8962 ins_cost(DEFAULT_COST*2); | |
| 8963 expand %{ | |
| 8964 flagsReg icc; | |
| 8965 compI_iReg(icc,op1,op2); | |
| 8966 cmovI_reg_gt(op2,op1,icc); | |
| 8967 %} | |
| 8968 %} | |
| 8969 | |
| 8970 | |
| 8971 //----------Float Compares---------------------------------------------------- | |
| 8972 // Compare floating, generate condition code | |
| 8973 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 8974 match(Set fcc (CmpF src1 src2)); | |
| 8975 | |
| 8976 size(4); | |
| 8977 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 8978 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 8979 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 8980 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 8981 %} | |
| 8982 | |
| 8983 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 8984 match(Set fcc (CmpD src1 src2)); | |
| 8985 | |
| 8986 size(4); | |
| 8987 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 8988 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 8989 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 8990 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 8991 %} | |
| 8992 | |
| 8993 | |
| 8994 // Compare floating, generate -1,0,1 | |
| 8995 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 8996 match(Set dst (CmpF3 src1 src2)); | |
| 8997 effect(KILL fcc0); | |
| 8998 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8999 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 9000 // Primary = float | |
| 9001 opcode( true ); | |
| 9002 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9003 ins_pipe( floating_cmp ); | |
| 9004 %} | |
| 9005 | |
| 9006 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 9007 match(Set dst (CmpD3 src1 src2)); | |
| 9008 effect(KILL fcc0); | |
| 9009 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9010 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 9011 // Primary = double (not float) | |
| 9012 opcode( false ); | |
| 9013 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9014 ins_pipe( floating_cmp ); | |
| 9015 %} | |
| 9016 | |
| 9017 //----------Branches--------------------------------------------------------- | |
| 9018 // Jump | |
| 9019 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9020 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9021 match(Jump switch_val); | |
| 9022 | |
| 9023 ins_cost(350); | |
| 9024 | |
| 2008 | 9025 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9026 "LD [O7 + $switch_val], O7\n\t" | |
| 0 | 9027 "JUMP O7" |
| 9028 %} | |
| 2008 | 9029 ins_encode %{ |
| 9030 // Calculate table address into a register. | |
| 9031 Register table_reg; | |
| 9032 Register label_reg = O7; | |
| 9033 if (constant_offset() == 0) { | |
| 9034 table_reg = $constanttablebase; | |
| 9035 } else { | |
| 9036 table_reg = O7; | |
| 9037 __ add($constanttablebase, $constantoffset, table_reg); | |
| 9038 } | |
| 9039 | |
| 9040 // Jump to base address + switch value | |
| 9041 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9042 __ jmp(label_reg, G0); | |
| 9043 __ delayed()->nop(); | |
| 9044 %} | |
| 0 | 9045 ins_pc_relative(1); |
| 9046 ins_pipe(ialu_reg_reg); | |
| 9047 %} | |
| 9048 | |
| 9049 // Direct Branch. Use V8 version with longer range. | |
| 9050 instruct branch(label labl) %{ | |
| 9051 match(Goto); | |
| 9052 effect(USE labl); | |
| 9053 | |
| 9054 size(8); | |
| 9055 ins_cost(BRANCH_COST); | |
| 9056 format %{ "BA $labl" %} | |
| 9057 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
| 9058 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
| 9059 ins_encode( enc_ba( labl ) ); | |
| 9060 ins_pc_relative(1); | |
| 9061 ins_pipe(br); | |
| 9062 %} | |
| 9063 | |
| 9064 // Conditional Direct Branch | |
| 9065 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9066 match(If cmp icc); | |
| 9067 effect(USE labl); | |
| 9068 | |
| 9069 size(8); | |
| 9070 ins_cost(BRANCH_COST); | |
| 9071 format %{ "BP$cmp $icc,$labl" %} | |
| 9072 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9073 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9074 ins_pc_relative(1); | |
| 9075 ins_pipe(br_cc); | |
| 9076 %} | |
| 9077 | |
| 9078 // Branch-on-register tests all 64 bits. We assume that values | |
| 9079 // in 64-bit registers always remains zero or sign extended | |
| 9080 // unless our code munges the high bits. Interrupts can chop | |
| 9081 // the high order bits to zero or sign at any time. | |
| 9082 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9083 match(If cmp (CmpI op1 zero)); | |
| 9084 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9085 effect(USE labl); | |
| 9086 | |
| 9087 size(8); | |
| 9088 ins_cost(BRANCH_COST); | |
| 9089 format %{ "BR$cmp $op1,$labl" %} | |
| 9090 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9091 ins_pc_relative(1); | |
| 9092 ins_pipe(br_reg); | |
| 9093 %} | |
| 9094 | |
| 9095 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9096 match(If cmp (CmpP op1 null)); | |
| 9097 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9098 effect(USE labl); | |
| 9099 | |
| 9100 size(8); | |
| 9101 ins_cost(BRANCH_COST); | |
| 9102 format %{ "BR$cmp $op1,$labl" %} | |
| 9103 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9104 ins_pc_relative(1); | |
| 9105 ins_pipe(br_reg); | |
| 9106 %} | |
| 9107 | |
| 9108 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9109 match(If cmp (CmpL op1 zero)); | |
| 9110 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9111 effect(USE labl); | |
| 9112 | |
| 9113 size(8); | |
| 9114 ins_cost(BRANCH_COST); | |
| 9115 format %{ "BR$cmp $op1,$labl" %} | |
| 9116 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9117 ins_pc_relative(1); | |
| 9118 ins_pipe(br_reg); | |
| 9119 %} | |
| 9120 | |
| 9121 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9122 match(If cmp icc); | |
| 9123 effect(USE labl); | |
| 9124 | |
| 9125 format %{ "BP$cmp $icc,$labl" %} | |
| 9126 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9127 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9128 ins_pc_relative(1); | |
| 9129 ins_pipe(br_cc); | |
| 9130 %} | |
| 9131 | |
| 9132 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9133 match(If cmp pcc); | |
| 9134 effect(USE labl); | |
| 9135 | |
| 9136 size(8); | |
| 9137 ins_cost(BRANCH_COST); | |
| 9138 format %{ "BP$cmp $pcc,$labl" %} | |
| 9139 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9140 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
| 9141 ins_pc_relative(1); | |
| 9142 ins_pipe(br_cc); | |
| 9143 %} | |
| 9144 | |
| 9145 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9146 match(If cmp fcc); | |
| 9147 effect(USE labl); | |
| 9148 | |
| 9149 size(8); | |
| 9150 ins_cost(BRANCH_COST); | |
| 9151 format %{ "FBP$cmp $fcc,$labl" %} | |
| 9152 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9153 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
| 9154 ins_pc_relative(1); | |
| 9155 ins_pipe(br_fcc); | |
| 9156 %} | |
| 9157 | |
| 9158 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9159 match(CountedLoopEnd cmp icc); | |
| 9160 effect(USE labl); | |
| 9161 | |
| 9162 size(8); | |
| 9163 ins_cost(BRANCH_COST); | |
| 9164 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9165 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9166 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9167 ins_pc_relative(1); | |
| 9168 ins_pipe(br_cc); | |
| 9169 %} | |
| 9170 | |
| 9171 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9172 match(CountedLoopEnd cmp icc); | |
| 9173 effect(USE labl); | |
| 9174 | |
| 9175 size(8); | |
| 9176 ins_cost(BRANCH_COST); | |
| 9177 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9178 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9179 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9180 ins_pc_relative(1); | |
| 9181 ins_pipe(br_cc); | |
| 9182 %} | |
| 9183 | |
| 9184 // ============================================================================ | |
| 9185 // Long Compare | |
| 9186 // | |
| 9187 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9188 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9189 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9190 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9191 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9192 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9193 // NE test is negated from that. | |
| 9194 | |
| 9195 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9196 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9197 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9198 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9199 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9200 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9201 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9202 // both forms beat the trinary form of long-compare and both are very useful | |
| 9203 // on Intel which has so few registers. | |
| 9204 | |
| 9205 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9206 match(If cmp xcc); | |
| 9207 effect(USE labl); | |
| 9208 | |
| 9209 size(8); | |
| 9210 ins_cost(BRANCH_COST); | |
| 9211 format %{ "BP$cmp $xcc,$labl" %} | |
| 9212 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9213 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
| 9214 ins_pc_relative(1); | |
| 9215 ins_pipe(br_cc); | |
| 9216 %} | |
| 9217 | |
| 9218 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9219 // This is the test to avoid. | |
| 9220 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9221 match(Set dst (CmpL3 src1 src2) ); | |
| 9222 effect( KILL ccr ); | |
| 9223 ins_cost(6*DEFAULT_COST); | |
| 9224 size(24); | |
| 9225 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9226 "\tBLT,a,pn done\n" | |
| 9227 "\tMOV -1,$dst\t! delay slot\n" | |
| 9228 "\tBGT,a,pn done\n" | |
| 9229 "\tMOV 1,$dst\t! delay slot\n" | |
| 9230 "\tCLR $dst\n" | |
| 9231 "done:" %} | |
| 9232 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9233 ins_pipe(cmpL_reg); | |
| 9234 %} | |
| 9235 | |
| 9236 // Conditional move | |
| 9237 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9238 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9239 ins_cost(150); | |
| 9240 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9241 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9242 ins_pipe(ialu_reg); | |
| 9243 %} | |
| 9244 | |
| 9245 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9246 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9247 ins_cost(140); | |
| 9248 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9249 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9250 ins_pipe(ialu_imm); | |
| 9251 %} | |
| 9252 | |
| 9253 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9254 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9255 ins_cost(150); | |
| 9256 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9257 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9258 ins_pipe(ialu_reg); | |
| 9259 %} | |
| 9260 | |
| 9261 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9262 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9263 ins_cost(140); | |
| 9264 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9265 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9266 ins_pipe(ialu_imm); | |
| 9267 %} | |
| 9268 | |
|
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9269 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9270 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9271 ins_cost(150); |
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9272 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9273 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9274 ins_pipe(ialu_reg); |
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9275 %} |
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9276 |
| 0 | 9277 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9278 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9279 ins_cost(150); | |
| 9280 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9281 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9282 ins_pipe(ialu_reg); | |
| 9283 %} | |
| 9284 | |
| 9285 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9286 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9287 ins_cost(140); | |
| 9288 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9289 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9290 ins_pipe(ialu_imm); | |
| 9291 %} | |
| 9292 | |
| 9293 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9294 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9295 ins_cost(150); | |
| 9296 opcode(0x101); | |
| 9297 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9298 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9299 ins_pipe(int_conditional_float_move); | |
| 9300 %} | |
| 9301 | |
| 9302 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9303 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9304 ins_cost(150); | |
| 9305 opcode(0x102); | |
| 9306 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9307 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9308 ins_pipe(int_conditional_float_move); | |
| 9309 %} | |
| 9310 | |
| 9311 // ============================================================================ | |
| 9312 // Safepoint Instruction | |
| 9313 instruct safePoint_poll(iRegP poll) %{ | |
| 9314 match(SafePoint poll); | |
| 9315 effect(USE poll); | |
| 9316 | |
| 9317 size(4); | |
| 9318 #ifdef _LP64 | |
| 9319 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9320 #else | |
| 9321 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9322 #endif | |
| 9323 ins_encode %{ | |
| 9324 __ relocate(relocInfo::poll_type); | |
| 9325 __ ld_ptr($poll$$Register, 0, G0); | |
| 9326 %} | |
| 9327 ins_pipe(loadPollP); | |
| 9328 %} | |
| 9329 | |
| 9330 // ============================================================================ | |
| 9331 // Call Instructions | |
| 9332 // Call Java Static Instruction | |
| 9333 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9334 match(CallStaticJava); | |
| 1567 | 9335 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9336 effect(USE meth); |
| 9337 | |
| 9338 size(8); | |
| 9339 ins_cost(CALL_COST); | |
| 9340 format %{ "CALL,static ; NOP ==> " %} | |
| 9341 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9342 ins_pc_relative(1); | |
| 9343 ins_pipe(simple_call); | |
| 9344 %} | |
| 9345 | |
| 1567 | 9346 // Call Java Static Instruction (method handle version) |
| 9347 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9348 match(CallStaticJava); | |
| 9349 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9350 effect(USE meth, KILL l7_mh_SP_save); | |
| 9351 | |
| 9352 size(8); | |
| 9353 ins_cost(CALL_COST); | |
| 9354 format %{ "CALL,static/MethodHandle" %} | |
| 9355 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9356 ins_pc_relative(1); | |
| 9357 ins_pipe(simple_call); | |
| 9358 %} | |
| 9359 | |
| 0 | 9360 // Call Java Dynamic Instruction |
| 9361 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9362 match(CallDynamicJava); | |
| 9363 effect(USE meth); | |
| 9364 | |
| 9365 ins_cost(CALL_COST); | |
| 9366 format %{ "SET (empty),R_G5\n\t" | |
| 9367 "CALL,dynamic ; NOP ==> " %} | |
| 9368 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9369 ins_pc_relative(1); | |
| 9370 ins_pipe(call); | |
| 9371 %} | |
| 9372 | |
| 9373 // Call Runtime Instruction | |
| 9374 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9375 match(CallRuntime); | |
| 9376 effect(USE meth, KILL l7); | |
| 9377 ins_cost(CALL_COST); | |
| 9378 format %{ "CALL,runtime" %} | |
| 9379 ins_encode( Java_To_Runtime( meth ), | |
| 9380 call_epilog, adjust_long_from_native_call ); | |
| 9381 ins_pc_relative(1); | |
| 9382 ins_pipe(simple_call); | |
| 9383 %} | |
| 9384 | |
| 9385 // Call runtime without safepoint - same as CallRuntime | |
| 9386 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9387 match(CallLeaf); | |
| 9388 effect(USE meth, KILL l7); | |
| 9389 ins_cost(CALL_COST); | |
| 9390 format %{ "CALL,runtime leaf" %} | |
| 9391 ins_encode( Java_To_Runtime( meth ), | |
| 9392 call_epilog, | |
| 9393 adjust_long_from_native_call ); | |
| 9394 ins_pc_relative(1); | |
| 9395 ins_pipe(simple_call); | |
| 9396 %} | |
| 9397 | |
| 9398 // Call runtime without safepoint - same as CallLeaf | |
| 9399 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9400 match(CallLeafNoFP); | |
| 9401 effect(USE meth, KILL l7); | |
| 9402 ins_cost(CALL_COST); | |
| 9403 format %{ "CALL,runtime leaf nofp" %} | |
| 9404 ins_encode( Java_To_Runtime( meth ), | |
| 9405 call_epilog, | |
| 9406 adjust_long_from_native_call ); | |
| 9407 ins_pc_relative(1); | |
| 9408 ins_pipe(simple_call); | |
| 9409 %} | |
| 9410 | |
| 9411 // Tail Call; Jump from runtime stub to Java code. | |
| 9412 // Also known as an 'interprocedural jump'. | |
| 9413 // Target of jump will eventually return to caller. | |
| 9414 // TailJump below removes the return address. | |
| 9415 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 9416 match(TailCall jump_target method_oop ); | |
| 9417 | |
| 9418 ins_cost(CALL_COST); | |
| 9419 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 9420 ins_encode(form_jmpl(jump_target)); | |
| 9421 ins_pipe(tail_call); | |
| 9422 %} | |
| 9423 | |
| 9424 | |
| 9425 // Return Instruction | |
| 9426 instruct Ret() %{ | |
| 9427 match(Return); | |
| 9428 | |
| 9429 // The epilogue node did the ret already. | |
| 9430 size(0); | |
| 9431 format %{ "! return" %} | |
| 9432 ins_encode(); | |
| 9433 ins_pipe(empty); | |
| 9434 %} | |
| 9435 | |
| 9436 | |
| 9437 // Tail Jump; remove the return address; jump to target. | |
| 9438 // TailCall above leaves the return address around. | |
| 9439 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 9440 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 9441 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 9442 // in %i0. | |
| 9443 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 9444 match( TailJump jump_target ex_oop ); | |
| 9445 ins_cost(CALL_COST); | |
| 9446 format %{ "! discard R_O7\n\t" | |
| 9447 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 9448 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 9449 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 9450 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 9451 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 9452 ins_pipe(tail_call); | |
| 9453 %} | |
| 9454 | |
| 9455 // Create exception oop: created by stack-crawling runtime code. | |
| 9456 // Created exception is now available to this handler, and is setup | |
| 9457 // just prior to jumping to this handler. No code emitted. | |
| 9458 instruct CreateException( o0RegP ex_oop ) | |
| 9459 %{ | |
| 9460 match(Set ex_oop (CreateEx)); | |
| 9461 ins_cost(0); | |
| 9462 | |
| 9463 size(0); | |
| 9464 // use the following format syntax | |
| 9465 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 9466 ins_encode(); | |
| 9467 ins_pipe(empty); | |
| 9468 %} | |
| 9469 | |
| 9470 | |
| 9471 // Rethrow exception: | |
| 9472 // The exception oop will come in the first argument position. | |
| 9473 // Then JUMP (not call) to the rethrow stub code. | |
| 9474 instruct RethrowException() | |
| 9475 %{ | |
| 9476 match(Rethrow); | |
| 9477 ins_cost(CALL_COST); | |
| 9478 | |
| 9479 // use the following format syntax | |
| 9480 format %{ "Jmp rethrow_stub" %} | |
| 9481 ins_encode(enc_rethrow); | |
| 9482 ins_pipe(tail_call); | |
| 9483 %} | |
| 9484 | |
| 9485 | |
| 9486 // Die now | |
| 9487 instruct ShouldNotReachHere( ) | |
| 9488 %{ | |
| 9489 match(Halt); | |
| 9490 ins_cost(CALL_COST); | |
| 9491 | |
| 9492 size(4); | |
| 9493 // Use the following format syntax | |
| 9494 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 9495 ins_encode( form2_illtrap() ); | |
| 9496 ins_pipe(tail_call); | |
| 9497 %} | |
| 9498 | |
| 9499 // ============================================================================ | |
| 9500 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 9501 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 9502 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 9503 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 9504 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 9505 match(Set index (PartialSubtypeCheck sub super)); | |
| 9506 effect( KILL pcc, KILL o7 ); | |
| 9507 ins_cost(DEFAULT_COST*10); | |
| 9508 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 9509 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9510 ins_pipe(partial_subtype_check_pipe); | |
| 9511 %} | |
| 9512 | |
| 9513 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 9514 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 9515 effect( KILL idx, KILL o7 ); | |
| 9516 ins_cost(DEFAULT_COST*10); | |
| 9517 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 9518 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9519 ins_pipe(partial_subtype_check_pipe); | |
| 9520 %} | |
| 9521 | |
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9522 |
| 0 | 9523 // ============================================================================ |
| 9524 // inlined locking and unlocking | |
| 9525 | |
| 9526 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9527 match(Set pcc (FastLock object box)); | |
| 9528 | |
| 9529 effect(KILL scratch, TEMP scratch2); | |
| 9530 ins_cost(100); | |
| 9531 | |
| 9532 size(4*112); // conservative overestimation ... | |
| 9533 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9534 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 9535 ins_pipe(long_memory_op); | |
| 9536 %} | |
| 9537 | |
| 9538 | |
| 9539 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9540 match(Set pcc (FastUnlock object box)); | |
| 9541 effect(KILL scratch, TEMP scratch2); | |
| 9542 ins_cost(100); | |
| 9543 | |
| 9544 size(4*120); // conservative overestimation ... | |
| 9545 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9546 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 9547 ins_pipe(long_memory_op); | |
| 9548 %} | |
| 9549 | |
| 9550 // Count and Base registers are fixed because the allocator cannot | |
| 9551 // kill unknown registers. The encodings are generic. | |
| 9552 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 9553 match(Set dummy (ClearArray cnt base)); | |
| 9554 effect(TEMP temp, KILL ccr); | |
| 9555 ins_cost(300); | |
| 9556 format %{ "MOV $cnt,$temp\n" | |
| 9557 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 9558 " BRge loop\t\t! Clearing loop\n" | |
| 9559 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 9560 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 9561 ins_pipe(long_memory_op); | |
| 9562 %} | |
| 9563 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9564 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9565 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9566 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9567 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 9568 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9569 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9570 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 9571 ins_pipe(long_memory_op); |
| 9572 %} | |
| 9573 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9574 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9575 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9576 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9577 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 9578 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9579 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9580 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 9581 ins_pipe(long_memory_op); |
| 9582 %} | |
| 9583 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9584 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9585 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 9586 match(Set result (AryEq ary1 ary2)); |
| 9587 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 9588 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9589 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9590 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 9591 ins_pipe(long_memory_op); |
| 9592 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9593 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9594 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9595 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9596 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9597 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9598 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9599 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9600 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9601 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9602 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9603 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9604 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9605 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9606 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9607 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9608 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9609 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9610 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9611 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9612 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9613 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9614 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9615 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9616 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9617 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9618 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9619 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9620 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9621 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9622 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9623 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9624 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9625 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9626 __ srl(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9627 __ srl(Rsrc, 0, Rdst); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9628 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9629 __ srl(Rdst, 2, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9630 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9631 __ srl(Rdst, 4, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9632 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9633 __ srl(Rdst, 8, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9634 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9635 __ srl(Rdst, 16, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9636 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9637 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9638 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9639 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9640 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9641 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9642 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9643 |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9644 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9645 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9646 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9647 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9648 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9649 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9650 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9651 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9652 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9653 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9654 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9655 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9656 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9657 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9658 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9659 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9660 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9661 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9662 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9663 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9664 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9665 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9666 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9667 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9668 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9669 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9670 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9671 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9672 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9673 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9674 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9675 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9676 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9677 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9678 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9679 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9680 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9681 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9682 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9683 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9684 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9685 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9686 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9687 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9688 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9689 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9690 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9691 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9692 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9693 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9694 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9695 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9696 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9697 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9698 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9699 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9700 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9701 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9702 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9703 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9704 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9705 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9706 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9707 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9708 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9709 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9710 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9711 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9712 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9713 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9714 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9715 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9716 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9717 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9718 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9719 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9720 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9721 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9722 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9723 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9724 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9725 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9726 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9727 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9728 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9729 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9730 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9731 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9732 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9733 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9734 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9735 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9736 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9737 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9738 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9739 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9740 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9741 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9742 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9743 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9744 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9745 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9746 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9747 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9748 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9749 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9750 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9751 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9752 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9753 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9754 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9755 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9756 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9757 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9758 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9759 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9760 |
| 0 | 9761 // ============================================================================ |
| 9762 //------------Bytes reverse-------------------------------------------------- | |
| 9763 | |
| 9764 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 9765 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9766 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9767 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9768 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9769 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9770 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9771 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9772 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9773 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9774 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9775 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9776 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9777 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9778 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9779 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9780 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9781 match(Set dst (ReverseBytesL src)); |
| 0 | 9782 |
| 9783 // Op cost is artificially doubled to make sure that load or store | |
| 9784 // instructions are preferred over this one which requires a spill | |
| 9785 // onto a stack slot. | |
| 9786 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9787 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9788 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9789 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9790 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9791 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9792 %} |
| 0 | 9793 ins_pipe( iload_mem ); |
| 9794 %} | |
| 9795 | |
|
1396
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9796 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9797 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9798 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9799 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9800 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9801 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9802 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9803 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9804 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9805 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9806 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9807 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9808 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9809 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9810 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9811 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9812 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9813 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9814 match(Set dst (ReverseBytesS src)); |
| 0 | 9815 |
| 9816 // Op cost is artificially doubled to make sure that load or store | |
| 9817 // instructions are preferred over this one which requires a spill | |
| 9818 // onto a stack slot. | |
| 9819 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9820 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9821 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9822 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9823 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9824 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9825 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9826 %} |
| 0 | 9827 ins_pipe( iload_mem ); |
| 9828 %} | |
| 9829 | |
| 9830 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9831 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 9832 match(Set dst (ReverseBytesI (LoadI src))); |
| 9833 | |
| 9834 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9835 size(4); |
| 0 | 9836 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 9837 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9838 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9839 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9840 %} |
| 0 | 9841 ins_pipe(iload_mem); |
| 9842 %} | |
| 9843 | |
| 9844 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9845 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 9846 match(Set dst (ReverseBytesL (LoadL src))); |
| 9847 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9848 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9849 size(4); |
| 0 | 9850 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 9851 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9852 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9853 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9854 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9855 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9856 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9857 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9858 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9859 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9860 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9861 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9862 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9863 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9864 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9865 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9866 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9867 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9868 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9869 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9870 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9871 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9872 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9873 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9874 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9875 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9876 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9877 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9878 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9879 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9880 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9881 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9882 %} |
| 0 | 9883 ins_pipe(iload_mem); |
| 9884 %} | |
| 9885 | |
| 9886 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9887 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 9888 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 9889 | |
| 9890 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9891 size(4); |
| 0 | 9892 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 9893 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9894 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9895 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9896 %} |
| 0 | 9897 ins_pipe(istore_mem_reg); |
| 9898 %} | |
| 9899 | |
| 9900 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9901 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 9902 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 9903 | |
| 9904 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9905 size(4); |
| 0 | 9906 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 9907 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9908 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9909 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9910 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9911 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9912 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9913 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9914 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9915 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9916 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9917 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9918 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9919 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9920 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9921 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9922 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9923 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9924 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9925 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9926 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9927 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9928 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9929 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9930 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9931 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9932 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9933 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9934 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9935 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9936 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9937 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9938 %} |
| 0 | 9939 ins_pipe(istore_mem_reg); |
| 9940 %} | |
| 9941 | |
| 9942 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 9943 // These must follow all instruction definitions as they use the names | |
| 9944 // defined in the instructions definitions. | |
| 9945 // | |
| 605 | 9946 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 9947 // |
| 9948 // peepconstraint %{ | |
| 9949 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 9950 // [, ...] ); | |
| 9951 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 9952 // | |
| 9953 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 9954 // // provide an instruction_number.operand_name for each operand that appears | |
| 9955 // // in the replacement instruction's match rule | |
| 9956 // | |
| 9957 // ---------VM FLAGS--------------------------------------------------------- | |
| 9958 // | |
| 9959 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 9960 // | |
| 9961 // Each peephole rule is given an identifying number starting with zero and | |
| 9962 // increasing by one in the order seen by the parser. An individual peephole | |
| 9963 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 9964 // on the command-line. | |
| 9965 // | |
| 9966 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 9967 // | |
| 9968 // Only match adjacent instructions in same basic block | |
| 9969 // Only equality constraints | |
| 9970 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 9971 // Only one replacement instruction | |
| 9972 // | |
| 9973 // ---------EXAMPLE---------------------------------------------------------- | |
| 9974 // | |
| 9975 // // pertinent parts of existing instructions in architecture description | |
| 9976 // instruct movI(eRegI dst, eRegI src) %{ | |
| 9977 // match(Set dst (CopyI src)); | |
| 9978 // %} | |
| 9979 // | |
| 9980 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 9981 // match(Set dst (AddI dst src)); | |
| 9982 // effect(KILL cr); | |
| 9983 // %} | |
| 9984 // | |
| 9985 // // Change (inc mov) to lea | |
| 9986 // peephole %{ | |
| 9987 // // increment preceeded by register-register move | |
| 9988 // peepmatch ( incI_eReg movI ); | |
| 9989 // // require that the destination register of the increment | |
| 9990 // // match the destination register of the move | |
| 9991 // peepconstraint ( 0.dst == 1.dst ); | |
| 9992 // // construct a replacement instruction that sets | |
| 9993 // // the destination to ( move's source register + one ) | |
| 9994 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 9995 // %} | |
| 9996 // | |
| 9997 | |
| 9998 // // Change load of spilled value to only a spill | |
| 9999 // instruct storeI(memory mem, eRegI src) %{ | |
| 10000 // match(Set mem (StoreI mem src)); | |
| 10001 // %} | |
| 10002 // | |
| 10003 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10004 // match(Set dst (LoadI mem)); | |
| 10005 // %} | |
| 10006 // | |
| 10007 // peephole %{ | |
| 10008 // peepmatch ( loadI storeI ); | |
| 10009 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10010 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 10011 // %} | |
| 10012 | |
| 10013 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 10014 // These must follow all instruction definitions as they use the names | |
| 10015 // defined in the instructions definitions. | |
| 10016 // | |
| 10017 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 10018 | |
| 10019 //----------PIPELINE----------------------------------------------------------- | |
| 10020 // Rules which define the behavior of the target architectures pipeline. |