Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 4582:b24386206122
Made all vm builds go into subdirectories, even product builds to simplify building the various types of VMs (server, client and graal).
Made HotSpot build jobs use the number of CPUs on the host machine.
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Mon, 13 Feb 2012 23:13:37 +0100 |
| parents | 04b9a2566eec |
| children | 33df1aeaebbf |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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2014
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
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6941466: Oracle rebranding changes for Hotspot repositories
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1513
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changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_x86.inline.hpp" | |
| 27 #include "gc_interface/collectedHeap.inline.hpp" | |
| 28 #include "interpreter/interpreter.hpp" | |
| 29 #include "memory/cardTableModRefBS.hpp" | |
| 30 #include "memory/resourceArea.hpp" | |
| 31 #include "prims/methodHandles.hpp" | |
| 32 #include "runtime/biasedLocking.hpp" | |
| 33 #include "runtime/interfaceSupport.hpp" | |
| 34 #include "runtime/objectMonitor.hpp" | |
| 35 #include "runtime/os.hpp" | |
| 36 #include "runtime/sharedRuntime.hpp" | |
| 37 #include "runtime/stubRoutines.hpp" | |
| 38 #ifndef SERIALGC | |
| 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 41 #include "gc_implementation/g1/heapRegion.hpp" | |
| 42 #endif | |
| 0 | 43 |
| 44 // Implementation of AddressLiteral | |
| 45 | |
| 46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 47 _is_lval = false; | |
| 48 _target = target; | |
| 49 switch (rtype) { | |
| 50 case relocInfo::oop_type: | |
| 51 // Oops are a special case. Normally they would be their own section | |
| 52 // but in cases like icBuffer they are literals in the code stream that | |
| 53 // we don't have a section for. We use none so that we get a literal address | |
| 54 // which is always patchable. | |
| 55 break; | |
| 56 case relocInfo::external_word_type: | |
| 57 _rspec = external_word_Relocation::spec(target); | |
| 58 break; | |
| 59 case relocInfo::internal_word_type: | |
| 60 _rspec = internal_word_Relocation::spec(target); | |
| 61 break; | |
| 62 case relocInfo::opt_virtual_call_type: | |
| 63 _rspec = opt_virtual_call_Relocation::spec(); | |
| 64 break; | |
| 65 case relocInfo::static_call_type: | |
| 66 _rspec = static_call_Relocation::spec(); | |
| 67 break; | |
| 68 case relocInfo::runtime_call_type: | |
| 69 _rspec = runtime_call_Relocation::spec(); | |
| 70 break; | |
| 71 case relocInfo::poll_type: | |
| 72 case relocInfo::poll_return_type: | |
| 73 _rspec = Relocation::spec_simple(rtype); | |
| 74 break; | |
| 75 case relocInfo::none: | |
| 76 break; | |
| 77 default: | |
| 78 ShouldNotReachHere(); | |
| 79 break; | |
| 80 } | |
| 81 } | |
| 82 | |
| 83 // Implementation of Address | |
| 84 | |
| 304 | 85 #ifdef _LP64 |
| 86 | |
| 0 | 87 Address Address::make_array(ArrayAddress adr) { |
| 88 // Not implementable on 64bit machines | |
| 89 // Should have been handled higher up the call chain. | |
| 90 ShouldNotReachHere(); | |
| 304 | 91 return Address(); |
| 92 } | |
| 93 | |
| 94 // exceedingly dangerous constructor | |
| 95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 96 _base = noreg; | |
| 97 _index = noreg; | |
| 98 _scale = no_scale; | |
| 99 _disp = disp; | |
| 100 switch (rtype) { | |
| 101 case relocInfo::external_word_type: | |
| 102 _rspec = external_word_Relocation::spec(loc); | |
| 103 break; | |
| 104 case relocInfo::internal_word_type: | |
| 105 _rspec = internal_word_Relocation::spec(loc); | |
| 106 break; | |
| 107 case relocInfo::runtime_call_type: | |
| 108 // HMM | |
| 109 _rspec = runtime_call_Relocation::spec(); | |
| 110 break; | |
| 111 case relocInfo::poll_type: | |
| 112 case relocInfo::poll_return_type: | |
| 113 _rspec = Relocation::spec_simple(rtype); | |
| 114 break; | |
| 115 case relocInfo::none: | |
| 116 break; | |
| 117 default: | |
| 118 ShouldNotReachHere(); | |
| 119 } | |
| 120 } | |
| 121 #else // LP64 | |
| 122 | |
| 123 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 124 AddressLiteral base = adr.base(); |
| 125 Address index = adr.index(); | |
| 126 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 128 array._rspec = base._rspec; | |
| 129 return array; | |
| 304 | 130 } |
| 0 | 131 |
| 132 // exceedingly dangerous constructor | |
| 133 Address::Address(address loc, RelocationHolder spec) { | |
| 134 _base = noreg; | |
| 135 _index = noreg; | |
| 136 _scale = no_scale; | |
| 137 _disp = (intptr_t) loc; | |
| 138 _rspec = spec; | |
| 139 } | |
| 304 | 140 |
| 0 | 141 #endif // _LP64 |
| 142 | |
| 304 | 143 |
| 144 | |
| 0 | 145 // Convert the raw encoding form into the form expected by the constructor for |
| 146 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 147 // that to noreg for the Address constructor. | |
| 624 | 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
| 149 RelocationHolder rspec; | |
| 150 if (disp_is_oop) { | |
| 151 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
| 152 } | |
| 0 | 153 bool valid_index = index != rsp->encoding(); |
| 154 if (valid_index) { | |
| 155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 156 madr._rspec = rspec; |
| 0 | 157 return madr; |
| 158 } else { | |
| 159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 160 madr._rspec = rspec; |
| 0 | 161 return madr; |
| 162 } | |
| 163 } | |
| 164 | |
| 165 // Implementation of Assembler | |
| 166 | |
| 167 int AbstractAssembler::code_fill_byte() { | |
| 168 return (u_char)'\xF4'; // hlt | |
| 169 } | |
| 170 | |
| 171 // make this go away someday | |
| 172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 173 if (rtype == relocInfo::none) | |
| 174 emit_long(data); | |
| 175 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 176 } | |
| 177 | |
| 178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 179 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 181 if (rspec.type() != relocInfo::none) { | |
| 182 #ifdef ASSERT | |
| 183 check_relocation(rspec, format); | |
| 184 #endif | |
| 185 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 186 // embedded words. Instead, relocate to the enclosing instruction. | |
| 187 | |
| 188 // hack. call32 is too wide for mask so use disp32 | |
| 189 if (format == call32_operand) | |
| 190 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 191 else | |
| 192 code_section()->relocate(inst_mark(), rspec, format); | |
| 193 } | |
| 194 emit_long(data); | |
| 195 } | |
| 196 | |
| 304 | 197 static int encode(Register r) { |
| 198 int enc = r->encoding(); | |
| 199 if (enc >= 8) { | |
| 200 enc -= 8; | |
| 201 } | |
| 202 return enc; | |
| 203 } | |
| 204 | |
| 205 static int encode(XMMRegister r) { | |
| 206 int enc = r->encoding(); | |
| 207 if (enc >= 8) { | |
| 208 enc -= 8; | |
| 209 } | |
| 210 return enc; | |
| 211 } | |
| 0 | 212 |
| 213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 214 assert(dst->has_byte_register(), "must have byte register"); | |
| 215 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 216 assert(isByte(imm8), "not a byte"); | |
| 217 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 218 emit_byte(op1); | |
| 304 | 219 emit_byte(op2 | encode(dst)); |
| 0 | 220 emit_byte(imm8); |
| 221 } | |
| 222 | |
| 223 | |
| 304 | 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 226 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 228 if (is8bit(imm32)) { | |
| 229 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 230 emit_byte(op2 | encode(dst)); |
| 0 | 231 emit_byte(imm32 & 0xFF); |
| 232 } else { | |
| 233 emit_byte(op1); | |
| 304 | 234 emit_byte(op2 | encode(dst)); |
| 0 | 235 emit_long(imm32); |
| 236 } | |
| 237 } | |
| 238 | |
| 239 // immediate-to-memory forms | |
| 304 | 240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 243 if (is8bit(imm32)) { | |
| 244 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 245 emit_operand(rm, adr, 1); |
| 0 | 246 emit_byte(imm32 & 0xFF); |
| 247 } else { | |
| 248 emit_byte(op1); | |
| 304 | 249 emit_operand(rm, adr, 4); |
| 0 | 250 emit_long(imm32); |
| 251 } | |
| 252 } | |
| 253 | |
| 254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
| 304 | 255 LP64_ONLY(ShouldNotReachHere()); |
| 0 | 256 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 257 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 259 InstructionMark im(this); | |
| 260 emit_byte(op1); | |
| 304 | 261 emit_byte(op2 | encode(dst)); |
| 262 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
| 0 | 263 } |
| 264 | |
| 265 | |
| 266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 267 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 268 emit_byte(op1); | |
| 304 | 269 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 270 } | |
| 271 | |
| 272 | |
| 273 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 274 Address::ScaleFactor scale, int disp, | |
| 275 RelocationHolder const& rspec, | |
| 276 int rip_relative_correction) { | |
| 0 | 277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 278 |
| 279 // Encode the registers as needed in the fields they are used in | |
| 280 | |
| 281 int regenc = encode(reg) << 3; | |
| 282 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 283 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 284 | |
| 0 | 285 if (base->is_valid()) { |
| 286 if (index->is_valid()) { | |
| 287 assert(scale != Address::no_scale, "inconsistent address"); | |
| 288 // [base + index*scale + disp] | |
| 304 | 289 if (disp == 0 && rtype == relocInfo::none && |
| 290 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 291 // [base + index*scale] |
| 292 // [00 reg 100][ss index base] | |
| 293 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 294 emit_byte(0x04 | regenc); |
| 295 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 296 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 297 // [base + index*scale + imm8] | |
| 298 // [01 reg 100][ss index base] imm8 | |
| 299 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 300 emit_byte(0x44 | regenc); |
| 301 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 302 emit_byte(disp & 0xFF); |
| 303 } else { | |
| 304 | 304 // [base + index*scale + disp32] |
| 305 // [10 reg 100][ss index base] disp32 | |
| 0 | 306 assert(index != rsp, "illegal addressing mode"); |
| 304 | 307 emit_byte(0x84 | regenc); |
| 308 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 309 emit_data(disp, rspec, disp32_operand); |
| 310 } | |
| 304 | 311 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 312 // [rsp + disp] | |
| 0 | 313 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 314 // [rsp] |
| 0 | 315 // [00 reg 100][00 100 100] |
| 304 | 316 emit_byte(0x04 | regenc); |
| 0 | 317 emit_byte(0x24); |
| 318 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 319 // [rsp + imm8] |
| 320 // [01 reg 100][00 100 100] disp8 | |
| 321 emit_byte(0x44 | regenc); | |
| 0 | 322 emit_byte(0x24); |
| 323 emit_byte(disp & 0xFF); | |
| 324 } else { | |
| 304 | 325 // [rsp + imm32] |
| 326 // [10 reg 100][00 100 100] disp32 | |
| 327 emit_byte(0x84 | regenc); | |
| 0 | 328 emit_byte(0x24); |
| 329 emit_data(disp, rspec, disp32_operand); | |
| 330 } | |
| 331 } else { | |
| 332 // [base + disp] | |
| 304 | 333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 334 if (disp == 0 && rtype == relocInfo::none && | |
| 335 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 336 // [base] |
| 337 // [00 reg base] | |
| 304 | 338 emit_byte(0x00 | regenc | baseenc); |
| 0 | 339 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 340 // [base + disp8] |
| 341 // [01 reg base] disp8 | |
| 342 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 343 emit_byte(disp & 0xFF); |
| 344 } else { | |
| 304 | 345 // [base + disp32] |
| 346 // [10 reg base] disp32 | |
| 347 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 348 emit_data(disp, rspec, disp32_operand); |
| 349 } | |
| 350 } | |
| 351 } else { | |
| 352 if (index->is_valid()) { | |
| 353 assert(scale != Address::no_scale, "inconsistent address"); | |
| 354 // [index*scale + disp] | |
| 304 | 355 // [00 reg 100][ss index 101] disp32 |
| 0 | 356 assert(index != rsp, "illegal addressing mode"); |
| 304 | 357 emit_byte(0x04 | regenc); |
| 358 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 359 emit_data(disp, rspec, disp32_operand); |
| 304 | 360 } else if (rtype != relocInfo::none ) { |
| 361 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 362 // [00 000 101] disp32 | |
| 363 | |
| 364 emit_byte(0x05 | regenc); | |
| 365 // Note that the RIP-rel. correction applies to the generated | |
| 366 // disp field, but _not_ to the target address in the rspec. | |
| 367 | |
| 368 // disp was created by converting the target address minus the pc | |
| 369 // at the start of the instruction. That needs more correction here. | |
| 370 // intptr_t disp = target - next_ip; | |
| 371 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 373 int64_t adjusted = disp; | |
| 374 // Do rip-rel adjustment for 64bit | |
| 375 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 376 assert(is_simm32(adjusted), | |
| 377 "must be 32bit offset (RIP relative address)"); | |
| 378 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 379 | |
| 0 | 380 } else { |
| 304 | 381 // 32bit never did this, did everything as the rip-rel/disp code above |
| 382 // [disp] ABSOLUTE | |
| 383 // [00 reg 100][00 100 101] disp32 | |
| 384 emit_byte(0x04 | regenc); | |
| 385 emit_byte(0x25); | |
| 0 | 386 emit_data(disp, rspec, disp32_operand); |
| 387 } | |
| 388 } | |
| 389 } | |
| 390 | |
| 304 | 391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 392 Address::ScaleFactor scale, int disp, | |
| 393 RelocationHolder const& rspec) { | |
| 394 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 395 } | |
| 396 | |
| 0 | 397 // Secret local extension to Assembler::WhichOperand: |
| 398 #define end_pc_operand (_WhichOperand_limit) | |
| 399 | |
| 400 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 401 // Decode the given instruction, and return the address of | |
| 402 // an embedded 32-bit operand word. | |
| 403 | |
| 404 // If "which" is disp32_operand, selects the displacement portion | |
| 405 // of an effective address specifier. | |
| 304 | 406 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 407 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 408 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 409 // and that it is 32/64 bits wide. |
| 0 | 410 |
| 411 // If "which" is end_pc_operand, find the end of the instruction. | |
| 412 | |
| 413 address ip = inst; | |
| 304 | 414 bool is_64bit = false; |
| 415 | |
| 416 debug_only(bool has_disp32 = false); | |
| 417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 418 | |
| 419 again_after_prefix: | |
| 0 | 420 switch (0xFF & *ip++) { |
| 421 | |
| 422 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 425 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 426 #define REP16(x) REP8((x)+0): \ |
| 0 | 427 case REP8((x)+8) |
| 428 | |
| 429 case CS_segment: | |
| 430 case SS_segment: | |
| 431 case DS_segment: | |
| 432 case ES_segment: | |
| 433 case FS_segment: | |
| 434 case GS_segment: | |
| 304 | 435 // Seems dubious |
| 436 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 437 assert(ip == inst+1, "only one prefix allowed"); |
| 438 goto again_after_prefix; | |
| 439 | |
| 304 | 440 case 0x67: |
| 441 case REX: | |
| 442 case REX_B: | |
| 443 case REX_X: | |
| 444 case REX_XB: | |
| 445 case REX_R: | |
| 446 case REX_RB: | |
| 447 case REX_RX: | |
| 448 case REX_RXB: | |
| 449 NOT_LP64(assert(false, "64bit prefixes")); | |
| 450 goto again_after_prefix; | |
| 451 | |
| 452 case REX_W: | |
| 453 case REX_WB: | |
| 454 case REX_WX: | |
| 455 case REX_WXB: | |
| 456 case REX_WR: | |
| 457 case REX_WRB: | |
| 458 case REX_WRX: | |
| 459 case REX_WRXB: | |
| 460 NOT_LP64(assert(false, "64bit prefixes")); | |
| 461 is_64bit = true; | |
| 462 goto again_after_prefix; | |
| 463 | |
| 464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 465 case 0x88: // movb a, r |
| 466 case 0x89: // movl a, r | |
| 467 case 0x8A: // movb r, a | |
| 468 case 0x8B: // movl r, a | |
| 469 case 0x8F: // popl a | |
| 304 | 470 debug_only(has_disp32 = true); |
| 0 | 471 break; |
| 472 | |
| 304 | 473 case 0x68: // pushq #32 |
| 474 if (which == end_pc_operand) { | |
| 475 return ip + 4; | |
| 476 } | |
| 477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 478 return ip; // not produced by emit_operand |
| 479 | |
| 480 case 0x66: // movw ... (size prefix) | |
| 304 | 481 again_after_size_prefix2: |
| 0 | 482 switch (0xFF & *ip++) { |
| 304 | 483 case REX: |
| 484 case REX_B: | |
| 485 case REX_X: | |
| 486 case REX_XB: | |
| 487 case REX_R: | |
| 488 case REX_RB: | |
| 489 case REX_RX: | |
| 490 case REX_RXB: | |
| 491 case REX_W: | |
| 492 case REX_WB: | |
| 493 case REX_WX: | |
| 494 case REX_WXB: | |
| 495 case REX_WR: | |
| 496 case REX_WRB: | |
| 497 case REX_WRX: | |
| 498 case REX_WRXB: | |
| 499 NOT_LP64(assert(false, "64bit prefix found")); | |
| 500 goto again_after_size_prefix2; | |
| 0 | 501 case 0x8B: // movw r, a |
| 502 case 0x89: // movw a, r | |
| 304 | 503 debug_only(has_disp32 = true); |
| 0 | 504 break; |
| 505 case 0xC7: // movw a, #16 | |
| 304 | 506 debug_only(has_disp32 = true); |
| 0 | 507 tail_size = 2; // the imm16 |
| 508 break; | |
| 509 case 0x0F: // several SSE/SSE2 variants | |
| 510 ip--; // reparse the 0x0F | |
| 511 goto again_after_prefix; | |
| 512 default: | |
| 513 ShouldNotReachHere(); | |
| 514 } | |
| 515 break; | |
| 516 | |
| 304 | 517 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 519 // these asserts are somewhat nonsensical | |
| 520 #ifndef _LP64 | |
| 521 assert(which == imm_operand || which == disp32_operand, ""); | |
| 522 #else | |
| 523 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 524 which == narrow_oop_operand && !is_64bit, ""); | |
| 525 #endif // _LP64 | |
| 0 | 526 return ip; |
| 527 | |
| 528 case 0x69: // imul r, a, #32 | |
| 529 case 0xC7: // movl a, #32(oop?) | |
| 530 tail_size = 4; | |
| 304 | 531 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 532 break; |
| 533 | |
| 534 case 0x0F: // movx..., etc. | |
| 535 switch (0xFF & *ip++) { | |
| 536 case 0x12: // movlps | |
| 537 case 0x28: // movaps | |
| 538 case 0x2E: // ucomiss | |
| 539 case 0x2F: // comiss | |
| 540 case 0x54: // andps | |
| 541 case 0x55: // andnps | |
| 542 case 0x56: // orps | |
| 543 case 0x57: // xorps | |
| 544 case 0x6E: // movd | |
| 545 case 0x7E: // movd | |
| 546 case 0xAE: // ldmxcsr a | |
| 304 | 547 // 64bit side says it these have both operands but that doesn't |
| 548 // appear to be true | |
| 549 debug_only(has_disp32 = true); | |
| 0 | 550 break; |
| 551 | |
| 552 case 0xAD: // shrd r, a, %cl | |
| 553 case 0xAF: // imul r, a | |
| 304 | 554 case 0xBE: // movsbl r, a (movsxb) |
| 555 case 0xBF: // movswl r, a (movsxw) | |
| 556 case 0xB6: // movzbl r, a (movzxb) | |
| 557 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 558 case REP16(0x40): // cmovl cc, r, a |
| 559 case 0xB0: // cmpxchgb | |
| 560 case 0xB1: // cmpxchg | |
| 561 case 0xC1: // xaddl | |
| 562 case 0xC7: // cmpxchg8 | |
| 563 case REP16(0x90): // setcc a | |
| 304 | 564 debug_only(has_disp32 = true); |
| 0 | 565 // fall out of the switch to decode the address |
| 566 break; | |
| 304 | 567 |
| 0 | 568 case 0xAC: // shrd r, a, #8 |
| 304 | 569 debug_only(has_disp32 = true); |
| 0 | 570 tail_size = 1; // the imm8 |
| 571 break; | |
| 304 | 572 |
| 0 | 573 case REP16(0x80): // jcc rdisp32 |
| 574 if (which == end_pc_operand) return ip + 4; | |
| 304 | 575 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 576 return ip; |
| 577 default: | |
| 578 ShouldNotReachHere(); | |
| 579 } | |
| 580 break; | |
| 581 | |
| 582 case 0x81: // addl a, #32; addl r, #32 | |
| 583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 584 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 585 tail_size = 4; |
| 304 | 586 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 587 break; |
| 588 | |
| 589 case 0x83: // addl a, #8; addl r, #8 | |
| 590 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 591 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 592 tail_size = 1; |
| 593 break; | |
| 594 | |
| 595 case 0x9B: | |
| 596 switch (0xFF & *ip++) { | |
| 597 case 0xD9: // fnstcw a | |
| 304 | 598 debug_only(has_disp32 = true); |
| 0 | 599 break; |
| 600 default: | |
| 601 ShouldNotReachHere(); | |
| 602 } | |
| 603 break; | |
| 604 | |
| 605 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 606 case REP4(0x10): // adc... | |
| 607 case REP4(0x20): // and... | |
| 608 case REP4(0x30): // xor... | |
| 609 case REP4(0x08): // or... | |
| 610 case REP4(0x18): // sbb... | |
| 611 case REP4(0x28): // sub... | |
| 304 | 612 case 0xF7: // mull a |
| 613 case 0x8D: // lea r, a | |
| 614 case 0x87: // xchg r, a | |
| 0 | 615 case REP4(0x38): // cmp... |
| 304 | 616 case 0x85: // test r, a |
| 617 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 618 break; |
| 619 | |
| 620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 621 case 0xC6: // movb a, #8 | |
| 622 case 0x80: // cmpb a, #8 | |
| 623 case 0x6B: // imul r, a, #8 | |
| 304 | 624 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 625 tail_size = 1; // the imm8 |
| 626 break; | |
| 627 | |
| 628 case 0xE8: // call rdisp32 | |
| 629 case 0xE9: // jmp rdisp32 | |
| 630 if (which == end_pc_operand) return ip + 4; | |
| 304 | 631 assert(which == call32_operand, "call has no disp32 or imm"); |
| 0 | 632 return ip; |
| 633 | |
| 634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 637 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 639 case 0xDF: // fild_d a; fistp_d a | |
| 640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 643 debug_only(has_disp32 = true); |
| 0 | 644 break; |
| 645 | |
|
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646 case 0xF0: // Lock |
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647 assert(os::is_MP(), "only on MP"); |
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648 goto again_after_prefix; |
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649 |
| 0 | 650 case 0xF3: // For SSE |
| 651 case 0xF2: // For SSE2 | |
| 304 | 652 switch (0xFF & *ip++) { |
| 653 case REX: | |
| 654 case REX_B: | |
| 655 case REX_X: | |
| 656 case REX_XB: | |
| 657 case REX_R: | |
| 658 case REX_RB: | |
| 659 case REX_RX: | |
| 660 case REX_RXB: | |
| 661 case REX_W: | |
| 662 case REX_WB: | |
| 663 case REX_WX: | |
| 664 case REX_WXB: | |
| 665 case REX_WR: | |
| 666 case REX_WRB: | |
| 667 case REX_WRX: | |
| 668 case REX_WRXB: | |
| 669 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 670 ip++; | |
| 671 default: | |
| 672 ip++; | |
| 673 } | |
| 674 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 675 break; |
| 676 | |
| 677 default: | |
| 678 ShouldNotReachHere(); | |
| 679 | |
| 304 | 680 #undef REP8 |
| 681 #undef REP16 | |
| 0 | 682 } |
| 683 | |
| 684 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 685 #ifdef _LP64 |
| 686 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 687 #else | |
| 688 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 689 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 690 #endif // LP64 | |
| 691 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 692 |
| 693 // parse the output of emit_operand | |
| 694 int op2 = 0xFF & *ip++; | |
| 695 int base = op2 & 0x07; | |
| 696 int op3 = -1; | |
| 697 const int b100 = 4; | |
| 698 const int b101 = 5; | |
| 699 if (base == b100 && (op2 >> 6) != 3) { | |
| 700 op3 = 0xFF & *ip++; | |
| 701 base = op3 & 0x07; // refetch the base | |
| 702 } | |
| 703 // now ip points at the disp (if any) | |
| 704 | |
| 705 switch (op2 >> 6) { | |
| 706 case 0: | |
| 707 // [00 reg 100][ss index base] | |
| 304 | 708 // [00 reg 100][00 100 esp] |
| 0 | 709 // [00 reg base] |
| 710 // [00 reg 100][ss index 101][disp32] | |
| 711 // [00 reg 101] [disp32] | |
| 712 | |
| 713 if (base == b101) { | |
| 714 if (which == disp32_operand) | |
| 715 return ip; // caller wants the disp32 | |
| 716 ip += 4; // skip the disp32 | |
| 717 } | |
| 718 break; | |
| 719 | |
| 720 case 1: | |
| 721 // [01 reg 100][ss index base][disp8] | |
| 304 | 722 // [01 reg 100][00 100 esp][disp8] |
| 0 | 723 // [01 reg base] [disp8] |
| 724 ip += 1; // skip the disp8 | |
| 725 break; | |
| 726 | |
| 727 case 2: | |
| 728 // [10 reg 100][ss index base][disp32] | |
| 304 | 729 // [10 reg 100][00 100 esp][disp32] |
| 0 | 730 // [10 reg base] [disp32] |
| 731 if (which == disp32_operand) | |
| 732 return ip; // caller wants the disp32 | |
| 733 ip += 4; // skip the disp32 | |
| 734 break; | |
| 735 | |
| 736 case 3: | |
| 737 // [11 reg base] (not a memory addressing mode) | |
| 738 break; | |
| 739 } | |
| 740 | |
| 741 if (which == end_pc_operand) { | |
| 742 return ip + tail_size; | |
| 743 } | |
| 744 | |
| 304 | 745 #ifdef _LP64 |
|
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746 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 747 #else |
| 748 assert(which == imm_operand, "instruction has only an imm field"); | |
| 749 #endif // LP64 | |
| 0 | 750 return ip; |
| 751 } | |
| 752 | |
| 753 address Assembler::locate_next_instruction(address inst) { | |
| 754 // Secretly share code with locate_operand: | |
| 755 return locate_operand(inst, end_pc_operand); | |
| 756 } | |
| 757 | |
| 758 | |
| 759 #ifdef ASSERT | |
| 760 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 761 address inst = inst_mark(); | |
| 762 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 763 address opnd; | |
| 764 | |
| 765 Relocation* r = rspec.reloc(); | |
| 766 if (r->type() == relocInfo::none) { | |
| 767 return; | |
| 768 } else if (r->is_call() || format == call32_operand) { | |
| 769 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 770 opnd = locate_operand(inst, call32_operand); | |
| 771 } else if (r->is_data()) { | |
| 304 | 772 assert(format == imm_operand || format == disp32_operand |
| 773 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 774 opnd = locate_operand(inst, (WhichOperand)format); |
| 775 } else { | |
| 304 | 776 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 777 return; |
| 778 } | |
| 779 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 780 } | |
| 304 | 781 #endif // ASSERT |
| 782 | |
| 783 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 784 assert(reg->encoding() < 8, "no extended registers"); | |
| 785 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 786 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 787 adr._rspec); | |
| 788 } | |
| 789 | |
| 790 void Assembler::emit_operand(Register reg, Address adr, | |
| 791 int rip_relative_correction) { | |
| 792 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 793 adr._rspec, | |
| 794 rip_relative_correction); | |
| 795 } | |
| 796 | |
| 797 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 798 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 799 adr._rspec); | |
| 800 } | |
| 801 | |
| 802 // MMX operations | |
| 803 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 804 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 805 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 806 } | |
| 807 | |
| 808 // work around gcc (3.2.1-7a) bug | |
| 809 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 810 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 811 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 812 } |
| 813 | |
| 814 | |
| 815 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 816 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 817 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 818 emit_byte(b1); | |
| 819 emit_byte(b2 + i); | |
| 820 } | |
| 821 | |
| 822 | |
|
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823 // Now the Assembler instructions (identical for 32/64 bits) |
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824 |
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825 void Assembler::adcl(Address dst, int32_t imm32) { |
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826 InstructionMark im(this); |
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827 prefix(dst); |
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828 emit_arith_operand(0x81, rdx, dst, imm32); |
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829 } |
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830 |
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831 void Assembler::adcl(Address dst, Register src) { |
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832 InstructionMark im(this); |
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833 prefix(dst, src); |
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834 emit_byte(0x11); |
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835 emit_operand(src, dst); |
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836 } |
| 304 | 837 |
| 838 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 839 prefix(dst); | |
| 0 | 840 emit_arith(0x81, 0xD0, dst, imm32); |
| 841 } | |
| 842 | |
| 843 void Assembler::adcl(Register dst, Address src) { | |
| 844 InstructionMark im(this); | |
| 304 | 845 prefix(src, dst); |
| 0 | 846 emit_byte(0x13); |
| 847 emit_operand(dst, src); | |
| 848 } | |
| 849 | |
| 850 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 851 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 852 emit_arith(0x13, 0xC0, dst, src); |
| 853 } | |
| 854 | |
| 304 | 855 void Assembler::addl(Address dst, int32_t imm32) { |
| 856 InstructionMark im(this); | |
| 857 prefix(dst); | |
| 858 emit_arith_operand(0x81, rax, dst, imm32); | |
| 859 } | |
| 0 | 860 |
| 861 void Assembler::addl(Address dst, Register src) { | |
| 862 InstructionMark im(this); | |
| 304 | 863 prefix(dst, src); |
| 0 | 864 emit_byte(0x01); |
| 865 emit_operand(src, dst); | |
| 866 } | |
| 867 | |
| 304 | 868 void Assembler::addl(Register dst, int32_t imm32) { |
| 869 prefix(dst); | |
| 0 | 870 emit_arith(0x81, 0xC0, dst, imm32); |
| 871 } | |
| 872 | |
| 873 void Assembler::addl(Register dst, Address src) { | |
| 874 InstructionMark im(this); | |
| 304 | 875 prefix(src, dst); |
| 0 | 876 emit_byte(0x03); |
| 877 emit_operand(dst, src); | |
| 878 } | |
| 879 | |
| 880 void Assembler::addl(Register dst, Register src) { | |
| 304 | 881 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 882 emit_arith(0x03, 0xC0, dst, src); |
| 883 } | |
| 884 | |
| 885 void Assembler::addr_nop_4() { | |
| 886 // 4 bytes: NOP DWORD PTR [EAX+0] | |
| 887 emit_byte(0x0F); | |
| 888 emit_byte(0x1F); | |
| 889 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 890 emit_byte(0); // 8-bits offset (1 byte) | |
| 891 } | |
| 892 | |
| 893 void Assembler::addr_nop_5() { | |
| 894 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
| 895 emit_byte(0x0F); | |
| 896 emit_byte(0x1F); | |
| 897 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 898 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 899 emit_byte(0); // 8-bits offset (1 byte) | |
| 900 } | |
| 901 | |
| 902 void Assembler::addr_nop_7() { | |
| 903 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
| 904 emit_byte(0x0F); | |
| 905 emit_byte(0x1F); | |
| 906 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 907 emit_long(0); // 32-bits offset (4 bytes) | |
| 908 } | |
| 909 | |
| 910 void Assembler::addr_nop_8() { | |
| 911 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
| 912 emit_byte(0x0F); | |
| 913 emit_byte(0x1F); | |
| 914 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 915 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 916 emit_long(0); // 32-bits offset (4 bytes) | |
| 917 } | |
| 918 | |
| 304 | 919 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 921 emit_byte(0xF2); | |
| 922 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 923 emit_byte(0x0F); | |
| 924 emit_byte(0x58); | |
| 925 emit_byte(0xC0 | encode); | |
| 926 } | |
| 927 | |
| 928 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 930 InstructionMark im(this); | |
| 931 emit_byte(0xF2); | |
| 932 prefix(src, dst); | |
| 933 emit_byte(0x0F); | |
| 934 emit_byte(0x58); | |
| 935 emit_operand(dst, src); | |
| 936 } | |
| 937 | |
| 938 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 940 emit_byte(0xF3); | |
| 941 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 942 emit_byte(0x0F); | |
| 943 emit_byte(0x58); | |
| 944 emit_byte(0xC0 | encode); | |
| 945 } | |
| 946 | |
| 947 void Assembler::addss(XMMRegister dst, Address src) { | |
| 948 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 949 InstructionMark im(this); | |
| 950 emit_byte(0xF3); | |
| 951 prefix(src, dst); | |
| 952 emit_byte(0x0F); | |
| 953 emit_byte(0x58); | |
| 954 emit_operand(dst, src); | |
| 955 } | |
| 956 | |
| 957 void Assembler::andl(Register dst, int32_t imm32) { | |
| 958 prefix(dst); | |
| 959 emit_arith(0x81, 0xE0, dst, imm32); | |
| 960 } | |
| 961 | |
| 962 void Assembler::andl(Register dst, Address src) { | |
| 963 InstructionMark im(this); | |
| 964 prefix(src, dst); | |
| 965 emit_byte(0x23); | |
| 966 emit_operand(dst, src); | |
| 967 } | |
| 968 | |
| 969 void Assembler::andl(Register dst, Register src) { | |
| 970 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 971 emit_arith(0x23, 0xC0, dst, src); | |
| 972 } | |
| 973 | |
| 974 void Assembler::andpd(XMMRegister dst, Address src) { | |
| 975 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 976 InstructionMark im(this); | |
| 977 emit_byte(0x66); | |
| 978 prefix(src, dst); | |
| 979 emit_byte(0x0F); | |
| 980 emit_byte(0x54); | |
| 981 emit_operand(dst, src); | |
| 982 } | |
| 983 | |
|
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984 void Assembler::bsfl(Register dst, Register src) { |
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985 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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986 emit_byte(0x0F); |
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987 emit_byte(0xBC); |
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988 emit_byte(0xC0 | encode); |
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989 } |
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990 |
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991 void Assembler::bsrl(Register dst, Register src) { |
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992 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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993 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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994 emit_byte(0x0F); |
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995 emit_byte(0xBD); |
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996 emit_byte(0xC0 | encode); |
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997 } |
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998 |
| 304 | 999 void Assembler::bswapl(Register reg) { // bswap |
| 1000 int encode = prefix_and_encode(reg->encoding()); | |
| 1001 emit_byte(0x0F); | |
| 1002 emit_byte(0xC8 | encode); | |
| 1003 } | |
| 1004 | |
| 1005 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1006 // suspect disp32 is always good | |
| 1007 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1008 | |
| 1009 if (L.is_bound()) { | |
| 1010 const int long_size = 5; | |
| 1011 int offs = (int)( target(L) - pc() ); | |
| 1012 assert(offs <= 0, "assembler error"); | |
| 1013 InstructionMark im(this); | |
| 1014 // 1110 1000 #32-bit disp | |
| 1015 emit_byte(0xE8); | |
| 1016 emit_data(offs - long_size, rtype, operand); | |
| 1017 } else { | |
| 1018 InstructionMark im(this); | |
| 1019 // 1110 1000 #32-bit disp | |
| 1020 L.add_patch_at(code(), locator()); | |
| 1021 | |
| 1022 emit_byte(0xE8); | |
| 1023 emit_data(int(0), rtype, operand); | |
| 1024 } | |
| 1025 } | |
| 1026 | |
| 1027 void Assembler::call(Register dst) { | |
| 1028 // This was originally using a 32bit register encoding | |
| 1029 // and surely we want 64bit! | |
| 1030 // this is a 32bit encoding but in 64bit mode the default | |
| 1031 // operand size is 64bit so there is no need for the | |
| 1032 // wide prefix. So prefix only happens if we use the | |
| 1033 // new registers. Much like push/pop. | |
| 1034 int x = offset(); | |
| 1035 // this may be true but dbx disassembles it as if it | |
| 1036 // were 32bits... | |
| 1037 // int encode = prefix_and_encode(dst->encoding()); | |
| 1038 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
| 1039 int encode = prefixq_and_encode(dst->encoding()); | |
| 1040 | |
| 1041 emit_byte(0xFF); | |
| 1042 emit_byte(0xD0 | encode); | |
| 1043 } | |
| 1044 | |
| 1045 | |
| 1046 void Assembler::call(Address adr) { | |
| 1047 InstructionMark im(this); | |
| 1048 prefix(adr); | |
| 1049 emit_byte(0xFF); | |
| 1050 emit_operand(rdx, adr); | |
| 1051 } | |
| 1052 | |
| 1053 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1054 assert(entry != NULL, "call most probably wrong"); | |
| 1055 InstructionMark im(this); | |
| 1056 emit_byte(0xE8); | |
| 1057 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1058 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1059 // Technically, should use call32_operand, but this format is | |
| 1060 // implied by the fact that we're emitting a call instruction. | |
| 1061 | |
| 1062 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1063 emit_data((int) disp, rspec, operand); | |
| 1064 } | |
| 1065 | |
| 1066 void Assembler::cdql() { | |
| 1067 emit_byte(0x99); | |
| 1068 } | |
| 1069 | |
| 1070 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1071 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1072 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1073 emit_byte(0x0F); | |
| 1074 emit_byte(0x40 | cc); | |
| 1075 emit_byte(0xC0 | encode); | |
| 1076 } | |
| 1077 | |
| 1078 | |
| 1079 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1080 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1081 prefix(src, dst); | |
| 1082 emit_byte(0x0F); | |
| 1083 emit_byte(0x40 | cc); | |
| 1084 emit_operand(dst, src); | |
| 1085 } | |
| 1086 | |
| 1087 void Assembler::cmpb(Address dst, int imm8) { | |
| 1088 InstructionMark im(this); | |
| 1089 prefix(dst); | |
| 1090 emit_byte(0x80); | |
| 1091 emit_operand(rdi, dst, 1); | |
| 1092 emit_byte(imm8); | |
| 1093 } | |
| 1094 | |
| 1095 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1096 InstructionMark im(this); | |
| 1097 prefix(dst); | |
| 1098 emit_byte(0x81); | |
| 1099 emit_operand(rdi, dst, 4); | |
| 1100 emit_long(imm32); | |
| 1101 } | |
| 1102 | |
| 1103 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1104 prefix(dst); | |
| 1105 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1106 } | |
| 1107 | |
| 1108 void Assembler::cmpl(Register dst, Register src) { | |
| 1109 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1110 emit_arith(0x3B, 0xC0, dst, src); | |
| 1111 } | |
| 1112 | |
| 1113 | |
| 1114 void Assembler::cmpl(Register dst, Address src) { | |
| 1115 InstructionMark im(this); | |
| 1116 prefix(src, dst); | |
| 1117 emit_byte(0x3B); | |
| 1118 emit_operand(dst, src); | |
| 1119 } | |
| 1120 | |
| 1121 void Assembler::cmpw(Address dst, int imm16) { | |
| 1122 InstructionMark im(this); | |
| 1123 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1124 emit_byte(0x66); | |
| 1125 emit_byte(0x81); | |
| 1126 emit_operand(rdi, dst, 2); | |
| 1127 emit_word(imm16); | |
| 1128 } | |
| 1129 | |
| 1130 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1131 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1132 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1133 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 1134 if (Atomics & 2) { | |
| 1135 // caveat: no instructionmark, so this isn't relocatable. | |
| 1136 // Emit a synthetic, non-atomic, CAS equivalent. | |
| 1137 // Beware. The synthetic form sets all ICCs, not just ZF. | |
| 1138 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
| 1139 cmpl(rax, adr); | |
| 1140 movl(rax, adr); | |
| 1141 if (reg != rax) { | |
| 1142 Label L ; | |
| 1143 jcc(Assembler::notEqual, L); | |
| 1144 movl(adr, reg); | |
| 1145 bind(L); | |
| 1146 } | |
| 1147 } else { | |
| 1148 InstructionMark im(this); | |
| 1149 prefix(adr, reg); | |
| 1150 emit_byte(0x0F); | |
| 1151 emit_byte(0xB1); | |
| 1152 emit_operand(reg, adr); | |
| 1153 } | |
| 1154 } | |
| 1155 | |
| 1156 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1157 // NOTE: dbx seems to decode this as comiss even though the | |
| 1158 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1159 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1160 emit_byte(0x66); | |
| 1161 comiss(dst, src); | |
| 1162 } | |
| 1163 | |
| 1164 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1165 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1166 | |
| 1167 InstructionMark im(this); | |
| 1168 prefix(src, dst); | |
| 1169 emit_byte(0x0F); | |
| 1170 emit_byte(0x2F); | |
| 1171 emit_operand(dst, src); | |
| 1172 } | |
| 1173 | |
| 1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
| 1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1176 emit_byte(0xF3); | |
| 1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1178 emit_byte(0x0F); | |
| 1179 emit_byte(0xE6); | |
| 1180 emit_byte(0xC0 | encode); | |
| 1181 } | |
| 1182 | |
| 1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1185 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1186 emit_byte(0x0F); | |
| 1187 emit_byte(0x5B); | |
| 1188 emit_byte(0xC0 | encode); | |
| 1189 } | |
| 1190 | |
| 1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1192 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1193 emit_byte(0xF2); | |
| 1194 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1195 emit_byte(0x0F); | |
| 1196 emit_byte(0x5A); | |
| 1197 emit_byte(0xC0 | encode); | |
| 1198 } | |
| 1199 | |
| 1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
| 1201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1202 emit_byte(0xF2); | |
| 1203 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1204 emit_byte(0x0F); | |
| 1205 emit_byte(0x2A); | |
| 1206 emit_byte(0xC0 | encode); | |
| 1207 } | |
| 1208 | |
| 1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
| 1210 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1211 emit_byte(0xF3); | |
| 1212 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1213 emit_byte(0x0F); | |
| 1214 emit_byte(0x2A); | |
| 1215 emit_byte(0xC0 | encode); | |
| 1216 } | |
| 1217 | |
| 1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
| 1219 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1220 emit_byte(0xF3); | |
| 1221 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1222 emit_byte(0x0F); | |
| 1223 emit_byte(0x5A); | |
| 1224 emit_byte(0xC0 | encode); | |
| 1225 } | |
| 1226 | |
| 1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
| 1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1229 emit_byte(0xF2); | |
| 1230 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1231 emit_byte(0x0F); | |
| 1232 emit_byte(0x2C); | |
| 1233 emit_byte(0xC0 | encode); | |
| 1234 } | |
| 1235 | |
| 1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1237 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1238 emit_byte(0xF3); | |
| 1239 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1240 emit_byte(0x0F); | |
| 1241 emit_byte(0x2C); | |
| 1242 emit_byte(0xC0 | encode); | |
| 1243 } | |
| 1244 | |
| 1245 void Assembler::decl(Address dst) { | |
| 1246 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1247 InstructionMark im(this); | |
| 1248 prefix(dst); | |
| 1249 emit_byte(0xFF); | |
| 1250 emit_operand(rcx, dst); | |
| 1251 } | |
| 1252 | |
| 1253 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1255 InstructionMark im(this); | |
| 1256 emit_byte(0xF2); | |
| 1257 prefix(src, dst); | |
| 1258 emit_byte(0x0F); | |
| 1259 emit_byte(0x5E); | |
| 1260 emit_operand(dst, src); | |
| 1261 } | |
| 1262 | |
| 1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1265 emit_byte(0xF2); | |
| 1266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1267 emit_byte(0x0F); | |
| 1268 emit_byte(0x5E); | |
| 1269 emit_byte(0xC0 | encode); | |
| 1270 } | |
| 1271 | |
| 1272 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1274 InstructionMark im(this); | |
| 1275 emit_byte(0xF3); | |
| 1276 prefix(src, dst); | |
| 1277 emit_byte(0x0F); | |
| 1278 emit_byte(0x5E); | |
| 1279 emit_operand(dst, src); | |
| 1280 } | |
| 1281 | |
| 1282 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1283 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1284 emit_byte(0xF3); | |
| 1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1286 emit_byte(0x0F); | |
| 1287 emit_byte(0x5E); | |
| 1288 emit_byte(0xC0 | encode); | |
| 1289 } | |
| 1290 | |
| 1291 void Assembler::emms() { | |
| 1292 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1293 emit_byte(0x0F); | |
| 1294 emit_byte(0x77); | |
| 1295 } | |
| 1296 | |
| 1297 void Assembler::hlt() { | |
| 1298 emit_byte(0xF4); | |
| 1299 } | |
| 1300 | |
| 1301 void Assembler::idivl(Register src) { | |
| 1302 int encode = prefix_and_encode(src->encoding()); | |
| 1303 emit_byte(0xF7); | |
| 1304 emit_byte(0xF8 | encode); | |
| 1305 } | |
| 1306 | |
| 1920 | 1307 void Assembler::divl(Register src) { // Unsigned |
| 1308 int encode = prefix_and_encode(src->encoding()); | |
| 1309 emit_byte(0xF7); | |
| 1310 emit_byte(0xF0 | encode); | |
| 1311 } | |
| 1312 | |
| 304 | 1313 void Assembler::imull(Register dst, Register src) { |
| 1314 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1315 emit_byte(0x0F); | |
| 1316 emit_byte(0xAF); | |
| 1317 emit_byte(0xC0 | encode); | |
| 1318 } | |
| 1319 | |
| 1320 | |
| 1321 void Assembler::imull(Register dst, Register src, int value) { | |
| 1322 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1323 if (is8bit(value)) { | |
| 1324 emit_byte(0x6B); | |
| 1325 emit_byte(0xC0 | encode); | |
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1326 emit_byte(value & 0xFF); |
| 304 | 1327 } else { |
| 1328 emit_byte(0x69); | |
| 1329 emit_byte(0xC0 | encode); | |
| 1330 emit_long(value); | |
| 1331 } | |
| 1332 } | |
| 1333 | |
| 1334 void Assembler::incl(Address dst) { | |
| 1335 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1336 InstructionMark im(this); | |
| 1337 prefix(dst); | |
| 1338 emit_byte(0xFF); | |
| 1339 emit_operand(rax, dst); | |
| 1340 } | |
| 1341 | |
| 3851 | 1342 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
| 1343 InstructionMark im(this); | |
| 304 | 1344 assert((0 <= cc) && (cc < 16), "illegal cc"); |
| 1345 if (L.is_bound()) { | |
| 1346 address dst = target(L); | |
| 1347 assert(dst != NULL, "jcc most probably wrong"); | |
| 1348 | |
| 1349 const int short_size = 2; | |
| 1350 const int long_size = 6; | |
| 1351 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 3851 | 1352 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1353 // 0111 tttn #8-bit disp |
| 1354 emit_byte(0x70 | cc); | |
| 1355 emit_byte((offs - short_size) & 0xFF); | |
| 1356 } else { | |
| 1357 // 0000 1111 1000 tttn #32-bit disp | |
| 1358 assert(is_simm32(offs - long_size), | |
| 1359 "must be 32bit offset (call4)"); | |
| 1360 emit_byte(0x0F); | |
| 1361 emit_byte(0x80 | cc); | |
| 1362 emit_long(offs - long_size); | |
| 1363 } | |
| 1364 } else { | |
| 1365 // Note: could eliminate cond. jumps to this jump if condition | |
| 1366 // is the same however, seems to be rather unlikely case. | |
| 1367 // Note: use jccb() if label to be bound is very close to get | |
| 1368 // an 8-bit displacement | |
| 1369 L.add_patch_at(code(), locator()); | |
| 1370 emit_byte(0x0F); | |
| 1371 emit_byte(0x80 | cc); | |
| 1372 emit_long(0); | |
| 1373 } | |
| 1374 } | |
| 1375 | |
| 1376 void Assembler::jccb(Condition cc, Label& L) { | |
| 1377 if (L.is_bound()) { | |
| 1378 const int short_size = 2; | |
| 1379 address entry = target(L); | |
| 1380 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
| 1381 "Dispacement too large for a short jmp"); | |
| 1382 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
| 1383 // 0111 tttn #8-bit disp | |
| 1384 emit_byte(0x70 | cc); | |
| 1385 emit_byte((offs - short_size) & 0xFF); | |
| 1386 } else { | |
| 1387 InstructionMark im(this); | |
| 1388 L.add_patch_at(code(), locator()); | |
| 1389 emit_byte(0x70 | cc); | |
| 1390 emit_byte(0); | |
| 1391 } | |
| 1392 } | |
| 1393 | |
| 1394 void Assembler::jmp(Address adr) { | |
| 1395 InstructionMark im(this); | |
| 1396 prefix(adr); | |
| 1397 emit_byte(0xFF); | |
| 1398 emit_operand(rsp, adr); | |
| 1399 } | |
| 1400 | |
| 3851 | 1401 void Assembler::jmp(Label& L, bool maybe_short) { |
| 304 | 1402 if (L.is_bound()) { |
| 1403 address entry = target(L); | |
| 1404 assert(entry != NULL, "jmp most probably wrong"); | |
| 1405 InstructionMark im(this); | |
| 1406 const int short_size = 2; | |
| 1407 const int long_size = 5; | |
| 1408 intptr_t offs = entry - _code_pos; | |
| 3851 | 1409 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1410 emit_byte(0xEB); |
| 1411 emit_byte((offs - short_size) & 0xFF); | |
| 1412 } else { | |
| 1413 emit_byte(0xE9); | |
| 1414 emit_long(offs - long_size); | |
| 1415 } | |
| 1416 } else { | |
| 1417 // By default, forward jumps are always 32-bit displacements, since | |
| 1418 // we can't yet know where the label will be bound. If you're sure that | |
| 1419 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1420 // force an 8-bit displacement. | |
| 1421 InstructionMark im(this); | |
| 1422 L.add_patch_at(code(), locator()); | |
| 1423 emit_byte(0xE9); | |
| 1424 emit_long(0); | |
| 1425 } | |
| 1426 } | |
| 1427 | |
| 1428 void Assembler::jmp(Register entry) { | |
| 1429 int encode = prefix_and_encode(entry->encoding()); | |
| 1430 emit_byte(0xFF); | |
| 1431 emit_byte(0xE0 | encode); | |
| 1432 } | |
| 1433 | |
| 1434 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1435 InstructionMark im(this); | |
| 1436 emit_byte(0xE9); | |
| 1437 assert(dest != NULL, "must have a target"); | |
| 1438 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1439 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1440 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1441 } | |
| 1442 | |
| 1443 void Assembler::jmpb(Label& L) { | |
| 1444 if (L.is_bound()) { | |
| 1445 const int short_size = 2; | |
| 1446 address entry = target(L); | |
| 1447 assert(is8bit((entry - _code_pos) + short_size), | |
| 1448 "Dispacement too large for a short jmp"); | |
| 1449 assert(entry != NULL, "jmp most probably wrong"); | |
| 1450 intptr_t offs = entry - _code_pos; | |
| 1451 emit_byte(0xEB); | |
| 1452 emit_byte((offs - short_size) & 0xFF); | |
| 1453 } else { | |
| 1454 InstructionMark im(this); | |
| 1455 L.add_patch_at(code(), locator()); | |
| 1456 emit_byte(0xEB); | |
| 1457 emit_byte(0); | |
| 1458 } | |
| 1459 } | |
| 1460 | |
| 1461 void Assembler::ldmxcsr( Address src) { | |
| 1462 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1463 InstructionMark im(this); | |
| 1464 prefix(src); | |
| 1465 emit_byte(0x0F); | |
| 1466 emit_byte(0xAE); | |
| 1467 emit_operand(as_Register(2), src); | |
| 1468 } | |
| 1469 | |
| 1470 void Assembler::leal(Register dst, Address src) { | |
| 1471 InstructionMark im(this); | |
| 1472 #ifdef _LP64 | |
| 1473 emit_byte(0x67); // addr32 | |
| 1474 prefix(src, dst); | |
| 1475 #endif // LP64 | |
| 1476 emit_byte(0x8D); | |
| 1477 emit_operand(dst, src); | |
| 1478 } | |
| 1479 | |
| 1480 void Assembler::lock() { | |
| 1481 if (Atomics & 1) { | |
| 1482 // Emit either nothing, a NOP, or a NOP: prefix | |
| 1483 emit_byte(0x90) ; | |
| 1484 } else { | |
| 1485 emit_byte(0xF0); | |
| 1486 } | |
| 1487 } | |
| 1488 | |
|
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1489 void Assembler::lzcntl(Register dst, Register src) { |
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1490 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1491 emit_byte(0xF3); |
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1492 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1493 emit_byte(0x0F); |
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1494 emit_byte(0xBD); |
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1495 emit_byte(0xC0 | encode); |
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1496 } |
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1497 |
|
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1498 // Emit mfence instruction |
| 304 | 1499 void Assembler::mfence() { |
|
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1500 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1501 emit_byte( 0x0F ); |
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1502 emit_byte( 0xAE ); |
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1503 emit_byte( 0xF0 ); |
| 304 | 1504 } |
| 1505 | |
| 1506 void Assembler::mov(Register dst, Register src) { | |
| 1507 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1508 } | |
| 1509 | |
| 1510 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1511 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1512 int dstenc = dst->encoding(); | |
| 1513 int srcenc = src->encoding(); | |
| 1514 emit_byte(0x66); | |
| 1515 if (dstenc < 8) { | |
| 1516 if (srcenc >= 8) { | |
| 1517 prefix(REX_B); | |
| 1518 srcenc -= 8; | |
| 1519 } | |
| 1520 } else { | |
| 1521 if (srcenc < 8) { | |
| 1522 prefix(REX_R); | |
| 1523 } else { | |
| 1524 prefix(REX_RB); | |
| 1525 srcenc -= 8; | |
| 1526 } | |
| 1527 dstenc -= 8; | |
| 1528 } | |
| 1529 emit_byte(0x0F); | |
| 1530 emit_byte(0x28); | |
| 1531 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1532 } | |
| 1533 | |
| 1534 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1535 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1536 int dstenc = dst->encoding(); | |
| 1537 int srcenc = src->encoding(); | |
| 1538 if (dstenc < 8) { | |
| 1539 if (srcenc >= 8) { | |
| 1540 prefix(REX_B); | |
| 1541 srcenc -= 8; | |
| 1542 } | |
| 1543 } else { | |
| 1544 if (srcenc < 8) { | |
| 1545 prefix(REX_R); | |
| 1546 } else { | |
| 1547 prefix(REX_RB); | |
| 1548 srcenc -= 8; | |
| 1549 } | |
| 1550 dstenc -= 8; | |
| 1551 } | |
| 1552 emit_byte(0x0F); | |
| 1553 emit_byte(0x28); | |
| 1554 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1555 } | |
| 1556 | |
| 1557 void Assembler::movb(Register dst, Address src) { | |
| 1558 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1559 InstructionMark im(this); | |
| 1560 prefix(src, dst, true); | |
| 1561 emit_byte(0x8A); | |
| 1562 emit_operand(dst, src); | |
| 1563 } | |
| 1564 | |
| 1565 | |
| 1566 void Assembler::movb(Address dst, int imm8) { | |
| 1567 InstructionMark im(this); | |
| 1568 prefix(dst); | |
| 1569 emit_byte(0xC6); | |
| 1570 emit_operand(rax, dst, 1); | |
| 1571 emit_byte(imm8); | |
| 1572 } | |
| 1573 | |
| 1574 | |
| 1575 void Assembler::movb(Address dst, Register src) { | |
| 1576 assert(src->has_byte_register(), "must have byte register"); | |
| 1577 InstructionMark im(this); | |
| 1578 prefix(dst, src, true); | |
| 1579 emit_byte(0x88); | |
| 1580 emit_operand(src, dst); | |
| 1581 } | |
| 1582 | |
| 1583 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1584 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1585 emit_byte(0x66); | |
| 1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1587 emit_byte(0x0F); | |
| 1588 emit_byte(0x6E); | |
| 1589 emit_byte(0xC0 | encode); | |
| 1590 } | |
| 1591 | |
| 1592 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1593 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1594 emit_byte(0x66); | |
| 1595 // swap src/dst to get correct prefix | |
| 1596 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
| 1597 emit_byte(0x0F); | |
| 1598 emit_byte(0x7E); | |
| 1599 emit_byte(0xC0 | encode); | |
| 1600 } | |
| 1601 | |
|
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1602 void Assembler::movdl(XMMRegister dst, Address src) { |
|
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1603 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
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1604 InstructionMark im(this); |
|
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1605 emit_byte(0x66); |
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1606 prefix(src, dst); |
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1607 emit_byte(0x0F); |
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1608 emit_byte(0x6E); |
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1609 emit_operand(dst, src); |
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1610 } |
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1611 |
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1612 |
| 304 | 1613 void Assembler::movdqa(XMMRegister dst, Address src) { |
| 1614 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1615 InstructionMark im(this); | |
| 1616 emit_byte(0x66); | |
| 1617 prefix(src, dst); | |
| 1618 emit_byte(0x0F); | |
| 1619 emit_byte(0x6F); | |
| 1620 emit_operand(dst, src); | |
| 1621 } | |
| 1622 | |
| 1623 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
| 1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1625 emit_byte(0x66); | |
| 1626 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1627 emit_byte(0x0F); | |
| 1628 emit_byte(0x6F); | |
| 1629 emit_byte(0xC0 | encode); | |
| 1630 } | |
| 1631 | |
| 1632 void Assembler::movdqa(Address dst, XMMRegister src) { | |
| 1633 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1634 InstructionMark im(this); | |
| 1635 emit_byte(0x66); | |
| 1636 prefix(dst, src); | |
| 1637 emit_byte(0x0F); | |
| 1638 emit_byte(0x7F); | |
| 1639 emit_operand(src, dst); | |
| 1640 } | |
| 1641 | |
| 405 | 1642 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1644 InstructionMark im(this); | |
| 1645 emit_byte(0xF3); | |
| 1646 prefix(src, dst); | |
| 1647 emit_byte(0x0F); | |
| 1648 emit_byte(0x6F); | |
| 1649 emit_operand(dst, src); | |
| 1650 } | |
| 1651 | |
| 1652 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1654 emit_byte(0xF3); | |
| 1655 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1656 emit_byte(0x0F); | |
| 1657 emit_byte(0x6F); | |
| 1658 emit_byte(0xC0 | encode); | |
| 1659 } | |
| 1660 | |
| 1661 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1663 InstructionMark im(this); | |
| 1664 emit_byte(0xF3); | |
| 1665 prefix(dst, src); | |
| 1666 emit_byte(0x0F); | |
| 1667 emit_byte(0x7F); | |
| 1668 emit_operand(src, dst); | |
| 1669 } | |
| 1670 | |
| 304 | 1671 // Uses zero extension on 64bit |
| 1672 | |
| 1673 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1674 int encode = prefix_and_encode(dst->encoding()); | |
| 1675 emit_byte(0xB8 | encode); | |
| 1676 emit_long(imm32); | |
| 1677 } | |
| 1678 | |
| 1679 void Assembler::movl(Register dst, Register src) { | |
| 1680 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1681 emit_byte(0x8B); | |
| 1682 emit_byte(0xC0 | encode); | |
| 1683 } | |
| 1684 | |
| 1685 void Assembler::movl(Register dst, Address src) { | |
| 1686 InstructionMark im(this); | |
| 1687 prefix(src, dst); | |
| 1688 emit_byte(0x8B); | |
| 1689 emit_operand(dst, src); | |
| 1690 } | |
| 1691 | |
| 1692 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1693 InstructionMark im(this); | |
| 1694 prefix(dst); | |
| 1695 emit_byte(0xC7); | |
| 1696 emit_operand(rax, dst, 4); | |
| 1697 emit_long(imm32); | |
| 1698 } | |
| 1699 | |
| 1700 void Assembler::movl(Address dst, Register src) { | |
| 1701 InstructionMark im(this); | |
| 1702 prefix(dst, src); | |
| 1703 emit_byte(0x89); | |
| 1704 emit_operand(src, dst); | |
| 1705 } | |
| 1706 | |
| 1707 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1708 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1709 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1710 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1711 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1712 InstructionMark im(this); | |
| 1713 emit_byte(0x66); | |
| 1714 prefix(src, dst); | |
| 1715 emit_byte(0x0F); | |
| 1716 emit_byte(0x12); | |
| 1717 emit_operand(dst, src); | |
| 1718 } | |
| 1719 | |
| 1720 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1721 assert( VM_Version::supports_mmx(), "" ); | |
| 1722 emit_byte(0x0F); | |
| 1723 emit_byte(0x6F); | |
| 1724 emit_operand(dst, src); | |
| 1725 } | |
| 1726 | |
| 1727 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1728 assert( VM_Version::supports_mmx(), "" ); | |
| 1729 emit_byte(0x0F); | |
| 1730 emit_byte(0x7F); | |
| 1731 // workaround gcc (3.2.1-7a) bug | |
| 1732 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1733 // gcc will tail jump and try and reverse the parameters completely | |
| 1734 // obliterating dst in the process. By having a version available | |
| 1735 // that doesn't need to swap the args at the tail jump the bug is | |
| 1736 // avoided. | |
| 1737 emit_operand(dst, src); | |
| 1738 } | |
| 1739 | |
| 1740 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1741 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1742 InstructionMark im(this); | |
| 1743 emit_byte(0xF3); | |
| 1744 prefix(src, dst); | |
| 1745 emit_byte(0x0F); | |
| 1746 emit_byte(0x7E); | |
| 1747 emit_operand(dst, src); | |
| 1748 } | |
| 1749 | |
| 1750 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1751 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1752 InstructionMark im(this); | |
| 1753 emit_byte(0x66); | |
| 1754 prefix(dst, src); | |
| 1755 emit_byte(0x0F); | |
| 1756 emit_byte(0xD6); | |
| 1757 emit_operand(src, dst); | |
| 1758 } | |
| 1759 | |
| 1760 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1761 InstructionMark im(this); | |
| 1762 prefix(src, dst); | |
| 1763 emit_byte(0x0F); | |
| 1764 emit_byte(0xBE); | |
| 1765 emit_operand(dst, src); | |
| 1766 } | |
| 1767 | |
| 1768 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1769 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1770 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1771 emit_byte(0x0F); | |
| 1772 emit_byte(0xBE); | |
| 1773 emit_byte(0xC0 | encode); | |
| 1774 } | |
| 1775 | |
| 1776 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1778 emit_byte(0xF2); | |
| 1779 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1780 emit_byte(0x0F); | |
| 1781 emit_byte(0x10); | |
| 1782 emit_byte(0xC0 | encode); | |
| 1783 } | |
| 1784 | |
| 1785 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1786 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1787 InstructionMark im(this); | |
| 1788 emit_byte(0xF2); | |
| 1789 prefix(src, dst); | |
| 1790 emit_byte(0x0F); | |
| 1791 emit_byte(0x10); | |
| 1792 emit_operand(dst, src); | |
| 1793 } | |
| 1794 | |
| 1795 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1796 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1797 InstructionMark im(this); | |
| 1798 emit_byte(0xF2); | |
| 1799 prefix(dst, src); | |
| 1800 emit_byte(0x0F); | |
| 1801 emit_byte(0x11); | |
| 1802 emit_operand(src, dst); | |
| 1803 } | |
| 1804 | |
| 1805 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1807 emit_byte(0xF3); | |
| 1808 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1809 emit_byte(0x0F); | |
| 1810 emit_byte(0x10); | |
| 1811 emit_byte(0xC0 | encode); | |
| 1812 } | |
| 1813 | |
| 1814 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1815 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1816 InstructionMark im(this); | |
| 1817 emit_byte(0xF3); | |
| 1818 prefix(src, dst); | |
| 1819 emit_byte(0x0F); | |
| 1820 emit_byte(0x10); | |
| 1821 emit_operand(dst, src); | |
| 1822 } | |
| 1823 | |
| 1824 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1825 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1826 InstructionMark im(this); | |
| 1827 emit_byte(0xF3); | |
| 1828 prefix(dst, src); | |
| 1829 emit_byte(0x0F); | |
| 1830 emit_byte(0x11); | |
| 1831 emit_operand(src, dst); | |
| 1832 } | |
| 1833 | |
| 1834 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1835 InstructionMark im(this); | |
| 1836 prefix(src, dst); | |
| 1837 emit_byte(0x0F); | |
| 1838 emit_byte(0xBF); | |
| 1839 emit_operand(dst, src); | |
| 1840 } | |
| 1841 | |
| 1842 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1843 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1844 emit_byte(0x0F); | |
| 1845 emit_byte(0xBF); | |
| 1846 emit_byte(0xC0 | encode); | |
| 1847 } | |
| 1848 | |
| 1849 void Assembler::movw(Address dst, int imm16) { | |
| 1850 InstructionMark im(this); | |
| 1851 | |
| 1852 emit_byte(0x66); // switch to 16-bit mode | |
| 1853 prefix(dst); | |
| 1854 emit_byte(0xC7); | |
| 1855 emit_operand(rax, dst, 2); | |
| 1856 emit_word(imm16); | |
| 1857 } | |
| 1858 | |
| 1859 void Assembler::movw(Register dst, Address src) { | |
| 1860 InstructionMark im(this); | |
| 1861 emit_byte(0x66); | |
| 1862 prefix(src, dst); | |
| 1863 emit_byte(0x8B); | |
| 1864 emit_operand(dst, src); | |
| 1865 } | |
| 1866 | |
| 1867 void Assembler::movw(Address dst, Register src) { | |
| 1868 InstructionMark im(this); | |
| 1869 emit_byte(0x66); | |
| 1870 prefix(dst, src); | |
| 1871 emit_byte(0x89); | |
| 1872 emit_operand(src, dst); | |
| 1873 } | |
| 1874 | |
| 1875 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1876 InstructionMark im(this); | |
| 1877 prefix(src, dst); | |
| 1878 emit_byte(0x0F); | |
| 1879 emit_byte(0xB6); | |
| 1880 emit_operand(dst, src); | |
| 1881 } | |
| 1882 | |
| 1883 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1884 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1885 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1886 emit_byte(0x0F); | |
| 1887 emit_byte(0xB6); | |
| 1888 emit_byte(0xC0 | encode); | |
| 1889 } | |
| 1890 | |
| 1891 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1892 InstructionMark im(this); | |
| 1893 prefix(src, dst); | |
| 1894 emit_byte(0x0F); | |
| 1895 emit_byte(0xB7); | |
| 1896 emit_operand(dst, src); | |
| 1897 } | |
| 1898 | |
| 1899 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1900 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1901 emit_byte(0x0F); | |
| 1902 emit_byte(0xB7); | |
| 1903 emit_byte(0xC0 | encode); | |
| 1904 } | |
| 1905 | |
| 1906 void Assembler::mull(Address src) { | |
| 1907 InstructionMark im(this); | |
| 1908 prefix(src); | |
| 1909 emit_byte(0xF7); | |
| 1910 emit_operand(rsp, src); | |
| 1911 } | |
| 1912 | |
| 1913 void Assembler::mull(Register src) { | |
| 1914 int encode = prefix_and_encode(src->encoding()); | |
| 1915 emit_byte(0xF7); | |
| 1916 emit_byte(0xE0 | encode); | |
| 1917 } | |
| 1918 | |
| 1919 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1921 InstructionMark im(this); | |
| 1922 emit_byte(0xF2); | |
| 1923 prefix(src, dst); | |
| 1924 emit_byte(0x0F); | |
| 1925 emit_byte(0x59); | |
| 1926 emit_operand(dst, src); | |
| 1927 } | |
| 1928 | |
| 1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1931 emit_byte(0xF2); | |
| 1932 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1933 emit_byte(0x0F); | |
| 1934 emit_byte(0x59); | |
| 1935 emit_byte(0xC0 | encode); | |
| 1936 } | |
| 1937 | |
| 1938 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1940 InstructionMark im(this); | |
| 1941 emit_byte(0xF3); | |
| 1942 prefix(src, dst); | |
| 1943 emit_byte(0x0F); | |
| 1944 emit_byte(0x59); | |
| 1945 emit_operand(dst, src); | |
| 1946 } | |
| 1947 | |
| 1948 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1949 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1950 emit_byte(0xF3); | |
| 1951 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1952 emit_byte(0x0F); | |
| 1953 emit_byte(0x59); | |
| 1954 emit_byte(0xC0 | encode); | |
| 1955 } | |
| 1956 | |
| 1957 void Assembler::negl(Register dst) { | |
| 1958 int encode = prefix_and_encode(dst->encoding()); | |
| 1959 emit_byte(0xF7); | |
| 1960 emit_byte(0xD8 | encode); | |
| 1961 } | |
| 1962 | |
| 0 | 1963 void Assembler::nop(int i) { |
| 304 | 1964 #ifdef ASSERT |
| 0 | 1965 assert(i > 0, " "); |
| 304 | 1966 // The fancy nops aren't currently recognized by debuggers making it a |
| 1967 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1968 // speed is not an issue so simply use the single byte traditional nop | |
| 1969 // to do alignment. | |
| 1970 | |
| 1971 for (; i > 0 ; i--) emit_byte(0x90); | |
| 1972 return; | |
| 1973 | |
| 1974 #endif // ASSERT | |
| 1975 | |
| 0 | 1976 if (UseAddressNop && VM_Version::is_intel()) { |
| 1977 // | |
| 1978 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1979 // 1: 0x90 | |
| 1980 // 2: 0x66 0x90 | |
| 1981 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1982 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1983 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1984 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1985 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1986 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1987 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1988 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1989 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1990 | |
| 1991 // The rest coding is Intel specific - don't use consecutive address nops | |
| 1992 | |
| 1993 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1994 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1995 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1996 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1997 | |
| 1998 while(i >= 15) { | |
| 1999 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 2000 i -= 15; | |
| 2001 emit_byte(0x66); // size prefix | |
| 2002 emit_byte(0x66); // size prefix | |
| 2003 emit_byte(0x66); // size prefix | |
| 2004 addr_nop_8(); | |
| 2005 emit_byte(0x66); // size prefix | |
| 2006 emit_byte(0x66); // size prefix | |
| 2007 emit_byte(0x66); // size prefix | |
| 2008 emit_byte(0x90); // nop | |
| 2009 } | |
| 2010 switch (i) { | |
| 2011 case 14: | |
| 2012 emit_byte(0x66); // size prefix | |
| 2013 case 13: | |
| 2014 emit_byte(0x66); // size prefix | |
| 2015 case 12: | |
| 2016 addr_nop_8(); | |
| 2017 emit_byte(0x66); // size prefix | |
| 2018 emit_byte(0x66); // size prefix | |
| 2019 emit_byte(0x66); // size prefix | |
| 2020 emit_byte(0x90); // nop | |
| 2021 break; | |
| 2022 case 11: | |
| 2023 emit_byte(0x66); // size prefix | |
| 2024 case 10: | |
| 2025 emit_byte(0x66); // size prefix | |
| 2026 case 9: | |
| 2027 emit_byte(0x66); // size prefix | |
| 2028 case 8: | |
| 2029 addr_nop_8(); | |
| 2030 break; | |
| 2031 case 7: | |
| 2032 addr_nop_7(); | |
| 2033 break; | |
| 2034 case 6: | |
| 2035 emit_byte(0x66); // size prefix | |
| 2036 case 5: | |
| 2037 addr_nop_5(); | |
| 2038 break; | |
| 2039 case 4: | |
| 2040 addr_nop_4(); | |
| 2041 break; | |
| 2042 case 3: | |
| 2043 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2044 emit_byte(0x66); // size prefix | |
| 2045 case 2: | |
| 2046 emit_byte(0x66); // size prefix | |
| 2047 case 1: | |
| 2048 emit_byte(0x90); // nop | |
| 2049 break; | |
| 2050 default: | |
| 2051 assert(i == 0, " "); | |
| 2052 } | |
| 2053 return; | |
| 2054 } | |
| 2055 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2056 // | |
| 2057 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2058 // 1: 0x90 | |
| 2059 // 2: 0x66 0x90 | |
| 2060 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2061 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2062 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2063 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2064 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2065 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2066 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2067 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2068 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2069 | |
| 2070 // The rest coding is AMD specific - use consecutive address nops | |
| 2071 | |
| 2072 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2073 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2074 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2075 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2076 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2077 // Size prefixes (0x66) are added for larger sizes | |
| 2078 | |
| 2079 while(i >= 22) { | |
| 2080 i -= 11; | |
| 2081 emit_byte(0x66); // size prefix | |
| 2082 emit_byte(0x66); // size prefix | |
| 2083 emit_byte(0x66); // size prefix | |
| 2084 addr_nop_8(); | |
| 2085 } | |
| 2086 // Generate first nop for size between 21-12 | |
| 2087 switch (i) { | |
| 2088 case 21: | |
| 2089 i -= 1; | |
| 2090 emit_byte(0x66); // size prefix | |
| 2091 case 20: | |
| 2092 case 19: | |
| 2093 i -= 1; | |
| 2094 emit_byte(0x66); // size prefix | |
| 2095 case 18: | |
| 2096 case 17: | |
| 2097 i -= 1; | |
| 2098 emit_byte(0x66); // size prefix | |
| 2099 case 16: | |
| 2100 case 15: | |
| 2101 i -= 8; | |
| 2102 addr_nop_8(); | |
| 2103 break; | |
| 2104 case 14: | |
| 2105 case 13: | |
| 2106 i -= 7; | |
| 2107 addr_nop_7(); | |
| 2108 break; | |
| 2109 case 12: | |
| 2110 i -= 6; | |
| 2111 emit_byte(0x66); // size prefix | |
| 2112 addr_nop_5(); | |
| 2113 break; | |
| 2114 default: | |
| 2115 assert(i < 12, " "); | |
| 2116 } | |
| 2117 | |
| 2118 // Generate second nop for size between 11-1 | |
| 2119 switch (i) { | |
| 2120 case 11: | |
| 2121 emit_byte(0x66); // size prefix | |
| 2122 case 10: | |
| 2123 emit_byte(0x66); // size prefix | |
| 2124 case 9: | |
| 2125 emit_byte(0x66); // size prefix | |
| 2126 case 8: | |
| 2127 addr_nop_8(); | |
| 2128 break; | |
| 2129 case 7: | |
| 2130 addr_nop_7(); | |
| 2131 break; | |
| 2132 case 6: | |
| 2133 emit_byte(0x66); // size prefix | |
| 2134 case 5: | |
| 2135 addr_nop_5(); | |
| 2136 break; | |
| 2137 case 4: | |
| 2138 addr_nop_4(); | |
| 2139 break; | |
| 2140 case 3: | |
| 2141 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2142 emit_byte(0x66); // size prefix | |
| 2143 case 2: | |
| 2144 emit_byte(0x66); // size prefix | |
| 2145 case 1: | |
| 2146 emit_byte(0x90); // nop | |
| 2147 break; | |
| 2148 default: | |
| 2149 assert(i == 0, " "); | |
| 2150 } | |
| 2151 return; | |
| 2152 } | |
| 2153 | |
| 2154 // Using nops with size prefixes "0x66 0x90". | |
| 2155 // From AMD Optimization Guide: | |
| 2156 // 1: 0x90 | |
| 2157 // 2: 0x66 0x90 | |
| 2158 // 3: 0x66 0x66 0x90 | |
| 2159 // 4: 0x66 0x66 0x66 0x90 | |
| 2160 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2161 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2162 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2163 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2164 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2165 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2166 // | |
| 2167 while(i > 12) { | |
| 2168 i -= 4; | |
| 2169 emit_byte(0x66); // size prefix | |
| 2170 emit_byte(0x66); | |
| 2171 emit_byte(0x66); | |
| 2172 emit_byte(0x90); // nop | |
| 2173 } | |
| 2174 // 1 - 12 nops | |
| 2175 if(i > 8) { | |
| 2176 if(i > 9) { | |
| 2177 i -= 1; | |
| 2178 emit_byte(0x66); | |
| 2179 } | |
| 2180 i -= 3; | |
| 2181 emit_byte(0x66); | |
| 2182 emit_byte(0x66); | |
| 2183 emit_byte(0x90); | |
| 2184 } | |
| 2185 // 1 - 8 nops | |
| 2186 if(i > 4) { | |
| 2187 if(i > 6) { | |
| 2188 i -= 1; | |
| 2189 emit_byte(0x66); | |
| 2190 } | |
| 2191 i -= 3; | |
| 2192 emit_byte(0x66); | |
| 2193 emit_byte(0x66); | |
| 2194 emit_byte(0x90); | |
| 2195 } | |
| 2196 switch (i) { | |
| 2197 case 4: | |
| 2198 emit_byte(0x66); | |
| 2199 case 3: | |
| 2200 emit_byte(0x66); | |
| 2201 case 2: | |
| 2202 emit_byte(0x66); | |
| 2203 case 1: | |
| 2204 emit_byte(0x90); | |
| 2205 break; | |
| 2206 default: | |
| 2207 assert(i == 0, " "); | |
| 2208 } | |
| 2209 } | |
| 2210 | |
| 304 | 2211 void Assembler::notl(Register dst) { |
| 2212 int encode = prefix_and_encode(dst->encoding()); | |
| 2213 emit_byte(0xF7); | |
| 2214 emit_byte(0xD0 | encode ); | |
| 2215 } | |
| 2216 | |
| 2217 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2218 InstructionMark im(this); | |
| 2219 prefix(dst); | |
|
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2220 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2221 } |
| 2222 | |
| 2223 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2224 prefix(dst); | |
| 2225 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2226 } | |
| 2227 | |
| 2228 void Assembler::orl(Register dst, Address src) { | |
| 2229 InstructionMark im(this); | |
| 2230 prefix(src, dst); | |
| 2231 emit_byte(0x0B); | |
| 2232 emit_operand(dst, src); | |
| 2233 } | |
| 2234 | |
| 2235 void Assembler::orl(Register dst, Register src) { | |
| 2236 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2237 emit_arith(0x0B, 0xC0, dst, src); | |
| 2238 } | |
| 2239 | |
| 681 | 2240 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2241 assert(VM_Version::supports_sse4_2(), ""); | |
| 2242 | |
| 2243 InstructionMark im(this); | |
| 2244 emit_byte(0x66); | |
| 2245 prefix(src, dst); | |
| 2246 emit_byte(0x0F); | |
| 2247 emit_byte(0x3A); | |
| 2248 emit_byte(0x61); | |
| 2249 emit_operand(dst, src); | |
| 2250 emit_byte(imm8); | |
| 2251 } | |
| 2252 | |
| 2253 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2254 assert(VM_Version::supports_sse4_2(), ""); | |
| 2255 | |
| 2256 emit_byte(0x66); | |
| 2257 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 2258 emit_byte(0x0F); | |
| 2259 emit_byte(0x3A); | |
| 2260 emit_byte(0x61); | |
| 2261 emit_byte(0xC0 | encode); | |
| 2262 emit_byte(imm8); | |
| 2263 } | |
| 2264 | |
| 304 | 2265 // generic |
| 2266 void Assembler::pop(Register dst) { | |
| 2267 int encode = prefix_and_encode(dst->encoding()); | |
| 2268 emit_byte(0x58 | encode); | |
| 2269 } | |
| 2270 | |
|
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2271 void Assembler::popcntl(Register dst, Address src) { |
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2272 assert(VM_Version::supports_popcnt(), "must support"); |
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2273 InstructionMark im(this); |
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2274 emit_byte(0xF3); |
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2275 prefix(src, dst); |
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2276 emit_byte(0x0F); |
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2277 emit_byte(0xB8); |
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2278 emit_operand(dst, src); |
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2279 } |
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2280 |
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2281 void Assembler::popcntl(Register dst, Register src) { |
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2282 assert(VM_Version::supports_popcnt(), "must support"); |
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2283 emit_byte(0xF3); |
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2284 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2285 emit_byte(0x0F); |
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2286 emit_byte(0xB8); |
|
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2287 emit_byte(0xC0 | encode); |
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2288 } |
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2289 |
| 304 | 2290 void Assembler::popf() { |
| 2291 emit_byte(0x9D); | |
| 2292 } | |
| 2293 | |
| 1060 | 2294 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2295 void Assembler::popl(Address dst) { |
| 2296 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2297 InstructionMark im(this); | |
| 2298 prefix(dst); | |
| 2299 emit_byte(0x8F); | |
| 2300 emit_operand(rax, dst); | |
| 2301 } | |
| 1060 | 2302 #endif |
| 304 | 2303 |
| 2304 void Assembler::prefetch_prefix(Address src) { | |
| 2305 prefix(src); | |
| 2306 emit_byte(0x0F); | |
| 2307 } | |
| 2308 | |
| 2309 void Assembler::prefetchnta(Address src) { | |
|
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2310 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
| 304 | 2311 InstructionMark im(this); |
| 2312 prefetch_prefix(src); | |
| 2313 emit_byte(0x18); | |
| 2314 emit_operand(rax, src); // 0, src | |
| 2315 } | |
| 2316 | |
| 2317 void Assembler::prefetchr(Address src) { | |
| 3854 | 2318 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2319 InstructionMark im(this); |
| 2320 prefetch_prefix(src); | |
| 2321 emit_byte(0x0D); | |
| 2322 emit_operand(rax, src); // 0, src | |
| 2323 } | |
| 2324 | |
| 2325 void Assembler::prefetcht0(Address src) { | |
| 2326 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2327 InstructionMark im(this); | |
| 2328 prefetch_prefix(src); | |
| 2329 emit_byte(0x18); | |
| 2330 emit_operand(rcx, src); // 1, src | |
| 2331 } | |
| 2332 | |
| 2333 void Assembler::prefetcht1(Address src) { | |
| 2334 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2335 InstructionMark im(this); | |
| 2336 prefetch_prefix(src); | |
| 2337 emit_byte(0x18); | |
| 2338 emit_operand(rdx, src); // 2, src | |
| 2339 } | |
| 2340 | |
| 2341 void Assembler::prefetcht2(Address src) { | |
| 2342 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2343 InstructionMark im(this); | |
| 2344 prefetch_prefix(src); | |
| 2345 emit_byte(0x18); | |
| 2346 emit_operand(rbx, src); // 3, src | |
| 2347 } | |
| 2348 | |
| 2349 void Assembler::prefetchw(Address src) { | |
| 3854 | 2350 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2351 InstructionMark im(this); |
| 2352 prefetch_prefix(src); | |
| 2353 emit_byte(0x0D); | |
| 2354 emit_operand(rcx, src); // 1, src | |
| 2355 } | |
| 2356 | |
| 2357 void Assembler::prefix(Prefix p) { | |
| 2358 a_byte(p); | |
| 2359 } | |
| 2360 | |
| 2262 | 2361 void Assembler::por(XMMRegister dst, XMMRegister src) { |
| 2362 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2363 | |
| 2364 emit_byte(0x66); | |
| 2365 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2366 emit_byte(0x0F); | |
| 2367 | |
| 2368 emit_byte(0xEB); | |
| 2369 emit_byte(0xC0 | encode); | |
| 2370 } | |
| 2371 | |
| 304 | 2372 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
| 2373 assert(isByte(mode), "invalid value"); | |
| 2374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2375 | |
| 2376 emit_byte(0x66); | |
| 2377 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2378 emit_byte(0x0F); | |
| 2379 emit_byte(0x70); | |
| 2380 emit_byte(0xC0 | encode); | |
| 2381 emit_byte(mode & 0xFF); | |
| 2382 | |
| 2383 } | |
| 2384 | |
| 2385 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2386 assert(isByte(mode), "invalid value"); | |
| 2387 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2388 | |
| 2389 InstructionMark im(this); | |
| 2390 emit_byte(0x66); | |
| 2391 prefix(src, dst); | |
| 2392 emit_byte(0x0F); | |
| 2393 emit_byte(0x70); | |
| 2394 emit_operand(dst, src); | |
| 2395 emit_byte(mode & 0xFF); | |
| 2396 } | |
| 2397 | |
| 2398 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2399 assert(isByte(mode), "invalid value"); | |
| 2400 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2401 | |
| 2402 emit_byte(0xF2); | |
| 2403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2404 emit_byte(0x0F); | |
| 2405 emit_byte(0x70); | |
| 2406 emit_byte(0xC0 | encode); | |
| 2407 emit_byte(mode & 0xFF); | |
| 2408 } | |
| 2409 | |
| 2410 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2411 assert(isByte(mode), "invalid value"); | |
| 2412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2413 | |
| 2414 InstructionMark im(this); | |
| 2415 emit_byte(0xF2); | |
| 2416 prefix(src, dst); // QQ new | |
| 2417 emit_byte(0x0F); | |
| 2418 emit_byte(0x70); | |
| 2419 emit_operand(dst, src); | |
| 2420 emit_byte(mode & 0xFF); | |
| 2421 } | |
| 2422 | |
| 2423 void Assembler::psrlq(XMMRegister dst, int shift) { | |
|
2320
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2424 // Shift 64 bit value logically right by specified number of bits. |
|
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2425 // HMM Table D-1 says sse2 or mmx. |
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2426 // Do not confuse it with psrldq SSE2 instruction which |
|
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2427 // shifts 128 bit value in xmm register by number of bytes. |
| 304 | 2428 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
| 2429 | |
| 2430 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
| 2431 emit_byte(0x66); | |
| 2432 emit_byte(0x0F); | |
| 2433 emit_byte(0x73); | |
| 2434 emit_byte(0xC0 | encode); | |
| 2435 emit_byte(shift); | |
| 2436 } | |
| 2437 | |
|
2320
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2438 void Assembler::psrldq(XMMRegister dst, int shift) { |
|
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2439 // Shift 128 bit value in xmm register by number of bytes. |
|
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2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
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2441 |
|
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2442 int encode = prefixq_and_encode(xmm3->encoding(), dst->encoding()); |
|
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2443 emit_byte(0x66); |
|
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2444 emit_byte(0x0F); |
|
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2445 emit_byte(0x73); |
|
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2446 emit_byte(0xC0 | encode); |
|
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2447 emit_byte(shift); |
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2448 } |
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2449 |
| 681 | 2450 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2451 assert(VM_Version::supports_sse4_1(), ""); | |
| 2452 | |
| 2453 InstructionMark im(this); | |
| 2454 emit_byte(0x66); | |
| 2455 prefix(src, dst); | |
| 2456 emit_byte(0x0F); | |
| 2457 emit_byte(0x38); | |
| 2458 emit_byte(0x17); | |
| 2459 emit_operand(dst, src); | |
| 2460 } | |
| 2461 | |
| 2462 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2463 assert(VM_Version::supports_sse4_1(), ""); | |
| 2464 | |
| 2465 emit_byte(0x66); | |
| 2466 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 2467 emit_byte(0x0F); | |
| 2468 emit_byte(0x38); | |
| 2469 emit_byte(0x17); | |
| 2470 emit_byte(0xC0 | encode); | |
| 2471 } | |
| 2472 | |
| 304 | 2473 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2474 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2475 emit_byte(0x66); | |
| 2476 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2477 emit_byte(0x0F); | |
| 2478 emit_byte(0x60); | |
| 2479 emit_byte(0xC0 | encode); | |
| 2480 } | |
| 2481 | |
| 2482 void Assembler::push(int32_t imm32) { | |
| 2483 // in 64bits we push 64bits onto the stack but only | |
| 2484 // take a 32bit immediate | |
| 2485 emit_byte(0x68); | |
| 2486 emit_long(imm32); | |
| 2487 } | |
| 2488 | |
| 2489 void Assembler::push(Register src) { | |
| 2490 int encode = prefix_and_encode(src->encoding()); | |
| 2491 | |
| 2492 emit_byte(0x50 | encode); | |
| 2493 } | |
| 2494 | |
| 2495 void Assembler::pushf() { | |
| 2496 emit_byte(0x9C); | |
| 2497 } | |
| 2498 | |
| 1060 | 2499 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2500 void Assembler::pushl(Address src) { |
| 2501 // Note this will push 64bit on 64bit | |
| 2502 InstructionMark im(this); | |
| 2503 prefix(src); | |
| 2504 emit_byte(0xFF); | |
| 2505 emit_operand(rsi, src); | |
| 2506 } | |
| 1060 | 2507 #endif |
| 304 | 2508 |
| 2509 void Assembler::pxor(XMMRegister dst, Address src) { | |
| 2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2511 InstructionMark im(this); | |
| 2512 emit_byte(0x66); | |
| 2513 prefix(src, dst); | |
| 2514 emit_byte(0x0F); | |
| 2515 emit_byte(0xEF); | |
| 2516 emit_operand(dst, src); | |
| 2517 } | |
| 2518 | |
| 2519 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
| 2520 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2521 InstructionMark im(this); | |
| 2522 emit_byte(0x66); | |
| 2523 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2524 emit_byte(0x0F); | |
| 2525 emit_byte(0xEF); | |
| 2526 emit_byte(0xC0 | encode); | |
| 2527 } | |
| 2528 | |
| 2529 void Assembler::rcll(Register dst, int imm8) { | |
| 2530 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2531 int encode = prefix_and_encode(dst->encoding()); | |
| 2532 if (imm8 == 1) { | |
| 2533 emit_byte(0xD1); | |
| 2534 emit_byte(0xD0 | encode); | |
| 2535 } else { | |
| 2536 emit_byte(0xC1); | |
| 2537 emit_byte(0xD0 | encode); | |
| 2538 emit_byte(imm8); | |
| 2539 } | |
| 2540 } | |
| 2541 | |
| 2542 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2543 // generic | |
| 2544 void Assembler::rep_mov() { | |
| 2545 emit_byte(0xF3); | |
| 2546 // MOVSQ | |
| 2547 LP64_ONLY(prefix(REX_W)); | |
| 2548 emit_byte(0xA5); | |
| 2549 } | |
| 2550 | |
| 2551 // sets rcx pointer sized words with rax, value at [edi] | |
| 2552 // generic | |
| 2553 void Assembler::rep_set() { // rep_set | |
| 2554 emit_byte(0xF3); | |
| 2555 // STOSQ | |
| 2556 LP64_ONLY(prefix(REX_W)); | |
| 2557 emit_byte(0xAB); | |
| 2558 } | |
| 2559 | |
| 2560 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2561 // generic | |
| 2562 void Assembler::repne_scan() { // repne_scan | |
| 2563 emit_byte(0xF2); | |
| 2564 // SCASQ | |
| 2565 LP64_ONLY(prefix(REX_W)); | |
| 2566 emit_byte(0xAF); | |
| 2567 } | |
| 2568 | |
| 2569 #ifdef _LP64 | |
| 2570 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2571 // generic | |
| 2572 void Assembler::repne_scanl() { // repne_scan | |
| 2573 emit_byte(0xF2); | |
| 2574 // SCASL | |
| 2575 emit_byte(0xAF); | |
| 2576 } | |
| 2577 #endif | |
| 2578 | |
| 0 | 2579 void Assembler::ret(int imm16) { |
| 2580 if (imm16 == 0) { | |
| 2581 emit_byte(0xC3); | |
| 2582 } else { | |
| 2583 emit_byte(0xC2); | |
| 2584 emit_word(imm16); | |
| 2585 } | |
| 2586 } | |
| 2587 | |
| 304 | 2588 void Assembler::sahf() { |
| 2589 #ifdef _LP64 | |
| 2590 // Not supported in 64bit mode | |
| 2591 ShouldNotReachHere(); | |
| 2592 #endif | |
| 2593 emit_byte(0x9E); | |
| 2594 } | |
| 2595 | |
| 2596 void Assembler::sarl(Register dst, int imm8) { | |
| 2597 int encode = prefix_and_encode(dst->encoding()); | |
| 2598 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2599 if (imm8 == 1) { | |
| 2600 emit_byte(0xD1); | |
| 2601 emit_byte(0xF8 | encode); | |
| 2602 } else { | |
| 2603 emit_byte(0xC1); | |
| 2604 emit_byte(0xF8 | encode); | |
| 2605 emit_byte(imm8); | |
| 2606 } | |
| 2607 } | |
| 2608 | |
| 2609 void Assembler::sarl(Register dst) { | |
| 2610 int encode = prefix_and_encode(dst->encoding()); | |
| 2611 emit_byte(0xD3); | |
| 2612 emit_byte(0xF8 | encode); | |
| 2613 } | |
| 2614 | |
| 2615 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2616 InstructionMark im(this); | |
| 2617 prefix(dst); | |
| 2618 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2619 } | |
| 2620 | |
| 2621 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2622 prefix(dst); | |
| 2623 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2624 } | |
| 2625 | |
| 2626 | |
| 2627 void Assembler::sbbl(Register dst, Address src) { | |
| 2628 InstructionMark im(this); | |
| 2629 prefix(src, dst); | |
| 2630 emit_byte(0x1B); | |
| 2631 emit_operand(dst, src); | |
| 2632 } | |
| 2633 | |
| 2634 void Assembler::sbbl(Register dst, Register src) { | |
| 2635 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2636 emit_arith(0x1B, 0xC0, dst, src); | |
| 2637 } | |
| 2638 | |
| 2639 void Assembler::setb(Condition cc, Register dst) { | |
| 2640 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2641 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2642 emit_byte(0x0F); |
| 304 | 2643 emit_byte(0x90 | cc); |
| 2644 emit_byte(0xC0 | encode); | |
| 2645 } | |
| 2646 | |
| 2647 void Assembler::shll(Register dst, int imm8) { | |
| 2648 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2649 int encode = prefix_and_encode(dst->encoding()); | |
| 2650 if (imm8 == 1 ) { | |
| 2651 emit_byte(0xD1); | |
| 2652 emit_byte(0xE0 | encode); | |
| 2653 } else { | |
| 2654 emit_byte(0xC1); | |
| 2655 emit_byte(0xE0 | encode); | |
| 2656 emit_byte(imm8); | |
| 2657 } | |
| 2658 } | |
| 2659 | |
| 2660 void Assembler::shll(Register dst) { | |
| 2661 int encode = prefix_and_encode(dst->encoding()); | |
| 2662 emit_byte(0xD3); | |
| 2663 emit_byte(0xE0 | encode); | |
| 2664 } | |
| 2665 | |
| 2666 void Assembler::shrl(Register dst, int imm8) { | |
| 2667 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2668 int encode = prefix_and_encode(dst->encoding()); | |
| 2669 emit_byte(0xC1); | |
| 2670 emit_byte(0xE8 | encode); | |
| 2671 emit_byte(imm8); | |
| 2672 } | |
| 2673 | |
| 2674 void Assembler::shrl(Register dst) { | |
| 2675 int encode = prefix_and_encode(dst->encoding()); | |
| 2676 emit_byte(0xD3); | |
| 2677 emit_byte(0xE8 | encode); | |
| 2678 } | |
| 0 | 2679 |
| 2680 // copies a single word from [esi] to [edi] | |
| 2681 void Assembler::smovl() { | |
| 2682 emit_byte(0xA5); | |
| 2683 } | |
| 2684 | |
| 304 | 2685 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2686 // HMM Table D-1 says sse2 | |
| 2687 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2688 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2689 emit_byte(0xF2); | |
| 2690 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2691 emit_byte(0x0F); | |
| 2692 emit_byte(0x51); | |
| 2693 emit_byte(0xC0 | encode); | |
| 2694 } | |
| 2695 | |
| 2008 | 2696 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2698 InstructionMark im(this); | |
| 2699 emit_byte(0xF2); | |
| 2700 prefix(src, dst); | |
| 2701 emit_byte(0x0F); | |
| 2702 emit_byte(0x51); | |
| 2703 emit_operand(dst, src); | |
| 2704 } | |
| 2705 | |
| 2706 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 2707 // HMM Table D-1 says sse2 | |
| 2708 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2710 emit_byte(0xF3); | |
| 2711 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2712 emit_byte(0x0F); | |
| 2713 emit_byte(0x51); | |
| 2714 emit_byte(0xC0 | encode); | |
| 2715 } | |
| 2716 | |
| 2717 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
| 2718 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2719 InstructionMark im(this); | |
| 2720 emit_byte(0xF3); | |
| 2721 prefix(src, dst); | |
| 2722 emit_byte(0x0F); | |
| 2723 emit_byte(0x51); | |
| 2724 emit_operand(dst, src); | |
| 2725 } | |
| 2726 | |
| 304 | 2727 void Assembler::stmxcsr( Address dst) { |
| 2728 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2729 InstructionMark im(this); | |
| 2730 prefix(dst); | |
| 2731 emit_byte(0x0F); | |
| 2732 emit_byte(0xAE); | |
| 2733 emit_operand(as_Register(3), dst); | |
| 2734 } | |
| 2735 | |
| 2736 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2737 InstructionMark im(this); | |
| 2738 prefix(dst); | |
|
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2739 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2740 } |
| 2741 | |
| 2742 void Assembler::subl(Address dst, Register src) { | |
| 2743 InstructionMark im(this); | |
| 2744 prefix(dst, src); | |
| 2745 emit_byte(0x29); | |
| 2746 emit_operand(src, dst); | |
| 2747 } | |
| 2748 | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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changeset
|
2749 void Assembler::subl(Register dst, int32_t imm32) { |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
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diff
changeset
|
2750 prefix(dst); |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
changeset
|
2751 emit_arith(0x81, 0xE8, dst, imm32); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2752 } |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2753 |
| 304 | 2754 void Assembler::subl(Register dst, Address src) { |
| 2755 InstructionMark im(this); | |
| 2756 prefix(src, dst); | |
| 2757 emit_byte(0x2B); | |
| 2758 emit_operand(dst, src); | |
| 2759 } | |
| 2760 | |
| 2761 void Assembler::subl(Register dst, Register src) { | |
| 2762 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2763 emit_arith(0x2B, 0xC0, dst, src); | |
| 2764 } | |
| 2765 | |
| 2766 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2767 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2768 emit_byte(0xF2); | |
| 2769 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2770 emit_byte(0x0F); | |
| 2771 emit_byte(0x5C); | |
| 2772 emit_byte(0xC0 | encode); | |
| 2773 } | |
| 2774 | |
| 2775 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2776 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2777 InstructionMark im(this); | |
| 2778 emit_byte(0xF2); | |
| 2779 prefix(src, dst); | |
| 2780 emit_byte(0x0F); | |
| 2781 emit_byte(0x5C); | |
| 2782 emit_operand(dst, src); | |
| 2783 } | |
| 2784 | |
| 2785 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2786 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 0 | 2787 emit_byte(0xF3); |
| 304 | 2788 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
| 2789 emit_byte(0x0F); | |
| 2790 emit_byte(0x5C); | |
| 2791 emit_byte(0xC0 | encode); | |
| 2792 } | |
| 2793 | |
| 2794 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2795 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2796 InstructionMark im(this); | |
| 2797 emit_byte(0xF3); | |
| 2798 prefix(src, dst); | |
| 2799 emit_byte(0x0F); | |
| 2800 emit_byte(0x5C); | |
| 2801 emit_operand(dst, src); | |
| 2802 } | |
| 2803 | |
| 2804 void Assembler::testb(Register dst, int imm8) { | |
| 2805 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2806 (void) prefix_and_encode(dst->encoding(), true); | |
| 2807 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2808 } | |
| 2809 | |
| 2810 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2811 // not using emit_arith because test | |
| 2812 // doesn't support sign-extension of | |
| 2813 // 8bit operands | |
| 2814 int encode = dst->encoding(); | |
| 2815 if (encode == 0) { | |
| 2816 emit_byte(0xA9); | |
| 2817 } else { | |
| 2818 encode = prefix_and_encode(encode); | |
| 2819 emit_byte(0xF7); | |
| 2820 emit_byte(0xC0 | encode); | |
| 2821 } | |
| 2822 emit_long(imm32); | |
| 2823 } | |
| 2824 | |
| 2825 void Assembler::testl(Register dst, Register src) { | |
| 2826 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2827 emit_arith(0x85, 0xC0, dst, src); | |
| 2828 } | |
| 2829 | |
| 2830 void Assembler::testl(Register dst, Address src) { | |
| 2831 InstructionMark im(this); | |
| 2832 prefix(src, dst); | |
| 2833 emit_byte(0x85); | |
| 2834 emit_operand(dst, src); | |
| 2835 } | |
| 2836 | |
| 2837 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2839 emit_byte(0x66); | |
| 2840 ucomiss(dst, src); | |
| 2841 } | |
| 2842 | |
| 2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2844 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2845 emit_byte(0x66); | |
| 2846 ucomiss(dst, src); | |
| 2847 } | |
| 2848 | |
| 2849 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2850 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2851 | |
| 2852 InstructionMark im(this); | |
| 2853 prefix(src, dst); | |
| 2854 emit_byte(0x0F); | |
| 2855 emit_byte(0x2E); | |
| 2856 emit_operand(dst, src); | |
| 2857 } | |
| 2858 | |
| 2859 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2860 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2861 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2862 emit_byte(0x0F); | |
| 2863 emit_byte(0x2E); | |
| 2864 emit_byte(0xC0 | encode); | |
| 2865 } | |
| 2866 | |
| 2867 | |
| 2868 void Assembler::xaddl(Address dst, Register src) { | |
| 2869 InstructionMark im(this); | |
| 2870 prefix(dst, src); | |
| 0 | 2871 emit_byte(0x0F); |
| 304 | 2872 emit_byte(0xC1); |
| 2873 emit_operand(src, dst); | |
| 2874 } | |
| 2875 | |
| 2876 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2877 InstructionMark im(this); | |
| 2878 prefix(src, dst); | |
| 2879 emit_byte(0x87); | |
| 2880 emit_operand(dst, src); | |
| 2881 } | |
| 2882 | |
| 2883 void Assembler::xchgl(Register dst, Register src) { | |
| 2884 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2885 emit_byte(0x87); | |
| 2886 emit_byte(0xc0 | encode); | |
| 2887 } | |
| 2888 | |
| 2889 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2890 prefix(dst); | |
| 2891 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2892 } | |
| 2893 | |
| 2894 void Assembler::xorl(Register dst, Address src) { | |
| 2895 InstructionMark im(this); | |
| 2896 prefix(src, dst); | |
| 2897 emit_byte(0x33); | |
| 2898 emit_operand(dst, src); | |
| 2899 } | |
| 2900 | |
| 2901 void Assembler::xorl(Register dst, Register src) { | |
| 2902 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2903 emit_arith(0x33, 0xC0, dst, src); | |
| 2904 } | |
| 2905 | |
| 2906 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
| 2907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2908 emit_byte(0x66); | |
| 2909 xorps(dst, src); | |
| 2910 } | |
| 2911 | |
| 2912 void Assembler::xorpd(XMMRegister dst, Address src) { | |
| 2913 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2914 InstructionMark im(this); | |
| 2915 emit_byte(0x66); | |
| 2916 prefix(src, dst); | |
| 2917 emit_byte(0x0F); | |
| 2918 emit_byte(0x57); | |
| 2919 emit_operand(dst, src); | |
| 2920 } | |
| 2921 | |
| 2922 | |
| 2923 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
| 2924 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2925 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2926 emit_byte(0x0F); | |
| 2927 emit_byte(0x57); | |
| 2928 emit_byte(0xC0 | encode); | |
| 2929 } | |
| 2930 | |
| 2931 void Assembler::xorps(XMMRegister dst, Address src) { | |
| 2932 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2933 InstructionMark im(this); | |
| 2934 prefix(src, dst); | |
| 2935 emit_byte(0x0F); | |
| 2936 emit_byte(0x57); | |
| 2937 emit_operand(dst, src); | |
| 2938 } | |
| 2939 | |
| 2940 #ifndef _LP64 | |
| 2941 // 32bit only pieces of the assembler | |
| 2942 | |
| 2943 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2944 // NO PREFIX AS NEVER 64BIT | |
| 2945 InstructionMark im(this); | |
| 2946 emit_byte(0x81); | |
| 2947 emit_byte(0xF8 | src1->encoding()); | |
| 2948 emit_data(imm32, rspec, 0); | |
| 2949 } | |
| 2950 | |
| 2951 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2952 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 2953 InstructionMark im(this); | |
| 2954 emit_byte(0x81); | |
| 2955 emit_operand(rdi, src1); | |
| 2956 emit_data(imm32, rspec, 0); | |
| 2957 } | |
| 2958 | |
| 2959 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 2960 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 2961 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 2962 void Assembler::cmpxchg8(Address adr) { | |
| 2963 InstructionMark im(this); | |
| 2964 emit_byte(0x0F); | |
| 2965 emit_byte(0xc7); | |
| 2966 emit_operand(rcx, adr); | |
| 2967 } | |
| 2968 | |
| 2969 void Assembler::decl(Register dst) { | |
| 2970 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 2971 emit_byte(0x48 | dst->encoding()); | |
| 2972 } | |
| 2973 | |
| 2974 #endif // _LP64 | |
| 2975 | |
| 2976 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 2977 | |
| 2978 void Assembler::fabs() { | |
| 2979 emit_byte(0xD9); | |
| 2980 emit_byte(0xE1); | |
| 2981 } | |
| 2982 | |
| 2983 void Assembler::fadd(int i) { | |
| 2984 emit_farith(0xD8, 0xC0, i); | |
| 2985 } | |
| 2986 | |
| 2987 void Assembler::fadd_d(Address src) { | |
| 2988 InstructionMark im(this); | |
| 2989 emit_byte(0xDC); | |
| 2990 emit_operand32(rax, src); | |
| 2991 } | |
| 2992 | |
| 2993 void Assembler::fadd_s(Address src) { | |
| 2994 InstructionMark im(this); | |
| 2995 emit_byte(0xD8); | |
| 2996 emit_operand32(rax, src); | |
| 2997 } | |
| 2998 | |
| 2999 void Assembler::fadda(int i) { | |
| 3000 emit_farith(0xDC, 0xC0, i); | |
| 3001 } | |
| 3002 | |
| 3003 void Assembler::faddp(int i) { | |
| 3004 emit_farith(0xDE, 0xC0, i); | |
| 3005 } | |
| 3006 | |
| 3007 void Assembler::fchs() { | |
| 3008 emit_byte(0xD9); | |
| 3009 emit_byte(0xE0); | |
| 3010 } | |
| 3011 | |
| 3012 void Assembler::fcom(int i) { | |
| 3013 emit_farith(0xD8, 0xD0, i); | |
| 3014 } | |
| 3015 | |
| 3016 void Assembler::fcomp(int i) { | |
| 3017 emit_farith(0xD8, 0xD8, i); | |
| 3018 } | |
| 3019 | |
| 3020 void Assembler::fcomp_d(Address src) { | |
| 3021 InstructionMark im(this); | |
| 3022 emit_byte(0xDC); | |
| 3023 emit_operand32(rbx, src); | |
| 3024 } | |
| 3025 | |
| 3026 void Assembler::fcomp_s(Address src) { | |
| 3027 InstructionMark im(this); | |
| 3028 emit_byte(0xD8); | |
| 3029 emit_operand32(rbx, src); | |
| 3030 } | |
| 3031 | |
| 3032 void Assembler::fcompp() { | |
| 3033 emit_byte(0xDE); | |
| 3034 emit_byte(0xD9); | |
| 3035 } | |
| 3036 | |
| 3037 void Assembler::fcos() { | |
| 3038 emit_byte(0xD9); | |
| 0 | 3039 emit_byte(0xFF); |
| 304 | 3040 } |
| 3041 | |
| 3042 void Assembler::fdecstp() { | |
| 3043 emit_byte(0xD9); | |
| 3044 emit_byte(0xF6); | |
| 3045 } | |
| 3046 | |
| 3047 void Assembler::fdiv(int i) { | |
| 3048 emit_farith(0xD8, 0xF0, i); | |
| 3049 } | |
| 3050 | |
| 3051 void Assembler::fdiv_d(Address src) { | |
| 3052 InstructionMark im(this); | |
| 3053 emit_byte(0xDC); | |
| 3054 emit_operand32(rsi, src); | |
| 3055 } | |
| 3056 | |
| 3057 void Assembler::fdiv_s(Address src) { | |
| 3058 InstructionMark im(this); | |
| 3059 emit_byte(0xD8); | |
| 3060 emit_operand32(rsi, src); | |
| 3061 } | |
| 3062 | |
| 3063 void Assembler::fdiva(int i) { | |
| 3064 emit_farith(0xDC, 0xF8, i); | |
| 3065 } | |
| 3066 | |
| 3067 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3068 // is erroneous for some of the floating-point instructions below. | |
| 3069 | |
| 3070 void Assembler::fdivp(int i) { | |
| 3071 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3072 } | |
| 3073 | |
| 3074 void Assembler::fdivr(int i) { | |
| 3075 emit_farith(0xD8, 0xF8, i); | |
| 3076 } | |
| 3077 | |
| 3078 void Assembler::fdivr_d(Address src) { | |
| 3079 InstructionMark im(this); | |
| 3080 emit_byte(0xDC); | |
| 3081 emit_operand32(rdi, src); | |
| 3082 } | |
| 3083 | |
| 3084 void Assembler::fdivr_s(Address src) { | |
| 3085 InstructionMark im(this); | |
| 3086 emit_byte(0xD8); | |
| 3087 emit_operand32(rdi, src); | |
| 3088 } | |
| 3089 | |
| 3090 void Assembler::fdivra(int i) { | |
| 3091 emit_farith(0xDC, 0xF0, i); | |
| 3092 } | |
| 3093 | |
| 3094 void Assembler::fdivrp(int i) { | |
| 3095 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3096 } | |
| 3097 | |
| 3098 void Assembler::ffree(int i) { | |
| 3099 emit_farith(0xDD, 0xC0, i); | |
| 3100 } | |
| 3101 | |
| 3102 void Assembler::fild_d(Address adr) { | |
| 3103 InstructionMark im(this); | |
| 3104 emit_byte(0xDF); | |
| 3105 emit_operand32(rbp, adr); | |
| 3106 } | |
| 3107 | |
| 3108 void Assembler::fild_s(Address adr) { | |
| 3109 InstructionMark im(this); | |
| 3110 emit_byte(0xDB); | |
| 3111 emit_operand32(rax, adr); | |
| 3112 } | |
| 3113 | |
| 3114 void Assembler::fincstp() { | |
| 3115 emit_byte(0xD9); | |
| 3116 emit_byte(0xF7); | |
| 3117 } | |
| 3118 | |
| 3119 void Assembler::finit() { | |
| 3120 emit_byte(0x9B); | |
| 3121 emit_byte(0xDB); | |
| 3122 emit_byte(0xE3); | |
| 3123 } | |
| 3124 | |
| 3125 void Assembler::fist_s(Address adr) { | |
| 3126 InstructionMark im(this); | |
| 3127 emit_byte(0xDB); | |
| 3128 emit_operand32(rdx, adr); | |
| 3129 } | |
| 3130 | |
| 3131 void Assembler::fistp_d(Address adr) { | |
| 3132 InstructionMark im(this); | |
| 3133 emit_byte(0xDF); | |
| 3134 emit_operand32(rdi, adr); | |
| 3135 } | |
| 3136 | |
| 3137 void Assembler::fistp_s(Address adr) { | |
| 3138 InstructionMark im(this); | |
| 3139 emit_byte(0xDB); | |
| 3140 emit_operand32(rbx, adr); | |
| 3141 } | |
| 0 | 3142 |
| 3143 void Assembler::fld1() { | |
| 3144 emit_byte(0xD9); | |
| 3145 emit_byte(0xE8); | |
| 3146 } | |
| 3147 | |
| 304 | 3148 void Assembler::fld_d(Address adr) { |
| 3149 InstructionMark im(this); | |
| 3150 emit_byte(0xDD); | |
| 3151 emit_operand32(rax, adr); | |
| 3152 } | |
| 0 | 3153 |
| 3154 void Assembler::fld_s(Address adr) { | |
| 3155 InstructionMark im(this); | |
| 3156 emit_byte(0xD9); | |
| 304 | 3157 emit_operand32(rax, adr); |
| 3158 } | |
| 3159 | |
| 3160 | |
| 3161 void Assembler::fld_s(int index) { | |
| 0 | 3162 emit_farith(0xD9, 0xC0, index); |
| 3163 } | |
| 3164 | |
| 3165 void Assembler::fld_x(Address adr) { | |
| 3166 InstructionMark im(this); | |
| 3167 emit_byte(0xDB); | |
| 304 | 3168 emit_operand32(rbp, adr); |
| 3169 } | |
| 3170 | |
| 3171 void Assembler::fldcw(Address src) { | |
| 3172 InstructionMark im(this); | |
| 3173 emit_byte(0xd9); | |
| 3174 emit_operand32(rbp, src); | |
| 3175 } | |
| 3176 | |
| 3177 void Assembler::fldenv(Address src) { | |
| 0 | 3178 InstructionMark im(this); |
| 3179 emit_byte(0xD9); | |
| 304 | 3180 emit_operand32(rsp, src); |
| 3181 } | |
| 3182 | |
| 3183 void Assembler::fldlg2() { | |
| 0 | 3184 emit_byte(0xD9); |
| 304 | 3185 emit_byte(0xEC); |
| 3186 } | |
| 0 | 3187 |
| 3188 void Assembler::fldln2() { | |
| 3189 emit_byte(0xD9); | |
| 3190 emit_byte(0xED); | |
| 3191 } | |
| 3192 | |
| 304 | 3193 void Assembler::fldz() { |
| 0 | 3194 emit_byte(0xD9); |
| 304 | 3195 emit_byte(0xEE); |
| 3196 } | |
| 0 | 3197 |
| 3198 void Assembler::flog() { | |
| 3199 fldln2(); | |
| 3200 fxch(); | |
| 3201 fyl2x(); | |
| 3202 } | |
| 3203 | |
| 3204 void Assembler::flog10() { | |
| 3205 fldlg2(); | |
| 3206 fxch(); | |
| 3207 fyl2x(); | |
| 3208 } | |
| 3209 | |
| 304 | 3210 void Assembler::fmul(int i) { |
| 3211 emit_farith(0xD8, 0xC8, i); | |
| 3212 } | |
| 3213 | |
| 3214 void Assembler::fmul_d(Address src) { | |
| 3215 InstructionMark im(this); | |
| 3216 emit_byte(0xDC); | |
| 3217 emit_operand32(rcx, src); | |
| 3218 } | |
| 3219 | |
| 3220 void Assembler::fmul_s(Address src) { | |
| 3221 InstructionMark im(this); | |
| 3222 emit_byte(0xD8); | |
| 3223 emit_operand32(rcx, src); | |
| 3224 } | |
| 3225 | |
| 3226 void Assembler::fmula(int i) { | |
| 3227 emit_farith(0xDC, 0xC8, i); | |
| 3228 } | |
| 3229 | |
| 3230 void Assembler::fmulp(int i) { | |
| 3231 emit_farith(0xDE, 0xC8, i); | |
| 3232 } | |
| 3233 | |
| 3234 void Assembler::fnsave(Address dst) { | |
| 3235 InstructionMark im(this); | |
| 3236 emit_byte(0xDD); | |
| 3237 emit_operand32(rsi, dst); | |
| 3238 } | |
| 3239 | |
| 3240 void Assembler::fnstcw(Address src) { | |
| 3241 InstructionMark im(this); | |
| 3242 emit_byte(0x9B); | |
| 3243 emit_byte(0xD9); | |
| 3244 emit_operand32(rdi, src); | |
| 3245 } | |
| 3246 | |
| 3247 void Assembler::fnstsw_ax() { | |
| 3248 emit_byte(0xdF); | |
| 3249 emit_byte(0xE0); | |
| 3250 } | |
| 3251 | |
| 3252 void Assembler::fprem() { | |
| 3253 emit_byte(0xD9); | |
| 3254 emit_byte(0xF8); | |
| 3255 } | |
| 3256 | |
| 3257 void Assembler::fprem1() { | |
| 3258 emit_byte(0xD9); | |
| 3259 emit_byte(0xF5); | |
| 3260 } | |
| 3261 | |
| 3262 void Assembler::frstor(Address src) { | |
| 3263 InstructionMark im(this); | |
| 3264 emit_byte(0xDD); | |
| 3265 emit_operand32(rsp, src); | |
| 3266 } | |
| 0 | 3267 |
| 3268 void Assembler::fsin() { | |
| 3269 emit_byte(0xD9); | |
| 3270 emit_byte(0xFE); | |
| 3271 } | |
| 3272 | |
| 304 | 3273 void Assembler::fsqrt() { |
| 3274 emit_byte(0xD9); | |
| 3275 emit_byte(0xFA); | |
| 3276 } | |
| 3277 | |
| 3278 void Assembler::fst_d(Address adr) { | |
| 3279 InstructionMark im(this); | |
| 3280 emit_byte(0xDD); | |
| 3281 emit_operand32(rdx, adr); | |
| 3282 } | |
| 3283 | |
| 3284 void Assembler::fst_s(Address adr) { | |
| 3285 InstructionMark im(this); | |
| 3286 emit_byte(0xD9); | |
| 3287 emit_operand32(rdx, adr); | |
| 3288 } | |
| 3289 | |
| 3290 void Assembler::fstp_d(Address adr) { | |
| 3291 InstructionMark im(this); | |
| 3292 emit_byte(0xDD); | |
| 3293 emit_operand32(rbx, adr); | |
| 3294 } | |
| 3295 | |
| 3296 void Assembler::fstp_d(int index) { | |
| 3297 emit_farith(0xDD, 0xD8, index); | |
| 3298 } | |
| 3299 | |
| 3300 void Assembler::fstp_s(Address adr) { | |
| 3301 InstructionMark im(this); | |
| 0 | 3302 emit_byte(0xD9); |
| 304 | 3303 emit_operand32(rbx, adr); |
| 3304 } | |
| 3305 | |
| 3306 void Assembler::fstp_x(Address adr) { | |
| 3307 InstructionMark im(this); | |
| 3308 emit_byte(0xDB); | |
| 3309 emit_operand32(rdi, adr); | |
| 3310 } | |
| 3311 | |
| 3312 void Assembler::fsub(int i) { | |
| 3313 emit_farith(0xD8, 0xE0, i); | |
| 3314 } | |
| 3315 | |
| 3316 void Assembler::fsub_d(Address src) { | |
| 3317 InstructionMark im(this); | |
| 3318 emit_byte(0xDC); | |
| 3319 emit_operand32(rsp, src); | |
| 3320 } | |
| 3321 | |
| 3322 void Assembler::fsub_s(Address src) { | |
| 3323 InstructionMark im(this); | |
| 3324 emit_byte(0xD8); | |
| 3325 emit_operand32(rsp, src); | |
| 3326 } | |
| 3327 | |
| 3328 void Assembler::fsuba(int i) { | |
| 3329 emit_farith(0xDC, 0xE8, i); | |
| 3330 } | |
| 3331 | |
| 3332 void Assembler::fsubp(int i) { | |
| 3333 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 3334 } | |
| 3335 | |
| 3336 void Assembler::fsubr(int i) { | |
| 3337 emit_farith(0xD8, 0xE8, i); | |
| 3338 } | |
| 3339 | |
| 3340 void Assembler::fsubr_d(Address src) { | |
| 3341 InstructionMark im(this); | |
| 3342 emit_byte(0xDC); | |
| 3343 emit_operand32(rbp, src); | |
| 3344 } | |
| 3345 | |
| 3346 void Assembler::fsubr_s(Address src) { | |
| 3347 InstructionMark im(this); | |
| 3348 emit_byte(0xD8); | |
| 3349 emit_operand32(rbp, src); | |
| 3350 } | |
| 3351 | |
| 3352 void Assembler::fsubra(int i) { | |
| 3353 emit_farith(0xDC, 0xE0, i); | |
| 3354 } | |
| 3355 | |
| 3356 void Assembler::fsubrp(int i) { | |
| 3357 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 3358 } |
| 3359 | |
| 3360 void Assembler::ftan() { | |
| 3361 emit_byte(0xD9); | |
| 3362 emit_byte(0xF2); | |
| 3363 emit_byte(0xDD); | |
| 3364 emit_byte(0xD8); | |
| 3365 } | |
| 3366 | |
| 304 | 3367 void Assembler::ftst() { |
| 0 | 3368 emit_byte(0xD9); |
| 304 | 3369 emit_byte(0xE4); |
| 3370 } | |
| 0 | 3371 |
| 3372 void Assembler::fucomi(int i) { | |
| 3373 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3374 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3375 emit_farith(0xDB, 0xE8, i); | |
| 3376 } | |
| 3377 | |
| 3378 void Assembler::fucomip(int i) { | |
| 3379 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3380 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3381 emit_farith(0xDF, 0xE8, i); | |
| 3382 } | |
| 3383 | |
| 3384 void Assembler::fwait() { | |
| 3385 emit_byte(0x9B); | |
| 3386 } | |
| 3387 | |
| 304 | 3388 void Assembler::fxch(int i) { |
| 3389 emit_farith(0xD9, 0xC8, i); | |
| 3390 } | |
| 3391 | |
| 3392 void Assembler::fyl2x() { | |
| 0 | 3393 emit_byte(0xD9); |
| 304 | 3394 emit_byte(0xF1); |
| 3395 } | |
| 3396 | |
| 3397 | |
| 3398 #ifndef _LP64 | |
| 3399 | |
| 3400 void Assembler::incl(Register dst) { | |
| 3401 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3402 emit_byte(0x40 | dst->encoding()); | |
| 3403 } | |
| 3404 | |
| 3405 void Assembler::lea(Register dst, Address src) { | |
| 3406 leal(dst, src); | |
| 3407 } | |
| 3408 | |
| 3409 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 3410 InstructionMark im(this); | |
| 3411 emit_byte(0xC7); | |
| 3412 emit_operand(rax, dst); | |
| 3413 emit_data((int)imm32, rspec, 0); | |
| 3414 } | |
| 3415 | |
|
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3416 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
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3417 InstructionMark im(this); |
|
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3418 int encode = prefix_and_encode(dst->encoding()); |
|
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3419 emit_byte(0xB8 | encode); |
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3420 emit_data((int)imm32, rspec, 0); |
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|
3421 } |
| 304 | 3422 |
| 3423 void Assembler::popa() { // 32bit | |
| 3424 emit_byte(0x61); | |
| 3425 } | |
| 3426 | |
| 3427 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 3428 InstructionMark im(this); | |
| 3429 emit_byte(0x68); | |
| 3430 emit_data(imm32, rspec, 0); | |
| 3431 } | |
| 3432 | |
| 3433 void Assembler::pusha() { // 32bit | |
| 3434 emit_byte(0x60); | |
| 3435 } | |
| 3436 | |
| 3437 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 3438 emit_byte(0x0F); |
| 304 | 3439 emit_byte(0x95); |
| 3440 emit_byte(0xE0 | dst->encoding()); | |
| 3441 } | |
| 3442 | |
| 3443 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 3444 emit_byte(0x0F); |
| 304 | 3445 emit_byte(0xA5); |
| 3446 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3447 } | |
| 3448 | |
| 3449 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 3450 emit_byte(0x0F); |
| 304 | 3451 emit_byte(0xAD); |
| 3452 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3453 } | |
| 3454 | |
| 3455 #else // LP64 | |
| 3456 | |
| 1369 | 3457 void Assembler::set_byte_if_not_zero(Register dst) { |
| 3458 int enc = prefix_and_encode(dst->encoding(), true); | |
| 3459 emit_byte(0x0F); | |
| 3460 emit_byte(0x95); | |
| 3461 emit_byte(0xE0 | enc); | |
| 3462 } | |
| 3463 | |
| 304 | 3464 // 64bit only pieces of the assembler |
| 3465 // This should only be used by 64bit instructions that can use rip-relative | |
| 3466 // it cannot be used by instructions that want an immediate value. | |
| 3467 | |
| 3468 bool Assembler::reachable(AddressLiteral adr) { | |
| 3469 int64_t disp; | |
| 3470 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 3471 // for something that will be patched later and we need to certain it will | |
| 3472 // always be reachable. | |
| 3473 if (adr.reloc() == relocInfo::none) { | |
| 3474 return false; | |
| 3475 } | |
| 3476 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 3477 // This should be rip relative and easily reachable. | |
| 3478 return true; | |
| 3479 } | |
| 3480 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 3481 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 3482 adr.reloc() == relocInfo::static_call_type || | |
| 3483 adr.reloc() == relocInfo::static_stub_type ) { | |
| 3484 // This should be rip relative within the code cache and easily | |
| 3485 // reachable until we get huge code caches. (At which point | |
| 3486 // ic code is going to have issues). | |
| 3487 return true; | |
| 3488 } | |
| 3489 if (adr.reloc() != relocInfo::external_word_type && | |
| 3490 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 3491 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 3492 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 3493 return false; | |
| 3494 } | |
| 3495 | |
| 3496 // Stress the correction code | |
| 3497 if (ForceUnreachable) { | |
| 3498 // Must be runtimecall reloc, see if it is in the codecache | |
| 3499 // Flipping stuff in the codecache to be unreachable causes issues | |
| 3500 // with things like inline caches where the additional instructions | |
| 3501 // are not handled. | |
| 3502 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 3503 return false; | |
| 3504 } | |
| 3505 } | |
| 3506 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 3507 // are now (possibly a temp buffer) and where we might end up | |
| 3508 // anywhere in the codeCache then we are always reachable. | |
| 3509 // This would have to change if we ever save/restore shared code | |
| 3510 // to be more pessimistic. | |
| 3511 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 3512 if (!is_simm32(disp)) return false; | |
| 3513 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 3514 if (!is_simm32(disp)) return false; | |
| 3515 | |
| 3516 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 3517 | |
| 3518 // Because rip relative is a disp + address_of_next_instruction and we | |
| 3519 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 3520 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 3521 // We don't have to fudge the checks above here because they are already worst case. | |
| 3522 | |
| 3523 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 3524 // + 4 because better safe than sorry. | |
| 3525 const int fudge = 12 + 4; | |
| 3526 if (disp < 0) { | |
| 3527 disp -= fudge; | |
| 3528 } else { | |
| 3529 disp += fudge; | |
| 3530 } | |
| 3531 return is_simm32(disp); | |
| 3532 } | |
| 3533 | |
|
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3534 // Check if the polling page is not reachable from the code cache using rip-relative |
|
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3535 // addressing. |
|
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|
3536 bool Assembler::is_polling_page_far() { |
|
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|
3537 intptr_t addr = (intptr_t)os::get_polling_page(); |
|
4118
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3938
diff
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|
3538 return ForceUnreachable || |
|
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3938
diff
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|
3539 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
|
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3540 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
|
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|
3541 } |
|
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|
3542 |
| 304 | 3543 void Assembler::emit_data64(jlong data, |
| 3544 relocInfo::relocType rtype, | |
| 3545 int format) { | |
| 3546 if (rtype == relocInfo::none) { | |
| 3547 emit_long64(data); | |
| 3548 } else { | |
| 3549 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 3550 } | |
| 3551 } | |
| 3552 | |
| 3553 void Assembler::emit_data64(jlong data, | |
| 3554 RelocationHolder const& rspec, | |
| 3555 int format) { | |
| 3556 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 3557 assert(imm_operand == format, "must be immediate"); | |
| 3558 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 3559 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 3560 // embedded words. Instead, relocate to the enclosing instruction. | |
| 3561 code_section()->relocate(inst_mark(), rspec, format); | |
| 3562 #ifdef ASSERT | |
| 3563 check_relocation(rspec, format); | |
| 3564 #endif | |
| 3565 emit_long64(data); | |
| 3566 } | |
| 3567 | |
| 3568 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 3569 if (reg_enc >= 8) { | |
| 3570 prefix(REX_B); | |
| 3571 reg_enc -= 8; | |
| 3572 } else if (byteinst && reg_enc >= 4) { | |
| 3573 prefix(REX); | |
| 3574 } | |
| 3575 return reg_enc; | |
| 3576 } | |
| 3577 | |
| 3578 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 3579 if (reg_enc < 8) { | |
| 3580 prefix(REX_W); | |
| 3581 } else { | |
| 3582 prefix(REX_WB); | |
| 3583 reg_enc -= 8; | |
| 3584 } | |
| 3585 return reg_enc; | |
| 3586 } | |
| 3587 | |
| 3588 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 3589 if (dst_enc < 8) { | |
| 3590 if (src_enc >= 8) { | |
| 3591 prefix(REX_B); | |
| 3592 src_enc -= 8; | |
| 3593 } else if (byteinst && src_enc >= 4) { | |
| 3594 prefix(REX); | |
| 3595 } | |
| 3596 } else { | |
| 3597 if (src_enc < 8) { | |
| 3598 prefix(REX_R); | |
| 3599 } else { | |
| 3600 prefix(REX_RB); | |
| 3601 src_enc -= 8; | |
| 3602 } | |
| 3603 dst_enc -= 8; | |
| 3604 } | |
| 3605 return dst_enc << 3 | src_enc; | |
| 3606 } | |
| 3607 | |
| 3608 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 3609 if (dst_enc < 8) { | |
| 3610 if (src_enc < 8) { | |
| 3611 prefix(REX_W); | |
| 3612 } else { | |
| 3613 prefix(REX_WB); | |
| 3614 src_enc -= 8; | |
| 3615 } | |
| 3616 } else { | |
| 3617 if (src_enc < 8) { | |
| 3618 prefix(REX_WR); | |
| 3619 } else { | |
| 3620 prefix(REX_WRB); | |
| 3621 src_enc -= 8; | |
| 3622 } | |
| 3623 dst_enc -= 8; | |
| 3624 } | |
| 3625 return dst_enc << 3 | src_enc; | |
| 3626 } | |
| 3627 | |
| 3628 void Assembler::prefix(Register reg) { | |
| 3629 if (reg->encoding() >= 8) { | |
| 3630 prefix(REX_B); | |
| 3631 } | |
| 3632 } | |
| 3633 | |
| 3634 void Assembler::prefix(Address adr) { | |
| 3635 if (adr.base_needs_rex()) { | |
| 3636 if (adr.index_needs_rex()) { | |
| 3637 prefix(REX_XB); | |
| 3638 } else { | |
| 3639 prefix(REX_B); | |
| 3640 } | |
| 3641 } else { | |
| 3642 if (adr.index_needs_rex()) { | |
| 3643 prefix(REX_X); | |
| 3644 } | |
| 3645 } | |
| 3646 } | |
| 3647 | |
| 3648 void Assembler::prefixq(Address adr) { | |
| 3649 if (adr.base_needs_rex()) { | |
| 3650 if (adr.index_needs_rex()) { | |
| 3651 prefix(REX_WXB); | |
| 3652 } else { | |
| 3653 prefix(REX_WB); | |
| 3654 } | |
| 3655 } else { | |
| 3656 if (adr.index_needs_rex()) { | |
| 3657 prefix(REX_WX); | |
| 3658 } else { | |
| 3659 prefix(REX_W); | |
| 3660 } | |
| 3661 } | |
| 3662 } | |
| 3663 | |
| 3664 | |
| 3665 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 3666 if (reg->encoding() < 8) { | |
| 3667 if (adr.base_needs_rex()) { | |
| 3668 if (adr.index_needs_rex()) { | |
| 3669 prefix(REX_XB); | |
| 3670 } else { | |
| 3671 prefix(REX_B); | |
| 3672 } | |
| 3673 } else { | |
| 3674 if (adr.index_needs_rex()) { | |
| 3675 prefix(REX_X); | |
| 3855 | 3676 } else if (byteinst && reg->encoding() >= 4 ) { |
| 304 | 3677 prefix(REX); |
| 3678 } | |
| 3679 } | |
| 3680 } else { | |
| 3681 if (adr.base_needs_rex()) { | |
| 3682 if (adr.index_needs_rex()) { | |
| 3683 prefix(REX_RXB); | |
| 3684 } else { | |
| 3685 prefix(REX_RB); | |
| 3686 } | |
| 3687 } else { | |
| 3688 if (adr.index_needs_rex()) { | |
| 3689 prefix(REX_RX); | |
| 3690 } else { | |
| 3691 prefix(REX_R); | |
| 3692 } | |
| 3693 } | |
| 3694 } | |
| 3695 } | |
| 3696 | |
| 3697 void Assembler::prefixq(Address adr, Register src) { | |
| 3698 if (src->encoding() < 8) { | |
| 3699 if (adr.base_needs_rex()) { | |
| 3700 if (adr.index_needs_rex()) { | |
| 3701 prefix(REX_WXB); | |
| 3702 } else { | |
| 3703 prefix(REX_WB); | |
| 3704 } | |
| 3705 } else { | |
| 3706 if (adr.index_needs_rex()) { | |
| 3707 prefix(REX_WX); | |
| 3708 } else { | |
| 3709 prefix(REX_W); | |
| 3710 } | |
| 3711 } | |
| 3712 } else { | |
| 3713 if (adr.base_needs_rex()) { | |
| 3714 if (adr.index_needs_rex()) { | |
| 3715 prefix(REX_WRXB); | |
| 3716 } else { | |
| 3717 prefix(REX_WRB); | |
| 3718 } | |
| 3719 } else { | |
| 3720 if (adr.index_needs_rex()) { | |
| 3721 prefix(REX_WRX); | |
| 3722 } else { | |
| 3723 prefix(REX_WR); | |
| 3724 } | |
| 3725 } | |
| 3726 } | |
| 3727 } | |
| 3728 | |
| 3729 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 3730 if (reg->encoding() < 8) { | |
| 3731 if (adr.base_needs_rex()) { | |
| 3732 if (adr.index_needs_rex()) { | |
| 3733 prefix(REX_XB); | |
| 3734 } else { | |
| 3735 prefix(REX_B); | |
| 3736 } | |
| 3737 } else { | |
| 3738 if (adr.index_needs_rex()) { | |
| 3739 prefix(REX_X); | |
| 3740 } | |
| 3741 } | |
| 3742 } else { | |
| 3743 if (adr.base_needs_rex()) { | |
| 3744 if (adr.index_needs_rex()) { | |
| 3745 prefix(REX_RXB); | |
| 3746 } else { | |
| 3747 prefix(REX_RB); | |
| 3748 } | |
| 3749 } else { | |
| 3750 if (adr.index_needs_rex()) { | |
| 3751 prefix(REX_RX); | |
| 3752 } else { | |
| 3753 prefix(REX_R); | |
| 3754 } | |
| 3755 } | |
| 3756 } | |
| 3757 } | |
| 3758 | |
| 3759 void Assembler::adcq(Register dst, int32_t imm32) { | |
| 3760 (void) prefixq_and_encode(dst->encoding()); | |
| 3761 emit_arith(0x81, 0xD0, dst, imm32); | |
| 3762 } | |
| 3763 | |
| 3764 void Assembler::adcq(Register dst, Address src) { | |
| 3765 InstructionMark im(this); | |
| 3766 prefixq(src, dst); | |
| 3767 emit_byte(0x13); | |
| 3768 emit_operand(dst, src); | |
| 3769 } | |
| 3770 | |
| 3771 void Assembler::adcq(Register dst, Register src) { | |
| 3772 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3773 emit_arith(0x13, 0xC0, dst, src); | |
| 3774 } | |
| 3775 | |
| 3776 void Assembler::addq(Address dst, int32_t imm32) { | |
| 3777 InstructionMark im(this); | |
| 3778 prefixq(dst); | |
| 3779 emit_arith_operand(0x81, rax, dst,imm32); | |
| 3780 } | |
| 3781 | |
| 3782 void Assembler::addq(Address dst, Register src) { | |
| 3783 InstructionMark im(this); | |
| 3784 prefixq(dst, src); | |
| 3785 emit_byte(0x01); | |
| 3786 emit_operand(src, dst); | |
| 3787 } | |
| 3788 | |
| 3789 void Assembler::addq(Register dst, int32_t imm32) { | |
| 3790 (void) prefixq_and_encode(dst->encoding()); | |
| 3791 emit_arith(0x81, 0xC0, dst, imm32); | |
| 3792 } | |
| 3793 | |
| 3794 void Assembler::addq(Register dst, Address src) { | |
| 3795 InstructionMark im(this); | |
| 3796 prefixq(src, dst); | |
| 3797 emit_byte(0x03); | |
| 3798 emit_operand(dst, src); | |
| 3799 } | |
| 3800 | |
| 3801 void Assembler::addq(Register dst, Register src) { | |
| 3802 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3803 emit_arith(0x03, 0xC0, dst, src); | |
| 3804 } | |
| 3805 | |
| 3457 | 3806 void Assembler::andq(Address dst, int32_t imm32) { |
| 3807 InstructionMark im(this); | |
| 3808 prefixq(dst); | |
| 3809 emit_byte(0x81); | |
| 3810 emit_operand(rsp, dst, 4); | |
| 3811 emit_long(imm32); | |
| 3812 } | |
| 3813 | |
| 304 | 3814 void Assembler::andq(Register dst, int32_t imm32) { |
| 3815 (void) prefixq_and_encode(dst->encoding()); | |
| 3816 emit_arith(0x81, 0xE0, dst, imm32); | |
| 3817 } | |
| 3818 | |
| 3819 void Assembler::andq(Register dst, Address src) { | |
| 3820 InstructionMark im(this); | |
| 3821 prefixq(src, dst); | |
| 3822 emit_byte(0x23); | |
| 3823 emit_operand(dst, src); | |
| 3824 } | |
| 3825 | |
| 3826 void Assembler::andq(Register dst, Register src) { | |
| 3827 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3828 emit_arith(0x23, 0xC0, dst, src); | |
| 3829 } | |
| 3830 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3831 void Assembler::bsfq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3832 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3833 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3834 emit_byte(0xBC); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3835 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3836 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3837 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3838 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3839 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3840 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3841 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3842 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3843 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3844 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3845 |
| 304 | 3846 void Assembler::bswapq(Register reg) { |
| 3847 int encode = prefixq_and_encode(reg->encoding()); | |
| 3848 emit_byte(0x0F); | |
| 3849 emit_byte(0xC8 | encode); | |
| 3850 } | |
| 3851 | |
| 3852 void Assembler::cdqq() { | |
| 3853 prefix(REX_W); | |
| 3854 emit_byte(0x99); | |
| 3855 } | |
| 3856 | |
| 3857 void Assembler::clflush(Address adr) { | |
| 3858 prefix(adr); | |
| 3859 emit_byte(0x0F); | |
| 3860 emit_byte(0xAE); | |
| 3861 emit_operand(rdi, adr); | |
| 3862 } | |
| 3863 | |
| 3864 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 3865 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3866 emit_byte(0x0F); | |
| 3867 emit_byte(0x40 | cc); | |
| 3868 emit_byte(0xC0 | encode); | |
| 3869 } | |
| 3870 | |
| 3871 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 3872 InstructionMark im(this); | |
| 3873 prefixq(src, dst); | |
| 3874 emit_byte(0x0F); | |
| 3875 emit_byte(0x40 | cc); | |
| 3876 emit_operand(dst, src); | |
| 3877 } | |
| 3878 | |
| 3879 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 3880 InstructionMark im(this); | |
| 3881 prefixq(dst); | |
| 3882 emit_byte(0x81); | |
| 3883 emit_operand(rdi, dst, 4); | |
| 3884 emit_long(imm32); | |
| 3885 } | |
| 3886 | |
| 3887 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 3888 (void) prefixq_and_encode(dst->encoding()); | |
| 3889 emit_arith(0x81, 0xF8, dst, imm32); | |
| 3890 } | |
| 3891 | |
| 3892 void Assembler::cmpq(Address dst, Register src) { | |
| 3893 InstructionMark im(this); | |
| 3894 prefixq(dst, src); | |
| 3895 emit_byte(0x3B); | |
| 3896 emit_operand(src, dst); | |
| 3897 } | |
| 3898 | |
| 3899 void Assembler::cmpq(Register dst, Register src) { | |
| 3900 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3901 emit_arith(0x3B, 0xC0, dst, src); | |
| 3902 } | |
| 3903 | |
| 3904 void Assembler::cmpq(Register dst, Address src) { | |
| 3905 InstructionMark im(this); | |
| 3906 prefixq(src, dst); | |
| 3907 emit_byte(0x3B); | |
| 3908 emit_operand(dst, src); | |
| 3909 } | |
| 3910 | |
| 3911 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 3912 InstructionMark im(this); | |
| 3913 prefixq(adr, reg); | |
| 3914 emit_byte(0x0F); | |
| 3915 emit_byte(0xB1); | |
| 3916 emit_operand(reg, adr); | |
| 3917 } | |
| 3918 | |
| 3919 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 3920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3921 emit_byte(0xF2); | |
| 3922 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3923 emit_byte(0x0F); | |
| 3924 emit_byte(0x2A); | |
| 3925 emit_byte(0xC0 | encode); | |
| 3926 } | |
| 3927 | |
| 3928 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
| 3929 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3930 emit_byte(0xF3); | |
| 3931 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3932 emit_byte(0x0F); | |
| 3933 emit_byte(0x2A); | |
| 3934 emit_byte(0xC0 | encode); | |
| 3935 } | |
| 3936 | |
| 3937 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
| 3938 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3939 emit_byte(0xF2); | |
| 3940 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3941 emit_byte(0x0F); | |
| 3942 emit_byte(0x2C); | |
| 3943 emit_byte(0xC0 | encode); | |
| 3944 } | |
| 3945 | |
| 3946 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 3947 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3948 emit_byte(0xF3); | |
| 3949 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3950 emit_byte(0x0F); | |
| 3951 emit_byte(0x2C); | |
| 3952 emit_byte(0xC0 | encode); | |
| 3953 } | |
| 3954 | |
| 3955 void Assembler::decl(Register dst) { | |
| 3956 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 3957 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 3958 int encode = prefix_and_encode(dst->encoding()); | |
| 3959 emit_byte(0xFF); | |
| 3960 emit_byte(0xC8 | encode); | |
| 3961 } | |
| 3962 | |
| 3963 void Assembler::decq(Register dst) { | |
| 3964 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3965 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3966 int encode = prefixq_and_encode(dst->encoding()); | |
| 3967 emit_byte(0xFF); | |
| 3968 emit_byte(0xC8 | encode); | |
| 3969 } | |
| 3970 | |
| 3971 void Assembler::decq(Address dst) { | |
| 3972 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3973 InstructionMark im(this); | |
| 3974 prefixq(dst); | |
| 3975 emit_byte(0xFF); | |
| 3976 emit_operand(rcx, dst); | |
| 3977 } | |
| 3978 | |
| 3979 void Assembler::fxrstor(Address src) { | |
| 3980 prefixq(src); | |
| 3981 emit_byte(0x0F); | |
| 3982 emit_byte(0xAE); | |
| 3983 emit_operand(as_Register(1), src); | |
| 3984 } | |
| 3985 | |
| 3986 void Assembler::fxsave(Address dst) { | |
| 3987 prefixq(dst); | |
| 3988 emit_byte(0x0F); | |
| 3989 emit_byte(0xAE); | |
| 3990 emit_operand(as_Register(0), dst); | |
| 3991 } | |
| 3992 | |
| 3993 void Assembler::idivq(Register src) { | |
| 3994 int encode = prefixq_and_encode(src->encoding()); | |
| 3995 emit_byte(0xF7); | |
| 3996 emit_byte(0xF8 | encode); | |
| 3997 } | |
| 3998 | |
| 3999 void Assembler::imulq(Register dst, Register src) { | |
| 4000 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4001 emit_byte(0x0F); | |
| 4002 emit_byte(0xAF); | |
| 4003 emit_byte(0xC0 | encode); | |
| 4004 } | |
| 4005 | |
| 4006 void Assembler::imulq(Register dst, Register src, int value) { | |
| 4007 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4008 if (is8bit(value)) { | |
| 4009 emit_byte(0x6B); | |
| 4010 emit_byte(0xC0 | encode); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1846
diff
changeset
|
4011 emit_byte(value & 0xFF); |
| 304 | 4012 } else { |
| 4013 emit_byte(0x69); | |
| 4014 emit_byte(0xC0 | encode); | |
| 4015 emit_long(value); | |
| 4016 } | |
| 4017 } | |
| 4018 | |
| 4019 void Assembler::incl(Register dst) { | |
| 4020 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4021 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4022 int encode = prefix_and_encode(dst->encoding()); | |
| 4023 emit_byte(0xFF); | |
| 4024 emit_byte(0xC0 | encode); | |
| 4025 } | |
| 4026 | |
| 4027 void Assembler::incq(Register dst) { | |
| 4028 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4029 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4030 int encode = prefixq_and_encode(dst->encoding()); | |
| 4031 emit_byte(0xFF); | |
| 4032 emit_byte(0xC0 | encode); | |
| 4033 } | |
| 4034 | |
| 4035 void Assembler::incq(Address dst) { | |
| 4036 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4037 InstructionMark im(this); | |
| 4038 prefixq(dst); | |
| 4039 emit_byte(0xFF); | |
| 4040 emit_operand(rax, dst); | |
| 4041 } | |
| 4042 | |
| 4043 void Assembler::lea(Register dst, Address src) { | |
| 4044 leaq(dst, src); | |
| 4045 } | |
| 4046 | |
| 4047 void Assembler::leaq(Register dst, Address src) { | |
| 4048 InstructionMark im(this); | |
| 4049 prefixq(src, dst); | |
| 4050 emit_byte(0x8D); | |
| 4051 emit_operand(dst, src); | |
| 4052 } | |
| 4053 | |
| 4054 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4055 InstructionMark im(this); | |
| 4056 int encode = prefixq_and_encode(dst->encoding()); | |
| 4057 emit_byte(0xB8 | encode); | |
| 4058 emit_long64(imm64); | |
| 4059 } | |
| 4060 | |
| 4061 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4062 InstructionMark im(this); | |
| 4063 int encode = prefixq_and_encode(dst->encoding()); | |
| 4064 emit_byte(0xB8 | encode); | |
| 4065 emit_data64(imm64, rspec); | |
| 4066 } | |
| 4067 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4068 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4069 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4070 int encode = prefix_and_encode(dst->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4071 emit_byte(0xB8 | encode); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4072 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4073 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4074 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4075 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4076 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4077 prefix(dst); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4078 emit_byte(0xC7); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4079 emit_operand(rax, dst, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4080 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4081 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4082 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4083 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4084 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4085 int encode = prefix_and_encode(src1->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4086 emit_byte(0x81); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4087 emit_byte(0xF8 | encode); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4088 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4089 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4090 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4091 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4092 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4093 prefix(src1); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4094 emit_byte(0x81); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4095 emit_operand(rax, src1, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4096 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4097 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4098 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4099 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4100 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4101 emit_byte(0xF3); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4102 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4103 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4104 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4105 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4106 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4107 |
| 304 | 4108 void Assembler::movdq(XMMRegister dst, Register src) { |
| 4109 // table D-1 says MMX/SSE2 | |
| 4110 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 4111 emit_byte(0x66); |
| 304 | 4112 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
| 0 | 4113 emit_byte(0x0F); |
| 304 | 4114 emit_byte(0x6E); |
| 4115 emit_byte(0xC0 | encode); | |
| 4116 } | |
| 4117 | |
| 4118 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 4119 // table D-1 says MMX/SSE2 | |
| 4120 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 4121 emit_byte(0x66); |
| 304 | 4122 // swap src/dst to get correct prefix |
| 4123 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
| 0 | 4124 emit_byte(0x0F); |
| 4125 emit_byte(0x7E); | |
| 304 | 4126 emit_byte(0xC0 | encode); |
| 4127 } | |
| 4128 | |
| 4129 void Assembler::movq(Register dst, Register src) { | |
| 4130 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4131 emit_byte(0x8B); | |
| 4132 emit_byte(0xC0 | encode); | |
| 4133 } | |
| 4134 | |
| 4135 void Assembler::movq(Register dst, Address src) { | |
| 4136 InstructionMark im(this); | |
| 4137 prefixq(src, dst); | |
| 4138 emit_byte(0x8B); | |
| 4139 emit_operand(dst, src); | |
| 4140 } | |
| 4141 | |
| 4142 void Assembler::movq(Address dst, Register src) { | |
| 4143 InstructionMark im(this); | |
| 4144 prefixq(dst, src); | |
| 4145 emit_byte(0x89); | |
| 4146 emit_operand(src, dst); | |
| 4147 } | |
| 4148 | |
| 624 | 4149 void Assembler::movsbq(Register dst, Address src) { |
| 4150 InstructionMark im(this); | |
| 4151 prefixq(src, dst); | |
| 4152 emit_byte(0x0F); | |
| 4153 emit_byte(0xBE); | |
| 4154 emit_operand(dst, src); | |
| 4155 } | |
| 4156 | |
| 4157 void Assembler::movsbq(Register dst, Register src) { | |
| 4158 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4159 emit_byte(0x0F); | |
| 4160 emit_byte(0xBE); | |
| 4161 emit_byte(0xC0 | encode); | |
| 4162 } | |
| 4163 | |
| 304 | 4164 void Assembler::movslq(Register dst, int32_t imm32) { |
| 4165 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 4166 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 4167 // as a result we shouldn't use until tested at runtime... | |
| 4168 ShouldNotReachHere(); | |
| 4169 InstructionMark im(this); | |
| 4170 int encode = prefixq_and_encode(dst->encoding()); | |
| 4171 emit_byte(0xC7 | encode); | |
| 4172 emit_long(imm32); | |
| 4173 } | |
| 4174 | |
| 4175 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 4176 assert(is_simm32(imm32), "lost bits"); | |
| 4177 InstructionMark im(this); | |
| 4178 prefixq(dst); | |
| 4179 emit_byte(0xC7); | |
| 4180 emit_operand(rax, dst, 4); | |
| 4181 emit_long(imm32); | |
| 4182 } | |
| 4183 | |
| 4184 void Assembler::movslq(Register dst, Address src) { | |
| 4185 InstructionMark im(this); | |
| 4186 prefixq(src, dst); | |
| 4187 emit_byte(0x63); | |
| 4188 emit_operand(dst, src); | |
| 4189 } | |
| 4190 | |
| 4191 void Assembler::movslq(Register dst, Register src) { | |
| 4192 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4193 emit_byte(0x63); | |
| 4194 emit_byte(0xC0 | encode); | |
| 4195 } | |
| 4196 | |
| 624 | 4197 void Assembler::movswq(Register dst, Address src) { |
| 4198 InstructionMark im(this); | |
| 4199 prefixq(src, dst); | |
| 4200 emit_byte(0x0F); | |
| 4201 emit_byte(0xBF); | |
| 4202 emit_operand(dst, src); | |
| 4203 } | |
| 4204 | |
| 4205 void Assembler::movswq(Register dst, Register src) { | |
| 4206 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4207 emit_byte(0x0F); | |
| 4208 emit_byte(0xBF); | |
| 4209 emit_byte(0xC0 | encode); | |
| 4210 } | |
| 4211 | |
| 4212 void Assembler::movzbq(Register dst, Address src) { | |
| 4213 InstructionMark im(this); | |
| 4214 prefixq(src, dst); | |
| 4215 emit_byte(0x0F); | |
| 4216 emit_byte(0xB6); | |
| 4217 emit_operand(dst, src); | |
| 4218 } | |
| 4219 | |
| 4220 void Assembler::movzbq(Register dst, Register src) { | |
| 4221 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4222 emit_byte(0x0F); | |
| 4223 emit_byte(0xB6); | |
| 4224 emit_byte(0xC0 | encode); | |
| 4225 } | |
| 4226 | |
| 4227 void Assembler::movzwq(Register dst, Address src) { | |
| 4228 InstructionMark im(this); | |
| 4229 prefixq(src, dst); | |
| 4230 emit_byte(0x0F); | |
| 4231 emit_byte(0xB7); | |
| 4232 emit_operand(dst, src); | |
| 4233 } | |
| 4234 | |
| 4235 void Assembler::movzwq(Register dst, Register src) { | |
| 4236 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4237 emit_byte(0x0F); | |
| 4238 emit_byte(0xB7); | |
| 4239 emit_byte(0xC0 | encode); | |
| 4240 } | |
| 4241 | |
| 304 | 4242 void Assembler::negq(Register dst) { |
| 4243 int encode = prefixq_and_encode(dst->encoding()); | |
| 4244 emit_byte(0xF7); | |
| 4245 emit_byte(0xD8 | encode); | |
| 4246 } | |
| 4247 | |
| 4248 void Assembler::notq(Register dst) { | |
| 4249 int encode = prefixq_and_encode(dst->encoding()); | |
| 4250 emit_byte(0xF7); | |
| 4251 emit_byte(0xD0 | encode); | |
| 4252 } | |
| 4253 | |
| 4254 void Assembler::orq(Address dst, int32_t imm32) { | |
| 4255 InstructionMark im(this); | |
| 4256 prefixq(dst); | |
| 4257 emit_byte(0x81); | |
| 4258 emit_operand(rcx, dst, 4); | |
| 4259 emit_long(imm32); | |
| 4260 } | |
| 4261 | |
| 4262 void Assembler::orq(Register dst, int32_t imm32) { | |
| 4263 (void) prefixq_and_encode(dst->encoding()); | |
| 4264 emit_arith(0x81, 0xC8, dst, imm32); | |
| 4265 } | |
| 4266 | |
| 4267 void Assembler::orq(Register dst, Address src) { | |
| 4268 InstructionMark im(this); | |
| 4269 prefixq(src, dst); | |
| 4270 emit_byte(0x0B); | |
| 4271 emit_operand(dst, src); | |
| 4272 } | |
| 4273 | |
| 4274 void Assembler::orq(Register dst, Register src) { | |
| 4275 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4276 emit_arith(0x0B, 0xC0, dst, src); | |
| 4277 } | |
| 4278 | |
| 4279 void Assembler::popa() { // 64bit | |
| 4280 movq(r15, Address(rsp, 0)); | |
| 4281 movq(r14, Address(rsp, wordSize)); | |
| 4282 movq(r13, Address(rsp, 2 * wordSize)); | |
| 4283 movq(r12, Address(rsp, 3 * wordSize)); | |
| 4284 movq(r11, Address(rsp, 4 * wordSize)); | |
| 4285 movq(r10, Address(rsp, 5 * wordSize)); | |
| 4286 movq(r9, Address(rsp, 6 * wordSize)); | |
| 4287 movq(r8, Address(rsp, 7 * wordSize)); | |
| 4288 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 4289 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 4290 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 4291 // skip rsp | |
| 4292 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 4293 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 4294 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 4295 movq(rax, Address(rsp, 15 * wordSize)); | |
| 4296 | |
| 4297 addq(rsp, 16 * wordSize); | |
| 4298 } | |
| 4299 | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4300 void Assembler::popcntq(Register dst, Address src) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4301 assert(VM_Version::supports_popcnt(), "must support"); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
642
diff
changeset
|
4302 InstructionMark im(this); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
642
diff
changeset
|
4303 emit_byte(0xF3); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4304 prefixq(src, dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4305 emit_byte(0x0F); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4306 emit_byte(0xB8); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4307 emit_operand(dst, src); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
642
diff
changeset
|
4308 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4309 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4310 void Assembler::popcntq(Register dst, Register src) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4311 assert(VM_Version::supports_popcnt(), "must support"); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4312 emit_byte(0xF3); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4313 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4314 emit_byte(0x0F); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4315 emit_byte(0xB8); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4316 emit_byte(0xC0 | encode); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
642
diff
changeset
|
4317 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4318 |
| 304 | 4319 void Assembler::popq(Address dst) { |
| 4320 InstructionMark im(this); | |
| 4321 prefixq(dst); | |
| 4322 emit_byte(0x8F); | |
| 4323 emit_operand(rax, dst); | |
| 4324 } | |
| 4325 | |
| 4326 void Assembler::pusha() { // 64bit | |
| 4327 // we have to store original rsp. ABI says that 128 bytes | |
| 4328 // below rsp are local scratch. | |
| 4329 movq(Address(rsp, -5 * wordSize), rsp); | |
| 4330 | |
| 4331 subq(rsp, 16 * wordSize); | |
| 4332 | |
| 4333 movq(Address(rsp, 15 * wordSize), rax); | |
| 4334 movq(Address(rsp, 14 * wordSize), rcx); | |
| 4335 movq(Address(rsp, 13 * wordSize), rdx); | |
| 4336 movq(Address(rsp, 12 * wordSize), rbx); | |
| 4337 // skip rsp | |
| 4338 movq(Address(rsp, 10 * wordSize), rbp); | |
| 4339 movq(Address(rsp, 9 * wordSize), rsi); | |
| 4340 movq(Address(rsp, 8 * wordSize), rdi); | |
| 4341 movq(Address(rsp, 7 * wordSize), r8); | |
| 4342 movq(Address(rsp, 6 * wordSize), r9); | |
| 4343 movq(Address(rsp, 5 * wordSize), r10); | |
| 4344 movq(Address(rsp, 4 * wordSize), r11); | |
| 4345 movq(Address(rsp, 3 * wordSize), r12); | |
| 4346 movq(Address(rsp, 2 * wordSize), r13); | |
| 4347 movq(Address(rsp, wordSize), r14); | |
| 4348 movq(Address(rsp, 0), r15); | |
| 4349 } | |
| 4350 | |
| 4351 void Assembler::pushq(Address src) { | |
| 4352 InstructionMark im(this); | |
| 4353 prefixq(src); | |
| 4354 emit_byte(0xFF); | |
| 4355 emit_operand(rsi, src); | |
| 4356 } | |
| 4357 | |
| 4358 void Assembler::rclq(Register dst, int imm8) { | |
| 4359 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4360 int encode = prefixq_and_encode(dst->encoding()); | |
| 4361 if (imm8 == 1) { | |
| 4362 emit_byte(0xD1); | |
| 4363 emit_byte(0xD0 | encode); | |
| 4364 } else { | |
| 4365 emit_byte(0xC1); | |
| 4366 emit_byte(0xD0 | encode); | |
| 4367 emit_byte(imm8); | |
| 4368 } | |
| 4369 } | |
| 4370 void Assembler::sarq(Register dst, int imm8) { | |
| 4371 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4372 int encode = prefixq_and_encode(dst->encoding()); | |
| 4373 if (imm8 == 1) { | |
| 4374 emit_byte(0xD1); | |
| 4375 emit_byte(0xF8 | encode); | |
| 4376 } else { | |
| 4377 emit_byte(0xC1); | |
| 4378 emit_byte(0xF8 | encode); | |
| 4379 emit_byte(imm8); | |
| 4380 } | |
| 4381 } | |
| 4382 | |
| 4383 void Assembler::sarq(Register dst) { | |
| 4384 int encode = prefixq_and_encode(dst->encoding()); | |
| 4385 emit_byte(0xD3); | |
| 4386 emit_byte(0xF8 | encode); | |
| 4387 } | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
4388 |
| 304 | 4389 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 4390 InstructionMark im(this); | |
| 4391 prefixq(dst); | |
| 4392 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 4393 } | |
| 4394 | |
| 4395 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 4396 (void) prefixq_and_encode(dst->encoding()); | |
| 4397 emit_arith(0x81, 0xD8, dst, imm32); | |
| 4398 } | |
| 4399 | |
| 4400 void Assembler::sbbq(Register dst, Address src) { | |
| 4401 InstructionMark im(this); | |
| 4402 prefixq(src, dst); | |
| 4403 emit_byte(0x1B); | |
| 4404 emit_operand(dst, src); | |
| 4405 } | |
| 4406 | |
| 4407 void Assembler::sbbq(Register dst, Register src) { | |
| 4408 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4409 emit_arith(0x1B, 0xC0, dst, src); | |
| 4410 } | |
| 4411 | |
| 4412 void Assembler::shlq(Register dst, int imm8) { | |
| 4413 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4414 int encode = prefixq_and_encode(dst->encoding()); | |
| 4415 if (imm8 == 1) { | |
| 4416 emit_byte(0xD1); | |
| 4417 emit_byte(0xE0 | encode); | |
| 4418 } else { | |
| 4419 emit_byte(0xC1); | |
| 4420 emit_byte(0xE0 | encode); | |
| 4421 emit_byte(imm8); | |
| 4422 } | |
| 4423 } | |
| 4424 | |
| 4425 void Assembler::shlq(Register dst) { | |
| 4426 int encode = prefixq_and_encode(dst->encoding()); | |
| 4427 emit_byte(0xD3); | |
| 4428 emit_byte(0xE0 | encode); | |
| 4429 } | |
| 4430 | |
| 4431 void Assembler::shrq(Register dst, int imm8) { | |
| 4432 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4433 int encode = prefixq_and_encode(dst->encoding()); | |
| 4434 emit_byte(0xC1); | |
| 4435 emit_byte(0xE8 | encode); | |
| 4436 emit_byte(imm8); | |
| 4437 } | |
| 4438 | |
| 4439 void Assembler::shrq(Register dst) { | |
| 4440 int encode = prefixq_and_encode(dst->encoding()); | |
| 4441 emit_byte(0xD3); | |
| 4442 emit_byte(0xE8 | encode); | |
| 4443 } | |
| 4444 | |
| 4445 void Assembler::subq(Address dst, int32_t imm32) { | |
| 4446 InstructionMark im(this); | |
| 4447 prefixq(dst); | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
4448 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 4449 } |
| 4450 | |
| 4451 void Assembler::subq(Address dst, Register src) { | |
| 4452 InstructionMark im(this); | |
| 4453 prefixq(dst, src); | |
| 4454 emit_byte(0x29); | |
| 4455 emit_operand(src, dst); | |
| 4456 } | |
| 4457 | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
4458 void Assembler::subq(Register dst, int32_t imm32) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
4459 (void) prefixq_and_encode(dst->encoding()); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
4460 emit_arith(0x81, 0xE8, dst, imm32); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
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diff
changeset
|
4461 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
4462 |
| 304 | 4463 void Assembler::subq(Register dst, Address src) { |
| 4464 InstructionMark im(this); | |
| 4465 prefixq(src, dst); | |
| 4466 emit_byte(0x2B); | |
| 4467 emit_operand(dst, src); | |
| 4468 } | |
| 4469 | |
| 4470 void Assembler::subq(Register dst, Register src) { | |
| 4471 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4472 emit_arith(0x2B, 0xC0, dst, src); | |
| 4473 } | |
| 4474 | |
| 4475 void Assembler::testq(Register dst, int32_t imm32) { | |
| 4476 // not using emit_arith because test | |
| 4477 // doesn't support sign-extension of | |
| 4478 // 8bit operands | |
| 4479 int encode = dst->encoding(); | |
| 4480 if (encode == 0) { | |
| 4481 prefix(REX_W); | |
| 4482 emit_byte(0xA9); | |
| 4483 } else { | |
| 4484 encode = prefixq_and_encode(encode); | |
| 4485 emit_byte(0xF7); | |
| 4486 emit_byte(0xC0 | encode); | |
| 4487 } | |
| 4488 emit_long(imm32); | |
| 4489 } | |
| 4490 | |
| 4491 void Assembler::testq(Register dst, Register src) { | |
| 4492 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4493 emit_arith(0x85, 0xC0, dst, src); | |
| 4494 } | |
| 4495 | |
| 4496 void Assembler::xaddq(Address dst, Register src) { | |
| 4497 InstructionMark im(this); | |
| 4498 prefixq(dst, src); | |
| 71 | 4499 emit_byte(0x0F); |
| 304 | 4500 emit_byte(0xC1); |
| 4501 emit_operand(src, dst); | |
| 4502 } | |
| 4503 | |
| 4504 void Assembler::xchgq(Register dst, Address src) { | |
| 4505 InstructionMark im(this); | |
| 4506 prefixq(src, dst); | |
| 4507 emit_byte(0x87); | |
| 4508 emit_operand(dst, src); | |
| 4509 } | |
| 4510 | |
| 4511 void Assembler::xchgq(Register dst, Register src) { | |
| 4512 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4513 emit_byte(0x87); | |
| 4514 emit_byte(0xc0 | encode); | |
| 4515 } | |
| 4516 | |
| 4517 void Assembler::xorq(Register dst, Register src) { | |
| 4518 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4519 emit_arith(0x33, 0xC0, dst, src); | |
| 4520 } | |
| 4521 | |
| 4522 void Assembler::xorq(Register dst, Address src) { | |
| 4523 InstructionMark im(this); | |
| 4524 prefixq(src, dst); | |
| 4525 emit_byte(0x33); | |
| 4526 emit_operand(dst, src); | |
| 4527 } | |
| 4528 | |
| 4529 #endif // !LP64 | |
| 4530 | |
| 4531 static Assembler::Condition reverse[] = { | |
| 4532 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 4533 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 4534 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 4535 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 4536 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 4537 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 4538 Assembler::above /* belowEqual = 0x6 */ , | |
| 4539 Assembler::belowEqual /* above = 0x7 */ , | |
| 4540 Assembler::positive /* negative = 0x8 */ , | |
| 4541 Assembler::negative /* positive = 0x9 */ , | |
| 4542 Assembler::noParity /* parity = 0xa */ , | |
| 4543 Assembler::parity /* noParity = 0xb */ , | |
| 4544 Assembler::greaterEqual /* less = 0xc */ , | |
| 4545 Assembler::less /* greaterEqual = 0xd */ , | |
| 4546 Assembler::greater /* lessEqual = 0xe */ , | |
| 4547 Assembler::lessEqual /* greater = 0xf, */ | |
| 4548 | |
| 4549 }; | |
| 4550 | |
| 0 | 4551 |
| 4552 // Implementation of MacroAssembler | |
| 4553 | |
| 304 | 4554 // First all the versions that have distinct versions depending on 32/64 bit |
| 4555 // Unless the difference is trivial (1 line or so). | |
| 4556 | |
| 4557 #ifndef _LP64 | |
| 4558 | |
| 4559 // 32bit versions | |
| 4560 | |
| 0 | 4561 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 4562 return Address(adr.target(), adr.rspec()); | |
| 4563 } | |
| 4564 | |
| 4565 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4566 return Address::make_array(adr); | |
| 4567 } | |
| 4568 | |
| 304 | 4569 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 4570 Register obj_reg, | |
| 4571 Register swap_reg, | |
| 4572 Register tmp_reg, | |
| 4573 bool swap_reg_contains_mark, | |
| 4574 Label& done, | |
| 4575 Label* slow_case, | |
| 4576 BiasedLockingCounters* counters) { | |
| 4577 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4578 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 4579 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 4580 | |
| 4581 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 4582 counters = BiasedLocking::counters(); | |
| 4583 | |
| 4584 bool need_tmp_reg = false; | |
| 4585 if (tmp_reg == noreg) { | |
| 4586 need_tmp_reg = true; | |
| 4587 tmp_reg = lock_reg; | |
| 4588 } else { | |
| 4589 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 4590 } | |
| 4591 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 4592 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 4593 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 4594 Address saved_mark_addr(lock_reg, 0); | |
| 4595 | |
| 4596 // Biased locking | |
| 4597 // See whether the lock is currently biased toward our thread and | |
| 4598 // whether the epoch is still valid | |
| 4599 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 4600 // pointers to allow age to be placed into low bits | |
| 4601 // First check to see whether biasing is even enabled for this object | |
| 4602 Label cas_label; | |
| 4603 int null_check_offset = -1; | |
| 4604 if (!swap_reg_contains_mark) { | |
| 4605 null_check_offset = offset(); | |
| 4606 movl(swap_reg, mark_addr); | |
| 4607 } | |
| 4608 if (need_tmp_reg) { | |
| 4609 push(tmp_reg); | |
| 4610 } | |
| 4611 movl(tmp_reg, swap_reg); | |
| 4612 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4613 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 4614 if (need_tmp_reg) { | |
| 4615 pop(tmp_reg); | |
| 4616 } | |
| 4617 jcc(Assembler::notEqual, cas_label); | |
| 4618 // The bias pattern is present in the object's header. Need to check | |
| 4619 // whether the bias owner and the epoch are both still current. | |
| 4620 // Note that because there is no current thread register on x86 we | |
| 4621 // need to store off the mark word we read out of the object to | |
| 4622 // avoid reloading it and needing to recheck invariants below. This | |
| 4623 // store is unfortunate but it makes the overall code shorter and | |
| 4624 // simpler. | |
| 4625 movl(saved_mark_addr, swap_reg); | |
| 4626 if (need_tmp_reg) { | |
| 4627 push(tmp_reg); | |
| 4628 } | |
| 4629 get_thread(tmp_reg); | |
| 4630 xorl(swap_reg, tmp_reg); | |
| 4631 if (swap_reg_contains_mark) { | |
| 4632 null_check_offset = offset(); | |
| 4633 } | |
| 4634 movl(tmp_reg, klass_addr); | |
| 4635 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4636 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 4637 if (need_tmp_reg) { | |
| 4638 pop(tmp_reg); | |
| 4639 } | |
| 4640 if (counters != NULL) { | |
| 4641 cond_inc32(Assembler::zero, | |
| 4642 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 4643 } | |
| 4644 jcc(Assembler::equal, done); | |
| 4645 | |
| 4646 Label try_revoke_bias; | |
| 4647 Label try_rebias; | |
| 4648 | |
| 4649 // At this point we know that the header has the bias pattern and | |
| 4650 // that we are not the bias owner in the current epoch. We need to | |
| 4651 // figure out more details about the state of the header in order to | |
| 4652 // know what operations can be legally performed on the object's | |
| 4653 // header. | |
| 4654 | |
| 4655 // If the low three bits in the xor result aren't clear, that means | |
| 4656 // the prototype header is no longer biased and we have to revoke | |
| 4657 // the bias on this object. | |
| 4658 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4659 jcc(Assembler::notZero, try_revoke_bias); | |
| 4660 | |
| 4661 // Biasing is still enabled for this data type. See whether the | |
| 4662 // epoch of the current bias is still valid, meaning that the epoch | |
| 4663 // bits of the mark word are equal to the epoch bits of the | |
| 4664 // prototype header. (Note that the prototype header's epoch bits | |
| 4665 // only change at a safepoint.) If not, attempt to rebias the object | |
| 4666 // toward the current thread. Note that we must be absolutely sure | |
| 4667 // that the current epoch is invalid in order to do this because | |
| 4668 // otherwise the manipulations it performs on the mark word are | |
| 4669 // illegal. | |
| 4670 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 4671 jcc(Assembler::notZero, try_rebias); | |
| 4672 | |
| 4673 // The epoch of the current bias is still valid but we know nothing | |
| 4674 // about the owner; it might be set or it might be clear. Try to | |
| 4675 // acquire the bias of the object using an atomic operation. If this | |
| 4676 // fails we will go in to the runtime to revoke the object's bias. | |
| 4677 // Note that we first construct the presumed unbiased header so we | |
| 4678 // don't accidentally blow away another thread's valid bias. | |
| 4679 movl(swap_reg, saved_mark_addr); | |
| 4680 andl(swap_reg, | |
| 4681 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 4682 if (need_tmp_reg) { | |
| 4683 push(tmp_reg); | |
| 4684 } | |
| 4685 get_thread(tmp_reg); | |
| 4686 orl(tmp_reg, swap_reg); | |
| 4687 if (os::is_MP()) { | |
| 4688 lock(); | |
| 4689 } | |
| 4690 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4691 if (need_tmp_reg) { | |
| 4692 pop(tmp_reg); | |
| 4693 } | |
| 4694 // If the biasing toward our thread failed, this means that | |
| 4695 // another thread succeeded in biasing it toward itself and we | |
| 4696 // need to revoke that bias. The revocation will occur in the | |
| 4697 // interpreter runtime in the slow case. | |
| 4698 if (counters != NULL) { | |
| 4699 cond_inc32(Assembler::zero, | |
| 4700 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 4701 } | |
| 4702 if (slow_case != NULL) { | |
| 4703 jcc(Assembler::notZero, *slow_case); | |
| 4704 } | |
| 4705 jmp(done); | |
| 4706 | |
| 4707 bind(try_rebias); | |
| 4708 // At this point we know the epoch has expired, meaning that the | |
| 4709 // current "bias owner", if any, is actually invalid. Under these | |
| 4710 // circumstances _only_, we are allowed to use the current header's | |
| 4711 // value as the comparison value when doing the cas to acquire the | |
| 4712 // bias in the current epoch. In other words, we allow transfer of | |
| 4713 // the bias from one thread to another directly in this situation. | |
| 4714 // | |
| 4715 // FIXME: due to a lack of registers we currently blow away the age | |
| 4716 // bits in this situation. Should attempt to preserve them. | |
| 4717 if (need_tmp_reg) { | |
| 4718 push(tmp_reg); | |
| 4719 } | |
| 4720 get_thread(tmp_reg); | |
| 4721 movl(swap_reg, klass_addr); | |
| 4722 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4723 movl(swap_reg, saved_mark_addr); | |
| 4724 if (os::is_MP()) { | |
| 4725 lock(); | |
| 4726 } | |
| 4727 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4728 if (need_tmp_reg) { | |
| 4729 pop(tmp_reg); | |
| 4730 } | |
| 4731 // If the biasing toward our thread failed, then another thread | |
| 4732 // succeeded in biasing it toward itself and we need to revoke that | |
| 4733 // bias. The revocation will occur in the runtime in the slow case. | |
| 4734 if (counters != NULL) { | |
| 4735 cond_inc32(Assembler::zero, | |
| 4736 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 4737 } | |
| 4738 if (slow_case != NULL) { | |
| 4739 jcc(Assembler::notZero, *slow_case); | |
| 4740 } | |
| 4741 jmp(done); | |
| 4742 | |
| 4743 bind(try_revoke_bias); | |
| 4744 // The prototype mark in the klass doesn't have the bias bit set any | |
| 4745 // more, indicating that objects of this data type are not supposed | |
| 4746 // to be biased any more. We are going to try to reset the mark of | |
| 4747 // this object to the prototype value and fall through to the | |
| 4748 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 4749 // that another thread raced us for the privilege of revoking the | |
| 4750 // bias of this particular object, so it's okay to continue in the | |
| 4751 // normal locking code. | |
| 4752 // | |
| 4753 // FIXME: due to a lack of registers we currently blow away the age | |
| 4754 // bits in this situation. Should attempt to preserve them. | |
| 4755 movl(swap_reg, saved_mark_addr); | |
| 4756 if (need_tmp_reg) { | |
| 4757 push(tmp_reg); | |
| 4758 } | |
| 4759 movl(tmp_reg, klass_addr); | |
| 4760 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4761 if (os::is_MP()) { | |
| 4762 lock(); | |
| 4763 } | |
| 4764 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4765 if (need_tmp_reg) { | |
| 4766 pop(tmp_reg); | |
| 4767 } | |
| 4768 // Fall through to the normal CAS-based lock, because no matter what | |
| 4769 // the result of the above CAS, some thread must have succeeded in | |
| 4770 // removing the bias bit from the object's header. | |
| 4771 if (counters != NULL) { | |
| 4772 cond_inc32(Assembler::zero, | |
| 4773 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 4774 } | |
| 4775 | |
| 4776 bind(cas_label); | |
| 4777 | |
| 4778 return null_check_offset; | |
| 4779 } | |
| 4780 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 4781 int number_of_arguments) { | |
| 4782 call(RuntimeAddress(entry_point)); | |
| 4783 increment(rsp, number_of_arguments * wordSize); | |
| 4784 } | |
| 4785 | |
| 4786 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
| 4787 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4788 } | |
| 4789 | |
| 4790 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 4791 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4792 } | |
| 4793 | |
| 4794 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 4795 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 4796 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 4797 cdql(); | |
| 4798 } else { | |
| 4799 movl(hi, lo); | |
| 4800 sarl(hi, 31); | |
| 4801 } | |
| 4802 } | |
| 4803 | |
| 0 | 4804 void MacroAssembler::fat_nop() { |
| 4805 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 4806 emit_byte(0x26); // es: | |
| 4807 emit_byte(0x2e); // cs: | |
| 4808 emit_byte(0x64); // fs: | |
| 4809 emit_byte(0x65); // gs: | |
| 4810 emit_byte(0x90); | |
| 4811 } | |
| 4812 | |
| 304 | 4813 void MacroAssembler::jC2(Register tmp, Label& L) { |
| 4814 // set parity bit if FPU flag C2 is set (via rax) | |
| 4815 save_rax(tmp); | |
| 4816 fwait(); fnstsw_ax(); | |
| 4817 sahf(); | |
| 4818 restore_rax(tmp); | |
| 4819 // branch | |
| 4820 jcc(Assembler::parity, L); | |
| 4821 } | |
| 4822 | |
| 4823 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 4824 // set parity bit if FPU flag C2 is set (via rax) | |
| 4825 save_rax(tmp); | |
| 4826 fwait(); fnstsw_ax(); | |
| 4827 sahf(); | |
| 4828 restore_rax(tmp); | |
| 4829 // branch | |
| 4830 jcc(Assembler::noParity, L); | |
| 4831 } | |
| 4832 | |
| 0 | 4833 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 4834 // to be installed in the Address class | |
| 4835 void MacroAssembler::jump(ArrayAddress entry) { | |
| 4836 jmp(as_Address(entry)); | |
| 4837 } | |
| 4838 | |
| 304 | 4839 // Note: y_lo will be destroyed |
| 4840 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 4841 // Long compare for Java (semantics as described in JVM spec.) | |
| 4842 Label high, low, done; | |
| 4843 | |
| 4844 cmpl(x_hi, y_hi); | |
| 4845 jcc(Assembler::less, low); | |
| 4846 jcc(Assembler::greater, high); | |
| 4847 // x_hi is the return register | |
| 4848 xorl(x_hi, x_hi); | |
| 4849 cmpl(x_lo, y_lo); | |
| 4850 jcc(Assembler::below, low); | |
| 4851 jcc(Assembler::equal, done); | |
| 4852 | |
| 4853 bind(high); | |
| 4854 xorl(x_hi, x_hi); | |
| 4855 increment(x_hi); | |
| 4856 jmp(done); | |
| 4857 | |
| 4858 bind(low); | |
| 4859 xorl(x_hi, x_hi); | |
| 4860 decrementl(x_hi); | |
| 4861 | |
| 4862 bind(done); | |
| 4863 } | |
| 4864 | |
| 4865 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 4866 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 4867 } |
| 4868 | |
| 4869 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 4870 // leal(dst, as_Address(adr)); | |
| 304 | 4871 // see note in movl as to why we must use a move |
| 0 | 4872 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 4873 } | |
| 4874 | |
| 4875 void MacroAssembler::leave() { | |
| 304 | 4876 mov(rsp, rbp); |
| 4877 pop(rbp); | |
| 4878 } | |
| 0 | 4879 |
| 4880 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 4881 // Multiplication of two Java long values stored on the stack | |
| 4882 // as illustrated below. Result is in rdx:rax. | |
| 4883 // | |
| 4884 // rsp ---> [ ?? ] \ \ | |
| 4885 // .... | y_rsp_offset | | |
| 4886 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 4887 // [ y_hi ] | (in bytes) | |
| 4888 // .... | | |
| 4889 // [ x_lo ] / | |
| 4890 // [ x_hi ] | |
| 4891 // .... | |
| 4892 // | |
| 4893 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 4894 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 4895 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 4896 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 4897 Label quick; | |
| 4898 // load x_hi, y_hi and check if quick | |
| 4899 // multiplication is possible | |
| 4900 movl(rbx, x_hi); | |
| 4901 movl(rcx, y_hi); | |
| 4902 movl(rax, rbx); | |
| 4903 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 4904 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 4905 // do full multiplication | |
| 4906 // 1st step | |
| 4907 mull(y_lo); // x_hi * y_lo | |
| 4908 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 4909 // 2nd step | |
| 4910 movl(rax, x_lo); | |
| 4911 mull(rcx); // x_lo * y_hi | |
| 4912 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 4913 // 3rd step | |
| 4914 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 4915 movl(rax, x_lo); | |
| 4916 mull(y_lo); // x_lo * y_lo | |
| 4917 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 4918 } | |
| 4919 | |
| 304 | 4920 void MacroAssembler::lneg(Register hi, Register lo) { |
| 4921 negl(lo); | |
| 4922 adcl(hi, 0); | |
| 4923 negl(hi); | |
| 4924 } | |
| 0 | 4925 |
| 4926 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 4927 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 4928 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 4929 // shift value is in rcx ! | |
| 4930 assert(hi != rcx, "must not use rcx"); | |
| 4931 assert(lo != rcx, "must not use rcx"); | |
| 4932 const Register s = rcx; // shift count | |
| 4933 const int n = BitsPerWord; | |
| 4934 Label L; | |
| 4935 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4936 cmpl(s, n); // if (s < n) | |
| 4937 jcc(Assembler::less, L); // else (s >= n) | |
| 4938 movl(hi, lo); // x := x << n | |
| 4939 xorl(lo, lo); | |
| 4940 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4941 bind(L); // s (mod n) < n | |
| 4942 shldl(hi, lo); // x := x << s | |
| 4943 shll(lo); | |
| 4944 } | |
| 4945 | |
| 4946 | |
| 4947 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 4948 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 4949 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 4950 assert(hi != rcx, "must not use rcx"); | |
| 4951 assert(lo != rcx, "must not use rcx"); | |
| 4952 const Register s = rcx; // shift count | |
| 4953 const int n = BitsPerWord; | |
| 4954 Label L; | |
| 4955 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4956 cmpl(s, n); // if (s < n) | |
| 4957 jcc(Assembler::less, L); // else (s >= n) | |
| 4958 movl(lo, hi); // x := x >> n | |
| 4959 if (sign_extension) sarl(hi, 31); | |
| 4960 else xorl(hi, hi); | |
| 4961 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4962 bind(L); // s (mod n) < n | |
| 4963 shrdl(lo, hi); // x := x >> s | |
| 4964 if (sign_extension) sarl(hi); | |
| 4965 else shrl(hi); | |
| 4966 } | |
| 4967 | |
| 304 | 4968 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 4969 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4970 } | |
| 4971 | |
| 4972 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 4973 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4974 } | |
| 4975 | |
| 4976 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 4977 if (src.is_lval()) { | |
| 4978 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 4979 } else { | |
| 4980 movl(dst, as_Address(src)); | |
| 4981 } | |
| 4982 } | |
| 4983 | |
| 4984 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 4985 movl(as_Address(dst), src); | |
| 4986 } | |
| 4987 | |
| 4988 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 4989 movl(dst, as_Address(src)); | |
| 4990 } | |
| 4991 | |
| 4992 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 4993 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 4994 movl(dst, src); | |
| 4995 } | |
| 4996 | |
| 4997 | |
| 4998 void MacroAssembler::pop_callee_saved_registers() { | |
| 4999 pop(rcx); | |
| 5000 pop(rdx); | |
| 5001 pop(rdi); | |
| 5002 pop(rsi); | |
| 5003 } | |
| 5004 | |
| 5005 void MacroAssembler::pop_fTOS() { | |
| 5006 fld_d(Address(rsp, 0)); | |
| 5007 addl(rsp, 2 * wordSize); | |
| 5008 } | |
| 5009 | |
| 5010 void MacroAssembler::push_callee_saved_registers() { | |
| 5011 push(rsi); | |
| 5012 push(rdi); | |
| 5013 push(rdx); | |
| 5014 push(rcx); | |
| 5015 } | |
| 5016 | |
| 5017 void MacroAssembler::push_fTOS() { | |
| 5018 subl(rsp, 2 * wordSize); | |
| 5019 fstp_d(Address(rsp, 0)); | |
| 5020 } | |
| 5021 | |
| 5022 | |
| 5023 void MacroAssembler::pushoop(jobject obj) { | |
| 5024 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5025 } | |
| 5026 | |
| 5027 | |
| 5028 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5029 if (src.is_lval()) { | |
| 5030 push_literal32((int32_t)src.target(), src.rspec()); | |
| 5031 } else { | |
| 5032 pushl(as_Address(src)); | |
| 5033 } | |
| 5034 } | |
| 5035 | |
| 5036 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 5037 xorl(dst, dst); | |
| 5038 set_byte_if_not_zero(dst); | |
| 5039 } | |
| 5040 | |
| 5041 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5042 masm->push(arg); | |
| 5043 } | |
| 5044 | |
| 5045 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5046 masm->push(arg); | |
| 5047 } | |
| 5048 | |
| 5049 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5050 masm->push(arg); | |
| 5051 } | |
| 5052 | |
| 5053 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5054 masm->push(arg); | |
| 5055 } | |
| 5056 | |
| 5057 #ifndef PRODUCT | |
| 5058 extern "C" void findpc(intptr_t x); | |
| 5059 #endif | |
| 5060 | |
| 5061 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 5062 // In order to get locks to work, we need to fake a in_VM state | |
| 5063 JavaThread* thread = JavaThread::current(); | |
| 5064 JavaThreadState saved_state = thread->thread_state(); | |
| 5065 thread->set_thread_state(_thread_in_vm); | |
| 5066 if (ShowMessageBoxOnError) { | |
| 5067 JavaThread* thread = JavaThread::current(); | |
| 5068 JavaThreadState saved_state = thread->thread_state(); | |
| 5069 thread->set_thread_state(_thread_in_vm); | |
| 5070 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5071 ttyLocker ttyl; | |
| 5072 BytecodeCounter::print(); | |
| 5073 } | |
| 5074 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5075 // This is the value of eip which points to where verify_oop will return. | |
| 5076 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5077 ttyLocker ttyl; | |
| 5078 tty->print_cr("eip = 0x%08x", eip); | |
| 5079 #ifndef PRODUCT | |
|
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|
5080 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
|
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|
5081 tty->cr(); |
|
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|
5082 findpc(eip); |
|
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|
5083 tty->cr(); |
|
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|
5084 } |
| 304 | 5085 #endif |
|
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|
5086 tty->print_cr("rax = 0x%08x", rax); |
|
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|
5087 tty->print_cr("rbx = 0x%08x", rbx); |
| 304 | 5088 tty->print_cr("rcx = 0x%08x", rcx); |
| 5089 tty->print_cr("rdx = 0x%08x", rdx); | |
| 5090 tty->print_cr("rdi = 0x%08x", rdi); | |
| 5091 tty->print_cr("rsi = 0x%08x", rsi); | |
|
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|
5092 tty->print_cr("rbp = 0x%08x", rbp); |
| 304 | 5093 tty->print_cr("rsp = 0x%08x", rsp); |
| 5094 BREAKPOINT; | |
|
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|
5095 assert(false, "start up GDB"); |
| 304 | 5096 } |
| 5097 } else { | |
| 5098 ttyLocker ttyl; | |
| 5099 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
|
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|
5100 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 5101 } |
| 5102 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
| 5103 } | |
| 5104 | |
| 5105 void MacroAssembler::stop(const char* msg) { | |
| 5106 ExternalAddress message((address)msg); | |
| 5107 // push address of message | |
| 5108 pushptr(message.addr()); | |
| 5109 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
| 5110 pusha(); // push registers | |
| 5111 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
| 5112 hlt(); | |
| 5113 } | |
| 5114 | |
| 5115 void MacroAssembler::warn(const char* msg) { | |
| 5116 push_CPU_state(); | |
| 5117 | |
| 5118 ExternalAddress message((address) msg); | |
| 5119 // push address of message | |
| 5120 pushptr(message.addr()); | |
| 5121 | |
| 5122 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 5123 addl(rsp, wordSize); // discard argument | |
| 5124 pop_CPU_state(); | |
| 5125 } | |
| 5126 | |
| 5127 #else // _LP64 | |
| 5128 | |
| 5129 // 64 bit versions | |
| 5130 | |
| 5131 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 5132 // amd64 always does this as a pc-rel | |
| 5133 // we can be absolute or disp based on the instruction type | |
| 5134 // jmp/call are displacements others are absolute | |
| 5135 assert(!adr.is_lval(), "must be rval"); | |
| 5136 assert(reachable(adr), "must be"); | |
| 5137 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 5138 | |
| 5139 } | |
| 5140 | |
| 5141 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 5142 AddressLiteral base = adr.base(); | |
| 5143 lea(rscratch1, base); | |
| 5144 Address index = adr.index(); | |
| 5145 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 5146 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 5147 return array; | |
| 5148 } | |
| 5149 | |
| 5150 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 5151 Register obj_reg, | |
| 5152 Register swap_reg, | |
| 5153 Register tmp_reg, | |
| 5154 bool swap_reg_contains_mark, | |
| 5155 Label& done, | |
| 5156 Label* slow_case, | |
| 5157 BiasedLockingCounters* counters) { | |
| 5158 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5159 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 5160 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 5161 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5162 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5163 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5164 Address saved_mark_addr(lock_reg, 0); | |
| 5165 | |
| 5166 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5167 counters = BiasedLocking::counters(); | |
| 5168 | |
| 5169 // Biased locking | |
| 5170 // See whether the lock is currently biased toward our thread and | |
| 5171 // whether the epoch is still valid | |
| 5172 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5173 // pointers to allow age to be placed into low bits | |
| 5174 // First check to see whether biasing is even enabled for this object | |
| 5175 Label cas_label; | |
| 5176 int null_check_offset = -1; | |
| 5177 if (!swap_reg_contains_mark) { | |
| 5178 null_check_offset = offset(); | |
| 5179 movq(swap_reg, mark_addr); | |
| 5180 } | |
| 5181 movq(tmp_reg, swap_reg); | |
| 5182 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5183 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5184 jcc(Assembler::notEqual, cas_label); | |
| 5185 // The bias pattern is present in the object's header. Need to check | |
| 5186 // whether the bias owner and the epoch are both still current. | |
| 5187 load_prototype_header(tmp_reg, obj_reg); | |
| 5188 orq(tmp_reg, r15_thread); | |
| 5189 xorq(tmp_reg, swap_reg); | |
| 5190 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 5191 if (counters != NULL) { | |
| 5192 cond_inc32(Assembler::zero, | |
| 5193 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5194 } | |
| 0 | 5195 jcc(Assembler::equal, done); |
| 5196 | |
| 304 | 5197 Label try_revoke_bias; |
| 5198 Label try_rebias; | |
| 5199 | |
| 5200 // At this point we know that the header has the bias pattern and | |
| 5201 // that we are not the bias owner in the current epoch. We need to | |
| 5202 // figure out more details about the state of the header in order to | |
| 5203 // know what operations can be legally performed on the object's | |
| 5204 // header. | |
| 5205 | |
| 5206 // If the low three bits in the xor result aren't clear, that means | |
| 5207 // the prototype header is no longer biased and we have to revoke | |
| 5208 // the bias on this object. | |
| 5209 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5210 jcc(Assembler::notZero, try_revoke_bias); | |
| 5211 | |
| 5212 // Biasing is still enabled for this data type. See whether the | |
| 5213 // epoch of the current bias is still valid, meaning that the epoch | |
| 5214 // bits of the mark word are equal to the epoch bits of the | |
| 5215 // prototype header. (Note that the prototype header's epoch bits | |
| 5216 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5217 // toward the current thread. Note that we must be absolutely sure | |
| 5218 // that the current epoch is invalid in order to do this because | |
| 5219 // otherwise the manipulations it performs on the mark word are | |
| 5220 // illegal. | |
| 5221 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 5222 jcc(Assembler::notZero, try_rebias); | |
| 5223 | |
| 5224 // The epoch of the current bias is still valid but we know nothing | |
| 5225 // about the owner; it might be set or it might be clear. Try to | |
| 5226 // acquire the bias of the object using an atomic operation. If this | |
| 5227 // fails we will go in to the runtime to revoke the object's bias. | |
| 5228 // Note that we first construct the presumed unbiased header so we | |
| 5229 // don't accidentally blow away another thread's valid bias. | |
| 5230 andq(swap_reg, | |
| 5231 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5232 movq(tmp_reg, swap_reg); | |
| 5233 orq(tmp_reg, r15_thread); | |
| 5234 if (os::is_MP()) { | |
| 5235 lock(); | |
| 5236 } | |
| 5237 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5238 // If the biasing toward our thread failed, this means that | |
| 5239 // another thread succeeded in biasing it toward itself and we | |
| 5240 // need to revoke that bias. The revocation will occur in the | |
| 5241 // interpreter runtime in the slow case. | |
| 5242 if (counters != NULL) { | |
| 5243 cond_inc32(Assembler::zero, | |
| 5244 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5245 } | |
| 5246 if (slow_case != NULL) { | |
| 5247 jcc(Assembler::notZero, *slow_case); | |
| 5248 } | |
| 0 | 5249 jmp(done); |
| 5250 | |
| 304 | 5251 bind(try_rebias); |
| 5252 // At this point we know the epoch has expired, meaning that the | |
| 5253 // current "bias owner", if any, is actually invalid. Under these | |
| 5254 // circumstances _only_, we are allowed to use the current header's | |
| 5255 // value as the comparison value when doing the cas to acquire the | |
| 5256 // bias in the current epoch. In other words, we allow transfer of | |
| 5257 // the bias from one thread to another directly in this situation. | |
| 5258 // | |
| 5259 // FIXME: due to a lack of registers we currently blow away the age | |
| 5260 // bits in this situation. Should attempt to preserve them. | |
| 5261 load_prototype_header(tmp_reg, obj_reg); | |
| 5262 orq(tmp_reg, r15_thread); | |
| 5263 if (os::is_MP()) { | |
| 5264 lock(); | |
| 5265 } | |
| 5266 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5267 // If the biasing toward our thread failed, then another thread | |
| 5268 // succeeded in biasing it toward itself and we need to revoke that | |
| 5269 // bias. The revocation will occur in the runtime in the slow case. | |
| 5270 if (counters != NULL) { | |
| 5271 cond_inc32(Assembler::zero, | |
| 5272 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 5273 } | |
| 5274 if (slow_case != NULL) { | |
| 5275 jcc(Assembler::notZero, *slow_case); | |
| 0 | 5276 } |
| 5277 jmp(done); | |
| 5278 | |
| 304 | 5279 bind(try_revoke_bias); |
| 5280 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5281 // more, indicating that objects of this data type are not supposed | |
| 5282 // to be biased any more. We are going to try to reset the mark of | |
| 5283 // this object to the prototype value and fall through to the | |
| 5284 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5285 // that another thread raced us for the privilege of revoking the | |
| 5286 // bias of this particular object, so it's okay to continue in the | |
| 5287 // normal locking code. | |
| 5288 // | |
| 5289 // FIXME: due to a lack of registers we currently blow away the age | |
| 5290 // bits in this situation. Should attempt to preserve them. | |
| 5291 load_prototype_header(tmp_reg, obj_reg); | |
| 5292 if (os::is_MP()) { | |
| 5293 lock(); | |
| 5294 } | |
| 5295 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5296 // Fall through to the normal CAS-based lock, because no matter what | |
| 5297 // the result of the above CAS, some thread must have succeeded in | |
| 5298 // removing the bias bit from the object's header. | |
| 5299 if (counters != NULL) { | |
| 5300 cond_inc32(Assembler::zero, | |
| 5301 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 5302 } | |
| 5303 | |
| 5304 bind(cas_label); | |
| 5305 | |
| 5306 return null_check_offset; | |
| 5307 } | |
| 5308 | |
| 5309 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 5310 Label L, E; | |
| 5311 | |
| 5312 #ifdef _WIN64 | |
| 5313 // Windows always allocates space for it's register args | |
| 5314 assert(num_args <= 4, "only register arguments supported"); | |
| 5315 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 5316 #endif | |
| 5317 | |
| 5318 // Align stack if necessary | |
| 5319 testl(rsp, 15); | |
| 5320 jcc(Assembler::zero, L); | |
| 5321 | |
| 5322 subq(rsp, 8); | |
| 5323 { | |
| 5324 call(RuntimeAddress(entry_point)); | |
| 5325 } | |
| 5326 addq(rsp, 8); | |
| 5327 jmp(E); | |
| 5328 | |
| 5329 bind(L); | |
| 5330 { | |
| 5331 call(RuntimeAddress(entry_point)); | |
| 5332 } | |
| 5333 | |
| 5334 bind(E); | |
| 5335 | |
| 5336 #ifdef _WIN64 | |
| 5337 // restore stack pointer | |
| 5338 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 5339 #endif | |
| 5340 | |
| 5341 } | |
| 5342 | |
| 5343 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 5344 assert(!src2.is_lval(), "should use cmpptr"); | |
| 5345 | |
| 5346 if (reachable(src2)) { | |
| 5347 cmpq(src1, as_Address(src2)); | |
| 5348 } else { | |
| 5349 lea(rscratch1, src2); | |
| 5350 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5351 } | |
| 5352 } | |
| 5353 | |
| 5354 int MacroAssembler::corrected_idivq(Register reg) { | |
| 5355 // Full implementation of Java ldiv and lrem; checks for special | |
| 5356 // case as described in JVM spec., p.243 & p.271. The function | |
| 5357 // returns the (pc) offset of the idivl instruction - may be needed | |
| 5358 // for implicit exceptions. | |
| 5359 // | |
| 5360 // normal case special case | |
| 5361 // | |
| 5362 // input : rax: dividend min_long | |
| 5363 // reg: divisor (may not be eax/edx) -1 | |
| 5364 // | |
| 5365 // output: rax: quotient (= rax idiv reg) min_long | |
| 5366 // rdx: remainder (= rax irem reg) 0 | |
| 5367 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 5368 static const int64_t min_long = 0x8000000000000000; | |
| 5369 Label normal_case, special_case; | |
| 5370 | |
| 5371 // check for special case | |
| 5372 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 5373 jcc(Assembler::notEqual, normal_case); | |
| 5374 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 5375 // remainder = 0) | |
| 5376 cmpq(reg, -1); | |
| 5377 jcc(Assembler::equal, special_case); | |
| 5378 | |
| 5379 // handle normal case | |
| 5380 bind(normal_case); | |
| 5381 cdqq(); | |
| 5382 int idivq_offset = offset(); | |
| 5383 idivq(reg); | |
| 5384 | |
| 5385 // normal and special case exit | |
| 5386 bind(special_case); | |
| 5387 | |
| 5388 return idivq_offset; | |
| 5389 } | |
| 5390 | |
| 5391 void MacroAssembler::decrementq(Register reg, int value) { | |
| 5392 if (value == min_jint) { subq(reg, value); return; } | |
| 5393 if (value < 0) { incrementq(reg, -value); return; } | |
| 5394 if (value == 0) { ; return; } | |
| 5395 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 5396 /* else */ { subq(reg, value) ; return; } | |
| 5397 } | |
| 5398 | |
| 5399 void MacroAssembler::decrementq(Address dst, int value) { | |
| 5400 if (value == min_jint) { subq(dst, value); return; } | |
| 5401 if (value < 0) { incrementq(dst, -value); return; } | |
| 5402 if (value == 0) { ; return; } | |
| 5403 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 5404 /* else */ { subq(dst, value) ; return; } | |
| 5405 } | |
| 5406 | |
| 5407 void MacroAssembler::fat_nop() { | |
| 5408 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 5409 // Recommened sequence from 'Software Optimization Guide for the AMD | |
| 5410 // Hammer Processor' | |
| 5411 emit_byte(0x66); | |
| 5412 emit_byte(0x66); | |
| 5413 emit_byte(0x90); | |
| 5414 emit_byte(0x66); | |
| 5415 emit_byte(0x90); | |
| 5416 } | |
| 5417 | |
| 5418 void MacroAssembler::incrementq(Register reg, int value) { | |
| 5419 if (value == min_jint) { addq(reg, value); return; } | |
| 5420 if (value < 0) { decrementq(reg, -value); return; } | |
| 5421 if (value == 0) { ; return; } | |
| 5422 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 5423 /* else */ { addq(reg, value) ; return; } | |
| 5424 } | |
| 5425 | |
| 5426 void MacroAssembler::incrementq(Address dst, int value) { | |
| 5427 if (value == min_jint) { addq(dst, value); return; } | |
| 5428 if (value < 0) { decrementq(dst, -value); return; } | |
| 5429 if (value == 0) { ; return; } | |
| 5430 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 5431 /* else */ { addq(dst, value) ; return; } | |
| 5432 } | |
| 5433 | |
| 5434 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 5435 // to be installed in the Address class | |
| 5436 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5437 lea(rscratch1, entry.base()); | |
| 5438 Address dispatch = entry.index(); | |
| 5439 assert(dispatch._base == noreg, "must be"); | |
| 5440 dispatch._base = rscratch1; | |
| 5441 jmp(dispatch); | |
| 5442 } | |
| 5443 | |
| 5444 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5445 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5446 cmpq(x_lo, y_lo); | |
| 5447 } | |
| 5448 | |
| 5449 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5450 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5451 } | |
| 5452 | |
| 5453 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5454 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 5455 movptr(dst, rscratch1); | |
| 5456 } | |
| 5457 | |
| 5458 void MacroAssembler::leave() { | |
| 5459 // %%% is this really better? Why not on 32bit too? | |
| 5460 emit_byte(0xC9); // LEAVE | |
| 5461 } | |
| 5462 | |
| 5463 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 5464 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5465 negq(lo); | |
| 5466 } | |
| 5467 | |
| 5468 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 5469 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5470 } | |
| 5471 | |
| 5472 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5473 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5474 movq(dst, rscratch1); | |
| 5475 } | |
| 5476 | |
| 5477 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5478 if (src.is_lval()) { | |
| 5479 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5480 } else { | |
| 5481 if (reachable(src)) { | |
| 5482 movq(dst, as_Address(src)); | |
| 5483 } else { | |
| 5484 lea(rscratch1, src); | |
| 5485 movq(dst, Address(rscratch1,0)); | |
| 0 | 5486 } |
| 304 | 5487 } |
| 5488 } | |
| 5489 | |
| 5490 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5491 movq(as_Address(dst), src); | |
| 5492 } | |
| 5493 | |
| 5494 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5495 movq(dst, as_Address(src)); | |
| 5496 } | |
| 5497 | |
| 5498 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5499 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5500 mov64(rscratch1, src); | |
| 5501 movq(dst, rscratch1); | |
| 5502 } | |
| 5503 | |
| 5504 // These are mostly for initializing NULL | |
| 5505 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 5506 movslq(dst, src); | |
| 5507 } | |
| 5508 | |
| 5509 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 5510 mov64(dst, (intptr_t)src); | |
| 5511 } | |
| 5512 | |
| 5513 void MacroAssembler::pushoop(jobject obj) { | |
| 5514 movoop(rscratch1, obj); | |
| 5515 push(rscratch1); | |
| 5516 } | |
| 5517 | |
| 5518 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5519 lea(rscratch1, src); | |
| 5520 if (src.is_lval()) { | |
| 5521 push(rscratch1); | |
| 5522 } else { | |
| 5523 pushq(Address(rscratch1, 0)); | |
| 5524 } | |
| 5525 } | |
| 5526 | |
| 5527 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 5528 bool clear_pc) { | |
| 5529 // we must set sp to zero to clear frame | |
|
512
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xlu
parents:
420
diff
changeset
|
5530 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 5531 // must clear fp, so that compiled frames are not confused; it is |
| 5532 // possible that we need it only for debugging | |
| 5533 if (clear_fp) { | |
|
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420
diff
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|
5534 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 5535 } |
| 5536 | |
| 5537 if (clear_pc) { | |
|
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diff
changeset
|
5538 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 5539 } |
| 5540 } | |
| 5541 | |
| 5542 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 5543 Register last_java_fp, | |
| 5544 address last_java_pc) { | |
| 5545 // determine last_java_sp register | |
| 5546 if (!last_java_sp->is_valid()) { | |
| 5547 last_java_sp = rsp; | |
| 5548 } | |
| 5549 | |
| 5550 // last_java_fp is optional | |
| 5551 if (last_java_fp->is_valid()) { | |
| 5552 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 5553 last_java_fp); | |
| 5554 } | |
| 5555 | |
| 5556 // last_java_pc is optional | |
| 5557 if (last_java_pc != NULL) { | |
| 5558 Address java_pc(r15_thread, | |
| 5559 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 5560 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 5561 movptr(java_pc, rscratch1); | |
| 5562 } | |
| 5563 | |
| 5564 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 5565 } | |
| 5566 | |
| 5567 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5568 if (c_rarg0 != arg ) { | |
| 5569 masm->mov(c_rarg0, arg); | |
| 5570 } | |
| 5571 } | |
| 5572 | |
| 5573 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5574 if (c_rarg1 != arg ) { | |
| 5575 masm->mov(c_rarg1, arg); | |
| 5576 } | |
| 5577 } | |
| 5578 | |
| 5579 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5580 if (c_rarg2 != arg ) { | |
| 5581 masm->mov(c_rarg2, arg); | |
| 5582 } | |
| 5583 } | |
| 5584 | |
| 5585 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5586 if (c_rarg3 != arg ) { | |
| 5587 masm->mov(c_rarg3, arg); | |
| 5588 } | |
| 5589 } | |
| 5590 | |
| 5591 void MacroAssembler::stop(const char* msg) { | |
| 5592 address rip = pc(); | |
| 5593 pusha(); // get regs on stack | |
| 5594 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5595 lea(c_rarg1, InternalAddress(rip)); | |
| 5596 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 5597 andq(rsp, -16); // align stack as required by ABI | |
| 5598 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 5599 hlt(); | |
| 5600 } | |
| 5601 | |
| 5602 void MacroAssembler::warn(const char* msg) { | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
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1972
diff
changeset
|
5603 push(rsp); |
| 304 | 5604 andq(rsp, -16); // align stack as required by push_CPU_state and call |
| 5605 | |
| 5606 push_CPU_state(); // keeps alignment at 16 bytes | |
| 5607 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5608 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 5609 pop_CPU_state(); | |
|
1976
0fc262af204f
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diff
changeset
|
5610 pop(rsp); |
| 304 | 5611 } |
| 5612 | |
| 5613 #ifndef PRODUCT | |
| 5614 extern "C" void findpc(intptr_t x); | |
| 5615 #endif | |
| 5616 | |
| 5617 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 5618 // In order to get locks to work, we need to fake a in_VM state | |
| 5619 if (ShowMessageBoxOnError ) { | |
| 5620 JavaThread* thread = JavaThread::current(); | |
| 5621 JavaThreadState saved_state = thread->thread_state(); | |
| 5622 thread->set_thread_state(_thread_in_vm); | |
| 5623 #ifndef PRODUCT | |
| 5624 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5625 ttyLocker ttyl; | |
| 5626 BytecodeCounter::print(); | |
| 0 | 5627 } |
| 304 | 5628 #endif |
| 5629 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5630 // XXX correct this offset for amd64 | |
| 5631 // This is the value of eip which points to where verify_oop will return. | |
| 5632 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5633 ttyLocker ttyl; | |
| 5634 tty->print_cr("rip = 0x%016lx", pc); | |
| 5635 #ifndef PRODUCT | |
| 5636 tty->cr(); | |
| 5637 findpc(pc); | |
| 5638 tty->cr(); | |
| 5639 #endif | |
| 5640 tty->print_cr("rax = 0x%016lx", regs[15]); | |
| 5641 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
| 5642 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
| 5643 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
| 5644 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
| 5645 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
| 5646 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
| 5647 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
| 5648 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
| 5649 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
| 5650 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
| 5651 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
| 5652 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
| 5653 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
| 5654 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
| 5655 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
| 5656 BREAKPOINT; | |
| 0 | 5657 } |
| 304 | 5658 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 5659 } else { | |
| 5660 ttyLocker ttyl; | |
| 5661 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 5662 msg); | |
|
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3336
diff
changeset
|
5663 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 5664 } |
| 5665 } | |
| 5666 | |
| 5667 #endif // _LP64 | |
| 5668 | |
| 5669 // Now versions that are common to 32/64 bit | |
| 5670 | |
| 5671 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 5672 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 5673 } | |
| 5674 | |
| 5675 void MacroAssembler::addptr(Register dst, Register src) { | |
| 5676 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5677 } | |
| 5678 | |
| 5679 void MacroAssembler::addptr(Address dst, Register src) { | |
| 5680 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5681 } | |
| 5682 | |
| 5683 void MacroAssembler::align(int modulus) { | |
| 5684 if (offset() % modulus != 0) { | |
| 5685 nop(modulus - (offset() % modulus)); | |
| 5686 } | |
| 5687 } | |
| 5688 | |
| 5689 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 5690 if (reachable(src)) { |
| 5691 andpd(dst, as_Address(src)); | |
| 5692 } else { | |
| 5693 lea(rscratch1, src); | |
| 5694 andpd(dst, Address(rscratch1, 0)); | |
| 5695 } | |
| 304 | 5696 } |
| 5697 | |
| 5698 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 5699 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 5700 } | |
| 5701 | |
| 5702 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 5703 pushf(); | |
| 5704 if (os::is_MP()) | |
| 5705 lock(); | |
| 5706 incrementl(counter_addr); | |
| 5707 popf(); | |
| 5708 } | |
| 5709 | |
| 5710 // Writes to stack successive pages until offset reached to check for | |
| 5711 // stack overflow + shadow pages. This clobbers tmp. | |
| 5712 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 5713 movptr(tmp, rsp); | |
| 5714 // Bang stack for total size given plus shadow page size. | |
| 5715 // Bang one page at a time because large size can bang beyond yellow and | |
| 5716 // red zones. | |
| 5717 Label loop; | |
| 5718 bind(loop); | |
| 5719 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 5720 subptr(tmp, os::vm_page_size()); | |
| 5721 subl(size, os::vm_page_size()); | |
| 5722 jcc(Assembler::greater, loop); | |
| 5723 | |
| 5724 // Bang down shadow pages too. | |
| 5725 // The -1 because we already subtracted 1 page. | |
| 5726 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 5727 // this could be any sized move but this is can be a debugging crumb | |
| 5728 // so the bigger the better. | |
| 5729 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 5730 } | |
| 5731 } | |
| 5732 | |
| 5733 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 5734 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5735 | |
| 5736 // Check for biased locking unlock case, which is a no-op | |
| 5737 // Note: we do not have to check the thread ID for two reasons. | |
| 5738 // First, the interpreter checks for IllegalMonitorStateException at | |
| 5739 // a higher level. Second, if the bias was revoked while we held the | |
| 5740 // lock, the object could not be rebiased toward another thread, so | |
| 5741 // the bias bit would be clear. | |
| 5742 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 5743 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5744 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 5745 jcc(Assembler::equal, done); | |
| 5746 } | |
| 5747 | |
| 5748 void MacroAssembler::c2bool(Register x) { | |
| 5749 // implements x == 0 ? 0 : 1 | |
| 5750 // note: must only look at least-significant byte of x | |
| 5751 // since C-style booleans are stored in one byte | |
| 5752 // only! (was bug) | |
| 5753 andl(x, 0xFF); | |
| 5754 setb(Assembler::notZero, x); | |
| 5755 } | |
| 5756 | |
| 5757 // Wouldn't need if AddressLiteral version had new name | |
| 5758 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 5759 Assembler::call(L, rtype); | |
| 5760 } | |
| 5761 | |
| 5762 void MacroAssembler::call(Register entry) { | |
| 5763 Assembler::call(entry); | |
| 5764 } | |
| 5765 | |
| 5766 void MacroAssembler::call(AddressLiteral entry) { | |
| 5767 if (reachable(entry)) { | |
| 5768 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 5769 } else { | |
| 5770 lea(rscratch1, entry); | |
| 5771 Assembler::call(rscratch1); | |
| 5772 } | |
| 5773 } | |
| 5774 | |
| 5775 // Implementation of call_VM versions | |
| 5776 | |
| 5777 void MacroAssembler::call_VM(Register oop_result, | |
| 5778 address entry_point, | |
| 5779 bool check_exceptions) { | |
| 5780 Label C, E; | |
| 5781 call(C, relocInfo::none); | |
| 5782 jmp(E); | |
| 5783 | |
| 5784 bind(C); | |
| 5785 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 5786 ret(0); | |
| 5787 | |
| 5788 bind(E); | |
| 5789 } | |
| 5790 | |
| 5791 void MacroAssembler::call_VM(Register oop_result, | |
| 5792 address entry_point, | |
| 5793 Register arg_1, | |
| 5794 bool check_exceptions) { | |
| 5795 Label C, E; | |
| 5796 call(C, relocInfo::none); | |
| 5797 jmp(E); | |
| 5798 | |
| 5799 bind(C); | |
| 5800 pass_arg1(this, arg_1); | |
| 5801 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 5802 ret(0); | |
| 5803 | |
| 5804 bind(E); | |
| 5805 } | |
| 5806 | |
| 5807 void MacroAssembler::call_VM(Register oop_result, | |
| 5808 address entry_point, | |
| 5809 Register arg_1, | |
| 5810 Register arg_2, | |
| 5811 bool check_exceptions) { | |
| 5812 Label C, E; | |
| 5813 call(C, relocInfo::none); | |
| 5814 jmp(E); | |
| 5815 | |
| 5816 bind(C); | |
| 5817 | |
| 5818 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5819 | |
| 5820 pass_arg2(this, arg_2); | |
| 5821 pass_arg1(this, arg_1); | |
| 5822 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 5823 ret(0); | |
| 5824 | |
| 5825 bind(E); | |
| 5826 } | |
| 5827 | |
| 5828 void MacroAssembler::call_VM(Register oop_result, | |
| 5829 address entry_point, | |
| 5830 Register arg_1, | |
| 5831 Register arg_2, | |
| 5832 Register arg_3, | |
| 5833 bool check_exceptions) { | |
| 5834 Label C, E; | |
| 5835 call(C, relocInfo::none); | |
| 5836 jmp(E); | |
| 5837 | |
| 5838 bind(C); | |
| 5839 | |
| 5840 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5841 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5842 pass_arg3(this, arg_3); | |
| 5843 | |
| 5844 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5845 pass_arg2(this, arg_2); | |
| 5846 | |
| 5847 pass_arg1(this, arg_1); | |
| 5848 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 5849 ret(0); | |
| 5850 | |
| 5851 bind(E); | |
| 5852 } | |
| 5853 | |
| 5854 void MacroAssembler::call_VM(Register oop_result, | |
| 5855 Register last_java_sp, | |
| 5856 address entry_point, | |
| 5857 int number_of_arguments, | |
| 5858 bool check_exceptions) { | |
| 5859 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 5860 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 5861 } | |
| 5862 | |
| 5863 void MacroAssembler::call_VM(Register oop_result, | |
| 5864 Register last_java_sp, | |
| 5865 address entry_point, | |
| 5866 Register arg_1, | |
| 5867 bool check_exceptions) { | |
| 5868 pass_arg1(this, arg_1); | |
| 5869 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 5870 } | |
| 5871 | |
| 5872 void MacroAssembler::call_VM(Register oop_result, | |
| 5873 Register last_java_sp, | |
| 5874 address entry_point, | |
| 5875 Register arg_1, | |
| 5876 Register arg_2, | |
| 5877 bool check_exceptions) { | |
| 5878 | |
| 5879 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5880 pass_arg2(this, arg_2); | |
| 5881 pass_arg1(this, arg_1); | |
| 5882 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 5883 } | |
| 5884 | |
| 5885 void MacroAssembler::call_VM(Register oop_result, | |
| 5886 Register last_java_sp, | |
| 5887 address entry_point, | |
| 5888 Register arg_1, | |
| 5889 Register arg_2, | |
| 5890 Register arg_3, | |
| 5891 bool check_exceptions) { | |
| 5892 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5893 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5894 pass_arg3(this, arg_3); | |
| 5895 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5896 pass_arg2(this, arg_2); | |
| 5897 pass_arg1(this, arg_1); | |
| 5898 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 5899 } | |
| 5900 | |
|
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3442
diff
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|
5901 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3442
diff
changeset
|
5902 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
changeset
|
5903 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3442
diff
changeset
|
5904 int number_of_arguments, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
changeset
|
5905 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
changeset
|
5906 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
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|
5907 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
changeset
|
5908 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
changeset
|
5909 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5910 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5911 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5912 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5913 Register arg_1, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5914 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5915 pass_arg1(this, arg_1); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5916 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5917 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5918 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5919 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5920 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5921 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5922 Register arg_1, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5923 Register arg_2, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5924 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5925 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5926 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5927 pass_arg2(this, arg_2); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5928 pass_arg1(this, arg_1); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5929 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3442
diff
changeset
|
5930 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5931 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5932 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5933 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5934 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5935 Register arg_1, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5936 Register arg_2, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5937 Register arg_3, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5938 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5939 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5940 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5941 pass_arg3(this, arg_3); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5942 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5943 pass_arg2(this, arg_2); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5944 pass_arg1(this, arg_1); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5945 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5946 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
5947 |
| 304 | 5948 void MacroAssembler::call_VM_base(Register oop_result, |
| 5949 Register java_thread, | |
| 5950 Register last_java_sp, | |
| 5951 address entry_point, | |
| 5952 int number_of_arguments, | |
| 5953 bool check_exceptions) { | |
| 5954 // determine java_thread register | |
| 5955 if (!java_thread->is_valid()) { | |
| 5956 #ifdef _LP64 | |
| 5957 java_thread = r15_thread; | |
| 5958 #else | |
| 5959 java_thread = rdi; | |
| 5960 get_thread(java_thread); | |
| 5961 #endif // LP64 | |
| 5962 } | |
| 5963 // determine last_java_sp register | |
| 5964 if (!last_java_sp->is_valid()) { | |
| 5965 last_java_sp = rsp; | |
| 5966 } | |
| 5967 // debugging support | |
| 5968 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 5969 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5970 #ifdef ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5971 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");) |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5972 #endif // ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5973 |
| 304 | 5974 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
| 5975 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 5976 | |
| 5977 // push java thread (becomes first argument of C function) | |
| 5978 | |
| 5979 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 5980 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 5981 | |
| 5982 // set last Java frame before call | |
| 5983 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 5984 | |
| 5985 // Only interpreter should have to set fp | |
| 5986 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 5987 | |
| 5988 // do the call, remove parameters | |
| 5989 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5990 | |
| 5991 // restore the thread (cannot use the pushed argument since arguments | |
| 5992 // may be overwritten by C code generated by an optimizing compiler); | |
| 5993 // however can use the register value directly if it is callee saved. | |
| 5994 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 5995 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 5996 #ifdef ASSERT | |
| 5997 guarantee(java_thread != rax, "change this code"); | |
| 5998 push(rax); | |
| 5999 { Label L; | |
| 6000 get_thread(rax); | |
| 6001 cmpptr(java_thread, rax); | |
| 6002 jcc(Assembler::equal, L); | |
| 6003 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
| 6004 bind(L); | |
| 0 | 6005 } |
| 304 | 6006 pop(rax); |
| 6007 #endif | |
| 6008 } else { | |
| 6009 get_thread(java_thread); | |
| 6010 } | |
| 6011 // reset last Java frame | |
| 6012 // Only interpreter should have to clear fp | |
| 6013 reset_last_Java_frame(java_thread, true, false); | |
| 6014 | |
| 6015 #ifndef CC_INTERP | |
| 6016 // C++ interp handles this in the interpreter | |
| 6017 check_and_handle_popframe(java_thread); | |
| 6018 check_and_handle_earlyret(java_thread); | |
| 6019 #endif /* CC_INTERP */ | |
| 6020 | |
| 6021 if (check_exceptions) { | |
| 6022 // check for pending exceptions (java_thread is set upon return) | |
| 6023 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 6024 #ifndef _LP64 | |
| 6025 jump_cc(Assembler::notEqual, | |
| 6026 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 6027 #else | |
| 6028 // This used to conditionally jump to forward_exception however it is | |
| 6029 // possible if we relocate that the branch will not reach. So we must jump | |
| 6030 // around so we can always reach | |
| 6031 | |
| 6032 Label ok; | |
| 6033 jcc(Assembler::equal, ok); | |
| 6034 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 6035 bind(ok); | |
| 6036 #endif // LP64 | |
| 6037 } | |
| 6038 | |
| 6039 // get oop result if there is one and reset the value in the thread | |
| 6040 if (oop_result->is_valid()) { | |
| 6041 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6042 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
| 304 | 6043 verify_oop(oop_result, "broken oop in call_VM_base"); |
| 6044 } | |
| 6045 } | |
| 6046 | |
| 6047 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 6048 | |
| 6049 // Calculate the value for last_Java_sp | |
| 6050 // somewhat subtle. call_VM does an intermediate call | |
| 6051 // which places a return address on the stack just under the | |
| 6052 // stack pointer as the user finsihed with it. This allows | |
| 6053 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 6054 // On 32bit we then have to push additional args on the stack to accomplish | |
| 6055 // the actual requested call. On 64bit call_VM only can use register args | |
| 6056 // so the only extra space is the return address that call_VM created. | |
| 6057 // This hopefully explains the calculations here. | |
| 6058 | |
| 6059 #ifdef _LP64 | |
| 6060 // We've pushed one address, correct last_Java_sp | |
| 6061 lea(rax, Address(rsp, wordSize)); | |
| 6062 #else | |
| 6063 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 6064 #endif // LP64 | |
| 6065 | |
| 6066 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 6067 | |
| 6068 } | |
| 6069 | |
| 6070 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 6071 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 6072 } | |
| 6073 | |
| 6074 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 6075 pass_arg0(this, arg_0); | |
| 6076 call_VM_leaf(entry_point, 1); | |
| 6077 } | |
| 6078 | |
| 6079 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 6080 | |
| 6081 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6082 pass_arg1(this, arg_1); | |
| 6083 pass_arg0(this, arg_0); | |
| 6084 call_VM_leaf(entry_point, 2); | |
| 6085 } | |
| 6086 | |
| 6087 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 6088 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 6089 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6090 pass_arg2(this, arg_2); | |
| 6091 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6092 pass_arg1(this, arg_1); | |
| 6093 pass_arg0(this, arg_0); | |
| 6094 call_VM_leaf(entry_point, 3); | |
| 6095 } | |
| 6096 | |
|
3336
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6097 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6098 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6099 MacroAssembler::call_VM_leaf_base(entry_point, 1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6100 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6101 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6102 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6103 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6104 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6105 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6106 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6107 MacroAssembler::call_VM_leaf_base(entry_point, 2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6108 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6109 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6110 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6111 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6112 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6113 pass_arg2(this, arg_2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6114 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6115 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6116 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6117 MacroAssembler::call_VM_leaf_base(entry_point, 3); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6118 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6119 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6120 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6121 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6122 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6123 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6124 pass_arg3(this, arg_3); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6125 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6126 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6127 pass_arg2(this, arg_2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6128 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6129 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6130 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6131 MacroAssembler::call_VM_leaf_base(entry_point, 4); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6132 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6133 |
| 304 | 6134 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { |
| 6135 } | |
| 6136 | |
| 6137 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 6138 } | |
| 6139 | |
| 6140 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 6141 if (reachable(src1)) { | |
| 6142 cmpl(as_Address(src1), imm); | |
| 6143 } else { | |
| 6144 lea(rscratch1, src1); | |
| 6145 cmpl(Address(rscratch1, 0), imm); | |
| 6146 } | |
| 6147 } | |
| 6148 | |
| 6149 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 6150 assert(!src2.is_lval(), "use cmpptr"); | |
| 6151 if (reachable(src2)) { | |
| 6152 cmpl(src1, as_Address(src2)); | |
| 6153 } else { | |
| 6154 lea(rscratch1, src2); | |
| 6155 cmpl(src1, Address(rscratch1, 0)); | |
| 6156 } | |
| 6157 } | |
| 6158 | |
| 6159 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 6160 Assembler::cmpl(src1, imm); | |
| 6161 } | |
| 6162 | |
| 6163 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 6164 Assembler::cmpl(src1, src2); | |
| 6165 } | |
| 6166 | |
| 6167 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6168 ucomisd(opr1, opr2); | |
| 6169 | |
| 6170 Label L; | |
| 6171 if (unordered_is_less) { | |
| 6172 movl(dst, -1); | |
| 6173 jcc(Assembler::parity, L); | |
| 6174 jcc(Assembler::below , L); | |
| 6175 movl(dst, 0); | |
| 6176 jcc(Assembler::equal , L); | |
| 6177 increment(dst); | |
| 6178 } else { // unordered is greater | |
| 6179 movl(dst, 1); | |
| 6180 jcc(Assembler::parity, L); | |
| 6181 jcc(Assembler::above , L); | |
| 6182 movl(dst, 0); | |
| 6183 jcc(Assembler::equal , L); | |
| 6184 decrementl(dst); | |
| 6185 } | |
| 6186 bind(L); | |
| 6187 } | |
| 6188 | |
| 6189 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6190 ucomiss(opr1, opr2); | |
| 6191 | |
| 6192 Label L; | |
| 6193 if (unordered_is_less) { | |
| 6194 movl(dst, -1); | |
| 6195 jcc(Assembler::parity, L); | |
| 6196 jcc(Assembler::below , L); | |
| 6197 movl(dst, 0); | |
| 6198 jcc(Assembler::equal , L); | |
| 6199 increment(dst); | |
| 6200 } else { // unordered is greater | |
| 6201 movl(dst, 1); | |
| 6202 jcc(Assembler::parity, L); | |
| 6203 jcc(Assembler::above , L); | |
| 6204 movl(dst, 0); | |
| 6205 jcc(Assembler::equal , L); | |
| 6206 decrementl(dst); | |
| 6207 } | |
| 6208 bind(L); | |
| 6209 } | |
| 6210 | |
| 6211 | |
| 6212 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 6213 if (reachable(src1)) { | |
| 6214 cmpb(as_Address(src1), imm); | |
| 6215 } else { | |
| 6216 lea(rscratch1, src1); | |
| 6217 cmpb(Address(rscratch1, 0), imm); | |
| 6218 } | |
| 6219 } | |
| 6220 | |
| 6221 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 6222 #ifdef _LP64 | |
| 6223 if (src2.is_lval()) { | |
| 6224 movptr(rscratch1, src2); | |
| 6225 Assembler::cmpq(src1, rscratch1); | |
| 6226 } else if (reachable(src2)) { | |
| 6227 cmpq(src1, as_Address(src2)); | |
| 6228 } else { | |
| 6229 lea(rscratch1, src2); | |
| 6230 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 6231 } | |
| 6232 #else | |
| 6233 if (src2.is_lval()) { | |
| 6234 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6235 } else { | |
| 6236 cmpl(src1, as_Address(src2)); | |
| 6237 } | |
| 6238 #endif // _LP64 | |
| 6239 } | |
| 6240 | |
| 6241 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 6242 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 6243 #ifdef _LP64 | |
| 6244 // moves src2's literal address | |
| 6245 movptr(rscratch1, src2); | |
| 6246 Assembler::cmpq(src1, rscratch1); | |
| 6247 #else | |
| 6248 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6249 #endif // _LP64 | |
| 6250 } | |
| 6251 | |
| 6252 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 6253 if (reachable(adr)) { | |
| 6254 if (os::is_MP()) | |
| 6255 lock(); | |
| 6256 cmpxchgptr(reg, as_Address(adr)); | |
| 6257 } else { | |
| 6258 lea(rscratch1, adr); | |
| 6259 if (os::is_MP()) | |
| 6260 lock(); | |
| 6261 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 6262 } | |
| 6263 } | |
| 6264 | |
| 6265 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 6266 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 6267 } | |
| 6268 | |
| 6269 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6270 if (reachable(src)) { |
| 6271 comisd(dst, as_Address(src)); | |
| 6272 } else { | |
| 6273 lea(rscratch1, src); | |
| 6274 comisd(dst, Address(rscratch1, 0)); | |
| 6275 } | |
| 304 | 6276 } |
| 6277 | |
| 6278 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6279 if (reachable(src)) { |
| 6280 comiss(dst, as_Address(src)); | |
| 6281 } else { | |
| 6282 lea(rscratch1, src); | |
| 6283 comiss(dst, Address(rscratch1, 0)); | |
| 6284 } | |
| 304 | 6285 } |
| 6286 | |
| 6287 | |
| 6288 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 6289 Condition negated_cond = negate_condition(cond); | |
| 6290 Label L; | |
| 6291 jcc(negated_cond, L); | |
| 6292 atomic_incl(counter_addr); | |
| 6293 bind(L); | |
| 6294 } | |
| 6295 | |
| 6296 int MacroAssembler::corrected_idivl(Register reg) { | |
| 6297 // Full implementation of Java idiv and irem; checks for | |
| 6298 // special case as described in JVM spec., p.243 & p.271. | |
| 6299 // The function returns the (pc) offset of the idivl | |
| 6300 // instruction - may be needed for implicit exceptions. | |
| 6301 // | |
| 6302 // normal case special case | |
| 6303 // | |
| 6304 // input : rax,: dividend min_int | |
| 6305 // reg: divisor (may not be rax,/rdx) -1 | |
| 6306 // | |
| 6307 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 6308 // rdx: remainder (= rax, irem reg) 0 | |
| 6309 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 6310 const int min_int = 0x80000000; | |
| 6311 Label normal_case, special_case; | |
| 6312 | |
| 6313 // check for special case | |
| 6314 cmpl(rax, min_int); | |
| 6315 jcc(Assembler::notEqual, normal_case); | |
| 6316 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 6317 cmpl(reg, -1); | |
| 6318 jcc(Assembler::equal, special_case); | |
| 6319 | |
| 6320 // handle normal case | |
| 6321 bind(normal_case); | |
| 6322 cdql(); | |
| 6323 int idivl_offset = offset(); | |
| 6324 idivl(reg); | |
| 6325 | |
| 6326 // normal and special case exit | |
| 6327 bind(special_case); | |
| 6328 | |
| 6329 return idivl_offset; | |
| 6330 } | |
| 6331 | |
| 6332 | |
| 6333 | |
| 6334 void MacroAssembler::decrementl(Register reg, int value) { | |
| 6335 if (value == min_jint) {subl(reg, value) ; return; } | |
| 6336 if (value < 0) { incrementl(reg, -value); return; } | |
| 6337 if (value == 0) { ; return; } | |
| 6338 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 6339 /* else */ { subl(reg, value) ; return; } | |
| 6340 } | |
| 6341 | |
| 6342 void MacroAssembler::decrementl(Address dst, int value) { | |
| 6343 if (value == min_jint) {subl(dst, value) ; return; } | |
| 6344 if (value < 0) { incrementl(dst, -value); return; } | |
| 6345 if (value == 0) { ; return; } | |
| 6346 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 6347 /* else */ { subl(dst, value) ; return; } | |
| 6348 } | |
| 6349 | |
| 6350 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 6351 assert (shift_value > 0, "illegal shift value"); | |
| 6352 Label _is_positive; | |
| 6353 testl (reg, reg); | |
| 6354 jcc (Assembler::positive, _is_positive); | |
| 6355 int offset = (1 << shift_value) - 1 ; | |
| 6356 | |
| 6357 if (offset == 1) { | |
| 6358 incrementl(reg); | |
| 6359 } else { | |
| 6360 addl(reg, offset); | |
| 6361 } | |
| 6362 | |
| 6363 bind (_is_positive); | |
| 6364 sarl(reg, shift_value); | |
| 6365 } | |
| 6366 | |
| 6367 // !defined(COMPILER2) is because of stupid core builds | |
| 6368 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 6369 void MacroAssembler::empty_FPU_stack() { | |
| 6370 if (VM_Version::supports_mmx()) { | |
| 6371 emms(); | |
| 6372 } else { | |
| 6373 for (int i = 8; i-- > 0; ) ffree(i); | |
| 6374 } | |
| 6375 } | |
| 6376 #endif // !LP64 || C1 || !C2 | |
| 6377 | |
| 6378 | |
| 6379 // Defines obj, preserves var_size_in_bytes | |
| 6380 void MacroAssembler::eden_allocate(Register obj, | |
| 6381 Register var_size_in_bytes, | |
| 6382 int con_size_in_bytes, | |
| 6383 Register t1, | |
| 6384 Label& slow_case) { | |
| 6385 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 6386 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 6387 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 6388 jmp(slow_case); | |
| 304 | 6389 } else { |
| 362 | 6390 Register end = t1; |
| 6391 Label retry; | |
| 6392 bind(retry); | |
| 6393 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 6394 movptr(obj, heap_top); | |
| 6395 if (var_size_in_bytes == noreg) { | |
| 6396 lea(end, Address(obj, con_size_in_bytes)); | |
| 6397 } else { | |
| 6398 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6399 } | |
| 6400 // if end < obj then we wrapped around => object too long => slow case | |
| 6401 cmpptr(end, obj); | |
| 6402 jcc(Assembler::below, slow_case); | |
| 6403 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 6404 jcc(Assembler::above, slow_case); | |
| 6405 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 6406 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 6407 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 6408 locked_cmpxchgptr(end, heap_top); | |
| 6409 jcc(Assembler::notEqual, retry); | |
| 6410 } | |
| 304 | 6411 } |
| 6412 | |
| 6413 void MacroAssembler::enter() { | |
| 6414 push(rbp); | |
| 6415 mov(rbp, rsp); | |
| 6416 } | |
| 0 | 6417 |
| 6418 void MacroAssembler::fcmp(Register tmp) { | |
| 6419 fcmp(tmp, 1, true, true); | |
| 6420 } | |
| 6421 | |
| 6422 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 6423 assert(!pop_right || pop_left, "usage error"); | |
| 6424 if (VM_Version::supports_cmov()) { | |
| 6425 assert(tmp == noreg, "unneeded temp"); | |
| 6426 if (pop_left) { | |
| 6427 fucomip(index); | |
| 6428 } else { | |
| 6429 fucomi(index); | |
| 6430 } | |
| 6431 if (pop_right) { | |
| 6432 fpop(); | |
| 6433 } | |
| 6434 } else { | |
| 6435 assert(tmp != noreg, "need temp"); | |
| 6436 if (pop_left) { | |
| 6437 if (pop_right) { | |
| 6438 fcompp(); | |
| 6439 } else { | |
| 6440 fcomp(index); | |
| 6441 } | |
| 6442 } else { | |
| 6443 fcom(index); | |
| 6444 } | |
| 6445 // convert FPU condition into eflags condition via rax, | |
| 6446 save_rax(tmp); | |
| 6447 fwait(); fnstsw_ax(); | |
| 6448 sahf(); | |
| 6449 restore_rax(tmp); | |
| 6450 } | |
| 6451 // condition codes set as follows: | |
| 6452 // | |
| 6453 // CF (corresponds to C0) if x < y | |
| 6454 // PF (corresponds to C2) if unordered | |
| 6455 // ZF (corresponds to C3) if x = y | |
| 6456 } | |
| 6457 | |
| 6458 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 6459 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 6460 } | |
| 6461 | |
| 6462 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 6463 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 6464 Label L; | |
| 6465 if (unordered_is_less) { | |
| 6466 movl(dst, -1); | |
| 6467 jcc(Assembler::parity, L); | |
| 6468 jcc(Assembler::below , L); | |
| 6469 movl(dst, 0); | |
| 6470 jcc(Assembler::equal , L); | |
| 6471 increment(dst); | |
| 6472 } else { // unordered is greater | |
| 6473 movl(dst, 1); | |
| 6474 jcc(Assembler::parity, L); | |
| 6475 jcc(Assembler::above , L); | |
| 6476 movl(dst, 0); | |
| 6477 jcc(Assembler::equal , L); | |
| 304 | 6478 decrementl(dst); |
| 0 | 6479 } |
| 6480 bind(L); | |
| 6481 } | |
| 6482 | |
| 304 | 6483 void MacroAssembler::fld_d(AddressLiteral src) { |
| 6484 fld_d(as_Address(src)); | |
| 6485 } | |
| 6486 | |
| 6487 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 6488 fld_s(as_Address(src)); | |
| 6489 } | |
| 6490 | |
| 6491 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 6492 Assembler::fld_x(as_Address(src)); | |
| 6493 } | |
| 6494 | |
| 6495 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 6496 Assembler::fldcw(as_Address(src)); | |
| 6497 } | |
| 0 | 6498 |
| 6499 void MacroAssembler::fpop() { | |
| 6500 ffree(); | |
| 6501 fincstp(); | |
| 6502 } | |
| 6503 | |
| 304 | 6504 void MacroAssembler::fremr(Register tmp) { |
| 6505 save_rax(tmp); | |
| 6506 { Label L; | |
| 6507 bind(L); | |
| 6508 fprem(); | |
| 6509 fwait(); fnstsw_ax(); | |
| 6510 #ifdef _LP64 | |
| 6511 testl(rax, 0x400); | |
| 6512 jcc(Assembler::notEqual, L); | |
| 6513 #else | |
| 6514 sahf(); | |
| 6515 jcc(Assembler::parity, L); | |
| 6516 #endif // _LP64 | |
| 6517 } | |
| 6518 restore_rax(tmp); | |
| 6519 // Result is in ST0. | |
| 6520 // Note: fxch & fpop to get rid of ST1 | |
| 6521 // (otherwise FPU stack could overflow eventually) | |
| 6522 fxch(1); | |
| 6523 fpop(); | |
| 6524 } | |
| 6525 | |
| 6526 | |
| 6527 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 6528 if (reachable(dst)) { | |
| 6529 incrementl(as_Address(dst)); | |
| 0 | 6530 } else { |
| 304 | 6531 lea(rscratch1, dst); |
| 6532 incrementl(Address(rscratch1, 0)); | |
| 6533 } | |
| 6534 } | |
| 6535 | |
| 6536 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 6537 incrementl(as_Address(dst)); | |
| 6538 } | |
| 6539 | |
| 6540 void MacroAssembler::incrementl(Register reg, int value) { | |
| 6541 if (value == min_jint) {addl(reg, value) ; return; } | |
| 6542 if (value < 0) { decrementl(reg, -value); return; } | |
| 6543 if (value == 0) { ; return; } | |
| 6544 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 6545 /* else */ { addl(reg, value) ; return; } | |
| 6546 } | |
| 6547 | |
| 6548 void MacroAssembler::incrementl(Address dst, int value) { | |
| 6549 if (value == min_jint) {addl(dst, value) ; return; } | |
| 6550 if (value < 0) { decrementl(dst, -value); return; } | |
| 6551 if (value == 0) { ; return; } | |
| 6552 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 6553 /* else */ { addl(dst, value) ; return; } | |
| 6554 } | |
| 6555 | |
| 6556 void MacroAssembler::jump(AddressLiteral dst) { | |
| 6557 if (reachable(dst)) { | |
| 6558 jmp_literal(dst.target(), dst.rspec()); | |
| 6559 } else { | |
| 6560 lea(rscratch1, dst); | |
| 6561 jmp(rscratch1); | |
| 6562 } | |
| 6563 } | |
| 6564 | |
| 6565 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 6566 if (reachable(dst)) { | |
| 6567 InstructionMark im(this); | |
| 6568 relocate(dst.reloc()); | |
| 6569 const int short_size = 2; | |
| 6570 const int long_size = 6; | |
| 6571 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 6572 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 6573 // 0111 tttn #8-bit disp | |
| 6574 emit_byte(0x70 | cc); | |
| 6575 emit_byte((offs - short_size) & 0xFF); | |
| 6576 } else { | |
| 6577 // 0000 1111 1000 tttn #32-bit disp | |
| 6578 emit_byte(0x0F); | |
| 6579 emit_byte(0x80 | cc); | |
| 6580 emit_long(offs - long_size); | |
| 6581 } | |
| 0 | 6582 } else { |
| 304 | 6583 #ifdef ASSERT |
| 6584 warning("reversing conditional branch"); | |
| 6585 #endif /* ASSERT */ | |
| 6586 Label skip; | |
| 6587 jccb(reverse[cc], skip); | |
| 6588 lea(rscratch1, dst); | |
| 6589 Assembler::jmp(rscratch1); | |
| 6590 bind(skip); | |
| 6591 } | |
| 6592 } | |
| 6593 | |
| 6594 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 6595 if (reachable(src)) { | |
| 6596 Assembler::ldmxcsr(as_Address(src)); | |
| 6597 } else { | |
| 6598 lea(rscratch1, src); | |
| 6599 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 6600 } | |
| 6601 } | |
| 6602 | |
| 6603 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 6604 int off; | |
| 6605 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6606 off = offset(); | |
| 6607 movsbl(dst, src); // movsxb | |
| 6608 } else { | |
| 6609 off = load_unsigned_byte(dst, src); | |
| 6610 shll(dst, 24); | |
| 6611 sarl(dst, 24); | |
| 6612 } | |
| 6613 return off; | |
| 6614 } | |
| 6615 | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6616 // Note: load_signed_short used to be called load_signed_word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6617 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6618 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
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6619 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
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|
6620 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 6621 int off; |
| 6622 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6623 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 6624 // version but this is what 64bit has always done. This seems to imply | |
| 6625 // that users are only using 32bits worth. | |
| 6626 off = offset(); | |
| 6627 movswl(dst, src); // movsxw | |
| 6628 } else { | |
|
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|
6629 off = load_unsigned_short(dst, src); |
| 304 | 6630 shll(dst, 16); |
| 6631 sarl(dst, 16); | |
| 6632 } | |
| 6633 return off; | |
| 6634 } | |
| 6635 | |
| 6636 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 6637 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 6638 // and "3.9 Partial Register Penalties", p. 22). | |
| 6639 int off; | |
| 6640 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 6641 off = offset(); | |
| 6642 movzbl(dst, src); // movzxb | |
| 6643 } else { | |
| 6644 xorl(dst, dst); | |
| 6645 off = offset(); | |
| 6646 movb(dst, src); | |
| 6647 } | |
| 6648 return off; | |
| 6649 } | |
| 6650 | |
|
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|
6651 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
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6652 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 6653 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 6654 // and "3.9 Partial Register Penalties", p. 22). | |
| 6655 int off; | |
| 6656 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 6657 off = offset(); | |
| 6658 movzwl(dst, src); // movzxw | |
| 6659 } else { | |
| 6660 xorl(dst, dst); | |
| 6661 off = offset(); | |
| 6662 movw(dst, src); | |
| 6663 } | |
| 6664 return off; | |
| 6665 } | |
| 6666 | |
|
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|
6667 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { |
| 1503 | 6668 switch (size_in_bytes) { |
|
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|
6669 #ifndef _LP64 |
|
2258
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|
6670 case 8: |
|
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|
6671 assert(dst2 != noreg, "second dest register required"); |
|
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|
6672 movl(dst, src); |
|
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|
6673 movl(dst2, src.plus_disp(BytesPerInt)); |
|
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|
6674 break; |
|
622
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|
6675 #else |
|
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|
6676 case 8: movq(dst, src); break; |
|
622
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|
6677 #endif |
|
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|
6678 case 4: movl(dst, src); break; |
|
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|
6679 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; |
|
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|
6680 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; |
|
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|
6681 default: ShouldNotReachHere(); |
|
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|
6682 } |
|
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|
6683 } |
|
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|
6684 |
|
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|
6685 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { |
|
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|
6686 switch (size_in_bytes) { |
|
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|
6687 #ifndef _LP64 |
|
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|
6688 case 8: |
|
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|
6689 assert(src2 != noreg, "second source register required"); |
|
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|
6690 movl(dst, src); |
|
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|
6691 movl(dst.plus_disp(BytesPerInt), src2); |
|
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|
6692 break; |
|
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|
6693 #else |
|
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diff
changeset
|
6694 case 8: movq(dst, src); break; |
|
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|
6695 #endif |
|
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twisti
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diff
changeset
|
6696 case 4: movl(dst, src); break; |
|
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diff
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|
6697 case 2: movw(dst, src); break; |
|
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diff
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|
6698 case 1: movb(dst, src); break; |
|
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|
6699 default: ShouldNotReachHere(); |
|
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|
6700 } |
|
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|
6701 } |
|
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|
6702 |
| 304 | 6703 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 6704 if (reachable(dst)) { | |
| 6705 movl(as_Address(dst), src); | |
| 6706 } else { | |
| 6707 lea(rscratch1, dst); | |
| 6708 movl(Address(rscratch1, 0), src); | |
| 6709 } | |
| 6710 } | |
| 6711 | |
| 6712 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 6713 if (reachable(src)) { | |
| 6714 movl(dst, as_Address(src)); | |
| 6715 } else { | |
| 6716 lea(rscratch1, src); | |
| 6717 movl(dst, Address(rscratch1, 0)); | |
| 6718 } | |
| 0 | 6719 } |
| 6720 | |
| 6721 // C++ bool manipulation | |
| 6722 | |
| 6723 void MacroAssembler::movbool(Register dst, Address src) { | |
| 6724 if(sizeof(bool) == 1) | |
| 6725 movb(dst, src); | |
| 6726 else if(sizeof(bool) == 2) | |
| 6727 movw(dst, src); | |
| 6728 else if(sizeof(bool) == 4) | |
| 6729 movl(dst, src); | |
| 6730 else | |
| 6731 // unsupported | |
| 6732 ShouldNotReachHere(); | |
| 6733 } | |
| 6734 | |
| 6735 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 6736 if(sizeof(bool) == 1) | |
| 6737 movb(dst, (int) boolconst); | |
| 6738 else if(sizeof(bool) == 2) | |
| 6739 movw(dst, (int) boolconst); | |
| 6740 else if(sizeof(bool) == 4) | |
| 6741 movl(dst, (int) boolconst); | |
| 6742 else | |
| 6743 // unsupported | |
| 6744 ShouldNotReachHere(); | |
| 6745 } | |
| 6746 | |
| 6747 void MacroAssembler::movbool(Address dst, Register src) { | |
| 6748 if(sizeof(bool) == 1) | |
| 6749 movb(dst, src); | |
| 6750 else if(sizeof(bool) == 2) | |
| 6751 movw(dst, src); | |
| 6752 else if(sizeof(bool) == 4) | |
| 6753 movl(dst, src); | |
| 6754 else | |
| 6755 // unsupported | |
| 6756 ShouldNotReachHere(); | |
| 6757 } | |
| 6758 | |
| 304 | 6759 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 6760 movb(as_Address(dst), src); | |
| 6761 } | |
| 6762 | |
| 6763 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
| 6764 if (reachable(src)) { | |
| 6765 if (UseXmmLoadAndClearUpper) { | |
| 6766 movsd (dst, as_Address(src)); | |
| 6767 } else { | |
| 6768 movlpd(dst, as_Address(src)); | |
| 6769 } | |
| 6770 } else { | |
| 6771 lea(rscratch1, src); | |
| 6772 if (UseXmmLoadAndClearUpper) { | |
| 6773 movsd (dst, Address(rscratch1, 0)); | |
| 6774 } else { | |
| 6775 movlpd(dst, Address(rscratch1, 0)); | |
| 6776 } | |
| 6777 } | |
| 6778 } | |
| 6779 | |
| 6780 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 6781 if (reachable(src)) { | |
| 6782 movss(dst, as_Address(src)); | |
| 6783 } else { | |
| 6784 lea(rscratch1, src); | |
| 6785 movss(dst, Address(rscratch1, 0)); | |
| 6786 } | |
| 6787 } | |
| 6788 | |
| 6789 void MacroAssembler::movptr(Register dst, Register src) { | |
| 6790 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6791 } | |
| 6792 | |
| 6793 void MacroAssembler::movptr(Register dst, Address src) { | |
| 6794 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6795 } | |
| 6796 | |
| 6797 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 6798 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 6799 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6800 } | |
| 6801 | |
| 6802 void MacroAssembler::movptr(Address dst, Register src) { | |
| 6803 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6804 } | |
| 6805 | |
| 6806 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
| 6807 if (reachable(src)) { | |
| 6808 movss(dst, as_Address(src)); | |
| 6809 } else { | |
| 6810 lea(rscratch1, src); | |
| 6811 movss(dst, Address(rscratch1, 0)); | |
| 6812 } | |
| 6813 } | |
| 6814 | |
| 6815 void MacroAssembler::null_check(Register reg, int offset) { | |
| 6816 if (needs_explicit_null_check(offset)) { | |
| 6817 // provoke OS NULL exception if reg = NULL by | |
| 6818 // accessing M[reg] w/o changing any (non-CC) registers | |
| 6819 // NOTE: cmpl is plenty here to provoke a segv | |
| 6820 cmpptr(rax, Address(reg, 0)); | |
| 6821 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 6822 // may be shorter code (however, this version of | |
| 6823 // testl needs to be implemented first) | |
| 6824 } else { | |
| 6825 // nothing to do, (later) access of M[reg + offset] | |
| 6826 // will provoke OS NULL exception if reg = NULL | |
| 6827 } | |
| 6828 } | |
| 6829 | |
| 6830 void MacroAssembler::os_breakpoint() { | |
| 6831 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 6832 // (e.g., MSVC can't call ps() otherwise) | |
| 6833 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 6834 } | |
| 6835 | |
| 6836 void MacroAssembler::pop_CPU_state() { | |
| 6837 pop_FPU_state(); | |
| 6838 pop_IU_state(); | |
| 6839 } | |
| 6840 | |
| 6841 void MacroAssembler::pop_FPU_state() { | |
| 6842 NOT_LP64(frstor(Address(rsp, 0));) | |
| 6843 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 6844 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6845 } | |
| 6846 | |
| 6847 void MacroAssembler::pop_IU_state() { | |
| 6848 popa(); | |
| 6849 LP64_ONLY(addq(rsp, 8)); | |
| 6850 popf(); | |
| 6851 } | |
| 6852 | |
| 6853 // Save Integer and Float state | |
| 6854 // Warning: Stack must be 16 byte aligned (64bit) | |
| 6855 void MacroAssembler::push_CPU_state() { | |
| 6856 push_IU_state(); | |
| 6857 push_FPU_state(); | |
| 6858 } | |
| 6859 | |
| 6860 void MacroAssembler::push_FPU_state() { | |
| 6861 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6862 #ifndef _LP64 | |
| 6863 fnsave(Address(rsp, 0)); | |
| 6864 fwait(); | |
| 6865 #else | |
| 6866 fxsave(Address(rsp, 0)); | |
| 6867 #endif // LP64 | |
| 6868 } | |
| 6869 | |
| 6870 void MacroAssembler::push_IU_state() { | |
| 6871 // Push flags first because pusha kills them | |
| 6872 pushf(); | |
| 6873 // Make sure rsp stays 16-byte aligned | |
| 6874 LP64_ONLY(subq(rsp, 8)); | |
| 6875 pusha(); | |
| 6876 } | |
| 6877 | |
| 6878 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 6879 // determine java_thread register | |
| 6880 if (!java_thread->is_valid()) { | |
| 6881 java_thread = rdi; | |
| 6882 get_thread(java_thread); | |
| 6883 } | |
| 6884 // we must set sp to zero to clear frame | |
|
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changeset
|
6885 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 6886 if (clear_fp) { |
|
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diff
changeset
|
6887 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 6888 } |
| 6889 | |
| 6890 if (clear_pc) | |
|
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|
6891 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 6892 |
| 6893 } | |
| 6894 | |
| 6895 void MacroAssembler::restore_rax(Register tmp) { | |
| 6896 if (tmp == noreg) pop(rax); | |
| 6897 else if (tmp != rax) mov(rax, tmp); | |
| 6898 } | |
| 6899 | |
| 6900 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 6901 addptr(reg, modulus - 1); | |
| 6902 andptr(reg, -modulus); | |
| 6903 } | |
| 6904 | |
| 6905 void MacroAssembler::save_rax(Register tmp) { | |
| 6906 if (tmp == noreg) push(rax); | |
| 6907 else if (tmp != rax) mov(tmp, rax); | |
| 6908 } | |
| 6909 | |
| 6910 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 6911 // We use the current thread pointer to calculate a thread specific | |
| 6912 // offset to write to within the page. This minimizes bus traffic | |
| 6913 // due to cache line collision. | |
| 6914 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 6915 movl(tmp, thread); | |
| 6916 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 6917 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 6918 | |
| 6919 Address index(noreg, tmp, Address::times_1); | |
| 6920 ExternalAddress page(os::get_memory_serialize_page()); | |
| 6921 | |
|
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|
6922 // Size of store must match masking code above |
|
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|
6923 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 6924 } |
| 6925 | |
| 6926 // Calls to C land | |
| 6927 // | |
| 6928 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 6929 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 6930 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 6931 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 6932 Register last_java_sp, | |
| 6933 Register last_java_fp, | |
| 6934 address last_java_pc) { | |
| 6935 // determine java_thread register | |
| 6936 if (!java_thread->is_valid()) { | |
| 6937 java_thread = rdi; | |
| 6938 get_thread(java_thread); | |
| 6939 } | |
| 6940 // determine last_java_sp register | |
| 6941 if (!last_java_sp->is_valid()) { | |
| 6942 last_java_sp = rsp; | |
| 6943 } | |
| 6944 | |
| 6945 // last_java_fp is optional | |
| 6946 | |
| 6947 if (last_java_fp->is_valid()) { | |
| 6948 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 6949 } | |
| 6950 | |
| 6951 // last_java_pc is optional | |
| 6952 | |
| 6953 if (last_java_pc != NULL) { | |
| 6954 lea(Address(java_thread, | |
| 6955 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 6956 InternalAddress(last_java_pc)); | |
| 6957 | |
| 6958 } | |
| 6959 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 6960 } | |
| 6961 | |
| 6962 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 6963 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 6964 } | |
| 6965 | |
| 6966 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 6967 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 6968 } | |
| 6969 | |
| 6970 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 6971 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 6972 movsbl(reg, reg); // movsxb | |
| 6973 } else { | |
| 6974 shll(reg, 24); | |
| 6975 sarl(reg, 24); | |
| 6976 } | |
| 6977 } | |
| 6978 | |
| 6979 void MacroAssembler::sign_extend_short(Register reg) { | |
| 6980 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6981 movswl(reg, reg); // movsxw | |
| 6982 } else { | |
| 6983 shll(reg, 16); | |
| 6984 sarl(reg, 16); | |
| 6985 } | |
| 6986 } | |
| 6987 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
6988 void MacroAssembler::testl(Register dst, AddressLiteral src) { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
6989 assert(reachable(src), "Address should be reachable"); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
6990 testl(dst, as_Address(src)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
6991 } |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
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diff
changeset
|
6992 |
| 362 | 6993 ////////////////////////////////////////////////////////////////////////////////// |
| 6994 #ifndef SERIALGC | |
| 6995 | |
| 6996 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
6997 Register pre_val, |
| 362 | 6998 Register thread, |
| 6999 Register tmp, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7000 bool tosca_live, |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7001 bool expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7002 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7003 // If expand_call is true then we expand the call_VM_leaf macro |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7004 // directly to skip generating the check by |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7005 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7006 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7007 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7008 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7009 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7010 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7011 Label done; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7012 Label runtime; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7013 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7014 assert(pre_val != noreg, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7015 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7016 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7017 assert_different_registers(obj, pre_val, tmp); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7018 assert(pre_val != rax, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7019 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7020 |
| 362 | 7021 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
| 7022 PtrQueue::byte_offset_of_active())); | |
| 7023 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 7024 PtrQueue::byte_offset_of_index())); | |
| 7025 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 7026 PtrQueue::byte_offset_of_buf())); | |
| 7027 | |
| 7028 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7029 // Is marking active? |
| 362 | 7030 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
| 7031 cmpl(in_progress, 0); | |
| 7032 } else { | |
| 7033 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 7034 cmpb(in_progress, 0); | |
| 7035 } | |
| 7036 jcc(Assembler::equal, done); | |
| 7037 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7038 // Do we need to load the previous value? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7039 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7040 load_heap_oop(pre_val, Address(obj, 0)); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7041 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7042 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7043 // Is the previous value null? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7044 cmpptr(pre_val, (int32_t) NULL_WORD); |
| 362 | 7045 jcc(Assembler::equal, done); |
| 7046 | |
| 7047 // Can we store original value in the thread's buffer? | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7048 // Is index == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7049 // (The index field is typed as size_t.) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7050 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7051 movptr(tmp, index); // tmp := *index_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7052 cmpptr(tmp, 0); // tmp == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7053 jcc(Assembler::equal, runtime); // If yes, goto runtime |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7054 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7055 subptr(tmp, wordSize); // tmp := tmp - wordSize |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7056 movptr(index, tmp); // *index_adr := tmp |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7057 addptr(tmp, buffer); // tmp := tmp + *buffer_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7058 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7059 // Record the previous value |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7060 movptr(Address(tmp, 0), pre_val); |
| 362 | 7061 jmp(done); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7062 |
| 362 | 7063 bind(runtime); |
| 7064 // save the live input values | |
| 7065 if(tosca_live) push(rax); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7066 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7067 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7068 push(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7069 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7070 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7071 push(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7072 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7073 // Calling the runtime using the regular call_VM_leaf mechanism generates |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7074 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7075 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7076 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7077 // If we care generating the pre-barrier without a frame (e.g. in the |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7078 // intrinsified Reference.get() routine) then ebp might be pointing to |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7079 // the caller frame and so this check will most likely fail at runtime. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7080 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7081 // Expanding the call directly bypasses the generation of the check. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7082 // So when we do not have have a full interpreter frame on the stack |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7083 // expand_call should be passed true. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7084 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7085 NOT_LP64( push(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7086 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7087 if (expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7088 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7089 pass_arg1(this, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7090 pass_arg0(this, pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7091 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7092 } else { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7093 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7094 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7095 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7096 NOT_LP64( pop(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7097 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7098 // save the live input values |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7099 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7100 pop(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7101 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7102 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7103 pop(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7104 |
| 362 | 7105 if(tosca_live) pop(rax); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7106 |
| 362 | 7107 bind(done); |
| 7108 } | |
| 7109 | |
| 7110 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 7111 Register new_val, | |
| 7112 Register thread, | |
| 7113 Register tmp, | |
| 7114 Register tmp2) { | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7115 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7116 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7117 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7118 |
| 362 | 7119 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + |
| 7120 PtrQueue::byte_offset_of_index())); | |
| 7121 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 7122 PtrQueue::byte_offset_of_buf())); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7123 |
| 362 | 7124 BarrierSet* bs = Universe::heap()->barrier_set(); |
| 7125 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 7126 Label done; | |
| 7127 Label runtime; | |
| 7128 | |
| 7129 // Does store cross heap regions? | |
| 7130 | |
| 7131 movptr(tmp, store_addr); | |
| 7132 xorptr(tmp, new_val); | |
| 7133 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 7134 jcc(Assembler::equal, done); | |
| 7135 | |
| 7136 // crosses regions, storing NULL? | |
| 7137 | |
| 7138 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 7139 jcc(Assembler::equal, done); | |
| 7140 | |
| 7141 // storing region crossing non-NULL, is card already dirty? | |
| 7142 | |
| 7143 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 7144 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 7145 #ifdef _LP64 | |
| 7146 const Register card_addr = tmp; | |
| 7147 | |
| 7148 movq(card_addr, store_addr); | |
| 7149 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 7150 | |
| 7151 lea(tmp2, cardtable); | |
| 7152 | |
| 7153 // get the address of the card | |
| 7154 addq(card_addr, tmp2); | |
| 7155 #else | |
| 7156 const Register card_index = tmp; | |
| 7157 | |
| 7158 movl(card_index, store_addr); | |
| 7159 shrl(card_index, CardTableModRefBS::card_shift); | |
| 7160 | |
| 7161 Address index(noreg, card_index, Address::times_1); | |
| 7162 const Register card_addr = tmp; | |
| 7163 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 7164 #endif | |
| 7165 cmpb(Address(card_addr, 0), 0); | |
| 7166 jcc(Assembler::equal, done); | |
| 7167 | |
| 7168 // storing a region crossing, non-NULL oop, card is clean. | |
| 7169 // dirty card and log. | |
| 7170 | |
| 7171 movb(Address(card_addr, 0), 0); | |
| 7172 | |
| 7173 cmpl(queue_index, 0); | |
| 7174 jcc(Assembler::equal, runtime); | |
| 7175 subl(queue_index, wordSize); | |
| 7176 movptr(tmp2, buffer); | |
| 7177 #ifdef _LP64 | |
| 7178 movslq(rscratch1, queue_index); | |
| 7179 addq(tmp2, rscratch1); | |
| 7180 movq(Address(tmp2, 0), card_addr); | |
| 7181 #else | |
| 7182 addl(tmp2, queue_index); | |
| 7183 movl(Address(tmp2, 0), card_index); | |
| 7184 #endif | |
| 7185 jmp(done); | |
| 7186 | |
| 7187 bind(runtime); | |
| 7188 // save the live input values | |
| 7189 push(store_addr); | |
| 7190 push(new_val); | |
| 7191 #ifdef _LP64 | |
| 7192 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 7193 #else | |
| 7194 push(thread); | |
| 7195 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 7196 pop(thread); | |
| 7197 #endif | |
| 7198 pop(new_val); | |
| 7199 pop(store_addr); | |
| 7200 | |
| 7201 bind(done); | |
| 7202 } | |
| 7203 | |
| 7204 #endif // SERIALGC | |
| 7205 ////////////////////////////////////////////////////////////////////////////////// | |
| 7206 | |
| 7207 | |
| 304 | 7208 void MacroAssembler::store_check(Register obj) { |
| 7209 // Does a store check for the oop in register obj. The content of | |
| 7210 // register obj is destroyed afterwards. | |
| 7211 store_check_part_1(obj); | |
| 7212 store_check_part_2(obj); | |
| 7213 } | |
| 7214 | |
| 7215 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 7216 store_check(obj); | |
| 7217 } | |
| 7218 | |
| 7219 | |
| 7220 // split the store check operation so that other instructions can be scheduled inbetween | |
| 7221 void MacroAssembler::store_check_part_1(Register obj) { | |
| 7222 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7223 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7224 shrptr(obj, CardTableModRefBS::card_shift); | |
| 7225 } | |
| 7226 | |
| 7227 void MacroAssembler::store_check_part_2(Register obj) { | |
| 7228 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7229 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7230 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 7231 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 7232 | |
| 7233 // The calculation for byte_map_base is as follows: | |
| 7234 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 7235 // So this essentially converts an address to a displacement and | |
| 7236 // it will never need to be relocated. On 64bit however the value may be too | |
| 7237 // large for a 32bit displacement | |
| 7238 | |
| 7239 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 7240 if (is_simm32(disp)) { | |
| 7241 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 7242 movb(cardtable, 0); | |
| 7243 } else { | |
| 7244 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 7245 // displacement and done in a single instruction given favorable mapping and | |
| 7246 // a smarter version of as_Address. Worst case it is two instructions which | |
| 7247 // is no worse off then loading disp into a register and doing as a simple | |
| 7248 // Address() as above. | |
| 7249 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 7250 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 7251 // in some cases we'll get a single instruction version. | |
| 7252 | |
| 7253 ExternalAddress cardtable((address)disp); | |
| 7254 Address index(noreg, obj, Address::times_1); | |
| 7255 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 7256 } | |
| 7257 } | |
| 7258 | |
| 7259 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 7260 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 7261 } | |
| 7262 | |
| 7263 void MacroAssembler::subptr(Register dst, Register src) { | |
| 7264 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 7265 } | |
| 7266 | |
| 7267 // C++ bool manipulation | |
| 0 | 7268 void MacroAssembler::testbool(Register dst) { |
| 7269 if(sizeof(bool) == 1) | |
| 304 | 7270 testb(dst, 0xff); |
| 0 | 7271 else if(sizeof(bool) == 2) { |
| 7272 // testw implementation needed for two byte bools | |
| 7273 ShouldNotReachHere(); | |
| 7274 } else if(sizeof(bool) == 4) | |
| 7275 testl(dst, dst); | |
| 7276 else | |
| 7277 // unsupported | |
| 7278 ShouldNotReachHere(); | |
| 7279 } | |
| 7280 | |
| 304 | 7281 void MacroAssembler::testptr(Register dst, Register src) { |
| 7282 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 7283 } | |
| 7284 | |
| 7285 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 7286 void MacroAssembler::tlab_allocate(Register obj, | |
| 7287 Register var_size_in_bytes, | |
| 7288 int con_size_in_bytes, | |
| 7289 Register t1, | |
| 7290 Register t2, | |
| 7291 Label& slow_case) { | |
| 7292 assert_different_registers(obj, t1, t2); | |
| 7293 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 7294 Register end = t2; | |
| 7295 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 7296 | |
| 7297 verify_tlab(); | |
| 7298 | |
| 7299 NOT_LP64(get_thread(thread)); | |
| 7300 | |
| 7301 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 7302 if (var_size_in_bytes == noreg) { | |
| 7303 lea(end, Address(obj, con_size_in_bytes)); | |
| 7304 } else { | |
| 7305 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 7306 } | |
| 7307 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 7308 jcc(Assembler::above, slow_case); | |
| 7309 | |
| 7310 // update the tlab top pointer | |
| 7311 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 7312 | |
| 7313 // recover var_size_in_bytes if necessary | |
| 7314 if (var_size_in_bytes == end) { | |
| 7315 subptr(var_size_in_bytes, obj); | |
| 7316 } | |
| 7317 verify_tlab(); | |
| 7318 } | |
| 7319 | |
| 7320 // Preserves rbx, and rdx. | |
|
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7321 Register MacroAssembler::tlab_refill(Label& retry, |
|
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7322 Label& try_eden, |
|
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7323 Label& slow_case) { |
| 304 | 7324 Register top = rax; |
| 7325 Register t1 = rcx; | |
| 7326 Register t2 = rsi; | |
| 7327 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 7328 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 7329 Label do_refill, discard_tlab; | |
| 7330 | |
| 7331 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 7332 // No allocation in the shared eden. | |
| 7333 jmp(slow_case); | |
| 7334 } | |
| 7335 | |
| 7336 NOT_LP64(get_thread(thread_reg)); | |
| 7337 | |
| 7338 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7339 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7340 | |
| 7341 // calculate amount of free space | |
| 7342 subptr(t1, top); | |
| 7343 shrptr(t1, LogHeapWordSize); | |
| 7344 | |
| 7345 // Retain tlab and allocate object in shared space if | |
| 7346 // the amount free in the tlab is too large to discard. | |
| 7347 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 7348 jcc(Assembler::lessEqual, discard_tlab); | |
| 7349 | |
| 7350 // Retain | |
| 7351 // %%% yuck as movptr... | |
| 7352 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 7353 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 7354 if (TLABStats) { | |
| 7355 // increment number of slow_allocations | |
| 7356 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 7357 } | |
| 7358 jmp(try_eden); | |
| 7359 | |
| 7360 bind(discard_tlab); | |
| 7361 if (TLABStats) { | |
| 7362 // increment number of refills | |
| 7363 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 7364 // accumulate wastage -- t1 is amount free in tlab | |
| 7365 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 7366 } | |
| 7367 | |
| 7368 // if tlab is currently allocated (top or end != null) then | |
| 7369 // fill [top, end + alignment_reserve) with array object | |
|
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7370 testptr(top, top); |
| 304 | 7371 jcc(Assembler::zero, do_refill); |
| 7372 | |
| 7373 // set up the mark word | |
| 7374 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 7375 // set the length to the remaining space | |
| 7376 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 7377 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 7378 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 1690 | 7379 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
| 304 | 7380 // set klass to intArrayKlass |
| 7381 // dubious reloc why not an oop reloc? | |
|
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7382 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); |
| 304 | 7383 // store klass last. concurrent gcs assumes klass length is valid if |
| 7384 // klass field is not null. | |
| 7385 store_klass(top, t1); | |
| 7386 | |
|
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7387 movptr(t1, top); |
|
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7388 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
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7389 incr_allocated_bytes(thread_reg, t1, 0); |
|
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|
7390 |
| 304 | 7391 // refill the tlab with an eden allocation |
| 7392 bind(do_refill); | |
| 7393 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7394 shlptr(t1, LogHeapWordSize); | |
|
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7395 // allocate new tlab, address returned in top |
| 304 | 7396 eden_allocate(top, t1, 0, t2, slow_case); |
| 7397 | |
| 7398 // Check that t1 was preserved in eden_allocate. | |
| 7399 #ifdef ASSERT | |
| 7400 if (UseTLAB) { | |
| 7401 Label ok; | |
| 7402 Register tsize = rsi; | |
| 7403 assert_different_registers(tsize, thread_reg, t1); | |
| 7404 push(tsize); | |
| 7405 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7406 shlptr(tsize, LogHeapWordSize); | |
| 7407 cmpptr(t1, tsize); | |
| 7408 jcc(Assembler::equal, ok); | |
| 7409 stop("assert(t1 != tlab size)"); | |
| 7410 should_not_reach_here(); | |
| 7411 | |
| 7412 bind(ok); | |
| 7413 pop(tsize); | |
| 7414 } | |
| 7415 #endif | |
| 7416 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 7417 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 7418 addptr(top, t1); | |
| 7419 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 7420 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 7421 verify_tlab(); | |
| 7422 jmp(retry); | |
|
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7423 |
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7424 return thread_reg; // for use by caller |
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7425 } |
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7426 |
|
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|
7427 void MacroAssembler::incr_allocated_bytes(Register thread, |
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7428 Register var_size_in_bytes, |
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7429 int con_size_in_bytes, |
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7430 Register t1) { |
|
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7431 #ifdef _LP64 |
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|
7432 if (var_size_in_bytes->is_valid()) { |
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7433 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
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7434 } else { |
|
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7435 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
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|
7436 } |
|
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|
7437 #else |
|
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|
7438 if (!thread->is_valid()) { |
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|
7439 assert(t1->is_valid(), "need temp reg"); |
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7440 thread = t1; |
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|
7441 get_thread(thread); |
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|
7442 } |
|
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|
7443 |
|
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|
7444 if (var_size_in_bytes->is_valid()) { |
|
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7445 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
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|
7446 } else { |
|
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|
7447 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
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|
7448 } |
|
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|
7449 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); |
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|
7450 #endif |
| 304 | 7451 } |
| 7452 | |
| 7453 static const double pi_4 = 0.7853981633974483; | |
| 7454 | |
| 7455 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 7456 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 7457 // was attempted in this code; unfortunately it appears that the | |
| 7458 // switch to 80-bit precision and back causes this to be | |
| 7459 // unprofitable compared with simply performing a runtime call if | |
| 7460 // the argument is out of the (-pi/4, pi/4) range. | |
| 7461 | |
| 7462 Register tmp = noreg; | |
| 7463 if (!VM_Version::supports_cmov()) { | |
| 7464 // fcmp needs a temporary so preserve rbx, | |
| 7465 tmp = rbx; | |
| 7466 push(tmp); | |
| 7467 } | |
| 7468 | |
| 7469 Label slow_case, done; | |
| 7470 | |
|
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7471 ExternalAddress pi4_adr = (address)&pi_4; |
|
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|
7472 if (reachable(pi4_adr)) { |
|
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|
7473 // x ?<= pi/4 |
|
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|
7474 fld_d(pi4_adr); |
|
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|
7475 fld_s(1); // Stack: X PI/4 X |
|
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|
7476 fabs(); // Stack: |X| PI/4 X |
|
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|
7477 fcmp(tmp); |
|
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|
7478 jcc(Assembler::above, slow_case); |
|
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parents:
512
diff
changeset
|
7479 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7480 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7481 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7482 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7483 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7484 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7485 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7486 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7487 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7488 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7489 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7490 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7491 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7492 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7493 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7494 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7495 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7496 } |
| 304 | 7497 |
| 7498 // slow case: runtime call | |
| 7499 bind(slow_case); | |
| 7500 // Preserve registers across runtime call | |
| 7501 pusha(); | |
| 7502 int incoming_argument_and_return_value_offset = -1; | |
| 7503 if (num_fpu_regs_in_use > 1) { | |
| 7504 // Must preserve all other FPU regs (could alternatively convert | |
| 7505 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
| 7506 // FPU state, but can not trust C compiler) | |
| 7507 NEEDS_CLEANUP; | |
| 7508 // NOTE that in this case we also push the incoming argument to | |
| 7509 // the stack and restore it later; we also use this stack slot to | |
| 7510 // hold the return value from dsin or dcos. | |
| 7511 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7512 subptr(rsp, sizeof(jdouble)); | |
| 7513 fstp_d(Address(rsp, 0)); | |
| 7514 } | |
| 7515 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
| 7516 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7517 } | |
| 7518 subptr(rsp, sizeof(jdouble)); | |
| 7519 fstp_d(Address(rsp, 0)); | |
| 7520 #ifdef _LP64 | |
| 7521 movdbl(xmm0, Address(rsp, 0)); | |
| 7522 #endif // _LP64 | |
| 7523 | |
| 7524 // NOTE: we must not use call_VM_leaf here because that requires a | |
| 7525 // complete interpreter frame in debug mode -- same bug as 4387334 | |
| 7526 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
| 7527 // do proper 64bit abi | |
| 7528 | |
| 7529 NEEDS_CLEANUP; | |
| 7530 // Need to add stack banging before this runtime call if it needs to | |
| 7531 // be taken; however, there is no generic stack banging routine at | |
| 7532 // the MacroAssembler level | |
| 7533 switch(trig) { | |
| 7534 case 's': | |
| 7535 { | |
| 7536 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
| 7537 } | |
| 7538 break; | |
| 7539 case 'c': | |
| 7540 { | |
| 7541 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
| 7542 } | |
| 7543 break; | |
| 7544 case 't': | |
| 7545 { | |
| 7546 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
| 7547 } | |
| 7548 break; | |
| 7549 default: | |
| 7550 assert(false, "bad intrinsic"); | |
| 7551 break; | |
| 7552 } | |
| 7553 #ifdef _LP64 | |
| 7554 movsd(Address(rsp, 0), xmm0); | |
| 7555 fld_d(Address(rsp, 0)); | |
| 7556 #endif // _LP64 | |
| 7557 addptr(rsp, sizeof(jdouble)); | |
| 7558 if (num_fpu_regs_in_use > 1) { | |
| 7559 // Must save return value to stack and then restore entire FPU stack | |
| 7560 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7561 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7562 fld_d(Address(rsp, 0)); | |
| 7563 addptr(rsp, sizeof(jdouble)); | |
| 7564 } | |
| 7565 } | |
| 7566 popa(); | |
| 7567 | |
| 7568 // Come here with result in F-TOS | |
| 7569 bind(done); | |
| 7570 | |
| 7571 if (tmp != noreg) { | |
| 7572 pop(tmp); | |
| 7573 } | |
| 7574 } | |
| 7575 | |
| 7576 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7577 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7578 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7579 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7580 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7581 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7582 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7583 Register intf_klass, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7584 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7585 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7586 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7587 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7588 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7589 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7590 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7591 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7592 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7593 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7594 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7595 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7596 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7597 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7598 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7599 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7600 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7601 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7602 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7603 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7604 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7605 // Round up to align_object_offset boundary |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7606 // see code for instanceKlass::start_of_itable! |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7607 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7608 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7609 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7610 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7611 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7612 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7613 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7614 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7615 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7616 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7617 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7618 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7619 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7620 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7621 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7622 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7623 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7624 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7625 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7626 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7627 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7628 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7629 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7630 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7631 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7632 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7633 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7634 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7635 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7636 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7637 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7638 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7639 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7640 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7641 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7642 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7643 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7644 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7645 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7646 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7647 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7648 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7649 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7650 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7651 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7652 void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7653 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7654 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7655 Label& L_success) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7656 Label L_failure; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7657 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7658 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7659 bind(L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7660 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7661 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7662 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7663 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7664 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7665 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7666 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7667 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7668 Label* L_slow_path, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7669 RegisterOrConstant super_check_offset) { |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7670 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7671 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7672 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7673 assert_different_registers(sub_klass, super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7674 super_check_offset.as_register()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7675 } else if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7676 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7677 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7678 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7679 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7680 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7681 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7682 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7683 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7684 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7685 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7686 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7687 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7688 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7689 Klass::super_check_offset_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7690 Address super_check_offset_addr(super_klass, sco_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7691 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7692 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7693 // range of a jccb. If this routine grows larger, reconsider at |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7694 // least some of these. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7695 #define local_jcc(assembler_cond, label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7696 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7697 else jcc( assembler_cond, label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7698 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7699 // Hacked jmp, which may only be used just before L_fallthrough. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7700 #define final_jmp(label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7701 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7702 else jmp(label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7703 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7704 // If the pointers are equal, we are done (e.g., String[] elements). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7705 // This self-check enables sharing of secondary supertype arrays among |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7706 // non-primary types such as array-of-interface. Otherwise, each such |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7707 // type would need its own customized SSA. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7708 // We move this check to the front of the fast path because many |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7709 // type checks are in fact trivially successful in this manner, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7710 // so we get a nicely predicted branch right at the start of the check. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7711 cmpptr(sub_klass, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7712 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7713 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7714 // Check the supertype display: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7715 if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7716 // Positive movl does right thing on LP64. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7717 movl(temp_reg, super_check_offset_addr); |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7718 super_check_offset = RegisterOrConstant(temp_reg); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7719 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7720 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7721 cmpptr(super_klass, super_check_addr); // load displayed supertype |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7722 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7723 // This check has worked decisively for primary supers. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7724 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7725 // (Secondary supers are interfaces and very deeply nested subtypes.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7726 // This works in the same check above because of a tricky aliasing |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7727 // between the super_cache and the primary super display elements. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7728 // (The 'super_check_addr' can address either, as the case requires.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7729 // Note that the cache is updated below if it does not help us find |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7730 // what we need immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7731 // So if it was a primary super, we can just fail immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7732 // Otherwise, it's the slow path for us (no success at this point). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7733 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7734 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7735 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7736 cmpl(super_check_offset.as_register(), sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7737 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7738 local_jcc(Assembler::equal, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7739 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7740 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7741 final_jmp(*L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7742 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7743 } else if (super_check_offset.as_constant() == sc_offset) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7744 // Need a slow path; fast failure is impossible. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7745 if (L_slow_path == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7746 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7747 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7748 local_jcc(Assembler::notEqual, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7749 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7750 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7751 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7752 // No slow path; it's a fast decision. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7753 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7754 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7755 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7756 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7757 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7758 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7759 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7760 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7761 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7762 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7763 #undef local_jcc |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7764 #undef final_jmp |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7765 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7766 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7767 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7768 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7769 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7770 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7771 Register temp2_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7772 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7773 Label* L_failure, |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7774 bool set_cond_codes) { |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7775 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
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643
diff
changeset
|
7776 if (temp2_reg != noreg) |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7777 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
|
c517646eef23
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643
diff
changeset
|
7778 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
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643
diff
changeset
|
7779 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7780 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7781 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7782 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7783 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7784 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7785 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7786 // a couple of useful fields in sub_klass: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7787 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7788 Klass::secondary_supers_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7789 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7790 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7791 Address secondary_supers_addr(sub_klass, ss_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7792 Address super_cache_addr( sub_klass, sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7793 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7794 // Do a linear scan of the secondary super-klass chain. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7795 // This code is rarely used, so simplicity is a virtue here. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7796 // The repne_scan instruction uses fixed registers, which we must spill. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7797 // Don't worry too much about pre-existing connections with the input regs. |
|
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643
diff
changeset
|
7798 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7799 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7800 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7801 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7802 // Get super_klass value into rax (even if it was in rdi or rcx). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7803 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7804 if (super_klass != rax || UseCompressedOops) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7805 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7806 mov(rax, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7807 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7808 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7809 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7810 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7811 #ifndef PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7812 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7813 ExternalAddress pst_counter_addr((address) pst_counter); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7814 NOT_LP64( incrementl(pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7815 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7816 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7817 #endif //PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7818 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7819 // We will consult the secondary-super array. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7820 movptr(rdi, secondary_supers_addr); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7821 // Load the array length. (Positive movl does right thing on LP64.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7822 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7823 // Skip to start of data. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7824 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7825 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7826 // Scan RCX words at [RDI] for an occurrence of RAX. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7827 // Set NZ/Z based on last compare. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7828 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7829 // not change flags (only scas instruction which is repeated sets flags). |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7830 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7831 #ifdef _LP64 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7832 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7833 // and we store values in objArrays always encoded, thus we need to encode |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7834 // the value of rax before repne. Note that rax is dead after the repne. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7835 if (UseCompressedOops) { |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7836 encode_heap_oop_not_null(rax); // Changes flags. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7837 // The superclass is never null; it would be a basic system error if a null |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7838 // pointer were to sneak in here. Note that we have already loaded the |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7839 // Klass::super_check_offset from the super_klass in the fast path, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7840 // so if there is a null in that register, we are already in the afterlife. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7841 testl(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7842 repne_scanl(); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7843 } else |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7844 #endif // _LP64 |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7845 { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7846 testptr(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7847 repne_scan(); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7848 } |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7849 // Unspill the temp. registers: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7850 if (pushed_rdi) pop(rdi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7851 if (pushed_rcx) pop(rcx); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7852 if (pushed_rax) pop(rax); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7853 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7854 if (set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7855 // Special hack for the AD files: rdi is guaranteed non-zero. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7856 assert(!pushed_rdi, "rdi must be left non-NULL"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7857 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7858 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7859 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7860 if (L_failure == &L_fallthrough) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7861 jccb(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7862 else jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7863 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7864 // Success. Cache the super we found and proceed in triumph. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7865 movptr(super_cache_addr, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7866 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7867 if (L_success != &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7868 jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7869 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7870 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7871 #undef IS_A_TEMP |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7872 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7873 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7874 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7875 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7876 |
| 304 | 7877 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
| 7878 ucomisd(dst, as_Address(src)); | |
| 7879 } | |
| 7880 | |
| 7881 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
| 7882 ucomiss(dst, as_Address(src)); | |
| 7883 } | |
| 7884 | |
| 7885 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
| 7886 if (reachable(src)) { | |
| 7887 xorpd(dst, as_Address(src)); | |
| 7888 } else { | |
| 7889 lea(rscratch1, src); | |
| 7890 xorpd(dst, Address(rscratch1, 0)); | |
| 7891 } | |
| 7892 } | |
| 7893 | |
| 7894 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
| 7895 if (reachable(src)) { | |
| 7896 xorps(dst, as_Address(src)); | |
| 7897 } else { | |
| 7898 lea(rscratch1, src); | |
| 7899 xorps(dst, Address(rscratch1, 0)); | |
| 7900 } | |
| 7901 } | |
| 7902 | |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
7903 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
7904 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
7905 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
7906 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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diff
changeset
|
7907 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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2404
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changeset
|
7908 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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parents:
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diff
changeset
|
7909 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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parents:
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diff
changeset
|
7910 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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parents:
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changeset
|
7911 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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changeset
|
7912 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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changeset
|
7913 |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
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diff
changeset
|
7914 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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diff
changeset
|
7915 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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changeset
|
7916 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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|
7917 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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diff
changeset
|
7918 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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diff
changeset
|
7919 jccb(negate_condition(cc), L); |
|
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7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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diff
changeset
|
7920 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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diff
changeset
|
7921 bind(L); |
|
09f96c3ff1ad
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changeset
|
7922 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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changeset
|
7923 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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|
7924 |
| 0 | 7925 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 7926 if (!VerifyOops) return; | |
| 304 | 7927 |
| 0 | 7928 // Pass register number to verify_oop_subroutine |
| 7929 char* b = new char[strlen(s) + 50]; | |
| 7930 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
| 1583 | 7931 #ifdef _LP64 |
| 7932 push(rscratch1); // save r10, trashed by movptr() | |
| 7933 #endif | |
| 304 | 7934 push(rax); // save rax, |
| 7935 push(reg); // pass register argument | |
| 0 | 7936 ExternalAddress buffer((address) b); |
| 304 | 7937 // avoid using pushptr, as it modifies scratch registers |
| 7938 // and our contract is not to modify anything | |
| 7939 movptr(rax, buffer.addr()); | |
| 7940 push(rax); | |
| 0 | 7941 // call indirectly to solve generation ordering problem |
| 7942 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7943 call(rax); | |
| 1583 | 7944 // Caller pops the arguments (oop, message) and restores rax, r10 |
| 0 | 7945 } |
| 7946 | |
| 7947 | |
|
665
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6814659: separable cleanups and subroutines for 6655638
jrose
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647
diff
changeset
|
7948 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
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|
7949 Register tmp, |
|
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changeset
|
7950 int offset) { |
|
622
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|
7951 intptr_t value = *delayed_value_addr; |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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|
7952 if (value != 0) |
|
665
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|
7953 return RegisterOrConstant(value + offset); |
|
622
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|
7954 |
|
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|
7955 // load indirectly to solve generation ordering problem |
|
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|
7956 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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|
7957 |
|
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diff
changeset
|
7958 #ifdef ASSERT |
|
1793
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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changeset
|
7959 { Label L; |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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diff
changeset
|
7960 testptr(tmp, tmp); |
|
d257356e35f0
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jrose
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diff
changeset
|
7961 if (WizardMode) { |
|
d257356e35f0
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jrose
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changeset
|
7962 jcc(Assembler::notZero, L); |
|
d257356e35f0
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diff
changeset
|
7963 char* buf = new char[40]; |
|
d257356e35f0
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diff
changeset
|
7964 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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changeset
|
7965 stop(buf); |
|
d257356e35f0
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diff
changeset
|
7966 } else { |
|
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diff
changeset
|
7967 jccb(Assembler::notZero, L); |
|
d257356e35f0
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jrose
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diff
changeset
|
7968 hlt(); |
|
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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diff
changeset
|
7969 } |
|
d257356e35f0
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jrose
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diff
changeset
|
7970 bind(L); |
|
d257356e35f0
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diff
changeset
|
7971 } |
|
622
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|
7972 #endif |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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changeset
|
7973 |
|
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606
diff
changeset
|
7974 if (offset != 0) |
|
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diff
changeset
|
7975 addptr(tmp, offset); |
|
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|
7976 |
|
665
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|
7977 return RegisterOrConstant(tmp); |
|
622
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|
7978 } |
|
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changeset
|
7979 |
|
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|
7980 |
| 710 | 7981 // registers on entry: |
| 7982 // - rax ('check' register): required MethodType | |
| 7983 // - rcx: method handle | |
| 7984 // - rdx, rsi, or ?: killable temp | |
| 7985 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
| 7986 Register temp_reg, | |
| 7987 Label& wrong_method_type) { | |
|
2357
8033953d67ff
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2320
diff
changeset
|
7988 Address type_addr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)); |
| 710 | 7989 // compare method type against that of the receiver |
| 1846 | 7990 if (UseCompressedOops) { |
| 7991 load_heap_oop(temp_reg, type_addr); | |
| 7992 cmpptr(mtype_reg, temp_reg); | |
| 7993 } else { | |
| 7994 cmpptr(mtype_reg, type_addr); | |
| 7995 } | |
| 710 | 7996 jcc(Assembler::notEqual, wrong_method_type); |
| 7997 } | |
| 7998 | |
| 7999 | |
| 8000 // A method handle has a "vmslots" field which gives the size of its | |
| 8001 // argument list in JVM stack slots. This field is either located directly | |
| 8002 // in every method handle, or else is indirectly accessed through the | |
| 8003 // method handle's MethodType. This macro hides the distinction. | |
| 8004 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
| 8005 Register temp_reg) { | |
| 1503 | 8006 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
| 710 | 8007 // load mh.type.form.vmslots |
| 3938 | 8008 Register temp2_reg = vmslots_reg; |
| 8009 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg))); | |
| 8010 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg))); | |
| 8011 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); | |
| 710 | 8012 } |
| 8013 | |
| 8014 | |
| 8015 // registers on entry: | |
| 8016 // - rcx: method handle | |
| 8017 // - rdx: killable temp (interpreted only) | |
| 8018 // - rax: killable temp (compiled only) | |
| 8019 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
| 8020 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
| 8021 assert_different_registers(mh_reg, temp_reg); | |
| 8022 | |
| 8023 // pick out the interpreted side of the handler | |
| 1846 | 8024 // NOTE: vmentry is not an oop! |
|
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2320
diff
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|
8025 movptr(temp_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
| 710 | 8026 |
| 8027 // off we go... | |
| 8028 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
| 8029 | |
| 8030 // for the various stubs which take control at this point, | |
| 8031 // see MethodHandles::generate_method_handle_stub | |
| 8032 } | |
| 8033 | |
| 8034 | |
| 8035 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
| 8036 int extra_slot_offset) { | |
| 8037 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
| 1506 | 8038 int stackElementSize = Interpreter::stackElementSize; |
| 710 | 8039 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
| 8040 #ifdef ASSERT | |
| 8041 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
| 8042 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
| 8043 #endif | |
| 8044 Register scale_reg = noreg; | |
| 8045 Address::ScaleFactor scale_factor = Address::no_scale; | |
| 8046 if (arg_slot.is_constant()) { | |
| 8047 offset += arg_slot.as_constant() * stackElementSize; | |
| 8048 } else { | |
| 8049 scale_reg = arg_slot.as_register(); | |
| 8050 scale_factor = Address::times(stackElementSize); | |
| 8051 } | |
| 8052 offset += wordSize; // return PC is on stack | |
| 8053 return Address(rsp, scale_reg, scale_factor, offset); | |
| 8054 } | |
| 8055 | |
| 8056 | |
| 0 | 8057 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 8058 if (!VerifyOops) return; | |
| 304 | 8059 |
| 0 | 8060 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 8061 // Pass register number to verify_oop_subroutine | |
| 8062 char* b = new char[strlen(s) + 50]; | |
| 8063 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 8064 |
| 1583 | 8065 #ifdef _LP64 |
| 8066 push(rscratch1); // save r10, trashed by movptr() | |
| 8067 #endif | |
| 304 | 8068 push(rax); // save rax, |
| 0 | 8069 // addr may contain rsp so we will have to adjust it based on the push |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
8070 // we just did (and on 64 bit we do two pushes) |
| 304 | 8071 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 8072 // stores rax into addr which is backwards of what was intended. | |
| 0 | 8073 if (addr.uses(rsp)) { |
| 304 | 8074 lea(rax, addr); |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
8075 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); |
| 0 | 8076 } else { |
| 304 | 8077 pushptr(addr); |
| 8078 } | |
| 8079 | |
| 0 | 8080 ExternalAddress buffer((address) b); |
| 8081 // pass msg argument | |
| 304 | 8082 // avoid using pushptr, as it modifies scratch registers |
| 8083 // and our contract is not to modify anything | |
| 8084 movptr(rax, buffer.addr()); | |
| 8085 push(rax); | |
| 8086 | |
| 0 | 8087 // call indirectly to solve generation ordering problem |
| 8088 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 8089 call(rax); | |
| 1583 | 8090 // Caller pops the arguments (addr, message) and restores rax, r10. |
| 0 | 8091 } |
| 8092 | |
| 304 | 8093 void MacroAssembler::verify_tlab() { |
| 8094 #ifdef ASSERT | |
| 8095 if (UseTLAB && VerifyOops) { | |
| 8096 Label next, ok; | |
| 8097 Register t1 = rsi; | |
| 8098 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 8099 | |
| 8100 push(t1); | |
| 8101 NOT_LP64(push(thread_reg)); | |
| 8102 NOT_LP64(get_thread(thread_reg)); | |
| 8103 | |
| 8104 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 8105 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 8106 jcc(Assembler::aboveEqual, next); | |
| 8107 stop("assert(top >= start)"); | |
| 8108 should_not_reach_here(); | |
| 8109 | |
| 8110 bind(next); | |
| 8111 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 8112 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 8113 jcc(Assembler::aboveEqual, ok); | |
| 8114 stop("assert(top <= end)"); | |
| 8115 should_not_reach_here(); | |
| 8116 | |
| 8117 bind(ok); | |
| 8118 NOT_LP64(pop(thread_reg)); | |
| 8119 pop(t1); | |
| 8120 } | |
| 8121 #endif | |
| 8122 } | |
| 0 | 8123 |
| 8124 class ControlWord { | |
| 8125 public: | |
| 8126 int32_t _value; | |
| 8127 | |
| 8128 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 8129 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 8130 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 8131 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 8132 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 8133 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 8134 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 8135 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 8136 | |
| 8137 void print() const { | |
| 8138 // rounding control | |
| 8139 const char* rc; | |
| 8140 switch (rounding_control()) { | |
| 8141 case 0: rc = "round near"; break; | |
| 8142 case 1: rc = "round down"; break; | |
| 8143 case 2: rc = "round up "; break; | |
| 8144 case 3: rc = "chop "; break; | |
| 8145 }; | |
| 8146 // precision control | |
| 8147 const char* pc; | |
| 8148 switch (precision_control()) { | |
| 8149 case 0: pc = "24 bits "; break; | |
| 8150 case 1: pc = "reserved"; break; | |
| 8151 case 2: pc = "53 bits "; break; | |
| 8152 case 3: pc = "64 bits "; break; | |
| 8153 }; | |
| 8154 // flags | |
| 8155 char f[9]; | |
| 8156 f[0] = ' '; | |
| 8157 f[1] = ' '; | |
| 8158 f[2] = (precision ()) ? 'P' : 'p'; | |
| 8159 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 8160 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 8161 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 8162 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 8163 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 8164 f[8] = '\x0'; | |
| 8165 // output | |
| 8166 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 8167 } | |
| 8168 | |
| 8169 }; | |
| 8170 | |
| 8171 class StatusWord { | |
| 8172 public: | |
| 8173 int32_t _value; | |
| 8174 | |
| 8175 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 8176 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 8177 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 8178 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 8179 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 8180 int top() const { return (_value >> 11) & 7 ; } | |
| 8181 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 8182 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 8183 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 8184 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 8185 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 8186 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 8187 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 8188 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 8189 | |
| 8190 void print() const { | |
| 8191 // condition codes | |
| 8192 char c[5]; | |
| 8193 c[0] = (C3()) ? '3' : '-'; | |
| 8194 c[1] = (C2()) ? '2' : '-'; | |
| 8195 c[2] = (C1()) ? '1' : '-'; | |
| 8196 c[3] = (C0()) ? '0' : '-'; | |
| 8197 c[4] = '\x0'; | |
| 8198 // flags | |
| 8199 char f[9]; | |
| 8200 f[0] = (error_status()) ? 'E' : '-'; | |
| 8201 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 8202 f[2] = (precision ()) ? 'P' : '-'; | |
| 8203 f[3] = (underflow ()) ? 'U' : '-'; | |
| 8204 f[4] = (overflow ()) ? 'O' : '-'; | |
| 8205 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 8206 f[6] = (denormalized()) ? 'D' : '-'; | |
| 8207 f[7] = (invalid ()) ? 'I' : '-'; | |
| 8208 f[8] = '\x0'; | |
| 8209 // output | |
| 8210 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 8211 } | |
| 8212 | |
| 8213 }; | |
| 8214 | |
| 8215 class TagWord { | |
| 8216 public: | |
| 8217 int32_t _value; | |
| 8218 | |
| 8219 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 8220 | |
| 8221 void print() const { | |
| 8222 printf("%04x", _value & 0xFFFF); | |
| 8223 } | |
| 8224 | |
| 8225 }; | |
| 8226 | |
| 8227 class FPU_Register { | |
| 8228 public: | |
| 8229 int32_t _m0; | |
| 8230 int32_t _m1; | |
| 8231 int16_t _ex; | |
| 8232 | |
| 8233 bool is_indefinite() const { | |
| 8234 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 8235 } | |
| 8236 | |
| 8237 void print() const { | |
| 8238 char sign = (_ex < 0) ? '-' : '+'; | |
| 8239 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 8240 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 8241 }; | |
| 8242 | |
| 8243 }; | |
| 8244 | |
| 8245 class FPU_State { | |
| 8246 public: | |
| 8247 enum { | |
| 8248 register_size = 10, | |
| 8249 number_of_registers = 8, | |
| 8250 register_mask = 7 | |
| 8251 }; | |
| 8252 | |
| 8253 ControlWord _control_word; | |
| 8254 StatusWord _status_word; | |
| 8255 TagWord _tag_word; | |
| 8256 int32_t _error_offset; | |
| 8257 int32_t _error_selector; | |
| 8258 int32_t _data_offset; | |
| 8259 int32_t _data_selector; | |
| 8260 int8_t _register[register_size * number_of_registers]; | |
| 8261 | |
| 8262 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 8263 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 8264 | |
| 8265 const char* tag_as_string(int tag) const { | |
| 8266 switch (tag) { | |
| 8267 case 0: return "valid"; | |
| 8268 case 1: return "zero"; | |
| 8269 case 2: return "special"; | |
| 8270 case 3: return "empty"; | |
| 8271 } | |
|
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|
8272 ShouldNotReachHere(); |
| 0 | 8273 return NULL; |
| 8274 } | |
| 8275 | |
| 8276 void print() const { | |
| 8277 // print computation registers | |
| 8278 { int t = _status_word.top(); | |
| 8279 for (int i = 0; i < number_of_registers; i++) { | |
| 8280 int j = (i - t) & register_mask; | |
| 8281 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 8282 st(j)->print(); | |
| 8283 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 8284 } | |
| 8285 } | |
| 8286 printf("\n"); | |
| 8287 // print control registers | |
| 8288 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 8289 printf("stat = "); _status_word .print(); printf("\n"); | |
| 8290 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 8291 } | |
| 8292 | |
| 8293 }; | |
| 8294 | |
| 8295 class Flag_Register { | |
| 8296 public: | |
| 8297 int32_t _value; | |
| 8298 | |
| 8299 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 8300 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 8301 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 8302 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 8303 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 8304 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 8305 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 8306 | |
| 8307 void print() const { | |
| 8308 // flags | |
| 8309 char f[8]; | |
| 8310 f[0] = (overflow ()) ? 'O' : '-'; | |
| 8311 f[1] = (direction ()) ? 'D' : '-'; | |
| 8312 f[2] = (sign ()) ? 'S' : '-'; | |
| 8313 f[3] = (zero ()) ? 'Z' : '-'; | |
| 8314 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 8315 f[5] = (parity ()) ? 'P' : '-'; | |
| 8316 f[6] = (carry ()) ? 'C' : '-'; | |
| 8317 f[7] = '\x0'; | |
| 8318 // output | |
| 8319 printf("%08x flags = %s", _value, f); | |
| 8320 } | |
| 8321 | |
| 8322 }; | |
| 8323 | |
| 8324 class IU_Register { | |
| 8325 public: | |
| 8326 int32_t _value; | |
| 8327 | |
| 8328 void print() const { | |
| 8329 printf("%08x %11d", _value, _value); | |
| 8330 } | |
| 8331 | |
| 8332 }; | |
| 8333 | |
| 8334 class IU_State { | |
| 8335 public: | |
| 8336 Flag_Register _eflags; | |
| 8337 IU_Register _rdi; | |
| 8338 IU_Register _rsi; | |
| 8339 IU_Register _rbp; | |
| 8340 IU_Register _rsp; | |
| 8341 IU_Register _rbx; | |
| 8342 IU_Register _rdx; | |
| 8343 IU_Register _rcx; | |
| 8344 IU_Register _rax; | |
| 8345 | |
| 8346 void print() const { | |
| 8347 // computation registers | |
| 8348 printf("rax, = "); _rax.print(); printf("\n"); | |
| 8349 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 8350 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 8351 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 8352 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 8353 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 8354 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 8355 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 8356 printf("\n"); | |
| 8357 // control registers | |
| 8358 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 8359 } | |
| 8360 }; | |
| 8361 | |
| 8362 | |
| 8363 class CPU_State { | |
| 8364 public: | |
| 8365 FPU_State _fpu_state; | |
| 8366 IU_State _iu_state; | |
| 8367 | |
| 8368 void print() const { | |
| 8369 printf("--------------------------------------------------\n"); | |
| 8370 _iu_state .print(); | |
| 8371 printf("\n"); | |
| 8372 _fpu_state.print(); | |
| 8373 printf("--------------------------------------------------\n"); | |
| 8374 } | |
| 8375 | |
| 8376 }; | |
| 8377 | |
| 8378 | |
| 8379 static void _print_CPU_state(CPU_State* state) { | |
| 8380 state->print(); | |
| 8381 }; | |
| 8382 | |
| 8383 | |
| 8384 void MacroAssembler::print_CPU_state() { | |
| 8385 push_CPU_state(); | |
| 304 | 8386 push(rsp); // pass CPU state |
| 0 | 8387 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 8388 addptr(rsp, wordSize); // discard argument |
| 0 | 8389 pop_CPU_state(); |
| 8390 } | |
| 8391 | |
| 8392 | |
| 8393 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 8394 static int counter = 0; | |
| 8395 FPU_State* fs = &state->_fpu_state; | |
| 8396 counter++; | |
| 8397 // For leaf calls, only verify that the top few elements remain empty. | |
| 8398 // We only need 1 empty at the top for C2 code. | |
| 8399 if( stack_depth < 0 ) { | |
| 8400 if( fs->tag_for_st(7) != 3 ) { | |
| 8401 printf("FPR7 not empty\n"); | |
| 8402 state->print(); | |
| 8403 assert(false, "error"); | |
| 8404 return false; | |
| 8405 } | |
| 8406 return true; // All other stack states do not matter | |
| 8407 } | |
| 8408 | |
| 8409 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 8410 "bad FPU control word"); | |
| 8411 | |
| 8412 // compute stack depth | |
| 8413 int i = 0; | |
| 8414 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 8415 int d = i; | |
| 8416 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 8417 // verify findings | |
| 8418 if (i != FPU_State::number_of_registers) { | |
| 8419 // stack not contiguous | |
| 8420 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 8421 state->print(); | |
| 8422 assert(false, "error"); | |
| 8423 return false; | |
| 8424 } | |
| 8425 // check if computed stack depth corresponds to expected stack depth | |
| 8426 if (stack_depth < 0) { | |
| 8427 // expected stack depth is -stack_depth or less | |
| 8428 if (d > -stack_depth) { | |
| 8429 // too many elements on the stack | |
| 8430 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 8431 state->print(); | |
| 8432 assert(false, "error"); | |
| 8433 return false; | |
| 8434 } | |
| 8435 } else { | |
| 8436 // expected stack depth is stack_depth | |
| 8437 if (d != stack_depth) { | |
| 8438 // wrong stack depth | |
| 8439 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 8440 state->print(); | |
| 8441 assert(false, "error"); | |
| 8442 return false; | |
| 8443 } | |
| 8444 } | |
| 8445 // everything is cool | |
| 8446 return true; | |
| 8447 } | |
| 8448 | |
| 8449 | |
| 8450 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 8451 if (!VerifyFPU) return; | |
| 8452 push_CPU_state(); | |
| 304 | 8453 push(rsp); // pass CPU state |
| 0 | 8454 ExternalAddress msg((address) s); |
| 8455 // pass message string s | |
| 8456 pushptr(msg.addr()); | |
| 304 | 8457 push(stack_depth); // pass stack depth |
| 0 | 8458 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 8459 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 8460 // check for error |
| 8461 { Label L; | |
| 8462 testl(rax, rax); | |
| 8463 jcc(Assembler::notZero, L); | |
| 8464 int3(); // break if error condition | |
| 8465 bind(L); | |
| 8466 } | |
| 8467 pop_CPU_state(); | |
| 8468 } | |
| 8469 | |
| 304 | 8470 void MacroAssembler::load_klass(Register dst, Register src) { |
| 8471 #ifdef _LP64 | |
| 8472 if (UseCompressedOops) { | |
| 8473 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8474 decode_heap_oop_not_null(dst); | |
| 8475 } else | |
| 8476 #endif | |
| 8477 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8478 } | |
| 8479 | |
| 8480 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 8481 #ifdef _LP64 | |
| 8482 if (UseCompressedOops) { | |
|
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|
8483 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8484 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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|
8485 if (Universe::narrow_oop_shift() != 0) { |
|
1571
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|
8486 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
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|
8487 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
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|
8488 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
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|
8489 } else { |
|
2d127394260e
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|
8490 // OK to use shift since we don't need to preserve flags. |
|
2d127394260e
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|
8491 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
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|
8492 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
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|
8493 } |
|
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|
8494 } else { |
|
660978a2a31a
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|
8495 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
660978a2a31a
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|
8496 } |
| 304 | 8497 } else |
| 8498 #endif | |
|
642
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|
8499 { |
|
660978a2a31a
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|
8500 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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|
8501 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
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|
8502 } |
| 304 | 8503 } |
| 8504 | |
| 8505 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 8506 #ifdef _LP64 | |
| 8507 if (UseCompressedOops) { | |
| 8508 encode_heap_oop_not_null(src); | |
| 8509 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8510 } else | |
| 8511 #endif | |
| 8512 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8513 } | |
| 8514 | |
| 1846 | 8515 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
| 8516 #ifdef _LP64 | |
| 8517 if (UseCompressedOops) { | |
| 8518 movl(dst, src); | |
| 8519 decode_heap_oop(dst); | |
| 8520 } else | |
| 8521 #endif | |
| 8522 movptr(dst, src); | |
| 8523 } | |
| 8524 | |
|
2464
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diff
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|
8525 // Doesn't do verfication, generates fixed size code |
|
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|
8526 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { |
|
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|
8527 #ifdef _LP64 |
|
d86923d96dca
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|
8528 if (UseCompressedOops) { |
|
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|
8529 movl(dst, src); |
|
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|
8530 decode_heap_oop_not_null(dst); |
|
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|
8531 } else |
|
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|
8532 #endif |
|
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|
8533 movptr(dst, src); |
|
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|
8534 } |
|
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|
8535 |
| 1846 | 8536 void MacroAssembler::store_heap_oop(Address dst, Register src) { |
| 8537 #ifdef _LP64 | |
| 8538 if (UseCompressedOops) { | |
| 8539 assert(!dst.uses(src), "not enough registers"); | |
| 8540 encode_heap_oop(src); | |
| 8541 movl(dst, src); | |
| 8542 } else | |
| 8543 #endif | |
| 8544 movptr(dst, src); | |
| 8545 } | |
| 8546 | |
| 8547 // Used for storing NULLs. | |
| 8548 void MacroAssembler::store_heap_oop_null(Address dst) { | |
| 8549 #ifdef _LP64 | |
| 8550 if (UseCompressedOops) { | |
| 8551 movl(dst, (int32_t)NULL_WORD); | |
| 8552 } else { | |
| 8553 movslq(dst, (int32_t)NULL_WORD); | |
| 8554 } | |
| 8555 #else | |
| 8556 movl(dst, (int32_t)NULL_WORD); | |
| 8557 #endif | |
| 8558 } | |
| 8559 | |
| 304 | 8560 #ifdef _LP64 |
| 8561 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
| 8562 if (UseCompressedOops) { | |
| 8563 // Store to klass gap in destination | |
| 8564 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 8565 } | |
| 8566 } | |
| 8567 | |
|
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|
8568 #ifdef ASSERT |
|
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|
8569 void MacroAssembler::verify_heapbase(const char* msg) { |
|
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|
8570 assert (UseCompressedOops, "should be compressed"); |
|
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|
8571 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
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|
8572 if (CheckCompressedOops) { |
|
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|
8573 Label ok; |
|
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changeset
|
8574 push(rscratch1); // cmpptr trashes rscratch1 |
|
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changeset
|
8575 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
|
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|
8576 jcc(Assembler::equal, ok); |
|
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|
8577 stop(msg); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8578 bind(ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8579 pop(rscratch1); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8580 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8581 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8582 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8583 |
| 304 | 8584 // Algorithm must match oop.inline.hpp encode_heap_oop. |
| 8585 void MacroAssembler::encode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8586 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8587 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8588 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8589 verify_oop(r, "broken oop in encode_heap_oop"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8590 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8591 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8592 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8593 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
8594 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8595 return; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
8596 } |
| 304 | 8597 testq(r, r); |
| 8598 cmovq(Assembler::equal, r, r12_heapbase); | |
| 8599 subq(r, r12_heapbase); | |
| 8600 shrq(r, LogMinObjAlignmentInBytes); | |
| 8601 } | |
| 8602 | |
| 8603 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 0 | 8604 #ifdef ASSERT |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8605 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
| 304 | 8606 if (CheckCompressedOops) { |
| 0 | 8607 Label ok; |
| 304 | 8608 testq(r, r); |
| 8609 jcc(Assembler::notEqual, ok); | |
| 8610 stop("null oop passed to encode_heap_oop_not_null"); | |
| 0 | 8611 bind(ok); |
| 304 | 8612 } |
| 8613 #endif | |
| 8614 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
8615 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8616 subq(r, r12_heapbase); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8617 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8618 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8619 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8620 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
8621 } |
| 304 | 8622 } |
| 8623 | |
| 8624 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 8625 #ifdef ASSERT | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8626 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
| 304 | 8627 if (CheckCompressedOops) { |
| 8628 Label ok; | |
| 8629 testq(src, src); | |
| 8630 jcc(Assembler::notEqual, ok); | |
| 8631 stop("null oop passed to encode_heap_oop_not_null2"); | |
| 8632 bind(ok); | |
| 0 | 8633 } |
| 8634 #endif | |
| 304 | 8635 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 8636 if (dst != src) { | |
| 8637 movq(dst, src); | |
| 8638 } | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8639 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8640 subq(dst, r12_heapbase); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8641 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8642 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8643 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8644 shrq(dst, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8645 } |
| 304 | 8646 } |
| 8647 | |
| 8648 void MacroAssembler::decode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8649 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8650 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8651 #endif |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8652 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8653 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8654 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8655 shlq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8656 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8657 } else { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8658 Label done; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8659 shlq(r, LogMinObjAlignmentInBytes); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8660 jccb(Assembler::equal, done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8661 addq(r, r12_heapbase); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8662 bind(done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8663 } |
| 304 | 8664 verify_oop(r, "broken oop in decode_heap_oop"); |
| 8665 } | |
| 8666 | |
| 8667 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8668 // Note: it will change flags |
| 304 | 8669 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8670 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8671 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8672 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8673 // Also do not verify_oop as this is called by verify_oop. | |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8674 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8675 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8676 shlq(r, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8677 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8678 addq(r, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8679 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8680 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8681 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8682 } |
| 304 | 8683 } |
| 8684 | |
| 8685 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8686 // Note: it will change flags |
| 304 | 8687 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8688 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8689 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8690 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8691 // Also do not verify_oop as this is called by verify_oop. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8692 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8693 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8694 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8695 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8696 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8697 if (dst != src) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8698 movq(dst, src); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8699 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8700 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8701 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8702 addq(dst, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8703 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8704 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8705 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8706 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8707 if (dst != src) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8708 movq(dst, src); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8709 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8710 } |
| 304 | 8711 } |
| 8712 | |
| 8713 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8714 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8715 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8716 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8717 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8718 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8719 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8720 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8721 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8722 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8723 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8724 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8725 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
| 304 | 8726 int oop_index = oop_recorder()->find_index(obj); |
| 8727 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8728 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8729 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8730 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8731 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8732 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8733 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8734 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8735 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8736 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8737 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8738 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8739 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8740 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8741 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8742 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8743 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8744 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8745 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8746 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
| 304 | 8747 } |
| 8748 | |
| 8749 void MacroAssembler::reinit_heapbase() { | |
| 8750 if (UseCompressedOops) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8751 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
| 304 | 8752 } |
| 8753 } | |
| 8754 #endif // _LP64 | |
| 0 | 8755 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8756 // IndexOf for constant substrings with size >= 8 chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8757 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8758 void MacroAssembler::string_indexofC8(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8759 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8760 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8761 XMMRegister vec, Register tmp) { |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8762 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8763 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8764 // This method uses pcmpestri inxtruction with bound registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8765 // inputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8766 // xmm - substring |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8767 // rax - substring length (elements count) |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8768 // mem - scanned string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8769 // rdx - string length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8770 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8771 // outputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8772 // rcx - matched index in string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8773 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8774 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8775 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8776 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8777 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8778 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8779 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8780 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8781 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8782 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8783 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8784 // Load substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8785 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8786 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8787 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8788 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8789 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8790 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8791 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8792 // Reload substr for rescan, this code |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8793 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8794 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8795 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8796 negptr(cnt2); // Jumped here with negative cnt2, convert to positive |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8797 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8798 bind(RELOAD_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8799 // We came here after the beginning of the substring was |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8800 // matched but the rest of it was not so we need to search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8801 // again. Start from the next element after the previous match. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8802 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8803 // cnt2 is number of substring reminding elements and |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8804 // cnt1 is number of string reminding elements when cmp failed. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8805 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8806 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8807 addl(cnt1, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8808 movl(cnt2, int_cnt2); // Now restore cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8809 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8810 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8811 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8812 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8813 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8814 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8815 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8816 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8817 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8818 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8819 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8820 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8821 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8822 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8823 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8824 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8825 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8826 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8827 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8828 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8829 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8830 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8831 // Matched whole vector if first element matched (tmp(rcx) == 0). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8832 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8833 jccb(Assembler::overflow, RET_FOUND); // OF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8834 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8835 jccb(Assembler::overflow, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8836 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8837 // After pcmpestri tmp(rcx) contains matched element index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8838 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8839 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8840 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8841 // Make sure string is still long enough |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8842 subl(cnt1, tmp); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8843 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8844 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8845 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8846 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8847 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8848 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8849 // Left less then substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8850 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8851 bind(RET_NOT_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8852 movl(result, -1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8853 jmpb(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8854 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8855 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8856 // This code is optimized for the case when whole substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8857 // is matched if its head is matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
8858 bind(MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8859 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
8860 // Reload only string if does not match |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8861 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8862 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8863 Label CONT_SCAN_SUBSTR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8864 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8865 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8866 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
8867 negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8868 addptr(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8869 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8870 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8871 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8872 cmpl(cnt2, -8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8873 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
8874 // Back-up strings to avoid reading beyond substring: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8875 // cnt1 = cnt1 - cnt2 + 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
8876 addl(cnt1, cnt2); // cnt2 is negative |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8877 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8878 movl(cnt2, 8); negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8879 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8880 if (int_cnt2 < (int)G) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8881 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8882 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); |
|
41d4973cf100
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parents:
2262
diff
changeset
|
8883 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8884 // calculate index in register to avoid integer overflow (int_cnt2*2) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8885 movl(tmp, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8886 addptr(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8887 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8888 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8889 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8890 // Need to reload strings pointers if not matched whole vector |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8891 jccb(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8892 addptr(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8893 jccb(Assembler::negative, SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8894 // Fall through if found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8895 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8896 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8897 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8898 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8899 // Found result if we matched full small substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8900 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8901 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8902 shrl(result, 1); // index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8903 bind(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8904 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8905 } // string_indexofC8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8906 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8907 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8908 void MacroAssembler::string_indexof(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8909 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8910 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8911 XMMRegister vec, Register tmp) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8912 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8913 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8914 // int_cnt2 is length of small (< 8 chars) constant substring |
|
41d4973cf100
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kvn
parents:
2262
diff
changeset
|
8915 // or (-1) for non constant substring in which case its length |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8916 // is in cnt2 register. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8917 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8918 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8919 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
8920 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8921 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8922 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8923 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8924 // This method uses pcmpestri inxtruction with bound registers |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8925 // inputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8926 // xmm - substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8927 // rax - substring length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8928 // mem - scanned string |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8929 // rdx - string length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8930 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8931 // outputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8932 // rcx - matched index in string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8933 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8934 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8935 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8936 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8937 FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8938 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8939 { //======================================================== |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8940 // We don't know where these strings are located |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8941 // and we can't read beyond them. Load them through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8942 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8943 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8944 movptr(tmp, rsp); // save old SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8945 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8946 if (int_cnt2 > 0) { // small (< 8 chars) constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8947 if (int_cnt2 == 1) { // One char |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8948 load_unsigned_short(result, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8949 movdl(vec, result); // move 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8950 } else if (int_cnt2 == 2) { // Two chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8951 movdl(vec, Address(str2, 0)); // move 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8952 } else if (int_cnt2 == 4) { // Four chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8953 movq(vec, Address(str2, 0)); // move 64 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8954 } else { // cnt2 = { 3, 5, 6, 7 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8955 // Array header size is 12 bytes in 32-bit VM |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8956 // + 6 bytes for 3 chars == 18 bytes, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8957 // enough space to load vec and shift. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8958 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8959 movdqu(vec, Address(str2, (int_cnt2*2)-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8960 psrldq(vec, 16-(int_cnt2*2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8961 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8962 } else { // not constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8963 cmpl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8964 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8965 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8966 // We can read beyond string if srt+16 does not cross page boundary |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8967 // since heaps are aligned and mapped by pages. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8968 assert(os::vm_page_size() < (int)G, "default page should be small"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8969 movl(result, str2); // We need only low 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8970 andl(result, (os::vm_page_size()-1)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8971 cmpl(result, (os::vm_page_size()-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8972 jccb(Assembler::belowEqual, CHECK_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8973 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8974 // Move small strings to stack to allow load 16 bytes into vec. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8975 subptr(rsp, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8976 int stk_offset = wordSize-2; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8977 push(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8978 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8979 bind(COPY_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8980 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8981 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8982 decrement(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8983 jccb(Assembler::notZero, COPY_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8984 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8985 pop(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8986 movptr(str2, rsp); // New substring address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8987 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8988 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8989 bind(CHECK_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8990 cmpl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8991 jccb(Assembler::aboveEqual, BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8992 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8993 // Check cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8994 movl(result, str1); // We need only low 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8995 andl(result, (os::vm_page_size()-1)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8996 cmpl(result, (os::vm_page_size()-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8997 jccb(Assembler::belowEqual, BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
8998 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
8999 subptr(rsp, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9000 int stk_offset = -2; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9001 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9002 push(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9003 stk_offset += wordSize; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9004 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9005 movl(cnt2, cnt1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9006 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9007 bind(COPY_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9008 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9009 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9010 decrement(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9011 jccb(Assembler::notZero, COPY_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9012 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9013 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9014 pop(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9015 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9016 movptr(str1, rsp); // New string address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9017 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9018 bind(BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9019 // Load substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9020 if (int_cnt2 < 0) { // -1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9021 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9022 push(cnt2); // substr count |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9023 push(str2); // substr addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9024 push(str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9025 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9026 // Small (< 8 chars) constant substrings are loaded already. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9027 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9028 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9029 push(tmp); // original SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9030 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9031 } // Finished loading |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9032 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9033 //======================================================== |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9034 // Start search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9035 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9036 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9037 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9038 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9039 if (int_cnt2 < 0) { // Only for non constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9040 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9041 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9042 // SP saved at sp+0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9043 // String saved at sp+1*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9044 // Substr saved at sp+2*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9045 // Substr count saved at sp+3*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9046 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9047 // Reload substr for rescan, this code |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9048 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9049 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9050 movptr(str2, Address(rsp, 2*wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9051 movl(cnt2, Address(rsp, 3*wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9052 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9053 // We came here after the beginning of the substring was |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9054 // matched but the rest of it was not so we need to search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9055 // again. Start from the next element after the previous match. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9056 subptr(str1, result); // Restore counter |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9057 shrl(str1, 1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9058 addl(cnt1, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9059 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9060 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9061 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9062 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9063 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9064 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9065 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9066 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9067 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9068 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9069 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9070 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9071 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9072 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9073 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9074 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9075 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9076 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9077 bind(ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9078 cmpl(cnt1, 8); // Do not read beyond string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9079 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9080 // Back-up string to avoid reading beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9081 lea(result, Address(result, cnt1, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9082 movl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9083 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9084 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9085 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9086 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9087 // After pcmpestri tmp(rcx) contains matched element index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9088 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9089 // Make sure string is still long enough |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9090 subl(cnt1, tmp); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9091 cmpl(cnt1, cnt2); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9092 jccb(Assembler::greaterEqual, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9093 // Left less then substring. |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9094 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9095 bind(RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9096 movl(result, -1); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9097 jmpb(CLEANUP); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9098 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9099 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9100 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9101 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9102 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9103 if (int_cnt2 > 0) { // Constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9104 // Repeat search for small substring (< 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9105 // from new point without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9106 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9107 cmpl(tmp, 8-int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9108 jccb(Assembler::greater, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9109 // Fall through if matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9110 } else { // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9111 assert(int_cnt2 == -1, "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9112 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9113 addl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9114 // Found result if we matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9115 cmpl(tmp, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9116 jccb(Assembler::lessEqual, RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9117 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9118 // Repeat search for small substring (<= 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9119 // from new point 'str1' without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9120 cmpl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9121 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9122 jccb(Assembler::lessEqual, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9123 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9124 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9125 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9126 movptr(str1, result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9127 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9128 cmpl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9129 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9130 jccb(Assembler::equal, CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9131 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9132 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9133 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9134 // Need to reload strings pointers if not matched whole vector |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9135 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9136 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9137 bind(CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9138 subl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9139 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9140 addptr(str1, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9141 addptr(str2, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9142 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9143 cmpl(cnt2, 8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9144 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9145 // Back-up strings to avoid reading beyond substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9146 lea(str2, Address(str2, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9147 lea(str1, Address(str1, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9148 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9149 movl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9150 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9151 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9152 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9153 jmpb(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9154 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9155 bind(RET_FOUND_LONG); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9156 movptr(str1, Address(rsp, wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9157 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9158 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9159 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9160 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9161 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9162 shrl(result, 1); // index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9163 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9164 bind(CLEANUP); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9165 pop(rsp); // restore SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9166 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9167 } // string_indexof |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9168 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9169 // Compare strings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9170 void MacroAssembler::string_compare(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9171 Register cnt1, Register cnt2, Register result, |
| 2262 | 9172 XMMRegister vec1) { |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9173 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9174 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9175 // Compute the minimum of the string lengths and the |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9176 // difference of the string lengths (stack). |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9177 // Do the conditional move stuff |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9178 movl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9179 subl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9180 push(cnt1); |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9181 cmov32(Assembler::lessEqual, cnt2, result); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9182 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9183 // Is the minimum length zero? |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9184 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9185 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9186 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9187 // Load first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9188 load_unsigned_short(result, Address(str1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9189 load_unsigned_short(cnt1, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9190 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9191 // Compare first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9192 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9193 jcc(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9194 decrementl(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9195 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9196 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9197 { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9198 // Check after comparing first character to see if strings are equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9199 Label LSkip2; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9200 // Check if the strings start at same location |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9201 cmpptr(str1, str2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9202 jccb(Assembler::notEqual, LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9203 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9204 // Check if the length difference is zero (from stack) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9205 cmpl(Address(rsp, 0), 0x0); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9206 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9207 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9208 // Strings might not be equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9209 bind(LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9210 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9211 |
| 2262 | 9212 Address::ScaleFactor scale = Address::times_2; |
| 9213 int stride = 8; | |
| 9214 | |
| 9215 // Advance to next element | |
| 9216 addptr(str1, 16/stride); | |
| 9217 addptr(str2, 16/stride); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9218 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9219 if (UseSSE42Intrinsics) { |
| 2262 | 9220 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
| 9221 int pcmpmask = 0x19; | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9222 // Setup to compare 16-byte vectors |
| 2262 | 9223 movl(result, cnt2); |
| 9224 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9225 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9226 |
| 2262 | 9227 lea(str1, Address(str1, result, scale)); |
| 9228 lea(str2, Address(str2, result, scale)); | |
| 9229 negptr(result); | |
| 9230 | |
| 9231 // pcmpestri | |
| 9232 // inputs: | |
| 9233 // vec1- substring | |
| 9234 // rax - negative string length (elements count) | |
| 9235 // mem - scaned string | |
| 9236 // rdx - string length (elements count) | |
| 9237 // pcmpmask - cmp mode: 11000 (string compare with negated result) | |
| 9238 // + 00 (unsigned bytes) or + 01 (unsigned shorts) | |
| 9239 // outputs: | |
| 9240 // rcx - first mismatched element index | |
| 9241 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); | |
| 9242 | |
| 9243 bind(COMPARE_WIDE_VECTORS); | |
| 9244 movdqu(vec1, Address(str1, result, scale)); | |
| 9245 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 9246 // After pcmpestri cnt1(rcx) contains mismatched element index | |
| 9247 | |
| 9248 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 | |
| 9249 addptr(result, stride); | |
| 9250 subptr(cnt2, stride); | |
| 9251 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
| 9252 | |
| 9253 // compare wide vectors tail | |
| 9254 testl(result, result); | |
| 9255 jccb(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 9256 | |
| 9257 movl(cnt2, stride); | |
| 9258 movl(result, stride); | |
| 9259 negptr(result); | |
| 9260 movdqu(vec1, Address(str1, result, scale)); | |
| 9261 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 9262 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9263 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9264 // Mismatched characters in the vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9265 bind(VECTOR_NOT_EQUAL); |
| 2262 | 9266 addptr(result, cnt1); |
| 9267 movptr(cnt2, result); | |
| 9268 load_unsigned_short(result, Address(str1, cnt2, scale)); | |
| 9269 load_unsigned_short(cnt1, Address(str2, cnt2, scale)); | |
| 9270 subl(result, cnt1); | |
| 9271 jmpb(POP_LABEL); | |
| 9272 | |
| 9273 bind(COMPARE_TAIL); // limit is zero | |
| 9274 movl(cnt2, result); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9275 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9276 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9277 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9278 // Shift str2 and str1 to the end of the arrays, negate min |
| 2262 | 9279 lea(str1, Address(str1, cnt2, scale, 0)); |
| 9280 lea(str2, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9281 negptr(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9282 |
| 2262 | 9283 // Compare the rest of the elements |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9284 bind(WHILE_HEAD_LABEL); |
| 2262 | 9285 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); |
| 9286 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9287 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9288 jccb(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9289 increment(cnt2); |
| 2262 | 9290 jccb(Assembler::notZero, WHILE_HEAD_LABEL); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9291 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9292 // Strings are equal up to min length. Return the length difference. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9293 bind(LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9294 pop(result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9295 jmpb(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9296 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9297 // Discard the stored length difference |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9298 bind(POP_LABEL); |
| 2262 | 9299 pop(cnt1); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9300 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9301 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9302 bind(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9303 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9304 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9305 // Compare char[] arrays aligned to 4 bytes or substrings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9306 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9307 Register limit, Register result, Register chr, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9308 XMMRegister vec1, XMMRegister vec2) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9309 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9310 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9311 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9312 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9313 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9314 // Check the input args |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9315 cmpptr(ary1, ary2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9316 jcc(Assembler::equal, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9317 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9318 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9319 // Need additional checks for arrays_equals. |
| 1016 | 9320 testptr(ary1, ary1); |
| 9321 jcc(Assembler::zero, FALSE_LABEL); | |
| 9322 testptr(ary2, ary2); | |
| 9323 jcc(Assembler::zero, FALSE_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9324 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9325 // Check the lengths |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9326 movl(limit, Address(ary1, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9327 cmpl(limit, Address(ary2, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9328 jcc(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9329 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9330 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9331 // count == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9332 testl(limit, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9333 jcc(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9334 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9335 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9336 // Load array address |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9337 lea(ary1, Address(ary1, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9338 lea(ary2, Address(ary2, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9339 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9340 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9341 shll(limit, 1); // byte count != 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9342 movl(result, limit); // copy |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9343 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9344 if (UseSSE42Intrinsics) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9345 // With SSE4.2, use double quad vector compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9346 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
| 2262 | 9347 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9348 // Compare 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9349 andl(result, 0x0000000e); // tail count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9350 andl(limit, 0xfffffff0); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9351 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9352 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9353 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9354 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9355 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9356 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9357 bind(COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9358 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9359 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9360 pxor(vec1, vec2); |
| 2262 | 9361 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9362 ptest(vec1, vec1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9363 jccb(Assembler::notZero, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9364 addptr(limit, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9365 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9366 |
| 2262 | 9367 testl(result, result); |
| 9368 jccb(Assembler::zero, TRUE_LABEL); | |
| 9369 | |
| 9370 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); | |
| 9371 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); | |
| 9372 pxor(vec1, vec2); | |
| 9373 | |
| 9374 ptest(vec1, vec1); | |
| 9375 jccb(Assembler::notZero, FALSE_LABEL); | |
| 9376 jmpb(TRUE_LABEL); | |
| 9377 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9378 bind(COMPARE_TAIL); // limit is zero |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9379 movl(limit, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9380 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9381 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9382 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9383 // Compare 4-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9384 andl(limit, 0xfffffffc); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9385 jccb(Assembler::zero, COMPARE_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9386 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9387 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9388 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9389 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9390 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9391 bind(COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9392 movl(chr, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9393 cmpl(chr, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9394 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9395 addptr(limit, 4); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9396 jcc(Assembler::notZero, COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9397 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9398 // Compare trailing char (final 2 bytes), if any |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9399 bind(COMPARE_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9400 testl(result, 0x2); // tail char |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9401 jccb(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9402 load_unsigned_short(chr, Address(ary1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9403 load_unsigned_short(limit, Address(ary2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9404 cmpl(chr, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9405 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9406 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9407 bind(TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
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9408 movl(result, 1); // return true |
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9409 jmpb(DONE); |
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9410 |
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9411 bind(FALSE_LABEL); |
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9412 xorl(result, result); // return false |
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9413 |
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9414 // That's it |
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9415 bind(DONE); |
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9416 } |
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9417 |
| 1763 | 9418 #ifdef PRODUCT |
| 9419 #define BLOCK_COMMENT(str) /* nothing */ | |
| 9420 #else | |
| 9421 #define BLOCK_COMMENT(str) block_comment(str) | |
| 9422 #endif | |
| 9423 | |
| 9424 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
| 9425 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
| 9426 Register to, Register value, Register count, | |
| 9427 Register rtmp, XMMRegister xtmp) { | |
| 9428 assert_different_registers(to, value, count, rtmp); | |
| 9429 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
| 9430 Label L_fill_2_bytes, L_fill_4_bytes; | |
| 9431 | |
| 9432 int shift = -1; | |
| 9433 switch (t) { | |
| 9434 case T_BYTE: | |
| 9435 shift = 2; | |
| 9436 break; | |
| 9437 case T_SHORT: | |
| 9438 shift = 1; | |
| 9439 break; | |
| 9440 case T_INT: | |
| 9441 shift = 0; | |
| 9442 break; | |
| 9443 default: ShouldNotReachHere(); | |
| 9444 } | |
| 9445 | |
| 9446 if (t == T_BYTE) { | |
| 9447 andl(value, 0xff); | |
| 9448 movl(rtmp, value); | |
| 9449 shll(rtmp, 8); | |
| 9450 orl(value, rtmp); | |
| 9451 } | |
| 9452 if (t == T_SHORT) { | |
| 9453 andl(value, 0xffff); | |
| 9454 } | |
| 9455 if (t == T_BYTE || t == T_SHORT) { | |
| 9456 movl(rtmp, value); | |
| 9457 shll(rtmp, 16); | |
| 9458 orl(value, rtmp); | |
| 9459 } | |
| 9460 | |
| 9461 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
| 9462 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
| 9463 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
| 9464 // align source address at 4 bytes address boundary | |
| 9465 if (t == T_BYTE) { | |
| 9466 // One byte misalignment happens only for byte arrays | |
| 9467 testptr(to, 1); | |
| 9468 jccb(Assembler::zero, L_skip_align1); | |
| 9469 movb(Address(to, 0), value); | |
| 9470 increment(to); | |
| 9471 decrement(count); | |
| 9472 BIND(L_skip_align1); | |
| 9473 } | |
| 9474 // Two bytes misalignment happens only for byte and short (char) arrays | |
| 9475 testptr(to, 2); | |
| 9476 jccb(Assembler::zero, L_skip_align2); | |
| 9477 movw(Address(to, 0), value); | |
| 9478 addptr(to, 2); | |
| 9479 subl(count, 1<<(shift-1)); | |
| 9480 BIND(L_skip_align2); | |
| 9481 } | |
| 9482 if (UseSSE < 2) { | |
| 9483 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 9484 // Fill 32-byte chunks | |
| 9485 subl(count, 8 << shift); | |
| 9486 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 9487 align(16); | |
| 9488 | |
| 9489 BIND(L_fill_32_bytes_loop); | |
| 9490 | |
| 9491 for (int i = 0; i < 32; i += 4) { | |
| 9492 movl(Address(to, i), value); | |
| 9493 } | |
| 9494 | |
| 9495 addptr(to, 32); | |
| 9496 subl(count, 8 << shift); | |
| 9497 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 9498 BIND(L_check_fill_8_bytes); | |
| 9499 addl(count, 8 << shift); | |
| 9500 jccb(Assembler::zero, L_exit); | |
| 9501 jmpb(L_fill_8_bytes); | |
| 9502 | |
| 9503 // | |
| 9504 // length is too short, just fill qwords | |
| 9505 // | |
| 9506 BIND(L_fill_8_bytes_loop); | |
| 9507 movl(Address(to, 0), value); | |
| 9508 movl(Address(to, 4), value); | |
| 9509 addptr(to, 8); | |
| 9510 BIND(L_fill_8_bytes); | |
| 9511 subl(count, 1 << (shift + 1)); | |
| 9512 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9513 // fall through to fill 4 bytes | |
| 9514 } else { | |
| 9515 Label L_fill_32_bytes; | |
| 9516 if (!UseUnalignedLoadStores) { | |
| 9517 // align to 8 bytes, we know we are 4 byte aligned to start | |
| 9518 testptr(to, 4); | |
| 9519 jccb(Assembler::zero, L_fill_32_bytes); | |
| 9520 movl(Address(to, 0), value); | |
| 9521 addptr(to, 4); | |
| 9522 subl(count, 1<<shift); | |
| 9523 } | |
| 9524 BIND(L_fill_32_bytes); | |
| 9525 { | |
| 9526 assert( UseSSE >= 2, "supported cpu only" ); | |
| 9527 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 9528 // Fill 32-byte chunks | |
| 9529 movdl(xtmp, value); | |
| 9530 pshufd(xtmp, xtmp, 0); | |
| 9531 | |
| 9532 subl(count, 8 << shift); | |
| 9533 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 9534 align(16); | |
| 9535 | |
| 9536 BIND(L_fill_32_bytes_loop); | |
| 9537 | |
| 9538 if (UseUnalignedLoadStores) { | |
| 9539 movdqu(Address(to, 0), xtmp); | |
| 9540 movdqu(Address(to, 16), xtmp); | |
| 9541 } else { | |
| 9542 movq(Address(to, 0), xtmp); | |
| 9543 movq(Address(to, 8), xtmp); | |
| 9544 movq(Address(to, 16), xtmp); | |
| 9545 movq(Address(to, 24), xtmp); | |
| 9546 } | |
| 9547 | |
| 9548 addptr(to, 32); | |
| 9549 subl(count, 8 << shift); | |
| 9550 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 9551 BIND(L_check_fill_8_bytes); | |
| 9552 addl(count, 8 << shift); | |
| 9553 jccb(Assembler::zero, L_exit); | |
| 9554 jmpb(L_fill_8_bytes); | |
| 9555 | |
| 9556 // | |
| 9557 // length is too short, just fill qwords | |
| 9558 // | |
| 9559 BIND(L_fill_8_bytes_loop); | |
| 9560 movq(Address(to, 0), xtmp); | |
| 9561 addptr(to, 8); | |
| 9562 BIND(L_fill_8_bytes); | |
| 9563 subl(count, 1 << (shift + 1)); | |
| 9564 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9565 } | |
| 9566 } | |
| 9567 // fill trailing 4 bytes | |
| 9568 BIND(L_fill_4_bytes); | |
| 9569 testl(count, 1<<shift); | |
| 9570 jccb(Assembler::zero, L_fill_2_bytes); | |
| 9571 movl(Address(to, 0), value); | |
| 9572 if (t == T_BYTE || t == T_SHORT) { | |
| 9573 addptr(to, 4); | |
| 9574 BIND(L_fill_2_bytes); | |
| 9575 // fill trailing 2 bytes | |
| 9576 testl(count, 1<<(shift-1)); | |
| 9577 jccb(Assembler::zero, L_fill_byte); | |
| 9578 movw(Address(to, 0), value); | |
| 9579 if (t == T_BYTE) { | |
| 9580 addptr(to, 2); | |
| 9581 BIND(L_fill_byte); | |
| 9582 // fill trailing byte | |
| 9583 testl(count, 1); | |
| 9584 jccb(Assembler::zero, L_exit); | |
| 9585 movb(Address(to, 0), value); | |
| 9586 } else { | |
| 9587 BIND(L_fill_byte); | |
| 9588 } | |
| 9589 } else { | |
| 9590 BIND(L_fill_2_bytes); | |
| 9591 } | |
| 9592 BIND(L_exit); | |
| 9593 } | |
| 9594 #undef BIND | |
| 9595 #undef BLOCK_COMMENT | |
| 9596 | |
| 9597 | |
| 0 | 9598 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
| 9599 switch (cond) { | |
| 9600 // Note some conditions are synonyms for others | |
| 9601 case Assembler::zero: return Assembler::notZero; | |
| 9602 case Assembler::notZero: return Assembler::zero; | |
| 9603 case Assembler::less: return Assembler::greaterEqual; | |
| 9604 case Assembler::lessEqual: return Assembler::greater; | |
| 9605 case Assembler::greater: return Assembler::lessEqual; | |
| 9606 case Assembler::greaterEqual: return Assembler::less; | |
| 9607 case Assembler::below: return Assembler::aboveEqual; | |
| 9608 case Assembler::belowEqual: return Assembler::above; | |
| 9609 case Assembler::above: return Assembler::belowEqual; | |
| 9610 case Assembler::aboveEqual: return Assembler::below; | |
| 9611 case Assembler::overflow: return Assembler::noOverflow; | |
| 9612 case Assembler::noOverflow: return Assembler::overflow; | |
| 9613 case Assembler::negative: return Assembler::positive; | |
| 9614 case Assembler::positive: return Assembler::negative; | |
| 9615 case Assembler::parity: return Assembler::noParity; | |
| 9616 case Assembler::noParity: return Assembler::parity; | |
| 9617 } | |
| 9618 ShouldNotReachHere(); return Assembler::overflow; | |
| 9619 } | |
| 9620 | |
| 9621 SkipIfEqual::SkipIfEqual( | |
| 9622 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 9623 _masm = masm; | |
| 9624 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 9625 _masm->jcc(Assembler::equal, _label); | |
| 9626 } | |
| 9627 | |
| 9628 SkipIfEqual::~SkipIfEqual() { | |
| 9629 _masm->bind(_label); | |
| 9630 } |