Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 2080:c04052fd6ae1
7006505: Use kstat info to identify SPARC processor
Summary: read Solaris kstat data to get more precise CPU information
Reviewed-by: iveresov, never, twisti, dholmes
author | kvn |
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date | Thu, 16 Dec 2010 14:15:12 -0800 |
parents | 7737fa7ec2b5 |
children | c17b998c5926 |
rev | line source |
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0 | 1 // |
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2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
0 | 22 // |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
429 %} | |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
463 // Macros to extract hi & lo halves from a long pair. | |
464 // G0 is not part of any long pair, so assert on that. | |
605 | 465 // Prevents accidentally using G1 instead of G0. |
0 | 466 #define LONG_HI_REG(x) (x) |
467 #define LONG_LO_REG(x) (x) | |
468 | |
469 %} | |
470 | |
471 source %{ | |
472 #define __ _masm. | |
473 | |
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474 // Block initializing store |
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475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
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476 |
0 | 477 // tertiary op of a LoadP or StoreP encoding |
478 #define REGP_OP true | |
479 | |
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
482 static Register reg_to_register_object(int register_encoding); | |
483 | |
484 // Used by the DFA in dfa_sparc.cpp. | |
485 // Check for being able to use a V9 branch-on-register. Requires a | |
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
487 // extended. Doesn't work following an integer ADD, for example, because of | |
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
490 // replace them with zero, which could become sign-extension in a different OS | |
491 // release. There's no obvious reason why an interrupt will ever fill these | |
492 // bits with non-zero junk (the registers are reloaded with standard LD | |
493 // instructions which either zero-fill or sign-fill). | |
494 bool can_branch_register( Node *bol, Node *cmp ) { | |
495 if( !BranchOnRegister ) return false; | |
496 #ifdef _LP64 | |
497 if( cmp->Opcode() == Op_CmpP ) | |
498 return true; // No problems with pointer compares | |
499 #endif | |
500 if( cmp->Opcode() == Op_CmpL ) | |
501 return true; // No problems with long compares | |
502 | |
503 if( !SparcV9RegsHiBitsZero ) return false; | |
504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
506 return false; | |
507 | |
508 // Check for comparing against a 'safe' value. Any operation which | |
509 // clears out the high word is safe. Thus, loads and certain shifts | |
510 // are safe, as are non-negative constants. Any operation which | |
511 // preserves zero bits in the high word is safe as long as each of its | |
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
513 // inputs are safe. At present, the only important case to recognize | |
514 // seems to be loads. Constants should fold away, and shifts & | |
515 // logicals can use the 'cc' forms. | |
516 Node *x = cmp->in(1); | |
517 if( x->is_Load() ) return true; | |
518 if( x->is_Phi() ) { | |
519 for( uint i = 1; i < x->req(); i++ ) | |
520 if( !x->in(i)->is_Load() ) | |
521 return false; | |
522 return true; | |
523 } | |
524 return false; | |
525 } | |
526 | |
527 // **************************************************************************** | |
528 | |
529 // REQUIRED FUNCTIONALITY | |
530 | |
531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
532 // from the start of the call to the point where the return address | |
533 // will point. | |
534 // The "return address" is the address of the call instruction, plus 8. | |
535 | |
536 int MachCallStaticJavaNode::ret_addr_offset() { | |
1567 | 537 int offset = NativeCall::instruction_size; // call; delay slot |
538 if (_method_handle_invoke) | |
539 offset += 4; // restore SP | |
540 return offset; | |
0 | 541 } |
542 | |
543 int MachCallDynamicJavaNode::ret_addr_offset() { | |
544 int vtable_index = this->_vtable_index; | |
545 if (vtable_index < 0) { | |
546 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
548 return (NativeMovConstReg::instruction_size + | |
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
550 } else { | |
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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554 int klass_load_size; |
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555 if (UseCompressedOops) { |
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556 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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557 if (Universe::narrow_oop_base() == NULL) |
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558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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559 else |
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560 klass_load_size = 3*BytesPerInstWord; |
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561 } else { |
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562 klass_load_size = 1*BytesPerInstWord; |
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563 } |
0 | 564 if( Assembler::is_simm13(v_off) ) { |
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565 return klass_load_size + |
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566 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 567 NativeCall::instruction_size); // call; delay slot |
568 } else { | |
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569 return klass_load_size + |
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570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 571 NativeCall::instruction_size); // call; delay slot |
572 } | |
573 } | |
574 } | |
575 | |
576 int MachCallRuntimeNode::ret_addr_offset() { | |
577 #ifdef _LP64 | |
578 return NativeFarCall::instruction_size; // farcall; delay slot | |
579 #else | |
580 return NativeCall::instruction_size; // call; delay slot | |
581 #endif | |
582 } | |
583 | |
584 // Indicate if the safepoint node needs the polling page as an input. | |
585 // Since Sparc does not have absolute addressing, it does. | |
586 bool SafePointNode::needs_polling_address_input() { | |
587 return true; | |
588 } | |
589 | |
590 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
591 void emit_break(CodeBuffer &cbuf) { | |
592 MacroAssembler _masm(&cbuf); | |
593 __ breakpoint_trap(); | |
594 } | |
595 | |
596 #ifndef PRODUCT | |
597 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
598 st->print("TA"); | |
599 } | |
600 #endif | |
601 | |
602 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
603 emit_break(cbuf); | |
604 } | |
605 | |
606 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
607 return MachNode::size(ra_); | |
608 } | |
609 | |
610 // Traceable jump | |
611 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
612 MacroAssembler _masm(&cbuf); | |
613 Register rdest = reg_to_register_object(jump_target); | |
614 __ JMP(rdest, 0); | |
615 __ delayed()->nop(); | |
616 } | |
617 | |
618 // Traceable jump and set exception pc | |
619 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
620 MacroAssembler _masm(&cbuf); | |
621 Register rdest = reg_to_register_object(jump_target); | |
622 __ JMP(rdest, 0); | |
623 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
624 } | |
625 | |
626 void emit_nop(CodeBuffer &cbuf) { | |
627 MacroAssembler _masm(&cbuf); | |
628 __ nop(); | |
629 } | |
630 | |
631 void emit_illtrap(CodeBuffer &cbuf) { | |
632 MacroAssembler _masm(&cbuf); | |
633 __ illtrap(0); | |
634 } | |
635 | |
636 | |
637 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
638 assert(n->rule() != loadUB_rule, ""); | |
639 | |
640 intptr_t offset = 0; | |
641 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
642 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
643 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
644 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
645 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
646 atype = atype->add_offset(offset); | |
647 assert(disp32 == offset, "wrong disp32"); | |
648 return atype->_offset; | |
649 } | |
650 | |
651 | |
652 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
653 assert(n->rule() != loadUB_rule, ""); | |
654 | |
655 intptr_t offset = 0; | |
656 Node* addr = n->in(2); | |
657 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
658 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
659 Node* a = addr->in(2/*AddPNode::Address*/); | |
660 Node* o = addr->in(3/*AddPNode::Offset*/); | |
661 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
662 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
663 assert(atype->isa_oop_ptr(), "still an oop"); | |
664 } | |
665 offset = atype->is_ptr()->_offset; | |
666 if (offset != Type::OffsetBot) offset += disp32; | |
667 return offset; | |
668 } | |
669 | |
2008 | 670 static inline jdouble replicate_immI(int con, int count, int width) { |
671 // Load a constant replicated "count" times with width "width" | |
672 int bit_width = width * 8; | |
673 jlong elt_val = con; | |
674 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits | |
675 jlong val = elt_val; | |
676 for (int i = 0; i < count - 1; i++) { | |
677 val <<= bit_width; | |
678 val |= elt_val; | |
679 } | |
680 jdouble dval = *((jdouble*) &val); // coerce to double type | |
681 return dval; | |
682 } | |
683 | |
0 | 684 // Standard Sparc opcode form2 field breakdown |
685 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
686 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
687 int op = (f30 << 30) | | |
688 (f29 << 29) | | |
689 (f25 << 25) | | |
690 (f22 << 22) | | |
691 (f20 << 20) | | |
692 (f19 << 19) | | |
693 (f0 << 0); | |
1748 | 694 cbuf.insts()->emit_int32(op); |
0 | 695 } |
696 | |
697 // Standard Sparc opcode form2 field breakdown | |
698 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
699 f0 >>= 10; // Drop 10 bits | |
700 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
701 int op = (f30 << 30) | | |
702 (f25 << 25) | | |
703 (f22 << 22) | | |
704 (f0 << 0); | |
1748 | 705 cbuf.insts()->emit_int32(op); |
0 | 706 } |
707 | |
708 // Standard Sparc opcode form3 field breakdown | |
709 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
710 int op = (f30 << 30) | | |
711 (f25 << 25) | | |
712 (f19 << 19) | | |
713 (f14 << 14) | | |
714 (f5 << 5) | | |
715 (f0 << 0); | |
1748 | 716 cbuf.insts()->emit_int32(op); |
0 | 717 } |
718 | |
719 // Standard Sparc opcode form3 field breakdown | |
720 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
721 simm13 &= (1<<13)-1; // Mask to 13 bits | |
722 int op = (f30 << 30) | | |
723 (f25 << 25) | | |
724 (f19 << 19) | | |
725 (f14 << 14) | | |
726 (1 << 13) | // bit to indicate immediate-mode | |
727 (simm13<<0); | |
1748 | 728 cbuf.insts()->emit_int32(op); |
0 | 729 } |
730 | |
731 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
732 simm10 &= (1<<10)-1; // Mask to 10 bits | |
733 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
734 } | |
735 | |
736 #ifdef ASSERT | |
737 // Helper function for VerifyOops in emit_form3_mem_reg | |
738 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
739 warning("VerifyOops encountered unexpected instruction:"); | |
740 n->dump(2); | |
741 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
742 } | |
743 #endif | |
744 | |
745 | |
746 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
747 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
748 | |
749 #ifdef ASSERT | |
750 // The following code implements the +VerifyOops feature. | |
751 // It verifies oop values which are loaded into or stored out of | |
752 // the current method activation. +VerifyOops complements techniques | |
753 // like ScavengeALot, because it eagerly inspects oops in transit, | |
754 // as they enter or leave the stack, as opposed to ScavengeALot, | |
755 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
756 // For this reason, +VerifyOops can sometimes detect bugs very close | |
757 // to their point of creation. It can also serve as a cross-check | |
758 // on the validity of oop maps, when used toegether with ScavengeALot. | |
759 | |
760 // It would be good to verify oops at other points, especially | |
761 // when an oop is used as a base pointer for a load or store. | |
762 // This is presently difficult, because it is hard to know when | |
763 // a base address is biased or not. (If we had such information, | |
764 // it would be easy and useful to make a two-argument version of | |
765 // verify_oop which unbiases the base, and performs verification.) | |
766 | |
767 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
768 bool is_verified_oop_base = false; | |
769 bool is_verified_oop_load = false; | |
770 bool is_verified_oop_store = false; | |
771 int tmp_enc = -1; | |
772 if (VerifyOops && src1_enc != R_SP_enc) { | |
773 // classify the op, mainly for an assert check | |
774 int st_op = 0, ld_op = 0; | |
775 switch (primary) { | |
776 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
777 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
778 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
779 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
780 case Assembler::std_op3: st_op = Op_StoreL; break; | |
781 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
782 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
783 | |
784 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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785 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 786 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
787 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
788 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
789 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
790 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
791 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
792 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
793 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
794 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
795 | |
796 default: ShouldNotReachHere(); | |
797 } | |
798 if (tertiary == REGP_OP) { | |
799 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
800 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
801 else ShouldNotReachHere(); | |
802 if (st_op) { | |
803 // a store | |
804 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
805 Node* n2 = n->in(3); | |
806 if (n2 != NULL) { | |
807 const Type* t = n2->bottom_type(); | |
808 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
809 } | |
810 } else { | |
811 // a load | |
812 const Type* t = n->bottom_type(); | |
813 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
814 } | |
815 } | |
816 | |
817 if (ld_op) { | |
818 // a Load | |
819 // inputs are (0:control, 1:memory, 2:address) | |
820 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
821 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
822 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
823 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
824 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
825 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
826 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
827 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
828 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
829 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
830 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
831 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
832 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
833 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
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834 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && |
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835 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && |
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836 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && |
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837 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && |
0 | 838 !(n->rule() == loadUB_rule)) { |
839 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
840 } | |
841 } else if (st_op) { | |
842 // a Store | |
843 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
844 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
845 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
846 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
847 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
848 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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849 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && |
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850 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && |
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851 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && |
0 | 852 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
853 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
854 } | |
855 } | |
856 | |
857 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
858 Node* addr = n->in(2); | |
859 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
860 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
861 if (atype != NULL) { | |
862 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
863 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
864 if (offset != offset_2) { | |
865 get_offset_from_base(n, atype, disp32); | |
866 get_offset_from_base_2(n, atype, disp32); | |
867 } | |
868 assert(offset == offset_2, "different offsets"); | |
869 if (offset == disp32) { | |
870 // we now know that src1 is a true oop pointer | |
871 is_verified_oop_base = true; | |
872 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
873 if( primary == Assembler::ldd_op3 ) { | |
874 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
875 } else { | |
876 tmp_enc = dst_enc; | |
877 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
878 assert(src1_enc != dst_enc, ""); | |
879 } | |
880 } | |
881 } | |
882 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
883 || offset == oopDesc::mark_offset_in_bytes())) { | |
884 // loading the mark should not be allowed either, but | |
885 // we don't check this since it conflicts with InlineObjectHash | |
886 // usage of LoadINode to get the mark. We could keep the | |
887 // check if we create a new LoadMarkNode | |
888 // but do not verify the object before its header is initialized | |
889 ShouldNotReachHere(); | |
890 } | |
891 } | |
892 } | |
893 } | |
894 } | |
895 #endif | |
896 | |
897 uint instr; | |
898 instr = (Assembler::ldst_op << 30) | |
899 | (dst_enc << 25) | |
900 | (primary << 19) | |
901 | (src1_enc << 14); | |
902 | |
903 uint index = src2_enc; | |
904 int disp = disp32; | |
905 | |
906 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
907 disp += STACK_BIAS; | |
908 | |
909 // We should have a compiler bailout here rather than a guarantee. | |
910 // Better yet would be some mechanism to handle variable-size matches correctly. | |
911 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
912 | |
913 if( disp == 0 ) { | |
914 // use reg-reg form | |
915 // bit 13 is already zero | |
916 instr |= index; | |
917 } else { | |
918 // use reg-imm form | |
919 instr |= 0x00002000; // set bit 13 to one | |
920 instr |= disp & 0x1FFF; | |
921 } | |
922 | |
1748 | 923 cbuf.insts()->emit_int32(instr); |
0 | 924 |
925 #ifdef ASSERT | |
926 { | |
927 MacroAssembler _masm(&cbuf); | |
928 if (is_verified_oop_base) { | |
929 __ verify_oop(reg_to_register_object(src1_enc)); | |
930 } | |
931 if (is_verified_oop_store) { | |
932 __ verify_oop(reg_to_register_object(dst_enc)); | |
933 } | |
934 if (tmp_enc != -1) { | |
935 __ mov(O7, reg_to_register_object(tmp_enc)); | |
936 } | |
937 if (is_verified_oop_load) { | |
938 __ verify_oop(reg_to_register_object(dst_enc)); | |
939 } | |
940 } | |
941 #endif | |
942 } | |
943 | |
944 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
945 // The method which records debug information at every safepoint | |
946 // expects the call to be the first instruction in the snippet as | |
947 // it creates a PcDesc structure which tracks the offset of a call | |
948 // from the start of the codeBlob. This offset is computed as | |
949 // code_end() - code_begin() of the code which has been emitted | |
950 // so far. | |
951 // In this particular case we have skirted around the problem by | |
952 // putting the "mov" instruction in the delay slot but the problem | |
953 // may bite us again at some other point and a cleaner/generic | |
954 // solution using relocations would be needed. | |
955 MacroAssembler _masm(&cbuf); | |
956 __ set_inst_mark(); | |
957 | |
958 // We flush the current window just so that there is a valid stack copy | |
959 // the fact that the current window becomes active again instantly is | |
960 // not a problem there is nothing live in it. | |
961 | |
962 #ifdef ASSERT | |
963 int startpos = __ offset(); | |
964 #endif /* ASSERT */ | |
965 | |
966 #ifdef _LP64 | |
967 // Calls to the runtime or native may not be reachable from compiled code, | |
968 // so we generate the far call sequence on 64 bit sparc. | |
969 // This code sequence is relocatable to any address, even on LP64. | |
970 if ( force_far_call ) { | |
971 __ relocate(rtype); | |
727 | 972 AddressLiteral dest(entry_point); |
973 __ jumpl_to(dest, O7, O7); | |
0 | 974 } |
975 else | |
976 #endif | |
977 { | |
978 __ call((address)entry_point, rtype); | |
979 } | |
980 | |
981 if (preserve_g2) __ delayed()->mov(G2, L7); | |
982 else __ delayed()->nop(); | |
983 | |
984 if (preserve_g2) __ mov(L7, G2); | |
985 | |
986 #ifdef ASSERT | |
987 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
988 #ifdef _LP64 | |
989 // Trash argument dump slots. | |
990 __ set(0xb0b8ac0db0b8ac0d, G1); | |
991 __ mov(G1, G5); | |
992 __ stx(G1, SP, STACK_BIAS + 0x80); | |
993 __ stx(G1, SP, STACK_BIAS + 0x88); | |
994 __ stx(G1, SP, STACK_BIAS + 0x90); | |
995 __ stx(G1, SP, STACK_BIAS + 0x98); | |
996 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
997 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
998 #else // _LP64 | |
999 // this is also a native call, so smash the first 7 stack locations, | |
1000 // and the various registers | |
1001 | |
1002 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
1003 // while [SP+0x44..0x58] are the argument dump slots. | |
1004 __ set((intptr_t)0xbaadf00d, G1); | |
1005 __ mov(G1, G5); | |
1006 __ sllx(G1, 32, G1); | |
1007 __ or3(G1, G5, G1); | |
1008 __ mov(G1, G5); | |
1009 __ stx(G1, SP, 0x40); | |
1010 __ stx(G1, SP, 0x48); | |
1011 __ stx(G1, SP, 0x50); | |
1012 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1013 #endif // _LP64 | |
1014 } | |
1015 #endif /*ASSERT*/ | |
1016 } | |
1017 | |
1018 //============================================================================= | |
1019 // REQUIRED FUNCTIONALITY for encoding | |
1020 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1021 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1022 | |
1023 | |
1024 //============================================================================= | |
2008 | 1025 const bool Matcher::constant_table_absolute_addressing = false; |
1026 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; | |
1027 | |
1028 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
1029 Compile* C = ra_->C; | |
1030 Compile::ConstantTable& constant_table = C->constant_table(); | |
1031 MacroAssembler _masm(&cbuf); | |
1032 | |
1033 Register r = as_Register(ra_->get_encode(this)); | |
1034 CodeSection* cs = __ code()->consts(); | |
1035 int consts_size = cs->align_at_start(cs->size()); | |
1036 | |
1037 if (UseRDPCForConstantTableBase) { | |
1038 // For the following RDPC logic to work correctly the consts | |
1039 // section must be allocated right before the insts section. This | |
1040 // assert checks for that. The layout and the SECT_* constants | |
1041 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
1042 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
1043 int offset = __ offset(); | |
1044 int disp; | |
1045 | |
1046 // If the displacement from the current PC to the constant table | |
1047 // base fits into simm13 we set the constant table base to the | |
1048 // current PC. | |
1049 if (__ is_simm13(-(consts_size + offset))) { | |
1050 constant_table.set_table_base_offset(-(consts_size + offset)); | |
1051 disp = 0; | |
1052 } else { | |
1053 // If the offset of the top constant (last entry in the table) | |
1054 // fits into simm13 we set the constant table base to the actual | |
1055 // table base. | |
1056 if (__ is_simm13(constant_table.top_offset())) { | |
1057 constant_table.set_table_base_offset(0); | |
1058 disp = consts_size + offset; | |
1059 } else { | |
1060 // Otherwise we set the constant table base in the middle of the | |
1061 // constant table. | |
1062 int half_consts_size = consts_size / 2; | |
1063 assert(half_consts_size * 2 == consts_size, "sanity"); | |
1064 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. | |
1065 disp = half_consts_size + offset; | |
1066 } | |
1067 } | |
1068 | |
1069 __ rdpc(r); | |
1070 | |
1071 if (disp != 0) { | |
1072 assert(r != O7, "need temporary"); | |
1073 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
1074 } | |
1075 } | |
1076 else { | |
1077 // Materialize the constant table base. | |
1078 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | |
1079 address baseaddr = cs->start() + -(constant_table.table_base_offset()); | |
1080 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); | |
1081 AddressLiteral base(baseaddr, rspec); | |
1082 __ set(base, r); | |
1083 } | |
1084 } | |
1085 | |
1086 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
1087 if (UseRDPCForConstantTableBase) { | |
1088 // This is really the worst case but generally it's only 1 instruction. | |
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1089 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
2008 | 1090 } else { |
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1091 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
2008 | 1092 } |
1093 } | |
1094 | |
1095 #ifndef PRODUCT | |
1096 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
1097 char reg[128]; | |
1098 ra_->dump_register(this, reg); | |
1099 if (UseRDPCForConstantTableBase) { | |
1100 st->print("RDPC %s\t! constant table base", reg); | |
1101 } else { | |
1102 st->print("SET &constanttable,%s\t! constant table base", reg); | |
1103 } | |
1104 } | |
1105 #endif | |
1106 | |
1107 | |
1108 //============================================================================= | |
0 | 1109 |
1110 #ifndef PRODUCT | |
1111 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1112 Compile* C = ra_->C; | |
1113 | |
1114 for (int i = 0; i < OptoPrologueNops; i++) { | |
1115 st->print_cr("NOP"); st->print("\t"); | |
1116 } | |
1117 | |
1118 if( VerifyThread ) { | |
1119 st->print_cr("Verify_Thread"); st->print("\t"); | |
1120 } | |
1121 | |
1122 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1123 | |
1124 // Calls to C2R adapters often do not accept exceptional returns. | |
1125 // We require that their callers must bang for them. But be careful, because | |
1126 // some VM calls (such as call site linkage) can use several kilobytes of | |
1127 // stack. But the stack safety zone should account for that. | |
1128 // See bugs 4446381, 4468289, 4497237. | |
1129 if (C->need_stack_bang(framesize)) { | |
1130 st->print_cr("! stack bang"); st->print("\t"); | |
1131 } | |
1132 | |
1133 if (Assembler::is_simm13(-framesize)) { | |
1134 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1135 } else { | |
1136 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1137 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1138 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1139 } | |
1140 | |
1141 } | |
1142 #endif | |
1143 | |
1144 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1145 Compile* C = ra_->C; | |
1146 MacroAssembler _masm(&cbuf); | |
1147 | |
1148 for (int i = 0; i < OptoPrologueNops; i++) { | |
1149 __ nop(); | |
1150 } | |
1151 | |
1152 __ verify_thread(); | |
1153 | |
1154 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1155 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1156 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1157 | |
1158 // Calls to C2R adapters often do not accept exceptional returns. | |
1159 // We require that their callers must bang for them. But be careful, because | |
1160 // some VM calls (such as call site linkage) can use several kilobytes of | |
1161 // stack. But the stack safety zone should account for that. | |
1162 // See bugs 4446381, 4468289, 4497237. | |
1163 if (C->need_stack_bang(framesize)) { | |
1164 __ generate_stack_overflow_check(framesize); | |
1165 } | |
1166 | |
1167 if (Assembler::is_simm13(-framesize)) { | |
1168 __ save(SP, -framesize, SP); | |
1169 } else { | |
1170 __ sethi(-framesize & ~0x3ff, G3); | |
1171 __ add(G3, -framesize & 0x3ff, G3); | |
1172 __ save(SP, G3, SP); | |
1173 } | |
1174 C->set_frame_complete( __ offset() ); | |
1175 } | |
1176 | |
1177 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1178 return MachNode::size(ra_); | |
1179 } | |
1180 | |
1181 int MachPrologNode::reloc() const { | |
1182 return 10; // a large enough number | |
1183 } | |
1184 | |
1185 //============================================================================= | |
1186 #ifndef PRODUCT | |
1187 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1188 Compile* C = ra_->C; | |
1189 | |
1190 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1191 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1192 #ifdef _LP64 | |
1193 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1194 #else | |
1195 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1196 #endif | |
1197 } | |
1198 | |
1199 if( do_polling() ) | |
1200 st->print("RET\n\t"); | |
1201 | |
1202 st->print("RESTORE"); | |
1203 } | |
1204 #endif | |
1205 | |
1206 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1207 MacroAssembler _masm(&cbuf); | |
1208 Compile* C = ra_->C; | |
1209 | |
1210 __ verify_thread(); | |
1211 | |
1212 // If this does safepoint polling, then do it here | |
1213 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1214 AddressLiteral polling_page(os::get_polling_page()); |
1215 __ sethi(polling_page, L0); | |
0 | 1216 __ relocate(relocInfo::poll_return_type); |
1217 __ ld_ptr( L0, 0, G0 ); | |
1218 } | |
1219 | |
1220 // If this is a return, then stuff the restore in the delay slot | |
1221 if( do_polling() ) { | |
1222 __ ret(); | |
1223 __ delayed()->restore(); | |
1224 } else { | |
1225 __ restore(); | |
1226 } | |
1227 } | |
1228 | |
1229 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1230 return MachNode::size(ra_); | |
1231 } | |
1232 | |
1233 int MachEpilogNode::reloc() const { | |
1234 return 16; // a large enough number | |
1235 } | |
1236 | |
1237 const Pipeline * MachEpilogNode::pipeline() const { | |
1238 return MachNode::pipeline_class(); | |
1239 } | |
1240 | |
1241 int MachEpilogNode::safepoint_offset() const { | |
1242 assert( do_polling(), "no return for this epilog node"); | |
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1243 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
0 | 1244 } |
1245 | |
1246 //============================================================================= | |
1247 | |
1248 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1249 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1250 static enum RC rc_class( OptoReg::Name reg ) { | |
1251 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1252 if (OptoReg::is_stack(reg)) return rc_stack; | |
1253 VMReg r = OptoReg::as_VMReg(reg); | |
1254 if (r->is_Register()) return rc_int; | |
1255 assert(r->is_FloatRegister(), "must be"); | |
1256 return rc_float; | |
1257 } | |
1258 | |
1259 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1260 if( cbuf ) { | |
1261 // Better yet would be some mechanism to handle variable-size matches correctly | |
1262 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1263 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1264 } else { | |
1265 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1266 } | |
1267 } | |
1268 #ifndef PRODUCT | |
1269 else if( !do_size ) { | |
1270 if( size != 0 ) st->print("\n\t"); | |
1271 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1272 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1273 } | |
1274 #endif | |
1275 return size+4; | |
1276 } | |
1277 | |
1278 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1279 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1280 #ifndef PRODUCT | |
1281 else if( !do_size ) { | |
1282 if( size != 0 ) st->print("\n\t"); | |
1283 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1284 } | |
1285 #endif | |
1286 return size+4; | |
1287 } | |
1288 | |
1289 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1290 PhaseRegAlloc *ra_, | |
1291 bool do_size, | |
1292 outputStream* st ) const { | |
1293 // Get registers to move | |
1294 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1295 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1296 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1297 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1298 | |
1299 enum RC src_second_rc = rc_class(src_second); | |
1300 enum RC src_first_rc = rc_class(src_first); | |
1301 enum RC dst_second_rc = rc_class(dst_second); | |
1302 enum RC dst_first_rc = rc_class(dst_first); | |
1303 | |
1304 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1305 | |
1306 // Generate spill code! | |
1307 int size = 0; | |
1308 | |
1309 if( src_first == dst_first && src_second == dst_second ) | |
1310 return size; // Self copy, no move | |
1311 | |
1312 // -------------------------------------- | |
1313 // Check for mem-mem move. Load into unused float registers and fall into | |
1314 // the float-store case. | |
1315 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1316 int offset = ra_->reg2offset(src_first); | |
1317 // Further check for aligned-adjacent pair, so we can use a double load | |
1318 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1319 src_second = OptoReg::Name(R_F31_num); | |
1320 src_second_rc = rc_float; | |
1321 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1322 } else { | |
1323 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1324 } | |
1325 src_first = OptoReg::Name(R_F30_num); | |
1326 src_first_rc = rc_float; | |
1327 } | |
1328 | |
1329 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1330 int offset = ra_->reg2offset(src_second); | |
1331 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1332 src_second = OptoReg::Name(R_F31_num); | |
1333 src_second_rc = rc_float; | |
1334 } | |
1335 | |
1336 // -------------------------------------- | |
1337 // Check for float->int copy; requires a trip through memory | |
1338 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
1339 int offset = frame::register_save_words*wordSize; | |
1340 if( cbuf ) { | |
1341 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
1342 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1343 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1344 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1345 } | |
1346 #ifndef PRODUCT | |
1347 else if( !do_size ) { | |
1348 if( size != 0 ) st->print("\n\t"); | |
1349 st->print( "SUB R_SP,16,R_SP\n"); | |
1350 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1351 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1352 st->print("\tADD R_SP,16,R_SP\n"); | |
1353 } | |
1354 #endif | |
1355 size += 16; | |
1356 } | |
1357 | |
1358 // -------------------------------------- | |
1359 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1360 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1361 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1362 // there. Misaligned sources only come from native-long-returns (handled | |
1363 // special below). | |
1364 #ifndef _LP64 | |
1365 if( src_first_rc == rc_int && // source is already big-endian | |
1366 src_second_rc != rc_bad && // 64-bit move | |
1367 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1368 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1369 // Do the big-endian flop. | |
1370 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1371 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1372 } | |
1373 #endif | |
1374 | |
1375 // -------------------------------------- | |
1376 // Check for integer reg-reg copy | |
1377 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1378 #ifndef _LP64 | |
1379 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1380 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1381 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1382 // operand contains the least significant word of the 64-bit value and vice versa. | |
1383 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1384 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1385 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1386 if( cbuf ) { | |
1387 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1388 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1389 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1390 #ifndef PRODUCT | |
1391 } else if( !do_size ) { | |
1392 if( size != 0 ) st->print("\n\t"); | |
1393 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1394 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1395 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1396 #endif | |
1397 } | |
1398 return size+12; | |
1399 } | |
1400 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1401 // returning a long value in I0/I1 | |
1402 // a SpillCopy must be able to target a return instruction's reg_class | |
1403 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1404 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1405 // operand contains the least significant word of the 64-bit value and vice versa. | |
1406 OptoReg::Name tdest = dst_first; | |
1407 | |
1408 if (src_first == dst_first) { | |
1409 tdest = OptoReg::Name(R_O7_num); | |
1410 size += 4; | |
1411 } | |
1412 | |
1413 if( cbuf ) { | |
1414 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1415 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1416 // ShrL_reg_imm6 | |
1417 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1418 // ShrR_reg_imm6 src, 0, dst | |
1419 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1420 if (tdest != dst_first) { | |
1421 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1422 } | |
1423 } | |
1424 #ifndef PRODUCT | |
1425 else if( !do_size ) { | |
1426 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1427 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1428 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1429 if (tdest != dst_first) { | |
1430 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1431 } | |
1432 } | |
1433 #endif // PRODUCT | |
1434 return size+8; | |
1435 } | |
1436 #endif // !_LP64 | |
1437 // Else normal reg-reg copy | |
1438 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1439 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1440 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1441 // This moves an aligned adjacent pair. | |
1442 // See if we are done. | |
1443 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1444 return size; | |
1445 } | |
1446 | |
1447 // Check for integer store | |
1448 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1449 int offset = ra_->reg2offset(dst_first); | |
1450 // Further check for aligned-adjacent pair, so we can use a double store | |
1451 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1452 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1453 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1454 } | |
1455 | |
1456 // Check for integer load | |
1457 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1458 int offset = ra_->reg2offset(src_first); | |
1459 // Further check for aligned-adjacent pair, so we can use a double load | |
1460 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1461 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1462 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1463 } | |
1464 | |
1465 // Check for float reg-reg copy | |
1466 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1467 // Further check for aligned-adjacent pair, so we can use a double move | |
1468 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1469 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1470 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1471 } | |
1472 | |
1473 // Check for float store | |
1474 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1475 int offset = ra_->reg2offset(dst_first); | |
1476 // Further check for aligned-adjacent pair, so we can use a double store | |
1477 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1478 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1479 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1480 } | |
1481 | |
1482 // Check for float load | |
1483 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1484 int offset = ra_->reg2offset(src_first); | |
1485 // Further check for aligned-adjacent pair, so we can use a double load | |
1486 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1487 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1488 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1489 } | |
1490 | |
1491 // -------------------------------------------------------------------- | |
1492 // Check for hi bits still needing moving. Only happens for misaligned | |
1493 // arguments to native calls. | |
1494 if( src_second == dst_second ) | |
1495 return size; // Self copy; no move | |
1496 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1497 | |
1498 #ifndef _LP64 | |
1499 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1500 // pairs, so there's never any need to move the high bits separately. |
0 | 1501 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1502 // all sorts of silly alignment problems. | |
1503 | |
1504 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1505 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1506 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1507 // happened already as part of a 64-bit move) | |
1508 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1509 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1510 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1511 // Shift src_second down to dst_second's low bits. | |
1512 if( cbuf ) { | |
1513 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1514 #ifndef PRODUCT | |
1515 } else if( !do_size ) { | |
1516 if( size != 0 ) st->print("\n\t"); | |
1517 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1518 #endif | |
1519 } | |
1520 return size+4; | |
1521 } | |
1522 | |
1523 // Check for high word integer store. Must down-shift the hi bits | |
1524 // into a temp register, then fall into the case of storing int bits. | |
1525 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1526 // Shift src_second down to dst_second's low bits. | |
1527 if( cbuf ) { | |
1528 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1529 #ifndef PRODUCT | |
1530 } else if( !do_size ) { | |
1531 if( size != 0 ) st->print("\n\t"); | |
1532 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1533 #endif | |
1534 } | |
1535 size+=4; | |
1536 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1537 } | |
1538 | |
1539 // Check for high word integer load | |
1540 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1541 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1542 | |
1543 // Check for high word integer store | |
1544 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1545 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1546 | |
1547 // Check for high word float store | |
1548 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1549 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1550 | |
1551 #endif // !_LP64 | |
1552 | |
1553 Unimplemented(); | |
1554 } | |
1555 | |
1556 #ifndef PRODUCT | |
1557 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1558 implementation( NULL, ra_, false, st ); | |
1559 } | |
1560 #endif | |
1561 | |
1562 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1563 implementation( &cbuf, ra_, false, NULL ); | |
1564 } | |
1565 | |
1566 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1567 return implementation( NULL, ra_, true, NULL ); | |
1568 } | |
1569 | |
1570 //============================================================================= | |
1571 #ifndef PRODUCT | |
1572 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1573 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1574 } | |
1575 #endif | |
1576 | |
1577 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1578 MacroAssembler _masm(&cbuf); | |
1579 for(int i = 0; i < _count; i += 1) { | |
1580 __ nop(); | |
1581 } | |
1582 } | |
1583 | |
1584 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1585 return 4 * _count; | |
1586 } | |
1587 | |
1588 | |
1589 //============================================================================= | |
1590 #ifndef PRODUCT | |
1591 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1592 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1593 int reg = ra_->get_reg_first(this); | |
1594 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1595 } | |
1596 #endif | |
1597 | |
1598 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1599 MacroAssembler _masm(&cbuf); | |
1600 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1601 int reg = ra_->get_encode(this); | |
1602 | |
1603 if (Assembler::is_simm13(offset)) { | |
1604 __ add(SP, offset, reg_to_register_object(reg)); | |
1605 } else { | |
1606 __ set(offset, O7); | |
1607 __ add(SP, O7, reg_to_register_object(reg)); | |
1608 } | |
1609 } | |
1610 | |
1611 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1612 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1613 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1614 return ra_->C->scratch_emit_size(this); | |
1615 } | |
1616 | |
1617 //============================================================================= | |
1618 | |
1619 // emit call stub, compiled java to interpretor | |
1620 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
1621 | |
1622 // Stub is fixed up when the corresponding call is converted from calling | |
1623 // compiled code to calling interpreted code. | |
1624 // set (empty), G5 | |
1625 // jmp -1 | |
1626 | |
1748 | 1627 address mark = cbuf.insts_mark(); // get mark within main instrs section |
0 | 1628 |
1629 MacroAssembler _masm(&cbuf); | |
1630 | |
1631 address base = | |
1632 __ start_a_stub(Compile::MAX_stubs_size); | |
1633 if (base == NULL) return; // CodeBuffer::expand failed | |
1634 | |
1635 // static stub relocation stores the instruction address of the call | |
1636 __ relocate(static_stub_Relocation::spec(mark)); | |
1637 | |
1638 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
1639 | |
1640 __ set_inst_mark(); | |
727 | 1641 AddressLiteral addrlit(-1); |
1642 __ JUMP(addrlit, G3, 0); | |
0 | 1643 |
1644 __ delayed()->nop(); | |
1645 | |
1646 // Update current stubs pointer and restore code_end. | |
1647 __ end_a_stub(); | |
1648 } | |
1649 | |
1650 // size of call stub, compiled java to interpretor | |
1651 uint size_java_to_interp() { | |
1652 // This doesn't need to be accurate but it must be larger or equal to | |
1653 // the real size of the stub. | |
1654 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
1655 NativeJump::instruction_size + // sethi; jmp; nop | |
1656 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
1657 } | |
1658 // relocation entries for call stub, compiled java to interpretor | |
1659 uint reloc_java_to_interp() { | |
1660 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
1661 } | |
1662 | |
1663 | |
1664 //============================================================================= | |
1665 #ifndef PRODUCT | |
1666 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1667 st->print_cr("\nUEP:"); | |
1668 #ifdef _LP64 | |
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1669 if (UseCompressedOops) { |
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1670 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1671 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1672 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1673 if (Universe::narrow_oop_base() != NULL) |
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1674 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1675 } else { |
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1676 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1677 } |
0 | 1678 st->print_cr("\tCMP R_G5,R_G3" ); |
1679 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1680 #else // _LP64 | |
1681 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1682 st->print_cr("\tCMP R_G5,R_G3" ); | |
1683 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1684 #endif // _LP64 | |
1685 } | |
1686 #endif | |
1687 | |
1688 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1689 MacroAssembler _masm(&cbuf); | |
1690 Label L; | |
1691 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1692 Register temp_reg = G3; | |
1693 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1694 | |
605 | 1695 // Load klass from receiver |
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1696 __ load_klass(O0, temp_reg); |
0 | 1697 // Compare against expected klass |
1698 __ cmp(temp_reg, G5_ic_reg); | |
1699 // Branch to miss code, checks xcc or icc depending | |
1700 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1701 } | |
1702 | |
1703 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1704 return MachNode::size(ra_); | |
1705 } | |
1706 | |
1707 | |
1708 //============================================================================= | |
1709 | |
1710 uint size_exception_handler() { | |
1711 if (TraceJumps) { | |
1712 return (400); // just a guess | |
1713 } | |
1714 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1715 } | |
1716 | |
1717 uint size_deopt_handler() { | |
1718 if (TraceJumps) { | |
1719 return (400); // just a guess | |
1720 } | |
1721 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1722 } | |
1723 | |
1724 // Emit exception handler code. | |
1725 int emit_exception_handler(CodeBuffer& cbuf) { | |
1726 Register temp_reg = G3; | |
1748 | 1727 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
0 | 1728 MacroAssembler _masm(&cbuf); |
1729 | |
1730 address base = | |
1731 __ start_a_stub(size_exception_handler()); | |
1732 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1733 | |
1734 int offset = __ offset(); | |
1735 | |
727 | 1736 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1737 __ delayed()->nop(); |
1738 | |
1739 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1740 | |
1741 __ end_a_stub(); | |
1742 | |
1743 return offset; | |
1744 } | |
1745 | |
1746 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1747 // Can't use any of the current frame's registers as we may have deopted | |
1748 // at a poll and everything (including G3) can be live. | |
1749 Register temp_reg = L0; | |
727 | 1750 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1751 MacroAssembler _masm(&cbuf); |
1752 | |
1753 address base = | |
1754 __ start_a_stub(size_deopt_handler()); | |
1755 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1756 | |
1757 int offset = __ offset(); | |
1758 __ save_frame(0); | |
727 | 1759 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1760 __ delayed()->restore(); |
1761 | |
1762 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1763 | |
1764 __ end_a_stub(); | |
1765 return offset; | |
1766 | |
1767 } | |
1768 | |
1769 // Given a register encoding, produce a Integer Register object | |
1770 static Register reg_to_register_object(int register_encoding) { | |
1771 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1772 return as_Register(register_encoding); | |
1773 } | |
1774 | |
1775 // Given a register encoding, produce a single-precision Float Register object | |
1776 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1777 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1778 return as_SingleFloatRegister(register_encoding); | |
1779 } | |
1780 | |
1781 // Given a register encoding, produce a double-precision Float Register object | |
1782 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1783 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1784 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1785 return as_DoubleFloatRegister(register_encoding); | |
1786 } | |
1787 | |
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1788 const bool Matcher::match_rule_supported(int opcode) { |
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1789 if (!has_match_rule(opcode)) |
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1790 return false; |
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1791 |
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1792 switch (opcode) { |
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1793 case Op_CountLeadingZerosI: |
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1794 case Op_CountLeadingZerosL: |
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1795 case Op_CountTrailingZerosI: |
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1796 case Op_CountTrailingZerosL: |
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1797 if (!UsePopCountInstruction) |
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1798 return false; |
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1799 break; |
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1800 } |
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1801 |
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1802 return true; // Per default match rules are supported. |
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1803 } |
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1804 |
0 | 1805 int Matcher::regnum_to_fpu_offset(int regnum) { |
1806 return regnum - 32; // The FP registers are in the second chunk | |
1807 } | |
1808 | |
1809 #ifdef ASSERT | |
1810 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1811 #endif | |
1812 | |
1813 // Vector width in bytes | |
1814 const uint Matcher::vector_width_in_bytes(void) { | |
1815 return 8; | |
1816 } | |
1817 | |
1818 // Vector ideal reg | |
1819 const uint Matcher::vector_ideal_reg(void) { | |
1820 return Op_RegD; | |
1821 } | |
1822 | |
1823 // USII supports fxtof through the whole range of number, USIII doesn't | |
1824 const bool Matcher::convL2FSupported(void) { | |
1825 return VM_Version::has_fast_fxtof(); | |
1826 } | |
1827 | |
1828 // Is this branch offset short enough that a short branch can be used? | |
1829 // | |
1830 // NOTE: If the platform does not provide any short branch variants, then | |
1831 // this method should return false for offset 0. | |
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1832 bool Matcher::is_short_branch_offset(int rule, int offset) { |
0 | 1833 return false; |
1834 } | |
1835 | |
1836 const bool Matcher::isSimpleConstant64(jlong value) { | |
1837 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1838 // Depends on optimizations in MacroAssembler::setx. | |
1839 int hi = (int)(value >> 32); | |
1840 int lo = (int)(value & ~0); | |
1841 return (hi == 0) || (hi == -1) || (lo == 0); | |
1842 } | |
1843 | |
1844 // No scaling for the parameter the ClearArray node. | |
1845 const bool Matcher::init_array_count_is_in_bytes = true; | |
1846 | |
1847 // Threshold size for cleararray. | |
1848 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1849 | |
1850 // Should the Matcher clone shifts on addressing modes, expecting them to | |
1851 // be subsumed into complex addressing expressions or compute them into | |
1852 // registers? True for Intel but false for most RISCs | |
1853 const bool Matcher::clone_shift_expressions = false; | |
1854 | |
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1855 bool Matcher::narrow_oop_use_complex_address() { |
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1856 NOT_LP64(ShouldNotCallThis()); |
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1857 assert(UseCompressedOops, "only for compressed oops code"); |
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1858 return false; |
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1859 } |
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1860 |
0 | 1861 // Is it better to copy float constants, or load them directly from memory? |
1862 // Intel can load a float constant from a direct address, requiring no | |
1863 // extra registers. Most RISCs will have to materialize an address into a | |
1864 // register first, so they would do better to copy the constant from stack. | |
1865 const bool Matcher::rematerialize_float_constants = false; | |
1866 | |
1867 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1868 // needed. Else we split the double into 2 integer pieces and move it | |
1869 // piece-by-piece. Only happens when passing doubles into C code as the | |
1870 // Java calling convention forces doubles to be aligned. | |
1871 #ifdef _LP64 | |
1872 const bool Matcher::misaligned_doubles_ok = true; | |
1873 #else | |
1874 const bool Matcher::misaligned_doubles_ok = false; | |
1875 #endif | |
1876 | |
1877 // No-op on SPARC. | |
1878 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1879 } | |
1880 | |
1881 // Advertise here if the CPU requires explicit rounding operations | |
1882 // to implement the UseStrictFP mode. | |
1883 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1884 | |
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1885 // Are floats conerted to double when stored to stack during deoptimization? |
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1886 // Sparc does not handle callee-save floats. |
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1887 bool Matcher::float_in_double() { return false; } |
0 | 1888 |
1889 // Do ints take an entire long register or just half? | |
1890 // Note that we if-def off of _LP64. | |
1891 // The relevant question is how the int is callee-saved. In _LP64 | |
1892 // the whole long is written but de-opt'ing will have to extract | |
1893 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1894 #ifdef _LP64 | |
1895 const bool Matcher::int_in_long = true; | |
1896 #else | |
1897 const bool Matcher::int_in_long = false; | |
1898 #endif | |
1899 | |
1900 // Return whether or not this register is ever used as an argument. This | |
1901 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1902 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1903 // arguments in those registers not be available to the callee. | |
1904 bool Matcher::can_be_java_arg( int reg ) { | |
1905 // Standard sparc 6 args in registers | |
1906 if( reg == R_I0_num || | |
1907 reg == R_I1_num || | |
1908 reg == R_I2_num || | |
1909 reg == R_I3_num || | |
1910 reg == R_I4_num || | |
1911 reg == R_I5_num ) return true; | |
1912 #ifdef _LP64 | |
1913 // 64-bit builds can pass 64-bit pointers and longs in | |
1914 // the high I registers | |
1915 if( reg == R_I0H_num || | |
1916 reg == R_I1H_num || | |
1917 reg == R_I2H_num || | |
1918 reg == R_I3H_num || | |
1919 reg == R_I4H_num || | |
1920 reg == R_I5H_num ) return true; | |
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1921 |
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1922 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1923 return true; |
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1924 } |
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1925 |
0 | 1926 #else |
1927 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1928 // Longs cannot be passed in O regs, because O regs become I regs | |
1929 // after a 'save' and I regs get their high bits chopped off on | |
1930 // interrupt. | |
1931 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1932 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1933 #endif | |
1934 // A few float args in registers | |
1935 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1936 | |
1937 return false; | |
1938 } | |
1939 | |
1940 bool Matcher::is_spillable_arg( int reg ) { | |
1941 return can_be_java_arg(reg); | |
1942 } | |
1943 | |
1914
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1944 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1945 // Use hardware SDIVX instruction when it is |
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1946 // faster than a code which use multiply. |
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1947 return VM_Version::has_fast_idiv(); |
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1948 } |
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1949 |
0 | 1950 // Register for DIVI projection of divmodI |
1951 RegMask Matcher::divI_proj_mask() { | |
1952 ShouldNotReachHere(); | |
1953 return RegMask(); | |
1954 } | |
1955 | |
1956 // Register for MODI projection of divmodI | |
1957 RegMask Matcher::modI_proj_mask() { | |
1958 ShouldNotReachHere(); | |
1959 return RegMask(); | |
1960 } | |
1961 | |
1962 // Register for DIVL projection of divmodL | |
1963 RegMask Matcher::divL_proj_mask() { | |
1964 ShouldNotReachHere(); | |
1965 return RegMask(); | |
1966 } | |
1967 | |
1968 // Register for MODL projection of divmodL | |
1969 RegMask Matcher::modL_proj_mask() { | |
1970 ShouldNotReachHere(); | |
1971 return RegMask(); | |
1972 } | |
1973 | |
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1974 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1567 | 1975 return L7_REGP_mask; |
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1976 } |
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1977 |
0 | 1978 %} |
1979 | |
1980 | |
1981 // The intptr_t operand types, defined by textual substitution. | |
1982 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
1983 #ifdef _LP64 | |
824 | 1984 #define immX immL |
1985 #define immX13 immL13 | |
1986 #define immX13m7 immL13m7 | |
1987 #define iRegX iRegL | |
1988 #define g1RegX g1RegL | |
0 | 1989 #else |
824 | 1990 #define immX immI |
1991 #define immX13 immI13 | |
1992 #define immX13m7 immI13m7 | |
1993 #define iRegX iRegI | |
1994 #define g1RegX g1RegI | |
0 | 1995 #endif |
1996 | |
1997 //----------ENCODING BLOCK----------------------------------------------------- | |
1998 // This block specifies the encoding classes used by the compiler to output | |
1999 // byte streams. Encoding classes are parameterized macros used by | |
2000 // Machine Instruction Nodes in order to generate the bit encoding of the | |
2001 // instruction. Operands specify their base encoding interface with the | |
2002 // interface keyword. There are currently supported four interfaces, | |
2003 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
2004 // operand to generate a function which returns its register number when | |
2005 // queried. CONST_INTER causes an operand to generate a function which | |
2006 // returns the value of the constant when queried. MEMORY_INTER causes an | |
2007 // operand to generate four functions which return the Base Register, the | |
2008 // Index Register, the Scale Value, and the Offset Value of the operand when | |
2009 // queried. COND_INTER causes an operand to generate six functions which | |
2010 // return the encoding code (ie - encoding bits for the instruction) | |
2011 // associated with each basic boolean condition for a conditional instruction. | |
2012 // | |
2013 // Instructions specify two basic values for encoding. Again, a function | |
2014 // is available to check if the constant displacement is an oop. They use the | |
2015 // ins_encode keyword to specify their encoding classes (which must be | |
2016 // a sequence of enc_class names, and their parameters, specified in | |
2017 // the encoding block), and they use the | |
2018 // opcode keyword to specify, in order, their primary, secondary, and | |
2019 // tertiary opcode. Only the opcode sections which a particular instruction | |
2020 // needs for encoding need to be specified. | |
2021 encode %{ | |
2022 enc_class enc_untested %{ | |
2023 #ifdef ASSERT | |
2024 MacroAssembler _masm(&cbuf); | |
2025 __ untested("encoding"); | |
2026 #endif | |
2027 %} | |
2028 | |
2029 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
2030 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
2031 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
2032 %} | |
2033 | |
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2034 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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2035 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2036 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2037 %} |
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2038 |
0 | 2039 enc_class form3_mem_prefetch_read( memory mem ) %{ |
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2040 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2041 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2042 %} | |
2043 | |
2044 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
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2045 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2046 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2047 %} | |
2048 | |
2049 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
2050 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
2051 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
2052 guarantee($mem$$index == R_G0_enc, "double index?"); | |
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2053 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2054 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 2055 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2056 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
2057 %} | |
2058 | |
2059 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
2060 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
2061 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
2062 guarantee($mem$$index == R_G0_enc, "double index?"); | |
2063 // Load long with 2 instructions | |
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2064 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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2065 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 2066 %} |
2067 | |
2068 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
2069 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
2070 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
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2071 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 2072 %} |
2073 | |
2074 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
2075 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2076 if( $rs2$$reg != $rd$$reg ) | |
2077 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2078 %} | |
2079 | |
2080 // Target lo half of long | |
2081 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
2082 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2083 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
2084 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2085 %} | |
2086 | |
2087 // Source lo half of long | |
2088 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2089 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2090 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2091 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2092 %} | |
2093 | |
2094 // Target hi half of long | |
2095 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2096 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2097 %} | |
2098 | |
2099 // Source lo half of long, and leave it sign extended. | |
2100 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2101 // Sign extend low half | |
2102 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2103 %} | |
2104 | |
2105 // Source hi half of long, and leave it sign extended. | |
2106 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2107 // Shift high half to low half | |
2108 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2109 %} | |
2110 | |
2111 // Source hi half of long | |
2112 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2113 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2114 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2115 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2116 %} | |
2117 | |
2118 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2119 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2120 %} | |
2121 | |
2122 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2123 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2124 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2125 %} | |
2126 | |
2127 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2128 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2129 // clear if nothing else is happening | |
2130 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2131 // blt,a,pn done | |
2132 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2133 // mov dst,-1 in delay slot | |
2134 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2135 %} | |
2136 | |
2137 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2138 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2139 %} | |
2140 | |
2141 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2142 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2143 %} | |
2144 | |
2145 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2146 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2147 %} | |
2148 | |
2149 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2150 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2151 %} | |
2152 | |
2153 enc_class move_return_pc_to_o1() %{ | |
2154 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2155 %} | |
2156 | |
2157 #ifdef _LP64 | |
2158 /* %%% merge with enc_to_bool */ | |
2159 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2160 MacroAssembler _masm(&cbuf); | |
2161 | |
2162 Register src_reg = reg_to_register_object($src$$reg); | |
2163 Register dst_reg = reg_to_register_object($dst$$reg); | |
2164 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2165 %} | |
2166 #endif | |
2167 | |
2168 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2169 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2170 MacroAssembler _masm(&cbuf); | |
2171 | |
2172 Register p_reg = reg_to_register_object($p$$reg); | |
2173 Register q_reg = reg_to_register_object($q$$reg); | |
2174 Register y_reg = reg_to_register_object($y$$reg); | |
2175 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2176 | |
2177 __ subcc( p_reg, q_reg, p_reg ); | |
2178 __ add ( p_reg, y_reg, tmp_reg ); | |
2179 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2180 %} | |
2181 | |
2182 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2183 // fcmp %fcc0,$src,$src | |
2184 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2185 // branch %fcc0 not-nan, predict taken | |
2186 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2187 // fdtoi $src,$dst | |
2188 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2189 // fitos $dst,$dst (if nan) | |
2190 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2191 // clear $dst (if nan) | |
2192 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2193 // carry on here... | |
2194 %} | |
2195 | |
2196 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2197 // fcmp %fcc0,$src,$src check for NAN | |
2198 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2199 // branch %fcc0 not-nan, predict taken | |
2200 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2201 // fdtox $src,$dst convert in delay slot | |
2202 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2203 // fxtod $dst,$dst (if nan) | |
2204 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2205 // clear $dst (if nan) | |
2206 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2207 // carry on here... | |
2208 %} | |
2209 | |
2210 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2211 // fcmps %fcc0,$src,$src | |
2212 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2213 // branch %fcc0 not-nan, predict taken | |
2214 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2215 // fstoi $src,$dst | |
2216 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2217 // fitos $dst,$dst (if nan) | |
2218 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2219 // clear $dst (if nan) | |
2220 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2221 // carry on here... | |
2222 %} | |
2223 | |
2224 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2225 // fcmps %fcc0,$src,$src | |
2226 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2227 // branch %fcc0 not-nan, predict taken | |
2228 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2229 // fstox $src,$dst | |
2230 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2231 // fxtod $dst,$dst (if nan) | |
2232 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2233 // clear $dst (if nan) | |
2234 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2235 // carry on here... | |
2236 %} | |
2237 | |
2238 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2239 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2240 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2241 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2242 | |
2243 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2244 | |
2245 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2246 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2247 | |
2248 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2249 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2250 %} | |
2251 | |
2252 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2253 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2254 %} | |
2255 | |
2256 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2257 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2258 %} | |
2259 | |
2260 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2261 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2262 %} | |
2263 | |
2264 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2265 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2266 %} | |
2267 | |
2268 // Encloding class for traceable jumps | |
2269 enc_class form_jmpl(g3RegP dest) %{ | |
2270 emit_jmpl(cbuf, $dest$$reg); | |
2271 %} | |
2272 | |
2273 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2274 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2275 %} | |
2276 | |
2277 enc_class form2_nop() %{ | |
2278 emit_nop(cbuf); | |
2279 %} | |
2280 | |
2281 enc_class form2_illtrap() %{ | |
2282 emit_illtrap(cbuf); | |
2283 %} | |
2284 | |
2285 | |
2286 // Compare longs and convert into -1, 0, 1. | |
2287 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2288 // CMP $src1,$src2 | |
2289 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2290 // blt,a,pn done | |
2291 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2292 // mov dst,-1 in delay slot | |
2293 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2294 // bgt,a,pn done | |
2295 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2296 // mov dst,1 in delay slot | |
2297 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2298 // CLR $dst | |
2299 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2300 %} | |
2301 | |
2302 enc_class enc_PartialSubtypeCheck() %{ | |
2303 MacroAssembler _masm(&cbuf); | |
2304 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2305 __ delayed()->nop(); | |
2306 %} | |
2307 | |
2308 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
2309 MacroAssembler _masm(&cbuf); | |
2310 Label &L = *($labl$$label); | |
2311 Assembler::Predict predict_taken = | |
2312 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2313 | |
2314 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
2315 __ delayed()->nop(); | |
2316 %} | |
2317 | |
2318 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
2319 MacroAssembler _masm(&cbuf); | |
2320 Label &L = *($labl$$label); | |
2321 Assembler::Predict predict_taken = | |
2322 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2323 | |
2324 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
2325 __ delayed()->nop(); | |
2326 %} | |
2327 | |
2328 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
2329 MacroAssembler _masm(&cbuf); | |
2330 Label &L = *($labl$$label); | |
2331 Assembler::Predict predict_taken = | |
2332 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2333 | |
2334 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
2335 __ delayed()->nop(); | |
2336 %} | |
2337 | |
2338 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
2339 MacroAssembler _masm(&cbuf); | |
2340 Label &L = *($labl$$label); | |
2341 Assembler::Predict predict_taken = | |
2342 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2343 | |
2344 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
2345 __ delayed()->nop(); | |
2346 %} | |
2347 | |
2348 enc_class enc_ba( Label labl ) %{ | |
2349 MacroAssembler _masm(&cbuf); | |
2350 Label &L = *($labl$$label); | |
2351 __ ba(false, L); | |
2352 __ delayed()->nop(); | |
2353 %} | |
2354 | |
2355 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
2356 MacroAssembler _masm(&cbuf); | |
2357 Label &L = *$labl$$label; | |
2358 Assembler::Predict predict_taken = | |
2359 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2360 | |
2361 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
2362 __ delayed()->nop(); | |
2363 %} | |
2364 | |
2365 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2366 int op = (Assembler::arith_op << 30) | | |
2367 ($dst$$reg << 25) | | |
2368 (Assembler::movcc_op3 << 19) | | |
2369 (1 << 18) | // cc2 bit for 'icc' | |
2370 ($cmp$$cmpcode << 14) | | |
2371 (0 << 13) | // select register move | |
2372 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2373 ($src$$reg << 0); | |
1748 | 2374 cbuf.insts()->emit_int32(op); |
0 | 2375 %} |
2376 | |
2377 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2378 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2379 int op = (Assembler::arith_op << 30) | | |
2380 ($dst$$reg << 25) | | |
2381 (Assembler::movcc_op3 << 19) | | |
2382 (1 << 18) | // cc2 bit for 'icc' | |
2383 ($cmp$$cmpcode << 14) | | |
2384 (1 << 13) | // select immediate move | |
2385 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2386 (simm11 << 0); | |
1748 | 2387 cbuf.insts()->emit_int32(op); |
0 | 2388 %} |
2389 | |
2390 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2391 int op = (Assembler::arith_op << 30) | | |
2392 ($dst$$reg << 25) | | |
2393 (Assembler::movcc_op3 << 19) | | |
2394 (0 << 18) | // cc2 bit for 'fccX' | |
2395 ($cmp$$cmpcode << 14) | | |
2396 (0 << 13) | // select register move | |
2397 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2398 ($src$$reg << 0); | |
1748 | 2399 cbuf.insts()->emit_int32(op); |
0 | 2400 %} |
2401 | |
2402 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2403 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2404 int op = (Assembler::arith_op << 30) | | |
2405 ($dst$$reg << 25) | | |
2406 (Assembler::movcc_op3 << 19) | | |
2407 (0 << 18) | // cc2 bit for 'fccX' | |
2408 ($cmp$$cmpcode << 14) | | |
2409 (1 << 13) | // select immediate move | |
2410 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2411 (simm11 << 0); | |
1748 | 2412 cbuf.insts()->emit_int32(op); |
0 | 2413 %} |
2414 | |
2415 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2416 int op = (Assembler::arith_op << 30) | | |
2417 ($dst$$reg << 25) | | |
2418 (Assembler::fpop2_op3 << 19) | | |
2419 (0 << 18) | | |
2420 ($cmp$$cmpcode << 14) | | |
2421 (1 << 13) | // select register move | |
2422 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2423 ($primary << 5) | // select single, double or quad | |
2424 ($src$$reg << 0); | |
1748 | 2425 cbuf.insts()->emit_int32(op); |
0 | 2426 %} |
2427 | |
2428 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2429 int op = (Assembler::arith_op << 30) | | |
2430 ($dst$$reg << 25) | | |
2431 (Assembler::fpop2_op3 << 19) | | |
2432 (0 << 18) | | |
2433 ($cmp$$cmpcode << 14) | | |
2434 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2435 ($primary << 5) | // select single, double or quad | |
2436 ($src$$reg << 0); | |
1748 | 2437 cbuf.insts()->emit_int32(op); |
0 | 2438 %} |
2439 | |
2440 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2441 // the condition comes from opcode-field instead of an argument. | |
2442 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2443 int op = (Assembler::arith_op << 30) | | |
2444 ($dst$$reg << 25) | | |
2445 (Assembler::movcc_op3 << 19) | | |
2446 (1 << 18) | // cc2 bit for 'icc' | |
2447 ($primary << 14) | | |
2448 (0 << 13) | // select register move | |
2449 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2450 ($src$$reg << 0); | |
1748 | 2451 cbuf.insts()->emit_int32(op); |
0 | 2452 %} |
2453 | |
2454 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2455 int op = (Assembler::arith_op << 30) | | |
2456 ($dst$$reg << 25) | | |
2457 (Assembler::movcc_op3 << 19) | | |
2458 (6 << 16) | // cc2 bit for 'xcc' | |
2459 ($primary << 14) | | |
2460 (0 << 13) | // select register move | |
2461 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2462 ($src$$reg << 0); | |
1748 | 2463 cbuf.insts()->emit_int32(op); |
0 | 2464 %} |
2465 | |
2466 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2467 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2468 %} | |
2469 | |
2470 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2471 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2472 %} | |
2473 | |
2474 enc_class Set32( immI src, iRegI rd ) %{ | |
2475 MacroAssembler _masm(&cbuf); | |
2476 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2477 %} | |
2478 | |
2479 enc_class call_epilog %{ | |
2480 if( VerifyStackAtCalls ) { | |
2481 MacroAssembler _masm(&cbuf); | |
2482 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2483 Register temp_reg = G3; | |
2484 __ add(SP, framesize, temp_reg); | |
2485 __ cmp(temp_reg, FP); | |
2486 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2487 } | |
2488 %} | |
2489 | |
2490 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2491 // to G1 so the register allocator will not have to deal with the misaligned register | |
2492 // pair. | |
2493 enc_class adjust_long_from_native_call %{ | |
2494 #ifndef _LP64 | |
2495 if (returns_long()) { | |
2496 // sllx O0,32,O0 | |
2497 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2498 // srl O1,0,O1 | |
2499 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2500 // or O0,O1,G1 | |
2501 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2502 } | |
2503 #endif | |
2504 %} | |
2505 | |
2506 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2507 // CALL directly to the runtime | |
2508 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2509 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
2510 /*preserve_g2=*/true, /*force far call*/true); | |
2511 %} | |
2512 | |
1567 | 2513 enc_class preserve_SP %{ |
2514 MacroAssembler _masm(&cbuf); | |
2515 __ mov(SP, L7_mh_SP_save); | |
2516 %} | |
2517 | |
2518 enc_class restore_SP %{ | |
2519 MacroAssembler _masm(&cbuf); | |
2520 __ mov(L7_mh_SP_save, SP); | |
2521 %} | |
2522 | |
0 | 2523 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2524 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2525 // who we intended to call. | |
2526 if ( !_method ) { | |
2527 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
2528 } else if (_optimized_virtual) { | |
2529 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2530 } else { | |
2531 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2532 } | |
2533 if( _method ) { // Emit stub for static call | |
2534 emit_java_to_interp(cbuf); | |
2535 } | |
2536 %} | |
2537 | |
2538 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2539 MacroAssembler _masm(&cbuf); | |
2540 __ set_inst_mark(); | |
2541 int vtable_index = this->_vtable_index; | |
2542 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2543 if (vtable_index < 0) { | |
2544 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
2545 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
2546 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2547 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2548 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
2549 // !!!!! | |
2550 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
2551 // emit_call_dynamic_prologue( cbuf ); | |
2552 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
2553 | |
2554 address virtual_call_oop_addr = __ inst_mark(); | |
2555 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2556 // who we intended to call. | |
2557 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
2558 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
2559 } else { | |
2560 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2561 // Just go thru the vtable | |
2562 // get receiver klass (receiver already checked for non-null) | |
2563 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2564 int off = __ offset(); | |
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2565 __ load_klass(O0, G3_scratch); |
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2566 int klass_load_size; |
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2567 if (UseCompressedOops) { |
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2568 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2569 if (Universe::narrow_oop_base() == NULL) |
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2570 klass_load_size = 2*BytesPerInstWord; |
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2571 else |
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2572 klass_load_size = 3*BytesPerInstWord; |
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2573 } else { |
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2574 klass_load_size = 1*BytesPerInstWord; |
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2575 } |
0 | 2576 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
2577 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
2578 if( __ is_simm13(v_off) ) { | |
2579 __ ld_ptr(G3, v_off, G5_method); | |
2580 } else { | |
2581 // Generate 2 instructions | |
2582 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2583 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2584 // ld_ptr, set_hi, set | |
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2585 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2586 "Unexpected instruction size(s)"); |
0 | 2587 __ ld_ptr(G3, G5_method, G5_method); |
2588 } | |
2589 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2590 // However it may very well end up in handle_wrong_method if the | |
2591 // method is abstract for the particular class. | |
2592 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
2593 // jump to target (either compiled code or c2iadapter) | |
2594 __ jmpl(G3_scratch, G0, O7); | |
2595 __ delayed()->nop(); | |
2596 } | |
2597 %} | |
2598 | |
2599 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2600 MacroAssembler _masm(&cbuf); | |
2601 | |
2602 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2603 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2604 // we might be calling a C2I adapter which needs it. | |
2605 | |
2606 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2607 // Load nmethod | |
2608 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
2609 | |
2610 // CALL to compiled java, indirect the contents of G3 | |
2611 __ set_inst_mark(); | |
2612 __ callr(temp_reg, G0); | |
2613 __ delayed()->nop(); | |
2614 %} | |
2615 | |
2616 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2617 MacroAssembler _masm(&cbuf); | |
2618 Register Rdividend = reg_to_register_object($src1$$reg); | |
2619 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2620 Register Rresult = reg_to_register_object($dst$$reg); | |
2621 | |
2622 __ sra(Rdivisor, 0, Rdivisor); | |
2623 __ sra(Rdividend, 0, Rdividend); | |
2624 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2625 %} | |
2626 | |
2627 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2628 MacroAssembler _masm(&cbuf); | |
2629 | |
2630 Register Rdividend = reg_to_register_object($src1$$reg); | |
2631 int divisor = $imm$$constant; | |
2632 Register Rresult = reg_to_register_object($dst$$reg); | |
2633 | |
2634 __ sra(Rdividend, 0, Rdividend); | |
2635 __ sdivx(Rdividend, divisor, Rresult); | |
2636 %} | |
2637 | |
2638 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2639 MacroAssembler _masm(&cbuf); | |
2640 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2641 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2642 Register Rdst = reg_to_register_object($dst$$reg); | |
2643 | |
2644 __ sra( Rsrc1, 0, Rsrc1 ); | |
2645 __ sra( Rsrc2, 0, Rsrc2 ); | |
2646 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2647 __ srlx( Rdst, 32, Rdst ); | |
2648 %} | |
2649 | |
2650 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2651 MacroAssembler _masm(&cbuf); | |
2652 Register Rdividend = reg_to_register_object($src1$$reg); | |
2653 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2654 Register Rresult = reg_to_register_object($dst$$reg); | |
2655 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2656 | |
2657 assert(Rdividend != Rscratch, ""); | |
2658 assert(Rdivisor != Rscratch, ""); | |
2659 | |
2660 __ sra(Rdividend, 0, Rdividend); | |
2661 __ sra(Rdivisor, 0, Rdivisor); | |
2662 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2663 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2664 __ sub(Rdividend, Rscratch, Rresult); | |
2665 %} | |
2666 | |
2667 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2668 MacroAssembler _masm(&cbuf); | |
2669 | |
2670 Register Rdividend = reg_to_register_object($src1$$reg); | |
2671 int divisor = $imm$$constant; | |
2672 Register Rresult = reg_to_register_object($dst$$reg); | |
2673 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2674 | |
2675 assert(Rdividend != Rscratch, ""); | |
2676 | |
2677 __ sra(Rdividend, 0, Rdividend); | |
2678 __ sdivx(Rdividend, divisor, Rscratch); | |
2679 __ mulx(Rscratch, divisor, Rscratch); | |
2680 __ sub(Rdividend, Rscratch, Rresult); | |
2681 %} | |
2682 | |
2683 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2684 MacroAssembler _masm(&cbuf); | |
2685 | |
2686 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2687 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2688 | |
2689 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2690 %} | |
2691 | |
2692 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2693 MacroAssembler _masm(&cbuf); | |
2694 | |
2695 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2696 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2697 | |
2698 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2699 %} | |
2700 | |
2701 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2702 MacroAssembler _masm(&cbuf); | |
2703 | |
2704 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2705 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2706 | |
2707 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2708 %} | |
2709 | |
2710 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2711 MacroAssembler _masm(&cbuf); | |
2712 | |
2713 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2714 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2715 | |
2716 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2717 %} | |
2718 | |
2719 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2720 MacroAssembler _masm(&cbuf); | |
2721 | |
2722 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2723 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2724 | |
2725 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2726 %} | |
2727 | |
2728 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2729 MacroAssembler _masm(&cbuf); | |
2730 | |
2731 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2732 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2733 | |
2734 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2735 %} | |
2736 | |
2737 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2738 MacroAssembler _masm(&cbuf); | |
2739 | |
2740 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2741 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2742 | |
2743 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2744 %} | |
2745 | |
2746 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2747 MacroAssembler _masm(&cbuf); | |
2748 | |
2749 Register Roop = reg_to_register_object($oop$$reg); | |
2750 Register Rbox = reg_to_register_object($box$$reg); | |
2751 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2752 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2753 | |
2754 assert(Roop != Rscratch, ""); | |
2755 assert(Roop != Rmark, ""); | |
2756 assert(Rbox != Rscratch, ""); | |
2757 assert(Rbox != Rmark, ""); | |
2758 | |
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2759 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2760 %} |
2761 | |
2762 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2763 MacroAssembler _masm(&cbuf); | |
2764 | |
2765 Register Roop = reg_to_register_object($oop$$reg); | |
2766 Register Rbox = reg_to_register_object($box$$reg); | |
2767 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2768 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2769 | |
2770 assert(Roop != Rscratch, ""); | |
2771 assert(Roop != Rmark, ""); | |
2772 assert(Rbox != Rscratch, ""); | |
2773 assert(Rbox != Rmark, ""); | |
2774 | |
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2775 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2776 %} |
2777 | |
2778 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2779 MacroAssembler _masm(&cbuf); | |
2780 Register Rmem = reg_to_register_object($mem$$reg); | |
2781 Register Rold = reg_to_register_object($old$$reg); | |
2782 Register Rnew = reg_to_register_object($new$$reg); | |
2783 | |
2784 // casx_under_lock picks 1 of 3 encodings: | |
2785 // For 32-bit pointers you get a 32-bit CAS | |
2786 // For 64-bit pointers you get a 64-bit CASX | |
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2787 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2788 __ cmp( Rold, Rnew ); |
2789 %} | |
2790 | |
2791 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2792 Register Rmem = reg_to_register_object($mem$$reg); | |
2793 Register Rold = reg_to_register_object($old$$reg); | |
2794 Register Rnew = reg_to_register_object($new$$reg); | |
2795 | |
2796 MacroAssembler _masm(&cbuf); | |
2797 __ mov(Rnew, O7); | |
2798 __ casx(Rmem, Rold, O7); | |
2799 __ cmp( Rold, O7 ); | |
2800 %} | |
2801 | |
2802 // raw int cas, used for compareAndSwap | |
2803 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2804 Register Rmem = reg_to_register_object($mem$$reg); | |
2805 Register Rold = reg_to_register_object($old$$reg); | |
2806 Register Rnew = reg_to_register_object($new$$reg); | |
2807 | |
2808 MacroAssembler _masm(&cbuf); | |
2809 __ mov(Rnew, O7); | |
2810 __ cas(Rmem, Rold, O7); | |
2811 __ cmp( Rold, O7 ); | |
2812 %} | |
2813 | |
2814 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2815 Register Rres = reg_to_register_object($res$$reg); | |
2816 | |
2817 MacroAssembler _masm(&cbuf); | |
2818 __ mov(1, Rres); | |
2819 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2820 %} | |
2821 | |
2822 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2823 Register Rres = reg_to_register_object($res$$reg); | |
2824 | |
2825 MacroAssembler _masm(&cbuf); | |
2826 __ mov(1, Rres); | |
2827 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2828 %} | |
2829 | |
2830 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2831 MacroAssembler _masm(&cbuf); | |
2832 Register Rdst = reg_to_register_object($dst$$reg); | |
2833 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2834 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2835 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2836 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2837 | |
2838 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2839 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2840 %} | |
2841 | |
2842 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
2843 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
2844 MacroAssembler _masm(&cbuf); | |
2845 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
2846 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
2847 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
2848 | |
2849 Label loop; | |
2850 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
2851 | |
2852 // Loop and clear, walking backwards through the array. | |
2853 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
2854 __ bind(loop); | |
2855 __ deccc(nof_bytes_tmp, 8); | |
2856 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
2857 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
2858 // %%%% this mini-loop must not cross a cache boundary! | |
2859 %} | |
2860 | |
2861 | |
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2862 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2863 Label Ldone, Lloop; |
2864 MacroAssembler _masm(&cbuf); | |
2865 | |
2866 Register str1_reg = reg_to_register_object($str1$$reg); | |
2867 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2868 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2869 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2870 Register result_reg = reg_to_register_object($result$$reg); |
2871 | |
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2872 assert(result_reg != str1_reg && |
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2873 result_reg != str2_reg && |
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2874 result_reg != cnt1_reg && |
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2875 result_reg != cnt2_reg , |
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2876 "need different registers"); |
0 | 2877 |
2878 // Compute the minimum of the string lengths(str1_reg) and the | |
2879 // difference of the string lengths (stack) | |
2880 | |
2881 // See if the lengths are different, and calculate min in str1_reg. | |
2882 // Stash diff in O7 in case we need it for a tie-breaker. | |
2883 Label Lskip; | |
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2884 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2885 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2886 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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2887 // cnt2 is shorter, so use its count: |
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2888 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2889 __ bind(Lskip); |
2890 | |
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2891 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2892 // Note: limit_reg holds the string length pre-scaled by 2 |
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2893 Register limit_reg = cnt1_reg; |
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2894 Register chr2_reg = cnt2_reg; |
0 | 2895 Register chr1_reg = result_reg; |
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2896 // str{12} are the base pointers |
0 | 2897 |
2898 // Is the minimum length zero? | |
2899 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2900 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2901 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2902 | |
2903 // Load first characters | |
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2904 __ lduh(str1_reg, 0, chr1_reg); |
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2905 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2906 |
2907 // Compare first characters | |
2908 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2909 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2910 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2911 __ delayed()->nop(); | |
2912 | |
2913 { | |
2914 // Check after comparing first character to see if strings are equivalent | |
2915 Label LSkip2; | |
2916 // Check if the strings start at same location | |
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2917 __ cmp(str1_reg, str2_reg); |
0 | 2918 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2919 __ delayed()->nop(); | |
2920 | |
2921 // Check if the length difference is zero (in O7) | |
2922 __ cmp(G0, O7); | |
2923 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2924 __ delayed()->mov(G0, result_reg); // result is zero | |
2925 | |
2926 // Strings might not be equal | |
2927 __ bind(LSkip2); | |
2928 } | |
2929 | |
2930 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2931 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2932 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2933 | |
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2934 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2935 __ add(str1_reg, limit_reg, str1_reg); |
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2936 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2937 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2938 | |
2939 // Compare the rest of the characters | |
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2940 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2941 __ bind(Lloop); |
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2942 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2943 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2944 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2945 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2946 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2947 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2948 // annul LDUH if branch is not taken to prevent access past end of string | |
2949 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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2950 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2951 |
2952 // If strings are equal up to min length, return the length difference. | |
2953 __ mov(O7, result_reg); | |
2954 | |
2955 // Otherwise, return the difference between the first mismatched chars. | |
2956 __ bind(Ldone); | |
2957 %} | |
2958 | |
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2959 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2960 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2961 MacroAssembler _masm(&cbuf); |
2962 | |
2963 Register str1_reg = reg_to_register_object($str1$$reg); | |
2964 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2965 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2966 Register tmp1_reg = O7; |
681 | 2967 Register result_reg = reg_to_register_object($result$$reg); |
2968 | |
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2969 assert(result_reg != str1_reg && |
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2970 result_reg != str2_reg && |
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2971 result_reg != cnt_reg && |
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2972 result_reg != tmp1_reg , |
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2973 "need different registers"); |
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2974 |
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2975 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2976 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2977 __ delayed()->add(G0, 1, result_reg); | |
2978 | |
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2979 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
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2980 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2981 |
681 | 2982 //rename registers |
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2983 Register limit_reg = cnt_reg; |
681 | 2984 Register chr1_reg = result_reg; |
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2985 Register chr2_reg = tmp1_reg; |
681 | 2986 |
2987 //check for alignment and position the pointers to the ends | |
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2988 __ or3(str1_reg, str2_reg, chr1_reg); |
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2989 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2990 // notZero means at least one not 4-byte aligned. |
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2991 // We could optimize the case when both arrays are not aligned |
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2992 // but it is not frequent case and it requires additional checks. |
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2993 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2994 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2995 |
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2996 // Compare char[] arrays aligned to 4 bytes. |
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2997 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2998 chr1_reg, chr2_reg, Ldone); |
681 | 2999 __ ba(false,Ldone); |
3000 __ delayed()->add(G0, 1, result_reg); | |
3001 | |
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3002 // char by char compare |
681 | 3003 __ bind(Lchar); |
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3004 __ add(str1_reg, limit_reg, str1_reg); |
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3005 __ add(str2_reg, limit_reg, str2_reg); |
681 | 3006 __ neg(limit_reg); //negate count |
3007 | |
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3008 __ lduh(str1_reg, limit_reg, chr1_reg); |
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3009 // Lchar_loop |
681 | 3010 __ bind(Lchar_loop); |
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3011 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 3012 __ cmp(chr1_reg, chr2_reg); |
3013 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3014 __ delayed()->mov(G0, result_reg); //not equal | |
3015 __ inccc(limit_reg, sizeof(jchar)); | |
3016 // annul LDUH if branch is not taken to prevent access past end of string | |
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3017 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3018 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 3019 |
3020 __ add(G0, 1, result_reg); //equal | |
3021 | |
3022 __ bind(Ldone); | |
3023 %} | |
3024 | |
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3025 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3026 Label Lvector, Ldone, Lloop; |
3027 MacroAssembler _masm(&cbuf); | |
3028 | |
3029 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3030 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3031 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
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3032 Register tmp2_reg = O7; |
681 | 3033 Register result_reg = reg_to_register_object($result$$reg); |
3034 | |
3035 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3036 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3037 | |
3038 // return true if the same array | |
3039 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3040 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3041 __ delayed()->add(G0, 1, result_reg); // equal |
3042 | |
3043 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3044 __ delayed()->mov(G0, result_reg); // not equal | |
3045 | |
3046 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3047 __ delayed()->mov(G0, result_reg); // not equal | |
3048 | |
3049 //load the lengths of arrays | |
727 | 3050 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3051 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3052 |
3053 // return false if the two arrays are not equal length | |
3054 __ cmp(tmp1_reg, tmp2_reg); | |
3055 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3056 __ delayed()->mov(G0, result_reg); // not equal | |
3057 | |
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3058 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
681 | 3059 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3060 | |
3061 // load array addresses | |
3062 __ add(ary1_reg, base_offset, ary1_reg); | |
3063 __ add(ary2_reg, base_offset, ary2_reg); | |
3064 | |
3065 // renaming registers | |
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3066 Register chr1_reg = result_reg; // for characters in ary1 |
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3067 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3068 Register limit_reg = tmp1_reg; // length |
3069 | |
3070 // set byte count | |
3071 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3072 |
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3073 // Compare char[] arrays aligned to 4 bytes. |
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3074 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3075 chr1_reg, chr2_reg, Ldone); |
681 | 3076 __ add(G0, 1, result_reg); // equals |
3077 | |
3078 __ bind(Ldone); | |
3079 %} | |
3080 | |
0 | 3081 enc_class enc_rethrow() %{ |
1748 | 3082 cbuf.set_insts_mark(); |
0 | 3083 Register temp_reg = G3; |
727 | 3084 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3085 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3086 MacroAssembler _masm(&cbuf); | |
3087 #ifdef ASSERT | |
3088 __ save_frame(0); | |
727 | 3089 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3090 __ sethi(last_rethrow_addrlit, L1); | |
3091 Address addr(L1, last_rethrow_addrlit.low10()); | |
0 | 3092 __ get_pc(L2); |
3093 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
727 | 3094 __ st_ptr(L2, addr); |
0 | 3095 __ restore(); |
3096 #endif | |
727 | 3097 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3098 __ delayed()->nop(); |
3099 %} | |
3100 | |
3101 enc_class emit_mem_nop() %{ | |
3102 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
1748 | 3103 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
0 | 3104 %} |
3105 | |
3106 enc_class emit_fadd_nop() %{ | |
3107 // Generates the instruction FMOVS f31,f31 | |
1748 | 3108 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
0 | 3109 %} |
3110 | |
3111 enc_class emit_br_nop() %{ | |
3112 // Generates the instruction BPN,PN . | |
1748 | 3113 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
0 | 3114 %} |
3115 | |
3116 enc_class enc_membar_acquire %{ | |
3117 MacroAssembler _masm(&cbuf); | |
3118 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3119 %} | |
3120 | |
3121 enc_class enc_membar_release %{ | |
3122 MacroAssembler _masm(&cbuf); | |
3123 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3124 %} | |
3125 | |
3126 enc_class enc_membar_volatile %{ | |
3127 MacroAssembler _masm(&cbuf); | |
3128 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3129 %} | |
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3130 |
0 | 3131 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
3132 MacroAssembler _masm(&cbuf); | |
3133 Register src_reg = reg_to_register_object($src$$reg); | |
3134 Register dst_reg = reg_to_register_object($dst$$reg); | |
3135 __ sllx(src_reg, 56, dst_reg); | |
3136 __ srlx(dst_reg, 8, O7); | |
3137 __ or3 (dst_reg, O7, dst_reg); | |
3138 __ srlx(dst_reg, 16, O7); | |
3139 __ or3 (dst_reg, O7, dst_reg); | |
3140 __ srlx(dst_reg, 32, O7); | |
3141 __ or3 (dst_reg, O7, dst_reg); | |
3142 %} | |
3143 | |
3144 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
3145 MacroAssembler _masm(&cbuf); | |
3146 Register src_reg = reg_to_register_object($src$$reg); | |
3147 Register dst_reg = reg_to_register_object($dst$$reg); | |
3148 __ sll(src_reg, 24, dst_reg); | |
3149 __ srl(dst_reg, 8, O7); | |
3150 __ or3(dst_reg, O7, dst_reg); | |
3151 __ srl(dst_reg, 16, O7); | |
3152 __ or3(dst_reg, O7, dst_reg); | |
3153 %} | |
3154 | |
3155 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
3156 MacroAssembler _masm(&cbuf); | |
3157 Register src_reg = reg_to_register_object($src$$reg); | |
3158 Register dst_reg = reg_to_register_object($dst$$reg); | |
3159 __ sllx(src_reg, 48, dst_reg); | |
3160 __ srlx(dst_reg, 16, O7); | |
3161 __ or3 (dst_reg, O7, dst_reg); | |
3162 __ srlx(dst_reg, 32, O7); | |
3163 __ or3 (dst_reg, O7, dst_reg); | |
3164 %} | |
3165 | |
3166 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
3167 MacroAssembler _masm(&cbuf); | |
3168 Register src_reg = reg_to_register_object($src$$reg); | |
3169 Register dst_reg = reg_to_register_object($dst$$reg); | |
3170 __ sllx(src_reg, 32, dst_reg); | |
3171 __ srlx(dst_reg, 32, O7); | |
3172 __ or3 (dst_reg, O7, dst_reg); | |
3173 %} | |
3174 | |
3175 %} | |
3176 | |
3177 //----------FRAME-------------------------------------------------------------- | |
3178 // Definition of frame structure and management information. | |
3179 // | |
3180 // S T A C K L A Y O U T Allocators stack-slot number | |
3181 // | (to get allocators register number | |
3182 // G Owned by | | v add VMRegImpl::stack0) | |
3183 // r CALLER | | | |
3184 // o | +--------+ pad to even-align allocators stack-slot | |
3185 // w V | pad0 | numbers; owned by CALLER | |
3186 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3187 // h ^ | in | 5 | |
3188 // | | args | 4 Holes in incoming args owned by SELF | |
3189 // | | | | 3 | |
3190 // | | +--------+ | |
3191 // V | | old out| Empty on Intel, window on Sparc | |
3192 // | old |preserve| Must be even aligned. | |
3193 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3194 // | | in | 3 area for Intel ret address | |
3195 // Owned by |preserve| Empty on Sparc. | |
3196 // SELF +--------+ | |
3197 // | | pad2 | 2 pad to align old SP | |
3198 // | +--------+ 1 | |
3199 // | | locks | 0 | |
3200 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3201 // | | pad1 | 11 pad to align new SP | |
3202 // | +--------+ | |
3203 // | | | 10 | |
3204 // | | spills | 9 spills | |
3205 // V | | 8 (pad0 slot for callee) | |
3206 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3207 // ^ | out | 7 | |
3208 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3209 // Owned by +--------+ | |
3210 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3211 // | new |preserve| Must be even-aligned. | |
3212 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3213 // | | | | |
3214 // | |
3215 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3216 // known from SELF's arguments and the Java calling convention. | |
3217 // Region 6-7 is determined per call site. | |
3218 // Note 2: If the calling convention leaves holes in the incoming argument | |
3219 // area, those holes are owned by SELF. Holes in the outgoing area | |
3220 // are owned by the CALLEE. Holes should not be nessecary in the | |
3221 // incoming area, as the Java calling convention is completely under | |
3222 // the control of the AD file. Doubles can be sorted and packed to | |
3223 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3224 // varargs C calling conventions. | |
3225 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3226 // even aligned with pad0 as needed. | |
3227 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3228 // region 6-11 is even aligned; it may be padded out more so that | |
3229 // the region from SP to FP meets the minimum stack alignment. | |
3230 | |
3231 frame %{ | |
3232 // What direction does stack grow in (assumed to be same for native & Java) | |
3233 stack_direction(TOWARDS_LOW); | |
3234 | |
3235 // These two registers define part of the calling convention | |
3236 // between compiled code and the interpreter. | |
3237 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
3238 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
3239 | |
3240 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3241 cisc_spilling_operand_name(indOffset); | |
3242 | |
3243 // Number of stack slots consumed by a Monitor enter | |
3244 #ifdef _LP64 | |
3245 sync_stack_slots(2); | |
3246 #else | |
3247 sync_stack_slots(1); | |
3248 #endif | |
3249 | |
3250 // Compiled code's Frame Pointer | |
3251 frame_pointer(R_SP); | |
3252 | |
3253 // Stack alignment requirement | |
3254 stack_alignment(StackAlignmentInBytes); | |
3255 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3256 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3257 | |
3258 // Number of stack slots between incoming argument block and the start of | |
3259 // a new frame. The PROLOG must add this many slots to the stack. The | |
3260 // EPILOG must remove this many slots. | |
3261 in_preserve_stack_slots(0); | |
3262 | |
3263 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3264 // for calls to C. Supports the var-args backing area for register parms. | |
3265 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3266 #ifdef _LP64 | |
3267 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3268 varargs_C_out_slots_killed(12); | |
3269 #else | |
3270 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3271 varargs_C_out_slots_killed( 7); | |
3272 #endif | |
3273 | |
3274 // The after-PROLOG location of the return address. Location of | |
3275 // return address specifies a type (REG or STACK) and a number | |
3276 // representing the register number (i.e. - use a register name) or | |
3277 // stack slot. | |
3278 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3279 | |
3280 // Body of function which returns an OptoRegs array locating | |
3281 // arguments either in registers or in stack slots for calling | |
3282 // java | |
3283 calling_convention %{ | |
3284 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3285 | |
3286 %} | |
3287 | |
3288 // Body of function which returns an OptoRegs array locating | |
3289 // arguments either in registers or in stack slots for callin | |
3290 // C. | |
3291 c_calling_convention %{ | |
3292 // This is obviously always outgoing | |
3293 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3294 %} | |
3295 | |
3296 // Location of native (C/C++) and interpreter return values. This is specified to | |
3297 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3298 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3299 // to and from the register pairs is done by the appropriate call and epilog | |
3300 // opcodes. This simplifies the register allocator. | |
3301 c_return_value %{ | |
3302 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3303 #ifdef _LP64 | |
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3304 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3305 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3306 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3307 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3308 #else // !_LP64 |
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3309 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3310 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3311 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3312 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3313 #endif |
3314 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3315 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3316 %} | |
3317 | |
3318 // Location of compiled Java return values. Same as C | |
3319 return_value %{ | |
3320 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3321 #ifdef _LP64 | |
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3322 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3323 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3324 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3325 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3326 #else // !_LP64 |
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3327 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3328 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3329 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3330 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3331 #endif |
3332 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3333 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3334 %} | |
3335 | |
3336 %} | |
3337 | |
3338 | |
3339 //----------ATTRIBUTES--------------------------------------------------------- | |
3340 //----------Operand Attributes------------------------------------------------- | |
3341 op_attrib op_cost(1); // Required cost attribute | |
3342 | |
3343 //----------Instruction Attributes--------------------------------------------- | |
3344 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3345 ins_attrib ins_size(32); // Required size attribute (in bits) | |
3346 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
3347 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
3348 // non-matching short branch variant of some | |
3349 // long branch? | |
3350 | |
3351 //----------OPERANDS----------------------------------------------------------- | |
3352 // Operand definitions must precede instruction definitions for correct parsing | |
3353 // in the ADLC because operands constitute user defined types which are used in | |
3354 // instruction definitions. | |
3355 | |
3356 //----------Simple Operands---------------------------------------------------- | |
3357 // Immediate Operands | |
3358 // Integer Immediate: 32-bit | |
3359 operand immI() %{ | |
3360 match(ConI); | |
3361 | |
3362 op_cost(0); | |
3363 // formats are generated automatically for constants and base registers | |
3364 format %{ %} | |
3365 interface(CONST_INTER); | |
3366 %} | |
3367 | |
824 | 3368 // Integer Immediate: 8-bit |
3369 operand immI8() %{ | |
3370 predicate(Assembler::is_simm(n->get_int(), 8)); | |
3371 match(ConI); | |
3372 op_cost(0); | |
3373 format %{ %} | |
3374 interface(CONST_INTER); | |
3375 %} | |
3376 | |
0 | 3377 // Integer Immediate: 13-bit |
3378 operand immI13() %{ | |
3379 predicate(Assembler::is_simm13(n->get_int())); | |
3380 match(ConI); | |
3381 op_cost(0); | |
3382 | |
3383 format %{ %} | |
3384 interface(CONST_INTER); | |
3385 %} | |
3386 | |
785 | 3387 // Integer Immediate: 13-bit minus 7 |
3388 operand immI13m7() %{ | |
3389 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3390 match(ConI); | |
3391 op_cost(0); | |
3392 | |
3393 format %{ %} | |
3394 interface(CONST_INTER); | |
3395 %} | |
3396 | |
824 | 3397 // Integer Immediate: 16-bit |
3398 operand immI16() %{ | |
3399 predicate(Assembler::is_simm(n->get_int(), 16)); | |
3400 match(ConI); | |
3401 op_cost(0); | |
3402 format %{ %} | |
3403 interface(CONST_INTER); | |
3404 %} | |
3405 | |
0 | 3406 // Unsigned (positive) Integer Immediate: 13-bit |
3407 operand immU13() %{ | |
3408 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3409 match(ConI); | |
3410 op_cost(0); | |
3411 | |
3412 format %{ %} | |
3413 interface(CONST_INTER); | |
3414 %} | |
3415 | |
3416 // Integer Immediate: 6-bit | |
3417 operand immU6() %{ | |
3418 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3419 match(ConI); | |
3420 op_cost(0); | |
3421 format %{ %} | |
3422 interface(CONST_INTER); | |
3423 %} | |
3424 | |
3425 // Integer Immediate: 11-bit | |
3426 operand immI11() %{ | |
3427 predicate(Assembler::is_simm(n->get_int(),11)); | |
3428 match(ConI); | |
3429 op_cost(0); | |
3430 format %{ %} | |
3431 interface(CONST_INTER); | |
3432 %} | |
3433 | |
3434 // Integer Immediate: 0-bit | |
3435 operand immI0() %{ | |
3436 predicate(n->get_int() == 0); | |
3437 match(ConI); | |
3438 op_cost(0); | |
3439 | |
3440 format %{ %} | |
3441 interface(CONST_INTER); | |
3442 %} | |
3443 | |
3444 // Integer Immediate: the value 10 | |
3445 operand immI10() %{ | |
3446 predicate(n->get_int() == 10); | |
3447 match(ConI); | |
3448 op_cost(0); | |
3449 | |
3450 format %{ %} | |
3451 interface(CONST_INTER); | |
3452 %} | |
3453 | |
3454 // Integer Immediate: the values 0-31 | |
3455 operand immU5() %{ | |
3456 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3457 match(ConI); | |
3458 op_cost(0); | |
3459 | |
3460 format %{ %} | |
3461 interface(CONST_INTER); | |
3462 %} | |
3463 | |
3464 // Integer Immediate: the values 1-31 | |
3465 operand immI_1_31() %{ | |
3466 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3467 match(ConI); | |
3468 op_cost(0); | |
3469 | |
3470 format %{ %} | |
3471 interface(CONST_INTER); | |
3472 %} | |
3473 | |
3474 // Integer Immediate: the values 32-63 | |
3475 operand immI_32_63() %{ | |
3476 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3477 match(ConI); | |
3478 op_cost(0); | |
3479 | |
3480 format %{ %} | |
3481 interface(CONST_INTER); | |
3482 %} | |
3483 | |
785 | 3484 // Immediates for special shifts (sign extend) |
3485 | |
3486 // Integer Immediate: the value 16 | |
3487 operand immI_16() %{ | |
3488 predicate(n->get_int() == 16); | |
3489 match(ConI); | |
3490 op_cost(0); | |
3491 | |
3492 format %{ %} | |
3493 interface(CONST_INTER); | |
3494 %} | |
3495 | |
3496 // Integer Immediate: the value 24 | |
3497 operand immI_24() %{ | |
3498 predicate(n->get_int() == 24); | |
3499 match(ConI); | |
3500 op_cost(0); | |
3501 | |
3502 format %{ %} | |
3503 interface(CONST_INTER); | |
3504 %} | |
3505 | |
0 | 3506 // Integer Immediate: the value 255 |
3507 operand immI_255() %{ | |
3508 predicate( n->get_int() == 255 ); | |
3509 match(ConI); | |
3510 op_cost(0); | |
3511 | |
3512 format %{ %} | |
3513 interface(CONST_INTER); | |
3514 %} | |
3515 | |
785 | 3516 // Integer Immediate: the value 65535 |
3517 operand immI_65535() %{ | |
3518 predicate(n->get_int() == 65535); | |
3519 match(ConI); | |
3520 op_cost(0); | |
3521 | |
3522 format %{ %} | |
3523 interface(CONST_INTER); | |
3524 %} | |
3525 | |
0 | 3526 // Long Immediate: the value FF |
3527 operand immL_FF() %{ | |
3528 predicate( n->get_long() == 0xFFL ); | |
3529 match(ConL); | |
3530 op_cost(0); | |
3531 | |
3532 format %{ %} | |
3533 interface(CONST_INTER); | |
3534 %} | |
3535 | |
3536 // Long Immediate: the value FFFF | |
3537 operand immL_FFFF() %{ | |
3538 predicate( n->get_long() == 0xFFFFL ); | |
3539 match(ConL); | |
3540 op_cost(0); | |
3541 | |
3542 format %{ %} | |
3543 interface(CONST_INTER); | |
3544 %} | |
3545 | |
3546 // Pointer Immediate: 32 or 64-bit | |
3547 operand immP() %{ | |
3548 match(ConP); | |
3549 | |
3550 op_cost(5); | |
3551 // formats are generated automatically for constants and base registers | |
3552 format %{ %} | |
3553 interface(CONST_INTER); | |
3554 %} | |
3555 | |
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3556 #ifdef _LP64 |
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3557 // Pointer Immediate: 64-bit |
2008 | 3558 operand immP_set() %{ |
2080 | 3559 predicate(!VM_Version::is_niagara_plus()); |
2008 | 3560 match(ConP); |
3561 | |
3562 op_cost(5); | |
3563 // formats are generated automatically for constants and base registers | |
3564 format %{ %} | |
3565 interface(CONST_INTER); | |
3566 %} | |
3567 | |
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3568 // Pointer Immediate: 64-bit |
2008 | 3569 // From Niagara2 processors on a load should be better than materializing. |
3570 operand immP_load() %{ | |
2080 | 3571 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
2008 | 3572 match(ConP); |
3573 | |
3574 op_cost(5); | |
3575 // formats are generated automatically for constants and base registers | |
3576 format %{ %} | |
3577 interface(CONST_INTER); | |
3578 %} | |
3579 | |
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3580 // Pointer Immediate: 64-bit |
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3581 operand immP_no_oop_cheap() %{ |
2080 | 3582 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
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3583 match(ConP); |
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3584 |
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3585 op_cost(5); |
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3586 // formats are generated automatically for constants and base registers |
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3587 format %{ %} |
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3588 interface(CONST_INTER); |
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3589 %} |
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3590 #endif |
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3591 |
0 | 3592 operand immP13() %{ |
3593 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3594 match(ConP); | |
3595 op_cost(0); | |
3596 | |
3597 format %{ %} | |
3598 interface(CONST_INTER); | |
3599 %} | |
3600 | |
3601 operand immP0() %{ | |
3602 predicate(n->get_ptr() == 0); | |
3603 match(ConP); | |
3604 op_cost(0); | |
3605 | |
3606 format %{ %} | |
3607 interface(CONST_INTER); | |
3608 %} | |
3609 | |
3610 operand immP_poll() %{ | |
3611 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3612 match(ConP); | |
3613 | |
3614 // formats are generated automatically for constants and base registers | |
3615 format %{ %} | |
3616 interface(CONST_INTER); | |
3617 %} | |
3618 | |
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3619 // Pointer Immediate |
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3620 operand immN() |
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3621 %{ |
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3622 match(ConN); |
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3623 |
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3624 op_cost(10); |
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3625 format %{ %} |
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3626 interface(CONST_INTER); |
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3627 %} |
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3628 |
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3629 // NULL Pointer Immediate |
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3630 operand immN0() |
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3631 %{ |
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3632 predicate(n->get_narrowcon() == 0); |
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3633 match(ConN); |
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3634 |
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3635 op_cost(0); |
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3636 format %{ %} |
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3637 interface(CONST_INTER); |
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3638 %} |
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3639 |
0 | 3640 operand immL() %{ |
3641 match(ConL); | |
3642 op_cost(40); | |
3643 // formats are generated automatically for constants and base registers | |
3644 format %{ %} | |
3645 interface(CONST_INTER); | |
3646 %} | |
3647 | |
3648 operand immL0() %{ | |
3649 predicate(n->get_long() == 0L); | |
3650 match(ConL); | |
3651 op_cost(0); | |
3652 // formats are generated automatically for constants and base registers | |
3653 format %{ %} | |
3654 interface(CONST_INTER); | |
3655 %} | |
3656 | |
3657 // Long Immediate: 13-bit | |
3658 operand immL13() %{ | |
3659 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3660 match(ConL); | |
3661 op_cost(0); | |
3662 | |
3663 format %{ %} | |
3664 interface(CONST_INTER); | |
3665 %} | |
3666 | |
785 | 3667 // Long Immediate: 13-bit minus 7 |
3668 operand immL13m7() %{ | |
3669 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3670 match(ConL); | |
3671 op_cost(0); | |
3672 | |
3673 format %{ %} | |
3674 interface(CONST_INTER); | |
3675 %} | |
3676 | |
0 | 3677 // Long Immediate: low 32-bit mask |
3678 operand immL_32bits() %{ | |
3679 predicate(n->get_long() == 0xFFFFFFFFL); | |
3680 match(ConL); | |
3681 op_cost(0); | |
3682 | |
3683 format %{ %} | |
3684 interface(CONST_INTER); | |
3685 %} | |
3686 | |
2008 | 3687 // Long Immediate: cheap (materialize in <= 3 instructions) |
3688 operand immL_cheap() %{ | |
2080 | 3689 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
2008 | 3690 match(ConL); |
3691 op_cost(0); | |
3692 | |
3693 format %{ %} | |
3694 interface(CONST_INTER); | |
3695 %} | |
3696 | |
3697 // Long Immediate: expensive (materialize in > 3 instructions) | |
3698 operand immL_expensive() %{ | |
2080 | 3699 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
2008 | 3700 match(ConL); |
3701 op_cost(0); | |
3702 | |
3703 format %{ %} | |
3704 interface(CONST_INTER); | |
3705 %} | |
3706 | |
0 | 3707 // Double Immediate |
3708 operand immD() %{ | |
3709 match(ConD); | |
3710 | |
3711 op_cost(40); | |
3712 format %{ %} | |
3713 interface(CONST_INTER); | |
3714 %} | |
3715 | |
3716 operand immD0() %{ | |
3717 #ifdef _LP64 | |
3718 // on 64-bit architectures this comparision is faster | |
3719 predicate(jlong_cast(n->getd()) == 0); | |
3720 #else | |
3721 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3722 #endif | |
3723 match(ConD); | |
3724 | |
3725 op_cost(0); | |
3726 format %{ %} | |
3727 interface(CONST_INTER); | |
3728 %} | |
3729 | |
3730 // Float Immediate | |
3731 operand immF() %{ | |
3732 match(ConF); | |
3733 | |
3734 op_cost(20); | |
3735 format %{ %} | |
3736 interface(CONST_INTER); | |
3737 %} | |
3738 | |
3739 // Float Immediate: 0 | |
3740 operand immF0() %{ | |
3741 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3742 match(ConF); | |
3743 | |
3744 op_cost(0); | |
3745 format %{ %} | |
3746 interface(CONST_INTER); | |
3747 %} | |
3748 | |
3749 // Integer Register Operands | |
3750 // Integer Register | |
3751 operand iRegI() %{ | |
3752 constraint(ALLOC_IN_RC(int_reg)); | |
3753 match(RegI); | |
3754 | |
3755 match(notemp_iRegI); | |
3756 match(g1RegI); | |
3757 match(o0RegI); | |
3758 match(iRegIsafe); | |
3759 | |
3760 format %{ %} | |
3761 interface(REG_INTER); | |
3762 %} | |
3763 | |
3764 operand notemp_iRegI() %{ | |
3765 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3766 match(RegI); | |
3767 | |
3768 match(o0RegI); | |
3769 | |
3770 format %{ %} | |
3771 interface(REG_INTER); | |
3772 %} | |
3773 | |
3774 operand o0RegI() %{ | |
3775 constraint(ALLOC_IN_RC(o0_regI)); | |
3776 match(iRegI); | |
3777 | |
3778 format %{ %} | |
3779 interface(REG_INTER); | |
3780 %} | |
3781 | |
3782 // Pointer Register | |
3783 operand iRegP() %{ | |
3784 constraint(ALLOC_IN_RC(ptr_reg)); | |
3785 match(RegP); | |
3786 | |
3787 match(lock_ptr_RegP); | |
3788 match(g1RegP); | |
3789 match(g2RegP); | |
3790 match(g3RegP); | |
3791 match(g4RegP); | |
3792 match(i0RegP); | |
3793 match(o0RegP); | |
3794 match(o1RegP); | |
3795 match(l7RegP); | |
3796 | |
3797 format %{ %} | |
3798 interface(REG_INTER); | |
3799 %} | |
3800 | |
3801 operand sp_ptr_RegP() %{ | |
3802 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3803 match(RegP); | |
3804 match(iRegP); | |
3805 | |
3806 format %{ %} | |
3807 interface(REG_INTER); | |
3808 %} | |
3809 | |
3810 operand lock_ptr_RegP() %{ | |
3811 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3812 match(RegP); | |
3813 match(i0RegP); | |
3814 match(o0RegP); | |
3815 match(o1RegP); | |
3816 match(l7RegP); | |
3817 | |
3818 format %{ %} | |
3819 interface(REG_INTER); | |
3820 %} | |
3821 | |
3822 operand g1RegP() %{ | |
3823 constraint(ALLOC_IN_RC(g1_regP)); | |
3824 match(iRegP); | |
3825 | |
3826 format %{ %} | |
3827 interface(REG_INTER); | |
3828 %} | |
3829 | |
3830 operand g2RegP() %{ | |
3831 constraint(ALLOC_IN_RC(g2_regP)); | |
3832 match(iRegP); | |
3833 | |
3834 format %{ %} | |
3835 interface(REG_INTER); | |
3836 %} | |
3837 | |
3838 operand g3RegP() %{ | |
3839 constraint(ALLOC_IN_RC(g3_regP)); | |
3840 match(iRegP); | |
3841 | |
3842 format %{ %} | |
3843 interface(REG_INTER); | |
3844 %} | |
3845 | |
3846 operand g1RegI() %{ | |
3847 constraint(ALLOC_IN_RC(g1_regI)); | |
3848 match(iRegI); | |
3849 | |
3850 format %{ %} | |
3851 interface(REG_INTER); | |
3852 %} | |
3853 | |
3854 operand g3RegI() %{ | |
3855 constraint(ALLOC_IN_RC(g3_regI)); | |
3856 match(iRegI); | |
3857 | |
3858 format %{ %} | |
3859 interface(REG_INTER); | |
3860 %} | |
3861 | |
3862 operand g4RegI() %{ | |
3863 constraint(ALLOC_IN_RC(g4_regI)); | |
3864 match(iRegI); | |
3865 | |
3866 format %{ %} | |
3867 interface(REG_INTER); | |
3868 %} | |
3869 | |
3870 operand g4RegP() %{ | |
3871 constraint(ALLOC_IN_RC(g4_regP)); | |
3872 match(iRegP); | |
3873 | |
3874 format %{ %} | |
3875 interface(REG_INTER); | |
3876 %} | |
3877 | |
3878 operand i0RegP() %{ | |
3879 constraint(ALLOC_IN_RC(i0_regP)); | |
3880 match(iRegP); | |
3881 | |
3882 format %{ %} | |
3883 interface(REG_INTER); | |
3884 %} | |
3885 | |
3886 operand o0RegP() %{ | |
3887 constraint(ALLOC_IN_RC(o0_regP)); | |
3888 match(iRegP); | |
3889 | |
3890 format %{ %} | |
3891 interface(REG_INTER); | |
3892 %} | |
3893 | |
3894 operand o1RegP() %{ | |
3895 constraint(ALLOC_IN_RC(o1_regP)); | |
3896 match(iRegP); | |
3897 | |
3898 format %{ %} | |
3899 interface(REG_INTER); | |
3900 %} | |
3901 | |
3902 operand o2RegP() %{ | |
3903 constraint(ALLOC_IN_RC(o2_regP)); | |
3904 match(iRegP); | |
3905 | |
3906 format %{ %} | |
3907 interface(REG_INTER); | |
3908 %} | |
3909 | |
3910 operand o7RegP() %{ | |
3911 constraint(ALLOC_IN_RC(o7_regP)); | |
3912 match(iRegP); | |
3913 | |
3914 format %{ %} | |
3915 interface(REG_INTER); | |
3916 %} | |
3917 | |
3918 operand l7RegP() %{ | |
3919 constraint(ALLOC_IN_RC(l7_regP)); | |
3920 match(iRegP); | |
3921 | |
3922 format %{ %} | |
3923 interface(REG_INTER); | |
3924 %} | |
3925 | |
3926 operand o7RegI() %{ | |
3927 constraint(ALLOC_IN_RC(o7_regI)); | |
3928 match(iRegI); | |
3929 | |
3930 format %{ %} | |
3931 interface(REG_INTER); | |
3932 %} | |
3933 | |
113
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3934 operand iRegN() %{ |
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3935 constraint(ALLOC_IN_RC(int_reg)); |
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3936 match(RegN); |
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3937 |
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3938 format %{ %} |
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3939 interface(REG_INTER); |
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3940 %} |
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3941 |
0 | 3942 // Long Register |
3943 operand iRegL() %{ | |
3944 constraint(ALLOC_IN_RC(long_reg)); | |
3945 match(RegL); | |
3946 | |
3947 format %{ %} | |
3948 interface(REG_INTER); | |
3949 %} | |
3950 | |
3951 operand o2RegL() %{ | |
3952 constraint(ALLOC_IN_RC(o2_regL)); | |
3953 match(iRegL); | |
3954 | |
3955 format %{ %} | |
3956 interface(REG_INTER); | |
3957 %} | |
3958 | |
3959 operand o7RegL() %{ | |
3960 constraint(ALLOC_IN_RC(o7_regL)); | |
3961 match(iRegL); | |
3962 | |
3963 format %{ %} | |
3964 interface(REG_INTER); | |
3965 %} | |
3966 | |
3967 operand g1RegL() %{ | |
3968 constraint(ALLOC_IN_RC(g1_regL)); | |
3969 match(iRegL); | |
3970 | |
3971 format %{ %} | |
3972 interface(REG_INTER); | |
3973 %} | |
3974 | |
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3975 operand g3RegL() %{ |
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3976 constraint(ALLOC_IN_RC(g3_regL)); |
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3977 match(iRegL); |
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3978 |
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3979 format %{ %} |
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3980 interface(REG_INTER); |
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3981 %} |
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3982 |
0 | 3983 // Int Register safe |
3984 // This is 64bit safe | |
3985 operand iRegIsafe() %{ | |
3986 constraint(ALLOC_IN_RC(long_reg)); | |
3987 | |
3988 match(iRegI); | |
3989 | |
3990 format %{ %} | |
3991 interface(REG_INTER); | |
3992 %} | |
3993 | |
3994 // Condition Code Flag Register | |
3995 operand flagsReg() %{ | |
3996 constraint(ALLOC_IN_RC(int_flags)); | |
3997 match(RegFlags); | |
3998 | |
3999 format %{ "ccr" %} // both ICC and XCC | |
4000 interface(REG_INTER); | |
4001 %} | |
4002 | |
4003 // Condition Code Register, unsigned comparisons. | |
4004 operand flagsRegU() %{ | |
4005 constraint(ALLOC_IN_RC(int_flags)); | |
4006 match(RegFlags); | |
4007 | |
4008 format %{ "icc_U" %} | |
4009 interface(REG_INTER); | |
4010 %} | |
4011 | |
4012 // Condition Code Register, pointer comparisons. | |
4013 operand flagsRegP() %{ | |
4014 constraint(ALLOC_IN_RC(int_flags)); | |
4015 match(RegFlags); | |
4016 | |
4017 #ifdef _LP64 | |
4018 format %{ "xcc_P" %} | |
4019 #else | |
4020 format %{ "icc_P" %} | |
4021 #endif | |
4022 interface(REG_INTER); | |
4023 %} | |
4024 | |
4025 // Condition Code Register, long comparisons. | |
4026 operand flagsRegL() %{ | |
4027 constraint(ALLOC_IN_RC(int_flags)); | |
4028 match(RegFlags); | |
4029 | |
4030 format %{ "xcc_L" %} | |
4031 interface(REG_INTER); | |
4032 %} | |
4033 | |
4034 // Condition Code Register, floating comparisons, unordered same as "less". | |
4035 operand flagsRegF() %{ | |
4036 constraint(ALLOC_IN_RC(float_flags)); | |
4037 match(RegFlags); | |
4038 match(flagsRegF0); | |
4039 | |
4040 format %{ %} | |
4041 interface(REG_INTER); | |
4042 %} | |
4043 | |
4044 operand flagsRegF0() %{ | |
4045 constraint(ALLOC_IN_RC(float_flag0)); | |
4046 match(RegFlags); | |
4047 | |
4048 format %{ %} | |
4049 interface(REG_INTER); | |
4050 %} | |
4051 | |
4052 | |
4053 // Condition Code Flag Register used by long compare | |
4054 operand flagsReg_long_LTGE() %{ | |
4055 constraint(ALLOC_IN_RC(int_flags)); | |
4056 match(RegFlags); | |
4057 format %{ "icc_LTGE" %} | |
4058 interface(REG_INTER); | |
4059 %} | |
4060 operand flagsReg_long_EQNE() %{ | |
4061 constraint(ALLOC_IN_RC(int_flags)); | |
4062 match(RegFlags); | |
4063 format %{ "icc_EQNE" %} | |
4064 interface(REG_INTER); | |
4065 %} | |
4066 operand flagsReg_long_LEGT() %{ | |
4067 constraint(ALLOC_IN_RC(int_flags)); | |
4068 match(RegFlags); | |
4069 format %{ "icc_LEGT" %} | |
4070 interface(REG_INTER); | |
4071 %} | |
4072 | |
4073 | |
4074 operand regD() %{ | |
4075 constraint(ALLOC_IN_RC(dflt_reg)); | |
4076 match(RegD); | |
4077 | |
551 | 4078 match(regD_low); |
4079 | |
0 | 4080 format %{ %} |
4081 interface(REG_INTER); | |
4082 %} | |
4083 | |
4084 operand regF() %{ | |
4085 constraint(ALLOC_IN_RC(sflt_reg)); | |
4086 match(RegF); | |
4087 | |
4088 format %{ %} | |
4089 interface(REG_INTER); | |
4090 %} | |
4091 | |
4092 operand regD_low() %{ | |
4093 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4094 match(regD); |
0 | 4095 |
4096 format %{ %} | |
4097 interface(REG_INTER); | |
4098 %} | |
4099 | |
4100 // Special Registers | |
4101 | |
4102 // Method Register | |
4103 operand inline_cache_regP(iRegP reg) %{ | |
4104 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4105 match(reg); | |
4106 format %{ %} | |
4107 interface(REG_INTER); | |
4108 %} | |
4109 | |
4110 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4111 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4112 match(reg); | |
4113 format %{ %} | |
4114 interface(REG_INTER); | |
4115 %} | |
4116 | |
4117 | |
4118 //----------Complex Operands--------------------------------------------------- | |
4119 // Indirect Memory Reference | |
4120 operand indirect(sp_ptr_RegP reg) %{ | |
4121 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4122 match(reg); | |
4123 | |
4124 op_cost(100); | |
4125 format %{ "[$reg]" %} | |
4126 interface(MEMORY_INTER) %{ | |
4127 base($reg); | |
4128 index(0x0); | |
4129 scale(0x0); | |
4130 disp(0x0); | |
4131 %} | |
4132 %} | |
4133 | |
785 | 4134 // Indirect with simm13 Offset |
0 | 4135 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4136 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4137 match(AddP reg offset); | |
4138 | |
4139 op_cost(100); | |
4140 format %{ "[$reg + $offset]" %} | |
4141 interface(MEMORY_INTER) %{ | |
4142 base($reg); | |
4143 index(0x0); | |
4144 scale(0x0); | |
4145 disp($offset); | |
4146 %} | |
4147 %} | |
4148 | |
785 | 4149 // Indirect with simm13 Offset minus 7 |
4150 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4151 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4152 match(AddP reg offset); | |
4153 | |
4154 op_cost(100); | |
4155 format %{ "[$reg + $offset]" %} | |
4156 interface(MEMORY_INTER) %{ | |
4157 base($reg); | |
4158 index(0x0); | |
4159 scale(0x0); | |
4160 disp($offset); | |
4161 %} | |
4162 %} | |
4163 | |
0 | 4164 // Note: Intel has a swapped version also, like this: |
4165 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4166 // constraint(ALLOC_IN_RC(int_reg)); | |
4167 // match(AddP offset reg); | |
4168 // | |
4169 // op_cost(100); | |
4170 // format %{ "[$reg + $offset]" %} | |
4171 // interface(MEMORY_INTER) %{ | |
4172 // base($reg); | |
4173 // index(0x0); | |
4174 // scale(0x0); | |
4175 // disp($offset); | |
4176 // %} | |
4177 //%} | |
4178 //// However, it doesn't make sense for SPARC, since | |
4179 // we have no particularly good way to embed oops in | |
4180 // single instructions. | |
4181 | |
4182 // Indirect with Register Index | |
4183 operand indIndex(iRegP addr, iRegX index) %{ | |
4184 constraint(ALLOC_IN_RC(ptr_reg)); | |
4185 match(AddP addr index); | |
4186 | |
4187 op_cost(100); | |
4188 format %{ "[$addr + $index]" %} | |
4189 interface(MEMORY_INTER) %{ | |
4190 base($addr); | |
4191 index($index); | |
4192 scale(0x0); | |
4193 disp(0x0); | |
4194 %} | |
4195 %} | |
4196 | |
4197 //----------Special Memory Operands-------------------------------------------- | |
4198 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4199 // values on the stack where a match requires a value to | |
4200 // flow through memory. | |
4201 operand stackSlotI(sRegI reg) %{ | |
4202 constraint(ALLOC_IN_RC(stack_slots)); | |
4203 op_cost(100); | |
4204 //match(RegI); | |
4205 format %{ "[$reg]" %} | |
4206 interface(MEMORY_INTER) %{ | |
4207 base(0xE); // R_SP | |
4208 index(0x0); | |
4209 scale(0x0); | |
4210 disp($reg); // Stack Offset | |
4211 %} | |
4212 %} | |
4213 | |
4214 operand stackSlotP(sRegP reg) %{ | |
4215 constraint(ALLOC_IN_RC(stack_slots)); | |
4216 op_cost(100); | |
4217 //match(RegP); | |
4218 format %{ "[$reg]" %} | |
4219 interface(MEMORY_INTER) %{ | |
4220 base(0xE); // R_SP | |
4221 index(0x0); | |
4222 scale(0x0); | |
4223 disp($reg); // Stack Offset | |
4224 %} | |
4225 %} | |
4226 | |
4227 operand stackSlotF(sRegF reg) %{ | |
4228 constraint(ALLOC_IN_RC(stack_slots)); | |
4229 op_cost(100); | |
4230 //match(RegF); | |
4231 format %{ "[$reg]" %} | |
4232 interface(MEMORY_INTER) %{ | |
4233 base(0xE); // R_SP | |
4234 index(0x0); | |
4235 scale(0x0); | |
4236 disp($reg); // Stack Offset | |
4237 %} | |
4238 %} | |
4239 operand stackSlotD(sRegD reg) %{ | |
4240 constraint(ALLOC_IN_RC(stack_slots)); | |
4241 op_cost(100); | |
4242 //match(RegD); | |
4243 format %{ "[$reg]" %} | |
4244 interface(MEMORY_INTER) %{ | |
4245 base(0xE); // R_SP | |
4246 index(0x0); | |
4247 scale(0x0); | |
4248 disp($reg); // Stack Offset | |
4249 %} | |
4250 %} | |
4251 operand stackSlotL(sRegL reg) %{ | |
4252 constraint(ALLOC_IN_RC(stack_slots)); | |
4253 op_cost(100); | |
4254 //match(RegL); | |
4255 format %{ "[$reg]" %} | |
4256 interface(MEMORY_INTER) %{ | |
4257 base(0xE); // R_SP | |
4258 index(0x0); | |
4259 scale(0x0); | |
4260 disp($reg); // Stack Offset | |
4261 %} | |
4262 %} | |
4263 | |
4264 // Operands for expressing Control Flow | |
4265 // NOTE: Label is a predefined operand which should not be redefined in | |
4266 // the AD file. It is generically handled within the ADLC. | |
4267 | |
4268 //----------Conditional Branch Operands---------------------------------------- | |
4269 // Comparison Op - This is the operation of the comparison, and is limited to | |
4270 // the following set of codes: | |
4271 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4272 // | |
4273 // Other attributes of the comparison, such as unsignedness, are specified | |
4274 // by the comparison instruction that sets a condition code flags register. | |
4275 // That result is represented by a flags operand whose subtype is appropriate | |
4276 // to the unsignedness (etc.) of the comparison. | |
4277 // | |
4278 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4279 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4280 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4281 | |
4282 operand cmpOp() %{ | |
4283 match(Bool); | |
4284 | |
4285 format %{ "" %} | |
4286 interface(COND_INTER) %{ | |
4287 equal(0x1); | |
4288 not_equal(0x9); | |
4289 less(0x3); | |
4290 greater_equal(0xB); | |
4291 less_equal(0x2); | |
4292 greater(0xA); | |
4293 %} | |
4294 %} | |
4295 | |
4296 // Comparison Op, unsigned | |
4297 operand cmpOpU() %{ | |
4298 match(Bool); | |
4299 | |
4300 format %{ "u" %} | |
4301 interface(COND_INTER) %{ | |
4302 equal(0x1); | |
4303 not_equal(0x9); | |
4304 less(0x5); | |
4305 greater_equal(0xD); | |
4306 less_equal(0x4); | |
4307 greater(0xC); | |
4308 %} | |
4309 %} | |
4310 | |
4311 // Comparison Op, pointer (same as unsigned) | |
4312 operand cmpOpP() %{ | |
4313 match(Bool); | |
4314 | |
4315 format %{ "p" %} | |
4316 interface(COND_INTER) %{ | |
4317 equal(0x1); | |
4318 not_equal(0x9); | |
4319 less(0x5); | |
4320 greater_equal(0xD); | |
4321 less_equal(0x4); | |
4322 greater(0xC); | |
4323 %} | |
4324 %} | |
4325 | |
4326 // Comparison Op, branch-register encoding | |
4327 operand cmpOp_reg() %{ | |
4328 match(Bool); | |
4329 | |
4330 format %{ "" %} | |
4331 interface(COND_INTER) %{ | |
4332 equal (0x1); | |
4333 not_equal (0x5); | |
4334 less (0x3); | |
4335 greater_equal(0x7); | |
4336 less_equal (0x2); | |
4337 greater (0x6); | |
4338 %} | |
4339 %} | |
4340 | |
4341 // Comparison Code, floating, unordered same as less | |
4342 operand cmpOpF() %{ | |
4343 match(Bool); | |
4344 | |
4345 format %{ "fl" %} | |
4346 interface(COND_INTER) %{ | |
4347 equal(0x9); | |
4348 not_equal(0x1); | |
4349 less(0x3); | |
4350 greater_equal(0xB); | |
4351 less_equal(0xE); | |
4352 greater(0x6); | |
4353 %} | |
4354 %} | |
4355 | |
4356 // Used by long compare | |
4357 operand cmpOp_commute() %{ | |
4358 match(Bool); | |
4359 | |
4360 format %{ "" %} | |
4361 interface(COND_INTER) %{ | |
4362 equal(0x1); | |
4363 not_equal(0x9); | |
4364 less(0xA); | |
4365 greater_equal(0x2); | |
4366 less_equal(0xB); | |
4367 greater(0x3); | |
4368 %} | |
4369 %} | |
4370 | |
4371 //----------OPERAND CLASSES---------------------------------------------------- | |
4372 // Operand Classes are groups of operands that are used to simplify | |
605 | 4373 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4374 // instructions for every form of operand when the instruction accepts |
4375 // multiple operand types with the same basic encoding and format. The classic | |
4376 // case of this is memory operands. | |
4377 opclass memory( indirect, indOffset13, indIndex ); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
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changeset
|
4378 opclass indIndexMemory( indIndex ); |
0 | 4379 |
4380 //----------PIPELINE----------------------------------------------------------- | |
4381 pipeline %{ | |
4382 | |
4383 //----------ATTRIBUTES--------------------------------------------------------- | |
4384 attributes %{ | |
4385 fixed_size_instructions; // Fixed size instructions | |
4386 branch_has_delay_slot; // Branch has delay slot following | |
4387 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4388 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4389 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4390 instruction_fetch_units = 1; // of 16 bytes | |
4391 | |
4392 // List of nop instructions | |
4393 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4394 %} | |
4395 | |
4396 //----------RESOURCES---------------------------------------------------------- | |
4397 // Resources are the functional units available to the machine | |
4398 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4399 | |
4400 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4401 // Pipeline Description specifies the stages in the machine's pipeline | |
4402 | |
4403 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4404 | |
4405 //----------PIPELINE CLASSES--------------------------------------------------- | |
4406 // Pipeline Classes describe the stages in which input and output are | |
4407 // referenced by the hardware pipeline. | |
4408 | |
4409 // Integer ALU reg-reg operation | |
4410 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4411 single_instruction; | |
4412 dst : E(write); | |
4413 src1 : R(read); | |
4414 src2 : R(read); | |
4415 IALU : R; | |
4416 %} | |
4417 | |
4418 // Integer ALU reg-reg long operation | |
4419 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4420 instruction_count(2); | |
4421 dst : E(write); | |
4422 src1 : R(read); | |
4423 src2 : R(read); | |
4424 IALU : R; | |
4425 IALU : R; | |
4426 %} | |
4427 | |
4428 // Integer ALU reg-reg long dependent operation | |
4429 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4430 instruction_count(1); multiple_bundles; | |
4431 dst : E(write); | |
4432 src1 : R(read); | |
4433 src2 : R(read); | |
4434 cr : E(write); | |
4435 IALU : R(2); | |
4436 %} | |
4437 | |
4438 // Integer ALU reg-imm operaion | |
4439 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4440 single_instruction; | |
4441 dst : E(write); | |
4442 src1 : R(read); | |
4443 IALU : R; | |
4444 %} | |
4445 | |
4446 // Integer ALU reg-reg operation with condition code | |
4447 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4448 single_instruction; | |
4449 dst : E(write); | |
4450 cr : E(write); | |
4451 src1 : R(read); | |
4452 src2 : R(read); | |
4453 IALU : R; | |
4454 %} | |
4455 | |
4456 // Integer ALU reg-imm operation with condition code | |
4457 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4458 single_instruction; | |
4459 dst : E(write); | |
4460 cr : E(write); | |
4461 src1 : R(read); | |
4462 IALU : R; | |
4463 %} | |
4464 | |
4465 // Integer ALU zero-reg operation | |
4466 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4467 single_instruction; | |
4468 dst : E(write); | |
4469 src2 : R(read); | |
4470 IALU : R; | |
4471 %} | |
4472 | |
4473 // Integer ALU zero-reg operation with condition code only | |
4474 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4475 single_instruction; | |
4476 cr : E(write); | |
4477 src : R(read); | |
4478 IALU : R; | |
4479 %} | |
4480 | |
4481 // Integer ALU reg-reg operation with condition code only | |
4482 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4483 single_instruction; | |
4484 cr : E(write); | |
4485 src1 : R(read); | |
4486 src2 : R(read); | |
4487 IALU : R; | |
4488 %} | |
4489 | |
4490 // Integer ALU reg-imm operation with condition code only | |
4491 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4492 single_instruction; | |
4493 cr : E(write); | |
4494 src1 : R(read); | |
4495 IALU : R; | |
4496 %} | |
4497 | |
4498 // Integer ALU reg-reg-zero operation with condition code only | |
4499 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4500 single_instruction; | |
4501 cr : E(write); | |
4502 src1 : R(read); | |
4503 src2 : R(read); | |
4504 IALU : R; | |
4505 %} | |
4506 | |
4507 // Integer ALU reg-imm-zero operation with condition code only | |
4508 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4509 single_instruction; | |
4510 cr : E(write); | |
4511 src1 : R(read); | |
4512 IALU : R; | |
4513 %} | |
4514 | |
4515 // Integer ALU reg-reg operation with condition code, src1 modified | |
4516 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4517 single_instruction; | |
4518 cr : E(write); | |
4519 src1 : E(write); | |
4520 src1 : R(read); | |
4521 src2 : R(read); | |
4522 IALU : R; | |
4523 %} | |
4524 | |
4525 // Integer ALU reg-imm operation with condition code, src1 modified | |
4526 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4527 single_instruction; | |
4528 cr : E(write); | |
4529 src1 : E(write); | |
4530 src1 : R(read); | |
4531 IALU : R; | |
4532 %} | |
4533 | |
4534 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4535 multiple_bundles; | |
4536 dst : E(write)+4; | |
4537 cr : E(write); | |
4538 src1 : R(read); | |
4539 src2 : R(read); | |
4540 IALU : R(3); | |
4541 BR : R(2); | |
4542 %} | |
4543 | |
4544 // Integer ALU operation | |
4545 pipe_class ialu_none(iRegI dst) %{ | |
4546 single_instruction; | |
4547 dst : E(write); | |
4548 IALU : R; | |
4549 %} | |
4550 | |
4551 // Integer ALU reg operation | |
4552 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4553 single_instruction; may_have_no_code; | |
4554 dst : E(write); | |
4555 src : R(read); | |
4556 IALU : R; | |
4557 %} | |
4558 | |
4559 // Integer ALU reg conditional operation | |
4560 // This instruction has a 1 cycle stall, and cannot execute | |
4561 // in the same cycle as the instruction setting the condition | |
4562 // code. We kludge this by pretending to read the condition code | |
4563 // 1 cycle earlier, and by marking the functional units as busy | |
4564 // for 2 cycles with the result available 1 cycle later than | |
4565 // is really the case. | |
4566 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4567 single_instruction; | |
4568 op2_out : C(write); | |
4569 op1 : R(read); | |
4570 cr : R(read); // This is really E, with a 1 cycle stall | |
4571 BR : R(2); | |
4572 MS : R(2); | |
4573 %} | |
4574 | |
4575 #ifdef _LP64 | |
4576 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4577 instruction_count(1); multiple_bundles; | |
4578 dst : C(write)+1; | |
4579 src : R(read)+1; | |
4580 IALU : R(1); | |
4581 BR : E(2); | |
4582 MS : E(2); | |
4583 %} | |
4584 #endif | |
4585 | |
4586 // Integer ALU reg operation | |
4587 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4588 single_instruction; may_have_no_code; | |
4589 dst : E(write); | |
4590 src : R(read); | |
4591 IALU : R; | |
4592 %} | |
4593 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4594 single_instruction; may_have_no_code; | |
4595 dst : E(write); | |
4596 src : R(read); | |
4597 IALU : R; | |
4598 %} | |
4599 | |
4600 // Two integer ALU reg operations | |
4601 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4602 instruction_count(2); | |
4603 dst : E(write); | |
4604 src : R(read); | |
4605 A0 : R; | |
4606 A1 : R; | |
4607 %} | |
4608 | |
4609 // Two integer ALU reg operations | |
4610 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4611 instruction_count(2); may_have_no_code; | |
4612 dst : E(write); | |
4613 src : R(read); | |
4614 A0 : R; | |
4615 A1 : R; | |
4616 %} | |
4617 | |
4618 // Integer ALU imm operation | |
4619 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4620 single_instruction; | |
4621 dst : E(write); | |
4622 IALU : R; | |
4623 %} | |
4624 | |
4625 // Integer ALU reg-reg with carry operation | |
4626 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4627 single_instruction; | |
4628 dst : E(write); | |
4629 src1 : R(read); | |
4630 src2 : R(read); | |
4631 IALU : R; | |
4632 %} | |
4633 | |
4634 // Integer ALU cc operation | |
4635 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4636 single_instruction; | |
4637 dst : E(write); | |
4638 cc : R(read); | |
4639 IALU : R; | |
4640 %} | |
4641 | |
4642 // Integer ALU cc / second IALU operation | |
4643 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4644 instruction_count(1); multiple_bundles; | |
4645 dst : E(write)+1; | |
4646 src : R(read); | |
4647 IALU : R; | |
4648 %} | |
4649 | |
4650 // Integer ALU cc / second IALU operation | |
4651 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4652 instruction_count(1); multiple_bundles; | |
4653 dst : E(write)+1; | |
4654 p : R(read); | |
4655 q : R(read); | |
4656 IALU : R; | |
4657 %} | |
4658 | |
4659 // Integer ALU hi-lo-reg operation | |
4660 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4661 instruction_count(1); multiple_bundles; | |
4662 dst : E(write)+1; | |
4663 IALU : R(2); | |
4664 %} | |
4665 | |
4666 // Float ALU hi-lo-reg operation (with temp) | |
4667 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4668 instruction_count(1); multiple_bundles; | |
4669 dst : E(write)+1; | |
4670 IALU : R(2); | |
4671 %} | |
4672 | |
4673 // Long Constant | |
4674 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4675 instruction_count(2); multiple_bundles; | |
4676 dst : E(write)+1; | |
4677 IALU : R(2); | |
4678 IALU : R(2); | |
4679 %} | |
4680 | |
4681 // Pointer Constant | |
4682 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4683 instruction_count(0); multiple_bundles; | |
4684 fixed_latency(6); | |
4685 %} | |
4686 | |
4687 // Polling Address | |
4688 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4689 #ifdef _LP64 | |
4690 instruction_count(0); multiple_bundles; | |
4691 fixed_latency(6); | |
4692 #else | |
4693 dst : E(write); | |
4694 IALU : R; | |
4695 #endif | |
4696 %} | |
4697 | |
4698 // Long Constant small | |
4699 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4700 instruction_count(2); | |
4701 dst : E(write); | |
4702 IALU : R; | |
4703 IALU : R; | |
4704 %} | |
4705 | |
4706 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4707 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4708 instruction_count(1); multiple_bundles; | |
4709 src : R(read); | |
4710 dst : M(write)+1; | |
4711 IALU : R; | |
4712 MS : E; | |
4713 %} | |
4714 | |
4715 // Integer ALU nop operation | |
4716 pipe_class ialu_nop() %{ | |
4717 single_instruction; | |
4718 IALU : R; | |
4719 %} | |
4720 | |
4721 // Integer ALU nop operation | |
4722 pipe_class ialu_nop_A0() %{ | |
4723 single_instruction; | |
4724 A0 : R; | |
4725 %} | |
4726 | |
4727 // Integer ALU nop operation | |
4728 pipe_class ialu_nop_A1() %{ | |
4729 single_instruction; | |
4730 A1 : R; | |
4731 %} | |
4732 | |
4733 // Integer Multiply reg-reg operation | |
4734 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4735 single_instruction; | |
4736 dst : E(write); | |
4737 src1 : R(read); | |
4738 src2 : R(read); | |
4739 MS : R(5); | |
4740 %} | |
4741 | |
4742 // Integer Multiply reg-imm operation | |
4743 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4744 single_instruction; | |
4745 dst : E(write); | |
4746 src1 : R(read); | |
4747 MS : R(5); | |
4748 %} | |
4749 | |
4750 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4751 single_instruction; | |
4752 dst : E(write)+4; | |
4753 src1 : R(read); | |
4754 src2 : R(read); | |
4755 MS : R(6); | |
4756 %} | |
4757 | |
4758 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4759 single_instruction; | |
4760 dst : E(write)+4; | |
4761 src1 : R(read); | |
4762 MS : R(6); | |
4763 %} | |
4764 | |
4765 // Integer Divide reg-reg | |
4766 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4767 instruction_count(1); multiple_bundles; | |
4768 dst : E(write); | |
4769 temp : E(write); | |
4770 src1 : R(read); | |
4771 src2 : R(read); | |
4772 temp : R(read); | |
4773 MS : R(38); | |
4774 %} | |
4775 | |
4776 // Integer Divide reg-imm | |
4777 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4778 instruction_count(1); multiple_bundles; | |
4779 dst : E(write); | |
4780 temp : E(write); | |
4781 src1 : R(read); | |
4782 temp : R(read); | |
4783 MS : R(38); | |
4784 %} | |
4785 | |
4786 // Long Divide | |
4787 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4788 dst : E(write)+71; | |
4789 src1 : R(read); | |
4790 src2 : R(read)+1; | |
4791 MS : R(70); | |
4792 %} | |
4793 | |
4794 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4795 dst : E(write)+71; | |
4796 src1 : R(read); | |
4797 MS : R(70); | |
4798 %} | |
4799 | |
4800 // Floating Point Add Float | |
4801 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4802 single_instruction; | |
4803 dst : X(write); | |
4804 src1 : E(read); | |
4805 src2 : E(read); | |
4806 FA : R; | |
4807 %} | |
4808 | |
4809 // Floating Point Add Double | |
4810 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4811 single_instruction; | |
4812 dst : X(write); | |
4813 src1 : E(read); | |
4814 src2 : E(read); | |
4815 FA : R; | |
4816 %} | |
4817 | |
4818 // Floating Point Conditional Move based on integer flags | |
4819 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4820 single_instruction; | |
4821 dst : X(write); | |
4822 src : E(read); | |
4823 cr : R(read); | |
4824 FA : R(2); | |
4825 BR : R(2); | |
4826 %} | |
4827 | |
4828 // Floating Point Conditional Move based on integer flags | |
4829 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4830 single_instruction; | |
4831 dst : X(write); | |
4832 src : E(read); | |
4833 cr : R(read); | |
4834 FA : R(2); | |
4835 BR : R(2); | |
4836 %} | |
4837 | |
4838 // Floating Point Multiply Float | |
4839 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4840 single_instruction; | |
4841 dst : X(write); | |
4842 src1 : E(read); | |
4843 src2 : E(read); | |
4844 FM : R; | |
4845 %} | |
4846 | |
4847 // Floating Point Multiply Double | |
4848 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4849 single_instruction; | |
4850 dst : X(write); | |
4851 src1 : E(read); | |
4852 src2 : E(read); | |
4853 FM : R; | |
4854 %} | |
4855 | |
4856 // Floating Point Divide Float | |
4857 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4858 single_instruction; | |
4859 dst : X(write); | |
4860 src1 : E(read); | |
4861 src2 : E(read); | |
4862 FM : R; | |
4863 FDIV : C(14); | |
4864 %} | |
4865 | |
4866 // Floating Point Divide Double | |
4867 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4868 single_instruction; | |
4869 dst : X(write); | |
4870 src1 : E(read); | |
4871 src2 : E(read); | |
4872 FM : R; | |
4873 FDIV : C(17); | |
4874 %} | |
4875 | |
4876 // Floating Point Move/Negate/Abs Float | |
4877 pipe_class faddF_reg(regF dst, regF src) %{ | |
4878 single_instruction; | |
4879 dst : W(write); | |
4880 src : E(read); | |
4881 FA : R(1); | |
4882 %} | |
4883 | |
4884 // Floating Point Move/Negate/Abs Double | |
4885 pipe_class faddD_reg(regD dst, regD src) %{ | |
4886 single_instruction; | |
4887 dst : W(write); | |
4888 src : E(read); | |
4889 FA : R; | |
4890 %} | |
4891 | |
4892 // Floating Point Convert F->D | |
4893 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4894 single_instruction; | |
4895 dst : X(write); | |
4896 src : E(read); | |
4897 FA : R; | |
4898 %} | |
4899 | |
4900 // Floating Point Convert I->D | |
4901 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4902 single_instruction; | |
4903 dst : X(write); | |
4904 src : E(read); | |
4905 FA : R; | |
4906 %} | |
4907 | |
4908 // Floating Point Convert LHi->D | |
4909 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4910 single_instruction; | |
4911 dst : X(write); | |
4912 src : E(read); | |
4913 FA : R; | |
4914 %} | |
4915 | |
4916 // Floating Point Convert L->D | |
4917 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4918 single_instruction; | |
4919 dst : X(write); | |
4920 src : E(read); | |
4921 FA : R; | |
4922 %} | |
4923 | |
4924 // Floating Point Convert L->F | |
4925 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4926 single_instruction; | |
4927 dst : X(write); | |
4928 src : E(read); | |
4929 FA : R; | |
4930 %} | |
4931 | |
4932 // Floating Point Convert D->F | |
4933 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4934 single_instruction; | |
4935 dst : X(write); | |
4936 src : E(read); | |
4937 FA : R; | |
4938 %} | |
4939 | |
4940 // Floating Point Convert I->L | |
4941 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4942 single_instruction; | |
4943 dst : X(write); | |
4944 src : E(read); | |
4945 FA : R; | |
4946 %} | |
4947 | |
4948 // Floating Point Convert D->F | |
4949 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4950 instruction_count(1); multiple_bundles; | |
4951 dst : X(write)+6; | |
4952 src : E(read); | |
4953 FA : R; | |
4954 %} | |
4955 | |
4956 // Floating Point Convert D->L | |
4957 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4958 instruction_count(1); multiple_bundles; | |
4959 dst : X(write)+6; | |
4960 src : E(read); | |
4961 FA : R; | |
4962 %} | |
4963 | |
4964 // Floating Point Convert F->I | |
4965 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4966 instruction_count(1); multiple_bundles; | |
4967 dst : X(write)+6; | |
4968 src : E(read); | |
4969 FA : R; | |
4970 %} | |
4971 | |
4972 // Floating Point Convert F->L | |
4973 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4974 instruction_count(1); multiple_bundles; | |
4975 dst : X(write)+6; | |
4976 src : E(read); | |
4977 FA : R; | |
4978 %} | |
4979 | |
4980 // Floating Point Convert I->F | |
4981 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4982 single_instruction; | |
4983 dst : X(write); | |
4984 src : E(read); | |
4985 FA : R; | |
4986 %} | |
4987 | |
4988 // Floating Point Compare | |
4989 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4990 single_instruction; | |
4991 cr : X(write); | |
4992 src1 : E(read); | |
4993 src2 : E(read); | |
4994 FA : R; | |
4995 %} | |
4996 | |
4997 // Floating Point Compare | |
4998 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4999 single_instruction; | |
5000 cr : X(write); | |
5001 src1 : E(read); | |
5002 src2 : E(read); | |
5003 FA : R; | |
5004 %} | |
5005 | |
5006 // Floating Add Nop | |
5007 pipe_class fadd_nop() %{ | |
5008 single_instruction; | |
5009 FA : R; | |
5010 %} | |
5011 | |
5012 // Integer Store to Memory | |
5013 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
5014 single_instruction; | |
5015 mem : R(read); | |
5016 src : C(read); | |
5017 MS : R; | |
5018 %} | |
5019 | |
5020 // Integer Store to Memory | |
5021 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
5022 single_instruction; | |
5023 mem : R(read); | |
5024 src : C(read); | |
5025 MS : R; | |
5026 %} | |
5027 | |
5028 // Integer Store Zero to Memory | |
5029 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
5030 single_instruction; | |
5031 mem : R(read); | |
5032 MS : R; | |
5033 %} | |
5034 | |
5035 // Special Stack Slot Store | |
5036 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
5037 single_instruction; | |
5038 stkSlot : R(read); | |
5039 src : C(read); | |
5040 MS : R; | |
5041 %} | |
5042 | |
5043 // Special Stack Slot Store | |
5044 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
5045 instruction_count(2); multiple_bundles; | |
5046 stkSlot : R(read); | |
5047 src : C(read); | |
5048 MS : R(2); | |
5049 %} | |
5050 | |
5051 // Float Store | |
5052 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
5053 single_instruction; | |
5054 mem : R(read); | |
5055 src : C(read); | |
5056 MS : R; | |
5057 %} | |
5058 | |
5059 // Float Store | |
5060 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
5061 single_instruction; | |
5062 mem : R(read); | |
5063 MS : R; | |
5064 %} | |
5065 | |
5066 // Double Store | |
5067 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5068 instruction_count(1); | |
5069 mem : R(read); | |
5070 src : C(read); | |
5071 MS : R; | |
5072 %} | |
5073 | |
5074 // Double Store | |
5075 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5076 single_instruction; | |
5077 mem : R(read); | |
5078 MS : R; | |
5079 %} | |
5080 | |
5081 // Special Stack Slot Float Store | |
5082 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5083 single_instruction; | |
5084 stkSlot : R(read); | |
5085 src : C(read); | |
5086 MS : R; | |
5087 %} | |
5088 | |
5089 // Special Stack Slot Double Store | |
5090 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5091 single_instruction; | |
5092 stkSlot : R(read); | |
5093 src : C(read); | |
5094 MS : R; | |
5095 %} | |
5096 | |
5097 // Integer Load (when sign bit propagation not needed) | |
5098 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5099 single_instruction; | |
5100 mem : R(read); | |
5101 dst : C(write); | |
5102 MS : R; | |
5103 %} | |
5104 | |
5105 // Integer Load from stack operand | |
5106 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5107 single_instruction; | |
5108 mem : R(read); | |
5109 dst : C(write); | |
5110 MS : R; | |
5111 %} | |
5112 | |
5113 // Integer Load (when sign bit propagation or masking is needed) | |
5114 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5115 single_instruction; | |
5116 mem : R(read); | |
5117 dst : M(write); | |
5118 MS : R; | |
5119 %} | |
5120 | |
5121 // Float Load | |
5122 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5123 single_instruction; | |
5124 mem : R(read); | |
5125 dst : M(write); | |
5126 MS : R; | |
5127 %} | |
5128 | |
5129 // Float Load | |
5130 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5131 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5132 mem : R(read); | |
5133 dst : M(write); | |
5134 MS : R; | |
5135 %} | |
5136 | |
5137 // Float Load | |
5138 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5139 single_instruction; | |
5140 stkSlot : R(read); | |
5141 dst : M(write); | |
5142 MS : R; | |
5143 %} | |
5144 | |
5145 // Float Load | |
5146 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5147 single_instruction; | |
5148 stkSlot : R(read); | |
5149 dst : M(write); | |
5150 MS : R; | |
5151 %} | |
5152 | |
5153 // Memory Nop | |
5154 pipe_class mem_nop() %{ | |
5155 single_instruction; | |
5156 MS : R; | |
5157 %} | |
5158 | |
5159 pipe_class sethi(iRegP dst, immI src) %{ | |
5160 single_instruction; | |
5161 dst : E(write); | |
5162 IALU : R; | |
5163 %} | |
5164 | |
5165 pipe_class loadPollP(iRegP poll) %{ | |
5166 single_instruction; | |
5167 poll : R(read); | |
5168 MS : R; | |
5169 %} | |
5170 | |
5171 pipe_class br(Universe br, label labl) %{ | |
5172 single_instruction_with_delay_slot; | |
5173 BR : R; | |
5174 %} | |
5175 | |
5176 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5177 single_instruction_with_delay_slot; | |
5178 cr : E(read); | |
5179 BR : R; | |
5180 %} | |
5181 | |
5182 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5183 single_instruction_with_delay_slot; | |
5184 op1 : E(read); | |
5185 BR : R; | |
5186 MS : R; | |
5187 %} | |
5188 | |
5189 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
5190 single_instruction_with_delay_slot; | |
5191 cr : E(read); | |
5192 BR : R; | |
5193 %} | |
5194 | |
5195 pipe_class br_nop() %{ | |
5196 single_instruction; | |
5197 BR : R; | |
5198 %} | |
5199 | |
5200 pipe_class simple_call(method meth) %{ | |
5201 instruction_count(2); multiple_bundles; force_serialization; | |
5202 fixed_latency(100); | |
5203 BR : R(1); | |
5204 MS : R(1); | |
5205 A0 : R(1); | |
5206 %} | |
5207 | |
5208 pipe_class compiled_call(method meth) %{ | |
5209 instruction_count(1); multiple_bundles; force_serialization; | |
5210 fixed_latency(100); | |
5211 MS : R(1); | |
5212 %} | |
5213 | |
5214 pipe_class call(method meth) %{ | |
5215 instruction_count(0); multiple_bundles; force_serialization; | |
5216 fixed_latency(100); | |
5217 %} | |
5218 | |
5219 pipe_class tail_call(Universe ignore, label labl) %{ | |
5220 single_instruction; has_delay_slot; | |
5221 fixed_latency(100); | |
5222 BR : R(1); | |
5223 MS : R(1); | |
5224 %} | |
5225 | |
5226 pipe_class ret(Universe ignore) %{ | |
5227 single_instruction; has_delay_slot; | |
5228 BR : R(1); | |
5229 MS : R(1); | |
5230 %} | |
5231 | |
5232 pipe_class ret_poll(g3RegP poll) %{ | |
5233 instruction_count(3); has_delay_slot; | |
5234 poll : E(read); | |
5235 MS : R; | |
5236 %} | |
5237 | |
5238 // The real do-nothing guy | |
5239 pipe_class empty( ) %{ | |
5240 instruction_count(0); | |
5241 %} | |
5242 | |
5243 pipe_class long_memory_op() %{ | |
5244 instruction_count(0); multiple_bundles; force_serialization; | |
5245 fixed_latency(25); | |
5246 MS : R(1); | |
5247 %} | |
5248 | |
5249 // Check-cast | |
5250 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5251 array : R(read); | |
5252 match : R(read); | |
5253 IALU : R(2); | |
5254 BR : R(2); | |
5255 MS : R; | |
5256 %} | |
5257 | |
5258 // Convert FPU flags into +1,0,-1 | |
5259 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5260 src1 : E(read); | |
5261 src2 : E(read); | |
5262 dst : E(write); | |
5263 FA : R; | |
5264 MS : R(2); | |
5265 BR : R(2); | |
5266 %} | |
5267 | |
5268 // Compare for p < q, and conditionally add y | |
5269 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5270 p : E(read); | |
5271 q : E(read); | |
5272 y : E(read); | |
5273 IALU : R(3) | |
5274 %} | |
5275 | |
5276 // Perform a compare, then move conditionally in a branch delay slot. | |
5277 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5278 src2 : E(read); | |
5279 srcdst : E(read); | |
5280 IALU : R; | |
5281 BR : R; | |
5282 %} | |
5283 | |
5284 // Define the class for the Nop node | |
5285 define %{ | |
5286 MachNop = ialu_nop; | |
5287 %} | |
5288 | |
5289 %} | |
5290 | |
5291 //----------INSTRUCTIONS------------------------------------------------------- | |
5292 | |
5293 //------------Special Stack Slot instructions - no match rules----------------- | |
5294 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5295 // No match rule to avoid chain rule match. | |
5296 effect(DEF dst, USE src); | |
5297 ins_cost(MEMORY_REF_COST); | |
5298 size(4); | |
5299 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5300 opcode(Assembler::ldf_op3); | |
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5301 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5302 ins_pipe(floadF_stk); |
5303 %} | |
5304 | |
5305 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5306 // No match rule to avoid chain rule match. | |
5307 effect(DEF dst, USE src); | |
5308 ins_cost(MEMORY_REF_COST); | |
5309 size(4); | |
5310 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5311 opcode(Assembler::lddf_op3); | |
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5312 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5313 ins_pipe(floadD_stk); |
5314 %} | |
5315 | |
5316 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5317 // No match rule to avoid chain rule match. | |
5318 effect(DEF dst, USE src); | |
5319 ins_cost(MEMORY_REF_COST); | |
5320 size(4); | |
5321 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5322 opcode(Assembler::stf_op3); | |
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5323 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5324 ins_pipe(fstoreF_stk_reg); |
5325 %} | |
5326 | |
5327 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5328 // No match rule to avoid chain rule match. | |
5329 effect(DEF dst, USE src); | |
5330 ins_cost(MEMORY_REF_COST); | |
5331 size(4); | |
5332 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5333 opcode(Assembler::stdf_op3); | |
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5334 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5335 ins_pipe(fstoreD_stk_reg); |
5336 %} | |
5337 | |
5338 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5339 effect(DEF dst, USE src); | |
5340 ins_cost(MEMORY_REF_COST*2); | |
5341 size(8); | |
5342 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5343 "STW R_G0,$dst.lo" %} | |
5344 opcode(Assembler::stw_op3); | |
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5345 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5346 ins_pipe(lstoreI_stk_reg); |
5347 %} | |
5348 | |
5349 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5350 // No match rule to avoid chain rule match. | |
5351 effect(DEF dst, USE src); | |
5352 ins_cost(MEMORY_REF_COST); | |
5353 size(4); | |
5354 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5355 opcode(Assembler::stx_op3); | |
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5356 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5357 ins_pipe(istore_stk_reg); |
5358 %} | |
5359 | |
5360 //---------- Chain stack slots between similar types -------- | |
5361 | |
5362 // Load integer from stack slot | |
5363 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5364 match(Set dst src); | |
5365 ins_cost(MEMORY_REF_COST); | |
5366 | |
5367 size(4); | |
5368 format %{ "LDUW $src,$dst\t!stk" %} | |
5369 opcode(Assembler::lduw_op3); | |
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5370 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5371 ins_pipe(iload_mem); |
5372 %} | |
5373 | |
5374 // Store integer to stack slot | |
5375 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5376 match(Set dst src); | |
5377 ins_cost(MEMORY_REF_COST); | |
5378 | |
5379 size(4); | |
5380 format %{ "STW $src,$dst\t!stk" %} | |
5381 opcode(Assembler::stw_op3); | |
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5382 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5383 ins_pipe(istore_mem_reg); |
5384 %} | |
5385 | |
5386 // Load long from stack slot | |
5387 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5388 match(Set dst src); | |
5389 | |
5390 ins_cost(MEMORY_REF_COST); | |
5391 size(4); | |
5392 format %{ "LDX $src,$dst\t! long" %} | |
5393 opcode(Assembler::ldx_op3); | |
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5394 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5395 ins_pipe(iload_mem); |
5396 %} | |
5397 | |
5398 // Store long to stack slot | |
5399 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5400 match(Set dst src); | |
5401 | |
5402 ins_cost(MEMORY_REF_COST); | |
5403 size(4); | |
5404 format %{ "STX $src,$dst\t! long" %} | |
5405 opcode(Assembler::stx_op3); | |
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|
5406 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5407 ins_pipe(istore_mem_reg); |
5408 %} | |
5409 | |
5410 #ifdef _LP64 | |
5411 // Load pointer from stack slot, 64-bit encoding | |
5412 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5413 match(Set dst src); | |
5414 ins_cost(MEMORY_REF_COST); | |
5415 size(4); | |
5416 format %{ "LDX $src,$dst\t!ptr" %} | |
5417 opcode(Assembler::ldx_op3); | |
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5418 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5419 ins_pipe(iload_mem); |
5420 %} | |
5421 | |
5422 // Store pointer to stack slot | |
5423 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5424 match(Set dst src); | |
5425 ins_cost(MEMORY_REF_COST); | |
5426 size(4); | |
5427 format %{ "STX $src,$dst\t!ptr" %} | |
5428 opcode(Assembler::stx_op3); | |
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|
5429 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5430 ins_pipe(istore_mem_reg); |
5431 %} | |
5432 #else // _LP64 | |
5433 // Load pointer from stack slot, 32-bit encoding | |
5434 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5435 match(Set dst src); | |
5436 ins_cost(MEMORY_REF_COST); | |
5437 format %{ "LDUW $src,$dst\t!ptr" %} | |
5438 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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|
5439 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5440 ins_pipe(iload_mem); |
5441 %} | |
5442 | |
5443 // Store pointer to stack slot | |
5444 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5445 match(Set dst src); | |
5446 ins_cost(MEMORY_REF_COST); | |
5447 format %{ "STW $src,$dst\t!ptr" %} | |
5448 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5449 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5450 ins_pipe(istore_mem_reg); |
5451 %} | |
5452 #endif // _LP64 | |
5453 | |
5454 //------------Special Nop instructions for bundling - no match rules----------- | |
5455 // Nop using the A0 functional unit | |
5456 instruct Nop_A0() %{ | |
5457 ins_cost(0); | |
5458 | |
5459 format %{ "NOP ! Alu Pipeline" %} | |
5460 opcode(Assembler::or_op3, Assembler::arith_op); | |
5461 ins_encode( form2_nop() ); | |
5462 ins_pipe(ialu_nop_A0); | |
5463 %} | |
5464 | |
5465 // Nop using the A1 functional unit | |
5466 instruct Nop_A1( ) %{ | |
5467 ins_cost(0); | |
5468 | |
5469 format %{ "NOP ! Alu Pipeline" %} | |
5470 opcode(Assembler::or_op3, Assembler::arith_op); | |
5471 ins_encode( form2_nop() ); | |
5472 ins_pipe(ialu_nop_A1); | |
5473 %} | |
5474 | |
5475 // Nop using the memory functional unit | |
5476 instruct Nop_MS( ) %{ | |
5477 ins_cost(0); | |
5478 | |
5479 format %{ "NOP ! Memory Pipeline" %} | |
5480 ins_encode( emit_mem_nop ); | |
5481 ins_pipe(mem_nop); | |
5482 %} | |
5483 | |
5484 // Nop using the floating add functional unit | |
5485 instruct Nop_FA( ) %{ | |
5486 ins_cost(0); | |
5487 | |
5488 format %{ "NOP ! Floating Add Pipeline" %} | |
5489 ins_encode( emit_fadd_nop ); | |
5490 ins_pipe(fadd_nop); | |
5491 %} | |
5492 | |
5493 // Nop using the branch functional unit | |
5494 instruct Nop_BR( ) %{ | |
5495 ins_cost(0); | |
5496 | |
5497 format %{ "NOP ! Branch Pipeline" %} | |
5498 ins_encode( emit_br_nop ); | |
5499 ins_pipe(br_nop); | |
5500 %} | |
5501 | |
5502 //----------Load/Store/Move Instructions--------------------------------------- | |
5503 //----------Load Instructions-------------------------------------------------- | |
5504 // Load Byte (8bit signed) | |
5505 instruct loadB(iRegI dst, memory mem) %{ | |
5506 match(Set dst (LoadB mem)); | |
5507 ins_cost(MEMORY_REF_COST); | |
5508 | |
5509 size(4); | |
624 | 5510 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5511 ins_encode %{ |
5512 __ ldsb($mem$$Address, $dst$$Register); | |
5513 %} | |
624 | 5514 ins_pipe(iload_mask_mem); |
5515 %} | |
5516 | |
5517 // Load Byte (8bit signed) into a Long Register | |
5518 instruct loadB2L(iRegL dst, memory mem) %{ | |
5519 match(Set dst (ConvI2L (LoadB mem))); | |
5520 ins_cost(MEMORY_REF_COST); | |
5521 | |
5522 size(4); | |
5523 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5524 ins_encode %{ |
5525 __ ldsb($mem$$Address, $dst$$Register); | |
5526 %} | |
0 | 5527 ins_pipe(iload_mask_mem); |
5528 %} | |
5529 | |
624 | 5530 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5531 instruct loadUB(iRegI dst, memory mem) %{ | |
5532 match(Set dst (LoadUB mem)); | |
0 | 5533 ins_cost(MEMORY_REF_COST); |
5534 | |
5535 size(4); | |
624 | 5536 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5537 ins_encode %{ |
5538 __ ldub($mem$$Address, $dst$$Register); | |
5539 %} | |
824 | 5540 ins_pipe(iload_mem); |
624 | 5541 %} |
5542 | |
5543 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5544 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5545 match(Set dst (ConvI2L (LoadUB mem))); | |
5546 ins_cost(MEMORY_REF_COST); | |
5547 | |
5548 size(4); | |
5549 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5550 ins_encode %{ |
5551 __ ldub($mem$$Address, $dst$$Register); | |
5552 %} | |
824 | 5553 ins_pipe(iload_mem); |
5554 %} | |
5555 | |
5556 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5557 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5558 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5559 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5560 | |
5561 size(2*4); | |
5562 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5563 "AND $dst,$mask,$dst" %} | |
5564 ins_encode %{ | |
5565 __ ldub($mem$$Address, $dst$$Register); | |
5566 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5567 %} | |
5568 ins_pipe(iload_mem); | |
0 | 5569 %} |
5570 | |
624 | 5571 // Load Short (16bit signed) |
5572 instruct loadS(iRegI dst, memory mem) %{ | |
5573 match(Set dst (LoadS mem)); | |
5574 ins_cost(MEMORY_REF_COST); | |
5575 | |
5576 size(4); | |
5577 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5578 ins_encode %{ |
5579 __ ldsh($mem$$Address, $dst$$Register); | |
5580 %} | |
624 | 5581 ins_pipe(iload_mask_mem); |
5582 %} | |
5583 | |
785 | 5584 // Load Short (16 bit signed) to Byte (8 bit signed) |
5585 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5586 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5587 ins_cost(MEMORY_REF_COST); | |
5588 | |
5589 size(4); | |
5590 | |
5591 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5592 ins_encode %{ | |
5593 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5594 %} | |
5595 ins_pipe(iload_mask_mem); | |
5596 %} | |
5597 | |
624 | 5598 // Load Short (16bit signed) into a Long Register |
5599 instruct loadS2L(iRegL dst, memory mem) %{ | |
5600 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5601 ins_cost(MEMORY_REF_COST); |
5602 | |
5603 size(4); | |
624 | 5604 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5605 ins_encode %{ |
5606 __ ldsh($mem$$Address, $dst$$Register); | |
5607 %} | |
624 | 5608 ins_pipe(iload_mask_mem); |
5609 %} | |
5610 | |
5611 // Load Unsigned Short/Char (16bit UNsigned) | |
5612 instruct loadUS(iRegI dst, memory mem) %{ | |
5613 match(Set dst (LoadUS mem)); | |
5614 ins_cost(MEMORY_REF_COST); | |
5615 | |
5616 size(4); | |
5617 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5618 ins_encode %{ |
5619 __ lduh($mem$$Address, $dst$$Register); | |
5620 %} | |
824 | 5621 ins_pipe(iload_mem); |
0 | 5622 %} |
5623 | |
785 | 5624 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5625 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5626 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5627 ins_cost(MEMORY_REF_COST); | |
5628 | |
5629 size(4); | |
5630 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5631 ins_encode %{ | |
5632 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5633 %} | |
5634 ins_pipe(iload_mask_mem); | |
5635 %} | |
5636 | |
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diff
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5637 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5638 instruct loadUS2L(iRegL dst, memory mem) %{ |
5639 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5640 ins_cost(MEMORY_REF_COST); |
5641 | |
5642 size(4); | |
624 | 5643 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5644 ins_encode %{ |
5645 __ lduh($mem$$Address, $dst$$Register); | |
5646 %} | |
824 | 5647 ins_pipe(iload_mem); |
5648 %} | |
5649 | |
5650 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5651 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5652 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5653 ins_cost(MEMORY_REF_COST); | |
5654 | |
5655 size(4); | |
5656 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5657 ins_encode %{ | |
5658 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5659 %} | |
5660 ins_pipe(iload_mem); | |
5661 %} | |
5662 | |
5663 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5664 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5665 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5666 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5667 | |
5668 size(2*4); | |
5669 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5670 "AND $dst,$mask,$dst" %} | |
5671 ins_encode %{ | |
5672 Register Rdst = $dst$$Register; | |
5673 __ lduh($mem$$Address, Rdst); | |
5674 __ and3(Rdst, $mask$$constant, Rdst); | |
5675 %} | |
5676 ins_pipe(iload_mem); | |
5677 %} | |
5678 | |
5679 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5680 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5681 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5682 effect(TEMP dst, TEMP tmp); | |
5683 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5684 | |
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1fbd5d696bf4
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twisti
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824
diff
changeset
|
5685 size((3+1)*4); // set may use two instructions. |
824 | 5686 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5687 "SET $mask,$tmp\n\t" | |
5688 "AND $dst,$tmp,$dst" %} | |
5689 ins_encode %{ | |
5690 Register Rdst = $dst$$Register; | |
5691 Register Rtmp = $tmp$$Register; | |
5692 __ lduh($mem$$Address, Rdst); | |
5693 __ set($mask$$constant, Rtmp); | |
5694 __ and3(Rdst, Rtmp, Rdst); | |
5695 %} | |
5696 ins_pipe(iload_mem); | |
0 | 5697 %} |
5698 | |
5699 // Load Integer | |
5700 instruct loadI(iRegI dst, memory mem) %{ | |
5701 match(Set dst (LoadI mem)); | |
5702 ins_cost(MEMORY_REF_COST); | |
624 | 5703 |
5704 size(4); | |
5705 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5706 ins_encode %{ |
5707 __ lduw($mem$$Address, $dst$$Register); | |
5708 %} | |
624 | 5709 ins_pipe(iload_mem); |
5710 %} | |
5711 | |
785 | 5712 // Load Integer to Byte (8 bit signed) |
5713 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5714 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5715 ins_cost(MEMORY_REF_COST); | |
5716 | |
5717 size(4); | |
5718 | |
5719 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5720 ins_encode %{ | |
5721 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5722 %} | |
5723 ins_pipe(iload_mask_mem); | |
5724 %} | |
5725 | |
5726 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5727 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5728 match(Set dst (AndI (LoadI mem) mask)); | |
5729 ins_cost(MEMORY_REF_COST); | |
5730 | |
5731 size(4); | |
5732 | |
5733 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5734 ins_encode %{ | |
5735 __ ldub($mem$$Address, $dst$$Register, 3); | |
5736 %} | |
5737 ins_pipe(iload_mask_mem); | |
5738 %} | |
5739 | |
5740 // Load Integer to Short (16 bit signed) | |
5741 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5742 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5743 ins_cost(MEMORY_REF_COST); | |
5744 | |
5745 size(4); | |
5746 | |
5747 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5748 ins_encode %{ | |
5749 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5750 %} | |
5751 ins_pipe(iload_mask_mem); | |
5752 %} | |
5753 | |
5754 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5755 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5756 match(Set dst (AndI (LoadI mem) mask)); | |
5757 ins_cost(MEMORY_REF_COST); | |
5758 | |
5759 size(4); | |
5760 | |
5761 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5762 ins_encode %{ | |
5763 __ lduh($mem$$Address, $dst$$Register, 2); | |
5764 %} | |
5765 ins_pipe(iload_mask_mem); | |
5766 %} | |
5767 | |
624 | 5768 // Load Integer into a Long Register |
5769 instruct loadI2L(iRegL dst, memory mem) %{ | |
5770 match(Set dst (ConvI2L (LoadI mem))); | |
5771 ins_cost(MEMORY_REF_COST); | |
5772 | |
5773 size(4); | |
5774 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5775 ins_encode %{ |
5776 __ ldsw($mem$$Address, $dst$$Register); | |
5777 %} | |
824 | 5778 ins_pipe(iload_mask_mem); |
5779 %} | |
5780 | |
5781 // Load Integer with mask 0xFF into a Long Register | |
5782 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5783 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5784 ins_cost(MEMORY_REF_COST); | |
5785 | |
5786 size(4); | |
5787 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5788 ins_encode %{ | |
5789 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5790 %} | |
5791 ins_pipe(iload_mem); | |
5792 %} | |
5793 | |
5794 // Load Integer with mask 0xFFFF into a Long Register | |
5795 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5796 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5797 ins_cost(MEMORY_REF_COST); | |
5798 | |
5799 size(4); | |
5800 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5801 ins_encode %{ | |
5802 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5803 %} | |
5804 ins_pipe(iload_mem); | |
5805 %} | |
5806 | |
5807 // Load Integer with a 13-bit mask into a Long Register | |
5808 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5809 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5810 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5811 | |
5812 size(2*4); | |
5813 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
5814 "AND $dst,$mask,$dst" %} | |
5815 ins_encode %{ | |
5816 Register Rdst = $dst$$Register; | |
5817 __ lduw($mem$$Address, Rdst); | |
5818 __ and3(Rdst, $mask$$constant, Rdst); | |
5819 %} | |
5820 ins_pipe(iload_mem); | |
5821 %} | |
5822 | |
5823 // Load Integer with a 32-bit mask into a Long Register | |
5824 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
5825 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5826 effect(TEMP dst, TEMP tmp); | |
5827 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5828 | |
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
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824
diff
changeset
|
5829 size((3+1)*4); // set may use two instructions. |
824 | 5830 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
5831 "SET $mask,$tmp\n\t" | |
5832 "AND $dst,$tmp,$dst" %} | |
5833 ins_encode %{ | |
5834 Register Rdst = $dst$$Register; | |
5835 Register Rtmp = $tmp$$Register; | |
5836 __ lduw($mem$$Address, Rdst); | |
5837 __ set($mask$$constant, Rtmp); | |
5838 __ and3(Rdst, Rtmp, Rdst); | |
5839 %} | |
624 | 5840 ins_pipe(iload_mem); |
5841 %} | |
5842 | |
5843 // Load Unsigned Integer into a Long Register | |
5844 instruct loadUI2L(iRegL dst, memory mem) %{ | |
5845 match(Set dst (LoadUI2L mem)); | |
5846 ins_cost(MEMORY_REF_COST); | |
5847 | |
5848 size(4); | |
5849 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5850 ins_encode %{ |
5851 __ lduw($mem$$Address, $dst$$Register); | |
5852 %} | |
0 | 5853 ins_pipe(iload_mem); |
5854 %} | |
5855 | |
5856 // Load Long - aligned | |
5857 instruct loadL(iRegL dst, memory mem ) %{ | |
5858 match(Set dst (LoadL mem)); | |
5859 ins_cost(MEMORY_REF_COST); | |
624 | 5860 |
0 | 5861 size(4); |
5862 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5863 ins_encode %{ |
5864 __ ldx($mem$$Address, $dst$$Register); | |
5865 %} | |
0 | 5866 ins_pipe(iload_mem); |
5867 %} | |
5868 | |
5869 // Load Long - UNaligned | |
5870 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5871 match(Set dst (LoadL_unaligned mem)); | |
5872 effect(KILL tmp); | |
5873 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5874 size(16); | |
5875 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5876 "\tLDUW $mem ,$dst\n" | |
5877 "\tSLLX #32, $dst, $dst\n" | |
5878 "\tOR $dst, R_O7, $dst" %} | |
5879 opcode(Assembler::lduw_op3); | |
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parents:
235
diff
changeset
|
5880 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5881 ins_pipe(iload_mem); |
5882 %} | |
5883 | |
5884 // Load Aligned Packed Byte into a Double Register | |
5885 instruct loadA8B(regD dst, memory mem) %{ | |
5886 match(Set dst (Load8B mem)); | |
5887 ins_cost(MEMORY_REF_COST); | |
5888 size(4); | |
5889 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
5890 opcode(Assembler::lddf_op3); | |
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5891 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5892 ins_pipe(floadD_mem); |
5893 %} | |
5894 | |
5895 // Load Aligned Packed Char into a Double Register | |
5896 instruct loadA4C(regD dst, memory mem) %{ | |
5897 match(Set dst (Load4C mem)); | |
5898 ins_cost(MEMORY_REF_COST); | |
5899 size(4); | |
5900 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
5901 opcode(Assembler::lddf_op3); | |
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5902 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5903 ins_pipe(floadD_mem); |
5904 %} | |
5905 | |
5906 // Load Aligned Packed Short into a Double Register | |
5907 instruct loadA4S(regD dst, memory mem) %{ | |
5908 match(Set dst (Load4S mem)); | |
5909 ins_cost(MEMORY_REF_COST); | |
5910 size(4); | |
5911 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
5912 opcode(Assembler::lddf_op3); | |
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5913 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5914 ins_pipe(floadD_mem); |
5915 %} | |
5916 | |
5917 // Load Aligned Packed Int into a Double Register | |
5918 instruct loadA2I(regD dst, memory mem) %{ | |
5919 match(Set dst (Load2I mem)); | |
5920 ins_cost(MEMORY_REF_COST); | |
5921 size(4); | |
5922 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
5923 opcode(Assembler::lddf_op3); | |
415
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5924 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5925 ins_pipe(floadD_mem); |
5926 %} | |
5927 | |
5928 // Load Range | |
5929 instruct loadRange(iRegI dst, memory mem) %{ | |
5930 match(Set dst (LoadRange mem)); | |
5931 ins_cost(MEMORY_REF_COST); | |
5932 | |
5933 size(4); | |
5934 format %{ "LDUW $mem,$dst\t! range" %} | |
5935 opcode(Assembler::lduw_op3); | |
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5936 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5937 ins_pipe(iload_mem); |
5938 %} | |
5939 | |
5940 // Load Integer into %f register (for fitos/fitod) | |
5941 instruct loadI_freg(regF dst, memory mem) %{ | |
5942 match(Set dst (LoadI mem)); | |
5943 ins_cost(MEMORY_REF_COST); | |
5944 size(4); | |
5945 | |
5946 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5947 opcode(Assembler::ldf_op3); | |
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5948 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5949 ins_pipe(floadF_mem); |
5950 %} | |
5951 | |
5952 // Load Pointer | |
5953 instruct loadP(iRegP dst, memory mem) %{ | |
5954 match(Set dst (LoadP mem)); | |
5955 ins_cost(MEMORY_REF_COST); | |
5956 size(4); | |
5957 | |
5958 #ifndef _LP64 | |
5959 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5960 ins_encode %{ |
5961 __ lduw($mem$$Address, $dst$$Register); | |
5962 %} | |
0 | 5963 #else |
5964 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5965 ins_encode %{ |
5966 __ ldx($mem$$Address, $dst$$Register); | |
5967 %} | |
0 | 5968 #endif |
5969 ins_pipe(iload_mem); | |
5970 %} | |
5971 | |
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5972 // Load Compressed Pointer |
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5973 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5974 match(Set dst (LoadN mem)); |
5975 ins_cost(MEMORY_REF_COST); | |
5976 size(4); | |
5977 | |
5978 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5979 ins_encode %{ | |
5980 __ lduw($mem$$Address, $dst$$Register); | |
5981 %} | |
5982 ins_pipe(iload_mem); | |
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5983 %} |
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5984 |
0 | 5985 // Load Klass Pointer |
5986 instruct loadKlass(iRegP dst, memory mem) %{ | |
5987 match(Set dst (LoadKlass mem)); | |
5988 ins_cost(MEMORY_REF_COST); | |
5989 size(4); | |
5990 | |
5991 #ifndef _LP64 | |
5992 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5993 ins_encode %{ |
5994 __ lduw($mem$$Address, $dst$$Register); | |
5995 %} | |
0 | 5996 #else |
5997 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5998 ins_encode %{ |
5999 __ ldx($mem$$Address, $dst$$Register); | |
6000 %} | |
0 | 6001 #endif |
6002 ins_pipe(iload_mem); | |
6003 %} | |
6004 | |
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6005 // Load narrow Klass Pointer |
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6006 instruct loadNKlass(iRegN dst, memory mem) %{ |
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6007 match(Set dst (LoadNKlass mem)); |
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6008 ins_cost(MEMORY_REF_COST); |
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6009 size(4); |
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6010 |
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6011 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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6012 ins_encode %{ |
727 | 6013 __ lduw($mem$$Address, $dst$$Register); |
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6014 %} |
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6015 ins_pipe(iload_mem); |
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6016 %} |
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6017 |
0 | 6018 // Load Double |
6019 instruct loadD(regD dst, memory mem) %{ | |
6020 match(Set dst (LoadD mem)); | |
6021 ins_cost(MEMORY_REF_COST); | |
6022 | |
6023 size(4); | |
6024 format %{ "LDDF $mem,$dst" %} | |
6025 opcode(Assembler::lddf_op3); | |
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6026 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6027 ins_pipe(floadD_mem); |
6028 %} | |
6029 | |
6030 // Load Double - UNaligned | |
6031 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
6032 match(Set dst (LoadD_unaligned mem)); | |
6033 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
6034 size(8); | |
6035 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
6036 "\tLDF $mem+4,$dst.lo\t!" %} | |
6037 opcode(Assembler::ldf_op3); | |
6038 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
6039 ins_pipe(iload_mem); | |
6040 %} | |
6041 | |
6042 // Load Float | |
6043 instruct loadF(regF dst, memory mem) %{ | |
6044 match(Set dst (LoadF mem)); | |
6045 ins_cost(MEMORY_REF_COST); | |
6046 | |
6047 size(4); | |
6048 format %{ "LDF $mem,$dst" %} | |
6049 opcode(Assembler::ldf_op3); | |
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6050 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6051 ins_pipe(floadF_mem); |
6052 %} | |
6053 | |
6054 // Load Constant | |
6055 instruct loadConI( iRegI dst, immI src ) %{ | |
6056 match(Set dst src); | |
6057 ins_cost(DEFAULT_COST * 3/2); | |
6058 format %{ "SET $src,$dst" %} | |
6059 ins_encode( Set32(src, dst) ); | |
6060 ins_pipe(ialu_hi_lo_reg); | |
6061 %} | |
6062 | |
6063 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
6064 match(Set dst src); | |
6065 | |
6066 size(4); | |
6067 format %{ "MOV $src,$dst" %} | |
6068 ins_encode( Set13( src, dst ) ); | |
6069 ins_pipe(ialu_imm); | |
6070 %} | |
6071 | |
2008 | 6072 #ifndef _LP64 |
6073 instruct loadConP(iRegP dst, immP con) %{ | |
6074 match(Set dst con); | |
6075 ins_cost(DEFAULT_COST * 3/2); | |
6076 format %{ "SET $con,$dst\t!ptr" %} | |
6077 ins_encode %{ | |
6078 // [RGV] This next line should be generated from ADLC | |
6079 if (_opnds[1]->constant_is_oop()) { | |
6080 intptr_t val = $con$$constant; | |
6081 __ set_oop_constant((jobject) val, $dst$$Register); | |
6082 } else { // non-oop pointers, e.g. card mark base, heap top | |
6083 __ set($con$$constant, $dst$$Register); | |
6084 } | |
6085 %} | |
6086 ins_pipe(loadConP); | |
6087 %} | |
6088 #else | |
6089 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
6090 match(Set dst con); | |
0 | 6091 ins_cost(DEFAULT_COST * 3/2); |
2008 | 6092 format %{ "SET $con,$dst\t! ptr" %} |
6093 ins_encode %{ | |
6094 // [RGV] This next line should be generated from ADLC | |
6095 if (_opnds[1]->constant_is_oop()) { | |
6096 intptr_t val = $con$$constant; | |
6097 __ set_oop_constant((jobject) val, $dst$$Register); | |
6098 } else { // non-oop pointers, e.g. card mark base, heap top | |
6099 __ set($con$$constant, $dst$$Register); | |
6100 } | |
6101 %} | |
0 | 6102 ins_pipe(loadConP); |
2008 | 6103 %} |
6104 | |
6105 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
6106 match(Set dst con); | |
6107 ins_cost(MEMORY_REF_COST); | |
6108 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
6109 ins_encode %{ | |
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6110 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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6111 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
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6112 %} |
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6113 ins_pipe(loadConP); |
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6114 %} |
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6115 |
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6116 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
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6117 match(Set dst con); |
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6118 ins_cost(DEFAULT_COST * 3/2); |
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6119 format %{ "SET $con,$dst\t! non-oop ptr" %} |
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6120 ins_encode %{ |
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6121 __ set($con$$constant, $dst$$Register); |
2008 | 6122 %} |
6123 ins_pipe(loadConP); | |
6124 %} | |
6125 #endif // _LP64 | |
0 | 6126 |
6127 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6128 match(Set dst src); | |
6129 | |
6130 size(4); | |
6131 format %{ "CLR $dst\t!ptr" %} | |
2008 | 6132 ins_encode %{ |
6133 __ clr($dst$$Register); | |
6134 %} | |
0 | 6135 ins_pipe(ialu_imm); |
6136 %} | |
6137 | |
6138 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6139 match(Set dst src); | |
6140 ins_cost(DEFAULT_COST); | |
6141 format %{ "SET $src,$dst\t!ptr" %} | |
6142 ins_encode %{ | |
727 | 6143 AddressLiteral polling_page(os::get_polling_page()); |
6144 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6145 %} |
6146 ins_pipe(loadConP_poll); | |
6147 %} | |
6148 | |
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6149 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6150 match(Set dst src); |
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6151 |
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6152 size(4); |
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6153 format %{ "CLR $dst\t! compressed NULL ptr" %} |
2008 | 6154 ins_encode %{ |
6155 __ clr($dst$$Register); | |
6156 %} | |
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6157 ins_pipe(ialu_imm); |
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6158 %} |
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6159 |
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6160 instruct loadConN(iRegN dst, immN src) %{ |
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6161 match(Set dst src); |
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6162 ins_cost(DEFAULT_COST * 3/2); |
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6163 format %{ "SET $src,$dst\t! compressed ptr" %} |
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6164 ins_encode %{ |
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6165 Register dst = $dst$$Register; |
164
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6166 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6167 %} |
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6168 ins_pipe(ialu_hi_lo_reg); |
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6169 %} |
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6170 |
2008 | 6171 // Materialize long value (predicated by immL_cheap). |
6172 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
6173 match(Set dst con); | |
0 | 6174 effect(KILL tmp); |
2008 | 6175 ins_cost(DEFAULT_COST * 3); |
6176 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
6177 ins_encode %{ | |
6178 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
6179 %} | |
6180 ins_pipe(loadConL); | |
6181 %} | |
6182 | |
6183 // Load long value from constant table (predicated by immL_expensive). | |
6184 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
6185 match(Set dst con); | |
6186 ins_cost(MEMORY_REF_COST); | |
6187 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
6188 ins_encode %{ | |
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6189 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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6190 __ ldx($constanttablebase, con_offset, $dst$$Register); |
2008 | 6191 %} |
0 | 6192 ins_pipe(loadConL); |
6193 %} | |
6194 | |
6195 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6196 match(Set dst src); | |
6197 ins_cost(DEFAULT_COST); | |
6198 size(4); | |
6199 format %{ "CLR $dst\t! long" %} | |
6200 ins_encode( Set13( src, dst ) ); | |
6201 ins_pipe(ialu_imm); | |
6202 %} | |
6203 | |
6204 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6205 match(Set dst src); | |
6206 ins_cost(DEFAULT_COST * 2); | |
6207 | |
6208 size(4); | |
6209 format %{ "MOV $src,$dst\t! long" %} | |
6210 ins_encode( Set13( src, dst ) ); | |
6211 ins_pipe(ialu_imm); | |
6212 %} | |
6213 | |
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6214 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
2008 | 6215 match(Set dst con); |
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6216 effect(KILL tmp); |
2008 | 6217 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
727 | 6218 ins_encode %{ |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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diff
changeset
|
6219 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
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kvn
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diff
changeset
|
6220 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
727 | 6221 %} |
0 | 6222 ins_pipe(loadConFD); |
6223 %} | |
6224 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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diff
changeset
|
6225 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
2008 | 6226 match(Set dst con); |
2012
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kvn
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2008
diff
changeset
|
6227 effect(KILL tmp); |
2008 | 6228 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
727 | 6229 ins_encode %{ |
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6230 // XXX This is a quick fix for 6833573. |
2008 | 6231 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
2012
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diff
changeset
|
6232 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
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kvn
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2008
diff
changeset
|
6233 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
727 | 6234 %} |
0 | 6235 ins_pipe(loadConFD); |
6236 %} | |
6237 | |
6238 // Prefetch instructions. | |
6239 // Must be safe to execute with invalid address (cannot fault). | |
6240 | |
6241 instruct prefetchr( memory mem ) %{ | |
6242 match( PrefetchRead mem ); | |
6243 ins_cost(MEMORY_REF_COST); | |
6244 | |
6245 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6246 opcode(Assembler::prefetch_op3); | |
6247 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6248 ins_pipe(iload_mem); | |
6249 %} | |
6250 | |
6251 instruct prefetchw( memory mem ) %{ | |
1367
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6940726: Use BIS instruction for allocation prefetch on Sparc
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1274
diff
changeset
|
6252 predicate(AllocatePrefetchStyle != 3 ); |
0 | 6253 match( PrefetchWrite mem ); |
6254 ins_cost(MEMORY_REF_COST); | |
6255 | |
6256 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6257 opcode(Assembler::prefetch_op3); | |
6258 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6259 ins_pipe(iload_mem); | |
6260 %} | |
6261 | |
1367
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6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
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diff
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|
6262 // Use BIS instruction to prefetch. |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6263 instruct prefetchw_bis( memory mem ) %{ |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6264 predicate(AllocatePrefetchStyle == 3); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6265 match( PrefetchWrite mem ); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
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parents:
1274
diff
changeset
|
6266 ins_cost(MEMORY_REF_COST); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
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diff
changeset
|
6267 |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
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1274
diff
changeset
|
6268 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6269 ins_encode %{ |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6270 Register base = as_Register($mem$$base); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6271 int disp = $mem$$disp; |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6272 if (disp != 0) { |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6273 __ add(base, AllocatePrefetchStepSize, base); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6274 } |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6275 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
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diff
changeset
|
6276 %} |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
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1274
diff
changeset
|
6277 ins_pipe(istore_mem_reg); |
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diff
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|
6278 %} |
0 | 6279 |
6280 //----------Store Instructions------------------------------------------------- | |
6281 // Store Byte | |
6282 instruct storeB(memory mem, iRegI src) %{ | |
6283 match(Set mem (StoreB mem src)); | |
6284 ins_cost(MEMORY_REF_COST); | |
6285 | |
6286 size(4); | |
6287 format %{ "STB $src,$mem\t! byte" %} | |
6288 opcode(Assembler::stb_op3); | |
415
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|
6289 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6290 ins_pipe(istore_mem_reg); |
6291 %} | |
6292 | |
6293 instruct storeB0(memory mem, immI0 src) %{ | |
6294 match(Set mem (StoreB mem src)); | |
6295 ins_cost(MEMORY_REF_COST); | |
6296 | |
6297 size(4); | |
6298 format %{ "STB $src,$mem\t! byte" %} | |
6299 opcode(Assembler::stb_op3); | |
415
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|
6300 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6301 ins_pipe(istore_mem_zero); |
6302 %} | |
6303 | |
6304 instruct storeCM0(memory mem, immI0 src) %{ | |
6305 match(Set mem (StoreCM mem src)); | |
6306 ins_cost(MEMORY_REF_COST); | |
6307 | |
6308 size(4); | |
6309 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6310 opcode(Assembler::stb_op3); | |
415
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|
6311 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6312 ins_pipe(istore_mem_zero); |
6313 %} | |
6314 | |
6315 // Store Char/Short | |
6316 instruct storeC(memory mem, iRegI src) %{ | |
6317 match(Set mem (StoreC mem src)); | |
6318 ins_cost(MEMORY_REF_COST); | |
6319 | |
6320 size(4); | |
6321 format %{ "STH $src,$mem\t! short" %} | |
6322 opcode(Assembler::sth_op3); | |
415
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|
6323 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6324 ins_pipe(istore_mem_reg); |
6325 %} | |
6326 | |
6327 instruct storeC0(memory mem, immI0 src) %{ | |
6328 match(Set mem (StoreC mem src)); | |
6329 ins_cost(MEMORY_REF_COST); | |
6330 | |
6331 size(4); | |
6332 format %{ "STH $src,$mem\t! short" %} | |
6333 opcode(Assembler::sth_op3); | |
415
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|
6334 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6335 ins_pipe(istore_mem_zero); |
6336 %} | |
6337 | |
6338 // Store Integer | |
6339 instruct storeI(memory mem, iRegI src) %{ | |
6340 match(Set mem (StoreI mem src)); | |
6341 ins_cost(MEMORY_REF_COST); | |
6342 | |
6343 size(4); | |
6344 format %{ "STW $src,$mem" %} | |
6345 opcode(Assembler::stw_op3); | |
415
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|
6346 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6347 ins_pipe(istore_mem_reg); |
6348 %} | |
6349 | |
6350 // Store Long | |
6351 instruct storeL(memory mem, iRegL src) %{ | |
6352 match(Set mem (StoreL mem src)); | |
6353 ins_cost(MEMORY_REF_COST); | |
6354 size(4); | |
6355 format %{ "STX $src,$mem\t! long" %} | |
6356 opcode(Assembler::stx_op3); | |
415
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|
6357 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6358 ins_pipe(istore_mem_reg); |
6359 %} | |
6360 | |
6361 instruct storeI0(memory mem, immI0 src) %{ | |
6362 match(Set mem (StoreI mem src)); | |
6363 ins_cost(MEMORY_REF_COST); | |
6364 | |
6365 size(4); | |
6366 format %{ "STW $src,$mem" %} | |
6367 opcode(Assembler::stw_op3); | |
415
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|
6368 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6369 ins_pipe(istore_mem_zero); |
6370 %} | |
6371 | |
6372 instruct storeL0(memory mem, immL0 src) %{ | |
6373 match(Set mem (StoreL mem src)); | |
6374 ins_cost(MEMORY_REF_COST); | |
6375 | |
6376 size(4); | |
6377 format %{ "STX $src,$mem" %} | |
6378 opcode(Assembler::stx_op3); | |
415
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|
6379 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6380 ins_pipe(istore_mem_zero); |
6381 %} | |
6382 | |
6383 // Store Integer from float register (used after fstoi) | |
6384 instruct storeI_Freg(memory mem, regF src) %{ | |
6385 match(Set mem (StoreI mem src)); | |
6386 ins_cost(MEMORY_REF_COST); | |
6387 | |
6388 size(4); | |
6389 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6390 opcode(Assembler::stf_op3); | |
415
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|
6391 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6392 ins_pipe(fstoreF_mem_reg); |
6393 %} | |
6394 | |
6395 // Store Pointer | |
6396 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6397 match(Set dst (StoreP dst src)); | |
6398 ins_cost(MEMORY_REF_COST); | |
6399 size(4); | |
6400 | |
6401 #ifndef _LP64 | |
6402 format %{ "STW $src,$dst\t! ptr" %} | |
6403 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6404 #else | |
6405 format %{ "STX $src,$dst\t! ptr" %} | |
6406 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6407 #endif | |
6408 ins_encode( form3_mem_reg( dst, src ) ); | |
6409 ins_pipe(istore_mem_spORreg); | |
6410 %} | |
6411 | |
6412 instruct storeP0(memory dst, immP0 src) %{ | |
6413 match(Set dst (StoreP dst src)); | |
6414 ins_cost(MEMORY_REF_COST); | |
6415 size(4); | |
6416 | |
6417 #ifndef _LP64 | |
6418 format %{ "STW $src,$dst\t! ptr" %} | |
6419 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6420 #else | |
6421 format %{ "STX $src,$dst\t! ptr" %} | |
6422 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6423 #endif | |
6424 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6425 ins_pipe(istore_mem_zero); | |
6426 %} | |
6427 | |
113
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|
6428 // Store Compressed Pointer |
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|
6429 instruct storeN(memory dst, iRegN src) %{ |
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|
6430 match(Set dst (StoreN dst src)); |
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|
6431 ins_cost(MEMORY_REF_COST); |
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|
6432 size(4); |
ba764ed4b6f2
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|
6433 |
ba764ed4b6f2
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|
6434 format %{ "STW $src,$dst\t! compressed ptr" %} |
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|
6435 ins_encode %{ |
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|
6436 Register base = as_Register($dst$$base); |
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|
6437 Register index = as_Register($dst$$index); |
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6438 Register src = $src$$Register; |
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|
6439 if (index != G0) { |
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|
6440 __ stw(src, base, index); |
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6441 } else { |
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|
6442 __ stw(src, base, $dst$$disp); |
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|
6443 } |
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|
6444 %} |
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|
6445 ins_pipe(istore_mem_spORreg); |
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|
6446 %} |
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|
6447 |
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|
6448 instruct storeN0(memory dst, immN0 src) %{ |
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6449 match(Set dst (StoreN dst src)); |
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6450 ins_cost(MEMORY_REF_COST); |
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6451 size(4); |
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|
6452 |
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|
6453 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6454 ins_encode %{ |
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6455 Register base = as_Register($dst$$base); |
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6456 Register index = as_Register($dst$$index); |
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6457 if (index != G0) { |
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6458 __ stw(0, base, index); |
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6459 } else { |
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6460 __ stw(0, base, $dst$$disp); |
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6461 } |
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|
6462 %} |
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6463 ins_pipe(istore_mem_zero); |
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6464 %} |
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6465 |
0 | 6466 // Store Double |
6467 instruct storeD( memory mem, regD src) %{ | |
6468 match(Set mem (StoreD mem src)); | |
6469 ins_cost(MEMORY_REF_COST); | |
6470 | |
6471 size(4); | |
6472 format %{ "STDF $src,$mem" %} | |
6473 opcode(Assembler::stdf_op3); | |
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6474 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6475 ins_pipe(fstoreD_mem_reg); |
6476 %} | |
6477 | |
6478 instruct storeD0( memory mem, immD0 src) %{ | |
6479 match(Set mem (StoreD mem src)); | |
6480 ins_cost(MEMORY_REF_COST); | |
6481 | |
6482 size(4); | |
6483 format %{ "STX $src,$mem" %} | |
6484 opcode(Assembler::stx_op3); | |
415
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|
6485 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6486 ins_pipe(fstoreD_mem_zero); |
6487 %} | |
6488 | |
6489 // Store Float | |
6490 instruct storeF( memory mem, regF src) %{ | |
6491 match(Set mem (StoreF mem src)); | |
6492 ins_cost(MEMORY_REF_COST); | |
6493 | |
6494 size(4); | |
6495 format %{ "STF $src,$mem" %} | |
6496 opcode(Assembler::stf_op3); | |
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6497 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6498 ins_pipe(fstoreF_mem_reg); |
6499 %} | |
6500 | |
6501 instruct storeF0( memory mem, immF0 src) %{ | |
6502 match(Set mem (StoreF mem src)); | |
6503 ins_cost(MEMORY_REF_COST); | |
6504 | |
6505 size(4); | |
6506 format %{ "STW $src,$mem\t! storeF0" %} | |
6507 opcode(Assembler::stw_op3); | |
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6508 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6509 ins_pipe(fstoreF_mem_zero); |
6510 %} | |
6511 | |
6512 // Store Aligned Packed Bytes in Double register to memory | |
6513 instruct storeA8B(memory mem, regD src) %{ | |
6514 match(Set mem (Store8B mem src)); | |
6515 ins_cost(MEMORY_REF_COST); | |
6516 size(4); | |
6517 format %{ "STDF $src,$mem\t! packed8B" %} | |
6518 opcode(Assembler::stdf_op3); | |
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6519 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6520 ins_pipe(fstoreD_mem_reg); |
6521 %} | |
6522 | |
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6523 // Convert oop pointer into compressed form |
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6524 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
221
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6525 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
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6526 match(Set dst (EncodeP src)); |
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|
6527 format %{ "encode_heap_oop $src, $dst" %} |
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6528 ins_encode %{ |
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6529 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6530 %} |
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|
6531 ins_pipe(ialu_reg); |
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6532 %} |
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|
6533 |
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6534 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
221
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6535 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
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6536 match(Set dst (EncodeP src)); |
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6537 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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|
6538 ins_encode %{ |
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6539 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6540 %} |
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|
6541 ins_pipe(ialu_reg); |
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|
6542 %} |
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|
6543 |
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6544 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
182
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6545 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6546 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
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6547 match(Set dst (DecodeN src)); |
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6548 format %{ "decode_heap_oop $src, $dst" %} |
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6549 ins_encode %{ |
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6550 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6551 %} |
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6552 ins_pipe(ialu_reg); |
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6553 %} |
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|
6554 |
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|
6555 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
182
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6556 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
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|
6557 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
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|
6558 match(Set dst (DecodeN src)); |
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6559 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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|
6560 ins_encode %{ |
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|
6561 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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|
6562 %} |
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|
6563 ins_pipe(ialu_reg); |
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|
6564 %} |
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|
6565 |
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6566 |
0 | 6567 // Store Zero into Aligned Packed Bytes |
6568 instruct storeA8B0(memory mem, immI0 zero) %{ | |
6569 match(Set mem (Store8B mem zero)); | |
6570 ins_cost(MEMORY_REF_COST); | |
6571 size(4); | |
6572 format %{ "STX $zero,$mem\t! packed8B" %} | |
6573 opcode(Assembler::stx_op3); | |
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|
6574 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6575 ins_pipe(fstoreD_mem_zero); |
6576 %} | |
6577 | |
6578 // Store Aligned Packed Chars/Shorts in Double register to memory | |
6579 instruct storeA4C(memory mem, regD src) %{ | |
6580 match(Set mem (Store4C mem src)); | |
6581 ins_cost(MEMORY_REF_COST); | |
6582 size(4); | |
6583 format %{ "STDF $src,$mem\t! packed4C" %} | |
6584 opcode(Assembler::stdf_op3); | |
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6585 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6586 ins_pipe(fstoreD_mem_reg); |
6587 %} | |
6588 | |
6589 // Store Zero into Aligned Packed Chars/Shorts | |
6590 instruct storeA4C0(memory mem, immI0 zero) %{ | |
6591 match(Set mem (Store4C mem (Replicate4C zero))); | |
6592 ins_cost(MEMORY_REF_COST); | |
6593 size(4); | |
6594 format %{ "STX $zero,$mem\t! packed4C" %} | |
6595 opcode(Assembler::stx_op3); | |
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|
6596 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6597 ins_pipe(fstoreD_mem_zero); |
6598 %} | |
6599 | |
6600 // Store Aligned Packed Ints in Double register to memory | |
6601 instruct storeA2I(memory mem, regD src) %{ | |
6602 match(Set mem (Store2I mem src)); | |
6603 ins_cost(MEMORY_REF_COST); | |
6604 size(4); | |
6605 format %{ "STDF $src,$mem\t! packed2I" %} | |
6606 opcode(Assembler::stdf_op3); | |
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6607 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6608 ins_pipe(fstoreD_mem_reg); |
6609 %} | |
6610 | |
6611 // Store Zero into Aligned Packed Ints | |
6612 instruct storeA2I0(memory mem, immI0 zero) %{ | |
6613 match(Set mem (Store2I mem zero)); | |
6614 ins_cost(MEMORY_REF_COST); | |
6615 size(4); | |
6616 format %{ "STX $zero,$mem\t! packed2I" %} | |
6617 opcode(Assembler::stx_op3); | |
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6618 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6619 ins_pipe(fstoreD_mem_zero); |
6620 %} | |
6621 | |
6622 | |
6623 //----------MemBar Instructions----------------------------------------------- | |
6624 // Memory barrier flavors | |
6625 | |
6626 instruct membar_acquire() %{ | |
6627 match(MemBarAcquire); | |
6628 ins_cost(4*MEMORY_REF_COST); | |
6629 | |
6630 size(0); | |
6631 format %{ "MEMBAR-acquire" %} | |
6632 ins_encode( enc_membar_acquire ); | |
6633 ins_pipe(long_memory_op); | |
6634 %} | |
6635 | |
6636 instruct membar_acquire_lock() %{ | |
6637 match(MemBarAcquire); | |
6638 predicate(Matcher::prior_fast_lock(n)); | |
6639 ins_cost(0); | |
6640 | |
6641 size(0); | |
6642 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6643 ins_encode( ); | |
6644 ins_pipe(empty); | |
6645 %} | |
6646 | |
6647 instruct membar_release() %{ | |
6648 match(MemBarRelease); | |
6649 ins_cost(4*MEMORY_REF_COST); | |
6650 | |
6651 size(0); | |
6652 format %{ "MEMBAR-release" %} | |
6653 ins_encode( enc_membar_release ); | |
6654 ins_pipe(long_memory_op); | |
6655 %} | |
6656 | |
6657 instruct membar_release_lock() %{ | |
6658 match(MemBarRelease); | |
6659 predicate(Matcher::post_fast_unlock(n)); | |
6660 ins_cost(0); | |
6661 | |
6662 size(0); | |
6663 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6664 ins_encode( ); | |
6665 ins_pipe(empty); | |
6666 %} | |
6667 | |
6668 instruct membar_volatile() %{ | |
6669 match(MemBarVolatile); | |
6670 ins_cost(4*MEMORY_REF_COST); | |
6671 | |
6672 size(4); | |
6673 format %{ "MEMBAR-volatile" %} | |
6674 ins_encode( enc_membar_volatile ); | |
6675 ins_pipe(long_memory_op); | |
6676 %} | |
6677 | |
6678 instruct unnecessary_membar_volatile() %{ | |
6679 match(MemBarVolatile); | |
6680 predicate(Matcher::post_store_load_barrier(n)); | |
6681 ins_cost(0); | |
6682 | |
6683 size(0); | |
6684 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6685 ins_encode( ); | |
6686 ins_pipe(empty); | |
6687 %} | |
6688 | |
6689 //----------Register Move Instructions----------------------------------------- | |
6690 instruct roundDouble_nop(regD dst) %{ | |
6691 match(Set dst (RoundDouble dst)); | |
6692 ins_cost(0); | |
6693 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6694 ins_encode( ); | |
6695 ins_pipe(empty); | |
6696 %} | |
6697 | |
6698 | |
6699 instruct roundFloat_nop(regF dst) %{ | |
6700 match(Set dst (RoundFloat dst)); | |
6701 ins_cost(0); | |
6702 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6703 ins_encode( ); | |
6704 ins_pipe(empty); | |
6705 %} | |
6706 | |
6707 | |
6708 // Cast Index to Pointer for unsafe natives | |
6709 instruct castX2P(iRegX src, iRegP dst) %{ | |
6710 match(Set dst (CastX2P src)); | |
6711 | |
6712 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6713 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6714 ins_pipe(ialu_reg); | |
6715 %} | |
6716 | |
6717 // Cast Pointer to Index for unsafe natives | |
6718 instruct castP2X(iRegP src, iRegX dst) %{ | |
6719 match(Set dst (CastP2X src)); | |
6720 | |
6721 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6722 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6723 ins_pipe(ialu_reg); | |
6724 %} | |
6725 | |
6726 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6727 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6728 match(Set stkSlot src); // chain rule | |
6729 ins_cost(MEMORY_REF_COST); | |
6730 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6731 opcode(Assembler::stdf_op3); | |
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6732 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6733 ins_pipe(fstoreD_stk_reg); |
6734 %} | |
6735 | |
6736 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6737 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6738 match(Set dst stkSlot); // chain rule | |
6739 ins_cost(MEMORY_REF_COST); | |
6740 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6741 opcode(Assembler::lddf_op3); | |
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6742 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6743 ins_pipe(floadD_stk); |
6744 %} | |
6745 | |
6746 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6747 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6748 match(Set stkSlot src); // chain rule | |
6749 ins_cost(MEMORY_REF_COST); | |
6750 format %{ "STF $src,$stkSlot\t!stk" %} | |
6751 opcode(Assembler::stf_op3); | |
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6752 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6753 ins_pipe(fstoreF_stk_reg); |
6754 %} | |
6755 | |
6756 //----------Conditional Move--------------------------------------------------- | |
6757 // Conditional move | |
6758 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6759 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6760 ins_cost(150); | |
6761 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6762 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6763 ins_pipe(ialu_reg); | |
6764 %} | |
6765 | |
6766 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6767 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6768 ins_cost(140); | |
6769 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6770 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6771 ins_pipe(ialu_imm); | |
6772 %} | |
6773 | |
6774 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6775 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6776 ins_cost(150); | |
6777 size(4); | |
6778 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6779 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6780 ins_pipe(ialu_reg); | |
6781 %} | |
6782 | |
6783 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6784 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6785 ins_cost(140); | |
6786 size(4); | |
6787 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6788 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6789 ins_pipe(ialu_imm); | |
6790 %} | |
6791 | |
1160
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|
6792 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6793 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6794 ins_cost(150); | |
6795 size(4); | |
6796 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6797 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6798 ins_pipe(ialu_reg); | |
6799 %} | |
6800 | |
1160
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diff
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|
6801 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6802 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6803 ins_cost(140); | |
6804 size(4); | |
6805 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6806 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6807 ins_pipe(ialu_imm); | |
6808 %} | |
6809 | |
6810 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6811 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6812 ins_cost(150); | |
6813 size(4); | |
6814 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6815 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6816 ins_pipe(ialu_reg); | |
6817 %} | |
6818 | |
6819 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6820 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6821 ins_cost(140); | |
6822 size(4); | |
6823 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6824 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6825 ins_pipe(ialu_imm); | |
6826 %} | |
6827 | |
164
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changeset
|
6828 // Conditional move for RegN. Only cmov(reg,reg). |
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diff
changeset
|
6829 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
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changeset
|
6830 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
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163
diff
changeset
|
6831 ins_cost(150); |
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163
diff
changeset
|
6832 format %{ "MOV$cmp $pcc,$src,$dst" %} |
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parents:
163
diff
changeset
|
6833 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
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parents:
163
diff
changeset
|
6834 ins_pipe(ialu_reg); |
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parents:
163
diff
changeset
|
6835 %} |
c436414a719e
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parents:
163
diff
changeset
|
6836 |
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parents:
163
diff
changeset
|
6837 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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parents:
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diff
changeset
|
6838 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
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parents:
163
diff
changeset
|
6839 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
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parents:
163
diff
changeset
|
6840 ins_cost(150); |
c436414a719e
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parents:
163
diff
changeset
|
6841 size(4); |
c436414a719e
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parents:
163
diff
changeset
|
6842 format %{ "MOV$cmp $icc,$src,$dst" %} |
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parents:
163
diff
changeset
|
6843 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
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parents:
163
diff
changeset
|
6844 ins_pipe(ialu_reg); |
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parents:
163
diff
changeset
|
6845 %} |
c436414a719e
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parents:
163
diff
changeset
|
6846 |
1160
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diff
changeset
|
6847 // This instruction also works with CmpN so we don't need cmovNN_reg. |
f24201449cac
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diff
changeset
|
6848 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6849 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6850 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6851 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6852 format %{ "MOV$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6853 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6854 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6855 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
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diff
changeset
|
6856 |
164
c436414a719e
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parents:
163
diff
changeset
|
6857 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
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parents:
163
diff
changeset
|
6858 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6859 ins_cost(150); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6860 size(4); |
c436414a719e
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parents:
163
diff
changeset
|
6861 format %{ "MOV$cmp $fcc,$src,$dst" %} |
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parents:
163
diff
changeset
|
6862 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
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parents:
163
diff
changeset
|
6863 ins_pipe(ialu_reg); |
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parents:
163
diff
changeset
|
6864 %} |
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parents:
163
diff
changeset
|
6865 |
0 | 6866 // Conditional move |
6867 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6868 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6869 ins_cost(150); | |
6870 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6871 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6872 ins_pipe(ialu_reg); | |
6873 %} | |
6874 | |
6875 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6876 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6877 ins_cost(140); | |
6878 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6879 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6880 ins_pipe(ialu_imm); | |
6881 %} | |
6882 | |
164
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parents:
163
diff
changeset
|
6883 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6884 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6885 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6886 ins_cost(150); | |
6887 | |
6888 size(4); | |
6889 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6890 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6891 ins_pipe(ialu_reg); | |
6892 %} | |
6893 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6894 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6895 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6896 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6897 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6898 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6899 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6900 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6901 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6902 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6903 |
0 | 6904 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
6905 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6906 ins_cost(140); | |
6907 | |
6908 size(4); | |
6909 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6910 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6911 ins_pipe(ialu_imm); | |
6912 %} | |
6913 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6914 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6915 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6916 ins_cost(140); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6917 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6918 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6919 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6920 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6921 ins_pipe(ialu_imm); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6922 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6923 |
0 | 6924 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
6925 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6926 ins_cost(150); | |
6927 size(4); | |
6928 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6929 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6930 ins_pipe(ialu_imm); | |
6931 %} | |
6932 | |
6933 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6934 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6935 ins_cost(140); | |
6936 size(4); | |
6937 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6938 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6939 ins_pipe(ialu_imm); | |
6940 %} | |
6941 | |
6942 // Conditional move | |
6943 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6944 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6945 ins_cost(150); | |
6946 opcode(0x101); | |
6947 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6948 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6949 ins_pipe(int_conditional_float_move); | |
6950 %} | |
6951 | |
6952 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6953 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6954 ins_cost(150); | |
6955 | |
6956 size(4); | |
6957 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6958 opcode(0x101); | |
6959 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6960 ins_pipe(int_conditional_float_move); | |
6961 %} | |
6962 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6963 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6964 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6965 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6966 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6967 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6968 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
f24201449cac
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1137
diff
changeset
|
6969 opcode(0x101); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6970 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6971 ins_pipe(int_conditional_float_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6972 %} |
f24201449cac
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1137
diff
changeset
|
6973 |
0 | 6974 // Conditional move, |
6975 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6976 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6977 ins_cost(150); | |
6978 size(4); | |
6979 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6980 opcode(0x1); | |
6981 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6982 ins_pipe(int_conditional_double_move); | |
6983 %} | |
6984 | |
6985 // Conditional move | |
6986 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6987 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
6988 ins_cost(150); | |
6989 size(4); | |
6990 opcode(0x102); | |
6991 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6992 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6993 ins_pipe(int_conditional_double_move); | |
6994 %} | |
6995 | |
6996 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
6997 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
6998 ins_cost(150); | |
6999 | |
7000 size(4); | |
7001 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
7002 opcode(0x102); | |
7003 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
7004 ins_pipe(int_conditional_double_move); | |
7005 %} | |
7006 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7007 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7008 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7009 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
7010 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
7011 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7012 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7013 opcode(0x102); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7014 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7015 ins_pipe(int_conditional_double_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7016 %} |
f24201449cac
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1137
diff
changeset
|
7017 |
0 | 7018 // Conditional move, |
7019 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
7020 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
7021 ins_cost(150); | |
7022 size(4); | |
7023 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
7024 opcode(0x2); | |
7025 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
7026 ins_pipe(int_conditional_double_move); | |
7027 %} | |
7028 | |
7029 // Conditional move | |
7030 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
7031 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7032 ins_cost(150); | |
7033 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7034 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7035 ins_pipe(ialu_reg); | |
7036 %} | |
7037 | |
7038 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
7039 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7040 ins_cost(140); | |
7041 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7042 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7043 ins_pipe(ialu_imm); | |
7044 %} | |
7045 | |
7046 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
7047 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
7048 ins_cost(150); | |
7049 | |
7050 size(4); | |
7051 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
7052 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
7053 ins_pipe(ialu_reg); | |
7054 %} | |
7055 | |
7056 | |
1160
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7057 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
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7058 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
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|
7059 ins_cost(150); |
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|
7060 |
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|
7061 size(4); |
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|
7062 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
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7063 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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|
7064 ins_pipe(ialu_reg); |
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|
7065 %} |
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|
7066 |
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7067 |
0 | 7068 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
7069 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
7070 ins_cost(150); | |
7071 | |
7072 size(4); | |
7073 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
7074 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
7075 ins_pipe(ialu_reg); | |
7076 %} | |
7077 | |
7078 | |
7079 | |
7080 //----------OS and Locking Instructions---------------------------------------- | |
7081 | |
7082 // This name is KNOWN by the ADLC and cannot be changed. | |
7083 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
7084 // for this guy. | |
7085 instruct tlsLoadP(g2RegP dst) %{ | |
7086 match(Set dst (ThreadLocal)); | |
7087 | |
7088 size(0); | |
7089 ins_cost(0); | |
7090 format %{ "# TLS is in G2" %} | |
7091 ins_encode( /*empty encoding*/ ); | |
7092 ins_pipe(ialu_none); | |
7093 %} | |
7094 | |
7095 instruct checkCastPP( iRegP dst ) %{ | |
7096 match(Set dst (CheckCastPP dst)); | |
7097 | |
7098 size(0); | |
7099 format %{ "# checkcastPP of $dst" %} | |
7100 ins_encode( /*empty encoding*/ ); | |
7101 ins_pipe(empty); | |
7102 %} | |
7103 | |
7104 | |
7105 instruct castPP( iRegP dst ) %{ | |
7106 match(Set dst (CastPP dst)); | |
7107 format %{ "# castPP of $dst" %} | |
7108 ins_encode( /*empty encoding*/ ); | |
7109 ins_pipe(empty); | |
7110 %} | |
7111 | |
7112 instruct castII( iRegI dst ) %{ | |
7113 match(Set dst (CastII dst)); | |
7114 format %{ "# castII of $dst" %} | |
7115 ins_encode( /*empty encoding*/ ); | |
7116 ins_cost(0); | |
7117 ins_pipe(empty); | |
7118 %} | |
7119 | |
7120 //----------Arithmetic Instructions-------------------------------------------- | |
7121 // Addition Instructions | |
7122 // Register Addition | |
7123 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7124 match(Set dst (AddI src1 src2)); | |
7125 | |
7126 size(4); | |
7127 format %{ "ADD $src1,$src2,$dst" %} | |
7128 ins_encode %{ | |
7129 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7130 %} | |
7131 ins_pipe(ialu_reg_reg); | |
7132 %} | |
7133 | |
7134 // Immediate Addition | |
7135 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7136 match(Set dst (AddI src1 src2)); | |
7137 | |
7138 size(4); | |
7139 format %{ "ADD $src1,$src2,$dst" %} | |
7140 opcode(Assembler::add_op3, Assembler::arith_op); | |
7141 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7142 ins_pipe(ialu_reg_imm); | |
7143 %} | |
7144 | |
7145 // Pointer Register Addition | |
7146 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7147 match(Set dst (AddP src1 src2)); | |
7148 | |
7149 size(4); | |
7150 format %{ "ADD $src1,$src2,$dst" %} | |
7151 opcode(Assembler::add_op3, Assembler::arith_op); | |
7152 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7153 ins_pipe(ialu_reg_reg); | |
7154 %} | |
7155 | |
7156 // Pointer Immediate Addition | |
7157 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7158 match(Set dst (AddP src1 src2)); | |
7159 | |
7160 size(4); | |
7161 format %{ "ADD $src1,$src2,$dst" %} | |
7162 opcode(Assembler::add_op3, Assembler::arith_op); | |
7163 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7164 ins_pipe(ialu_reg_imm); | |
7165 %} | |
7166 | |
7167 // Long Addition | |
7168 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7169 match(Set dst (AddL src1 src2)); | |
7170 | |
7171 size(4); | |
7172 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7173 opcode(Assembler::add_op3, Assembler::arith_op); | |
7174 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7175 ins_pipe(ialu_reg_reg); | |
7176 %} | |
7177 | |
7178 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7179 match(Set dst (AddL src1 con)); | |
7180 | |
7181 size(4); | |
7182 format %{ "ADD $src1,$con,$dst" %} | |
7183 opcode(Assembler::add_op3, Assembler::arith_op); | |
7184 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7185 ins_pipe(ialu_reg_imm); | |
7186 %} | |
7187 | |
7188 //----------Conditional_store-------------------------------------------------- | |
7189 // Conditional-store of the updated heap-top. | |
7190 // Used during allocation of the shared heap. | |
7191 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7192 | |
7193 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7194 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7195 match(Set dst (LoadPLocked mem)); | |
7196 ins_cost(MEMORY_REF_COST); | |
7197 | |
7198 #ifndef _LP64 | |
7199 size(4); | |
7200 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7201 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7202 #else | |
7203 format %{ "LDX $mem,$dst\t! ptr" %} | |
7204 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7205 #endif | |
7206 ins_encode( form3_mem_reg( mem, dst ) ); | |
7207 ins_pipe(iload_mem); | |
7208 %} | |
7209 | |
7210 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
7211 instruct loadLLocked(iRegL dst, memory mem) %{ | |
7212 match(Set dst (LoadLLocked mem)); | |
7213 ins_cost(MEMORY_REF_COST); | |
7214 size(4); | |
7215 format %{ "LDX $mem,$dst\t! long" %} | |
7216 opcode(Assembler::ldx_op3); | |
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7217 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 7218 ins_pipe(iload_mem); |
7219 %} | |
7220 | |
7221 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7222 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7223 effect( KILL newval ); | |
7224 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7225 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7226 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7227 ins_pipe( long_memory_op ); | |
7228 %} | |
7229 | |
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7230 // Conditional-store of an int value. |
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7231 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
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7232 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
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7233 effect( KILL newval ); |
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7234 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7235 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7236 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7237 ins_pipe( long_memory_op ); |
7238 %} | |
7239 | |
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7240 // Conditional-store of a long value. |
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7241 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
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7242 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
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7243 effect( KILL newval ); |
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7244 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7245 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7246 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7247 ins_pipe( long_memory_op ); |
7248 %} | |
7249 | |
7250 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7251 | |
7252 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7253 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
7254 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7255 format %{ | |
7256 "MOV $newval,O7\n\t" | |
7257 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7258 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7259 "MOV 1,$res\n\t" | |
7260 "MOVne xcc,R_G0,$res" | |
7261 %} | |
7262 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7263 enc_lflags_ne_to_boolean(res) ); | |
7264 ins_pipe( long_memory_op ); | |
7265 %} | |
7266 | |
7267 | |
7268 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7269 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7270 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7271 format %{ | |
7272 "MOV $newval,O7\n\t" | |
7273 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7274 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7275 "MOV 1,$res\n\t" | |
7276 "MOVne icc,R_G0,$res" | |
7277 %} | |
7278 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7279 enc_iflags_ne_to_boolean(res) ); | |
7280 ins_pipe( long_memory_op ); | |
7281 %} | |
7282 | |
7283 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7284 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
7285 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7286 format %{ | |
7287 "MOV $newval,O7\n\t" | |
113
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7288 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7289 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7290 "MOV 1,$res\n\t" | |
7291 "MOVne xcc,R_G0,$res" | |
7292 %} | |
113
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7293 #ifdef _LP64 |
0 | 7294 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7295 enc_lflags_ne_to_boolean(res) ); | |
7296 #else | |
113
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7297 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7298 enc_iflags_ne_to_boolean(res) ); |
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7299 #endif |
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7300 ins_pipe( long_memory_op ); |
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7301 %} |
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7302 |
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7303 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
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7304 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7305 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7306 format %{ |
7307 "MOV $newval,O7\n\t" | |
7308 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7309 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7310 "MOV 1,$res\n\t" | |
7311 "MOVne icc,R_G0,$res" | |
7312 %} | |
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7313 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7314 enc_iflags_ne_to_boolean(res) ); |
0 | 7315 ins_pipe( long_memory_op ); |
7316 %} | |
7317 | |
7318 //--------------------- | |
7319 // Subtraction Instructions | |
7320 // Register Subtraction | |
7321 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7322 match(Set dst (SubI src1 src2)); | |
7323 | |
7324 size(4); | |
7325 format %{ "SUB $src1,$src2,$dst" %} | |
7326 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7327 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7328 ins_pipe(ialu_reg_reg); | |
7329 %} | |
7330 | |
7331 // Immediate Subtraction | |
7332 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7333 match(Set dst (SubI src1 src2)); | |
7334 | |
7335 size(4); | |
7336 format %{ "SUB $src1,$src2,$dst" %} | |
7337 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7338 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7339 ins_pipe(ialu_reg_imm); | |
7340 %} | |
7341 | |
7342 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7343 match(Set dst (SubI zero src2)); | |
7344 | |
7345 size(4); | |
7346 format %{ "NEG $src2,$dst" %} | |
7347 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7348 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7349 ins_pipe(ialu_zero_reg); | |
7350 %} | |
7351 | |
7352 // Long subtraction | |
7353 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7354 match(Set dst (SubL src1 src2)); | |
7355 | |
7356 size(4); | |
7357 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7358 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7359 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7360 ins_pipe(ialu_reg_reg); | |
7361 %} | |
7362 | |
7363 // Immediate Subtraction | |
7364 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7365 match(Set dst (SubL src1 con)); | |
7366 | |
7367 size(4); | |
7368 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7369 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7370 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7371 ins_pipe(ialu_reg_imm); | |
7372 %} | |
7373 | |
7374 // Long negation | |
7375 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7376 match(Set dst (SubL zero src2)); | |
7377 | |
7378 size(4); | |
7379 format %{ "NEG $src2,$dst\t! long" %} | |
7380 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7381 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7382 ins_pipe(ialu_zero_reg); | |
7383 %} | |
7384 | |
7385 // Multiplication Instructions | |
7386 // Integer Multiplication | |
7387 // Register Multiplication | |
7388 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7389 match(Set dst (MulI src1 src2)); | |
7390 | |
7391 size(4); | |
7392 format %{ "MULX $src1,$src2,$dst" %} | |
7393 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7394 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7395 ins_pipe(imul_reg_reg); | |
7396 %} | |
7397 | |
7398 // Immediate Multiplication | |
7399 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7400 match(Set dst (MulI src1 src2)); | |
7401 | |
7402 size(4); | |
7403 format %{ "MULX $src1,$src2,$dst" %} | |
7404 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7405 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7406 ins_pipe(imul_reg_imm); | |
7407 %} | |
7408 | |
7409 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7410 match(Set dst (MulL src1 src2)); | |
7411 ins_cost(DEFAULT_COST * 5); | |
7412 size(4); | |
7413 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7414 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7415 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7416 ins_pipe(mulL_reg_reg); | |
7417 %} | |
7418 | |
7419 // Immediate Multiplication | |
7420 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7421 match(Set dst (MulL src1 src2)); | |
7422 ins_cost(DEFAULT_COST * 5); | |
7423 size(4); | |
7424 format %{ "MULX $src1,$src2,$dst" %} | |
7425 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7426 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7427 ins_pipe(mulL_reg_imm); | |
7428 %} | |
7429 | |
7430 // Integer Division | |
7431 // Register Division | |
7432 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7433 match(Set dst (DivI src1 src2)); | |
7434 ins_cost((2+71)*DEFAULT_COST); | |
7435 | |
7436 format %{ "SRA $src2,0,$src2\n\t" | |
7437 "SRA $src1,0,$src1\n\t" | |
7438 "SDIVX $src1,$src2,$dst" %} | |
7439 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7440 ins_pipe(sdiv_reg_reg); | |
7441 %} | |
7442 | |
7443 // Immediate Division | |
7444 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7445 match(Set dst (DivI src1 src2)); | |
7446 ins_cost((2+71)*DEFAULT_COST); | |
7447 | |
7448 format %{ "SRA $src1,0,$src1\n\t" | |
7449 "SDIVX $src1,$src2,$dst" %} | |
7450 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7451 ins_pipe(sdiv_reg_imm); | |
7452 %} | |
7453 | |
7454 //----------Div-By-10-Expansion------------------------------------------------ | |
7455 // Extract hi bits of a 32x32->64 bit multiply. | |
7456 // Expand rule only, not matched | |
7457 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7458 effect( DEF dst, USE src1, USE src2 ); | |
7459 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7460 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7461 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7462 ins_pipe(sdiv_reg_reg); | |
7463 %} | |
7464 | |
605 | 7465 // Magic constant, reciprocal of 10 |
0 | 7466 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7467 effect( DEF dst ); | |
7468 | |
7469 size(8); | |
7470 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7471 ins_encode( Set32(0x66666667, dst) ); | |
7472 ins_pipe(ialu_hi_lo_reg); | |
7473 %} | |
7474 | |
605 | 7475 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7476 instruct sra_31( iRegI dst, iRegI src ) %{ |
7477 effect( DEF dst, USE src ); | |
7478 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7479 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7480 ins_pipe(ialu_reg_reg); | |
7481 %} | |
7482 | |
7483 // Arithmetic Shift Right by 8-bit immediate | |
7484 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7485 effect( DEF dst, USE src ); | |
7486 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7487 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7488 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7489 ins_pipe(ialu_reg_imm); | |
7490 %} | |
7491 | |
7492 // Integer DIV with 10 | |
7493 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7494 match(Set dst (DivI src div)); | |
7495 ins_cost((6+6)*DEFAULT_COST); | |
7496 expand %{ | |
7497 iRegIsafe tmp1; // Killed temps; | |
7498 iRegIsafe tmp2; // Killed temps; | |
7499 iRegI tmp3; // Killed temps; | |
7500 iRegI tmp4; // Killed temps; | |
7501 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7502 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7503 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7504 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7505 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7506 %} | |
7507 %} | |
7508 | |
7509 // Register Long Division | |
7510 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7511 match(Set dst (DivL src1 src2)); | |
7512 ins_cost(DEFAULT_COST*71); | |
7513 size(4); | |
7514 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7515 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7516 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7517 ins_pipe(divL_reg_reg); | |
7518 %} | |
7519 | |
7520 // Register Long Division | |
7521 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7522 match(Set dst (DivL src1 src2)); | |
7523 ins_cost(DEFAULT_COST*71); | |
7524 size(4); | |
7525 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7526 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7527 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7528 ins_pipe(divL_reg_imm); | |
7529 %} | |
7530 | |
7531 // Integer Remainder | |
7532 // Register Remainder | |
7533 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7534 match(Set dst (ModI src1 src2)); | |
7535 effect( KILL ccr, KILL temp); | |
7536 | |
7537 format %{ "SREM $src1,$src2,$dst" %} | |
7538 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7539 ins_pipe(sdiv_reg_reg); | |
7540 %} | |
7541 | |
7542 // Immediate Remainder | |
7543 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7544 match(Set dst (ModI src1 src2)); | |
7545 effect( KILL ccr, KILL temp); | |
7546 | |
7547 format %{ "SREM $src1,$src2,$dst" %} | |
7548 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7549 ins_pipe(sdiv_reg_imm); | |
7550 %} | |
7551 | |
7552 // Register Long Remainder | |
7553 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7554 effect(DEF dst, USE src1, USE src2); | |
7555 size(4); | |
7556 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7557 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7558 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7559 ins_pipe(divL_reg_reg); | |
7560 %} | |
7561 | |
7562 // Register Long Division | |
7563 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7564 effect(DEF dst, USE src1, USE src2); | |
7565 size(4); | |
7566 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7567 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7568 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7569 ins_pipe(divL_reg_imm); | |
7570 %} | |
7571 | |
7572 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7573 effect(DEF dst, USE src1, USE src2); | |
7574 size(4); | |
7575 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7576 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7577 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7578 ins_pipe(mulL_reg_reg); | |
7579 %} | |
7580 | |
7581 // Immediate Multiplication | |
7582 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7583 effect(DEF dst, USE src1, USE src2); | |
7584 size(4); | |
7585 format %{ "MULX $src1,$src2,$dst" %} | |
7586 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7587 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7588 ins_pipe(mulL_reg_imm); | |
7589 %} | |
7590 | |
7591 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7592 effect(DEF dst, USE src1, USE src2); | |
7593 size(4); | |
7594 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7595 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7596 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7597 ins_pipe(ialu_reg_reg); | |
7598 %} | |
7599 | |
7600 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7601 effect(DEF dst, USE src1, USE src2); | |
7602 size(4); | |
7603 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7604 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7605 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7606 ins_pipe(ialu_reg_reg); | |
7607 %} | |
7608 | |
7609 // Register Long Remainder | |
7610 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7611 match(Set dst (ModL src1 src2)); | |
7612 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7613 expand %{ | |
7614 iRegL tmp1; | |
7615 iRegL tmp2; | |
7616 divL_reg_reg_1(tmp1, src1, src2); | |
7617 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7618 subL_reg_reg_1(dst, src1, tmp2); | |
7619 %} | |
7620 %} | |
7621 | |
7622 // Register Long Remainder | |
7623 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7624 match(Set dst (ModL src1 src2)); | |
7625 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7626 expand %{ | |
7627 iRegL tmp1; | |
7628 iRegL tmp2; | |
7629 divL_reg_imm13_1(tmp1, src1, src2); | |
7630 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7631 subL_reg_reg_2 (dst, src1, tmp2); | |
7632 %} | |
7633 %} | |
7634 | |
7635 // Integer Shift Instructions | |
7636 // Register Shift Left | |
7637 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7638 match(Set dst (LShiftI src1 src2)); | |
7639 | |
7640 size(4); | |
7641 format %{ "SLL $src1,$src2,$dst" %} | |
7642 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7643 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7644 ins_pipe(ialu_reg_reg); | |
7645 %} | |
7646 | |
7647 // Register Shift Left Immediate | |
7648 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7649 match(Set dst (LShiftI src1 src2)); | |
7650 | |
7651 size(4); | |
7652 format %{ "SLL $src1,$src2,$dst" %} | |
7653 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7654 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7655 ins_pipe(ialu_reg_imm); | |
7656 %} | |
7657 | |
7658 // Register Shift Left | |
7659 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7660 match(Set dst (LShiftL src1 src2)); | |
7661 | |
7662 size(4); | |
7663 format %{ "SLLX $src1,$src2,$dst" %} | |
7664 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7665 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7666 ins_pipe(ialu_reg_reg); | |
7667 %} | |
7668 | |
7669 // Register Shift Left Immediate | |
7670 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7671 match(Set dst (LShiftL src1 src2)); | |
7672 | |
7673 size(4); | |
7674 format %{ "SLLX $src1,$src2,$dst" %} | |
7675 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7676 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7677 ins_pipe(ialu_reg_imm); | |
7678 %} | |
7679 | |
7680 // Register Arithmetic Shift Right | |
7681 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7682 match(Set dst (RShiftI src1 src2)); | |
7683 size(4); | |
7684 format %{ "SRA $src1,$src2,$dst" %} | |
7685 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7686 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7687 ins_pipe(ialu_reg_reg); | |
7688 %} | |
7689 | |
7690 // Register Arithmetic Shift Right Immediate | |
7691 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7692 match(Set dst (RShiftI src1 src2)); | |
7693 | |
7694 size(4); | |
7695 format %{ "SRA $src1,$src2,$dst" %} | |
7696 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7697 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7698 ins_pipe(ialu_reg_imm); | |
7699 %} | |
7700 | |
7701 // Register Shift Right Arithmatic Long | |
7702 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7703 match(Set dst (RShiftL src1 src2)); | |
7704 | |
7705 size(4); | |
7706 format %{ "SRAX $src1,$src2,$dst" %} | |
7707 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7708 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7709 ins_pipe(ialu_reg_reg); | |
7710 %} | |
7711 | |
7712 // Register Shift Left Immediate | |
7713 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7714 match(Set dst (RShiftL src1 src2)); | |
7715 | |
7716 size(4); | |
7717 format %{ "SRAX $src1,$src2,$dst" %} | |
7718 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7719 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7720 ins_pipe(ialu_reg_imm); | |
7721 %} | |
7722 | |
7723 // Register Shift Right | |
7724 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7725 match(Set dst (URShiftI src1 src2)); | |
7726 | |
7727 size(4); | |
7728 format %{ "SRL $src1,$src2,$dst" %} | |
7729 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7730 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7731 ins_pipe(ialu_reg_reg); | |
7732 %} | |
7733 | |
7734 // Register Shift Right Immediate | |
7735 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7736 match(Set dst (URShiftI src1 src2)); | |
7737 | |
7738 size(4); | |
7739 format %{ "SRL $src1,$src2,$dst" %} | |
7740 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7741 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7742 ins_pipe(ialu_reg_imm); | |
7743 %} | |
7744 | |
7745 // Register Shift Right | |
7746 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7747 match(Set dst (URShiftL src1 src2)); | |
7748 | |
7749 size(4); | |
7750 format %{ "SRLX $src1,$src2,$dst" %} | |
7751 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7752 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7753 ins_pipe(ialu_reg_reg); | |
7754 %} | |
7755 | |
7756 // Register Shift Right Immediate | |
7757 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7758 match(Set dst (URShiftL src1 src2)); | |
7759 | |
7760 size(4); | |
7761 format %{ "SRLX $src1,$src2,$dst" %} | |
7762 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7763 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7764 ins_pipe(ialu_reg_imm); | |
7765 %} | |
7766 | |
7767 // Register Shift Right Immediate with a CastP2X | |
7768 #ifdef _LP64 | |
7769 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7770 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7771 size(4); | |
7772 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7773 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7774 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7775 ins_pipe(ialu_reg_imm); | |
7776 %} | |
7777 #else | |
7778 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7779 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7780 size(4); | |
7781 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7782 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7783 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7784 ins_pipe(ialu_reg_imm); | |
7785 %} | |
7786 #endif | |
7787 | |
7788 | |
7789 //----------Floating Point Arithmetic Instructions----------------------------- | |
7790 | |
7791 // Add float single precision | |
7792 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7793 match(Set dst (AddF src1 src2)); | |
7794 | |
7795 size(4); | |
7796 format %{ "FADDS $src1,$src2,$dst" %} | |
7797 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7798 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7799 ins_pipe(faddF_reg_reg); | |
7800 %} | |
7801 | |
7802 // Add float double precision | |
7803 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7804 match(Set dst (AddD src1 src2)); | |
7805 | |
7806 size(4); | |
7807 format %{ "FADDD $src1,$src2,$dst" %} | |
7808 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7809 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7810 ins_pipe(faddD_reg_reg); | |
7811 %} | |
7812 | |
7813 // Sub float single precision | |
7814 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7815 match(Set dst (SubF src1 src2)); | |
7816 | |
7817 size(4); | |
7818 format %{ "FSUBS $src1,$src2,$dst" %} | |
7819 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7820 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7821 ins_pipe(faddF_reg_reg); | |
7822 %} | |
7823 | |
7824 // Sub float double precision | |
7825 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7826 match(Set dst (SubD src1 src2)); | |
7827 | |
7828 size(4); | |
7829 format %{ "FSUBD $src1,$src2,$dst" %} | |
7830 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7831 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7832 ins_pipe(faddD_reg_reg); | |
7833 %} | |
7834 | |
7835 // Mul float single precision | |
7836 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7837 match(Set dst (MulF src1 src2)); | |
7838 | |
7839 size(4); | |
7840 format %{ "FMULS $src1,$src2,$dst" %} | |
7841 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7842 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7843 ins_pipe(fmulF_reg_reg); | |
7844 %} | |
7845 | |
7846 // Mul float double precision | |
7847 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7848 match(Set dst (MulD src1 src2)); | |
7849 | |
7850 size(4); | |
7851 format %{ "FMULD $src1,$src2,$dst" %} | |
7852 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7853 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7854 ins_pipe(fmulD_reg_reg); | |
7855 %} | |
7856 | |
7857 // Div float single precision | |
7858 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7859 match(Set dst (DivF src1 src2)); | |
7860 | |
7861 size(4); | |
7862 format %{ "FDIVS $src1,$src2,$dst" %} | |
7863 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7864 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7865 ins_pipe(fdivF_reg_reg); | |
7866 %} | |
7867 | |
7868 // Div float double precision | |
7869 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7870 match(Set dst (DivD src1 src2)); | |
7871 | |
7872 size(4); | |
7873 format %{ "FDIVD $src1,$src2,$dst" %} | |
7874 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7875 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7876 ins_pipe(fdivD_reg_reg); | |
7877 %} | |
7878 | |
7879 // Absolute float double precision | |
7880 instruct absD_reg(regD dst, regD src) %{ | |
7881 match(Set dst (AbsD src)); | |
7882 | |
7883 format %{ "FABSd $src,$dst" %} | |
7884 ins_encode(fabsd(dst, src)); | |
7885 ins_pipe(faddD_reg); | |
7886 %} | |
7887 | |
7888 // Absolute float single precision | |
7889 instruct absF_reg(regF dst, regF src) %{ | |
7890 match(Set dst (AbsF src)); | |
7891 | |
7892 format %{ "FABSs $src,$dst" %} | |
7893 ins_encode(fabss(dst, src)); | |
7894 ins_pipe(faddF_reg); | |
7895 %} | |
7896 | |
7897 instruct negF_reg(regF dst, regF src) %{ | |
7898 match(Set dst (NegF src)); | |
7899 | |
7900 size(4); | |
7901 format %{ "FNEGs $src,$dst" %} | |
7902 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7903 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7904 ins_pipe(faddF_reg); | |
7905 %} | |
7906 | |
7907 instruct negD_reg(regD dst, regD src) %{ | |
7908 match(Set dst (NegD src)); | |
7909 | |
7910 format %{ "FNEGd $src,$dst" %} | |
7911 ins_encode(fnegd(dst, src)); | |
7912 ins_pipe(faddD_reg); | |
7913 %} | |
7914 | |
7915 // Sqrt float double precision | |
7916 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7917 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7918 | |
7919 size(4); | |
7920 format %{ "FSQRTS $src,$dst" %} | |
7921 ins_encode(fsqrts(dst, src)); | |
7922 ins_pipe(fdivF_reg_reg); | |
7923 %} | |
7924 | |
7925 // Sqrt float double precision | |
7926 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7927 match(Set dst (SqrtD src)); | |
7928 | |
7929 size(4); | |
7930 format %{ "FSQRTD $src,$dst" %} | |
7931 ins_encode(fsqrtd(dst, src)); | |
7932 ins_pipe(fdivD_reg_reg); | |
7933 %} | |
7934 | |
7935 //----------Logical Instructions----------------------------------------------- | |
7936 // And Instructions | |
7937 // Register And | |
7938 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7939 match(Set dst (AndI src1 src2)); | |
7940 | |
7941 size(4); | |
7942 format %{ "AND $src1,$src2,$dst" %} | |
7943 opcode(Assembler::and_op3, Assembler::arith_op); | |
7944 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7945 ins_pipe(ialu_reg_reg); | |
7946 %} | |
7947 | |
7948 // Immediate And | |
7949 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7950 match(Set dst (AndI src1 src2)); | |
7951 | |
7952 size(4); | |
7953 format %{ "AND $src1,$src2,$dst" %} | |
7954 opcode(Assembler::and_op3, Assembler::arith_op); | |
7955 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7956 ins_pipe(ialu_reg_imm); | |
7957 %} | |
7958 | |
7959 // Register And Long | |
7960 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7961 match(Set dst (AndL src1 src2)); | |
7962 | |
7963 ins_cost(DEFAULT_COST); | |
7964 size(4); | |
7965 format %{ "AND $src1,$src2,$dst\t! long" %} | |
7966 opcode(Assembler::and_op3, Assembler::arith_op); | |
7967 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7968 ins_pipe(ialu_reg_reg); | |
7969 %} | |
7970 | |
7971 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7972 match(Set dst (AndL src1 con)); | |
7973 | |
7974 ins_cost(DEFAULT_COST); | |
7975 size(4); | |
7976 format %{ "AND $src1,$con,$dst\t! long" %} | |
7977 opcode(Assembler::and_op3, Assembler::arith_op); | |
7978 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7979 ins_pipe(ialu_reg_imm); | |
7980 %} | |
7981 | |
7982 // Or Instructions | |
7983 // Register Or | |
7984 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7985 match(Set dst (OrI src1 src2)); | |
7986 | |
7987 size(4); | |
7988 format %{ "OR $src1,$src2,$dst" %} | |
7989 opcode(Assembler::or_op3, Assembler::arith_op); | |
7990 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7991 ins_pipe(ialu_reg_reg); | |
7992 %} | |
7993 | |
7994 // Immediate Or | |
7995 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7996 match(Set dst (OrI src1 src2)); | |
7997 | |
7998 size(4); | |
7999 format %{ "OR $src1,$src2,$dst" %} | |
8000 opcode(Assembler::or_op3, Assembler::arith_op); | |
8001 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8002 ins_pipe(ialu_reg_imm); | |
8003 %} | |
8004 | |
8005 // Register Or Long | |
8006 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8007 match(Set dst (OrL src1 src2)); | |
8008 | |
8009 ins_cost(DEFAULT_COST); | |
8010 size(4); | |
8011 format %{ "OR $src1,$src2,$dst\t! long" %} | |
8012 opcode(Assembler::or_op3, Assembler::arith_op); | |
8013 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8014 ins_pipe(ialu_reg_reg); | |
8015 %} | |
8016 | |
8017 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8018 match(Set dst (OrL src1 con)); | |
8019 ins_cost(DEFAULT_COST*2); | |
8020 | |
8021 ins_cost(DEFAULT_COST); | |
8022 size(4); | |
8023 format %{ "OR $src1,$con,$dst\t! long" %} | |
8024 opcode(Assembler::or_op3, Assembler::arith_op); | |
8025 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8026 ins_pipe(ialu_reg_imm); | |
8027 %} | |
8028 | |
420
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8029 #ifndef _LP64 |
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8030 |
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8031 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8032 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8033 match(Set dst (OrI src1 (CastP2X src2))); |
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8034 |
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8035 size(4); |
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8036 format %{ "OR $src1,$src2,$dst" %} |
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8037 opcode(Assembler::or_op3, Assembler::arith_op); |
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8038 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8039 ins_pipe(ialu_reg_reg); |
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8040 %} |
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8041 |
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8042 #else |
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8043 |
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8044 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8045 match(Set dst (OrL src1 (CastP2X src2))); |
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8046 |
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8047 ins_cost(DEFAULT_COST); |
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8048 size(4); |
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8049 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8050 opcode(Assembler::or_op3, Assembler::arith_op); |
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8051 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8052 ins_pipe(ialu_reg_reg); |
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8053 %} |
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8054 |
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8055 #endif |
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8056 |
0 | 8057 // Xor Instructions |
8058 // Register Xor | |
8059 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8060 match(Set dst (XorI src1 src2)); | |
8061 | |
8062 size(4); | |
8063 format %{ "XOR $src1,$src2,$dst" %} | |
8064 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8065 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8066 ins_pipe(ialu_reg_reg); | |
8067 %} | |
8068 | |
8069 // Immediate Xor | |
8070 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8071 match(Set dst (XorI src1 src2)); | |
8072 | |
8073 size(4); | |
8074 format %{ "XOR $src1,$src2,$dst" %} | |
8075 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8076 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8077 ins_pipe(ialu_reg_imm); | |
8078 %} | |
8079 | |
8080 // Register Xor Long | |
8081 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8082 match(Set dst (XorL src1 src2)); | |
8083 | |
8084 ins_cost(DEFAULT_COST); | |
8085 size(4); | |
8086 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
8087 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8088 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8089 ins_pipe(ialu_reg_reg); | |
8090 %} | |
8091 | |
8092 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8093 match(Set dst (XorL src1 con)); | |
8094 | |
8095 ins_cost(DEFAULT_COST); | |
8096 size(4); | |
8097 format %{ "XOR $src1,$con,$dst\t! long" %} | |
8098 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8099 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8100 ins_pipe(ialu_reg_imm); | |
8101 %} | |
8102 | |
8103 //----------Convert to Boolean------------------------------------------------- | |
8104 // Nice hack for 32-bit tests but doesn't work for | |
8105 // 64-bit pointers. | |
8106 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
8107 match(Set dst (Conv2B src)); | |
8108 effect( KILL ccr ); | |
8109 ins_cost(DEFAULT_COST*2); | |
8110 format %{ "CMP R_G0,$src\n\t" | |
8111 "ADDX R_G0,0,$dst" %} | |
8112 ins_encode( enc_to_bool( src, dst ) ); | |
8113 ins_pipe(ialu_reg_ialu); | |
8114 %} | |
8115 | |
8116 #ifndef _LP64 | |
8117 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
8118 match(Set dst (Conv2B src)); | |
8119 effect( KILL ccr ); | |
8120 ins_cost(DEFAULT_COST*2); | |
8121 format %{ "CMP R_G0,$src\n\t" | |
8122 "ADDX R_G0,0,$dst" %} | |
8123 ins_encode( enc_to_bool( src, dst ) ); | |
8124 ins_pipe(ialu_reg_ialu); | |
8125 %} | |
8126 #else | |
8127 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8128 match(Set dst (Conv2B src)); | |
8129 ins_cost(DEFAULT_COST*2); | |
8130 format %{ "MOV $src,$dst\n\t" | |
8131 "MOVRNZ $src,1,$dst" %} | |
8132 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8133 ins_pipe(ialu_clr_and_mover); | |
8134 %} | |
8135 #endif | |
8136 | |
8137 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
8138 match(Set dst (CmpLTMask p q)); | |
8139 effect( KILL ccr ); | |
8140 ins_cost(DEFAULT_COST*4); | |
8141 format %{ "CMP $p,$q\n\t" | |
8142 "MOV #0,$dst\n\t" | |
8143 "BLT,a .+8\n\t" | |
8144 "MOV #-1,$dst" %} | |
8145 ins_encode( enc_ltmask(p,q,dst) ); | |
8146 ins_pipe(ialu_reg_reg_ialu); | |
8147 %} | |
8148 | |
8149 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8150 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8151 effect(KILL ccr, TEMP tmp); | |
8152 ins_cost(DEFAULT_COST*3); | |
8153 | |
8154 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8155 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
8156 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
8157 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
8158 ins_pipe( cadd_cmpltmask ); | |
8159 %} | |
8160 | |
8161 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8162 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
8163 effect( KILL ccr, TEMP tmp); | |
8164 ins_cost(DEFAULT_COST*3); | |
8165 | |
8166 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8167 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
8168 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
8169 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
8170 ins_pipe( cadd_cmpltmask ); | |
8171 %} | |
8172 | |
8173 //----------Arithmetic Conversion Instructions--------------------------------- | |
8174 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8175 | |
8176 instruct convD2F_reg(regF dst, regD src) %{ | |
8177 match(Set dst (ConvD2F src)); | |
8178 size(4); | |
8179 format %{ "FDTOS $src,$dst" %} | |
8180 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8181 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8182 ins_pipe(fcvtD2F); | |
8183 %} | |
8184 | |
8185 | |
8186 // Convert a double to an int in a float register. | |
8187 // If the double is a NAN, stuff a zero in instead. | |
8188 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8189 effect(DEF dst, USE src, KILL fcc0); | |
8190 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8191 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8192 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8193 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8194 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8195 "skip:" %} | |
8196 ins_encode(form_d2i_helper(src,dst)); | |
8197 ins_pipe(fcvtD2I); | |
8198 %} | |
8199 | |
8200 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
8201 match(Set dst (ConvD2I src)); | |
8202 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8203 expand %{ | |
8204 regF tmp; | |
8205 convD2I_helper(tmp, src); | |
8206 regF_to_stkI(dst, tmp); | |
8207 %} | |
8208 %} | |
8209 | |
8210 // Convert a double to a long in a double register. | |
8211 // If the double is a NAN, stuff a zero in instead. | |
8212 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8213 effect(DEF dst, USE src, KILL fcc0); | |
8214 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8215 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8216 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8217 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8218 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8219 "skip:" %} | |
8220 ins_encode(form_d2l_helper(src,dst)); | |
8221 ins_pipe(fcvtD2L); | |
8222 %} | |
8223 | |
8224 | |
8225 // Double to Long conversion | |
8226 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
8227 match(Set dst (ConvD2L src)); | |
8228 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8229 expand %{ | |
8230 regD tmp; | |
8231 convD2L_helper(tmp, src); | |
8232 regD_to_stkL(dst, tmp); | |
8233 %} | |
8234 %} | |
8235 | |
8236 | |
8237 instruct convF2D_reg(regD dst, regF src) %{ | |
8238 match(Set dst (ConvF2D src)); | |
8239 format %{ "FSTOD $src,$dst" %} | |
8240 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8241 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8242 ins_pipe(fcvtF2D); | |
8243 %} | |
8244 | |
8245 | |
8246 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8247 effect(DEF dst, USE src, KILL fcc0); | |
8248 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8249 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8250 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8251 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8252 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8253 "skip:" %} | |
8254 ins_encode(form_f2i_helper(src,dst)); | |
8255 ins_pipe(fcvtF2I); | |
8256 %} | |
8257 | |
8258 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
8259 match(Set dst (ConvF2I src)); | |
8260 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8261 expand %{ | |
8262 regF tmp; | |
8263 convF2I_helper(tmp, src); | |
8264 regF_to_stkI(dst, tmp); | |
8265 %} | |
8266 %} | |
8267 | |
8268 | |
8269 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8270 effect(DEF dst, USE src, KILL fcc0); | |
8271 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8272 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8273 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8274 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8275 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8276 "skip:" %} | |
8277 ins_encode(form_f2l_helper(src,dst)); | |
8278 ins_pipe(fcvtF2L); | |
8279 %} | |
8280 | |
8281 // Float to Long conversion | |
8282 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
8283 match(Set dst (ConvF2L src)); | |
8284 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8285 expand %{ | |
8286 regD tmp; | |
8287 convF2L_helper(tmp, src); | |
8288 regD_to_stkL(dst, tmp); | |
8289 %} | |
8290 %} | |
8291 | |
8292 | |
8293 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8294 effect(USE tmp, DEF dst); | |
8295 format %{ "FITOD $tmp,$dst" %} | |
8296 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8297 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8298 ins_pipe(fcvtI2D); | |
8299 %} | |
8300 | |
8301 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
8302 match(Set dst (ConvI2D src)); | |
8303 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8304 expand %{ | |
8305 regF tmp; | |
8306 stkI_to_regF( tmp, src); | |
8307 convI2D_helper( dst, tmp); | |
8308 %} | |
8309 %} | |
8310 | |
8311 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
8312 match(Set dst (ConvI2D (LoadI mem))); | |
8313 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8314 size(8); | |
8315 format %{ "LDF $mem,$dst\n\t" | |
8316 "FITOD $dst,$dst" %} | |
8317 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
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8318 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8319 ins_pipe(floadF_mem); |
8320 %} | |
8321 | |
8322 | |
8323 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8324 effect(DEF dst, USE tmp); | |
8325 format %{ "FITOS $tmp,$dst" %} | |
8326 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8327 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8328 ins_pipe(fcvtI2F); | |
8329 %} | |
8330 | |
8331 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
8332 match(Set dst (ConvI2F src)); | |
8333 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8334 expand %{ | |
8335 regF tmp; | |
8336 stkI_to_regF(tmp,src); | |
8337 convI2F_helper(dst, tmp); | |
8338 %} | |
8339 %} | |
8340 | |
8341 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8342 match(Set dst (ConvI2F (LoadI mem))); | |
8343 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8344 size(8); | |
8345 format %{ "LDF $mem,$dst\n\t" | |
8346 "FITOS $dst,$dst" %} | |
8347 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
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8348 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8349 ins_pipe(floadF_mem); |
8350 %} | |
8351 | |
8352 | |
8353 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8354 match(Set dst (ConvI2L src)); | |
8355 size(4); | |
8356 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8357 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8358 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8359 ins_pipe(ialu_reg_reg); | |
8360 %} | |
8361 | |
8362 // Zero-extend convert int to long | |
8363 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8364 match(Set dst (AndL (ConvI2L src) mask) ); | |
8365 size(4); | |
8366 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8367 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8368 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8369 ins_pipe(ialu_reg_reg); | |
8370 %} | |
8371 | |
8372 // Zero-extend long | |
8373 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8374 match(Set dst (AndL src mask) ); | |
8375 size(4); | |
8376 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8377 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8378 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8379 ins_pipe(ialu_reg_reg); | |
8380 %} | |
8381 | |
8382 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
8383 match(Set dst (MoveF2I src)); | |
8384 effect(DEF dst, USE src); | |
8385 ins_cost(MEMORY_REF_COST); | |
8386 | |
8387 size(4); | |
8388 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8389 opcode(Assembler::lduw_op3); | |
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8390 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8391 ins_pipe(iload_mem); |
8392 %} | |
8393 | |
8394 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8395 match(Set dst (MoveI2F src)); | |
8396 effect(DEF dst, USE src); | |
8397 ins_cost(MEMORY_REF_COST); | |
8398 | |
8399 size(4); | |
8400 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8401 opcode(Assembler::ldf_op3); | |
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8402 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8403 ins_pipe(floadF_stk); |
8404 %} | |
8405 | |
8406 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8407 match(Set dst (MoveD2L src)); | |
8408 effect(DEF dst, USE src); | |
8409 ins_cost(MEMORY_REF_COST); | |
8410 | |
8411 size(4); | |
8412 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8413 opcode(Assembler::ldx_op3); | |
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8414 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8415 ins_pipe(iload_mem); |
8416 %} | |
8417 | |
8418 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8419 match(Set dst (MoveL2D src)); | |
8420 effect(DEF dst, USE src); | |
8421 ins_cost(MEMORY_REF_COST); | |
8422 | |
8423 size(4); | |
8424 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8425 opcode(Assembler::lddf_op3); | |
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8426 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8427 ins_pipe(floadD_stk); |
8428 %} | |
8429 | |
8430 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8431 match(Set dst (MoveF2I src)); | |
8432 effect(DEF dst, USE src); | |
8433 ins_cost(MEMORY_REF_COST); | |
8434 | |
8435 size(4); | |
8436 format %{ "STF $src,$dst\t!MoveF2I" %} | |
8437 opcode(Assembler::stf_op3); | |
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8438 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8439 ins_pipe(fstoreF_stk_reg); |
8440 %} | |
8441 | |
8442 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8443 match(Set dst (MoveI2F src)); | |
8444 effect(DEF dst, USE src); | |
8445 ins_cost(MEMORY_REF_COST); | |
8446 | |
8447 size(4); | |
8448 format %{ "STW $src,$dst\t!MoveI2F" %} | |
8449 opcode(Assembler::stw_op3); | |
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8450 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8451 ins_pipe(istore_mem_reg); |
8452 %} | |
8453 | |
8454 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8455 match(Set dst (MoveD2L src)); | |
8456 effect(DEF dst, USE src); | |
8457 ins_cost(MEMORY_REF_COST); | |
8458 | |
8459 size(4); | |
8460 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
8461 opcode(Assembler::stdf_op3); | |
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8462 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8463 ins_pipe(fstoreD_stk_reg); |
8464 %} | |
8465 | |
8466 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8467 match(Set dst (MoveL2D src)); | |
8468 effect(DEF dst, USE src); | |
8469 ins_cost(MEMORY_REF_COST); | |
8470 | |
8471 size(4); | |
8472 format %{ "STX $src,$dst\t!MoveL2D" %} | |
8473 opcode(Assembler::stx_op3); | |
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8474 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8475 ins_pipe(istore_mem_reg); |
8476 %} | |
8477 | |
8478 | |
8479 //----------- | |
8480 // Long to Double conversion using V8 opcodes. | |
8481 // Still useful because cheetah traps and becomes | |
8482 // amazingly slow for some common numbers. | |
8483 | |
8484 // Magic constant, 0x43300000 | |
8485 instruct loadConI_x43300000(iRegI dst) %{ | |
8486 effect(DEF dst); | |
8487 size(4); | |
8488 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8489 ins_encode(SetHi22(0x43300000, dst)); | |
8490 ins_pipe(ialu_none); | |
8491 %} | |
8492 | |
8493 // Magic constant, 0x41f00000 | |
8494 instruct loadConI_x41f00000(iRegI dst) %{ | |
8495 effect(DEF dst); | |
8496 size(4); | |
8497 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8498 ins_encode(SetHi22(0x41f00000, dst)); | |
8499 ins_pipe(ialu_none); | |
8500 %} | |
8501 | |
8502 // Construct a double from two float halves | |
8503 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8504 effect(DEF dst, USE src1, USE src2); | |
8505 size(8); | |
8506 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8507 "FMOVS $src2.lo,$dst.lo" %} | |
8508 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8509 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8510 ins_pipe(faddD_reg_reg); | |
8511 %} | |
8512 | |
8513 // Convert integer in high half of a double register (in the lower half of | |
8514 // the double register file) to double | |
8515 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8516 effect(DEF dst, USE src); | |
8517 size(4); | |
8518 format %{ "FITOD $src,$dst" %} | |
8519 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8520 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8521 ins_pipe(fcvtLHi2D); | |
8522 %} | |
8523 | |
8524 // Add float double precision | |
8525 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8526 effect(DEF dst, USE src1, USE src2); | |
8527 size(4); | |
8528 format %{ "FADDD $src1,$src2,$dst" %} | |
8529 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8530 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8531 ins_pipe(faddD_reg_reg); | |
8532 %} | |
8533 | |
8534 // Sub float double precision | |
8535 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8536 effect(DEF dst, USE src1, USE src2); | |
8537 size(4); | |
8538 format %{ "FSUBD $src1,$src2,$dst" %} | |
8539 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8540 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8541 ins_pipe(faddD_reg_reg); | |
8542 %} | |
8543 | |
8544 // Mul float double precision | |
8545 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8546 effect(DEF dst, USE src1, USE src2); | |
8547 size(4); | |
8548 format %{ "FMULD $src1,$src2,$dst" %} | |
8549 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8550 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8551 ins_pipe(fmulD_reg_reg); | |
8552 %} | |
8553 | |
8554 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8555 match(Set dst (ConvL2D src)); | |
8556 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8557 | |
8558 expand %{ | |
8559 regD_low tmpsrc; | |
8560 iRegI ix43300000; | |
8561 iRegI ix41f00000; | |
8562 stackSlotL lx43300000; | |
8563 stackSlotL lx41f00000; | |
8564 regD_low dx43300000; | |
8565 regD dx41f00000; | |
8566 regD tmp1; | |
8567 regD_low tmp2; | |
8568 regD tmp3; | |
8569 regD tmp4; | |
8570 | |
8571 stkL_to_regD(tmpsrc, src); | |
8572 | |
8573 loadConI_x43300000(ix43300000); | |
8574 loadConI_x41f00000(ix41f00000); | |
8575 regI_to_stkLHi(lx43300000, ix43300000); | |
8576 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8577 stkL_to_regD(dx43300000, lx43300000); | |
8578 stkL_to_regD(dx41f00000, lx41f00000); | |
8579 | |
8580 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8581 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8582 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8583 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8584 addD_regD_regD(dst, tmp3, tmp4); | |
8585 %} | |
8586 %} | |
8587 | |
8588 // Long to Double conversion using fast fxtof | |
8589 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8590 effect(DEF dst, USE tmp); | |
8591 size(4); | |
8592 format %{ "FXTOD $tmp,$dst" %} | |
8593 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8594 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8595 ins_pipe(fcvtL2D); | |
8596 %} | |
8597 | |
8598 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
8599 predicate(VM_Version::has_fast_fxtof()); | |
8600 match(Set dst (ConvL2D src)); | |
8601 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8602 expand %{ | |
8603 regD tmp; | |
8604 stkL_to_regD(tmp, src); | |
8605 convL2D_helper(dst, tmp); | |
8606 %} | |
8607 %} | |
8608 | |
8609 //----------- | |
8610 // Long to Float conversion using V8 opcodes. | |
8611 // Still useful because cheetah traps and becomes | |
8612 // amazingly slow for some common numbers. | |
8613 | |
8614 // Long to Float conversion using fast fxtof | |
8615 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8616 effect(DEF dst, USE tmp); | |
8617 size(4); | |
8618 format %{ "FXTOS $tmp,$dst" %} | |
8619 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8620 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8621 ins_pipe(fcvtL2F); | |
8622 %} | |
8623 | |
8624 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
8625 match(Set dst (ConvL2F src)); | |
8626 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8627 expand %{ | |
8628 regD tmp; | |
8629 stkL_to_regD(tmp, src); | |
8630 convL2F_helper(dst, tmp); | |
8631 %} | |
8632 %} | |
8633 //----------- | |
8634 | |
8635 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8636 match(Set dst (ConvL2I src)); | |
8637 #ifndef _LP64 | |
8638 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8639 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8640 ins_pipe(ialu_move_reg_I_to_L); | |
8641 #else | |
8642 size(4); | |
8643 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8644 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8645 ins_pipe(ialu_reg); | |
8646 #endif | |
8647 %} | |
8648 | |
8649 // Register Shift Right Immediate | |
8650 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8651 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8652 | |
8653 size(4); | |
8654 format %{ "SRAX $src,$cnt,$dst" %} | |
8655 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8656 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8657 ins_pipe(ialu_reg_imm); | |
8658 %} | |
8659 | |
8660 // Replicate scalar to packed byte values in Double register | |
8661 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
8662 effect(DEF dst, USE src); | |
8663 format %{ "SLLX $src,56,$dst\n\t" | |
8664 "SRLX $dst, 8,O7\n\t" | |
8665 "OR $dst,O7,$dst\n\t" | |
8666 "SRLX $dst,16,O7\n\t" | |
8667 "OR $dst,O7,$dst\n\t" | |
8668 "SRLX $dst,32,O7\n\t" | |
8669 "OR $dst,O7,$dst\t! replicate8B" %} | |
8670 ins_encode( enc_repl8b(src, dst)); | |
8671 ins_pipe(ialu_reg); | |
8672 %} | |
8673 | |
8674 // Replicate scalar to packed byte values in Double register | |
8675 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
8676 match(Set dst (Replicate8B src)); | |
8677 expand %{ | |
8678 iRegL tmp; | |
8679 Repl8B_reg_helper(tmp, src); | |
8680 regL_to_stkD(dst, tmp); | |
8681 %} | |
8682 %} | |
8683 | |
8684 // Replicate scalar constant to packed byte values in Double register | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8685 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
2008 | 8686 match(Set dst (Replicate8B con)); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8687 effect(KILL tmp); |
2008 | 8688 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
8689 ins_encode %{ | |
8690 // XXX This is a quick fix for 6833573. | |
8691 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8692 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8693 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
2008 | 8694 %} |
0 | 8695 ins_pipe(loadConFD); |
8696 %} | |
8697 | |
8698 // Replicate scalar to packed char values into stack slot | |
8699 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
8700 effect(DEF dst, USE src); | |
8701 format %{ "SLLX $src,48,$dst\n\t" | |
8702 "SRLX $dst,16,O7\n\t" | |
8703 "OR $dst,O7,$dst\n\t" | |
8704 "SRLX $dst,32,O7\n\t" | |
8705 "OR $dst,O7,$dst\t! replicate4C" %} | |
8706 ins_encode( enc_repl4s(src, dst) ); | |
8707 ins_pipe(ialu_reg); | |
8708 %} | |
8709 | |
8710 // Replicate scalar to packed char values into stack slot | |
8711 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
8712 match(Set dst (Replicate4C src)); | |
8713 expand %{ | |
8714 iRegL tmp; | |
8715 Repl4C_reg_helper(tmp, src); | |
8716 regL_to_stkD(dst, tmp); | |
8717 %} | |
8718 %} | |
8719 | |
8720 // Replicate scalar constant to packed char values in Double register | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8721 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{ |
2008 | 8722 match(Set dst (Replicate4C con)); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8723 effect(KILL tmp); |
2008 | 8724 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} |
8725 ins_encode %{ | |
8726 // XXX This is a quick fix for 6833573. | |
8727 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8728 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8729 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
2008 | 8730 %} |
0 | 8731 ins_pipe(loadConFD); |
8732 %} | |
8733 | |
8734 // Replicate scalar to packed short values into stack slot | |
8735 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
8736 effect(DEF dst, USE src); | |
8737 format %{ "SLLX $src,48,$dst\n\t" | |
8738 "SRLX $dst,16,O7\n\t" | |
8739 "OR $dst,O7,$dst\n\t" | |
8740 "SRLX $dst,32,O7\n\t" | |
8741 "OR $dst,O7,$dst\t! replicate4S" %} | |
8742 ins_encode( enc_repl4s(src, dst) ); | |
8743 ins_pipe(ialu_reg); | |
8744 %} | |
8745 | |
8746 // Replicate scalar to packed short values into stack slot | |
8747 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
8748 match(Set dst (Replicate4S src)); | |
8749 expand %{ | |
8750 iRegL tmp; | |
8751 Repl4S_reg_helper(tmp, src); | |
8752 regL_to_stkD(dst, tmp); | |
8753 %} | |
8754 %} | |
8755 | |
8756 // Replicate scalar constant to packed short values in Double register | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8757 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
2008 | 8758 match(Set dst (Replicate4S con)); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8759 effect(KILL tmp); |
2008 | 8760 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
8761 ins_encode %{ | |
8762 // XXX This is a quick fix for 6833573. | |
8763 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8764 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8765 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
2008 | 8766 %} |
0 | 8767 ins_pipe(loadConFD); |
8768 %} | |
8769 | |
8770 // Replicate scalar to packed int values in Double register | |
8771 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
8772 effect(DEF dst, USE src); | |
8773 format %{ "SLLX $src,32,$dst\n\t" | |
8774 "SRLX $dst,32,O7\n\t" | |
8775 "OR $dst,O7,$dst\t! replicate2I" %} | |
8776 ins_encode( enc_repl2i(src, dst)); | |
8777 ins_pipe(ialu_reg); | |
8778 %} | |
8779 | |
8780 // Replicate scalar to packed int values in Double register | |
8781 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
8782 match(Set dst (Replicate2I src)); | |
8783 expand %{ | |
8784 iRegL tmp; | |
8785 Repl2I_reg_helper(tmp, src); | |
8786 regL_to_stkD(dst, tmp); | |
8787 %} | |
8788 %} | |
8789 | |
8790 // Replicate scalar zero constant to packed int values in Double register | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8791 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
2008 | 8792 match(Set dst (Replicate2I con)); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8793 effect(KILL tmp); |
2008 | 8794 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
8795 ins_encode %{ | |
8796 // XXX This is a quick fix for 6833573. | |
8797 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8798 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8799 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
2008 | 8800 %} |
0 | 8801 ins_pipe(loadConFD); |
8802 %} | |
8803 | |
8804 //----------Control Flow Instructions------------------------------------------ | |
8805 // Compare Instructions | |
8806 // Compare Integers | |
8807 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8808 match(Set icc (CmpI op1 op2)); | |
8809 effect( DEF icc, USE op1, USE op2 ); | |
8810 | |
8811 size(4); | |
8812 format %{ "CMP $op1,$op2" %} | |
8813 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8814 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8815 ins_pipe(ialu_cconly_reg_reg); | |
8816 %} | |
8817 | |
8818 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8819 match(Set icc (CmpU op1 op2)); | |
8820 | |
8821 size(4); | |
8822 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8823 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8824 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8825 ins_pipe(ialu_cconly_reg_reg); | |
8826 %} | |
8827 | |
8828 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8829 match(Set icc (CmpI op1 op2)); | |
8830 effect( DEF icc, USE op1 ); | |
8831 | |
8832 size(4); | |
8833 format %{ "CMP $op1,$op2" %} | |
8834 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8835 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8836 ins_pipe(ialu_cconly_reg_imm); | |
8837 %} | |
8838 | |
8839 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8840 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8841 | |
8842 size(4); | |
8843 format %{ "BTST $op2,$op1" %} | |
8844 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8845 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8846 ins_pipe(ialu_cconly_reg_reg_zero); | |
8847 %} | |
8848 | |
8849 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8850 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8851 | |
8852 size(4); | |
8853 format %{ "BTST $op2,$op1" %} | |
8854 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8855 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8856 ins_pipe(ialu_cconly_reg_imm_zero); | |
8857 %} | |
8858 | |
8859 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8860 match(Set xcc (CmpL op1 op2)); | |
8861 effect( DEF xcc, USE op1, USE op2 ); | |
8862 | |
8863 size(4); | |
8864 format %{ "CMP $op1,$op2\t\t! long" %} | |
8865 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8866 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8867 ins_pipe(ialu_cconly_reg_reg); | |
8868 %} | |
8869 | |
8870 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8871 match(Set xcc (CmpL op1 con)); | |
8872 effect( DEF xcc, USE op1, USE con ); | |
8873 | |
8874 size(4); | |
8875 format %{ "CMP $op1,$con\t\t! long" %} | |
8876 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8877 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8878 ins_pipe(ialu_cconly_reg_reg); | |
8879 %} | |
8880 | |
8881 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8882 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8883 effect( DEF xcc, USE op1, USE op2 ); | |
8884 | |
8885 size(4); | |
8886 format %{ "BTST $op1,$op2\t\t! long" %} | |
8887 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8888 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8889 ins_pipe(ialu_cconly_reg_reg); | |
8890 %} | |
8891 | |
8892 // useful for checking the alignment of a pointer: | |
8893 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8894 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8895 effect( DEF xcc, USE op1, USE con ); | |
8896 | |
8897 size(4); | |
8898 format %{ "BTST $op1,$con\t\t! long" %} | |
8899 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8900 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8901 ins_pipe(ialu_cconly_reg_reg); | |
8902 %} | |
8903 | |
8904 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8905 match(Set icc (CmpU op1 op2)); | |
8906 | |
8907 size(4); | |
8908 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8909 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8910 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8911 ins_pipe(ialu_cconly_reg_imm); | |
8912 %} | |
8913 | |
8914 // Compare Pointers | |
8915 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8916 match(Set pcc (CmpP op1 op2)); | |
8917 | |
8918 size(4); | |
8919 format %{ "CMP $op1,$op2\t! ptr" %} | |
8920 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8921 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8922 ins_pipe(ialu_cconly_reg_reg); | |
8923 %} | |
8924 | |
8925 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8926 match(Set pcc (CmpP op1 op2)); | |
8927 | |
8928 size(4); | |
8929 format %{ "CMP $op1,$op2\t! ptr" %} | |
8930 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8931 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8932 ins_pipe(ialu_cconly_reg_imm); | |
8933 %} | |
8934 | |
164
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163
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8935 // Compare Narrow oops |
c436414a719e
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8936 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
c436414a719e
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8937 match(Set icc (CmpN op1 op2)); |
c436414a719e
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kvn
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163
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|
8938 |
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163
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|
8939 size(4); |
c436414a719e
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|
8940 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
c436414a719e
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|
8941 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8942 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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|
8943 ins_pipe(ialu_cconly_reg_reg); |
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|
8944 %} |
c436414a719e
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163
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|
8945 |
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163
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|
8946 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
c436414a719e
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|
8947 match(Set icc (CmpN op1 op2)); |
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163
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|
8948 |
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163
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|
8949 size(4); |
c436414a719e
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|
8950 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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|
8951 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8952 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8953 ins_pipe(ialu_cconly_reg_imm); |
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8954 %} |
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|
8955 |
0 | 8956 //----------Max and Min-------------------------------------------------------- |
8957 // Min Instructions | |
8958 // Conditional move for min | |
8959 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8960 effect( USE_DEF op2, USE op1, USE icc ); | |
8961 | |
8962 size(4); | |
8963 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
8964 opcode(Assembler::less); | |
8965 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8966 ins_pipe(ialu_reg_flags); | |
8967 %} | |
8968 | |
8969 // Min Register with Register. | |
8970 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
8971 match(Set op2 (MinI op1 op2)); | |
8972 ins_cost(DEFAULT_COST*2); | |
8973 expand %{ | |
8974 flagsReg icc; | |
8975 compI_iReg(icc,op1,op2); | |
8976 cmovI_reg_lt(op2,op1,icc); | |
8977 %} | |
8978 %} | |
8979 | |
8980 // Max Instructions | |
8981 // Conditional move for max | |
8982 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8983 effect( USE_DEF op2, USE op1, USE icc ); | |
8984 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
8985 opcode(Assembler::greater); | |
8986 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8987 ins_pipe(ialu_reg_flags); | |
8988 %} | |
8989 | |
8990 // Max Register with Register | |
8991 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
8992 match(Set op2 (MaxI op1 op2)); | |
8993 ins_cost(DEFAULT_COST*2); | |
8994 expand %{ | |
8995 flagsReg icc; | |
8996 compI_iReg(icc,op1,op2); | |
8997 cmovI_reg_gt(op2,op1,icc); | |
8998 %} | |
8999 %} | |
9000 | |
9001 | |
9002 //----------Float Compares---------------------------------------------------- | |
9003 // Compare floating, generate condition code | |
9004 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
9005 match(Set fcc (CmpF src1 src2)); | |
9006 | |
9007 size(4); | |
9008 format %{ "FCMPs $fcc,$src1,$src2" %} | |
9009 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
9010 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
9011 ins_pipe(faddF_fcc_reg_reg_zero); | |
9012 %} | |
9013 | |
9014 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
9015 match(Set fcc (CmpD src1 src2)); | |
9016 | |
9017 size(4); | |
9018 format %{ "FCMPd $fcc,$src1,$src2" %} | |
9019 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
9020 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
9021 ins_pipe(faddD_fcc_reg_reg_zero); | |
9022 %} | |
9023 | |
9024 | |
9025 // Compare floating, generate -1,0,1 | |
9026 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
9027 match(Set dst (CmpF3 src1 src2)); | |
9028 effect(KILL fcc0); | |
9029 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9030 format %{ "fcmpl $dst,$src1,$src2" %} | |
9031 // Primary = float | |
9032 opcode( true ); | |
9033 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9034 ins_pipe( floating_cmp ); | |
9035 %} | |
9036 | |
9037 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
9038 match(Set dst (CmpD3 src1 src2)); | |
9039 effect(KILL fcc0); | |
9040 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9041 format %{ "dcmpl $dst,$src1,$src2" %} | |
9042 // Primary = double (not float) | |
9043 opcode( false ); | |
9044 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9045 ins_pipe( floating_cmp ); | |
9046 %} | |
9047 | |
9048 //----------Branches--------------------------------------------------------- | |
9049 // Jump | |
9050 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
9051 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
9052 match(Jump switch_val); | |
9053 | |
9054 ins_cost(350); | |
9055 | |
2008 | 9056 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9057 "LD [O7 + $switch_val], O7\n\t" | |
0 | 9058 "JUMP O7" |
9059 %} | |
2008 | 9060 ins_encode %{ |
9061 // Calculate table address into a register. | |
9062 Register table_reg; | |
9063 Register label_reg = O7; | |
9064 if (constant_offset() == 0) { | |
9065 table_reg = $constanttablebase; | |
9066 } else { | |
9067 table_reg = O7; | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
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9068 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
9069 __ add($constanttablebase, con_offset, table_reg); |
2008 | 9070 } |
9071 | |
9072 // Jump to base address + switch value | |
9073 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
9074 __ jmp(label_reg, G0); | |
9075 __ delayed()->nop(); | |
9076 %} | |
0 | 9077 ins_pc_relative(1); |
9078 ins_pipe(ialu_reg_reg); | |
9079 %} | |
9080 | |
9081 // Direct Branch. Use V8 version with longer range. | |
9082 instruct branch(label labl) %{ | |
9083 match(Goto); | |
9084 effect(USE labl); | |
9085 | |
9086 size(8); | |
9087 ins_cost(BRANCH_COST); | |
9088 format %{ "BA $labl" %} | |
9089 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
9090 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
9091 ins_encode( enc_ba( labl ) ); | |
9092 ins_pc_relative(1); | |
9093 ins_pipe(br); | |
9094 %} | |
9095 | |
9096 // Conditional Direct Branch | |
9097 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
9098 match(If cmp icc); | |
9099 effect(USE labl); | |
9100 | |
9101 size(8); | |
9102 ins_cost(BRANCH_COST); | |
9103 format %{ "BP$cmp $icc,$labl" %} | |
9104 // Prim = bits 24-22, Secnd = bits 31-30 | |
9105 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9106 ins_pc_relative(1); | |
9107 ins_pipe(br_cc); | |
9108 %} | |
9109 | |
9110 // Branch-on-register tests all 64 bits. We assume that values | |
9111 // in 64-bit registers always remains zero or sign extended | |
9112 // unless our code munges the high bits. Interrupts can chop | |
9113 // the high order bits to zero or sign at any time. | |
9114 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
9115 match(If cmp (CmpI op1 zero)); | |
9116 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9117 effect(USE labl); | |
9118 | |
9119 size(8); | |
9120 ins_cost(BRANCH_COST); | |
9121 format %{ "BR$cmp $op1,$labl" %} | |
9122 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9123 ins_pc_relative(1); | |
9124 ins_pipe(br_reg); | |
9125 %} | |
9126 | |
9127 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
9128 match(If cmp (CmpP op1 null)); | |
9129 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9130 effect(USE labl); | |
9131 | |
9132 size(8); | |
9133 ins_cost(BRANCH_COST); | |
9134 format %{ "BR$cmp $op1,$labl" %} | |
9135 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9136 ins_pc_relative(1); | |
9137 ins_pipe(br_reg); | |
9138 %} | |
9139 | |
9140 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9141 match(If cmp (CmpL op1 zero)); | |
9142 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9143 effect(USE labl); | |
9144 | |
9145 size(8); | |
9146 ins_cost(BRANCH_COST); | |
9147 format %{ "BR$cmp $op1,$labl" %} | |
9148 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9149 ins_pc_relative(1); | |
9150 ins_pipe(br_reg); | |
9151 %} | |
9152 | |
9153 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9154 match(If cmp icc); | |
9155 effect(USE labl); | |
9156 | |
9157 format %{ "BP$cmp $icc,$labl" %} | |
9158 // Prim = bits 24-22, Secnd = bits 31-30 | |
9159 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9160 ins_pc_relative(1); | |
9161 ins_pipe(br_cc); | |
9162 %} | |
9163 | |
9164 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9165 match(If cmp pcc); | |
9166 effect(USE labl); | |
9167 | |
9168 size(8); | |
9169 ins_cost(BRANCH_COST); | |
9170 format %{ "BP$cmp $pcc,$labl" %} | |
9171 // Prim = bits 24-22, Secnd = bits 31-30 | |
9172 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
9173 ins_pc_relative(1); | |
9174 ins_pipe(br_cc); | |
9175 %} | |
9176 | |
9177 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9178 match(If cmp fcc); | |
9179 effect(USE labl); | |
9180 | |
9181 size(8); | |
9182 ins_cost(BRANCH_COST); | |
9183 format %{ "FBP$cmp $fcc,$labl" %} | |
9184 // Prim = bits 24-22, Secnd = bits 31-30 | |
9185 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
9186 ins_pc_relative(1); | |
9187 ins_pipe(br_fcc); | |
9188 %} | |
9189 | |
9190 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9191 match(CountedLoopEnd cmp icc); | |
9192 effect(USE labl); | |
9193 | |
9194 size(8); | |
9195 ins_cost(BRANCH_COST); | |
9196 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9197 // Prim = bits 24-22, Secnd = bits 31-30 | |
9198 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9199 ins_pc_relative(1); | |
9200 ins_pipe(br_cc); | |
9201 %} | |
9202 | |
9203 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9204 match(CountedLoopEnd cmp icc); | |
9205 effect(USE labl); | |
9206 | |
9207 size(8); | |
9208 ins_cost(BRANCH_COST); | |
9209 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9210 // Prim = bits 24-22, Secnd = bits 31-30 | |
9211 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9212 ins_pc_relative(1); | |
9213 ins_pipe(br_cc); | |
9214 %} | |
9215 | |
9216 // ============================================================================ | |
9217 // Long Compare | |
9218 // | |
9219 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9220 // is tricky. The flavor of compare used depends on whether we are testing | |
9221 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9222 // The GE test is the negated LT test. The LE test can be had by commuting | |
9223 // the operands (yielding a GE test) and then negating; negate again for the | |
9224 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9225 // NE test is negated from that. | |
9226 | |
9227 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9228 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9229 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9230 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9231 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9232 // foo match ends up with the wrong leaf. One fix is to not match both | |
9233 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9234 // both forms beat the trinary form of long-compare and both are very useful | |
9235 // on Intel which has so few registers. | |
9236 | |
9237 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9238 match(If cmp xcc); | |
9239 effect(USE labl); | |
9240 | |
9241 size(8); | |
9242 ins_cost(BRANCH_COST); | |
9243 format %{ "BP$cmp $xcc,$labl" %} | |
9244 // Prim = bits 24-22, Secnd = bits 31-30 | |
9245 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
9246 ins_pc_relative(1); | |
9247 ins_pipe(br_cc); | |
9248 %} | |
9249 | |
9250 // Manifest a CmpL3 result in an integer register. Very painful. | |
9251 // This is the test to avoid. | |
9252 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9253 match(Set dst (CmpL3 src1 src2) ); | |
9254 effect( KILL ccr ); | |
9255 ins_cost(6*DEFAULT_COST); | |
9256 size(24); | |
9257 format %{ "CMP $src1,$src2\t\t! long\n" | |
9258 "\tBLT,a,pn done\n" | |
9259 "\tMOV -1,$dst\t! delay slot\n" | |
9260 "\tBGT,a,pn done\n" | |
9261 "\tMOV 1,$dst\t! delay slot\n" | |
9262 "\tCLR $dst\n" | |
9263 "done:" %} | |
9264 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9265 ins_pipe(cmpL_reg); | |
9266 %} | |
9267 | |
9268 // Conditional move | |
9269 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9270 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9271 ins_cost(150); | |
9272 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9273 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9274 ins_pipe(ialu_reg); | |
9275 %} | |
9276 | |
9277 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9278 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9279 ins_cost(140); | |
9280 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9281 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9282 ins_pipe(ialu_imm); | |
9283 %} | |
9284 | |
9285 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9286 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9287 ins_cost(150); | |
9288 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9289 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9290 ins_pipe(ialu_reg); | |
9291 %} | |
9292 | |
9293 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9294 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9295 ins_cost(140); | |
9296 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9297 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9298 ins_pipe(ialu_imm); | |
9299 %} | |
9300 | |
164
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163
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9301 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
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163
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9302 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
c436414a719e
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kvn
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9303 ins_cost(150); |
c436414a719e
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kvn
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163
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|
9304 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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kvn
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163
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9305 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
c436414a719e
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kvn
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9306 ins_pipe(ialu_reg); |
c436414a719e
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9307 %} |
c436414a719e
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9308 |
0 | 9309 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9310 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9311 ins_cost(150); | |
9312 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9313 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9314 ins_pipe(ialu_reg); | |
9315 %} | |
9316 | |
9317 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9318 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9319 ins_cost(140); | |
9320 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9321 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9322 ins_pipe(ialu_imm); | |
9323 %} | |
9324 | |
9325 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9326 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9327 ins_cost(150); | |
9328 opcode(0x101); | |
9329 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9330 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9331 ins_pipe(int_conditional_float_move); | |
9332 %} | |
9333 | |
9334 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9335 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9336 ins_cost(150); | |
9337 opcode(0x102); | |
9338 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9339 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9340 ins_pipe(int_conditional_float_move); | |
9341 %} | |
9342 | |
9343 // ============================================================================ | |
9344 // Safepoint Instruction | |
9345 instruct safePoint_poll(iRegP poll) %{ | |
9346 match(SafePoint poll); | |
9347 effect(USE poll); | |
9348 | |
9349 size(4); | |
9350 #ifdef _LP64 | |
9351 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9352 #else | |
9353 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9354 #endif | |
9355 ins_encode %{ | |
9356 __ relocate(relocInfo::poll_type); | |
9357 __ ld_ptr($poll$$Register, 0, G0); | |
9358 %} | |
9359 ins_pipe(loadPollP); | |
9360 %} | |
9361 | |
9362 // ============================================================================ | |
9363 // Call Instructions | |
9364 // Call Java Static Instruction | |
9365 instruct CallStaticJavaDirect( method meth ) %{ | |
9366 match(CallStaticJava); | |
1567 | 9367 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
0 | 9368 effect(USE meth); |
9369 | |
9370 size(8); | |
9371 ins_cost(CALL_COST); | |
9372 format %{ "CALL,static ; NOP ==> " %} | |
9373 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9374 ins_pc_relative(1); | |
9375 ins_pipe(simple_call); | |
9376 %} | |
9377 | |
1567 | 9378 // Call Java Static Instruction (method handle version) |
9379 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
9380 match(CallStaticJava); | |
9381 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
9382 effect(USE meth, KILL l7_mh_SP_save); | |
9383 | |
9384 size(8); | |
9385 ins_cost(CALL_COST); | |
9386 format %{ "CALL,static/MethodHandle" %} | |
9387 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
9388 ins_pc_relative(1); | |
9389 ins_pipe(simple_call); | |
9390 %} | |
9391 | |
0 | 9392 // Call Java Dynamic Instruction |
9393 instruct CallDynamicJavaDirect( method meth ) %{ | |
9394 match(CallDynamicJava); | |
9395 effect(USE meth); | |
9396 | |
9397 ins_cost(CALL_COST); | |
9398 format %{ "SET (empty),R_G5\n\t" | |
9399 "CALL,dynamic ; NOP ==> " %} | |
9400 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9401 ins_pc_relative(1); | |
9402 ins_pipe(call); | |
9403 %} | |
9404 | |
9405 // Call Runtime Instruction | |
9406 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9407 match(CallRuntime); | |
9408 effect(USE meth, KILL l7); | |
9409 ins_cost(CALL_COST); | |
9410 format %{ "CALL,runtime" %} | |
9411 ins_encode( Java_To_Runtime( meth ), | |
9412 call_epilog, adjust_long_from_native_call ); | |
9413 ins_pc_relative(1); | |
9414 ins_pipe(simple_call); | |
9415 %} | |
9416 | |
9417 // Call runtime without safepoint - same as CallRuntime | |
9418 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9419 match(CallLeaf); | |
9420 effect(USE meth, KILL l7); | |
9421 ins_cost(CALL_COST); | |
9422 format %{ "CALL,runtime leaf" %} | |
9423 ins_encode( Java_To_Runtime( meth ), | |
9424 call_epilog, | |
9425 adjust_long_from_native_call ); | |
9426 ins_pc_relative(1); | |
9427 ins_pipe(simple_call); | |
9428 %} | |
9429 | |
9430 // Call runtime without safepoint - same as CallLeaf | |
9431 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9432 match(CallLeafNoFP); | |
9433 effect(USE meth, KILL l7); | |
9434 ins_cost(CALL_COST); | |
9435 format %{ "CALL,runtime leaf nofp" %} | |
9436 ins_encode( Java_To_Runtime( meth ), | |
9437 call_epilog, | |
9438 adjust_long_from_native_call ); | |
9439 ins_pc_relative(1); | |
9440 ins_pipe(simple_call); | |
9441 %} | |
9442 | |
9443 // Tail Call; Jump from runtime stub to Java code. | |
9444 // Also known as an 'interprocedural jump'. | |
9445 // Target of jump will eventually return to caller. | |
9446 // TailJump below removes the return address. | |
9447 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9448 match(TailCall jump_target method_oop ); | |
9449 | |
9450 ins_cost(CALL_COST); | |
9451 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9452 ins_encode(form_jmpl(jump_target)); | |
9453 ins_pipe(tail_call); | |
9454 %} | |
9455 | |
9456 | |
9457 // Return Instruction | |
9458 instruct Ret() %{ | |
9459 match(Return); | |
9460 | |
9461 // The epilogue node did the ret already. | |
9462 size(0); | |
9463 format %{ "! return" %} | |
9464 ins_encode(); | |
9465 ins_pipe(empty); | |
9466 %} | |
9467 | |
9468 | |
9469 // Tail Jump; remove the return address; jump to target. | |
9470 // TailCall above leaves the return address around. | |
9471 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
9472 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
9473 // "restore" before this instruction (in Epilogue), we need to materialize it | |
9474 // in %i0. | |
9475 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
9476 match( TailJump jump_target ex_oop ); | |
9477 ins_cost(CALL_COST); | |
9478 format %{ "! discard R_O7\n\t" | |
9479 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
9480 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
9481 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
9482 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
9483 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
9484 ins_pipe(tail_call); | |
9485 %} | |
9486 | |
9487 // Create exception oop: created by stack-crawling runtime code. | |
9488 // Created exception is now available to this handler, and is setup | |
9489 // just prior to jumping to this handler. No code emitted. | |
9490 instruct CreateException( o0RegP ex_oop ) | |
9491 %{ | |
9492 match(Set ex_oop (CreateEx)); | |
9493 ins_cost(0); | |
9494 | |
9495 size(0); | |
9496 // use the following format syntax | |
9497 format %{ "! exception oop is in R_O0; no code emitted" %} | |
9498 ins_encode(); | |
9499 ins_pipe(empty); | |
9500 %} | |
9501 | |
9502 | |
9503 // Rethrow exception: | |
9504 // The exception oop will come in the first argument position. | |
9505 // Then JUMP (not call) to the rethrow stub code. | |
9506 instruct RethrowException() | |
9507 %{ | |
9508 match(Rethrow); | |
9509 ins_cost(CALL_COST); | |
9510 | |
9511 // use the following format syntax | |
9512 format %{ "Jmp rethrow_stub" %} | |
9513 ins_encode(enc_rethrow); | |
9514 ins_pipe(tail_call); | |
9515 %} | |
9516 | |
9517 | |
9518 // Die now | |
9519 instruct ShouldNotReachHere( ) | |
9520 %{ | |
9521 match(Halt); | |
9522 ins_cost(CALL_COST); | |
9523 | |
9524 size(4); | |
9525 // Use the following format syntax | |
9526 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
9527 ins_encode( form2_illtrap() ); | |
9528 ins_pipe(tail_call); | |
9529 %} | |
9530 | |
9531 // ============================================================================ | |
9532 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
9533 // array for an instance of the superklass. Set a hidden internal cache on a | |
9534 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
9535 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
9536 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
9537 match(Set index (PartialSubtypeCheck sub super)); | |
9538 effect( KILL pcc, KILL o7 ); | |
9539 ins_cost(DEFAULT_COST*10); | |
9540 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
9541 ins_encode( enc_PartialSubtypeCheck() ); | |
9542 ins_pipe(partial_subtype_check_pipe); | |
9543 %} | |
9544 | |
9545 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
9546 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
9547 effect( KILL idx, KILL o7 ); | |
9548 ins_cost(DEFAULT_COST*10); | |
9549 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
9550 ins_encode( enc_PartialSubtypeCheck() ); | |
9551 ins_pipe(partial_subtype_check_pipe); | |
9552 %} | |
9553 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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81
diff
changeset
|
9554 |
0 | 9555 // ============================================================================ |
9556 // inlined locking and unlocking | |
9557 | |
9558 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9559 match(Set pcc (FastLock object box)); | |
9560 | |
9561 effect(KILL scratch, TEMP scratch2); | |
9562 ins_cost(100); | |
9563 | |
9564 size(4*112); // conservative overestimation ... | |
9565 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9566 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
9567 ins_pipe(long_memory_op); | |
9568 %} | |
9569 | |
9570 | |
9571 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9572 match(Set pcc (FastUnlock object box)); | |
9573 effect(KILL scratch, TEMP scratch2); | |
9574 ins_cost(100); | |
9575 | |
9576 size(4*120); // conservative overestimation ... | |
9577 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9578 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
9579 ins_pipe(long_memory_op); | |
9580 %} | |
9581 | |
9582 // Count and Base registers are fixed because the allocator cannot | |
9583 // kill unknown registers. The encodings are generic. | |
9584 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
9585 match(Set dummy (ClearArray cnt base)); | |
9586 effect(TEMP temp, KILL ccr); | |
9587 ins_cost(300); | |
9588 format %{ "MOV $cnt,$temp\n" | |
9589 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
9590 " BRge loop\t\t! Clearing loop\n" | |
9591 " STX G0,[$base+$temp]\t! delay slot" %} | |
9592 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
9593 ins_pipe(long_memory_op); | |
9594 %} | |
9595 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9596 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9597 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9598 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9599 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 9600 ins_cost(300); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9601 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9602 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 9603 ins_pipe(long_memory_op); |
9604 %} | |
9605 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9606 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9607 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9608 match(Set result (StrEquals (Binary str1 str2) cnt)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9609 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 9610 ins_cost(300); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9611 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9612 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 9613 ins_pipe(long_memory_op); |
9614 %} | |
9615 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9616 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9617 o7RegI tmp2, flagsReg ccr) %{ |
681 | 9618 match(Set result (AryEq ary1 ary2)); |
9619 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
9620 ins_cost(300); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9621 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9622 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 9623 ins_pipe(long_memory_op); |
9624 %} | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9625 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9626 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9627 //---------- Zeros Count Instructions ------------------------------------------ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9628 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9629 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9630 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9631 match(Set dst (CountLeadingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9632 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9633 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9634 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9635 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9636 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9637 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9638 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9639 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9640 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9641 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9642 "OR $dst,$tmp,$dst\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9643 "SRL $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9644 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9645 "SRL $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9646 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9647 "SRL $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9648 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9649 "SRL $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9650 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9651 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9652 "MOV 32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9653 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9654 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9655 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9656 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9657 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9658 __ srl(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9659 __ srl(Rsrc, 0, Rdst); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9660 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9661 __ srl(Rdst, 2, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9662 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9663 __ srl(Rdst, 4, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9664 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9665 __ srl(Rdst, 8, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9666 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9667 __ srl(Rdst, 16, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9668 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9669 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9670 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9671 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9672 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9673 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9674 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9675 |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9676 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9677 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9678 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9679 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9680 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9681 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9682 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9683 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9684 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9685 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9686 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9687 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9688 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9689 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9690 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9691 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9692 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9693 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9694 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9695 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9696 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9697 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9698 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9699 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9700 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9701 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9702 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9703 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9704 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9705 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9706 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9707 __ srlx(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9708 __ or3( Rsrc, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9709 __ srlx(Rdst, 2, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9710 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9711 __ srlx(Rdst, 4, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9712 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9713 __ srlx(Rdst, 8, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9714 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9715 __ srlx(Rdst, 16, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9716 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9717 __ srlx(Rdst, 32, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9718 __ or3( Rdst, Rtmp, Rdst); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9719 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9720 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9721 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9722 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9723 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9724 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9725 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9726 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9727 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9728 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9729 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9730 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9731 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9732 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9733 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9734 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9735 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9736 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9737 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9738 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9739 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9740 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9741 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9742 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9743 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9744 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9745 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9746 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9747 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9748 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9749 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9750 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9751 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9752 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9753 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9754 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9755 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9756 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9757 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9758 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9759 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9760 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9761 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9762 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9763 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9764 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9765 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9766 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9767 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9768 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9769 instruct popCountI(iRegI dst, iRegI src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9770 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9771 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9772 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9773 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9774 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9775 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9776 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9777 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9778 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9779 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9780 // Note: Long.bitCount(long) returns an int. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9781 instruct popCountL(iRegI dst, iRegL src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9782 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9783 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9784 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9785 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9786 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9787 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9788 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9789 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9790 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9791 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9792 |
0 | 9793 // ============================================================================ |
9794 //------------Bytes reverse-------------------------------------------------- | |
9795 | |
9796 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
9797 match(Set dst (ReverseBytesI src)); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9798 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9799 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9800 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9801 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9802 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9803 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9804 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9805 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9806 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9807 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9808 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9809 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9810 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9811 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9812 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9813 match(Set dst (ReverseBytesL src)); |
0 | 9814 |
9815 // Op cost is artificially doubled to make sure that load or store | |
9816 // instructions are preferred over this one which requires a spill | |
9817 // onto a stack slot. | |
9818 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9819 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9820 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9821 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9822 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9823 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9824 %} |
0 | 9825 ins_pipe( iload_mem ); |
9826 %} | |
9827 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9828 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9829 match(Set dst (ReverseBytesUS src)); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9830 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9831 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9832 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9833 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9834 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9835 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9836 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9837 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9838 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9839 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9840 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9841 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9842 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9843 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9844 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9845 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9846 match(Set dst (ReverseBytesS src)); |
0 | 9847 |
9848 // Op cost is artificially doubled to make sure that load or store | |
9849 // instructions are preferred over this one which requires a spill | |
9850 // onto a stack slot. | |
9851 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9852 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9853 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9854 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9855 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9856 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9857 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9858 %} |
0 | 9859 ins_pipe( iload_mem ); |
9860 %} | |
9861 | |
9862 // Load Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9863 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
0 | 9864 match(Set dst (ReverseBytesI (LoadI src))); |
9865 | |
9866 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9867 size(4); |
0 | 9868 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
9869 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9870 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9871 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9872 %} |
0 | 9873 ins_pipe(iload_mem); |
9874 %} | |
9875 | |
9876 // Load Long - aligned and reversed | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9877 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
0 | 9878 match(Set dst (ReverseBytesL (LoadL src))); |
9879 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9880 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9881 size(4); |
0 | 9882 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
9883 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9884 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9885 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9886 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9887 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9888 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9889 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9890 // Load unsigned short / char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9891 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9892 match(Set dst (ReverseBytesUS (LoadUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9893 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9894 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9895 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9896 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9897 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9898 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9899 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9900 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9901 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9902 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9903 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9904 // Load short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9905 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9906 match(Set dst (ReverseBytesS (LoadS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9907 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9908 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9909 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9910 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9911 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9912 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9913 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9914 %} |
0 | 9915 ins_pipe(iload_mem); |
9916 %} | |
9917 | |
9918 // Store Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9919 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
0 | 9920 match(Set dst (StoreI dst (ReverseBytesI src))); |
9921 | |
9922 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9923 size(4); |
0 | 9924 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
9925 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9926 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9927 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9928 %} |
0 | 9929 ins_pipe(istore_mem_reg); |
9930 %} | |
9931 | |
9932 // Store Long reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9933 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
0 | 9934 match(Set dst (StoreL dst (ReverseBytesL src))); |
9935 | |
9936 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9937 size(4); |
0 | 9938 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
9939 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9940 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9941 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9942 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9943 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9944 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9945 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9946 // Store unsighed short/char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9947 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9948 match(Set dst (StoreC dst (ReverseBytesUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9949 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9950 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9951 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9952 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9953 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9954 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9955 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9956 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9957 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9958 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9959 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9960 // Store short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9961 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9962 match(Set dst (StoreC dst (ReverseBytesS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9963 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9964 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9965 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9966 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9967 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9968 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9969 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9970 %} |
0 | 9971 ins_pipe(istore_mem_reg); |
9972 %} | |
9973 | |
9974 //----------PEEPHOLE RULES----------------------------------------------------- | |
9975 // These must follow all instruction definitions as they use the names | |
9976 // defined in the instructions definitions. | |
9977 // | |
605 | 9978 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 9979 // |
9980 // peepconstraint %{ | |
9981 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
9982 // [, ...] ); | |
9983 // // instruction numbers are zero-based using left to right order in peepmatch | |
9984 // | |
9985 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
9986 // // provide an instruction_number.operand_name for each operand that appears | |
9987 // // in the replacement instruction's match rule | |
9988 // | |
9989 // ---------VM FLAGS--------------------------------------------------------- | |
9990 // | |
9991 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
9992 // | |
9993 // Each peephole rule is given an identifying number starting with zero and | |
9994 // increasing by one in the order seen by the parser. An individual peephole | |
9995 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
9996 // on the command-line. | |
9997 // | |
9998 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
9999 // | |
10000 // Only match adjacent instructions in same basic block | |
10001 // Only equality constraints | |
10002 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
10003 // Only one replacement instruction | |
10004 // | |
10005 // ---------EXAMPLE---------------------------------------------------------- | |
10006 // | |
10007 // // pertinent parts of existing instructions in architecture description | |
10008 // instruct movI(eRegI dst, eRegI src) %{ | |
10009 // match(Set dst (CopyI src)); | |
10010 // %} | |
10011 // | |
10012 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
10013 // match(Set dst (AddI dst src)); | |
10014 // effect(KILL cr); | |
10015 // %} | |
10016 // | |
10017 // // Change (inc mov) to lea | |
10018 // peephole %{ | |
10019 // // increment preceeded by register-register move | |
10020 // peepmatch ( incI_eReg movI ); | |
10021 // // require that the destination register of the increment | |
10022 // // match the destination register of the move | |
10023 // peepconstraint ( 0.dst == 1.dst ); | |
10024 // // construct a replacement instruction that sets | |
10025 // // the destination to ( move's source register + one ) | |
10026 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
10027 // %} | |
10028 // | |
10029 | |
10030 // // Change load of spilled value to only a spill | |
10031 // instruct storeI(memory mem, eRegI src) %{ | |
10032 // match(Set mem (StoreI mem src)); | |
10033 // %} | |
10034 // | |
10035 // instruct loadI(eRegI dst, memory mem) %{ | |
10036 // match(Set dst (LoadI mem)); | |
10037 // %} | |
10038 // | |
10039 // peephole %{ | |
10040 // peepmatch ( loadI storeI ); | |
10041 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
10042 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
10043 // %} | |
10044 | |
10045 //----------SMARTSPILL RULES--------------------------------------------------- | |
10046 // These must follow all instruction definitions as they use the names | |
10047 // defined in the instructions definitions. | |
10048 // | |
10049 // SPARC will probably not have any of these rules due to RISC instruction set. | |
10050 | |
10051 //----------PIPELINE----------------------------------------------------------- | |
10052 // Rules which define the behavior of the target architectures pipeline. |