Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 2121:c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
Summary: Make both compilers emit near and far calls when necessary.
Reviewed-by: never, kvn, phh
| author | iveresov |
|---|---|
| date | Wed, 12 Jan 2011 18:33:25 -0800 |
| parents | c04052fd6ae1 |
| children | ab42c7e1cf83 |
| rev | line source |
|---|---|
| 0 | 1 // |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
|
1007
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
|
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
| 429 %} | |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 463 // Macros to extract hi & lo halves from a long pair. | |
| 464 // G0 is not part of any long pair, so assert on that. | |
| 605 | 465 // Prevents accidentally using G1 instead of G0. |
| 0 | 466 #define LONG_HI_REG(x) (x) |
| 467 #define LONG_LO_REG(x) (x) | |
| 468 | |
| 469 %} | |
| 470 | |
| 471 source %{ | |
| 472 #define __ _masm. | |
| 473 | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
474 // Block initializing store |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
476 |
| 0 | 477 // tertiary op of a LoadP or StoreP encoding |
| 478 #define REGP_OP true | |
| 479 | |
| 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 482 static Register reg_to_register_object(int register_encoding); | |
| 483 | |
| 484 // Used by the DFA in dfa_sparc.cpp. | |
| 485 // Check for being able to use a V9 branch-on-register. Requires a | |
| 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 487 // extended. Doesn't work following an integer ADD, for example, because of | |
| 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 490 // replace them with zero, which could become sign-extension in a different OS | |
| 491 // release. There's no obvious reason why an interrupt will ever fill these | |
| 492 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 493 // instructions which either zero-fill or sign-fill). | |
| 494 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 495 if( !BranchOnRegister ) return false; | |
| 496 #ifdef _LP64 | |
| 497 if( cmp->Opcode() == Op_CmpP ) | |
| 498 return true; // No problems with pointer compares | |
| 499 #endif | |
| 500 if( cmp->Opcode() == Op_CmpL ) | |
| 501 return true; // No problems with long compares | |
| 502 | |
| 503 if( !SparcV9RegsHiBitsZero ) return false; | |
| 504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 506 return false; | |
| 507 | |
| 508 // Check for comparing against a 'safe' value. Any operation which | |
| 509 // clears out the high word is safe. Thus, loads and certain shifts | |
| 510 // are safe, as are non-negative constants. Any operation which | |
| 511 // preserves zero bits in the high word is safe as long as each of its | |
| 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 513 // inputs are safe. At present, the only important case to recognize | |
| 514 // seems to be loads. Constants should fold away, and shifts & | |
| 515 // logicals can use the 'cc' forms. | |
| 516 Node *x = cmp->in(1); | |
| 517 if( x->is_Load() ) return true; | |
| 518 if( x->is_Phi() ) { | |
| 519 for( uint i = 1; i < x->req(); i++ ) | |
| 520 if( !x->in(i)->is_Load() ) | |
| 521 return false; | |
| 522 return true; | |
| 523 } | |
| 524 return false; | |
| 525 } | |
| 526 | |
| 527 // **************************************************************************** | |
| 528 | |
| 529 // REQUIRED FUNCTIONALITY | |
| 530 | |
| 531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 532 // from the start of the call to the point where the return address | |
| 533 // will point. | |
| 534 // The "return address" is the address of the call instruction, plus 8. | |
| 535 | |
| 536 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 537 int offset = NativeCall::instruction_size; // call; delay slot |
| 538 if (_method_handle_invoke) | |
| 539 offset += 4; // restore SP | |
| 540 return offset; | |
| 0 | 541 } |
| 542 | |
| 543 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 544 int vtable_index = this->_vtable_index; | |
| 545 if (vtable_index < 0) { | |
| 546 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 548 return (NativeMovConstReg::instruction_size + | |
| 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 550 } else { | |
| 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
554 int klass_load_size; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
555 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
556 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
557 if (Universe::narrow_oop_base() == NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
559 else |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
560 klass_load_size = 3*BytesPerInstWord; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
561 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
562 klass_load_size = 1*BytesPerInstWord; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
563 } |
| 0 | 564 if( Assembler::is_simm13(v_off) ) { |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
565 return klass_load_size + |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 567 NativeCall::instruction_size); // call; delay slot |
| 568 } else { | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
569 return klass_load_size + |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 571 NativeCall::instruction_size); // call; delay slot |
| 572 } | |
| 573 } | |
| 574 } | |
| 575 | |
| 576 int MachCallRuntimeNode::ret_addr_offset() { | |
| 577 #ifdef _LP64 | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
578 if (MacroAssembler::is_far_target(entry_point())) { |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
579 return NativeFarCall::instruction_size; |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
580 } else { |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
581 return NativeCall::instruction_size; |
|
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
582 } |
| 0 | 583 #else |
| 584 return NativeCall::instruction_size; // call; delay slot | |
| 585 #endif | |
| 586 } | |
| 587 | |
| 588 // Indicate if the safepoint node needs the polling page as an input. | |
| 589 // Since Sparc does not have absolute addressing, it does. | |
| 590 bool SafePointNode::needs_polling_address_input() { | |
| 591 return true; | |
| 592 } | |
| 593 | |
| 594 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 595 void emit_break(CodeBuffer &cbuf) { | |
| 596 MacroAssembler _masm(&cbuf); | |
| 597 __ breakpoint_trap(); | |
| 598 } | |
| 599 | |
| 600 #ifndef PRODUCT | |
| 601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 602 st->print("TA"); | |
| 603 } | |
| 604 #endif | |
| 605 | |
| 606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 607 emit_break(cbuf); | |
| 608 } | |
| 609 | |
| 610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 611 return MachNode::size(ra_); | |
| 612 } | |
| 613 | |
| 614 // Traceable jump | |
| 615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 616 MacroAssembler _masm(&cbuf); | |
| 617 Register rdest = reg_to_register_object(jump_target); | |
| 618 __ JMP(rdest, 0); | |
| 619 __ delayed()->nop(); | |
| 620 } | |
| 621 | |
| 622 // Traceable jump and set exception pc | |
| 623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 624 MacroAssembler _masm(&cbuf); | |
| 625 Register rdest = reg_to_register_object(jump_target); | |
| 626 __ JMP(rdest, 0); | |
| 627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 628 } | |
| 629 | |
| 630 void emit_nop(CodeBuffer &cbuf) { | |
| 631 MacroAssembler _masm(&cbuf); | |
| 632 __ nop(); | |
| 633 } | |
| 634 | |
| 635 void emit_illtrap(CodeBuffer &cbuf) { | |
| 636 MacroAssembler _masm(&cbuf); | |
| 637 __ illtrap(0); | |
| 638 } | |
| 639 | |
| 640 | |
| 641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 642 assert(n->rule() != loadUB_rule, ""); | |
| 643 | |
| 644 intptr_t offset = 0; | |
| 645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 646 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 648 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 649 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 650 atype = atype->add_offset(offset); | |
| 651 assert(disp32 == offset, "wrong disp32"); | |
| 652 return atype->_offset; | |
| 653 } | |
| 654 | |
| 655 | |
| 656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 657 assert(n->rule() != loadUB_rule, ""); | |
| 658 | |
| 659 intptr_t offset = 0; | |
| 660 Node* addr = n->in(2); | |
| 661 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 663 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 664 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 666 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 667 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 668 } | |
| 669 offset = atype->is_ptr()->_offset; | |
| 670 if (offset != Type::OffsetBot) offset += disp32; | |
| 671 return offset; | |
| 672 } | |
| 673 | |
| 2008 | 674 static inline jdouble replicate_immI(int con, int count, int width) { |
| 675 // Load a constant replicated "count" times with width "width" | |
| 676 int bit_width = width * 8; | |
| 677 jlong elt_val = con; | |
| 678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits | |
| 679 jlong val = elt_val; | |
| 680 for (int i = 0; i < count - 1; i++) { | |
| 681 val <<= bit_width; | |
| 682 val |= elt_val; | |
| 683 } | |
| 684 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 685 return dval; | |
| 686 } | |
| 687 | |
| 0 | 688 // Standard Sparc opcode form2 field breakdown |
| 689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 690 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 691 int op = (f30 << 30) | | |
| 692 (f29 << 29) | | |
| 693 (f25 << 25) | | |
| 694 (f22 << 22) | | |
| 695 (f20 << 20) | | |
| 696 (f19 << 19) | | |
| 697 (f0 << 0); | |
| 1748 | 698 cbuf.insts()->emit_int32(op); |
| 0 | 699 } |
| 700 | |
| 701 // Standard Sparc opcode form2 field breakdown | |
| 702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 703 f0 >>= 10; // Drop 10 bits | |
| 704 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 705 int op = (f30 << 30) | | |
| 706 (f25 << 25) | | |
| 707 (f22 << 22) | | |
| 708 (f0 << 0); | |
| 1748 | 709 cbuf.insts()->emit_int32(op); |
| 0 | 710 } |
| 711 | |
| 712 // Standard Sparc opcode form3 field breakdown | |
| 713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 714 int op = (f30 << 30) | | |
| 715 (f25 << 25) | | |
| 716 (f19 << 19) | | |
| 717 (f14 << 14) | | |
| 718 (f5 << 5) | | |
| 719 (f0 << 0); | |
| 1748 | 720 cbuf.insts()->emit_int32(op); |
| 0 | 721 } |
| 722 | |
| 723 // Standard Sparc opcode form3 field breakdown | |
| 724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 725 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 726 int op = (f30 << 30) | | |
| 727 (f25 << 25) | | |
| 728 (f19 << 19) | | |
| 729 (f14 << 14) | | |
| 730 (1 << 13) | // bit to indicate immediate-mode | |
| 731 (simm13<<0); | |
| 1748 | 732 cbuf.insts()->emit_int32(op); |
| 0 | 733 } |
| 734 | |
| 735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 736 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 738 } | |
| 739 | |
| 740 #ifdef ASSERT | |
| 741 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 743 warning("VerifyOops encountered unexpected instruction:"); | |
| 744 n->dump(2); | |
| 745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 746 } | |
| 747 #endif | |
| 748 | |
| 749 | |
| 750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 751 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 752 | |
| 753 #ifdef ASSERT | |
| 754 // The following code implements the +VerifyOops feature. | |
| 755 // It verifies oop values which are loaded into or stored out of | |
| 756 // the current method activation. +VerifyOops complements techniques | |
| 757 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 758 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 759 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 760 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 761 // to their point of creation. It can also serve as a cross-check | |
| 762 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 763 | |
| 764 // It would be good to verify oops at other points, especially | |
| 765 // when an oop is used as a base pointer for a load or store. | |
| 766 // This is presently difficult, because it is hard to know when | |
| 767 // a base address is biased or not. (If we had such information, | |
| 768 // it would be easy and useful to make a two-argument version of | |
| 769 // verify_oop which unbiases the base, and performs verification.) | |
| 770 | |
| 771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 772 bool is_verified_oop_base = false; | |
| 773 bool is_verified_oop_load = false; | |
| 774 bool is_verified_oop_store = false; | |
| 775 int tmp_enc = -1; | |
| 776 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 777 // classify the op, mainly for an assert check | |
| 778 int st_op = 0, ld_op = 0; | |
| 779 switch (primary) { | |
| 780 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 781 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 783 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 784 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 785 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 786 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 787 | |
| 788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 791 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 793 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 794 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 795 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 796 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 797 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 799 | |
| 800 default: ShouldNotReachHere(); | |
| 801 } | |
| 802 if (tertiary == REGP_OP) { | |
| 803 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 805 else ShouldNotReachHere(); | |
| 806 if (st_op) { | |
| 807 // a store | |
| 808 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 809 Node* n2 = n->in(3); | |
| 810 if (n2 != NULL) { | |
| 811 const Type* t = n2->bottom_type(); | |
| 812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 813 } | |
| 814 } else { | |
| 815 // a load | |
| 816 const Type* t = n->bottom_type(); | |
| 817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 818 } | |
| 819 } | |
| 820 | |
| 821 if (ld_op) { | |
| 822 // a Load | |
| 823 // inputs are (0:control, 1:memory, 2:address) | |
| 824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && |
| 0 | 842 !(n->rule() == loadUB_rule)) { |
| 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 844 } | |
| 845 } else if (st_op) { | |
| 846 // a Store | |
| 847 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && |
| 0 | 856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 857 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 858 } | |
| 859 } | |
| 860 | |
| 861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 862 Node* addr = n->in(2); | |
| 863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 865 if (atype != NULL) { | |
| 866 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 868 if (offset != offset_2) { | |
| 869 get_offset_from_base(n, atype, disp32); | |
| 870 get_offset_from_base_2(n, atype, disp32); | |
| 871 } | |
| 872 assert(offset == offset_2, "different offsets"); | |
| 873 if (offset == disp32) { | |
| 874 // we now know that src1 is a true oop pointer | |
| 875 is_verified_oop_base = true; | |
| 876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 877 if( primary == Assembler::ldd_op3 ) { | |
| 878 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 879 } else { | |
| 880 tmp_enc = dst_enc; | |
| 881 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 882 assert(src1_enc != dst_enc, ""); | |
| 883 } | |
| 884 } | |
| 885 } | |
| 886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 887 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 888 // loading the mark should not be allowed either, but | |
| 889 // we don't check this since it conflicts with InlineObjectHash | |
| 890 // usage of LoadINode to get the mark. We could keep the | |
| 891 // check if we create a new LoadMarkNode | |
| 892 // but do not verify the object before its header is initialized | |
| 893 ShouldNotReachHere(); | |
| 894 } | |
| 895 } | |
| 896 } | |
| 897 } | |
| 898 } | |
| 899 #endif | |
| 900 | |
| 901 uint instr; | |
| 902 instr = (Assembler::ldst_op << 30) | |
| 903 | (dst_enc << 25) | |
| 904 | (primary << 19) | |
| 905 | (src1_enc << 14); | |
| 906 | |
| 907 uint index = src2_enc; | |
| 908 int disp = disp32; | |
| 909 | |
| 910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 911 disp += STACK_BIAS; | |
| 912 | |
| 913 // We should have a compiler bailout here rather than a guarantee. | |
| 914 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 916 | |
| 917 if( disp == 0 ) { | |
| 918 // use reg-reg form | |
| 919 // bit 13 is already zero | |
| 920 instr |= index; | |
| 921 } else { | |
| 922 // use reg-imm form | |
| 923 instr |= 0x00002000; // set bit 13 to one | |
| 924 instr |= disp & 0x1FFF; | |
| 925 } | |
| 926 | |
| 1748 | 927 cbuf.insts()->emit_int32(instr); |
| 0 | 928 |
| 929 #ifdef ASSERT | |
| 930 { | |
| 931 MacroAssembler _masm(&cbuf); | |
| 932 if (is_verified_oop_base) { | |
| 933 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 934 } | |
| 935 if (is_verified_oop_store) { | |
| 936 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 937 } | |
| 938 if (tmp_enc != -1) { | |
| 939 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 940 } | |
| 941 if (is_verified_oop_load) { | |
| 942 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 943 } | |
| 944 } | |
| 945 #endif | |
| 946 } | |
| 947 | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
| 0 | 949 // The method which records debug information at every safepoint |
| 950 // expects the call to be the first instruction in the snippet as | |
| 951 // it creates a PcDesc structure which tracks the offset of a call | |
| 952 // from the start of the codeBlob. This offset is computed as | |
| 953 // code_end() - code_begin() of the code which has been emitted | |
| 954 // so far. | |
| 955 // In this particular case we have skirted around the problem by | |
| 956 // putting the "mov" instruction in the delay slot but the problem | |
| 957 // may bite us again at some other point and a cleaner/generic | |
| 958 // solution using relocations would be needed. | |
| 959 MacroAssembler _masm(&cbuf); | |
| 960 __ set_inst_mark(); | |
| 961 | |
| 962 // We flush the current window just so that there is a valid stack copy | |
| 963 // the fact that the current window becomes active again instantly is | |
| 964 // not a problem there is nothing live in it. | |
| 965 | |
| 966 #ifdef ASSERT | |
| 967 int startpos = __ offset(); | |
| 968 #endif /* ASSERT */ | |
| 969 | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
970 __ call((address)entry_point, rtype); |
| 0 | 971 |
| 972 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 973 else __ delayed()->nop(); | |
| 974 | |
| 975 if (preserve_g2) __ mov(L7, G2); | |
| 976 | |
| 977 #ifdef ASSERT | |
| 978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 979 #ifdef _LP64 | |
| 980 // Trash argument dump slots. | |
| 981 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 982 __ mov(G1, G5); | |
| 983 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 984 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 985 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 986 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 987 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 988 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 989 #else // _LP64 | |
| 990 // this is also a native call, so smash the first 7 stack locations, | |
| 991 // and the various registers | |
| 992 | |
| 993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 994 // while [SP+0x44..0x58] are the argument dump slots. | |
| 995 __ set((intptr_t)0xbaadf00d, G1); | |
| 996 __ mov(G1, G5); | |
| 997 __ sllx(G1, 32, G1); | |
| 998 __ or3(G1, G5, G1); | |
| 999 __ mov(G1, G5); | |
| 1000 __ stx(G1, SP, 0x40); | |
| 1001 __ stx(G1, SP, 0x48); | |
| 1002 __ stx(G1, SP, 0x50); | |
| 1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1004 #endif // _LP64 | |
| 1005 } | |
| 1006 #endif /*ASSERT*/ | |
| 1007 } | |
| 1008 | |
| 1009 //============================================================================= | |
| 1010 // REQUIRED FUNCTIONALITY for encoding | |
| 1011 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1012 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1013 | |
| 1014 | |
| 1015 //============================================================================= | |
| 2008 | 1016 const bool Matcher::constant_table_absolute_addressing = false; |
| 1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; | |
| 1018 | |
| 1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 1020 Compile* C = ra_->C; | |
| 1021 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1022 MacroAssembler _masm(&cbuf); | |
| 1023 | |
| 1024 Register r = as_Register(ra_->get_encode(this)); | |
| 1025 CodeSection* cs = __ code()->consts(); | |
| 1026 int consts_size = cs->align_at_start(cs->size()); | |
| 1027 | |
| 1028 if (UseRDPCForConstantTableBase) { | |
| 1029 // For the following RDPC logic to work correctly the consts | |
| 1030 // section must be allocated right before the insts section. This | |
| 1031 // assert checks for that. The layout and the SECT_* constants | |
| 1032 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
| 1034 int offset = __ offset(); | |
| 1035 int disp; | |
| 1036 | |
| 1037 // If the displacement from the current PC to the constant table | |
| 1038 // base fits into simm13 we set the constant table base to the | |
| 1039 // current PC. | |
| 1040 if (__ is_simm13(-(consts_size + offset))) { | |
| 1041 constant_table.set_table_base_offset(-(consts_size + offset)); | |
| 1042 disp = 0; | |
| 1043 } else { | |
| 1044 // If the offset of the top constant (last entry in the table) | |
| 1045 // fits into simm13 we set the constant table base to the actual | |
| 1046 // table base. | |
| 1047 if (__ is_simm13(constant_table.top_offset())) { | |
| 1048 constant_table.set_table_base_offset(0); | |
| 1049 disp = consts_size + offset; | |
| 1050 } else { | |
| 1051 // Otherwise we set the constant table base in the middle of the | |
| 1052 // constant table. | |
| 1053 int half_consts_size = consts_size / 2; | |
| 1054 assert(half_consts_size * 2 == consts_size, "sanity"); | |
| 1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. | |
| 1056 disp = half_consts_size + offset; | |
| 1057 } | |
| 1058 } | |
| 1059 | |
| 1060 __ rdpc(r); | |
| 1061 | |
| 1062 if (disp != 0) { | |
| 1063 assert(r != O7, "need temporary"); | |
| 1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1065 } | |
| 1066 } | |
| 1067 else { | |
| 1068 // Materialize the constant table base. | |
| 1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | |
| 1070 address baseaddr = cs->start() + -(constant_table.table_base_offset()); | |
| 1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); | |
| 1072 AddressLiteral base(baseaddr, rspec); | |
| 1073 __ set(base, r); | |
| 1074 } | |
| 1075 } | |
| 1076 | |
| 1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1078 if (UseRDPCForConstantTableBase) { | |
| 1079 // This is really the worst case but generally it's only 1 instruction. | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
| 2008 | 1081 } else { |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
| 2008 | 1083 } |
| 1084 } | |
| 1085 | |
| 1086 #ifndef PRODUCT | |
| 1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1088 char reg[128]; | |
| 1089 ra_->dump_register(this, reg); | |
| 1090 if (UseRDPCForConstantTableBase) { | |
| 1091 st->print("RDPC %s\t! constant table base", reg); | |
| 1092 } else { | |
| 1093 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1094 } | |
| 1095 } | |
| 1096 #endif | |
| 1097 | |
| 1098 | |
| 1099 //============================================================================= | |
| 0 | 1100 |
| 1101 #ifndef PRODUCT | |
| 1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1103 Compile* C = ra_->C; | |
| 1104 | |
| 1105 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1106 st->print_cr("NOP"); st->print("\t"); | |
| 1107 } | |
| 1108 | |
| 1109 if( VerifyThread ) { | |
| 1110 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1111 } | |
| 1112 | |
| 1113 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1114 | |
| 1115 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1116 // We require that their callers must bang for them. But be careful, because | |
| 1117 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1118 // stack. But the stack safety zone should account for that. | |
| 1119 // See bugs 4446381, 4468289, 4497237. | |
| 1120 if (C->need_stack_bang(framesize)) { | |
| 1121 st->print_cr("! stack bang"); st->print("\t"); | |
| 1122 } | |
| 1123 | |
| 1124 if (Assembler::is_simm13(-framesize)) { | |
| 1125 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1126 } else { | |
| 1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1129 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1130 } | |
| 1131 | |
| 1132 } | |
| 1133 #endif | |
| 1134 | |
| 1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1136 Compile* C = ra_->C; | |
| 1137 MacroAssembler _masm(&cbuf); | |
| 1138 | |
| 1139 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1140 __ nop(); | |
| 1141 } | |
| 1142 | |
| 1143 __ verify_thread(); | |
| 1144 | |
| 1145 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1146 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1148 | |
| 1149 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1150 // We require that their callers must bang for them. But be careful, because | |
| 1151 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1152 // stack. But the stack safety zone should account for that. | |
| 1153 // See bugs 4446381, 4468289, 4497237. | |
| 1154 if (C->need_stack_bang(framesize)) { | |
| 1155 __ generate_stack_overflow_check(framesize); | |
| 1156 } | |
| 1157 | |
| 1158 if (Assembler::is_simm13(-framesize)) { | |
| 1159 __ save(SP, -framesize, SP); | |
| 1160 } else { | |
| 1161 __ sethi(-framesize & ~0x3ff, G3); | |
| 1162 __ add(G3, -framesize & 0x3ff, G3); | |
| 1163 __ save(SP, G3, SP); | |
| 1164 } | |
| 1165 C->set_frame_complete( __ offset() ); | |
| 1166 } | |
| 1167 | |
| 1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1169 return MachNode::size(ra_); | |
| 1170 } | |
| 1171 | |
| 1172 int MachPrologNode::reloc() const { | |
| 1173 return 10; // a large enough number | |
| 1174 } | |
| 1175 | |
| 1176 //============================================================================= | |
| 1177 #ifndef PRODUCT | |
| 1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1179 Compile* C = ra_->C; | |
| 1180 | |
| 1181 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1183 #ifdef _LP64 | |
| 1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1185 #else | |
| 1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1187 #endif | |
| 1188 } | |
| 1189 | |
| 1190 if( do_polling() ) | |
| 1191 st->print("RET\n\t"); | |
| 1192 | |
| 1193 st->print("RESTORE"); | |
| 1194 } | |
| 1195 #endif | |
| 1196 | |
| 1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1198 MacroAssembler _masm(&cbuf); | |
| 1199 Compile* C = ra_->C; | |
| 1200 | |
| 1201 __ verify_thread(); | |
| 1202 | |
| 1203 // If this does safepoint polling, then do it here | |
| 1204 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1205 AddressLiteral polling_page(os::get_polling_page()); |
| 1206 __ sethi(polling_page, L0); | |
| 0 | 1207 __ relocate(relocInfo::poll_return_type); |
| 1208 __ ld_ptr( L0, 0, G0 ); | |
| 1209 } | |
| 1210 | |
| 1211 // If this is a return, then stuff the restore in the delay slot | |
| 1212 if( do_polling() ) { | |
| 1213 __ ret(); | |
| 1214 __ delayed()->restore(); | |
| 1215 } else { | |
| 1216 __ restore(); | |
| 1217 } | |
| 1218 } | |
| 1219 | |
| 1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1221 return MachNode::size(ra_); | |
| 1222 } | |
| 1223 | |
| 1224 int MachEpilogNode::reloc() const { | |
| 1225 return 16; // a large enough number | |
| 1226 } | |
| 1227 | |
| 1228 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1229 return MachNode::pipeline_class(); | |
| 1230 } | |
| 1231 | |
| 1232 int MachEpilogNode::safepoint_offset() const { | |
| 1233 assert( do_polling(), "no return for this epilog node"); | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
| 0 | 1235 } |
| 1236 | |
| 1237 //============================================================================= | |
| 1238 | |
| 1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1240 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1241 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1242 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1243 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1244 VMReg r = OptoReg::as_VMReg(reg); | |
| 1245 if (r->is_Register()) return rc_int; | |
| 1246 assert(r->is_FloatRegister(), "must be"); | |
| 1247 return rc_float; | |
| 1248 } | |
| 1249 | |
| 1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1251 if( cbuf ) { | |
| 1252 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1255 } else { | |
| 1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1257 } | |
| 1258 } | |
| 1259 #ifndef PRODUCT | |
| 1260 else if( !do_size ) { | |
| 1261 if( size != 0 ) st->print("\n\t"); | |
| 1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1264 } | |
| 1265 #endif | |
| 1266 return size+4; | |
| 1267 } | |
| 1268 | |
| 1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1271 #ifndef PRODUCT | |
| 1272 else if( !do_size ) { | |
| 1273 if( size != 0 ) st->print("\n\t"); | |
| 1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1275 } | |
| 1276 #endif | |
| 1277 return size+4; | |
| 1278 } | |
| 1279 | |
| 1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1281 PhaseRegAlloc *ra_, | |
| 1282 bool do_size, | |
| 1283 outputStream* st ) const { | |
| 1284 // Get registers to move | |
| 1285 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1286 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1287 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1288 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1289 | |
| 1290 enum RC src_second_rc = rc_class(src_second); | |
| 1291 enum RC src_first_rc = rc_class(src_first); | |
| 1292 enum RC dst_second_rc = rc_class(dst_second); | |
| 1293 enum RC dst_first_rc = rc_class(dst_first); | |
| 1294 | |
| 1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1296 | |
| 1297 // Generate spill code! | |
| 1298 int size = 0; | |
| 1299 | |
| 1300 if( src_first == dst_first && src_second == dst_second ) | |
| 1301 return size; // Self copy, no move | |
| 1302 | |
| 1303 // -------------------------------------- | |
| 1304 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1305 // the float-store case. | |
| 1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1307 int offset = ra_->reg2offset(src_first); | |
| 1308 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1309 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1310 src_second = OptoReg::Name(R_F31_num); | |
| 1311 src_second_rc = rc_float; | |
| 1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1313 } else { | |
| 1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1315 } | |
| 1316 src_first = OptoReg::Name(R_F30_num); | |
| 1317 src_first_rc = rc_float; | |
| 1318 } | |
| 1319 | |
| 1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1321 int offset = ra_->reg2offset(src_second); | |
| 1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1323 src_second = OptoReg::Name(R_F31_num); | |
| 1324 src_second_rc = rc_float; | |
| 1325 } | |
| 1326 | |
| 1327 // -------------------------------------- | |
| 1328 // Check for float->int copy; requires a trip through memory | |
| 1329 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
| 1330 int offset = frame::register_save_words*wordSize; | |
| 1331 if( cbuf ) { | |
| 1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
| 1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1336 } | |
| 1337 #ifndef PRODUCT | |
| 1338 else if( !do_size ) { | |
| 1339 if( size != 0 ) st->print("\n\t"); | |
| 1340 st->print( "SUB R_SP,16,R_SP\n"); | |
| 1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1343 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1344 } | |
| 1345 #endif | |
| 1346 size += 16; | |
| 1347 } | |
| 1348 | |
| 1349 // -------------------------------------- | |
| 1350 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1351 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1352 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1353 // there. Misaligned sources only come from native-long-returns (handled | |
| 1354 // special below). | |
| 1355 #ifndef _LP64 | |
| 1356 if( src_first_rc == rc_int && // source is already big-endian | |
| 1357 src_second_rc != rc_bad && // 64-bit move | |
| 1358 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1359 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1360 // Do the big-endian flop. | |
| 1361 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1362 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1363 } | |
| 1364 #endif | |
| 1365 | |
| 1366 // -------------------------------------- | |
| 1367 // Check for integer reg-reg copy | |
| 1368 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1369 #ifndef _LP64 | |
| 1370 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1371 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1372 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1373 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1374 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1375 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1376 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1377 if( cbuf ) { | |
| 1378 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1379 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1380 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1381 #ifndef PRODUCT | |
| 1382 } else if( !do_size ) { | |
| 1383 if( size != 0 ) st->print("\n\t"); | |
| 1384 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1385 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1386 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1387 #endif | |
| 1388 } | |
| 1389 return size+12; | |
| 1390 } | |
| 1391 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1392 // returning a long value in I0/I1 | |
| 1393 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1394 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1395 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1396 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1397 OptoReg::Name tdest = dst_first; | |
| 1398 | |
| 1399 if (src_first == dst_first) { | |
| 1400 tdest = OptoReg::Name(R_O7_num); | |
| 1401 size += 4; | |
| 1402 } | |
| 1403 | |
| 1404 if( cbuf ) { | |
| 1405 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1406 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1407 // ShrL_reg_imm6 | |
| 1408 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1409 // ShrR_reg_imm6 src, 0, dst | |
| 1410 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1411 if (tdest != dst_first) { | |
| 1412 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1413 } | |
| 1414 } | |
| 1415 #ifndef PRODUCT | |
| 1416 else if( !do_size ) { | |
| 1417 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1418 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1419 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1420 if (tdest != dst_first) { | |
| 1421 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1422 } | |
| 1423 } | |
| 1424 #endif // PRODUCT | |
| 1425 return size+8; | |
| 1426 } | |
| 1427 #endif // !_LP64 | |
| 1428 // Else normal reg-reg copy | |
| 1429 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1430 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1431 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1432 // This moves an aligned adjacent pair. | |
| 1433 // See if we are done. | |
| 1434 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1435 return size; | |
| 1436 } | |
| 1437 | |
| 1438 // Check for integer store | |
| 1439 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1440 int offset = ra_->reg2offset(dst_first); | |
| 1441 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1442 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1443 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1444 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1445 } | |
| 1446 | |
| 1447 // Check for integer load | |
| 1448 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1449 int offset = ra_->reg2offset(src_first); | |
| 1450 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1451 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1452 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1453 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1454 } | |
| 1455 | |
| 1456 // Check for float reg-reg copy | |
| 1457 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1458 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1459 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1460 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1461 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1462 } | |
| 1463 | |
| 1464 // Check for float store | |
| 1465 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1466 int offset = ra_->reg2offset(dst_first); | |
| 1467 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1468 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1469 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1470 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1471 } | |
| 1472 | |
| 1473 // Check for float load | |
| 1474 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1475 int offset = ra_->reg2offset(src_first); | |
| 1476 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1477 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1478 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1479 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1480 } | |
| 1481 | |
| 1482 // -------------------------------------------------------------------- | |
| 1483 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1484 // arguments to native calls. | |
| 1485 if( src_second == dst_second ) | |
| 1486 return size; // Self copy; no move | |
| 1487 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1488 | |
| 1489 #ifndef _LP64 | |
| 1490 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1491 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1492 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1493 // all sorts of silly alignment problems. | |
| 1494 | |
| 1495 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1496 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1497 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1498 // happened already as part of a 64-bit move) | |
| 1499 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1500 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1501 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1502 // Shift src_second down to dst_second's low bits. | |
| 1503 if( cbuf ) { | |
| 1504 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1505 #ifndef PRODUCT | |
| 1506 } else if( !do_size ) { | |
| 1507 if( size != 0 ) st->print("\n\t"); | |
| 1508 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1509 #endif | |
| 1510 } | |
| 1511 return size+4; | |
| 1512 } | |
| 1513 | |
| 1514 // Check for high word integer store. Must down-shift the hi bits | |
| 1515 // into a temp register, then fall into the case of storing int bits. | |
| 1516 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1517 // Shift src_second down to dst_second's low bits. | |
| 1518 if( cbuf ) { | |
| 1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1520 #ifndef PRODUCT | |
| 1521 } else if( !do_size ) { | |
| 1522 if( size != 0 ) st->print("\n\t"); | |
| 1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1524 #endif | |
| 1525 } | |
| 1526 size+=4; | |
| 1527 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1528 } | |
| 1529 | |
| 1530 // Check for high word integer load | |
| 1531 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1532 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1533 | |
| 1534 // Check for high word integer store | |
| 1535 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1536 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1537 | |
| 1538 // Check for high word float store | |
| 1539 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1540 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1541 | |
| 1542 #endif // !_LP64 | |
| 1543 | |
| 1544 Unimplemented(); | |
| 1545 } | |
| 1546 | |
| 1547 #ifndef PRODUCT | |
| 1548 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1549 implementation( NULL, ra_, false, st ); | |
| 1550 } | |
| 1551 #endif | |
| 1552 | |
| 1553 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1554 implementation( &cbuf, ra_, false, NULL ); | |
| 1555 } | |
| 1556 | |
| 1557 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1558 return implementation( NULL, ra_, true, NULL ); | |
| 1559 } | |
| 1560 | |
| 1561 //============================================================================= | |
| 1562 #ifndef PRODUCT | |
| 1563 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1564 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1565 } | |
| 1566 #endif | |
| 1567 | |
| 1568 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1569 MacroAssembler _masm(&cbuf); | |
| 1570 for(int i = 0; i < _count; i += 1) { | |
| 1571 __ nop(); | |
| 1572 } | |
| 1573 } | |
| 1574 | |
| 1575 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1576 return 4 * _count; | |
| 1577 } | |
| 1578 | |
| 1579 | |
| 1580 //============================================================================= | |
| 1581 #ifndef PRODUCT | |
| 1582 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1583 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1584 int reg = ra_->get_reg_first(this); | |
| 1585 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1586 } | |
| 1587 #endif | |
| 1588 | |
| 1589 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1590 MacroAssembler _masm(&cbuf); | |
| 1591 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1592 int reg = ra_->get_encode(this); | |
| 1593 | |
| 1594 if (Assembler::is_simm13(offset)) { | |
| 1595 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1596 } else { | |
| 1597 __ set(offset, O7); | |
| 1598 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1599 } | |
| 1600 } | |
| 1601 | |
| 1602 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1603 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1604 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1605 return ra_->C->scratch_emit_size(this); | |
| 1606 } | |
| 1607 | |
| 1608 //============================================================================= | |
| 1609 | |
| 1610 // emit call stub, compiled java to interpretor | |
| 1611 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1612 | |
| 1613 // Stub is fixed up when the corresponding call is converted from calling | |
| 1614 // compiled code to calling interpreted code. | |
| 1615 // set (empty), G5 | |
| 1616 // jmp -1 | |
| 1617 | |
| 1748 | 1618 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 0 | 1619 |
| 1620 MacroAssembler _masm(&cbuf); | |
| 1621 | |
| 1622 address base = | |
| 1623 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1624 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1625 | |
| 1626 // static stub relocation stores the instruction address of the call | |
| 1627 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1628 | |
| 1629 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1630 | |
| 1631 __ set_inst_mark(); | |
| 727 | 1632 AddressLiteral addrlit(-1); |
| 1633 __ JUMP(addrlit, G3, 0); | |
| 0 | 1634 |
| 1635 __ delayed()->nop(); | |
| 1636 | |
| 1637 // Update current stubs pointer and restore code_end. | |
| 1638 __ end_a_stub(); | |
| 1639 } | |
| 1640 | |
| 1641 // size of call stub, compiled java to interpretor | |
| 1642 uint size_java_to_interp() { | |
| 1643 // This doesn't need to be accurate but it must be larger or equal to | |
| 1644 // the real size of the stub. | |
| 1645 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1646 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1647 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1648 } | |
| 1649 // relocation entries for call stub, compiled java to interpretor | |
| 1650 uint reloc_java_to_interp() { | |
| 1651 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1652 } | |
| 1653 | |
| 1654 | |
| 1655 //============================================================================= | |
| 1656 #ifndef PRODUCT | |
| 1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1658 st->print_cr("\nUEP:"); | |
| 1659 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1660 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1661 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1663 st->print_cr("\tSLL R_G5,3,R_G5"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1664 if (Universe::narrow_oop_base() != NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1665 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1666 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1667 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1668 } |
| 0 | 1669 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1670 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1671 #else // _LP64 | |
| 1672 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1673 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1674 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1675 #endif // _LP64 | |
| 1676 } | |
| 1677 #endif | |
| 1678 | |
| 1679 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1680 MacroAssembler _masm(&cbuf); | |
| 1681 Label L; | |
| 1682 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1683 Register temp_reg = G3; | |
| 1684 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1685 | |
| 605 | 1686 // Load klass from receiver |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1687 __ load_klass(O0, temp_reg); |
| 0 | 1688 // Compare against expected klass |
| 1689 __ cmp(temp_reg, G5_ic_reg); | |
| 1690 // Branch to miss code, checks xcc or icc depending | |
| 1691 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1692 } | |
| 1693 | |
| 1694 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1695 return MachNode::size(ra_); | |
| 1696 } | |
| 1697 | |
| 1698 | |
| 1699 //============================================================================= | |
| 1700 | |
| 1701 uint size_exception_handler() { | |
| 1702 if (TraceJumps) { | |
| 1703 return (400); // just a guess | |
| 1704 } | |
| 1705 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1706 } | |
| 1707 | |
| 1708 uint size_deopt_handler() { | |
| 1709 if (TraceJumps) { | |
| 1710 return (400); // just a guess | |
| 1711 } | |
| 1712 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1713 } | |
| 1714 | |
| 1715 // Emit exception handler code. | |
| 1716 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1717 Register temp_reg = G3; | |
| 1748 | 1718 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1719 MacroAssembler _masm(&cbuf); |
| 1720 | |
| 1721 address base = | |
| 1722 __ start_a_stub(size_exception_handler()); | |
| 1723 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1724 | |
| 1725 int offset = __ offset(); | |
| 1726 | |
| 727 | 1727 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1728 __ delayed()->nop(); |
| 1729 | |
| 1730 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1731 | |
| 1732 __ end_a_stub(); | |
| 1733 | |
| 1734 return offset; | |
| 1735 } | |
| 1736 | |
| 1737 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1738 // Can't use any of the current frame's registers as we may have deopted | |
| 1739 // at a poll and everything (including G3) can be live. | |
| 1740 Register temp_reg = L0; | |
| 727 | 1741 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1742 MacroAssembler _masm(&cbuf); |
| 1743 | |
| 1744 address base = | |
| 1745 __ start_a_stub(size_deopt_handler()); | |
| 1746 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1747 | |
| 1748 int offset = __ offset(); | |
| 1749 __ save_frame(0); | |
| 727 | 1750 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1751 __ delayed()->restore(); |
| 1752 | |
| 1753 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1754 | |
| 1755 __ end_a_stub(); | |
| 1756 return offset; | |
| 1757 | |
| 1758 } | |
| 1759 | |
| 1760 // Given a register encoding, produce a Integer Register object | |
| 1761 static Register reg_to_register_object(int register_encoding) { | |
| 1762 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1763 return as_Register(register_encoding); | |
| 1764 } | |
| 1765 | |
| 1766 // Given a register encoding, produce a single-precision Float Register object | |
| 1767 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1768 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1769 return as_SingleFloatRegister(register_encoding); | |
| 1770 } | |
| 1771 | |
| 1772 // Given a register encoding, produce a double-precision Float Register object | |
| 1773 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1774 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1775 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1776 return as_DoubleFloatRegister(register_encoding); | |
| 1777 } | |
| 1778 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1779 const bool Matcher::match_rule_supported(int opcode) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1780 if (!has_match_rule(opcode)) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1781 return false; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1782 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1783 switch (opcode) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1784 case Op_CountLeadingZerosI: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1785 case Op_CountLeadingZerosL: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1786 case Op_CountTrailingZerosI: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1787 case Op_CountTrailingZerosL: |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1788 if (!UsePopCountInstruction) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1789 return false; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1790 break; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1791 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1792 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1793 return true; // Per default match rules are supported. |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1794 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1795 |
| 0 | 1796 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1797 return regnum - 32; // The FP registers are in the second chunk | |
| 1798 } | |
| 1799 | |
| 1800 #ifdef ASSERT | |
| 1801 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1802 #endif | |
| 1803 | |
| 1804 // Vector width in bytes | |
| 1805 const uint Matcher::vector_width_in_bytes(void) { | |
| 1806 return 8; | |
| 1807 } | |
| 1808 | |
| 1809 // Vector ideal reg | |
| 1810 const uint Matcher::vector_ideal_reg(void) { | |
| 1811 return Op_RegD; | |
| 1812 } | |
| 1813 | |
| 1814 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1815 const bool Matcher::convL2FSupported(void) { | |
| 1816 return VM_Version::has_fast_fxtof(); | |
| 1817 } | |
| 1818 | |
| 1819 // Is this branch offset short enough that a short branch can be used? | |
| 1820 // | |
| 1821 // NOTE: If the platform does not provide any short branch variants, then | |
| 1822 // this method should return false for offset 0. | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1823 bool Matcher::is_short_branch_offset(int rule, int offset) { |
| 0 | 1824 return false; |
| 1825 } | |
| 1826 | |
| 1827 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1828 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1829 // Depends on optimizations in MacroAssembler::setx. | |
| 1830 int hi = (int)(value >> 32); | |
| 1831 int lo = (int)(value & ~0); | |
| 1832 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1833 } | |
| 1834 | |
| 1835 // No scaling for the parameter the ClearArray node. | |
| 1836 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1837 | |
| 1838 // Threshold size for cleararray. | |
| 1839 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1840 | |
| 1841 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1842 // be subsumed into complex addressing expressions or compute them into | |
| 1843 // registers? True for Intel but false for most RISCs | |
| 1844 const bool Matcher::clone_shift_expressions = false; | |
| 1845 | |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1846 bool Matcher::narrow_oop_use_complex_address() { |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1847 NOT_LP64(ShouldNotCallThis()); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1848 assert(UseCompressedOops, "only for compressed oops code"); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1849 return false; |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1850 } |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1851 |
| 0 | 1852 // Is it better to copy float constants, or load them directly from memory? |
| 1853 // Intel can load a float constant from a direct address, requiring no | |
| 1854 // extra registers. Most RISCs will have to materialize an address into a | |
| 1855 // register first, so they would do better to copy the constant from stack. | |
| 1856 const bool Matcher::rematerialize_float_constants = false; | |
| 1857 | |
| 1858 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1859 // needed. Else we split the double into 2 integer pieces and move it | |
| 1860 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1861 // Java calling convention forces doubles to be aligned. | |
| 1862 #ifdef _LP64 | |
| 1863 const bool Matcher::misaligned_doubles_ok = true; | |
| 1864 #else | |
| 1865 const bool Matcher::misaligned_doubles_ok = false; | |
| 1866 #endif | |
| 1867 | |
| 1868 // No-op on SPARC. | |
| 1869 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1870 } | |
| 1871 | |
| 1872 // Advertise here if the CPU requires explicit rounding operations | |
| 1873 // to implement the UseStrictFP mode. | |
| 1874 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1875 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1876 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1877 // Sparc does not handle callee-save floats. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1878 bool Matcher::float_in_double() { return false; } |
| 0 | 1879 |
| 1880 // Do ints take an entire long register or just half? | |
| 1881 // Note that we if-def off of _LP64. | |
| 1882 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1883 // the whole long is written but de-opt'ing will have to extract | |
| 1884 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1885 #ifdef _LP64 | |
| 1886 const bool Matcher::int_in_long = true; | |
| 1887 #else | |
| 1888 const bool Matcher::int_in_long = false; | |
| 1889 #endif | |
| 1890 | |
| 1891 // Return whether or not this register is ever used as an argument. This | |
| 1892 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1893 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1894 // arguments in those registers not be available to the callee. | |
| 1895 bool Matcher::can_be_java_arg( int reg ) { | |
| 1896 // Standard sparc 6 args in registers | |
| 1897 if( reg == R_I0_num || | |
| 1898 reg == R_I1_num || | |
| 1899 reg == R_I2_num || | |
| 1900 reg == R_I3_num || | |
| 1901 reg == R_I4_num || | |
| 1902 reg == R_I5_num ) return true; | |
| 1903 #ifdef _LP64 | |
| 1904 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1905 // the high I registers | |
| 1906 if( reg == R_I0H_num || | |
| 1907 reg == R_I1H_num || | |
| 1908 reg == R_I2H_num || | |
| 1909 reg == R_I3H_num || | |
| 1910 reg == R_I4H_num || | |
| 1911 reg == R_I5H_num ) return true; | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1912 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1913 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1914 return true; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1915 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1916 |
| 0 | 1917 #else |
| 1918 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1919 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1920 // after a 'save' and I regs get their high bits chopped off on | |
| 1921 // interrupt. | |
| 1922 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1923 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1924 #endif | |
| 1925 // A few float args in registers | |
| 1926 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1927 | |
| 1928 return false; | |
| 1929 } | |
| 1930 | |
| 1931 bool Matcher::is_spillable_arg( int reg ) { | |
| 1932 return can_be_java_arg(reg); | |
| 1933 } | |
| 1934 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1935 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1936 // Use hardware SDIVX instruction when it is |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1937 // faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1938 return VM_Version::has_fast_idiv(); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1939 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1940 |
| 0 | 1941 // Register for DIVI projection of divmodI |
| 1942 RegMask Matcher::divI_proj_mask() { | |
| 1943 ShouldNotReachHere(); | |
| 1944 return RegMask(); | |
| 1945 } | |
| 1946 | |
| 1947 // Register for MODI projection of divmodI | |
| 1948 RegMask Matcher::modI_proj_mask() { | |
| 1949 ShouldNotReachHere(); | |
| 1950 return RegMask(); | |
| 1951 } | |
| 1952 | |
| 1953 // Register for DIVL projection of divmodL | |
| 1954 RegMask Matcher::divL_proj_mask() { | |
| 1955 ShouldNotReachHere(); | |
| 1956 return RegMask(); | |
| 1957 } | |
| 1958 | |
| 1959 // Register for MODL projection of divmodL | |
| 1960 RegMask Matcher::modL_proj_mask() { | |
| 1961 ShouldNotReachHere(); | |
| 1962 return RegMask(); | |
| 1963 } | |
| 1964 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
1965 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
| 1567 | 1966 return L7_REGP_mask; |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
1967 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
1968 |
| 0 | 1969 %} |
| 1970 | |
| 1971 | |
| 1972 // The intptr_t operand types, defined by textual substitution. | |
| 1973 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1974 #ifdef _LP64 | |
| 824 | 1975 #define immX immL |
| 1976 #define immX13 immL13 | |
| 1977 #define immX13m7 immL13m7 | |
| 1978 #define iRegX iRegL | |
| 1979 #define g1RegX g1RegL | |
| 0 | 1980 #else |
| 824 | 1981 #define immX immI |
| 1982 #define immX13 immI13 | |
| 1983 #define immX13m7 immI13m7 | |
| 1984 #define iRegX iRegI | |
| 1985 #define g1RegX g1RegI | |
| 0 | 1986 #endif |
| 1987 | |
| 1988 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1989 // This block specifies the encoding classes used by the compiler to output | |
| 1990 // byte streams. Encoding classes are parameterized macros used by | |
| 1991 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1992 // instruction. Operands specify their base encoding interface with the | |
| 1993 // interface keyword. There are currently supported four interfaces, | |
| 1994 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1995 // operand to generate a function which returns its register number when | |
| 1996 // queried. CONST_INTER causes an operand to generate a function which | |
| 1997 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1998 // operand to generate four functions which return the Base Register, the | |
| 1999 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2000 // queried. COND_INTER causes an operand to generate six functions which | |
| 2001 // return the encoding code (ie - encoding bits for the instruction) | |
| 2002 // associated with each basic boolean condition for a conditional instruction. | |
| 2003 // | |
| 2004 // Instructions specify two basic values for encoding. Again, a function | |
| 2005 // is available to check if the constant displacement is an oop. They use the | |
| 2006 // ins_encode keyword to specify their encoding classes (which must be | |
| 2007 // a sequence of enc_class names, and their parameters, specified in | |
| 2008 // the encoding block), and they use the | |
| 2009 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2010 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2011 // needs for encoding need to be specified. | |
| 2012 encode %{ | |
| 2013 enc_class enc_untested %{ | |
| 2014 #ifdef ASSERT | |
| 2015 MacroAssembler _masm(&cbuf); | |
| 2016 __ untested("encoding"); | |
| 2017 #endif | |
| 2018 %} | |
| 2019 | |
| 2020 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 2021 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 2022 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 2023 %} | |
| 2024 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2025 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2026 emit_form3_mem_reg(cbuf, this, $primary, -1, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2027 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2028 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2029 |
| 0 | 2030 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2031 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2032 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2033 %} | |
| 2034 | |
| 2035 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2036 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2037 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2038 %} | |
| 2039 | |
| 2040 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 2041 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2042 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2043 guarantee($mem$$index == R_G0_enc, "double index?"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2044 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2045 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2046 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2047 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2048 %} | |
| 2049 | |
| 2050 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 2051 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2052 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2053 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 2054 // Load long with 2 instructions | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2055 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2056 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2057 %} |
| 2058 | |
| 2059 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2060 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2061 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2062 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2063 %} |
| 2064 | |
| 2065 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2066 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2067 if( $rs2$$reg != $rd$$reg ) | |
| 2068 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2069 %} | |
| 2070 | |
| 2071 // Target lo half of long | |
| 2072 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2073 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2074 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2075 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2076 %} | |
| 2077 | |
| 2078 // Source lo half of long | |
| 2079 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2080 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2081 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2082 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2083 %} | |
| 2084 | |
| 2085 // Target hi half of long | |
| 2086 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2087 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2088 %} | |
| 2089 | |
| 2090 // Source lo half of long, and leave it sign extended. | |
| 2091 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2092 // Sign extend low half | |
| 2093 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2094 %} | |
| 2095 | |
| 2096 // Source hi half of long, and leave it sign extended. | |
| 2097 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2098 // Shift high half to low half | |
| 2099 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2100 %} | |
| 2101 | |
| 2102 // Source hi half of long | |
| 2103 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2104 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2105 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2106 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2107 %} | |
| 2108 | |
| 2109 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2110 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2111 %} | |
| 2112 | |
| 2113 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2114 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2115 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2116 %} | |
| 2117 | |
| 2118 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2119 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2120 // clear if nothing else is happening | |
| 2121 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2122 // blt,a,pn done | |
| 2123 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2124 // mov dst,-1 in delay slot | |
| 2125 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2126 %} | |
| 2127 | |
| 2128 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2129 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2130 %} | |
| 2131 | |
| 2132 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2133 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2134 %} | |
| 2135 | |
| 2136 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2137 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2138 %} | |
| 2139 | |
| 2140 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2141 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2142 %} | |
| 2143 | |
| 2144 enc_class move_return_pc_to_o1() %{ | |
| 2145 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2146 %} | |
| 2147 | |
| 2148 #ifdef _LP64 | |
| 2149 /* %%% merge with enc_to_bool */ | |
| 2150 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2151 MacroAssembler _masm(&cbuf); | |
| 2152 | |
| 2153 Register src_reg = reg_to_register_object($src$$reg); | |
| 2154 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2155 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2156 %} | |
| 2157 #endif | |
| 2158 | |
| 2159 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2160 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2161 MacroAssembler _masm(&cbuf); | |
| 2162 | |
| 2163 Register p_reg = reg_to_register_object($p$$reg); | |
| 2164 Register q_reg = reg_to_register_object($q$$reg); | |
| 2165 Register y_reg = reg_to_register_object($y$$reg); | |
| 2166 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2167 | |
| 2168 __ subcc( p_reg, q_reg, p_reg ); | |
| 2169 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2170 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2171 %} | |
| 2172 | |
| 2173 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2174 // fcmp %fcc0,$src,$src | |
| 2175 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2176 // branch %fcc0 not-nan, predict taken | |
| 2177 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2178 // fdtoi $src,$dst | |
| 2179 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2180 // fitos $dst,$dst (if nan) | |
| 2181 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2182 // clear $dst (if nan) | |
| 2183 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2184 // carry on here... | |
| 2185 %} | |
| 2186 | |
| 2187 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2188 // fcmp %fcc0,$src,$src check for NAN | |
| 2189 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2190 // branch %fcc0 not-nan, predict taken | |
| 2191 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2192 // fdtox $src,$dst convert in delay slot | |
| 2193 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2194 // fxtod $dst,$dst (if nan) | |
| 2195 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2196 // clear $dst (if nan) | |
| 2197 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2198 // carry on here... | |
| 2199 %} | |
| 2200 | |
| 2201 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2202 // fcmps %fcc0,$src,$src | |
| 2203 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2204 // branch %fcc0 not-nan, predict taken | |
| 2205 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2206 // fstoi $src,$dst | |
| 2207 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2208 // fitos $dst,$dst (if nan) | |
| 2209 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2210 // clear $dst (if nan) | |
| 2211 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2212 // carry on here... | |
| 2213 %} | |
| 2214 | |
| 2215 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2216 // fcmps %fcc0,$src,$src | |
| 2217 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2218 // branch %fcc0 not-nan, predict taken | |
| 2219 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2220 // fstox $src,$dst | |
| 2221 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2222 // fxtod $dst,$dst (if nan) | |
| 2223 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2224 // clear $dst (if nan) | |
| 2225 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2226 // carry on here... | |
| 2227 %} | |
| 2228 | |
| 2229 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2230 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2231 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2232 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2233 | |
| 2234 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2235 | |
| 2236 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2237 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2238 | |
| 2239 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2240 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2241 %} | |
| 2242 | |
| 2243 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2244 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2245 %} | |
| 2246 | |
| 2247 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2248 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2249 %} | |
| 2250 | |
| 2251 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2252 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2253 %} | |
| 2254 | |
| 2255 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2256 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2257 %} | |
| 2258 | |
| 2259 // Encloding class for traceable jumps | |
| 2260 enc_class form_jmpl(g3RegP dest) %{ | |
| 2261 emit_jmpl(cbuf, $dest$$reg); | |
| 2262 %} | |
| 2263 | |
| 2264 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2265 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2266 %} | |
| 2267 | |
| 2268 enc_class form2_nop() %{ | |
| 2269 emit_nop(cbuf); | |
| 2270 %} | |
| 2271 | |
| 2272 enc_class form2_illtrap() %{ | |
| 2273 emit_illtrap(cbuf); | |
| 2274 %} | |
| 2275 | |
| 2276 | |
| 2277 // Compare longs and convert into -1, 0, 1. | |
| 2278 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2279 // CMP $src1,$src2 | |
| 2280 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2281 // blt,a,pn done | |
| 2282 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2283 // mov dst,-1 in delay slot | |
| 2284 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2285 // bgt,a,pn done | |
| 2286 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2287 // mov dst,1 in delay slot | |
| 2288 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2289 // CLR $dst | |
| 2290 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2291 %} | |
| 2292 | |
| 2293 enc_class enc_PartialSubtypeCheck() %{ | |
| 2294 MacroAssembler _masm(&cbuf); | |
| 2295 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2296 __ delayed()->nop(); | |
| 2297 %} | |
| 2298 | |
| 2299 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
| 2300 MacroAssembler _masm(&cbuf); | |
| 2301 Label &L = *($labl$$label); | |
| 2302 Assembler::Predict predict_taken = | |
| 2303 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2304 | |
| 2305 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
| 2306 __ delayed()->nop(); | |
| 2307 %} | |
| 2308 | |
| 2309 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
| 2310 MacroAssembler _masm(&cbuf); | |
| 2311 Label &L = *($labl$$label); | |
| 2312 Assembler::Predict predict_taken = | |
| 2313 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2314 | |
| 2315 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
| 2316 __ delayed()->nop(); | |
| 2317 %} | |
| 2318 | |
| 2319 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
| 2320 MacroAssembler _masm(&cbuf); | |
| 2321 Label &L = *($labl$$label); | |
| 2322 Assembler::Predict predict_taken = | |
| 2323 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2324 | |
| 2325 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
| 2326 __ delayed()->nop(); | |
| 2327 %} | |
| 2328 | |
| 2329 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
| 2330 MacroAssembler _masm(&cbuf); | |
| 2331 Label &L = *($labl$$label); | |
| 2332 Assembler::Predict predict_taken = | |
| 2333 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2334 | |
| 2335 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
| 2336 __ delayed()->nop(); | |
| 2337 %} | |
| 2338 | |
| 2339 enc_class enc_ba( Label labl ) %{ | |
| 2340 MacroAssembler _masm(&cbuf); | |
| 2341 Label &L = *($labl$$label); | |
| 2342 __ ba(false, L); | |
| 2343 __ delayed()->nop(); | |
| 2344 %} | |
| 2345 | |
| 2346 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
| 2347 MacroAssembler _masm(&cbuf); | |
| 2348 Label &L = *$labl$$label; | |
| 2349 Assembler::Predict predict_taken = | |
| 2350 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2351 | |
| 2352 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
| 2353 __ delayed()->nop(); | |
| 2354 %} | |
| 2355 | |
| 2356 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2357 int op = (Assembler::arith_op << 30) | | |
| 2358 ($dst$$reg << 25) | | |
| 2359 (Assembler::movcc_op3 << 19) | | |
| 2360 (1 << 18) | // cc2 bit for 'icc' | |
| 2361 ($cmp$$cmpcode << 14) | | |
| 2362 (0 << 13) | // select register move | |
| 2363 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2364 ($src$$reg << 0); | |
| 1748 | 2365 cbuf.insts()->emit_int32(op); |
| 0 | 2366 %} |
| 2367 | |
| 2368 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2369 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2370 int op = (Assembler::arith_op << 30) | | |
| 2371 ($dst$$reg << 25) | | |
| 2372 (Assembler::movcc_op3 << 19) | | |
| 2373 (1 << 18) | // cc2 bit for 'icc' | |
| 2374 ($cmp$$cmpcode << 14) | | |
| 2375 (1 << 13) | // select immediate move | |
| 2376 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2377 (simm11 << 0); | |
| 1748 | 2378 cbuf.insts()->emit_int32(op); |
| 0 | 2379 %} |
| 2380 | |
| 2381 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2382 int op = (Assembler::arith_op << 30) | | |
| 2383 ($dst$$reg << 25) | | |
| 2384 (Assembler::movcc_op3 << 19) | | |
| 2385 (0 << 18) | // cc2 bit for 'fccX' | |
| 2386 ($cmp$$cmpcode << 14) | | |
| 2387 (0 << 13) | // select register move | |
| 2388 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2389 ($src$$reg << 0); | |
| 1748 | 2390 cbuf.insts()->emit_int32(op); |
| 0 | 2391 %} |
| 2392 | |
| 2393 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2394 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2395 int op = (Assembler::arith_op << 30) | | |
| 2396 ($dst$$reg << 25) | | |
| 2397 (Assembler::movcc_op3 << 19) | | |
| 2398 (0 << 18) | // cc2 bit for 'fccX' | |
| 2399 ($cmp$$cmpcode << 14) | | |
| 2400 (1 << 13) | // select immediate move | |
| 2401 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2402 (simm11 << 0); | |
| 1748 | 2403 cbuf.insts()->emit_int32(op); |
| 0 | 2404 %} |
| 2405 | |
| 2406 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2407 int op = (Assembler::arith_op << 30) | | |
| 2408 ($dst$$reg << 25) | | |
| 2409 (Assembler::fpop2_op3 << 19) | | |
| 2410 (0 << 18) | | |
| 2411 ($cmp$$cmpcode << 14) | | |
| 2412 (1 << 13) | // select register move | |
| 2413 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2414 ($primary << 5) | // select single, double or quad | |
| 2415 ($src$$reg << 0); | |
| 1748 | 2416 cbuf.insts()->emit_int32(op); |
| 0 | 2417 %} |
| 2418 | |
| 2419 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2420 int op = (Assembler::arith_op << 30) | | |
| 2421 ($dst$$reg << 25) | | |
| 2422 (Assembler::fpop2_op3 << 19) | | |
| 2423 (0 << 18) | | |
| 2424 ($cmp$$cmpcode << 14) | | |
| 2425 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2426 ($primary << 5) | // select single, double or quad | |
| 2427 ($src$$reg << 0); | |
| 1748 | 2428 cbuf.insts()->emit_int32(op); |
| 0 | 2429 %} |
| 2430 | |
| 2431 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2432 // the condition comes from opcode-field instead of an argument. | |
| 2433 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2434 int op = (Assembler::arith_op << 30) | | |
| 2435 ($dst$$reg << 25) | | |
| 2436 (Assembler::movcc_op3 << 19) | | |
| 2437 (1 << 18) | // cc2 bit for 'icc' | |
| 2438 ($primary << 14) | | |
| 2439 (0 << 13) | // select register move | |
| 2440 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2441 ($src$$reg << 0); | |
| 1748 | 2442 cbuf.insts()->emit_int32(op); |
| 0 | 2443 %} |
| 2444 | |
| 2445 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2446 int op = (Assembler::arith_op << 30) | | |
| 2447 ($dst$$reg << 25) | | |
| 2448 (Assembler::movcc_op3 << 19) | | |
| 2449 (6 << 16) | // cc2 bit for 'xcc' | |
| 2450 ($primary << 14) | | |
| 2451 (0 << 13) | // select register move | |
| 2452 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2453 ($src$$reg << 0); | |
| 1748 | 2454 cbuf.insts()->emit_int32(op); |
| 0 | 2455 %} |
| 2456 | |
| 2457 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2458 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2459 %} | |
| 2460 | |
| 2461 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2462 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2463 %} | |
| 2464 | |
| 2465 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2466 MacroAssembler _masm(&cbuf); | |
| 2467 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2468 %} | |
| 2469 | |
| 2470 enc_class call_epilog %{ | |
| 2471 if( VerifyStackAtCalls ) { | |
| 2472 MacroAssembler _masm(&cbuf); | |
| 2473 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2474 Register temp_reg = G3; | |
| 2475 __ add(SP, framesize, temp_reg); | |
| 2476 __ cmp(temp_reg, FP); | |
| 2477 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2478 } | |
| 2479 %} | |
| 2480 | |
| 2481 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2482 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2483 // pair. | |
| 2484 enc_class adjust_long_from_native_call %{ | |
| 2485 #ifndef _LP64 | |
| 2486 if (returns_long()) { | |
| 2487 // sllx O0,32,O0 | |
| 2488 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2489 // srl O1,0,O1 | |
| 2490 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2491 // or O0,O1,G1 | |
| 2492 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2493 } | |
| 2494 #endif | |
| 2495 %} | |
| 2496 | |
| 2497 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2498 // CALL directly to the runtime | |
| 2499 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2500 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
|
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
2501 /*preserve_g2=*/true); |
| 0 | 2502 %} |
| 2503 | |
| 1567 | 2504 enc_class preserve_SP %{ |
| 2505 MacroAssembler _masm(&cbuf); | |
| 2506 __ mov(SP, L7_mh_SP_save); | |
| 2507 %} | |
| 2508 | |
| 2509 enc_class restore_SP %{ | |
| 2510 MacroAssembler _masm(&cbuf); | |
| 2511 __ mov(L7_mh_SP_save, SP); | |
| 2512 %} | |
| 2513 | |
| 0 | 2514 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2515 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2516 // who we intended to call. | |
| 2517 if ( !_method ) { | |
| 2518 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2519 } else if (_optimized_virtual) { | |
| 2520 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2521 } else { | |
| 2522 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2523 } | |
| 2524 if( _method ) { // Emit stub for static call | |
| 2525 emit_java_to_interp(cbuf); | |
| 2526 } | |
| 2527 %} | |
| 2528 | |
| 2529 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2530 MacroAssembler _masm(&cbuf); | |
| 2531 __ set_inst_mark(); | |
| 2532 int vtable_index = this->_vtable_index; | |
| 2533 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2534 if (vtable_index < 0) { | |
| 2535 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2536 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2537 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2538 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2539 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2540 // !!!!! | |
| 2541 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2542 // emit_call_dynamic_prologue( cbuf ); | |
| 2543 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2544 | |
| 2545 address virtual_call_oop_addr = __ inst_mark(); | |
| 2546 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2547 // who we intended to call. | |
| 2548 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2549 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2550 } else { | |
| 2551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2552 // Just go thru the vtable | |
| 2553 // get receiver klass (receiver already checked for non-null) | |
| 2554 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2555 int off = __ offset(); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2556 __ load_klass(O0, G3_scratch); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2557 int klass_load_size; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2558 if (UseCompressedOops) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2559 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2560 if (Universe::narrow_oop_base() == NULL) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2561 klass_load_size = 2*BytesPerInstWord; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2562 else |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2563 klass_load_size = 3*BytesPerInstWord; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2564 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2565 klass_load_size = 1*BytesPerInstWord; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2566 } |
| 0 | 2567 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2568 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2569 if( __ is_simm13(v_off) ) { | |
| 2570 __ ld_ptr(G3, v_off, G5_method); | |
| 2571 } else { | |
| 2572 // Generate 2 instructions | |
| 2573 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2574 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2575 // ld_ptr, set_hi, set | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2576 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2577 "Unexpected instruction size(s)"); |
| 0 | 2578 __ ld_ptr(G3, G5_method, G5_method); |
| 2579 } | |
| 2580 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2581 // However it may very well end up in handle_wrong_method if the | |
| 2582 // method is abstract for the particular class. | |
| 2583 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2584 // jump to target (either compiled code or c2iadapter) | |
| 2585 __ jmpl(G3_scratch, G0, O7); | |
| 2586 __ delayed()->nop(); | |
| 2587 } | |
| 2588 %} | |
| 2589 | |
| 2590 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2591 MacroAssembler _masm(&cbuf); | |
| 2592 | |
| 2593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2594 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2595 // we might be calling a C2I adapter which needs it. | |
| 2596 | |
| 2597 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2598 // Load nmethod | |
| 2599 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2600 | |
| 2601 // CALL to compiled java, indirect the contents of G3 | |
| 2602 __ set_inst_mark(); | |
| 2603 __ callr(temp_reg, G0); | |
| 2604 __ delayed()->nop(); | |
| 2605 %} | |
| 2606 | |
| 2607 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2608 MacroAssembler _masm(&cbuf); | |
| 2609 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2610 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2611 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2612 | |
| 2613 __ sra(Rdivisor, 0, Rdivisor); | |
| 2614 __ sra(Rdividend, 0, Rdividend); | |
| 2615 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2616 %} | |
| 2617 | |
| 2618 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2619 MacroAssembler _masm(&cbuf); | |
| 2620 | |
| 2621 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2622 int divisor = $imm$$constant; | |
| 2623 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2624 | |
| 2625 __ sra(Rdividend, 0, Rdividend); | |
| 2626 __ sdivx(Rdividend, divisor, Rresult); | |
| 2627 %} | |
| 2628 | |
| 2629 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2630 MacroAssembler _masm(&cbuf); | |
| 2631 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2632 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2633 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2634 | |
| 2635 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2636 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2637 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2638 __ srlx( Rdst, 32, Rdst ); | |
| 2639 %} | |
| 2640 | |
| 2641 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2642 MacroAssembler _masm(&cbuf); | |
| 2643 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2644 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2645 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2646 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2647 | |
| 2648 assert(Rdividend != Rscratch, ""); | |
| 2649 assert(Rdivisor != Rscratch, ""); | |
| 2650 | |
| 2651 __ sra(Rdividend, 0, Rdividend); | |
| 2652 __ sra(Rdivisor, 0, Rdivisor); | |
| 2653 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2654 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2655 __ sub(Rdividend, Rscratch, Rresult); | |
| 2656 %} | |
| 2657 | |
| 2658 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2659 MacroAssembler _masm(&cbuf); | |
| 2660 | |
| 2661 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2662 int divisor = $imm$$constant; | |
| 2663 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2664 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2665 | |
| 2666 assert(Rdividend != Rscratch, ""); | |
| 2667 | |
| 2668 __ sra(Rdividend, 0, Rdividend); | |
| 2669 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2670 __ mulx(Rscratch, divisor, Rscratch); | |
| 2671 __ sub(Rdividend, Rscratch, Rresult); | |
| 2672 %} | |
| 2673 | |
| 2674 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2675 MacroAssembler _masm(&cbuf); | |
| 2676 | |
| 2677 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2678 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2679 | |
| 2680 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2681 %} | |
| 2682 | |
| 2683 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2684 MacroAssembler _masm(&cbuf); | |
| 2685 | |
| 2686 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2687 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2688 | |
| 2689 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2690 %} | |
| 2691 | |
| 2692 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2693 MacroAssembler _masm(&cbuf); | |
| 2694 | |
| 2695 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2696 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2697 | |
| 2698 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2699 %} | |
| 2700 | |
| 2701 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2702 MacroAssembler _masm(&cbuf); | |
| 2703 | |
| 2704 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2705 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2706 | |
| 2707 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2708 %} | |
| 2709 | |
| 2710 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2711 MacroAssembler _masm(&cbuf); | |
| 2712 | |
| 2713 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2714 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2715 | |
| 2716 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2717 %} | |
| 2718 | |
| 2719 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2720 MacroAssembler _masm(&cbuf); | |
| 2721 | |
| 2722 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2723 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2724 | |
| 2725 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2726 %} | |
| 2727 | |
| 2728 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2729 MacroAssembler _masm(&cbuf); | |
| 2730 | |
| 2731 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2732 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2733 | |
| 2734 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2735 %} | |
| 2736 | |
| 2737 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2738 MacroAssembler _masm(&cbuf); | |
| 2739 | |
| 2740 Register Roop = reg_to_register_object($oop$$reg); | |
| 2741 Register Rbox = reg_to_register_object($box$$reg); | |
| 2742 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2743 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2744 | |
| 2745 assert(Roop != Rscratch, ""); | |
| 2746 assert(Roop != Rmark, ""); | |
| 2747 assert(Rbox != Rscratch, ""); | |
| 2748 assert(Rbox != Rmark, ""); | |
| 2749 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2750 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2751 %} |
| 2752 | |
| 2753 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2754 MacroAssembler _masm(&cbuf); | |
| 2755 | |
| 2756 Register Roop = reg_to_register_object($oop$$reg); | |
| 2757 Register Rbox = reg_to_register_object($box$$reg); | |
| 2758 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2759 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2760 | |
| 2761 assert(Roop != Rscratch, ""); | |
| 2762 assert(Roop != Rmark, ""); | |
| 2763 assert(Rbox != Rscratch, ""); | |
| 2764 assert(Rbox != Rmark, ""); | |
| 2765 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2766 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2767 %} |
| 2768 | |
| 2769 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2770 MacroAssembler _masm(&cbuf); | |
| 2771 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2772 Register Rold = reg_to_register_object($old$$reg); | |
| 2773 Register Rnew = reg_to_register_object($new$$reg); | |
| 2774 | |
| 2775 // casx_under_lock picks 1 of 3 encodings: | |
| 2776 // For 32-bit pointers you get a 32-bit CAS | |
| 2777 // For 64-bit pointers you get a 64-bit CASX | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2778 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2779 __ cmp( Rold, Rnew ); |
| 2780 %} | |
| 2781 | |
| 2782 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2783 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2784 Register Rold = reg_to_register_object($old$$reg); | |
| 2785 Register Rnew = reg_to_register_object($new$$reg); | |
| 2786 | |
| 2787 MacroAssembler _masm(&cbuf); | |
| 2788 __ mov(Rnew, O7); | |
| 2789 __ casx(Rmem, Rold, O7); | |
| 2790 __ cmp( Rold, O7 ); | |
| 2791 %} | |
| 2792 | |
| 2793 // raw int cas, used for compareAndSwap | |
| 2794 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2795 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2796 Register Rold = reg_to_register_object($old$$reg); | |
| 2797 Register Rnew = reg_to_register_object($new$$reg); | |
| 2798 | |
| 2799 MacroAssembler _masm(&cbuf); | |
| 2800 __ mov(Rnew, O7); | |
| 2801 __ cas(Rmem, Rold, O7); | |
| 2802 __ cmp( Rold, O7 ); | |
| 2803 %} | |
| 2804 | |
| 2805 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2806 Register Rres = reg_to_register_object($res$$reg); | |
| 2807 | |
| 2808 MacroAssembler _masm(&cbuf); | |
| 2809 __ mov(1, Rres); | |
| 2810 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2811 %} | |
| 2812 | |
| 2813 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2814 Register Rres = reg_to_register_object($res$$reg); | |
| 2815 | |
| 2816 MacroAssembler _masm(&cbuf); | |
| 2817 __ mov(1, Rres); | |
| 2818 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2819 %} | |
| 2820 | |
| 2821 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2822 MacroAssembler _masm(&cbuf); | |
| 2823 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2824 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2825 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2826 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2827 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2828 | |
| 2829 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2830 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2831 %} | |
| 2832 | |
| 2833 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2834 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2835 MacroAssembler _masm(&cbuf); | |
| 2836 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2837 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2838 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 2839 | |
| 2840 Label loop; | |
| 2841 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 2842 | |
| 2843 // Loop and clear, walking backwards through the array. | |
| 2844 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2845 __ bind(loop); | |
| 2846 __ deccc(nof_bytes_tmp, 8); | |
| 2847 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2848 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2849 // %%%% this mini-loop must not cross a cache boundary! | |
| 2850 %} | |
| 2851 | |
| 2852 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2853 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2854 Label Ldone, Lloop; |
| 2855 MacroAssembler _masm(&cbuf); | |
| 2856 | |
| 2857 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2858 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2859 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2860 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2861 Register result_reg = reg_to_register_object($result$$reg); |
| 2862 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2863 assert(result_reg != str1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2864 result_reg != str2_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2865 result_reg != cnt1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2866 result_reg != cnt2_reg , |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2867 "need different registers"); |
| 0 | 2868 |
| 2869 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2870 // difference of the string lengths (stack) | |
| 2871 | |
| 2872 // See if the lengths are different, and calculate min in str1_reg. | |
| 2873 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2874 Label Lskip; | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2875 __ subcc(cnt1_reg, cnt2_reg, O7); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2876 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2877 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2878 // cnt2 is shorter, so use its count: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2879 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2880 __ bind(Lskip); |
| 2881 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2882 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2883 // Note: limit_reg holds the string length pre-scaled by 2 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2884 Register limit_reg = cnt1_reg; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2885 Register chr2_reg = cnt2_reg; |
| 0 | 2886 Register chr1_reg = result_reg; |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2887 // str{12} are the base pointers |
| 0 | 2888 |
| 2889 // Is the minimum length zero? | |
| 2890 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2891 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2892 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2893 | |
| 2894 // Load first characters | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2895 __ lduh(str1_reg, 0, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2896 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2897 |
| 2898 // Compare first characters | |
| 2899 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2900 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2901 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2902 __ delayed()->nop(); | |
| 2903 | |
| 2904 { | |
| 2905 // Check after comparing first character to see if strings are equivalent | |
| 2906 Label LSkip2; | |
| 2907 // Check if the strings start at same location | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2908 __ cmp(str1_reg, str2_reg); |
| 0 | 2909 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2910 __ delayed()->nop(); | |
| 2911 | |
| 2912 // Check if the length difference is zero (in O7) | |
| 2913 __ cmp(G0, O7); | |
| 2914 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2915 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2916 | |
| 2917 // Strings might not be equal | |
| 2918 __ bind(LSkip2); | |
| 2919 } | |
| 2920 | |
| 2921 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2922 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2923 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2924 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2925 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2926 __ add(str1_reg, limit_reg, str1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2927 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2928 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2929 | |
| 2930 // Compare the rest of the characters | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2931 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2932 __ bind(Lloop); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2933 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2934 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2935 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2936 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2937 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2938 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2939 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2940 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2941 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2942 |
| 2943 // If strings are equal up to min length, return the length difference. | |
| 2944 __ mov(O7, result_reg); | |
| 2945 | |
| 2946 // Otherwise, return the difference between the first mismatched chars. | |
| 2947 __ bind(Ldone); | |
| 2948 %} | |
| 2949 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2950 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2951 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2952 MacroAssembler _masm(&cbuf); |
| 2953 | |
| 2954 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2955 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2956 Register cnt_reg = reg_to_register_object($cnt$$reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2957 Register tmp1_reg = O7; |
| 681 | 2958 Register result_reg = reg_to_register_object($result$$reg); |
| 2959 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2960 assert(result_reg != str1_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2961 result_reg != str2_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2962 result_reg != cnt_reg && |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2963 result_reg != tmp1_reg , |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2964 "need different registers"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2965 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2966 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2967 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2968 __ delayed()->add(G0, 1, result_reg); | |
| 2969 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2970 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2971 __ delayed()->add(G0, 1, result_reg); // count == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2972 |
| 681 | 2973 //rename registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2974 Register limit_reg = cnt_reg; |
| 681 | 2975 Register chr1_reg = result_reg; |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2976 Register chr2_reg = tmp1_reg; |
| 681 | 2977 |
| 2978 //check for alignment and position the pointers to the ends | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2979 __ or3(str1_reg, str2_reg, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2980 __ andcc(chr1_reg, 0x3, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2981 // notZero means at least one not 4-byte aligned. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2982 // We could optimize the case when both arrays are not aligned |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2983 // but it is not frequent case and it requires additional checks. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2984 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2985 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2986 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2987 // Compare char[] arrays aligned to 4 bytes. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2988 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2989 chr1_reg, chr2_reg, Ldone); |
| 681 | 2990 __ ba(false,Ldone); |
| 2991 __ delayed()->add(G0, 1, result_reg); | |
| 2992 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2993 // char by char compare |
| 681 | 2994 __ bind(Lchar); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2995 __ add(str1_reg, limit_reg, str1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2996 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 2997 __ neg(limit_reg); //negate count |
| 2998 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2999 __ lduh(str1_reg, limit_reg, chr1_reg); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3000 // Lchar_loop |
| 681 | 3001 __ bind(Lchar_loop); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3002 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 3003 __ cmp(chr1_reg, chr2_reg); |
| 3004 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 3005 __ delayed()->mov(G0, result_reg); //not equal | |
| 3006 __ inccc(limit_reg, sizeof(jchar)); | |
| 3007 // annul LDUH if branch is not taken to prevent access past end of string | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3008 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3009 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 3010 |
| 3011 __ add(G0, 1, result_reg); //equal | |
| 3012 | |
| 3013 __ bind(Ldone); | |
| 3014 %} | |
| 3015 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3016 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 3017 Label Lvector, Ldone, Lloop; |
| 3018 MacroAssembler _masm(&cbuf); | |
| 3019 | |
| 3020 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3021 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3022 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3023 Register tmp2_reg = O7; |
| 681 | 3024 Register result_reg = reg_to_register_object($result$$reg); |
| 3025 | |
| 3026 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3027 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3028 | |
| 3029 // return true if the same array | |
| 3030 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3031 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3032 __ delayed()->add(G0, 1, result_reg); // equal |
| 3033 | |
| 3034 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3035 __ delayed()->mov(G0, result_reg); // not equal | |
| 3036 | |
| 3037 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3038 __ delayed()->mov(G0, result_reg); // not equal | |
| 3039 | |
| 3040 //load the lengths of arrays | |
| 727 | 3041 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3042 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3043 |
| 3044 // return false if the two arrays are not equal length | |
| 3045 __ cmp(tmp1_reg, tmp2_reg); | |
| 3046 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3047 __ delayed()->mov(G0, result_reg); // not equal | |
| 3048 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3049 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
| 681 | 3050 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3051 | |
| 3052 // load array addresses | |
| 3053 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3054 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3055 | |
| 3056 // renaming registers | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3057 Register chr1_reg = result_reg; // for characters in ary1 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3058 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3059 Register limit_reg = tmp1_reg; // length |
| 3060 | |
| 3061 // set byte count | |
| 3062 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3063 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3064 // Compare char[] arrays aligned to 4 bytes. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3065 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3066 chr1_reg, chr2_reg, Ldone); |
| 681 | 3067 __ add(G0, 1, result_reg); // equals |
| 3068 | |
| 3069 __ bind(Ldone); | |
| 3070 %} | |
| 3071 | |
| 0 | 3072 enc_class enc_rethrow() %{ |
| 1748 | 3073 cbuf.set_insts_mark(); |
| 0 | 3074 Register temp_reg = G3; |
| 727 | 3075 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3076 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3077 MacroAssembler _masm(&cbuf); | |
| 3078 #ifdef ASSERT | |
| 3079 __ save_frame(0); | |
| 727 | 3080 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3081 __ sethi(last_rethrow_addrlit, L1); | |
| 3082 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3083 __ get_pc(L2); |
| 3084 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3085 __ st_ptr(L2, addr); |
| 0 | 3086 __ restore(); |
| 3087 #endif | |
| 727 | 3088 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3089 __ delayed()->nop(); |
| 3090 %} | |
| 3091 | |
| 3092 enc_class emit_mem_nop() %{ | |
| 3093 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3094 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3095 %} |
| 3096 | |
| 3097 enc_class emit_fadd_nop() %{ | |
| 3098 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3099 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3100 %} |
| 3101 | |
| 3102 enc_class emit_br_nop() %{ | |
| 3103 // Generates the instruction BPN,PN . | |
| 1748 | 3104 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3105 %} |
| 3106 | |
| 3107 enc_class enc_membar_acquire %{ | |
| 3108 MacroAssembler _masm(&cbuf); | |
| 3109 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3110 %} | |
| 3111 | |
| 3112 enc_class enc_membar_release %{ | |
| 3113 MacroAssembler _masm(&cbuf); | |
| 3114 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3115 %} | |
| 3116 | |
| 3117 enc_class enc_membar_volatile %{ | |
| 3118 MacroAssembler _masm(&cbuf); | |
| 3119 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3120 %} | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3121 |
| 0 | 3122 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3123 MacroAssembler _masm(&cbuf); | |
| 3124 Register src_reg = reg_to_register_object($src$$reg); | |
| 3125 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3126 __ sllx(src_reg, 56, dst_reg); | |
| 3127 __ srlx(dst_reg, 8, O7); | |
| 3128 __ or3 (dst_reg, O7, dst_reg); | |
| 3129 __ srlx(dst_reg, 16, O7); | |
| 3130 __ or3 (dst_reg, O7, dst_reg); | |
| 3131 __ srlx(dst_reg, 32, O7); | |
| 3132 __ or3 (dst_reg, O7, dst_reg); | |
| 3133 %} | |
| 3134 | |
| 3135 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3136 MacroAssembler _masm(&cbuf); | |
| 3137 Register src_reg = reg_to_register_object($src$$reg); | |
| 3138 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3139 __ sll(src_reg, 24, dst_reg); | |
| 3140 __ srl(dst_reg, 8, O7); | |
| 3141 __ or3(dst_reg, O7, dst_reg); | |
| 3142 __ srl(dst_reg, 16, O7); | |
| 3143 __ or3(dst_reg, O7, dst_reg); | |
| 3144 %} | |
| 3145 | |
| 3146 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3147 MacroAssembler _masm(&cbuf); | |
| 3148 Register src_reg = reg_to_register_object($src$$reg); | |
| 3149 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3150 __ sllx(src_reg, 48, dst_reg); | |
| 3151 __ srlx(dst_reg, 16, O7); | |
| 3152 __ or3 (dst_reg, O7, dst_reg); | |
| 3153 __ srlx(dst_reg, 32, O7); | |
| 3154 __ or3 (dst_reg, O7, dst_reg); | |
| 3155 %} | |
| 3156 | |
| 3157 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3158 MacroAssembler _masm(&cbuf); | |
| 3159 Register src_reg = reg_to_register_object($src$$reg); | |
| 3160 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3161 __ sllx(src_reg, 32, dst_reg); | |
| 3162 __ srlx(dst_reg, 32, O7); | |
| 3163 __ or3 (dst_reg, O7, dst_reg); | |
| 3164 %} | |
| 3165 | |
| 3166 %} | |
| 3167 | |
| 3168 //----------FRAME-------------------------------------------------------------- | |
| 3169 // Definition of frame structure and management information. | |
| 3170 // | |
| 3171 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3172 // | (to get allocators register number | |
| 3173 // G Owned by | | v add VMRegImpl::stack0) | |
| 3174 // r CALLER | | | |
| 3175 // o | +--------+ pad to even-align allocators stack-slot | |
| 3176 // w V | pad0 | numbers; owned by CALLER | |
| 3177 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3178 // h ^ | in | 5 | |
| 3179 // | | args | 4 Holes in incoming args owned by SELF | |
| 3180 // | | | | 3 | |
| 3181 // | | +--------+ | |
| 3182 // V | | old out| Empty on Intel, window on Sparc | |
| 3183 // | old |preserve| Must be even aligned. | |
| 3184 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3185 // | | in | 3 area for Intel ret address | |
| 3186 // Owned by |preserve| Empty on Sparc. | |
| 3187 // SELF +--------+ | |
| 3188 // | | pad2 | 2 pad to align old SP | |
| 3189 // | +--------+ 1 | |
| 3190 // | | locks | 0 | |
| 3191 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3192 // | | pad1 | 11 pad to align new SP | |
| 3193 // | +--------+ | |
| 3194 // | | | 10 | |
| 3195 // | | spills | 9 spills | |
| 3196 // V | | 8 (pad0 slot for callee) | |
| 3197 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3198 // ^ | out | 7 | |
| 3199 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3200 // Owned by +--------+ | |
| 3201 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3202 // | new |preserve| Must be even-aligned. | |
| 3203 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3204 // | | | | |
| 3205 // | |
| 3206 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3207 // known from SELF's arguments and the Java calling convention. | |
| 3208 // Region 6-7 is determined per call site. | |
| 3209 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3210 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3211 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3212 // incoming area, as the Java calling convention is completely under | |
| 3213 // the control of the AD file. Doubles can be sorted and packed to | |
| 3214 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3215 // varargs C calling conventions. | |
| 3216 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3217 // even aligned with pad0 as needed. | |
| 3218 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3219 // region 6-11 is even aligned; it may be padded out more so that | |
| 3220 // the region from SP to FP meets the minimum stack alignment. | |
| 3221 | |
| 3222 frame %{ | |
| 3223 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3224 stack_direction(TOWARDS_LOW); | |
| 3225 | |
| 3226 // These two registers define part of the calling convention | |
| 3227 // between compiled code and the interpreter. | |
| 3228 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3229 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3230 | |
| 3231 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3232 cisc_spilling_operand_name(indOffset); | |
| 3233 | |
| 3234 // Number of stack slots consumed by a Monitor enter | |
| 3235 #ifdef _LP64 | |
| 3236 sync_stack_slots(2); | |
| 3237 #else | |
| 3238 sync_stack_slots(1); | |
| 3239 #endif | |
| 3240 | |
| 3241 // Compiled code's Frame Pointer | |
| 3242 frame_pointer(R_SP); | |
| 3243 | |
| 3244 // Stack alignment requirement | |
| 3245 stack_alignment(StackAlignmentInBytes); | |
| 3246 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3247 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3248 | |
| 3249 // Number of stack slots between incoming argument block and the start of | |
| 3250 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3251 // EPILOG must remove this many slots. | |
| 3252 in_preserve_stack_slots(0); | |
| 3253 | |
| 3254 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3255 // for calls to C. Supports the var-args backing area for register parms. | |
| 3256 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3257 #ifdef _LP64 | |
| 3258 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3259 varargs_C_out_slots_killed(12); | |
| 3260 #else | |
| 3261 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3262 varargs_C_out_slots_killed( 7); | |
| 3263 #endif | |
| 3264 | |
| 3265 // The after-PROLOG location of the return address. Location of | |
| 3266 // return address specifies a type (REG or STACK) and a number | |
| 3267 // representing the register number (i.e. - use a register name) or | |
| 3268 // stack slot. | |
| 3269 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3270 | |
| 3271 // Body of function which returns an OptoRegs array locating | |
| 3272 // arguments either in registers or in stack slots for calling | |
| 3273 // java | |
| 3274 calling_convention %{ | |
| 3275 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3276 | |
| 3277 %} | |
| 3278 | |
| 3279 // Body of function which returns an OptoRegs array locating | |
| 3280 // arguments either in registers or in stack slots for callin | |
| 3281 // C. | |
| 3282 c_calling_convention %{ | |
| 3283 // This is obviously always outgoing | |
| 3284 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3285 %} | |
| 3286 | |
| 3287 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3288 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3289 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3290 // to and from the register pairs is done by the appropriate call and epilog | |
| 3291 // opcodes. This simplifies the register allocator. | |
| 3292 c_return_value %{ | |
| 3293 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3294 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3295 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3296 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3297 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3298 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3299 #else // !_LP64 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3300 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3301 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3302 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3303 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3304 #endif |
| 3305 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3306 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3307 %} | |
| 3308 | |
| 3309 // Location of compiled Java return values. Same as C | |
| 3310 return_value %{ | |
| 3311 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3312 #ifdef _LP64 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3313 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3314 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3315 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3316 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3317 #else // !_LP64 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3318 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3319 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3320 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3321 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3322 #endif |
| 3323 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3324 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3325 %} | |
| 3326 | |
| 3327 %} | |
| 3328 | |
| 3329 | |
| 3330 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3331 //----------Operand Attributes------------------------------------------------- | |
| 3332 op_attrib op_cost(1); // Required cost attribute | |
| 3333 | |
| 3334 //----------Instruction Attributes--------------------------------------------- | |
| 3335 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3336 ins_attrib ins_size(32); // Required size attribute (in bits) | |
| 3337 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 3338 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3339 // non-matching short branch variant of some | |
| 3340 // long branch? | |
| 3341 | |
| 3342 //----------OPERANDS----------------------------------------------------------- | |
| 3343 // Operand definitions must precede instruction definitions for correct parsing | |
| 3344 // in the ADLC because operands constitute user defined types which are used in | |
| 3345 // instruction definitions. | |
| 3346 | |
| 3347 //----------Simple Operands---------------------------------------------------- | |
| 3348 // Immediate Operands | |
| 3349 // Integer Immediate: 32-bit | |
| 3350 operand immI() %{ | |
| 3351 match(ConI); | |
| 3352 | |
| 3353 op_cost(0); | |
| 3354 // formats are generated automatically for constants and base registers | |
| 3355 format %{ %} | |
| 3356 interface(CONST_INTER); | |
| 3357 %} | |
| 3358 | |
| 824 | 3359 // Integer Immediate: 8-bit |
| 3360 operand immI8() %{ | |
| 3361 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 3362 match(ConI); | |
| 3363 op_cost(0); | |
| 3364 format %{ %} | |
| 3365 interface(CONST_INTER); | |
| 3366 %} | |
| 3367 | |
| 0 | 3368 // Integer Immediate: 13-bit |
| 3369 operand immI13() %{ | |
| 3370 predicate(Assembler::is_simm13(n->get_int())); | |
| 3371 match(ConI); | |
| 3372 op_cost(0); | |
| 3373 | |
| 3374 format %{ %} | |
| 3375 interface(CONST_INTER); | |
| 3376 %} | |
| 3377 | |
| 785 | 3378 // Integer Immediate: 13-bit minus 7 |
| 3379 operand immI13m7() %{ | |
| 3380 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3381 match(ConI); | |
| 3382 op_cost(0); | |
| 3383 | |
| 3384 format %{ %} | |
| 3385 interface(CONST_INTER); | |
| 3386 %} | |
| 3387 | |
| 824 | 3388 // Integer Immediate: 16-bit |
| 3389 operand immI16() %{ | |
| 3390 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 3391 match(ConI); | |
| 3392 op_cost(0); | |
| 3393 format %{ %} | |
| 3394 interface(CONST_INTER); | |
| 3395 %} | |
| 3396 | |
| 0 | 3397 // Unsigned (positive) Integer Immediate: 13-bit |
| 3398 operand immU13() %{ | |
| 3399 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3400 match(ConI); | |
| 3401 op_cost(0); | |
| 3402 | |
| 3403 format %{ %} | |
| 3404 interface(CONST_INTER); | |
| 3405 %} | |
| 3406 | |
| 3407 // Integer Immediate: 6-bit | |
| 3408 operand immU6() %{ | |
| 3409 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3410 match(ConI); | |
| 3411 op_cost(0); | |
| 3412 format %{ %} | |
| 3413 interface(CONST_INTER); | |
| 3414 %} | |
| 3415 | |
| 3416 // Integer Immediate: 11-bit | |
| 3417 operand immI11() %{ | |
| 3418 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3419 match(ConI); | |
| 3420 op_cost(0); | |
| 3421 format %{ %} | |
| 3422 interface(CONST_INTER); | |
| 3423 %} | |
| 3424 | |
| 3425 // Integer Immediate: 0-bit | |
| 3426 operand immI0() %{ | |
| 3427 predicate(n->get_int() == 0); | |
| 3428 match(ConI); | |
| 3429 op_cost(0); | |
| 3430 | |
| 3431 format %{ %} | |
| 3432 interface(CONST_INTER); | |
| 3433 %} | |
| 3434 | |
| 3435 // Integer Immediate: the value 10 | |
| 3436 operand immI10() %{ | |
| 3437 predicate(n->get_int() == 10); | |
| 3438 match(ConI); | |
| 3439 op_cost(0); | |
| 3440 | |
| 3441 format %{ %} | |
| 3442 interface(CONST_INTER); | |
| 3443 %} | |
| 3444 | |
| 3445 // Integer Immediate: the values 0-31 | |
| 3446 operand immU5() %{ | |
| 3447 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3448 match(ConI); | |
| 3449 op_cost(0); | |
| 3450 | |
| 3451 format %{ %} | |
| 3452 interface(CONST_INTER); | |
| 3453 %} | |
| 3454 | |
| 3455 // Integer Immediate: the values 1-31 | |
| 3456 operand immI_1_31() %{ | |
| 3457 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3458 match(ConI); | |
| 3459 op_cost(0); | |
| 3460 | |
| 3461 format %{ %} | |
| 3462 interface(CONST_INTER); | |
| 3463 %} | |
| 3464 | |
| 3465 // Integer Immediate: the values 32-63 | |
| 3466 operand immI_32_63() %{ | |
| 3467 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3468 match(ConI); | |
| 3469 op_cost(0); | |
| 3470 | |
| 3471 format %{ %} | |
| 3472 interface(CONST_INTER); | |
| 3473 %} | |
| 3474 | |
| 785 | 3475 // Immediates for special shifts (sign extend) |
| 3476 | |
| 3477 // Integer Immediate: the value 16 | |
| 3478 operand immI_16() %{ | |
| 3479 predicate(n->get_int() == 16); | |
| 3480 match(ConI); | |
| 3481 op_cost(0); | |
| 3482 | |
| 3483 format %{ %} | |
| 3484 interface(CONST_INTER); | |
| 3485 %} | |
| 3486 | |
| 3487 // Integer Immediate: the value 24 | |
| 3488 operand immI_24() %{ | |
| 3489 predicate(n->get_int() == 24); | |
| 3490 match(ConI); | |
| 3491 op_cost(0); | |
| 3492 | |
| 3493 format %{ %} | |
| 3494 interface(CONST_INTER); | |
| 3495 %} | |
| 3496 | |
| 0 | 3497 // Integer Immediate: the value 255 |
| 3498 operand immI_255() %{ | |
| 3499 predicate( n->get_int() == 255 ); | |
| 3500 match(ConI); | |
| 3501 op_cost(0); | |
| 3502 | |
| 3503 format %{ %} | |
| 3504 interface(CONST_INTER); | |
| 3505 %} | |
| 3506 | |
| 785 | 3507 // Integer Immediate: the value 65535 |
| 3508 operand immI_65535() %{ | |
| 3509 predicate(n->get_int() == 65535); | |
| 3510 match(ConI); | |
| 3511 op_cost(0); | |
| 3512 | |
| 3513 format %{ %} | |
| 3514 interface(CONST_INTER); | |
| 3515 %} | |
| 3516 | |
| 0 | 3517 // Long Immediate: the value FF |
| 3518 operand immL_FF() %{ | |
| 3519 predicate( n->get_long() == 0xFFL ); | |
| 3520 match(ConL); | |
| 3521 op_cost(0); | |
| 3522 | |
| 3523 format %{ %} | |
| 3524 interface(CONST_INTER); | |
| 3525 %} | |
| 3526 | |
| 3527 // Long Immediate: the value FFFF | |
| 3528 operand immL_FFFF() %{ | |
| 3529 predicate( n->get_long() == 0xFFFFL ); | |
| 3530 match(ConL); | |
| 3531 op_cost(0); | |
| 3532 | |
| 3533 format %{ %} | |
| 3534 interface(CONST_INTER); | |
| 3535 %} | |
| 3536 | |
| 3537 // Pointer Immediate: 32 or 64-bit | |
| 3538 operand immP() %{ | |
| 3539 match(ConP); | |
| 3540 | |
| 3541 op_cost(5); | |
| 3542 // formats are generated automatically for constants and base registers | |
| 3543 format %{ %} | |
| 3544 interface(CONST_INTER); | |
| 3545 %} | |
| 3546 | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3547 #ifdef _LP64 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3548 // Pointer Immediate: 64-bit |
| 2008 | 3549 operand immP_set() %{ |
| 2080 | 3550 predicate(!VM_Version::is_niagara_plus()); |
| 2008 | 3551 match(ConP); |
| 3552 | |
| 3553 op_cost(5); | |
| 3554 // formats are generated automatically for constants and base registers | |
| 3555 format %{ %} | |
| 3556 interface(CONST_INTER); | |
| 3557 %} | |
| 3558 | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3559 // Pointer Immediate: 64-bit |
| 2008 | 3560 // From Niagara2 processors on a load should be better than materializing. |
| 3561 operand immP_load() %{ | |
| 2080 | 3562 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
| 2008 | 3563 match(ConP); |
| 3564 | |
| 3565 op_cost(5); | |
| 3566 // formats are generated automatically for constants and base registers | |
| 3567 format %{ %} | |
| 3568 interface(CONST_INTER); | |
| 3569 %} | |
| 3570 | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3571 // Pointer Immediate: 64-bit |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3572 operand immP_no_oop_cheap() %{ |
| 2080 | 3573 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3574 match(ConP); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3575 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3576 op_cost(5); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3577 // formats are generated automatically for constants and base registers |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3578 format %{ %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3579 interface(CONST_INTER); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3580 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3581 #endif |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3582 |
| 0 | 3583 operand immP13() %{ |
| 3584 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3585 match(ConP); | |
| 3586 op_cost(0); | |
| 3587 | |
| 3588 format %{ %} | |
| 3589 interface(CONST_INTER); | |
| 3590 %} | |
| 3591 | |
| 3592 operand immP0() %{ | |
| 3593 predicate(n->get_ptr() == 0); | |
| 3594 match(ConP); | |
| 3595 op_cost(0); | |
| 3596 | |
| 3597 format %{ %} | |
| 3598 interface(CONST_INTER); | |
| 3599 %} | |
| 3600 | |
| 3601 operand immP_poll() %{ | |
| 3602 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3603 match(ConP); | |
| 3604 | |
| 3605 // formats are generated automatically for constants and base registers | |
| 3606 format %{ %} | |
| 3607 interface(CONST_INTER); | |
| 3608 %} | |
| 3609 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3610 // Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3611 operand immN() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3612 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3613 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3614 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3615 op_cost(10); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3616 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3617 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3618 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3619 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3620 // NULL Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3621 operand immN0() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3622 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3623 predicate(n->get_narrowcon() == 0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3624 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3625 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3626 op_cost(0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3627 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3628 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3629 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3630 |
| 0 | 3631 operand immL() %{ |
| 3632 match(ConL); | |
| 3633 op_cost(40); | |
| 3634 // formats are generated automatically for constants and base registers | |
| 3635 format %{ %} | |
| 3636 interface(CONST_INTER); | |
| 3637 %} | |
| 3638 | |
| 3639 operand immL0() %{ | |
| 3640 predicate(n->get_long() == 0L); | |
| 3641 match(ConL); | |
| 3642 op_cost(0); | |
| 3643 // formats are generated automatically for constants and base registers | |
| 3644 format %{ %} | |
| 3645 interface(CONST_INTER); | |
| 3646 %} | |
| 3647 | |
| 3648 // Long Immediate: 13-bit | |
| 3649 operand immL13() %{ | |
| 3650 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3651 match(ConL); | |
| 3652 op_cost(0); | |
| 3653 | |
| 3654 format %{ %} | |
| 3655 interface(CONST_INTER); | |
| 3656 %} | |
| 3657 | |
| 785 | 3658 // Long Immediate: 13-bit minus 7 |
| 3659 operand immL13m7() %{ | |
| 3660 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3661 match(ConL); | |
| 3662 op_cost(0); | |
| 3663 | |
| 3664 format %{ %} | |
| 3665 interface(CONST_INTER); | |
| 3666 %} | |
| 3667 | |
| 0 | 3668 // Long Immediate: low 32-bit mask |
| 3669 operand immL_32bits() %{ | |
| 3670 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3671 match(ConL); | |
| 3672 op_cost(0); | |
| 3673 | |
| 3674 format %{ %} | |
| 3675 interface(CONST_INTER); | |
| 3676 %} | |
| 3677 | |
| 2008 | 3678 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3679 operand immL_cheap() %{ | |
| 2080 | 3680 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
| 2008 | 3681 match(ConL); |
| 3682 op_cost(0); | |
| 3683 | |
| 3684 format %{ %} | |
| 3685 interface(CONST_INTER); | |
| 3686 %} | |
| 3687 | |
| 3688 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3689 operand immL_expensive() %{ | |
| 2080 | 3690 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
| 2008 | 3691 match(ConL); |
| 3692 op_cost(0); | |
| 3693 | |
| 3694 format %{ %} | |
| 3695 interface(CONST_INTER); | |
| 3696 %} | |
| 3697 | |
| 0 | 3698 // Double Immediate |
| 3699 operand immD() %{ | |
| 3700 match(ConD); | |
| 3701 | |
| 3702 op_cost(40); | |
| 3703 format %{ %} | |
| 3704 interface(CONST_INTER); | |
| 3705 %} | |
| 3706 | |
| 3707 operand immD0() %{ | |
| 3708 #ifdef _LP64 | |
| 3709 // on 64-bit architectures this comparision is faster | |
| 3710 predicate(jlong_cast(n->getd()) == 0); | |
| 3711 #else | |
| 3712 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3713 #endif | |
| 3714 match(ConD); | |
| 3715 | |
| 3716 op_cost(0); | |
| 3717 format %{ %} | |
| 3718 interface(CONST_INTER); | |
| 3719 %} | |
| 3720 | |
| 3721 // Float Immediate | |
| 3722 operand immF() %{ | |
| 3723 match(ConF); | |
| 3724 | |
| 3725 op_cost(20); | |
| 3726 format %{ %} | |
| 3727 interface(CONST_INTER); | |
| 3728 %} | |
| 3729 | |
| 3730 // Float Immediate: 0 | |
| 3731 operand immF0() %{ | |
| 3732 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3733 match(ConF); | |
| 3734 | |
| 3735 op_cost(0); | |
| 3736 format %{ %} | |
| 3737 interface(CONST_INTER); | |
| 3738 %} | |
| 3739 | |
| 3740 // Integer Register Operands | |
| 3741 // Integer Register | |
| 3742 operand iRegI() %{ | |
| 3743 constraint(ALLOC_IN_RC(int_reg)); | |
| 3744 match(RegI); | |
| 3745 | |
| 3746 match(notemp_iRegI); | |
| 3747 match(g1RegI); | |
| 3748 match(o0RegI); | |
| 3749 match(iRegIsafe); | |
| 3750 | |
| 3751 format %{ %} | |
| 3752 interface(REG_INTER); | |
| 3753 %} | |
| 3754 | |
| 3755 operand notemp_iRegI() %{ | |
| 3756 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3757 match(RegI); | |
| 3758 | |
| 3759 match(o0RegI); | |
| 3760 | |
| 3761 format %{ %} | |
| 3762 interface(REG_INTER); | |
| 3763 %} | |
| 3764 | |
| 3765 operand o0RegI() %{ | |
| 3766 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3767 match(iRegI); | |
| 3768 | |
| 3769 format %{ %} | |
| 3770 interface(REG_INTER); | |
| 3771 %} | |
| 3772 | |
| 3773 // Pointer Register | |
| 3774 operand iRegP() %{ | |
| 3775 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3776 match(RegP); | |
| 3777 | |
| 3778 match(lock_ptr_RegP); | |
| 3779 match(g1RegP); | |
| 3780 match(g2RegP); | |
| 3781 match(g3RegP); | |
| 3782 match(g4RegP); | |
| 3783 match(i0RegP); | |
| 3784 match(o0RegP); | |
| 3785 match(o1RegP); | |
| 3786 match(l7RegP); | |
| 3787 | |
| 3788 format %{ %} | |
| 3789 interface(REG_INTER); | |
| 3790 %} | |
| 3791 | |
| 3792 operand sp_ptr_RegP() %{ | |
| 3793 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3794 match(RegP); | |
| 3795 match(iRegP); | |
| 3796 | |
| 3797 format %{ %} | |
| 3798 interface(REG_INTER); | |
| 3799 %} | |
| 3800 | |
| 3801 operand lock_ptr_RegP() %{ | |
| 3802 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3803 match(RegP); | |
| 3804 match(i0RegP); | |
| 3805 match(o0RegP); | |
| 3806 match(o1RegP); | |
| 3807 match(l7RegP); | |
| 3808 | |
| 3809 format %{ %} | |
| 3810 interface(REG_INTER); | |
| 3811 %} | |
| 3812 | |
| 3813 operand g1RegP() %{ | |
| 3814 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3815 match(iRegP); | |
| 3816 | |
| 3817 format %{ %} | |
| 3818 interface(REG_INTER); | |
| 3819 %} | |
| 3820 | |
| 3821 operand g2RegP() %{ | |
| 3822 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3823 match(iRegP); | |
| 3824 | |
| 3825 format %{ %} | |
| 3826 interface(REG_INTER); | |
| 3827 %} | |
| 3828 | |
| 3829 operand g3RegP() %{ | |
| 3830 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3831 match(iRegP); | |
| 3832 | |
| 3833 format %{ %} | |
| 3834 interface(REG_INTER); | |
| 3835 %} | |
| 3836 | |
| 3837 operand g1RegI() %{ | |
| 3838 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3839 match(iRegI); | |
| 3840 | |
| 3841 format %{ %} | |
| 3842 interface(REG_INTER); | |
| 3843 %} | |
| 3844 | |
| 3845 operand g3RegI() %{ | |
| 3846 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3847 match(iRegI); | |
| 3848 | |
| 3849 format %{ %} | |
| 3850 interface(REG_INTER); | |
| 3851 %} | |
| 3852 | |
| 3853 operand g4RegI() %{ | |
| 3854 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3855 match(iRegI); | |
| 3856 | |
| 3857 format %{ %} | |
| 3858 interface(REG_INTER); | |
| 3859 %} | |
| 3860 | |
| 3861 operand g4RegP() %{ | |
| 3862 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3863 match(iRegP); | |
| 3864 | |
| 3865 format %{ %} | |
| 3866 interface(REG_INTER); | |
| 3867 %} | |
| 3868 | |
| 3869 operand i0RegP() %{ | |
| 3870 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3871 match(iRegP); | |
| 3872 | |
| 3873 format %{ %} | |
| 3874 interface(REG_INTER); | |
| 3875 %} | |
| 3876 | |
| 3877 operand o0RegP() %{ | |
| 3878 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3879 match(iRegP); | |
| 3880 | |
| 3881 format %{ %} | |
| 3882 interface(REG_INTER); | |
| 3883 %} | |
| 3884 | |
| 3885 operand o1RegP() %{ | |
| 3886 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3887 match(iRegP); | |
| 3888 | |
| 3889 format %{ %} | |
| 3890 interface(REG_INTER); | |
| 3891 %} | |
| 3892 | |
| 3893 operand o2RegP() %{ | |
| 3894 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3895 match(iRegP); | |
| 3896 | |
| 3897 format %{ %} | |
| 3898 interface(REG_INTER); | |
| 3899 %} | |
| 3900 | |
| 3901 operand o7RegP() %{ | |
| 3902 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3903 match(iRegP); | |
| 3904 | |
| 3905 format %{ %} | |
| 3906 interface(REG_INTER); | |
| 3907 %} | |
| 3908 | |
| 3909 operand l7RegP() %{ | |
| 3910 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3911 match(iRegP); | |
| 3912 | |
| 3913 format %{ %} | |
| 3914 interface(REG_INTER); | |
| 3915 %} | |
| 3916 | |
| 3917 operand o7RegI() %{ | |
| 3918 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3919 match(iRegI); | |
| 3920 | |
| 3921 format %{ %} | |
| 3922 interface(REG_INTER); | |
| 3923 %} | |
| 3924 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3925 operand iRegN() %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3926 constraint(ALLOC_IN_RC(int_reg)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3927 match(RegN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3928 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3929 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3930 interface(REG_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3931 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3932 |
| 0 | 3933 // Long Register |
| 3934 operand iRegL() %{ | |
| 3935 constraint(ALLOC_IN_RC(long_reg)); | |
| 3936 match(RegL); | |
| 3937 | |
| 3938 format %{ %} | |
| 3939 interface(REG_INTER); | |
| 3940 %} | |
| 3941 | |
| 3942 operand o2RegL() %{ | |
| 3943 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3944 match(iRegL); | |
| 3945 | |
| 3946 format %{ %} | |
| 3947 interface(REG_INTER); | |
| 3948 %} | |
| 3949 | |
| 3950 operand o7RegL() %{ | |
| 3951 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3952 match(iRegL); | |
| 3953 | |
| 3954 format %{ %} | |
| 3955 interface(REG_INTER); | |
| 3956 %} | |
| 3957 | |
| 3958 operand g1RegL() %{ | |
| 3959 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3960 match(iRegL); | |
| 3961 | |
| 3962 format %{ %} | |
| 3963 interface(REG_INTER); | |
| 3964 %} | |
| 3965 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3966 operand g3RegL() %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3967 constraint(ALLOC_IN_RC(g3_regL)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3968 match(iRegL); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3969 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3970 format %{ %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3971 interface(REG_INTER); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3972 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3973 |
| 0 | 3974 // Int Register safe |
| 3975 // This is 64bit safe | |
| 3976 operand iRegIsafe() %{ | |
| 3977 constraint(ALLOC_IN_RC(long_reg)); | |
| 3978 | |
| 3979 match(iRegI); | |
| 3980 | |
| 3981 format %{ %} | |
| 3982 interface(REG_INTER); | |
| 3983 %} | |
| 3984 | |
| 3985 // Condition Code Flag Register | |
| 3986 operand flagsReg() %{ | |
| 3987 constraint(ALLOC_IN_RC(int_flags)); | |
| 3988 match(RegFlags); | |
| 3989 | |
| 3990 format %{ "ccr" %} // both ICC and XCC | |
| 3991 interface(REG_INTER); | |
| 3992 %} | |
| 3993 | |
| 3994 // Condition Code Register, unsigned comparisons. | |
| 3995 operand flagsRegU() %{ | |
| 3996 constraint(ALLOC_IN_RC(int_flags)); | |
| 3997 match(RegFlags); | |
| 3998 | |
| 3999 format %{ "icc_U" %} | |
| 4000 interface(REG_INTER); | |
| 4001 %} | |
| 4002 | |
| 4003 // Condition Code Register, pointer comparisons. | |
| 4004 operand flagsRegP() %{ | |
| 4005 constraint(ALLOC_IN_RC(int_flags)); | |
| 4006 match(RegFlags); | |
| 4007 | |
| 4008 #ifdef _LP64 | |
| 4009 format %{ "xcc_P" %} | |
| 4010 #else | |
| 4011 format %{ "icc_P" %} | |
| 4012 #endif | |
| 4013 interface(REG_INTER); | |
| 4014 %} | |
| 4015 | |
| 4016 // Condition Code Register, long comparisons. | |
| 4017 operand flagsRegL() %{ | |
| 4018 constraint(ALLOC_IN_RC(int_flags)); | |
| 4019 match(RegFlags); | |
| 4020 | |
| 4021 format %{ "xcc_L" %} | |
| 4022 interface(REG_INTER); | |
| 4023 %} | |
| 4024 | |
| 4025 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4026 operand flagsRegF() %{ | |
| 4027 constraint(ALLOC_IN_RC(float_flags)); | |
| 4028 match(RegFlags); | |
| 4029 match(flagsRegF0); | |
| 4030 | |
| 4031 format %{ %} | |
| 4032 interface(REG_INTER); | |
| 4033 %} | |
| 4034 | |
| 4035 operand flagsRegF0() %{ | |
| 4036 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4037 match(RegFlags); | |
| 4038 | |
| 4039 format %{ %} | |
| 4040 interface(REG_INTER); | |
| 4041 %} | |
| 4042 | |
| 4043 | |
| 4044 // Condition Code Flag Register used by long compare | |
| 4045 operand flagsReg_long_LTGE() %{ | |
| 4046 constraint(ALLOC_IN_RC(int_flags)); | |
| 4047 match(RegFlags); | |
| 4048 format %{ "icc_LTGE" %} | |
| 4049 interface(REG_INTER); | |
| 4050 %} | |
| 4051 operand flagsReg_long_EQNE() %{ | |
| 4052 constraint(ALLOC_IN_RC(int_flags)); | |
| 4053 match(RegFlags); | |
| 4054 format %{ "icc_EQNE" %} | |
| 4055 interface(REG_INTER); | |
| 4056 %} | |
| 4057 operand flagsReg_long_LEGT() %{ | |
| 4058 constraint(ALLOC_IN_RC(int_flags)); | |
| 4059 match(RegFlags); | |
| 4060 format %{ "icc_LEGT" %} | |
| 4061 interface(REG_INTER); | |
| 4062 %} | |
| 4063 | |
| 4064 | |
| 4065 operand regD() %{ | |
| 4066 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4067 match(RegD); | |
| 4068 | |
| 551 | 4069 match(regD_low); |
| 4070 | |
| 0 | 4071 format %{ %} |
| 4072 interface(REG_INTER); | |
| 4073 %} | |
| 4074 | |
| 4075 operand regF() %{ | |
| 4076 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4077 match(RegF); | |
| 4078 | |
| 4079 format %{ %} | |
| 4080 interface(REG_INTER); | |
| 4081 %} | |
| 4082 | |
| 4083 operand regD_low() %{ | |
| 4084 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4085 match(regD); |
| 0 | 4086 |
| 4087 format %{ %} | |
| 4088 interface(REG_INTER); | |
| 4089 %} | |
| 4090 | |
| 4091 // Special Registers | |
| 4092 | |
| 4093 // Method Register | |
| 4094 operand inline_cache_regP(iRegP reg) %{ | |
| 4095 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4096 match(reg); | |
| 4097 format %{ %} | |
| 4098 interface(REG_INTER); | |
| 4099 %} | |
| 4100 | |
| 4101 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4102 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4103 match(reg); | |
| 4104 format %{ %} | |
| 4105 interface(REG_INTER); | |
| 4106 %} | |
| 4107 | |
| 4108 | |
| 4109 //----------Complex Operands--------------------------------------------------- | |
| 4110 // Indirect Memory Reference | |
| 4111 operand indirect(sp_ptr_RegP reg) %{ | |
| 4112 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4113 match(reg); | |
| 4114 | |
| 4115 op_cost(100); | |
| 4116 format %{ "[$reg]" %} | |
| 4117 interface(MEMORY_INTER) %{ | |
| 4118 base($reg); | |
| 4119 index(0x0); | |
| 4120 scale(0x0); | |
| 4121 disp(0x0); | |
| 4122 %} | |
| 4123 %} | |
| 4124 | |
| 785 | 4125 // Indirect with simm13 Offset |
| 0 | 4126 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4127 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4128 match(AddP reg offset); | |
| 4129 | |
| 4130 op_cost(100); | |
| 4131 format %{ "[$reg + $offset]" %} | |
| 4132 interface(MEMORY_INTER) %{ | |
| 4133 base($reg); | |
| 4134 index(0x0); | |
| 4135 scale(0x0); | |
| 4136 disp($offset); | |
| 4137 %} | |
| 4138 %} | |
| 4139 | |
| 785 | 4140 // Indirect with simm13 Offset minus 7 |
| 4141 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4142 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4143 match(AddP reg offset); | |
| 4144 | |
| 4145 op_cost(100); | |
| 4146 format %{ "[$reg + $offset]" %} | |
| 4147 interface(MEMORY_INTER) %{ | |
| 4148 base($reg); | |
| 4149 index(0x0); | |
| 4150 scale(0x0); | |
| 4151 disp($offset); | |
| 4152 %} | |
| 4153 %} | |
| 4154 | |
| 0 | 4155 // Note: Intel has a swapped version also, like this: |
| 4156 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4157 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4158 // match(AddP offset reg); | |
| 4159 // | |
| 4160 // op_cost(100); | |
| 4161 // format %{ "[$reg + $offset]" %} | |
| 4162 // interface(MEMORY_INTER) %{ | |
| 4163 // base($reg); | |
| 4164 // index(0x0); | |
| 4165 // scale(0x0); | |
| 4166 // disp($offset); | |
| 4167 // %} | |
| 4168 //%} | |
| 4169 //// However, it doesn't make sense for SPARC, since | |
| 4170 // we have no particularly good way to embed oops in | |
| 4171 // single instructions. | |
| 4172 | |
| 4173 // Indirect with Register Index | |
| 4174 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4175 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4176 match(AddP addr index); | |
| 4177 | |
| 4178 op_cost(100); | |
| 4179 format %{ "[$addr + $index]" %} | |
| 4180 interface(MEMORY_INTER) %{ | |
| 4181 base($addr); | |
| 4182 index($index); | |
| 4183 scale(0x0); | |
| 4184 disp(0x0); | |
| 4185 %} | |
| 4186 %} | |
| 4187 | |
| 4188 //----------Special Memory Operands-------------------------------------------- | |
| 4189 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4190 // values on the stack where a match requires a value to | |
| 4191 // flow through memory. | |
| 4192 operand stackSlotI(sRegI reg) %{ | |
| 4193 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4194 op_cost(100); | |
| 4195 //match(RegI); | |
| 4196 format %{ "[$reg]" %} | |
| 4197 interface(MEMORY_INTER) %{ | |
| 4198 base(0xE); // R_SP | |
| 4199 index(0x0); | |
| 4200 scale(0x0); | |
| 4201 disp($reg); // Stack Offset | |
| 4202 %} | |
| 4203 %} | |
| 4204 | |
| 4205 operand stackSlotP(sRegP reg) %{ | |
| 4206 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4207 op_cost(100); | |
| 4208 //match(RegP); | |
| 4209 format %{ "[$reg]" %} | |
| 4210 interface(MEMORY_INTER) %{ | |
| 4211 base(0xE); // R_SP | |
| 4212 index(0x0); | |
| 4213 scale(0x0); | |
| 4214 disp($reg); // Stack Offset | |
| 4215 %} | |
| 4216 %} | |
| 4217 | |
| 4218 operand stackSlotF(sRegF reg) %{ | |
| 4219 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4220 op_cost(100); | |
| 4221 //match(RegF); | |
| 4222 format %{ "[$reg]" %} | |
| 4223 interface(MEMORY_INTER) %{ | |
| 4224 base(0xE); // R_SP | |
| 4225 index(0x0); | |
| 4226 scale(0x0); | |
| 4227 disp($reg); // Stack Offset | |
| 4228 %} | |
| 4229 %} | |
| 4230 operand stackSlotD(sRegD reg) %{ | |
| 4231 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4232 op_cost(100); | |
| 4233 //match(RegD); | |
| 4234 format %{ "[$reg]" %} | |
| 4235 interface(MEMORY_INTER) %{ | |
| 4236 base(0xE); // R_SP | |
| 4237 index(0x0); | |
| 4238 scale(0x0); | |
| 4239 disp($reg); // Stack Offset | |
| 4240 %} | |
| 4241 %} | |
| 4242 operand stackSlotL(sRegL reg) %{ | |
| 4243 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4244 op_cost(100); | |
| 4245 //match(RegL); | |
| 4246 format %{ "[$reg]" %} | |
| 4247 interface(MEMORY_INTER) %{ | |
| 4248 base(0xE); // R_SP | |
| 4249 index(0x0); | |
| 4250 scale(0x0); | |
| 4251 disp($reg); // Stack Offset | |
| 4252 %} | |
| 4253 %} | |
| 4254 | |
| 4255 // Operands for expressing Control Flow | |
| 4256 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4257 // the AD file. It is generically handled within the ADLC. | |
| 4258 | |
| 4259 //----------Conditional Branch Operands---------------------------------------- | |
| 4260 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4261 // the following set of codes: | |
| 4262 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4263 // | |
| 4264 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4265 // by the comparison instruction that sets a condition code flags register. | |
| 4266 // That result is represented by a flags operand whose subtype is appropriate | |
| 4267 // to the unsignedness (etc.) of the comparison. | |
| 4268 // | |
| 4269 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4270 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4271 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4272 | |
| 4273 operand cmpOp() %{ | |
| 4274 match(Bool); | |
| 4275 | |
| 4276 format %{ "" %} | |
| 4277 interface(COND_INTER) %{ | |
| 4278 equal(0x1); | |
| 4279 not_equal(0x9); | |
| 4280 less(0x3); | |
| 4281 greater_equal(0xB); | |
| 4282 less_equal(0x2); | |
| 4283 greater(0xA); | |
| 4284 %} | |
| 4285 %} | |
| 4286 | |
| 4287 // Comparison Op, unsigned | |
| 4288 operand cmpOpU() %{ | |
| 4289 match(Bool); | |
| 4290 | |
| 4291 format %{ "u" %} | |
| 4292 interface(COND_INTER) %{ | |
| 4293 equal(0x1); | |
| 4294 not_equal(0x9); | |
| 4295 less(0x5); | |
| 4296 greater_equal(0xD); | |
| 4297 less_equal(0x4); | |
| 4298 greater(0xC); | |
| 4299 %} | |
| 4300 %} | |
| 4301 | |
| 4302 // Comparison Op, pointer (same as unsigned) | |
| 4303 operand cmpOpP() %{ | |
| 4304 match(Bool); | |
| 4305 | |
| 4306 format %{ "p" %} | |
| 4307 interface(COND_INTER) %{ | |
| 4308 equal(0x1); | |
| 4309 not_equal(0x9); | |
| 4310 less(0x5); | |
| 4311 greater_equal(0xD); | |
| 4312 less_equal(0x4); | |
| 4313 greater(0xC); | |
| 4314 %} | |
| 4315 %} | |
| 4316 | |
| 4317 // Comparison Op, branch-register encoding | |
| 4318 operand cmpOp_reg() %{ | |
| 4319 match(Bool); | |
| 4320 | |
| 4321 format %{ "" %} | |
| 4322 interface(COND_INTER) %{ | |
| 4323 equal (0x1); | |
| 4324 not_equal (0x5); | |
| 4325 less (0x3); | |
| 4326 greater_equal(0x7); | |
| 4327 less_equal (0x2); | |
| 4328 greater (0x6); | |
| 4329 %} | |
| 4330 %} | |
| 4331 | |
| 4332 // Comparison Code, floating, unordered same as less | |
| 4333 operand cmpOpF() %{ | |
| 4334 match(Bool); | |
| 4335 | |
| 4336 format %{ "fl" %} | |
| 4337 interface(COND_INTER) %{ | |
| 4338 equal(0x9); | |
| 4339 not_equal(0x1); | |
| 4340 less(0x3); | |
| 4341 greater_equal(0xB); | |
| 4342 less_equal(0xE); | |
| 4343 greater(0x6); | |
| 4344 %} | |
| 4345 %} | |
| 4346 | |
| 4347 // Used by long compare | |
| 4348 operand cmpOp_commute() %{ | |
| 4349 match(Bool); | |
| 4350 | |
| 4351 format %{ "" %} | |
| 4352 interface(COND_INTER) %{ | |
| 4353 equal(0x1); | |
| 4354 not_equal(0x9); | |
| 4355 less(0xA); | |
| 4356 greater_equal(0x2); | |
| 4357 less_equal(0xB); | |
| 4358 greater(0x3); | |
| 4359 %} | |
| 4360 %} | |
| 4361 | |
| 4362 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4363 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4364 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4365 // instructions for every form of operand when the instruction accepts |
| 4366 // multiple operand types with the same basic encoding and format. The classic | |
| 4367 // case of this is memory operands. | |
| 4368 opclass memory( indirect, indOffset13, indIndex ); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
4369 opclass indIndexMemory( indIndex ); |
| 0 | 4370 |
| 4371 //----------PIPELINE----------------------------------------------------------- | |
| 4372 pipeline %{ | |
| 4373 | |
| 4374 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4375 attributes %{ | |
| 4376 fixed_size_instructions; // Fixed size instructions | |
| 4377 branch_has_delay_slot; // Branch has delay slot following | |
| 4378 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4379 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4380 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4381 instruction_fetch_units = 1; // of 16 bytes | |
| 4382 | |
| 4383 // List of nop instructions | |
| 4384 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4385 %} | |
| 4386 | |
| 4387 //----------RESOURCES---------------------------------------------------------- | |
| 4388 // Resources are the functional units available to the machine | |
| 4389 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4390 | |
| 4391 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4392 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4393 | |
| 4394 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4395 | |
| 4396 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4397 // Pipeline Classes describe the stages in which input and output are | |
| 4398 // referenced by the hardware pipeline. | |
| 4399 | |
| 4400 // Integer ALU reg-reg operation | |
| 4401 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4402 single_instruction; | |
| 4403 dst : E(write); | |
| 4404 src1 : R(read); | |
| 4405 src2 : R(read); | |
| 4406 IALU : R; | |
| 4407 %} | |
| 4408 | |
| 4409 // Integer ALU reg-reg long operation | |
| 4410 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4411 instruction_count(2); | |
| 4412 dst : E(write); | |
| 4413 src1 : R(read); | |
| 4414 src2 : R(read); | |
| 4415 IALU : R; | |
| 4416 IALU : R; | |
| 4417 %} | |
| 4418 | |
| 4419 // Integer ALU reg-reg long dependent operation | |
| 4420 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4421 instruction_count(1); multiple_bundles; | |
| 4422 dst : E(write); | |
| 4423 src1 : R(read); | |
| 4424 src2 : R(read); | |
| 4425 cr : E(write); | |
| 4426 IALU : R(2); | |
| 4427 %} | |
| 4428 | |
| 4429 // Integer ALU reg-imm operaion | |
| 4430 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4431 single_instruction; | |
| 4432 dst : E(write); | |
| 4433 src1 : R(read); | |
| 4434 IALU : R; | |
| 4435 %} | |
| 4436 | |
| 4437 // Integer ALU reg-reg operation with condition code | |
| 4438 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4439 single_instruction; | |
| 4440 dst : E(write); | |
| 4441 cr : E(write); | |
| 4442 src1 : R(read); | |
| 4443 src2 : R(read); | |
| 4444 IALU : R; | |
| 4445 %} | |
| 4446 | |
| 4447 // Integer ALU reg-imm operation with condition code | |
| 4448 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4449 single_instruction; | |
| 4450 dst : E(write); | |
| 4451 cr : E(write); | |
| 4452 src1 : R(read); | |
| 4453 IALU : R; | |
| 4454 %} | |
| 4455 | |
| 4456 // Integer ALU zero-reg operation | |
| 4457 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4458 single_instruction; | |
| 4459 dst : E(write); | |
| 4460 src2 : R(read); | |
| 4461 IALU : R; | |
| 4462 %} | |
| 4463 | |
| 4464 // Integer ALU zero-reg operation with condition code only | |
| 4465 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4466 single_instruction; | |
| 4467 cr : E(write); | |
| 4468 src : R(read); | |
| 4469 IALU : R; | |
| 4470 %} | |
| 4471 | |
| 4472 // Integer ALU reg-reg operation with condition code only | |
| 4473 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4474 single_instruction; | |
| 4475 cr : E(write); | |
| 4476 src1 : R(read); | |
| 4477 src2 : R(read); | |
| 4478 IALU : R; | |
| 4479 %} | |
| 4480 | |
| 4481 // Integer ALU reg-imm operation with condition code only | |
| 4482 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4483 single_instruction; | |
| 4484 cr : E(write); | |
| 4485 src1 : R(read); | |
| 4486 IALU : R; | |
| 4487 %} | |
| 4488 | |
| 4489 // Integer ALU reg-reg-zero operation with condition code only | |
| 4490 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4491 single_instruction; | |
| 4492 cr : E(write); | |
| 4493 src1 : R(read); | |
| 4494 src2 : R(read); | |
| 4495 IALU : R; | |
| 4496 %} | |
| 4497 | |
| 4498 // Integer ALU reg-imm-zero operation with condition code only | |
| 4499 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4500 single_instruction; | |
| 4501 cr : E(write); | |
| 4502 src1 : R(read); | |
| 4503 IALU : R; | |
| 4504 %} | |
| 4505 | |
| 4506 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4507 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4508 single_instruction; | |
| 4509 cr : E(write); | |
| 4510 src1 : E(write); | |
| 4511 src1 : R(read); | |
| 4512 src2 : R(read); | |
| 4513 IALU : R; | |
| 4514 %} | |
| 4515 | |
| 4516 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4517 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4518 single_instruction; | |
| 4519 cr : E(write); | |
| 4520 src1 : E(write); | |
| 4521 src1 : R(read); | |
| 4522 IALU : R; | |
| 4523 %} | |
| 4524 | |
| 4525 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4526 multiple_bundles; | |
| 4527 dst : E(write)+4; | |
| 4528 cr : E(write); | |
| 4529 src1 : R(read); | |
| 4530 src2 : R(read); | |
| 4531 IALU : R(3); | |
| 4532 BR : R(2); | |
| 4533 %} | |
| 4534 | |
| 4535 // Integer ALU operation | |
| 4536 pipe_class ialu_none(iRegI dst) %{ | |
| 4537 single_instruction; | |
| 4538 dst : E(write); | |
| 4539 IALU : R; | |
| 4540 %} | |
| 4541 | |
| 4542 // Integer ALU reg operation | |
| 4543 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4544 single_instruction; may_have_no_code; | |
| 4545 dst : E(write); | |
| 4546 src : R(read); | |
| 4547 IALU : R; | |
| 4548 %} | |
| 4549 | |
| 4550 // Integer ALU reg conditional operation | |
| 4551 // This instruction has a 1 cycle stall, and cannot execute | |
| 4552 // in the same cycle as the instruction setting the condition | |
| 4553 // code. We kludge this by pretending to read the condition code | |
| 4554 // 1 cycle earlier, and by marking the functional units as busy | |
| 4555 // for 2 cycles with the result available 1 cycle later than | |
| 4556 // is really the case. | |
| 4557 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4558 single_instruction; | |
| 4559 op2_out : C(write); | |
| 4560 op1 : R(read); | |
| 4561 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4562 BR : R(2); | |
| 4563 MS : R(2); | |
| 4564 %} | |
| 4565 | |
| 4566 #ifdef _LP64 | |
| 4567 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4568 instruction_count(1); multiple_bundles; | |
| 4569 dst : C(write)+1; | |
| 4570 src : R(read)+1; | |
| 4571 IALU : R(1); | |
| 4572 BR : E(2); | |
| 4573 MS : E(2); | |
| 4574 %} | |
| 4575 #endif | |
| 4576 | |
| 4577 // Integer ALU reg operation | |
| 4578 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4579 single_instruction; may_have_no_code; | |
| 4580 dst : E(write); | |
| 4581 src : R(read); | |
| 4582 IALU : R; | |
| 4583 %} | |
| 4584 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4585 single_instruction; may_have_no_code; | |
| 4586 dst : E(write); | |
| 4587 src : R(read); | |
| 4588 IALU : R; | |
| 4589 %} | |
| 4590 | |
| 4591 // Two integer ALU reg operations | |
| 4592 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4593 instruction_count(2); | |
| 4594 dst : E(write); | |
| 4595 src : R(read); | |
| 4596 A0 : R; | |
| 4597 A1 : R; | |
| 4598 %} | |
| 4599 | |
| 4600 // Two integer ALU reg operations | |
| 4601 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4602 instruction_count(2); may_have_no_code; | |
| 4603 dst : E(write); | |
| 4604 src : R(read); | |
| 4605 A0 : R; | |
| 4606 A1 : R; | |
| 4607 %} | |
| 4608 | |
| 4609 // Integer ALU imm operation | |
| 4610 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4611 single_instruction; | |
| 4612 dst : E(write); | |
| 4613 IALU : R; | |
| 4614 %} | |
| 4615 | |
| 4616 // Integer ALU reg-reg with carry operation | |
| 4617 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4618 single_instruction; | |
| 4619 dst : E(write); | |
| 4620 src1 : R(read); | |
| 4621 src2 : R(read); | |
| 4622 IALU : R; | |
| 4623 %} | |
| 4624 | |
| 4625 // Integer ALU cc operation | |
| 4626 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4627 single_instruction; | |
| 4628 dst : E(write); | |
| 4629 cc : R(read); | |
| 4630 IALU : R; | |
| 4631 %} | |
| 4632 | |
| 4633 // Integer ALU cc / second IALU operation | |
| 4634 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4635 instruction_count(1); multiple_bundles; | |
| 4636 dst : E(write)+1; | |
| 4637 src : R(read); | |
| 4638 IALU : R; | |
| 4639 %} | |
| 4640 | |
| 4641 // Integer ALU cc / second IALU operation | |
| 4642 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4643 instruction_count(1); multiple_bundles; | |
| 4644 dst : E(write)+1; | |
| 4645 p : R(read); | |
| 4646 q : R(read); | |
| 4647 IALU : R; | |
| 4648 %} | |
| 4649 | |
| 4650 // Integer ALU hi-lo-reg operation | |
| 4651 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4652 instruction_count(1); multiple_bundles; | |
| 4653 dst : E(write)+1; | |
| 4654 IALU : R(2); | |
| 4655 %} | |
| 4656 | |
| 4657 // Float ALU hi-lo-reg operation (with temp) | |
| 4658 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4659 instruction_count(1); multiple_bundles; | |
| 4660 dst : E(write)+1; | |
| 4661 IALU : R(2); | |
| 4662 %} | |
| 4663 | |
| 4664 // Long Constant | |
| 4665 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4666 instruction_count(2); multiple_bundles; | |
| 4667 dst : E(write)+1; | |
| 4668 IALU : R(2); | |
| 4669 IALU : R(2); | |
| 4670 %} | |
| 4671 | |
| 4672 // Pointer Constant | |
| 4673 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4674 instruction_count(0); multiple_bundles; | |
| 4675 fixed_latency(6); | |
| 4676 %} | |
| 4677 | |
| 4678 // Polling Address | |
| 4679 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4680 #ifdef _LP64 | |
| 4681 instruction_count(0); multiple_bundles; | |
| 4682 fixed_latency(6); | |
| 4683 #else | |
| 4684 dst : E(write); | |
| 4685 IALU : R; | |
| 4686 #endif | |
| 4687 %} | |
| 4688 | |
| 4689 // Long Constant small | |
| 4690 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4691 instruction_count(2); | |
| 4692 dst : E(write); | |
| 4693 IALU : R; | |
| 4694 IALU : R; | |
| 4695 %} | |
| 4696 | |
| 4697 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4698 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4699 instruction_count(1); multiple_bundles; | |
| 4700 src : R(read); | |
| 4701 dst : M(write)+1; | |
| 4702 IALU : R; | |
| 4703 MS : E; | |
| 4704 %} | |
| 4705 | |
| 4706 // Integer ALU nop operation | |
| 4707 pipe_class ialu_nop() %{ | |
| 4708 single_instruction; | |
| 4709 IALU : R; | |
| 4710 %} | |
| 4711 | |
| 4712 // Integer ALU nop operation | |
| 4713 pipe_class ialu_nop_A0() %{ | |
| 4714 single_instruction; | |
| 4715 A0 : R; | |
| 4716 %} | |
| 4717 | |
| 4718 // Integer ALU nop operation | |
| 4719 pipe_class ialu_nop_A1() %{ | |
| 4720 single_instruction; | |
| 4721 A1 : R; | |
| 4722 %} | |
| 4723 | |
| 4724 // Integer Multiply reg-reg operation | |
| 4725 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4726 single_instruction; | |
| 4727 dst : E(write); | |
| 4728 src1 : R(read); | |
| 4729 src2 : R(read); | |
| 4730 MS : R(5); | |
| 4731 %} | |
| 4732 | |
| 4733 // Integer Multiply reg-imm operation | |
| 4734 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4735 single_instruction; | |
| 4736 dst : E(write); | |
| 4737 src1 : R(read); | |
| 4738 MS : R(5); | |
| 4739 %} | |
| 4740 | |
| 4741 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4742 single_instruction; | |
| 4743 dst : E(write)+4; | |
| 4744 src1 : R(read); | |
| 4745 src2 : R(read); | |
| 4746 MS : R(6); | |
| 4747 %} | |
| 4748 | |
| 4749 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4750 single_instruction; | |
| 4751 dst : E(write)+4; | |
| 4752 src1 : R(read); | |
| 4753 MS : R(6); | |
| 4754 %} | |
| 4755 | |
| 4756 // Integer Divide reg-reg | |
| 4757 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4758 instruction_count(1); multiple_bundles; | |
| 4759 dst : E(write); | |
| 4760 temp : E(write); | |
| 4761 src1 : R(read); | |
| 4762 src2 : R(read); | |
| 4763 temp : R(read); | |
| 4764 MS : R(38); | |
| 4765 %} | |
| 4766 | |
| 4767 // Integer Divide reg-imm | |
| 4768 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4769 instruction_count(1); multiple_bundles; | |
| 4770 dst : E(write); | |
| 4771 temp : E(write); | |
| 4772 src1 : R(read); | |
| 4773 temp : R(read); | |
| 4774 MS : R(38); | |
| 4775 %} | |
| 4776 | |
| 4777 // Long Divide | |
| 4778 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4779 dst : E(write)+71; | |
| 4780 src1 : R(read); | |
| 4781 src2 : R(read)+1; | |
| 4782 MS : R(70); | |
| 4783 %} | |
| 4784 | |
| 4785 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4786 dst : E(write)+71; | |
| 4787 src1 : R(read); | |
| 4788 MS : R(70); | |
| 4789 %} | |
| 4790 | |
| 4791 // Floating Point Add Float | |
| 4792 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4793 single_instruction; | |
| 4794 dst : X(write); | |
| 4795 src1 : E(read); | |
| 4796 src2 : E(read); | |
| 4797 FA : R; | |
| 4798 %} | |
| 4799 | |
| 4800 // Floating Point Add Double | |
| 4801 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4802 single_instruction; | |
| 4803 dst : X(write); | |
| 4804 src1 : E(read); | |
| 4805 src2 : E(read); | |
| 4806 FA : R; | |
| 4807 %} | |
| 4808 | |
| 4809 // Floating Point Conditional Move based on integer flags | |
| 4810 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4811 single_instruction; | |
| 4812 dst : X(write); | |
| 4813 src : E(read); | |
| 4814 cr : R(read); | |
| 4815 FA : R(2); | |
| 4816 BR : R(2); | |
| 4817 %} | |
| 4818 | |
| 4819 // Floating Point Conditional Move based on integer flags | |
| 4820 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4821 single_instruction; | |
| 4822 dst : X(write); | |
| 4823 src : E(read); | |
| 4824 cr : R(read); | |
| 4825 FA : R(2); | |
| 4826 BR : R(2); | |
| 4827 %} | |
| 4828 | |
| 4829 // Floating Point Multiply Float | |
| 4830 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4831 single_instruction; | |
| 4832 dst : X(write); | |
| 4833 src1 : E(read); | |
| 4834 src2 : E(read); | |
| 4835 FM : R; | |
| 4836 %} | |
| 4837 | |
| 4838 // Floating Point Multiply Double | |
| 4839 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4840 single_instruction; | |
| 4841 dst : X(write); | |
| 4842 src1 : E(read); | |
| 4843 src2 : E(read); | |
| 4844 FM : R; | |
| 4845 %} | |
| 4846 | |
| 4847 // Floating Point Divide Float | |
| 4848 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4849 single_instruction; | |
| 4850 dst : X(write); | |
| 4851 src1 : E(read); | |
| 4852 src2 : E(read); | |
| 4853 FM : R; | |
| 4854 FDIV : C(14); | |
| 4855 %} | |
| 4856 | |
| 4857 // Floating Point Divide Double | |
| 4858 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4859 single_instruction; | |
| 4860 dst : X(write); | |
| 4861 src1 : E(read); | |
| 4862 src2 : E(read); | |
| 4863 FM : R; | |
| 4864 FDIV : C(17); | |
| 4865 %} | |
| 4866 | |
| 4867 // Floating Point Move/Negate/Abs Float | |
| 4868 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4869 single_instruction; | |
| 4870 dst : W(write); | |
| 4871 src : E(read); | |
| 4872 FA : R(1); | |
| 4873 %} | |
| 4874 | |
| 4875 // Floating Point Move/Negate/Abs Double | |
| 4876 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4877 single_instruction; | |
| 4878 dst : W(write); | |
| 4879 src : E(read); | |
| 4880 FA : R; | |
| 4881 %} | |
| 4882 | |
| 4883 // Floating Point Convert F->D | |
| 4884 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4885 single_instruction; | |
| 4886 dst : X(write); | |
| 4887 src : E(read); | |
| 4888 FA : R; | |
| 4889 %} | |
| 4890 | |
| 4891 // Floating Point Convert I->D | |
| 4892 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4893 single_instruction; | |
| 4894 dst : X(write); | |
| 4895 src : E(read); | |
| 4896 FA : R; | |
| 4897 %} | |
| 4898 | |
| 4899 // Floating Point Convert LHi->D | |
| 4900 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4901 single_instruction; | |
| 4902 dst : X(write); | |
| 4903 src : E(read); | |
| 4904 FA : R; | |
| 4905 %} | |
| 4906 | |
| 4907 // Floating Point Convert L->D | |
| 4908 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4909 single_instruction; | |
| 4910 dst : X(write); | |
| 4911 src : E(read); | |
| 4912 FA : R; | |
| 4913 %} | |
| 4914 | |
| 4915 // Floating Point Convert L->F | |
| 4916 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4917 single_instruction; | |
| 4918 dst : X(write); | |
| 4919 src : E(read); | |
| 4920 FA : R; | |
| 4921 %} | |
| 4922 | |
| 4923 // Floating Point Convert D->F | |
| 4924 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4925 single_instruction; | |
| 4926 dst : X(write); | |
| 4927 src : E(read); | |
| 4928 FA : R; | |
| 4929 %} | |
| 4930 | |
| 4931 // Floating Point Convert I->L | |
| 4932 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4933 single_instruction; | |
| 4934 dst : X(write); | |
| 4935 src : E(read); | |
| 4936 FA : R; | |
| 4937 %} | |
| 4938 | |
| 4939 // Floating Point Convert D->F | |
| 4940 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4941 instruction_count(1); multiple_bundles; | |
| 4942 dst : X(write)+6; | |
| 4943 src : E(read); | |
| 4944 FA : R; | |
| 4945 %} | |
| 4946 | |
| 4947 // Floating Point Convert D->L | |
| 4948 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4949 instruction_count(1); multiple_bundles; | |
| 4950 dst : X(write)+6; | |
| 4951 src : E(read); | |
| 4952 FA : R; | |
| 4953 %} | |
| 4954 | |
| 4955 // Floating Point Convert F->I | |
| 4956 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4957 instruction_count(1); multiple_bundles; | |
| 4958 dst : X(write)+6; | |
| 4959 src : E(read); | |
| 4960 FA : R; | |
| 4961 %} | |
| 4962 | |
| 4963 // Floating Point Convert F->L | |
| 4964 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4965 instruction_count(1); multiple_bundles; | |
| 4966 dst : X(write)+6; | |
| 4967 src : E(read); | |
| 4968 FA : R; | |
| 4969 %} | |
| 4970 | |
| 4971 // Floating Point Convert I->F | |
| 4972 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4973 single_instruction; | |
| 4974 dst : X(write); | |
| 4975 src : E(read); | |
| 4976 FA : R; | |
| 4977 %} | |
| 4978 | |
| 4979 // Floating Point Compare | |
| 4980 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4981 single_instruction; | |
| 4982 cr : X(write); | |
| 4983 src1 : E(read); | |
| 4984 src2 : E(read); | |
| 4985 FA : R; | |
| 4986 %} | |
| 4987 | |
| 4988 // Floating Point Compare | |
| 4989 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 4990 single_instruction; | |
| 4991 cr : X(write); | |
| 4992 src1 : E(read); | |
| 4993 src2 : E(read); | |
| 4994 FA : R; | |
| 4995 %} | |
| 4996 | |
| 4997 // Floating Add Nop | |
| 4998 pipe_class fadd_nop() %{ | |
| 4999 single_instruction; | |
| 5000 FA : R; | |
| 5001 %} | |
| 5002 | |
| 5003 // Integer Store to Memory | |
| 5004 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5005 single_instruction; | |
| 5006 mem : R(read); | |
| 5007 src : C(read); | |
| 5008 MS : R; | |
| 5009 %} | |
| 5010 | |
| 5011 // Integer Store to Memory | |
| 5012 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5013 single_instruction; | |
| 5014 mem : R(read); | |
| 5015 src : C(read); | |
| 5016 MS : R; | |
| 5017 %} | |
| 5018 | |
| 5019 // Integer Store Zero to Memory | |
| 5020 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5021 single_instruction; | |
| 5022 mem : R(read); | |
| 5023 MS : R; | |
| 5024 %} | |
| 5025 | |
| 5026 // Special Stack Slot Store | |
| 5027 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5028 single_instruction; | |
| 5029 stkSlot : R(read); | |
| 5030 src : C(read); | |
| 5031 MS : R; | |
| 5032 %} | |
| 5033 | |
| 5034 // Special Stack Slot Store | |
| 5035 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5036 instruction_count(2); multiple_bundles; | |
| 5037 stkSlot : R(read); | |
| 5038 src : C(read); | |
| 5039 MS : R(2); | |
| 5040 %} | |
| 5041 | |
| 5042 // Float Store | |
| 5043 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5044 single_instruction; | |
| 5045 mem : R(read); | |
| 5046 src : C(read); | |
| 5047 MS : R; | |
| 5048 %} | |
| 5049 | |
| 5050 // Float Store | |
| 5051 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5052 single_instruction; | |
| 5053 mem : R(read); | |
| 5054 MS : R; | |
| 5055 %} | |
| 5056 | |
| 5057 // Double Store | |
| 5058 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5059 instruction_count(1); | |
| 5060 mem : R(read); | |
| 5061 src : C(read); | |
| 5062 MS : R; | |
| 5063 %} | |
| 5064 | |
| 5065 // Double Store | |
| 5066 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5067 single_instruction; | |
| 5068 mem : R(read); | |
| 5069 MS : R; | |
| 5070 %} | |
| 5071 | |
| 5072 // Special Stack Slot Float Store | |
| 5073 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5074 single_instruction; | |
| 5075 stkSlot : R(read); | |
| 5076 src : C(read); | |
| 5077 MS : R; | |
| 5078 %} | |
| 5079 | |
| 5080 // Special Stack Slot Double Store | |
| 5081 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5082 single_instruction; | |
| 5083 stkSlot : R(read); | |
| 5084 src : C(read); | |
| 5085 MS : R; | |
| 5086 %} | |
| 5087 | |
| 5088 // Integer Load (when sign bit propagation not needed) | |
| 5089 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5090 single_instruction; | |
| 5091 mem : R(read); | |
| 5092 dst : C(write); | |
| 5093 MS : R; | |
| 5094 %} | |
| 5095 | |
| 5096 // Integer Load from stack operand | |
| 5097 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5098 single_instruction; | |
| 5099 mem : R(read); | |
| 5100 dst : C(write); | |
| 5101 MS : R; | |
| 5102 %} | |
| 5103 | |
| 5104 // Integer Load (when sign bit propagation or masking is needed) | |
| 5105 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5106 single_instruction; | |
| 5107 mem : R(read); | |
| 5108 dst : M(write); | |
| 5109 MS : R; | |
| 5110 %} | |
| 5111 | |
| 5112 // Float Load | |
| 5113 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5114 single_instruction; | |
| 5115 mem : R(read); | |
| 5116 dst : M(write); | |
| 5117 MS : R; | |
| 5118 %} | |
| 5119 | |
| 5120 // Float Load | |
| 5121 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5122 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5123 mem : R(read); | |
| 5124 dst : M(write); | |
| 5125 MS : R; | |
| 5126 %} | |
| 5127 | |
| 5128 // Float Load | |
| 5129 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5130 single_instruction; | |
| 5131 stkSlot : R(read); | |
| 5132 dst : M(write); | |
| 5133 MS : R; | |
| 5134 %} | |
| 5135 | |
| 5136 // Float Load | |
| 5137 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5138 single_instruction; | |
| 5139 stkSlot : R(read); | |
| 5140 dst : M(write); | |
| 5141 MS : R; | |
| 5142 %} | |
| 5143 | |
| 5144 // Memory Nop | |
| 5145 pipe_class mem_nop() %{ | |
| 5146 single_instruction; | |
| 5147 MS : R; | |
| 5148 %} | |
| 5149 | |
| 5150 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5151 single_instruction; | |
| 5152 dst : E(write); | |
| 5153 IALU : R; | |
| 5154 %} | |
| 5155 | |
| 5156 pipe_class loadPollP(iRegP poll) %{ | |
| 5157 single_instruction; | |
| 5158 poll : R(read); | |
| 5159 MS : R; | |
| 5160 %} | |
| 5161 | |
| 5162 pipe_class br(Universe br, label labl) %{ | |
| 5163 single_instruction_with_delay_slot; | |
| 5164 BR : R; | |
| 5165 %} | |
| 5166 | |
| 5167 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5168 single_instruction_with_delay_slot; | |
| 5169 cr : E(read); | |
| 5170 BR : R; | |
| 5171 %} | |
| 5172 | |
| 5173 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5174 single_instruction_with_delay_slot; | |
| 5175 op1 : E(read); | |
| 5176 BR : R; | |
| 5177 MS : R; | |
| 5178 %} | |
| 5179 | |
| 5180 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
| 5181 single_instruction_with_delay_slot; | |
| 5182 cr : E(read); | |
| 5183 BR : R; | |
| 5184 %} | |
| 5185 | |
| 5186 pipe_class br_nop() %{ | |
| 5187 single_instruction; | |
| 5188 BR : R; | |
| 5189 %} | |
| 5190 | |
| 5191 pipe_class simple_call(method meth) %{ | |
| 5192 instruction_count(2); multiple_bundles; force_serialization; | |
| 5193 fixed_latency(100); | |
| 5194 BR : R(1); | |
| 5195 MS : R(1); | |
| 5196 A0 : R(1); | |
| 5197 %} | |
| 5198 | |
| 5199 pipe_class compiled_call(method meth) %{ | |
| 5200 instruction_count(1); multiple_bundles; force_serialization; | |
| 5201 fixed_latency(100); | |
| 5202 MS : R(1); | |
| 5203 %} | |
| 5204 | |
| 5205 pipe_class call(method meth) %{ | |
| 5206 instruction_count(0); multiple_bundles; force_serialization; | |
| 5207 fixed_latency(100); | |
| 5208 %} | |
| 5209 | |
| 5210 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5211 single_instruction; has_delay_slot; | |
| 5212 fixed_latency(100); | |
| 5213 BR : R(1); | |
| 5214 MS : R(1); | |
| 5215 %} | |
| 5216 | |
| 5217 pipe_class ret(Universe ignore) %{ | |
| 5218 single_instruction; has_delay_slot; | |
| 5219 BR : R(1); | |
| 5220 MS : R(1); | |
| 5221 %} | |
| 5222 | |
| 5223 pipe_class ret_poll(g3RegP poll) %{ | |
| 5224 instruction_count(3); has_delay_slot; | |
| 5225 poll : E(read); | |
| 5226 MS : R; | |
| 5227 %} | |
| 5228 | |
| 5229 // The real do-nothing guy | |
| 5230 pipe_class empty( ) %{ | |
| 5231 instruction_count(0); | |
| 5232 %} | |
| 5233 | |
| 5234 pipe_class long_memory_op() %{ | |
| 5235 instruction_count(0); multiple_bundles; force_serialization; | |
| 5236 fixed_latency(25); | |
| 5237 MS : R(1); | |
| 5238 %} | |
| 5239 | |
| 5240 // Check-cast | |
| 5241 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5242 array : R(read); | |
| 5243 match : R(read); | |
| 5244 IALU : R(2); | |
| 5245 BR : R(2); | |
| 5246 MS : R; | |
| 5247 %} | |
| 5248 | |
| 5249 // Convert FPU flags into +1,0,-1 | |
| 5250 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5251 src1 : E(read); | |
| 5252 src2 : E(read); | |
| 5253 dst : E(write); | |
| 5254 FA : R; | |
| 5255 MS : R(2); | |
| 5256 BR : R(2); | |
| 5257 %} | |
| 5258 | |
| 5259 // Compare for p < q, and conditionally add y | |
| 5260 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5261 p : E(read); | |
| 5262 q : E(read); | |
| 5263 y : E(read); | |
| 5264 IALU : R(3) | |
| 5265 %} | |
| 5266 | |
| 5267 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5268 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5269 src2 : E(read); | |
| 5270 srcdst : E(read); | |
| 5271 IALU : R; | |
| 5272 BR : R; | |
| 5273 %} | |
| 5274 | |
| 5275 // Define the class for the Nop node | |
| 5276 define %{ | |
| 5277 MachNop = ialu_nop; | |
| 5278 %} | |
| 5279 | |
| 5280 %} | |
| 5281 | |
| 5282 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5283 | |
| 5284 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5285 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5286 // No match rule to avoid chain rule match. | |
| 5287 effect(DEF dst, USE src); | |
| 5288 ins_cost(MEMORY_REF_COST); | |
| 5289 size(4); | |
| 5290 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5291 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5292 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5293 ins_pipe(floadF_stk); |
| 5294 %} | |
| 5295 | |
| 5296 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5297 // No match rule to avoid chain rule match. | |
| 5298 effect(DEF dst, USE src); | |
| 5299 ins_cost(MEMORY_REF_COST); | |
| 5300 size(4); | |
| 5301 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5302 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5303 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5304 ins_pipe(floadD_stk); |
| 5305 %} | |
| 5306 | |
| 5307 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5308 // No match rule to avoid chain rule match. | |
| 5309 effect(DEF dst, USE src); | |
| 5310 ins_cost(MEMORY_REF_COST); | |
| 5311 size(4); | |
| 5312 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5313 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5314 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5315 ins_pipe(fstoreF_stk_reg); |
| 5316 %} | |
| 5317 | |
| 5318 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5319 // No match rule to avoid chain rule match. | |
| 5320 effect(DEF dst, USE src); | |
| 5321 ins_cost(MEMORY_REF_COST); | |
| 5322 size(4); | |
| 5323 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5324 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5325 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5326 ins_pipe(fstoreD_stk_reg); |
| 5327 %} | |
| 5328 | |
| 5329 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5330 effect(DEF dst, USE src); | |
| 5331 ins_cost(MEMORY_REF_COST*2); | |
| 5332 size(8); | |
| 5333 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5334 "STW R_G0,$dst.lo" %} | |
| 5335 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5336 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5337 ins_pipe(lstoreI_stk_reg); |
| 5338 %} | |
| 5339 | |
| 5340 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5341 // No match rule to avoid chain rule match. | |
| 5342 effect(DEF dst, USE src); | |
| 5343 ins_cost(MEMORY_REF_COST); | |
| 5344 size(4); | |
| 5345 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5346 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5347 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5348 ins_pipe(istore_stk_reg); |
| 5349 %} | |
| 5350 | |
| 5351 //---------- Chain stack slots between similar types -------- | |
| 5352 | |
| 5353 // Load integer from stack slot | |
| 5354 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5355 match(Set dst src); | |
| 5356 ins_cost(MEMORY_REF_COST); | |
| 5357 | |
| 5358 size(4); | |
| 5359 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5360 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5361 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5362 ins_pipe(iload_mem); |
| 5363 %} | |
| 5364 | |
| 5365 // Store integer to stack slot | |
| 5366 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5367 match(Set dst src); | |
| 5368 ins_cost(MEMORY_REF_COST); | |
| 5369 | |
| 5370 size(4); | |
| 5371 format %{ "STW $src,$dst\t!stk" %} | |
| 5372 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5373 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5374 ins_pipe(istore_mem_reg); |
| 5375 %} | |
| 5376 | |
| 5377 // Load long from stack slot | |
| 5378 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5379 match(Set dst src); | |
| 5380 | |
| 5381 ins_cost(MEMORY_REF_COST); | |
| 5382 size(4); | |
| 5383 format %{ "LDX $src,$dst\t! long" %} | |
| 5384 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5385 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5386 ins_pipe(iload_mem); |
| 5387 %} | |
| 5388 | |
| 5389 // Store long to stack slot | |
| 5390 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5391 match(Set dst src); | |
| 5392 | |
| 5393 ins_cost(MEMORY_REF_COST); | |
| 5394 size(4); | |
| 5395 format %{ "STX $src,$dst\t! long" %} | |
| 5396 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5397 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5398 ins_pipe(istore_mem_reg); |
| 5399 %} | |
| 5400 | |
| 5401 #ifdef _LP64 | |
| 5402 // Load pointer from stack slot, 64-bit encoding | |
| 5403 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5404 match(Set dst src); | |
| 5405 ins_cost(MEMORY_REF_COST); | |
| 5406 size(4); | |
| 5407 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5408 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5409 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5410 ins_pipe(iload_mem); |
| 5411 %} | |
| 5412 | |
| 5413 // Store pointer to stack slot | |
| 5414 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5415 match(Set dst src); | |
| 5416 ins_cost(MEMORY_REF_COST); | |
| 5417 size(4); | |
| 5418 format %{ "STX $src,$dst\t!ptr" %} | |
| 5419 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5420 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5421 ins_pipe(istore_mem_reg); |
| 5422 %} | |
| 5423 #else // _LP64 | |
| 5424 // Load pointer from stack slot, 32-bit encoding | |
| 5425 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5426 match(Set dst src); | |
| 5427 ins_cost(MEMORY_REF_COST); | |
| 5428 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5429 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5430 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5431 ins_pipe(iload_mem); |
| 5432 %} | |
| 5433 | |
| 5434 // Store pointer to stack slot | |
| 5435 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5436 match(Set dst src); | |
| 5437 ins_cost(MEMORY_REF_COST); | |
| 5438 format %{ "STW $src,$dst\t!ptr" %} | |
| 5439 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5440 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5441 ins_pipe(istore_mem_reg); |
| 5442 %} | |
| 5443 #endif // _LP64 | |
| 5444 | |
| 5445 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5446 // Nop using the A0 functional unit | |
| 5447 instruct Nop_A0() %{ | |
| 5448 ins_cost(0); | |
| 5449 | |
| 5450 format %{ "NOP ! Alu Pipeline" %} | |
| 5451 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5452 ins_encode( form2_nop() ); | |
| 5453 ins_pipe(ialu_nop_A0); | |
| 5454 %} | |
| 5455 | |
| 5456 // Nop using the A1 functional unit | |
| 5457 instruct Nop_A1( ) %{ | |
| 5458 ins_cost(0); | |
| 5459 | |
| 5460 format %{ "NOP ! Alu Pipeline" %} | |
| 5461 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5462 ins_encode( form2_nop() ); | |
| 5463 ins_pipe(ialu_nop_A1); | |
| 5464 %} | |
| 5465 | |
| 5466 // Nop using the memory functional unit | |
| 5467 instruct Nop_MS( ) %{ | |
| 5468 ins_cost(0); | |
| 5469 | |
| 5470 format %{ "NOP ! Memory Pipeline" %} | |
| 5471 ins_encode( emit_mem_nop ); | |
| 5472 ins_pipe(mem_nop); | |
| 5473 %} | |
| 5474 | |
| 5475 // Nop using the floating add functional unit | |
| 5476 instruct Nop_FA( ) %{ | |
| 5477 ins_cost(0); | |
| 5478 | |
| 5479 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5480 ins_encode( emit_fadd_nop ); | |
| 5481 ins_pipe(fadd_nop); | |
| 5482 %} | |
| 5483 | |
| 5484 // Nop using the branch functional unit | |
| 5485 instruct Nop_BR( ) %{ | |
| 5486 ins_cost(0); | |
| 5487 | |
| 5488 format %{ "NOP ! Branch Pipeline" %} | |
| 5489 ins_encode( emit_br_nop ); | |
| 5490 ins_pipe(br_nop); | |
| 5491 %} | |
| 5492 | |
| 5493 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5494 //----------Load Instructions-------------------------------------------------- | |
| 5495 // Load Byte (8bit signed) | |
| 5496 instruct loadB(iRegI dst, memory mem) %{ | |
| 5497 match(Set dst (LoadB mem)); | |
| 5498 ins_cost(MEMORY_REF_COST); | |
| 5499 | |
| 5500 size(4); | |
| 624 | 5501 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5502 ins_encode %{ |
| 5503 __ ldsb($mem$$Address, $dst$$Register); | |
| 5504 %} | |
| 624 | 5505 ins_pipe(iload_mask_mem); |
| 5506 %} | |
| 5507 | |
| 5508 // Load Byte (8bit signed) into a Long Register | |
| 5509 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5510 match(Set dst (ConvI2L (LoadB mem))); | |
| 5511 ins_cost(MEMORY_REF_COST); | |
| 5512 | |
| 5513 size(4); | |
| 5514 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5515 ins_encode %{ |
| 5516 __ ldsb($mem$$Address, $dst$$Register); | |
| 5517 %} | |
| 0 | 5518 ins_pipe(iload_mask_mem); |
| 5519 %} | |
| 5520 | |
| 624 | 5521 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5522 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5523 match(Set dst (LoadUB mem)); | |
| 0 | 5524 ins_cost(MEMORY_REF_COST); |
| 5525 | |
| 5526 size(4); | |
| 624 | 5527 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5528 ins_encode %{ |
| 5529 __ ldub($mem$$Address, $dst$$Register); | |
| 5530 %} | |
| 824 | 5531 ins_pipe(iload_mem); |
| 624 | 5532 %} |
| 5533 | |
| 5534 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5535 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5536 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5537 ins_cost(MEMORY_REF_COST); | |
| 5538 | |
| 5539 size(4); | |
| 5540 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5541 ins_encode %{ |
| 5542 __ ldub($mem$$Address, $dst$$Register); | |
| 5543 %} | |
| 824 | 5544 ins_pipe(iload_mem); |
| 5545 %} | |
| 5546 | |
| 5547 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5548 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5549 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5550 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5551 | |
| 5552 size(2*4); | |
| 5553 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5554 "AND $dst,$mask,$dst" %} | |
| 5555 ins_encode %{ | |
| 5556 __ ldub($mem$$Address, $dst$$Register); | |
| 5557 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5558 %} | |
| 5559 ins_pipe(iload_mem); | |
| 0 | 5560 %} |
| 5561 | |
| 624 | 5562 // Load Short (16bit signed) |
| 5563 instruct loadS(iRegI dst, memory mem) %{ | |
| 5564 match(Set dst (LoadS mem)); | |
| 5565 ins_cost(MEMORY_REF_COST); | |
| 5566 | |
| 5567 size(4); | |
| 5568 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5569 ins_encode %{ |
| 5570 __ ldsh($mem$$Address, $dst$$Register); | |
| 5571 %} | |
| 624 | 5572 ins_pipe(iload_mask_mem); |
| 5573 %} | |
| 5574 | |
| 785 | 5575 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5576 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5577 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5578 ins_cost(MEMORY_REF_COST); | |
| 5579 | |
| 5580 size(4); | |
| 5581 | |
| 5582 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5583 ins_encode %{ | |
| 5584 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5585 %} | |
| 5586 ins_pipe(iload_mask_mem); | |
| 5587 %} | |
| 5588 | |
| 624 | 5589 // Load Short (16bit signed) into a Long Register |
| 5590 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5591 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5592 ins_cost(MEMORY_REF_COST); |
| 5593 | |
| 5594 size(4); | |
| 624 | 5595 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5596 ins_encode %{ |
| 5597 __ ldsh($mem$$Address, $dst$$Register); | |
| 5598 %} | |
| 624 | 5599 ins_pipe(iload_mask_mem); |
| 5600 %} | |
| 5601 | |
| 5602 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5603 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5604 match(Set dst (LoadUS mem)); | |
| 5605 ins_cost(MEMORY_REF_COST); | |
| 5606 | |
| 5607 size(4); | |
| 5608 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5609 ins_encode %{ |
| 5610 __ lduh($mem$$Address, $dst$$Register); | |
| 5611 %} | |
| 824 | 5612 ins_pipe(iload_mem); |
| 0 | 5613 %} |
| 5614 | |
| 785 | 5615 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5616 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5617 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5618 ins_cost(MEMORY_REF_COST); | |
| 5619 | |
| 5620 size(4); | |
| 5621 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5622 ins_encode %{ | |
| 5623 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5624 %} | |
| 5625 ins_pipe(iload_mask_mem); | |
| 5626 %} | |
| 5627 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
5628 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5629 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5630 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5631 ins_cost(MEMORY_REF_COST); |
| 5632 | |
| 5633 size(4); | |
| 624 | 5634 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5635 ins_encode %{ |
| 5636 __ lduh($mem$$Address, $dst$$Register); | |
| 5637 %} | |
| 824 | 5638 ins_pipe(iload_mem); |
| 5639 %} | |
| 5640 | |
| 5641 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5642 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5643 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5644 ins_cost(MEMORY_REF_COST); | |
| 5645 | |
| 5646 size(4); | |
| 5647 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5648 ins_encode %{ | |
| 5649 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5650 %} | |
| 5651 ins_pipe(iload_mem); | |
| 5652 %} | |
| 5653 | |
| 5654 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5655 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5656 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5657 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5658 | |
| 5659 size(2*4); | |
| 5660 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5661 "AND $dst,$mask,$dst" %} | |
| 5662 ins_encode %{ | |
| 5663 Register Rdst = $dst$$Register; | |
| 5664 __ lduh($mem$$Address, Rdst); | |
| 5665 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5666 %} | |
| 5667 ins_pipe(iload_mem); | |
| 5668 %} | |
| 5669 | |
| 5670 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5671 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5672 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5673 effect(TEMP dst, TEMP tmp); | |
| 5674 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5675 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5676 size((3+1)*4); // set may use two instructions. |
| 824 | 5677 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5678 "SET $mask,$tmp\n\t" | |
| 5679 "AND $dst,$tmp,$dst" %} | |
| 5680 ins_encode %{ | |
| 5681 Register Rdst = $dst$$Register; | |
| 5682 Register Rtmp = $tmp$$Register; | |
| 5683 __ lduh($mem$$Address, Rdst); | |
| 5684 __ set($mask$$constant, Rtmp); | |
| 5685 __ and3(Rdst, Rtmp, Rdst); | |
| 5686 %} | |
| 5687 ins_pipe(iload_mem); | |
| 0 | 5688 %} |
| 5689 | |
| 5690 // Load Integer | |
| 5691 instruct loadI(iRegI dst, memory mem) %{ | |
| 5692 match(Set dst (LoadI mem)); | |
| 5693 ins_cost(MEMORY_REF_COST); | |
| 624 | 5694 |
| 5695 size(4); | |
| 5696 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5697 ins_encode %{ |
| 5698 __ lduw($mem$$Address, $dst$$Register); | |
| 5699 %} | |
| 624 | 5700 ins_pipe(iload_mem); |
| 5701 %} | |
| 5702 | |
| 785 | 5703 // Load Integer to Byte (8 bit signed) |
| 5704 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5705 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5706 ins_cost(MEMORY_REF_COST); | |
| 5707 | |
| 5708 size(4); | |
| 5709 | |
| 5710 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5711 ins_encode %{ | |
| 5712 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5713 %} | |
| 5714 ins_pipe(iload_mask_mem); | |
| 5715 %} | |
| 5716 | |
| 5717 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5718 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5719 match(Set dst (AndI (LoadI mem) mask)); | |
| 5720 ins_cost(MEMORY_REF_COST); | |
| 5721 | |
| 5722 size(4); | |
| 5723 | |
| 5724 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5725 ins_encode %{ | |
| 5726 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5727 %} | |
| 5728 ins_pipe(iload_mask_mem); | |
| 5729 %} | |
| 5730 | |
| 5731 // Load Integer to Short (16 bit signed) | |
| 5732 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5733 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5734 ins_cost(MEMORY_REF_COST); | |
| 5735 | |
| 5736 size(4); | |
| 5737 | |
| 5738 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5739 ins_encode %{ | |
| 5740 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5741 %} | |
| 5742 ins_pipe(iload_mask_mem); | |
| 5743 %} | |
| 5744 | |
| 5745 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5746 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5747 match(Set dst (AndI (LoadI mem) mask)); | |
| 5748 ins_cost(MEMORY_REF_COST); | |
| 5749 | |
| 5750 size(4); | |
| 5751 | |
| 5752 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5753 ins_encode %{ | |
| 5754 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5755 %} | |
| 5756 ins_pipe(iload_mask_mem); | |
| 5757 %} | |
| 5758 | |
| 624 | 5759 // Load Integer into a Long Register |
| 5760 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5761 match(Set dst (ConvI2L (LoadI mem))); | |
| 5762 ins_cost(MEMORY_REF_COST); | |
| 5763 | |
| 5764 size(4); | |
| 5765 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5766 ins_encode %{ |
| 5767 __ ldsw($mem$$Address, $dst$$Register); | |
| 5768 %} | |
| 824 | 5769 ins_pipe(iload_mask_mem); |
| 5770 %} | |
| 5771 | |
| 5772 // Load Integer with mask 0xFF into a Long Register | |
| 5773 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5774 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5775 ins_cost(MEMORY_REF_COST); | |
| 5776 | |
| 5777 size(4); | |
| 5778 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5779 ins_encode %{ | |
| 5780 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5781 %} | |
| 5782 ins_pipe(iload_mem); | |
| 5783 %} | |
| 5784 | |
| 5785 // Load Integer with mask 0xFFFF into a Long Register | |
| 5786 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5787 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5788 ins_cost(MEMORY_REF_COST); | |
| 5789 | |
| 5790 size(4); | |
| 5791 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5792 ins_encode %{ | |
| 5793 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5794 %} | |
| 5795 ins_pipe(iload_mem); | |
| 5796 %} | |
| 5797 | |
| 5798 // Load Integer with a 13-bit mask into a Long Register | |
| 5799 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5800 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5801 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5802 | |
| 5803 size(2*4); | |
| 5804 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5805 "AND $dst,$mask,$dst" %} | |
| 5806 ins_encode %{ | |
| 5807 Register Rdst = $dst$$Register; | |
| 5808 __ lduw($mem$$Address, Rdst); | |
| 5809 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5810 %} | |
| 5811 ins_pipe(iload_mem); | |
| 5812 %} | |
| 5813 | |
| 5814 // Load Integer with a 32-bit mask into a Long Register | |
| 5815 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5816 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5817 effect(TEMP dst, TEMP tmp); | |
| 5818 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5819 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5820 size((3+1)*4); // set may use two instructions. |
| 824 | 5821 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5822 "SET $mask,$tmp\n\t" | |
| 5823 "AND $dst,$tmp,$dst" %} | |
| 5824 ins_encode %{ | |
| 5825 Register Rdst = $dst$$Register; | |
| 5826 Register Rtmp = $tmp$$Register; | |
| 5827 __ lduw($mem$$Address, Rdst); | |
| 5828 __ set($mask$$constant, Rtmp); | |
| 5829 __ and3(Rdst, Rtmp, Rdst); | |
| 5830 %} | |
| 624 | 5831 ins_pipe(iload_mem); |
| 5832 %} | |
| 5833 | |
| 5834 // Load Unsigned Integer into a Long Register | |
| 5835 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5836 match(Set dst (LoadUI2L mem)); | |
| 5837 ins_cost(MEMORY_REF_COST); | |
| 5838 | |
| 5839 size(4); | |
| 5840 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5841 ins_encode %{ |
| 5842 __ lduw($mem$$Address, $dst$$Register); | |
| 5843 %} | |
| 0 | 5844 ins_pipe(iload_mem); |
| 5845 %} | |
| 5846 | |
| 5847 // Load Long - aligned | |
| 5848 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5849 match(Set dst (LoadL mem)); | |
| 5850 ins_cost(MEMORY_REF_COST); | |
| 624 | 5851 |
| 0 | 5852 size(4); |
| 5853 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5854 ins_encode %{ |
| 5855 __ ldx($mem$$Address, $dst$$Register); | |
| 5856 %} | |
| 0 | 5857 ins_pipe(iload_mem); |
| 5858 %} | |
| 5859 | |
| 5860 // Load Long - UNaligned | |
| 5861 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5862 match(Set dst (LoadL_unaligned mem)); | |
| 5863 effect(KILL tmp); | |
| 5864 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5865 size(16); | |
| 5866 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5867 "\tLDUW $mem ,$dst\n" | |
| 5868 "\tSLLX #32, $dst, $dst\n" | |
| 5869 "\tOR $dst, R_O7, $dst" %} | |
| 5870 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5871 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5872 ins_pipe(iload_mem); |
| 5873 %} | |
| 5874 | |
| 5875 // Load Aligned Packed Byte into a Double Register | |
| 5876 instruct loadA8B(regD dst, memory mem) %{ | |
| 5877 match(Set dst (Load8B mem)); | |
| 5878 ins_cost(MEMORY_REF_COST); | |
| 5879 size(4); | |
| 5880 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5881 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5882 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5883 ins_pipe(floadD_mem); |
| 5884 %} | |
| 5885 | |
| 5886 // Load Aligned Packed Char into a Double Register | |
| 5887 instruct loadA4C(regD dst, memory mem) %{ | |
| 5888 match(Set dst (Load4C mem)); | |
| 5889 ins_cost(MEMORY_REF_COST); | |
| 5890 size(4); | |
| 5891 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5892 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5893 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5894 ins_pipe(floadD_mem); |
| 5895 %} | |
| 5896 | |
| 5897 // Load Aligned Packed Short into a Double Register | |
| 5898 instruct loadA4S(regD dst, memory mem) %{ | |
| 5899 match(Set dst (Load4S mem)); | |
| 5900 ins_cost(MEMORY_REF_COST); | |
| 5901 size(4); | |
| 5902 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5903 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5904 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5905 ins_pipe(floadD_mem); |
| 5906 %} | |
| 5907 | |
| 5908 // Load Aligned Packed Int into a Double Register | |
| 5909 instruct loadA2I(regD dst, memory mem) %{ | |
| 5910 match(Set dst (Load2I mem)); | |
| 5911 ins_cost(MEMORY_REF_COST); | |
| 5912 size(4); | |
| 5913 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5914 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5915 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5916 ins_pipe(floadD_mem); |
| 5917 %} | |
| 5918 | |
| 5919 // Load Range | |
| 5920 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5921 match(Set dst (LoadRange mem)); | |
| 5922 ins_cost(MEMORY_REF_COST); | |
| 5923 | |
| 5924 size(4); | |
| 5925 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5926 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5927 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5928 ins_pipe(iload_mem); |
| 5929 %} | |
| 5930 | |
| 5931 // Load Integer into %f register (for fitos/fitod) | |
| 5932 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5933 match(Set dst (LoadI mem)); | |
| 5934 ins_cost(MEMORY_REF_COST); | |
| 5935 size(4); | |
| 5936 | |
| 5937 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5938 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5939 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5940 ins_pipe(floadF_mem); |
| 5941 %} | |
| 5942 | |
| 5943 // Load Pointer | |
| 5944 instruct loadP(iRegP dst, memory mem) %{ | |
| 5945 match(Set dst (LoadP mem)); | |
| 5946 ins_cost(MEMORY_REF_COST); | |
| 5947 size(4); | |
| 5948 | |
| 5949 #ifndef _LP64 | |
| 5950 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5951 ins_encode %{ |
| 5952 __ lduw($mem$$Address, $dst$$Register); | |
| 5953 %} | |
| 0 | 5954 #else |
| 5955 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5956 ins_encode %{ |
| 5957 __ ldx($mem$$Address, $dst$$Register); | |
| 5958 %} | |
| 0 | 5959 #endif |
| 5960 ins_pipe(iload_mem); | |
| 5961 %} | |
| 5962 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5963 // Load Compressed Pointer |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5964 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5965 match(Set dst (LoadN mem)); |
| 5966 ins_cost(MEMORY_REF_COST); | |
| 5967 size(4); | |
| 5968 | |
| 5969 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5970 ins_encode %{ | |
| 5971 __ lduw($mem$$Address, $dst$$Register); | |
| 5972 %} | |
| 5973 ins_pipe(iload_mem); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5974 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5975 |
| 0 | 5976 // Load Klass Pointer |
| 5977 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5978 match(Set dst (LoadKlass mem)); | |
| 5979 ins_cost(MEMORY_REF_COST); | |
| 5980 size(4); | |
| 5981 | |
| 5982 #ifndef _LP64 | |
| 5983 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 5984 ins_encode %{ |
| 5985 __ lduw($mem$$Address, $dst$$Register); | |
| 5986 %} | |
| 0 | 5987 #else |
| 5988 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 5989 ins_encode %{ |
| 5990 __ ldx($mem$$Address, $dst$$Register); | |
| 5991 %} | |
| 0 | 5992 #endif |
| 5993 ins_pipe(iload_mem); | |
| 5994 %} | |
| 5995 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5996 // Load narrow Klass Pointer |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5997 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5998 match(Set dst (LoadNKlass mem)); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5999 ins_cost(MEMORY_REF_COST); |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
164
diff
changeset
|
6000 size(4); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6001 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6002 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6003 ins_encode %{ |
| 727 | 6004 __ lduw($mem$$Address, $dst$$Register); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6005 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6006 ins_pipe(iload_mem); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6007 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6008 |
| 0 | 6009 // Load Double |
| 6010 instruct loadD(regD dst, memory mem) %{ | |
| 6011 match(Set dst (LoadD mem)); | |
| 6012 ins_cost(MEMORY_REF_COST); | |
| 6013 | |
| 6014 size(4); | |
| 6015 format %{ "LDDF $mem,$dst" %} | |
| 6016 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6017 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6018 ins_pipe(floadD_mem); |
| 6019 %} | |
| 6020 | |
| 6021 // Load Double - UNaligned | |
| 6022 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6023 match(Set dst (LoadD_unaligned mem)); | |
| 6024 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6025 size(8); | |
| 6026 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6027 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6028 opcode(Assembler::ldf_op3); | |
| 6029 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6030 ins_pipe(iload_mem); | |
| 6031 %} | |
| 6032 | |
| 6033 // Load Float | |
| 6034 instruct loadF(regF dst, memory mem) %{ | |
| 6035 match(Set dst (LoadF mem)); | |
| 6036 ins_cost(MEMORY_REF_COST); | |
| 6037 | |
| 6038 size(4); | |
| 6039 format %{ "LDF $mem,$dst" %} | |
| 6040 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6041 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6042 ins_pipe(floadF_mem); |
| 6043 %} | |
| 6044 | |
| 6045 // Load Constant | |
| 6046 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6047 match(Set dst src); | |
| 6048 ins_cost(DEFAULT_COST * 3/2); | |
| 6049 format %{ "SET $src,$dst" %} | |
| 6050 ins_encode( Set32(src, dst) ); | |
| 6051 ins_pipe(ialu_hi_lo_reg); | |
| 6052 %} | |
| 6053 | |
| 6054 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6055 match(Set dst src); | |
| 6056 | |
| 6057 size(4); | |
| 6058 format %{ "MOV $src,$dst" %} | |
| 6059 ins_encode( Set13( src, dst ) ); | |
| 6060 ins_pipe(ialu_imm); | |
| 6061 %} | |
| 6062 | |
| 2008 | 6063 #ifndef _LP64 |
| 6064 instruct loadConP(iRegP dst, immP con) %{ | |
| 6065 match(Set dst con); | |
| 6066 ins_cost(DEFAULT_COST * 3/2); | |
| 6067 format %{ "SET $con,$dst\t!ptr" %} | |
| 6068 ins_encode %{ | |
| 6069 // [RGV] This next line should be generated from ADLC | |
| 6070 if (_opnds[1]->constant_is_oop()) { | |
| 6071 intptr_t val = $con$$constant; | |
| 6072 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6073 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6074 __ set($con$$constant, $dst$$Register); | |
| 6075 } | |
| 6076 %} | |
| 6077 ins_pipe(loadConP); | |
| 6078 %} | |
| 6079 #else | |
| 6080 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6081 match(Set dst con); | |
| 0 | 6082 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6083 format %{ "SET $con,$dst\t! ptr" %} |
| 6084 ins_encode %{ | |
| 6085 // [RGV] This next line should be generated from ADLC | |
| 6086 if (_opnds[1]->constant_is_oop()) { | |
| 6087 intptr_t val = $con$$constant; | |
| 6088 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6089 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6090 __ set($con$$constant, $dst$$Register); | |
| 6091 } | |
| 6092 %} | |
| 0 | 6093 ins_pipe(loadConP); |
| 2008 | 6094 %} |
| 6095 | |
| 6096 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6097 match(Set dst con); | |
| 6098 ins_cost(MEMORY_REF_COST); | |
| 6099 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6100 ins_encode %{ | |
|
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6101 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6102 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6103 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6104 ins_pipe(loadConP); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6105 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6106 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6107 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6108 match(Set dst con); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6109 ins_cost(DEFAULT_COST * 3/2); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6110 format %{ "SET $con,$dst\t! non-oop ptr" %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6111 ins_encode %{ |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6112 __ set($con$$constant, $dst$$Register); |
| 2008 | 6113 %} |
| 6114 ins_pipe(loadConP); | |
| 6115 %} | |
| 6116 #endif // _LP64 | |
| 0 | 6117 |
| 6118 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6119 match(Set dst src); | |
| 6120 | |
| 6121 size(4); | |
| 6122 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6123 ins_encode %{ |
| 6124 __ clr($dst$$Register); | |
| 6125 %} | |
| 0 | 6126 ins_pipe(ialu_imm); |
| 6127 %} | |
| 6128 | |
| 6129 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6130 match(Set dst src); | |
| 6131 ins_cost(DEFAULT_COST); | |
| 6132 format %{ "SET $src,$dst\t!ptr" %} | |
| 6133 ins_encode %{ | |
| 727 | 6134 AddressLiteral polling_page(os::get_polling_page()); |
| 6135 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6136 %} |
| 6137 ins_pipe(loadConP_poll); | |
| 6138 %} | |
| 6139 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6140 instruct loadConN0(iRegN dst, immN0 src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6141 match(Set dst src); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6142 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6143 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6144 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6145 ins_encode %{ |
| 6146 __ clr($dst$$Register); | |
| 6147 %} | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6148 ins_pipe(ialu_imm); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6149 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6150 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6151 instruct loadConN(iRegN dst, immN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6152 match(Set dst src); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6153 ins_cost(DEFAULT_COST * 3/2); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6154 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6155 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6156 Register dst = $dst$$Register; |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6157 __ set_narrow_oop((jobject)$src$$constant, dst); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6158 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6159 ins_pipe(ialu_hi_lo_reg); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6160 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6161 |
| 2008 | 6162 // Materialize long value (predicated by immL_cheap). |
| 6163 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6164 match(Set dst con); | |
| 0 | 6165 effect(KILL tmp); |
| 2008 | 6166 ins_cost(DEFAULT_COST * 3); |
| 6167 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6168 ins_encode %{ | |
| 6169 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6170 %} | |
| 6171 ins_pipe(loadConL); | |
| 6172 %} | |
| 6173 | |
| 6174 // Load long value from constant table (predicated by immL_expensive). | |
| 6175 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6176 match(Set dst con); | |
| 6177 ins_cost(MEMORY_REF_COST); | |
| 6178 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6179 ins_encode %{ | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6180 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6181 __ ldx($constanttablebase, con_offset, $dst$$Register); |
| 2008 | 6182 %} |
| 0 | 6183 ins_pipe(loadConL); |
| 6184 %} | |
| 6185 | |
| 6186 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6187 match(Set dst src); | |
| 6188 ins_cost(DEFAULT_COST); | |
| 6189 size(4); | |
| 6190 format %{ "CLR $dst\t! long" %} | |
| 6191 ins_encode( Set13( src, dst ) ); | |
| 6192 ins_pipe(ialu_imm); | |
| 6193 %} | |
| 6194 | |
| 6195 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6196 match(Set dst src); | |
| 6197 ins_cost(DEFAULT_COST * 2); | |
| 6198 | |
| 6199 size(4); | |
| 6200 format %{ "MOV $src,$dst\t! long" %} | |
| 6201 ins_encode( Set13( src, dst ) ); | |
| 6202 ins_pipe(ialu_imm); | |
| 6203 %} | |
| 6204 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6205 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
| 2008 | 6206 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6207 effect(KILL tmp); |
| 2008 | 6208 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
| 727 | 6209 ins_encode %{ |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6210 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6211 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
| 727 | 6212 %} |
| 0 | 6213 ins_pipe(loadConFD); |
| 6214 %} | |
| 6215 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6216 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
| 2008 | 6217 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6218 effect(KILL tmp); |
| 2008 | 6219 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
| 727 | 6220 ins_encode %{ |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6221 // XXX This is a quick fix for 6833573. |
| 2008 | 6222 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6223 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6224 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 727 | 6225 %} |
| 0 | 6226 ins_pipe(loadConFD); |
| 6227 %} | |
| 6228 | |
| 6229 // Prefetch instructions. | |
| 6230 // Must be safe to execute with invalid address (cannot fault). | |
| 6231 | |
| 6232 instruct prefetchr( memory mem ) %{ | |
| 6233 match( PrefetchRead mem ); | |
| 6234 ins_cost(MEMORY_REF_COST); | |
| 6235 | |
| 6236 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6237 opcode(Assembler::prefetch_op3); | |
| 6238 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6239 ins_pipe(iload_mem); | |
| 6240 %} | |
| 6241 | |
| 6242 instruct prefetchw( memory mem ) %{ | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6243 predicate(AllocatePrefetchStyle != 3 ); |
| 0 | 6244 match( PrefetchWrite mem ); |
| 6245 ins_cost(MEMORY_REF_COST); | |
| 6246 | |
| 6247 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6248 opcode(Assembler::prefetch_op3); | |
| 6249 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6250 ins_pipe(iload_mem); | |
| 6251 %} | |
| 6252 | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6253 // Use BIS instruction to prefetch. |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6254 instruct prefetchw_bis( memory mem ) %{ |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6255 predicate(AllocatePrefetchStyle == 3); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6256 match( PrefetchWrite mem ); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6257 ins_cost(MEMORY_REF_COST); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6258 |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6259 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6260 ins_encode %{ |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6261 Register base = as_Register($mem$$base); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6262 int disp = $mem$$disp; |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6263 if (disp != 0) { |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6264 __ add(base, AllocatePrefetchStepSize, base); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6265 } |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6266 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6267 %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6268 ins_pipe(istore_mem_reg); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6269 %} |
| 0 | 6270 |
| 6271 //----------Store Instructions------------------------------------------------- | |
| 6272 // Store Byte | |
| 6273 instruct storeB(memory mem, iRegI src) %{ | |
| 6274 match(Set mem (StoreB mem src)); | |
| 6275 ins_cost(MEMORY_REF_COST); | |
| 6276 | |
| 6277 size(4); | |
| 6278 format %{ "STB $src,$mem\t! byte" %} | |
| 6279 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6280 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6281 ins_pipe(istore_mem_reg); |
| 6282 %} | |
| 6283 | |
| 6284 instruct storeB0(memory mem, immI0 src) %{ | |
| 6285 match(Set mem (StoreB mem src)); | |
| 6286 ins_cost(MEMORY_REF_COST); | |
| 6287 | |
| 6288 size(4); | |
| 6289 format %{ "STB $src,$mem\t! byte" %} | |
| 6290 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6291 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6292 ins_pipe(istore_mem_zero); |
| 6293 %} | |
| 6294 | |
| 6295 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6296 match(Set mem (StoreCM mem src)); | |
| 6297 ins_cost(MEMORY_REF_COST); | |
| 6298 | |
| 6299 size(4); | |
| 6300 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6301 opcode(Assembler::stb_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6302 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6303 ins_pipe(istore_mem_zero); |
| 6304 %} | |
| 6305 | |
| 6306 // Store Char/Short | |
| 6307 instruct storeC(memory mem, iRegI src) %{ | |
| 6308 match(Set mem (StoreC mem src)); | |
| 6309 ins_cost(MEMORY_REF_COST); | |
| 6310 | |
| 6311 size(4); | |
| 6312 format %{ "STH $src,$mem\t! short" %} | |
| 6313 opcode(Assembler::sth_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6314 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6315 ins_pipe(istore_mem_reg); |
| 6316 %} | |
| 6317 | |
| 6318 instruct storeC0(memory mem, immI0 src) %{ | |
| 6319 match(Set mem (StoreC mem src)); | |
| 6320 ins_cost(MEMORY_REF_COST); | |
| 6321 | |
| 6322 size(4); | |
| 6323 format %{ "STH $src,$mem\t! short" %} | |
| 6324 opcode(Assembler::sth_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6325 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6326 ins_pipe(istore_mem_zero); |
| 6327 %} | |
| 6328 | |
| 6329 // Store Integer | |
| 6330 instruct storeI(memory mem, iRegI src) %{ | |
| 6331 match(Set mem (StoreI mem src)); | |
| 6332 ins_cost(MEMORY_REF_COST); | |
| 6333 | |
| 6334 size(4); | |
| 6335 format %{ "STW $src,$mem" %} | |
| 6336 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6337 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6338 ins_pipe(istore_mem_reg); |
| 6339 %} | |
| 6340 | |
| 6341 // Store Long | |
| 6342 instruct storeL(memory mem, iRegL src) %{ | |
| 6343 match(Set mem (StoreL mem src)); | |
| 6344 ins_cost(MEMORY_REF_COST); | |
| 6345 size(4); | |
| 6346 format %{ "STX $src,$mem\t! long" %} | |
| 6347 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6348 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6349 ins_pipe(istore_mem_reg); |
| 6350 %} | |
| 6351 | |
| 6352 instruct storeI0(memory mem, immI0 src) %{ | |
| 6353 match(Set mem (StoreI mem src)); | |
| 6354 ins_cost(MEMORY_REF_COST); | |
| 6355 | |
| 6356 size(4); | |
| 6357 format %{ "STW $src,$mem" %} | |
| 6358 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6359 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6360 ins_pipe(istore_mem_zero); |
| 6361 %} | |
| 6362 | |
| 6363 instruct storeL0(memory mem, immL0 src) %{ | |
| 6364 match(Set mem (StoreL mem src)); | |
| 6365 ins_cost(MEMORY_REF_COST); | |
| 6366 | |
| 6367 size(4); | |
| 6368 format %{ "STX $src,$mem" %} | |
| 6369 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6370 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6371 ins_pipe(istore_mem_zero); |
| 6372 %} | |
| 6373 | |
| 6374 // Store Integer from float register (used after fstoi) | |
| 6375 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6376 match(Set mem (StoreI mem src)); | |
| 6377 ins_cost(MEMORY_REF_COST); | |
| 6378 | |
| 6379 size(4); | |
| 6380 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6381 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6382 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6383 ins_pipe(fstoreF_mem_reg); |
| 6384 %} | |
| 6385 | |
| 6386 // Store Pointer | |
| 6387 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6388 match(Set dst (StoreP dst src)); | |
| 6389 ins_cost(MEMORY_REF_COST); | |
| 6390 size(4); | |
| 6391 | |
| 6392 #ifndef _LP64 | |
| 6393 format %{ "STW $src,$dst\t! ptr" %} | |
| 6394 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6395 #else | |
| 6396 format %{ "STX $src,$dst\t! ptr" %} | |
| 6397 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6398 #endif | |
| 6399 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6400 ins_pipe(istore_mem_spORreg); | |
| 6401 %} | |
| 6402 | |
| 6403 instruct storeP0(memory dst, immP0 src) %{ | |
| 6404 match(Set dst (StoreP dst src)); | |
| 6405 ins_cost(MEMORY_REF_COST); | |
| 6406 size(4); | |
| 6407 | |
| 6408 #ifndef _LP64 | |
| 6409 format %{ "STW $src,$dst\t! ptr" %} | |
| 6410 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6411 #else | |
| 6412 format %{ "STX $src,$dst\t! ptr" %} | |
| 6413 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6414 #endif | |
| 6415 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6416 ins_pipe(istore_mem_zero); | |
| 6417 %} | |
| 6418 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6419 // Store Compressed Pointer |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6420 instruct storeN(memory dst, iRegN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6421 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6422 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6423 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6424 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6425 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6426 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6427 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6428 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6429 Register src = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6430 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6431 __ stw(src, base, index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6432 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6433 __ stw(src, base, $dst$$disp); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6434 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6435 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6436 ins_pipe(istore_mem_spORreg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6437 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6438 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6439 instruct storeN0(memory dst, immN0 src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6440 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6441 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6442 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6443 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6444 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6445 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6446 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6447 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6448 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6449 __ stw(0, base, index); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6450 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6451 __ stw(0, base, $dst$$disp); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6452 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6453 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6454 ins_pipe(istore_mem_zero); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6455 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6456 |
| 0 | 6457 // Store Double |
| 6458 instruct storeD( memory mem, regD src) %{ | |
| 6459 match(Set mem (StoreD mem src)); | |
| 6460 ins_cost(MEMORY_REF_COST); | |
| 6461 | |
| 6462 size(4); | |
| 6463 format %{ "STDF $src,$mem" %} | |
| 6464 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6465 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6466 ins_pipe(fstoreD_mem_reg); |
| 6467 %} | |
| 6468 | |
| 6469 instruct storeD0( memory mem, immD0 src) %{ | |
| 6470 match(Set mem (StoreD mem src)); | |
| 6471 ins_cost(MEMORY_REF_COST); | |
| 6472 | |
| 6473 size(4); | |
| 6474 format %{ "STX $src,$mem" %} | |
| 6475 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6476 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6477 ins_pipe(fstoreD_mem_zero); |
| 6478 %} | |
| 6479 | |
| 6480 // Store Float | |
| 6481 instruct storeF( memory mem, regF src) %{ | |
| 6482 match(Set mem (StoreF mem src)); | |
| 6483 ins_cost(MEMORY_REF_COST); | |
| 6484 | |
| 6485 size(4); | |
| 6486 format %{ "STF $src,$mem" %} | |
| 6487 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6488 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6489 ins_pipe(fstoreF_mem_reg); |
| 6490 %} | |
| 6491 | |
| 6492 instruct storeF0( memory mem, immF0 src) %{ | |
| 6493 match(Set mem (StoreF mem src)); | |
| 6494 ins_cost(MEMORY_REF_COST); | |
| 6495 | |
| 6496 size(4); | |
| 6497 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6498 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6499 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6500 ins_pipe(fstoreF_mem_zero); |
| 6501 %} | |
| 6502 | |
| 6503 // Store Aligned Packed Bytes in Double register to memory | |
| 6504 instruct storeA8B(memory mem, regD src) %{ | |
| 6505 match(Set mem (Store8B mem src)); | |
| 6506 ins_cost(MEMORY_REF_COST); | |
| 6507 size(4); | |
| 6508 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 6509 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6510 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6511 ins_pipe(fstoreD_mem_reg); |
| 6512 %} | |
| 6513 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6514 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6515 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6516 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6517 match(Set dst (EncodeP src)); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6518 format %{ "encode_heap_oop $src, $dst" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6519 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6520 __ encode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6521 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6522 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6523 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6524 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6525 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6526 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6527 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6528 format %{ "encode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6529 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6530 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6531 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6532 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6533 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6534 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6535 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6536 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6537 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6538 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6539 format %{ "decode_heap_oop $src, $dst" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6540 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6541 __ decode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6542 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6543 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6544 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6545 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6546 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6547 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6548 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6549 match(Set dst (DecodeN src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6550 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6551 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6552 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6553 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6554 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6555 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6556 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6557 |
| 0 | 6558 // Store Zero into Aligned Packed Bytes |
| 6559 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6560 match(Set mem (Store8B mem zero)); | |
| 6561 ins_cost(MEMORY_REF_COST); | |
| 6562 size(4); | |
| 6563 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6564 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6565 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6566 ins_pipe(fstoreD_mem_zero); |
| 6567 %} | |
| 6568 | |
| 6569 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6570 instruct storeA4C(memory mem, regD src) %{ | |
| 6571 match(Set mem (Store4C mem src)); | |
| 6572 ins_cost(MEMORY_REF_COST); | |
| 6573 size(4); | |
| 6574 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6575 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6576 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6577 ins_pipe(fstoreD_mem_reg); |
| 6578 %} | |
| 6579 | |
| 6580 // Store Zero into Aligned Packed Chars/Shorts | |
| 6581 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6582 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6583 ins_cost(MEMORY_REF_COST); | |
| 6584 size(4); | |
| 6585 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6586 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6587 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6588 ins_pipe(fstoreD_mem_zero); |
| 6589 %} | |
| 6590 | |
| 6591 // Store Aligned Packed Ints in Double register to memory | |
| 6592 instruct storeA2I(memory mem, regD src) %{ | |
| 6593 match(Set mem (Store2I mem src)); | |
| 6594 ins_cost(MEMORY_REF_COST); | |
| 6595 size(4); | |
| 6596 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6597 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6598 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6599 ins_pipe(fstoreD_mem_reg); |
| 6600 %} | |
| 6601 | |
| 6602 // Store Zero into Aligned Packed Ints | |
| 6603 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6604 match(Set mem (Store2I mem zero)); | |
| 6605 ins_cost(MEMORY_REF_COST); | |
| 6606 size(4); | |
| 6607 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6608 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6609 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6610 ins_pipe(fstoreD_mem_zero); |
| 6611 %} | |
| 6612 | |
| 6613 | |
| 6614 //----------MemBar Instructions----------------------------------------------- | |
| 6615 // Memory barrier flavors | |
| 6616 | |
| 6617 instruct membar_acquire() %{ | |
| 6618 match(MemBarAcquire); | |
| 6619 ins_cost(4*MEMORY_REF_COST); | |
| 6620 | |
| 6621 size(0); | |
| 6622 format %{ "MEMBAR-acquire" %} | |
| 6623 ins_encode( enc_membar_acquire ); | |
| 6624 ins_pipe(long_memory_op); | |
| 6625 %} | |
| 6626 | |
| 6627 instruct membar_acquire_lock() %{ | |
| 6628 match(MemBarAcquire); | |
| 6629 predicate(Matcher::prior_fast_lock(n)); | |
| 6630 ins_cost(0); | |
| 6631 | |
| 6632 size(0); | |
| 6633 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6634 ins_encode( ); | |
| 6635 ins_pipe(empty); | |
| 6636 %} | |
| 6637 | |
| 6638 instruct membar_release() %{ | |
| 6639 match(MemBarRelease); | |
| 6640 ins_cost(4*MEMORY_REF_COST); | |
| 6641 | |
| 6642 size(0); | |
| 6643 format %{ "MEMBAR-release" %} | |
| 6644 ins_encode( enc_membar_release ); | |
| 6645 ins_pipe(long_memory_op); | |
| 6646 %} | |
| 6647 | |
| 6648 instruct membar_release_lock() %{ | |
| 6649 match(MemBarRelease); | |
| 6650 predicate(Matcher::post_fast_unlock(n)); | |
| 6651 ins_cost(0); | |
| 6652 | |
| 6653 size(0); | |
| 6654 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6655 ins_encode( ); | |
| 6656 ins_pipe(empty); | |
| 6657 %} | |
| 6658 | |
| 6659 instruct membar_volatile() %{ | |
| 6660 match(MemBarVolatile); | |
| 6661 ins_cost(4*MEMORY_REF_COST); | |
| 6662 | |
| 6663 size(4); | |
| 6664 format %{ "MEMBAR-volatile" %} | |
| 6665 ins_encode( enc_membar_volatile ); | |
| 6666 ins_pipe(long_memory_op); | |
| 6667 %} | |
| 6668 | |
| 6669 instruct unnecessary_membar_volatile() %{ | |
| 6670 match(MemBarVolatile); | |
| 6671 predicate(Matcher::post_store_load_barrier(n)); | |
| 6672 ins_cost(0); | |
| 6673 | |
| 6674 size(0); | |
| 6675 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6676 ins_encode( ); | |
| 6677 ins_pipe(empty); | |
| 6678 %} | |
| 6679 | |
| 6680 //----------Register Move Instructions----------------------------------------- | |
| 6681 instruct roundDouble_nop(regD dst) %{ | |
| 6682 match(Set dst (RoundDouble dst)); | |
| 6683 ins_cost(0); | |
| 6684 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6685 ins_encode( ); | |
| 6686 ins_pipe(empty); | |
| 6687 %} | |
| 6688 | |
| 6689 | |
| 6690 instruct roundFloat_nop(regF dst) %{ | |
| 6691 match(Set dst (RoundFloat dst)); | |
| 6692 ins_cost(0); | |
| 6693 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6694 ins_encode( ); | |
| 6695 ins_pipe(empty); | |
| 6696 %} | |
| 6697 | |
| 6698 | |
| 6699 // Cast Index to Pointer for unsafe natives | |
| 6700 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6701 match(Set dst (CastX2P src)); | |
| 6702 | |
| 6703 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6704 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6705 ins_pipe(ialu_reg); | |
| 6706 %} | |
| 6707 | |
| 6708 // Cast Pointer to Index for unsafe natives | |
| 6709 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6710 match(Set dst (CastP2X src)); | |
| 6711 | |
| 6712 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6713 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6714 ins_pipe(ialu_reg); | |
| 6715 %} | |
| 6716 | |
| 6717 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6718 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6719 match(Set stkSlot src); // chain rule | |
| 6720 ins_cost(MEMORY_REF_COST); | |
| 6721 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6722 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6723 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6724 ins_pipe(fstoreD_stk_reg); |
| 6725 %} | |
| 6726 | |
| 6727 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6728 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6729 match(Set dst stkSlot); // chain rule | |
| 6730 ins_cost(MEMORY_REF_COST); | |
| 6731 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6732 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6733 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6734 ins_pipe(floadD_stk); |
| 6735 %} | |
| 6736 | |
| 6737 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6738 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6739 match(Set stkSlot src); // chain rule | |
| 6740 ins_cost(MEMORY_REF_COST); | |
| 6741 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6742 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6743 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6744 ins_pipe(fstoreF_stk_reg); |
| 6745 %} | |
| 6746 | |
| 6747 //----------Conditional Move--------------------------------------------------- | |
| 6748 // Conditional move | |
| 6749 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6750 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6751 ins_cost(150); | |
| 6752 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6753 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6754 ins_pipe(ialu_reg); | |
| 6755 %} | |
| 6756 | |
| 6757 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6758 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6759 ins_cost(140); | |
| 6760 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6761 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6762 ins_pipe(ialu_imm); | |
| 6763 %} | |
| 6764 | |
| 6765 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6766 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6767 ins_cost(150); | |
| 6768 size(4); | |
| 6769 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6771 ins_pipe(ialu_reg); | |
| 6772 %} | |
| 6773 | |
| 6774 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6775 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6776 ins_cost(140); | |
| 6777 size(4); | |
| 6778 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6779 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6780 ins_pipe(ialu_imm); | |
| 6781 %} | |
| 6782 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6783 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6784 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6785 ins_cost(150); | |
| 6786 size(4); | |
| 6787 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6789 ins_pipe(ialu_reg); | |
| 6790 %} | |
| 6791 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6792 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6793 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6794 ins_cost(140); | |
| 6795 size(4); | |
| 6796 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6797 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6798 ins_pipe(ialu_imm); | |
| 6799 %} | |
| 6800 | |
| 6801 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6802 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6803 ins_cost(150); | |
| 6804 size(4); | |
| 6805 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6806 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6807 ins_pipe(ialu_reg); | |
| 6808 %} | |
| 6809 | |
| 6810 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6811 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6812 ins_cost(140); | |
| 6813 size(4); | |
| 6814 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6815 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6816 ins_pipe(ialu_imm); | |
| 6817 %} | |
| 6818 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6819 // Conditional move for RegN. Only cmov(reg,reg). |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6820 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6821 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6822 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6823 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6825 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6826 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6827 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6828 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6829 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6830 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6831 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6832 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6833 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6834 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6835 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6836 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6837 |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6838 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6839 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6840 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6841 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6842 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6843 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6844 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6845 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6846 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6847 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6848 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6849 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6850 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6851 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6852 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6853 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6854 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6855 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6856 |
| 0 | 6857 // Conditional move |
| 6858 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6859 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6860 ins_cost(150); | |
| 6861 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6862 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6863 ins_pipe(ialu_reg); | |
| 6864 %} | |
| 6865 | |
| 6866 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6867 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6868 ins_cost(140); | |
| 6869 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6870 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6871 ins_pipe(ialu_imm); | |
| 6872 %} | |
| 6873 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6874 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6875 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6876 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6877 ins_cost(150); | |
| 6878 | |
| 6879 size(4); | |
| 6880 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6881 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6882 ins_pipe(ialu_reg); | |
| 6883 %} | |
| 6884 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6885 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6886 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6887 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6888 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6889 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6890 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6891 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6892 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6893 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6894 |
| 0 | 6895 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6896 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6897 ins_cost(140); | |
| 6898 | |
| 6899 size(4); | |
| 6900 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6901 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6902 ins_pipe(ialu_imm); | |
| 6903 %} | |
| 6904 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6905 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6906 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6907 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6908 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6909 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6910 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6911 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6912 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6913 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6914 |
| 0 | 6915 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6916 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6917 ins_cost(150); | |
| 6918 size(4); | |
| 6919 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6920 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6921 ins_pipe(ialu_imm); | |
| 6922 %} | |
| 6923 | |
| 6924 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6925 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6926 ins_cost(140); | |
| 6927 size(4); | |
| 6928 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6929 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6930 ins_pipe(ialu_imm); | |
| 6931 %} | |
| 6932 | |
| 6933 // Conditional move | |
| 6934 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6935 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6936 ins_cost(150); | |
| 6937 opcode(0x101); | |
| 6938 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6940 ins_pipe(int_conditional_float_move); | |
| 6941 %} | |
| 6942 | |
| 6943 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6944 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6945 ins_cost(150); | |
| 6946 | |
| 6947 size(4); | |
| 6948 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6949 opcode(0x101); | |
| 6950 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6951 ins_pipe(int_conditional_float_move); | |
| 6952 %} | |
| 6953 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6954 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6955 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6956 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6957 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6958 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6959 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6960 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6961 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6962 ins_pipe(int_conditional_float_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6963 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6964 |
| 0 | 6965 // Conditional move, |
| 6966 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6967 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6968 ins_cost(150); | |
| 6969 size(4); | |
| 6970 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6971 opcode(0x1); | |
| 6972 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6973 ins_pipe(int_conditional_double_move); | |
| 6974 %} | |
| 6975 | |
| 6976 // Conditional move | |
| 6977 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6978 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6979 ins_cost(150); | |
| 6980 size(4); | |
| 6981 opcode(0x102); | |
| 6982 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6983 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6984 ins_pipe(int_conditional_double_move); | |
| 6985 %} | |
| 6986 | |
| 6987 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 6988 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 6989 ins_cost(150); | |
| 6990 | |
| 6991 size(4); | |
| 6992 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 6993 opcode(0x102); | |
| 6994 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6995 ins_pipe(int_conditional_double_move); | |
| 6996 %} | |
| 6997 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6998 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6999 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7000 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7001 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7002 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7003 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7004 opcode(0x102); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7005 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7006 ins_pipe(int_conditional_double_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7007 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7008 |
| 0 | 7009 // Conditional move, |
| 7010 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 7011 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 7012 ins_cost(150); | |
| 7013 size(4); | |
| 7014 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 7015 opcode(0x2); | |
| 7016 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7017 ins_pipe(int_conditional_double_move); | |
| 7018 %} | |
| 7019 | |
| 7020 // Conditional move | |
| 7021 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7022 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7023 ins_cost(150); | |
| 7024 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7025 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7026 ins_pipe(ialu_reg); | |
| 7027 %} | |
| 7028 | |
| 7029 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7030 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7031 ins_cost(140); | |
| 7032 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7033 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7034 ins_pipe(ialu_imm); | |
| 7035 %} | |
| 7036 | |
| 7037 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7038 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7039 ins_cost(150); | |
| 7040 | |
| 7041 size(4); | |
| 7042 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7043 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7044 ins_pipe(ialu_reg); | |
| 7045 %} | |
| 7046 | |
| 7047 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7048 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7049 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7050 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7051 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7052 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7053 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7054 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7055 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7056 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7057 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7058 |
| 0 | 7059 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7060 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7061 ins_cost(150); | |
| 7062 | |
| 7063 size(4); | |
| 7064 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7065 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7066 ins_pipe(ialu_reg); | |
| 7067 %} | |
| 7068 | |
| 7069 | |
| 7070 | |
| 7071 //----------OS and Locking Instructions---------------------------------------- | |
| 7072 | |
| 7073 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7074 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7075 // for this guy. | |
| 7076 instruct tlsLoadP(g2RegP dst) %{ | |
| 7077 match(Set dst (ThreadLocal)); | |
| 7078 | |
| 7079 size(0); | |
| 7080 ins_cost(0); | |
| 7081 format %{ "# TLS is in G2" %} | |
| 7082 ins_encode( /*empty encoding*/ ); | |
| 7083 ins_pipe(ialu_none); | |
| 7084 %} | |
| 7085 | |
| 7086 instruct checkCastPP( iRegP dst ) %{ | |
| 7087 match(Set dst (CheckCastPP dst)); | |
| 7088 | |
| 7089 size(0); | |
| 7090 format %{ "# checkcastPP of $dst" %} | |
| 7091 ins_encode( /*empty encoding*/ ); | |
| 7092 ins_pipe(empty); | |
| 7093 %} | |
| 7094 | |
| 7095 | |
| 7096 instruct castPP( iRegP dst ) %{ | |
| 7097 match(Set dst (CastPP dst)); | |
| 7098 format %{ "# castPP of $dst" %} | |
| 7099 ins_encode( /*empty encoding*/ ); | |
| 7100 ins_pipe(empty); | |
| 7101 %} | |
| 7102 | |
| 7103 instruct castII( iRegI dst ) %{ | |
| 7104 match(Set dst (CastII dst)); | |
| 7105 format %{ "# castII of $dst" %} | |
| 7106 ins_encode( /*empty encoding*/ ); | |
| 7107 ins_cost(0); | |
| 7108 ins_pipe(empty); | |
| 7109 %} | |
| 7110 | |
| 7111 //----------Arithmetic Instructions-------------------------------------------- | |
| 7112 // Addition Instructions | |
| 7113 // Register Addition | |
| 7114 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7115 match(Set dst (AddI src1 src2)); | |
| 7116 | |
| 7117 size(4); | |
| 7118 format %{ "ADD $src1,$src2,$dst" %} | |
| 7119 ins_encode %{ | |
| 7120 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7121 %} | |
| 7122 ins_pipe(ialu_reg_reg); | |
| 7123 %} | |
| 7124 | |
| 7125 // Immediate Addition | |
| 7126 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7127 match(Set dst (AddI src1 src2)); | |
| 7128 | |
| 7129 size(4); | |
| 7130 format %{ "ADD $src1,$src2,$dst" %} | |
| 7131 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7132 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7133 ins_pipe(ialu_reg_imm); | |
| 7134 %} | |
| 7135 | |
| 7136 // Pointer Register Addition | |
| 7137 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7138 match(Set dst (AddP src1 src2)); | |
| 7139 | |
| 7140 size(4); | |
| 7141 format %{ "ADD $src1,$src2,$dst" %} | |
| 7142 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7143 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7144 ins_pipe(ialu_reg_reg); | |
| 7145 %} | |
| 7146 | |
| 7147 // Pointer Immediate Addition | |
| 7148 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7149 match(Set dst (AddP src1 src2)); | |
| 7150 | |
| 7151 size(4); | |
| 7152 format %{ "ADD $src1,$src2,$dst" %} | |
| 7153 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7154 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7155 ins_pipe(ialu_reg_imm); | |
| 7156 %} | |
| 7157 | |
| 7158 // Long Addition | |
| 7159 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7160 match(Set dst (AddL src1 src2)); | |
| 7161 | |
| 7162 size(4); | |
| 7163 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7164 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7165 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7166 ins_pipe(ialu_reg_reg); | |
| 7167 %} | |
| 7168 | |
| 7169 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7170 match(Set dst (AddL src1 con)); | |
| 7171 | |
| 7172 size(4); | |
| 7173 format %{ "ADD $src1,$con,$dst" %} | |
| 7174 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7175 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7176 ins_pipe(ialu_reg_imm); | |
| 7177 %} | |
| 7178 | |
| 7179 //----------Conditional_store-------------------------------------------------- | |
| 7180 // Conditional-store of the updated heap-top. | |
| 7181 // Used during allocation of the shared heap. | |
| 7182 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7183 | |
| 7184 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7185 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7186 match(Set dst (LoadPLocked mem)); | |
| 7187 ins_cost(MEMORY_REF_COST); | |
| 7188 | |
| 7189 #ifndef _LP64 | |
| 7190 size(4); | |
| 7191 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7192 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7193 #else | |
| 7194 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7195 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7196 #endif | |
| 7197 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7198 ins_pipe(iload_mem); | |
| 7199 %} | |
| 7200 | |
| 7201 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 7202 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 7203 match(Set dst (LoadLLocked mem)); | |
| 7204 ins_cost(MEMORY_REF_COST); | |
| 7205 size(4); | |
| 7206 format %{ "LDX $mem,$dst\t! long" %} | |
| 7207 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
7208 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 7209 ins_pipe(iload_mem); |
| 7210 %} | |
| 7211 | |
| 7212 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7213 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7214 effect( KILL newval ); | |
| 7215 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7216 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7217 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7218 ins_pipe( long_memory_op ); | |
| 7219 %} | |
| 7220 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7221 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7222 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7223 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7224 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7225 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7226 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7227 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7228 ins_pipe( long_memory_op ); |
| 7229 %} | |
| 7230 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7231 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7232 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7233 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7234 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7235 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7236 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7237 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7238 ins_pipe( long_memory_op ); |
| 7239 %} | |
| 7240 | |
| 7241 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7242 | |
| 7243 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7244 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7245 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7246 format %{ | |
| 7247 "MOV $newval,O7\n\t" | |
| 7248 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7249 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7250 "MOV 1,$res\n\t" | |
| 7251 "MOVne xcc,R_G0,$res" | |
| 7252 %} | |
| 7253 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7254 enc_lflags_ne_to_boolean(res) ); | |
| 7255 ins_pipe( long_memory_op ); | |
| 7256 %} | |
| 7257 | |
| 7258 | |
| 7259 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7260 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7261 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7262 format %{ | |
| 7263 "MOV $newval,O7\n\t" | |
| 7264 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7265 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7266 "MOV 1,$res\n\t" | |
| 7267 "MOVne icc,R_G0,$res" | |
| 7268 %} | |
| 7269 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7270 enc_iflags_ne_to_boolean(res) ); | |
| 7271 ins_pipe( long_memory_op ); | |
| 7272 %} | |
| 7273 | |
| 7274 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7275 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7276 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7277 format %{ | |
| 7278 "MOV $newval,O7\n\t" | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7279 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7280 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7281 "MOV 1,$res\n\t" | |
| 7282 "MOVne xcc,R_G0,$res" | |
| 7283 %} | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7284 #ifdef _LP64 |
| 0 | 7285 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7286 enc_lflags_ne_to_boolean(res) ); | |
| 7287 #else | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7288 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7289 enc_iflags_ne_to_boolean(res) ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7290 #endif |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7291 ins_pipe( long_memory_op ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7292 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7293 |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7294 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7295 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7296 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7297 format %{ |
| 7298 "MOV $newval,O7\n\t" | |
| 7299 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7300 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7301 "MOV 1,$res\n\t" | |
| 7302 "MOVne icc,R_G0,$res" | |
| 7303 %} | |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7304 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7305 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7306 ins_pipe( long_memory_op ); |
| 7307 %} | |
| 7308 | |
| 7309 //--------------------- | |
| 7310 // Subtraction Instructions | |
| 7311 // Register Subtraction | |
| 7312 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7313 match(Set dst (SubI src1 src2)); | |
| 7314 | |
| 7315 size(4); | |
| 7316 format %{ "SUB $src1,$src2,$dst" %} | |
| 7317 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7318 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7319 ins_pipe(ialu_reg_reg); | |
| 7320 %} | |
| 7321 | |
| 7322 // Immediate Subtraction | |
| 7323 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7324 match(Set dst (SubI src1 src2)); | |
| 7325 | |
| 7326 size(4); | |
| 7327 format %{ "SUB $src1,$src2,$dst" %} | |
| 7328 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7329 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7330 ins_pipe(ialu_reg_imm); | |
| 7331 %} | |
| 7332 | |
| 7333 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7334 match(Set dst (SubI zero src2)); | |
| 7335 | |
| 7336 size(4); | |
| 7337 format %{ "NEG $src2,$dst" %} | |
| 7338 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7339 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7340 ins_pipe(ialu_zero_reg); | |
| 7341 %} | |
| 7342 | |
| 7343 // Long subtraction | |
| 7344 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7345 match(Set dst (SubL src1 src2)); | |
| 7346 | |
| 7347 size(4); | |
| 7348 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7349 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7350 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7351 ins_pipe(ialu_reg_reg); | |
| 7352 %} | |
| 7353 | |
| 7354 // Immediate Subtraction | |
| 7355 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7356 match(Set dst (SubL src1 con)); | |
| 7357 | |
| 7358 size(4); | |
| 7359 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7360 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7361 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7362 ins_pipe(ialu_reg_imm); | |
| 7363 %} | |
| 7364 | |
| 7365 // Long negation | |
| 7366 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7367 match(Set dst (SubL zero src2)); | |
| 7368 | |
| 7369 size(4); | |
| 7370 format %{ "NEG $src2,$dst\t! long" %} | |
| 7371 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7372 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7373 ins_pipe(ialu_zero_reg); | |
| 7374 %} | |
| 7375 | |
| 7376 // Multiplication Instructions | |
| 7377 // Integer Multiplication | |
| 7378 // Register Multiplication | |
| 7379 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7380 match(Set dst (MulI src1 src2)); | |
| 7381 | |
| 7382 size(4); | |
| 7383 format %{ "MULX $src1,$src2,$dst" %} | |
| 7384 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7385 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7386 ins_pipe(imul_reg_reg); | |
| 7387 %} | |
| 7388 | |
| 7389 // Immediate Multiplication | |
| 7390 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7391 match(Set dst (MulI src1 src2)); | |
| 7392 | |
| 7393 size(4); | |
| 7394 format %{ "MULX $src1,$src2,$dst" %} | |
| 7395 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7396 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7397 ins_pipe(imul_reg_imm); | |
| 7398 %} | |
| 7399 | |
| 7400 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7401 match(Set dst (MulL src1 src2)); | |
| 7402 ins_cost(DEFAULT_COST * 5); | |
| 7403 size(4); | |
| 7404 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7405 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7406 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7407 ins_pipe(mulL_reg_reg); | |
| 7408 %} | |
| 7409 | |
| 7410 // Immediate Multiplication | |
| 7411 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7412 match(Set dst (MulL src1 src2)); | |
| 7413 ins_cost(DEFAULT_COST * 5); | |
| 7414 size(4); | |
| 7415 format %{ "MULX $src1,$src2,$dst" %} | |
| 7416 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7417 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7418 ins_pipe(mulL_reg_imm); | |
| 7419 %} | |
| 7420 | |
| 7421 // Integer Division | |
| 7422 // Register Division | |
| 7423 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7424 match(Set dst (DivI src1 src2)); | |
| 7425 ins_cost((2+71)*DEFAULT_COST); | |
| 7426 | |
| 7427 format %{ "SRA $src2,0,$src2\n\t" | |
| 7428 "SRA $src1,0,$src1\n\t" | |
| 7429 "SDIVX $src1,$src2,$dst" %} | |
| 7430 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7431 ins_pipe(sdiv_reg_reg); | |
| 7432 %} | |
| 7433 | |
| 7434 // Immediate Division | |
| 7435 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7436 match(Set dst (DivI src1 src2)); | |
| 7437 ins_cost((2+71)*DEFAULT_COST); | |
| 7438 | |
| 7439 format %{ "SRA $src1,0,$src1\n\t" | |
| 7440 "SDIVX $src1,$src2,$dst" %} | |
| 7441 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7442 ins_pipe(sdiv_reg_imm); | |
| 7443 %} | |
| 7444 | |
| 7445 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7446 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7447 // Expand rule only, not matched | |
| 7448 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7449 effect( DEF dst, USE src1, USE src2 ); | |
| 7450 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7451 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7452 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7453 ins_pipe(sdiv_reg_reg); | |
| 7454 %} | |
| 7455 | |
| 605 | 7456 // Magic constant, reciprocal of 10 |
| 0 | 7457 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7458 effect( DEF dst ); | |
| 7459 | |
| 7460 size(8); | |
| 7461 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7462 ins_encode( Set32(0x66666667, dst) ); | |
| 7463 ins_pipe(ialu_hi_lo_reg); | |
| 7464 %} | |
| 7465 | |
| 605 | 7466 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7467 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7468 effect( DEF dst, USE src ); | |
| 7469 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7470 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7471 ins_pipe(ialu_reg_reg); | |
| 7472 %} | |
| 7473 | |
| 7474 // Arithmetic Shift Right by 8-bit immediate | |
| 7475 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7476 effect( DEF dst, USE src ); | |
| 7477 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7478 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7479 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7480 ins_pipe(ialu_reg_imm); | |
| 7481 %} | |
| 7482 | |
| 7483 // Integer DIV with 10 | |
| 7484 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7485 match(Set dst (DivI src div)); | |
| 7486 ins_cost((6+6)*DEFAULT_COST); | |
| 7487 expand %{ | |
| 7488 iRegIsafe tmp1; // Killed temps; | |
| 7489 iRegIsafe tmp2; // Killed temps; | |
| 7490 iRegI tmp3; // Killed temps; | |
| 7491 iRegI tmp4; // Killed temps; | |
| 7492 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7493 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7494 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7495 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7496 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7497 %} | |
| 7498 %} | |
| 7499 | |
| 7500 // Register Long Division | |
| 7501 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7502 match(Set dst (DivL src1 src2)); | |
| 7503 ins_cost(DEFAULT_COST*71); | |
| 7504 size(4); | |
| 7505 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7506 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7507 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7508 ins_pipe(divL_reg_reg); | |
| 7509 %} | |
| 7510 | |
| 7511 // Register Long Division | |
| 7512 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7513 match(Set dst (DivL src1 src2)); | |
| 7514 ins_cost(DEFAULT_COST*71); | |
| 7515 size(4); | |
| 7516 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7517 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7518 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7519 ins_pipe(divL_reg_imm); | |
| 7520 %} | |
| 7521 | |
| 7522 // Integer Remainder | |
| 7523 // Register Remainder | |
| 7524 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7525 match(Set dst (ModI src1 src2)); | |
| 7526 effect( KILL ccr, KILL temp); | |
| 7527 | |
| 7528 format %{ "SREM $src1,$src2,$dst" %} | |
| 7529 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7530 ins_pipe(sdiv_reg_reg); | |
| 7531 %} | |
| 7532 | |
| 7533 // Immediate Remainder | |
| 7534 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7535 match(Set dst (ModI src1 src2)); | |
| 7536 effect( KILL ccr, KILL temp); | |
| 7537 | |
| 7538 format %{ "SREM $src1,$src2,$dst" %} | |
| 7539 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7540 ins_pipe(sdiv_reg_imm); | |
| 7541 %} | |
| 7542 | |
| 7543 // Register Long Remainder | |
| 7544 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7545 effect(DEF dst, USE src1, USE src2); | |
| 7546 size(4); | |
| 7547 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7548 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7549 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7550 ins_pipe(divL_reg_reg); | |
| 7551 %} | |
| 7552 | |
| 7553 // Register Long Division | |
| 7554 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7555 effect(DEF dst, USE src1, USE src2); | |
| 7556 size(4); | |
| 7557 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7558 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7559 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7560 ins_pipe(divL_reg_imm); | |
| 7561 %} | |
| 7562 | |
| 7563 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7564 effect(DEF dst, USE src1, USE src2); | |
| 7565 size(4); | |
| 7566 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7567 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7569 ins_pipe(mulL_reg_reg); | |
| 7570 %} | |
| 7571 | |
| 7572 // Immediate Multiplication | |
| 7573 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7574 effect(DEF dst, USE src1, USE src2); | |
| 7575 size(4); | |
| 7576 format %{ "MULX $src1,$src2,$dst" %} | |
| 7577 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7579 ins_pipe(mulL_reg_imm); | |
| 7580 %} | |
| 7581 | |
| 7582 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7583 effect(DEF dst, USE src1, USE src2); | |
| 7584 size(4); | |
| 7585 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7586 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7587 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7588 ins_pipe(ialu_reg_reg); | |
| 7589 %} | |
| 7590 | |
| 7591 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7592 effect(DEF dst, USE src1, USE src2); | |
| 7593 size(4); | |
| 7594 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7595 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7596 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7597 ins_pipe(ialu_reg_reg); | |
| 7598 %} | |
| 7599 | |
| 7600 // Register Long Remainder | |
| 7601 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7602 match(Set dst (ModL src1 src2)); | |
| 7603 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7604 expand %{ | |
| 7605 iRegL tmp1; | |
| 7606 iRegL tmp2; | |
| 7607 divL_reg_reg_1(tmp1, src1, src2); | |
| 7608 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7609 subL_reg_reg_1(dst, src1, tmp2); | |
| 7610 %} | |
| 7611 %} | |
| 7612 | |
| 7613 // Register Long Remainder | |
| 7614 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7615 match(Set dst (ModL src1 src2)); | |
| 7616 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7617 expand %{ | |
| 7618 iRegL tmp1; | |
| 7619 iRegL tmp2; | |
| 7620 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7621 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7622 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7623 %} | |
| 7624 %} | |
| 7625 | |
| 7626 // Integer Shift Instructions | |
| 7627 // Register Shift Left | |
| 7628 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7629 match(Set dst (LShiftI src1 src2)); | |
| 7630 | |
| 7631 size(4); | |
| 7632 format %{ "SLL $src1,$src2,$dst" %} | |
| 7633 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7634 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7635 ins_pipe(ialu_reg_reg); | |
| 7636 %} | |
| 7637 | |
| 7638 // Register Shift Left Immediate | |
| 7639 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7640 match(Set dst (LShiftI src1 src2)); | |
| 7641 | |
| 7642 size(4); | |
| 7643 format %{ "SLL $src1,$src2,$dst" %} | |
| 7644 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7645 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7646 ins_pipe(ialu_reg_imm); | |
| 7647 %} | |
| 7648 | |
| 7649 // Register Shift Left | |
| 7650 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7651 match(Set dst (LShiftL src1 src2)); | |
| 7652 | |
| 7653 size(4); | |
| 7654 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7655 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7656 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7657 ins_pipe(ialu_reg_reg); | |
| 7658 %} | |
| 7659 | |
| 7660 // Register Shift Left Immediate | |
| 7661 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7662 match(Set dst (LShiftL src1 src2)); | |
| 7663 | |
| 7664 size(4); | |
| 7665 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7666 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7667 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7668 ins_pipe(ialu_reg_imm); | |
| 7669 %} | |
| 7670 | |
| 7671 // Register Arithmetic Shift Right | |
| 7672 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7673 match(Set dst (RShiftI src1 src2)); | |
| 7674 size(4); | |
| 7675 format %{ "SRA $src1,$src2,$dst" %} | |
| 7676 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7677 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7678 ins_pipe(ialu_reg_reg); | |
| 7679 %} | |
| 7680 | |
| 7681 // Register Arithmetic Shift Right Immediate | |
| 7682 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7683 match(Set dst (RShiftI src1 src2)); | |
| 7684 | |
| 7685 size(4); | |
| 7686 format %{ "SRA $src1,$src2,$dst" %} | |
| 7687 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7688 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7689 ins_pipe(ialu_reg_imm); | |
| 7690 %} | |
| 7691 | |
| 7692 // Register Shift Right Arithmatic Long | |
| 7693 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7694 match(Set dst (RShiftL src1 src2)); | |
| 7695 | |
| 7696 size(4); | |
| 7697 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7698 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7699 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7700 ins_pipe(ialu_reg_reg); | |
| 7701 %} | |
| 7702 | |
| 7703 // Register Shift Left Immediate | |
| 7704 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7705 match(Set dst (RShiftL src1 src2)); | |
| 7706 | |
| 7707 size(4); | |
| 7708 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7709 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7710 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7711 ins_pipe(ialu_reg_imm); | |
| 7712 %} | |
| 7713 | |
| 7714 // Register Shift Right | |
| 7715 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7716 match(Set dst (URShiftI src1 src2)); | |
| 7717 | |
| 7718 size(4); | |
| 7719 format %{ "SRL $src1,$src2,$dst" %} | |
| 7720 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7721 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7722 ins_pipe(ialu_reg_reg); | |
| 7723 %} | |
| 7724 | |
| 7725 // Register Shift Right Immediate | |
| 7726 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7727 match(Set dst (URShiftI src1 src2)); | |
| 7728 | |
| 7729 size(4); | |
| 7730 format %{ "SRL $src1,$src2,$dst" %} | |
| 7731 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7732 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7733 ins_pipe(ialu_reg_imm); | |
| 7734 %} | |
| 7735 | |
| 7736 // Register Shift Right | |
| 7737 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7738 match(Set dst (URShiftL src1 src2)); | |
| 7739 | |
| 7740 size(4); | |
| 7741 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7742 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7743 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7744 ins_pipe(ialu_reg_reg); | |
| 7745 %} | |
| 7746 | |
| 7747 // Register Shift Right Immediate | |
| 7748 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7749 match(Set dst (URShiftL src1 src2)); | |
| 7750 | |
| 7751 size(4); | |
| 7752 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7753 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7754 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7755 ins_pipe(ialu_reg_imm); | |
| 7756 %} | |
| 7757 | |
| 7758 // Register Shift Right Immediate with a CastP2X | |
| 7759 #ifdef _LP64 | |
| 7760 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7761 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7762 size(4); | |
| 7763 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7764 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7765 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7766 ins_pipe(ialu_reg_imm); | |
| 7767 %} | |
| 7768 #else | |
| 7769 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7770 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7771 size(4); | |
| 7772 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7773 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7774 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7775 ins_pipe(ialu_reg_imm); | |
| 7776 %} | |
| 7777 #endif | |
| 7778 | |
| 7779 | |
| 7780 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7781 | |
| 7782 // Add float single precision | |
| 7783 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7784 match(Set dst (AddF src1 src2)); | |
| 7785 | |
| 7786 size(4); | |
| 7787 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7789 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7790 ins_pipe(faddF_reg_reg); | |
| 7791 %} | |
| 7792 | |
| 7793 // Add float double precision | |
| 7794 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7795 match(Set dst (AddD src1 src2)); | |
| 7796 | |
| 7797 size(4); | |
| 7798 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7800 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7801 ins_pipe(faddD_reg_reg); | |
| 7802 %} | |
| 7803 | |
| 7804 // Sub float single precision | |
| 7805 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7806 match(Set dst (SubF src1 src2)); | |
| 7807 | |
| 7808 size(4); | |
| 7809 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7810 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7811 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7812 ins_pipe(faddF_reg_reg); | |
| 7813 %} | |
| 7814 | |
| 7815 // Sub float double precision | |
| 7816 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7817 match(Set dst (SubD src1 src2)); | |
| 7818 | |
| 7819 size(4); | |
| 7820 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7821 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7822 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7823 ins_pipe(faddD_reg_reg); | |
| 7824 %} | |
| 7825 | |
| 7826 // Mul float single precision | |
| 7827 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7828 match(Set dst (MulF src1 src2)); | |
| 7829 | |
| 7830 size(4); | |
| 7831 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7832 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7833 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7834 ins_pipe(fmulF_reg_reg); | |
| 7835 %} | |
| 7836 | |
| 7837 // Mul float double precision | |
| 7838 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7839 match(Set dst (MulD src1 src2)); | |
| 7840 | |
| 7841 size(4); | |
| 7842 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7843 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7844 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7845 ins_pipe(fmulD_reg_reg); | |
| 7846 %} | |
| 7847 | |
| 7848 // Div float single precision | |
| 7849 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7850 match(Set dst (DivF src1 src2)); | |
| 7851 | |
| 7852 size(4); | |
| 7853 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7854 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7855 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7856 ins_pipe(fdivF_reg_reg); | |
| 7857 %} | |
| 7858 | |
| 7859 // Div float double precision | |
| 7860 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7861 match(Set dst (DivD src1 src2)); | |
| 7862 | |
| 7863 size(4); | |
| 7864 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7865 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7866 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7867 ins_pipe(fdivD_reg_reg); | |
| 7868 %} | |
| 7869 | |
| 7870 // Absolute float double precision | |
| 7871 instruct absD_reg(regD dst, regD src) %{ | |
| 7872 match(Set dst (AbsD src)); | |
| 7873 | |
| 7874 format %{ "FABSd $src,$dst" %} | |
| 7875 ins_encode(fabsd(dst, src)); | |
| 7876 ins_pipe(faddD_reg); | |
| 7877 %} | |
| 7878 | |
| 7879 // Absolute float single precision | |
| 7880 instruct absF_reg(regF dst, regF src) %{ | |
| 7881 match(Set dst (AbsF src)); | |
| 7882 | |
| 7883 format %{ "FABSs $src,$dst" %} | |
| 7884 ins_encode(fabss(dst, src)); | |
| 7885 ins_pipe(faddF_reg); | |
| 7886 %} | |
| 7887 | |
| 7888 instruct negF_reg(regF dst, regF src) %{ | |
| 7889 match(Set dst (NegF src)); | |
| 7890 | |
| 7891 size(4); | |
| 7892 format %{ "FNEGs $src,$dst" %} | |
| 7893 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7894 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7895 ins_pipe(faddF_reg); | |
| 7896 %} | |
| 7897 | |
| 7898 instruct negD_reg(regD dst, regD src) %{ | |
| 7899 match(Set dst (NegD src)); | |
| 7900 | |
| 7901 format %{ "FNEGd $src,$dst" %} | |
| 7902 ins_encode(fnegd(dst, src)); | |
| 7903 ins_pipe(faddD_reg); | |
| 7904 %} | |
| 7905 | |
| 7906 // Sqrt float double precision | |
| 7907 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7908 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7909 | |
| 7910 size(4); | |
| 7911 format %{ "FSQRTS $src,$dst" %} | |
| 7912 ins_encode(fsqrts(dst, src)); | |
| 7913 ins_pipe(fdivF_reg_reg); | |
| 7914 %} | |
| 7915 | |
| 7916 // Sqrt float double precision | |
| 7917 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7918 match(Set dst (SqrtD src)); | |
| 7919 | |
| 7920 size(4); | |
| 7921 format %{ "FSQRTD $src,$dst" %} | |
| 7922 ins_encode(fsqrtd(dst, src)); | |
| 7923 ins_pipe(fdivD_reg_reg); | |
| 7924 %} | |
| 7925 | |
| 7926 //----------Logical Instructions----------------------------------------------- | |
| 7927 // And Instructions | |
| 7928 // Register And | |
| 7929 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7930 match(Set dst (AndI src1 src2)); | |
| 7931 | |
| 7932 size(4); | |
| 7933 format %{ "AND $src1,$src2,$dst" %} | |
| 7934 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7936 ins_pipe(ialu_reg_reg); | |
| 7937 %} | |
| 7938 | |
| 7939 // Immediate And | |
| 7940 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7941 match(Set dst (AndI src1 src2)); | |
| 7942 | |
| 7943 size(4); | |
| 7944 format %{ "AND $src1,$src2,$dst" %} | |
| 7945 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7947 ins_pipe(ialu_reg_imm); | |
| 7948 %} | |
| 7949 | |
| 7950 // Register And Long | |
| 7951 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7952 match(Set dst (AndL src1 src2)); | |
| 7953 | |
| 7954 ins_cost(DEFAULT_COST); | |
| 7955 size(4); | |
| 7956 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7957 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7959 ins_pipe(ialu_reg_reg); | |
| 7960 %} | |
| 7961 | |
| 7962 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7963 match(Set dst (AndL src1 con)); | |
| 7964 | |
| 7965 ins_cost(DEFAULT_COST); | |
| 7966 size(4); | |
| 7967 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7968 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7969 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7970 ins_pipe(ialu_reg_imm); | |
| 7971 %} | |
| 7972 | |
| 7973 // Or Instructions | |
| 7974 // Register Or | |
| 7975 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7976 match(Set dst (OrI src1 src2)); | |
| 7977 | |
| 7978 size(4); | |
| 7979 format %{ "OR $src1,$src2,$dst" %} | |
| 7980 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7981 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7982 ins_pipe(ialu_reg_reg); | |
| 7983 %} | |
| 7984 | |
| 7985 // Immediate Or | |
| 7986 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7987 match(Set dst (OrI src1 src2)); | |
| 7988 | |
| 7989 size(4); | |
| 7990 format %{ "OR $src1,$src2,$dst" %} | |
| 7991 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7992 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7993 ins_pipe(ialu_reg_imm); | |
| 7994 %} | |
| 7995 | |
| 7996 // Register Or Long | |
| 7997 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7998 match(Set dst (OrL src1 src2)); | |
| 7999 | |
| 8000 ins_cost(DEFAULT_COST); | |
| 8001 size(4); | |
| 8002 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 8003 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8004 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8005 ins_pipe(ialu_reg_reg); | |
| 8006 %} | |
| 8007 | |
| 8008 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8009 match(Set dst (OrL src1 con)); | |
| 8010 ins_cost(DEFAULT_COST*2); | |
| 8011 | |
| 8012 ins_cost(DEFAULT_COST); | |
| 8013 size(4); | |
| 8014 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 8015 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8016 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8017 ins_pipe(ialu_reg_imm); | |
| 8018 %} | |
| 8019 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8020 #ifndef _LP64 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8021 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8022 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8023 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8024 match(Set dst (OrI src1 (CastP2X src2))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8025 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8026 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8027 format %{ "OR $src1,$src2,$dst" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8028 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8030 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8031 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8032 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8033 #else |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8034 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8035 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8036 match(Set dst (OrL src1 (CastP2X src2))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8037 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8038 ins_cost(DEFAULT_COST); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8039 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8040 format %{ "OR $src1,$src2,$dst\t! long" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8041 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8042 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8043 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8044 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8045 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8046 #endif |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8047 |
| 0 | 8048 // Xor Instructions |
| 8049 // Register Xor | |
| 8050 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8051 match(Set dst (XorI src1 src2)); | |
| 8052 | |
| 8053 size(4); | |
| 8054 format %{ "XOR $src1,$src2,$dst" %} | |
| 8055 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8056 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8057 ins_pipe(ialu_reg_reg); | |
| 8058 %} | |
| 8059 | |
| 8060 // Immediate Xor | |
| 8061 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8062 match(Set dst (XorI src1 src2)); | |
| 8063 | |
| 8064 size(4); | |
| 8065 format %{ "XOR $src1,$src2,$dst" %} | |
| 8066 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8067 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8068 ins_pipe(ialu_reg_imm); | |
| 8069 %} | |
| 8070 | |
| 8071 // Register Xor Long | |
| 8072 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8073 match(Set dst (XorL src1 src2)); | |
| 8074 | |
| 8075 ins_cost(DEFAULT_COST); | |
| 8076 size(4); | |
| 8077 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8078 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8079 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8080 ins_pipe(ialu_reg_reg); | |
| 8081 %} | |
| 8082 | |
| 8083 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8084 match(Set dst (XorL src1 con)); | |
| 8085 | |
| 8086 ins_cost(DEFAULT_COST); | |
| 8087 size(4); | |
| 8088 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8089 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8090 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8091 ins_pipe(ialu_reg_imm); | |
| 8092 %} | |
| 8093 | |
| 8094 //----------Convert to Boolean------------------------------------------------- | |
| 8095 // Nice hack for 32-bit tests but doesn't work for | |
| 8096 // 64-bit pointers. | |
| 8097 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8098 match(Set dst (Conv2B src)); | |
| 8099 effect( KILL ccr ); | |
| 8100 ins_cost(DEFAULT_COST*2); | |
| 8101 format %{ "CMP R_G0,$src\n\t" | |
| 8102 "ADDX R_G0,0,$dst" %} | |
| 8103 ins_encode( enc_to_bool( src, dst ) ); | |
| 8104 ins_pipe(ialu_reg_ialu); | |
| 8105 %} | |
| 8106 | |
| 8107 #ifndef _LP64 | |
| 8108 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8109 match(Set dst (Conv2B src)); | |
| 8110 effect( KILL ccr ); | |
| 8111 ins_cost(DEFAULT_COST*2); | |
| 8112 format %{ "CMP R_G0,$src\n\t" | |
| 8113 "ADDX R_G0,0,$dst" %} | |
| 8114 ins_encode( enc_to_bool( src, dst ) ); | |
| 8115 ins_pipe(ialu_reg_ialu); | |
| 8116 %} | |
| 8117 #else | |
| 8118 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8119 match(Set dst (Conv2B src)); | |
| 8120 ins_cost(DEFAULT_COST*2); | |
| 8121 format %{ "MOV $src,$dst\n\t" | |
| 8122 "MOVRNZ $src,1,$dst" %} | |
| 8123 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8124 ins_pipe(ialu_clr_and_mover); | |
| 8125 %} | |
| 8126 #endif | |
| 8127 | |
| 8128 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
| 8129 match(Set dst (CmpLTMask p q)); | |
| 8130 effect( KILL ccr ); | |
| 8131 ins_cost(DEFAULT_COST*4); | |
| 8132 format %{ "CMP $p,$q\n\t" | |
| 8133 "MOV #0,$dst\n\t" | |
| 8134 "BLT,a .+8\n\t" | |
| 8135 "MOV #-1,$dst" %} | |
| 8136 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8137 ins_pipe(ialu_reg_reg_ialu); | |
| 8138 %} | |
| 8139 | |
| 8140 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8141 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8142 effect(KILL ccr, TEMP tmp); | |
| 8143 ins_cost(DEFAULT_COST*3); | |
| 8144 | |
| 8145 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8146 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8147 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8148 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8149 ins_pipe( cadd_cmpltmask ); | |
| 8150 %} | |
| 8151 | |
| 8152 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8153 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
| 8154 effect( KILL ccr, TEMP tmp); | |
| 8155 ins_cost(DEFAULT_COST*3); | |
| 8156 | |
| 8157 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8158 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8159 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8160 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8161 ins_pipe( cadd_cmpltmask ); | |
| 8162 %} | |
| 8163 | |
| 8164 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 8165 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8166 | |
| 8167 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8168 match(Set dst (ConvD2F src)); | |
| 8169 size(4); | |
| 8170 format %{ "FDTOS $src,$dst" %} | |
| 8171 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8172 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8173 ins_pipe(fcvtD2F); | |
| 8174 %} | |
| 8175 | |
| 8176 | |
| 8177 // Convert a double to an int in a float register. | |
| 8178 // If the double is a NAN, stuff a zero in instead. | |
| 8179 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8180 effect(DEF dst, USE src, KILL fcc0); | |
| 8181 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8182 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8183 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8184 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8185 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8186 "skip:" %} | |
| 8187 ins_encode(form_d2i_helper(src,dst)); | |
| 8188 ins_pipe(fcvtD2I); | |
| 8189 %} | |
| 8190 | |
| 8191 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
| 8192 match(Set dst (ConvD2I src)); | |
| 8193 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8194 expand %{ | |
| 8195 regF tmp; | |
| 8196 convD2I_helper(tmp, src); | |
| 8197 regF_to_stkI(dst, tmp); | |
| 8198 %} | |
| 8199 %} | |
| 8200 | |
| 8201 // Convert a double to a long in a double register. | |
| 8202 // If the double is a NAN, stuff a zero in instead. | |
| 8203 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8204 effect(DEF dst, USE src, KILL fcc0); | |
| 8205 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8206 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8207 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8208 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8209 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8210 "skip:" %} | |
| 8211 ins_encode(form_d2l_helper(src,dst)); | |
| 8212 ins_pipe(fcvtD2L); | |
| 8213 %} | |
| 8214 | |
| 8215 | |
| 8216 // Double to Long conversion | |
| 8217 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
| 8218 match(Set dst (ConvD2L src)); | |
| 8219 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8220 expand %{ | |
| 8221 regD tmp; | |
| 8222 convD2L_helper(tmp, src); | |
| 8223 regD_to_stkL(dst, tmp); | |
| 8224 %} | |
| 8225 %} | |
| 8226 | |
| 8227 | |
| 8228 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8229 match(Set dst (ConvF2D src)); | |
| 8230 format %{ "FSTOD $src,$dst" %} | |
| 8231 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8232 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8233 ins_pipe(fcvtF2D); | |
| 8234 %} | |
| 8235 | |
| 8236 | |
| 8237 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8238 effect(DEF dst, USE src, KILL fcc0); | |
| 8239 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8240 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8241 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8242 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8243 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8244 "skip:" %} | |
| 8245 ins_encode(form_f2i_helper(src,dst)); | |
| 8246 ins_pipe(fcvtF2I); | |
| 8247 %} | |
| 8248 | |
| 8249 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
| 8250 match(Set dst (ConvF2I src)); | |
| 8251 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8252 expand %{ | |
| 8253 regF tmp; | |
| 8254 convF2I_helper(tmp, src); | |
| 8255 regF_to_stkI(dst, tmp); | |
| 8256 %} | |
| 8257 %} | |
| 8258 | |
| 8259 | |
| 8260 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8261 effect(DEF dst, USE src, KILL fcc0); | |
| 8262 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8263 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8264 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8265 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8266 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8267 "skip:" %} | |
| 8268 ins_encode(form_f2l_helper(src,dst)); | |
| 8269 ins_pipe(fcvtF2L); | |
| 8270 %} | |
| 8271 | |
| 8272 // Float to Long conversion | |
| 8273 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
| 8274 match(Set dst (ConvF2L src)); | |
| 8275 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8276 expand %{ | |
| 8277 regD tmp; | |
| 8278 convF2L_helper(tmp, src); | |
| 8279 regD_to_stkL(dst, tmp); | |
| 8280 %} | |
| 8281 %} | |
| 8282 | |
| 8283 | |
| 8284 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8285 effect(USE tmp, DEF dst); | |
| 8286 format %{ "FITOD $tmp,$dst" %} | |
| 8287 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8288 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8289 ins_pipe(fcvtI2D); | |
| 8290 %} | |
| 8291 | |
| 8292 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
| 8293 match(Set dst (ConvI2D src)); | |
| 8294 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8295 expand %{ | |
| 8296 regF tmp; | |
| 8297 stkI_to_regF( tmp, src); | |
| 8298 convI2D_helper( dst, tmp); | |
| 8299 %} | |
| 8300 %} | |
| 8301 | |
| 8302 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
| 8303 match(Set dst (ConvI2D (LoadI mem))); | |
| 8304 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8305 size(8); | |
| 8306 format %{ "LDF $mem,$dst\n\t" | |
| 8307 "FITOD $dst,$dst" %} | |
| 8308 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8309 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8310 ins_pipe(floadF_mem); |
| 8311 %} | |
| 8312 | |
| 8313 | |
| 8314 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8315 effect(DEF dst, USE tmp); | |
| 8316 format %{ "FITOS $tmp,$dst" %} | |
| 8317 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8318 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8319 ins_pipe(fcvtI2F); | |
| 8320 %} | |
| 8321 | |
| 8322 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
| 8323 match(Set dst (ConvI2F src)); | |
| 8324 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8325 expand %{ | |
| 8326 regF tmp; | |
| 8327 stkI_to_regF(tmp,src); | |
| 8328 convI2F_helper(dst, tmp); | |
| 8329 %} | |
| 8330 %} | |
| 8331 | |
| 8332 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8333 match(Set dst (ConvI2F (LoadI mem))); | |
| 8334 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8335 size(8); | |
| 8336 format %{ "LDF $mem,$dst\n\t" | |
| 8337 "FITOS $dst,$dst" %} | |
| 8338 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8339 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8340 ins_pipe(floadF_mem); |
| 8341 %} | |
| 8342 | |
| 8343 | |
| 8344 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8345 match(Set dst (ConvI2L src)); | |
| 8346 size(4); | |
| 8347 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8348 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8349 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8350 ins_pipe(ialu_reg_reg); | |
| 8351 %} | |
| 8352 | |
| 8353 // Zero-extend convert int to long | |
| 8354 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8355 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8356 size(4); | |
| 8357 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8358 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8359 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8360 ins_pipe(ialu_reg_reg); | |
| 8361 %} | |
| 8362 | |
| 8363 // Zero-extend long | |
| 8364 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8365 match(Set dst (AndL src mask) ); | |
| 8366 size(4); | |
| 8367 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8368 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8369 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8370 ins_pipe(ialu_reg_reg); | |
| 8371 %} | |
| 8372 | |
| 8373 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
| 8374 match(Set dst (MoveF2I src)); | |
| 8375 effect(DEF dst, USE src); | |
| 8376 ins_cost(MEMORY_REF_COST); | |
| 8377 | |
| 8378 size(4); | |
| 8379 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8380 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8381 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8382 ins_pipe(iload_mem); |
| 8383 %} | |
| 8384 | |
| 8385 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8386 match(Set dst (MoveI2F src)); | |
| 8387 effect(DEF dst, USE src); | |
| 8388 ins_cost(MEMORY_REF_COST); | |
| 8389 | |
| 8390 size(4); | |
| 8391 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8392 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8393 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8394 ins_pipe(floadF_stk); |
| 8395 %} | |
| 8396 | |
| 8397 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8398 match(Set dst (MoveD2L src)); | |
| 8399 effect(DEF dst, USE src); | |
| 8400 ins_cost(MEMORY_REF_COST); | |
| 8401 | |
| 8402 size(4); | |
| 8403 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8404 opcode(Assembler::ldx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8405 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8406 ins_pipe(iload_mem); |
| 8407 %} | |
| 8408 | |
| 8409 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8410 match(Set dst (MoveL2D src)); | |
| 8411 effect(DEF dst, USE src); | |
| 8412 ins_cost(MEMORY_REF_COST); | |
| 8413 | |
| 8414 size(4); | |
| 8415 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8416 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8417 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8418 ins_pipe(floadD_stk); |
| 8419 %} | |
| 8420 | |
| 8421 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8422 match(Set dst (MoveF2I src)); | |
| 8423 effect(DEF dst, USE src); | |
| 8424 ins_cost(MEMORY_REF_COST); | |
| 8425 | |
| 8426 size(4); | |
| 8427 format %{ "STF $src,$dst\t!MoveF2I" %} | |
| 8428 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8429 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8430 ins_pipe(fstoreF_stk_reg); |
| 8431 %} | |
| 8432 | |
| 8433 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8434 match(Set dst (MoveI2F src)); | |
| 8435 effect(DEF dst, USE src); | |
| 8436 ins_cost(MEMORY_REF_COST); | |
| 8437 | |
| 8438 size(4); | |
| 8439 format %{ "STW $src,$dst\t!MoveI2F" %} | |
| 8440 opcode(Assembler::stw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8441 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8442 ins_pipe(istore_mem_reg); |
| 8443 %} | |
| 8444 | |
| 8445 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8446 match(Set dst (MoveD2L src)); | |
| 8447 effect(DEF dst, USE src); | |
| 8448 ins_cost(MEMORY_REF_COST); | |
| 8449 | |
| 8450 size(4); | |
| 8451 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
| 8452 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8453 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8454 ins_pipe(fstoreD_stk_reg); |
| 8455 %} | |
| 8456 | |
| 8457 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8458 match(Set dst (MoveL2D src)); | |
| 8459 effect(DEF dst, USE src); | |
| 8460 ins_cost(MEMORY_REF_COST); | |
| 8461 | |
| 8462 size(4); | |
| 8463 format %{ "STX $src,$dst\t!MoveL2D" %} | |
| 8464 opcode(Assembler::stx_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8465 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8466 ins_pipe(istore_mem_reg); |
| 8467 %} | |
| 8468 | |
| 8469 | |
| 8470 //----------- | |
| 8471 // Long to Double conversion using V8 opcodes. | |
| 8472 // Still useful because cheetah traps and becomes | |
| 8473 // amazingly slow for some common numbers. | |
| 8474 | |
| 8475 // Magic constant, 0x43300000 | |
| 8476 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8477 effect(DEF dst); | |
| 8478 size(4); | |
| 8479 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8480 ins_encode(SetHi22(0x43300000, dst)); | |
| 8481 ins_pipe(ialu_none); | |
| 8482 %} | |
| 8483 | |
| 8484 // Magic constant, 0x41f00000 | |
| 8485 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8486 effect(DEF dst); | |
| 8487 size(4); | |
| 8488 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8489 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8490 ins_pipe(ialu_none); | |
| 8491 %} | |
| 8492 | |
| 8493 // Construct a double from two float halves | |
| 8494 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8495 effect(DEF dst, USE src1, USE src2); | |
| 8496 size(8); | |
| 8497 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8498 "FMOVS $src2.lo,$dst.lo" %} | |
| 8499 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8500 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8501 ins_pipe(faddD_reg_reg); | |
| 8502 %} | |
| 8503 | |
| 8504 // Convert integer in high half of a double register (in the lower half of | |
| 8505 // the double register file) to double | |
| 8506 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8507 effect(DEF dst, USE src); | |
| 8508 size(4); | |
| 8509 format %{ "FITOD $src,$dst" %} | |
| 8510 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8511 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8512 ins_pipe(fcvtLHi2D); | |
| 8513 %} | |
| 8514 | |
| 8515 // Add float double precision | |
| 8516 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8517 effect(DEF dst, USE src1, USE src2); | |
| 8518 size(4); | |
| 8519 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8520 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8521 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8522 ins_pipe(faddD_reg_reg); | |
| 8523 %} | |
| 8524 | |
| 8525 // Sub float double precision | |
| 8526 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8527 effect(DEF dst, USE src1, USE src2); | |
| 8528 size(4); | |
| 8529 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8530 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8531 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8532 ins_pipe(faddD_reg_reg); | |
| 8533 %} | |
| 8534 | |
| 8535 // Mul float double precision | |
| 8536 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8537 effect(DEF dst, USE src1, USE src2); | |
| 8538 size(4); | |
| 8539 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8540 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8541 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8542 ins_pipe(fmulD_reg_reg); | |
| 8543 %} | |
| 8544 | |
| 8545 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8546 match(Set dst (ConvL2D src)); | |
| 8547 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8548 | |
| 8549 expand %{ | |
| 8550 regD_low tmpsrc; | |
| 8551 iRegI ix43300000; | |
| 8552 iRegI ix41f00000; | |
| 8553 stackSlotL lx43300000; | |
| 8554 stackSlotL lx41f00000; | |
| 8555 regD_low dx43300000; | |
| 8556 regD dx41f00000; | |
| 8557 regD tmp1; | |
| 8558 regD_low tmp2; | |
| 8559 regD tmp3; | |
| 8560 regD tmp4; | |
| 8561 | |
| 8562 stkL_to_regD(tmpsrc, src); | |
| 8563 | |
| 8564 loadConI_x43300000(ix43300000); | |
| 8565 loadConI_x41f00000(ix41f00000); | |
| 8566 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8567 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8568 stkL_to_regD(dx43300000, lx43300000); | |
| 8569 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8570 | |
| 8571 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8572 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8573 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8574 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8575 addD_regD_regD(dst, tmp3, tmp4); | |
| 8576 %} | |
| 8577 %} | |
| 8578 | |
| 8579 // Long to Double conversion using fast fxtof | |
| 8580 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8581 effect(DEF dst, USE tmp); | |
| 8582 size(4); | |
| 8583 format %{ "FXTOD $tmp,$dst" %} | |
| 8584 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8585 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8586 ins_pipe(fcvtL2D); | |
| 8587 %} | |
| 8588 | |
| 8589 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
| 8590 predicate(VM_Version::has_fast_fxtof()); | |
| 8591 match(Set dst (ConvL2D src)); | |
| 8592 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8593 expand %{ | |
| 8594 regD tmp; | |
| 8595 stkL_to_regD(tmp, src); | |
| 8596 convL2D_helper(dst, tmp); | |
| 8597 %} | |
| 8598 %} | |
| 8599 | |
| 8600 //----------- | |
| 8601 // Long to Float conversion using V8 opcodes. | |
| 8602 // Still useful because cheetah traps and becomes | |
| 8603 // amazingly slow for some common numbers. | |
| 8604 | |
| 8605 // Long to Float conversion using fast fxtof | |
| 8606 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8607 effect(DEF dst, USE tmp); | |
| 8608 size(4); | |
| 8609 format %{ "FXTOS $tmp,$dst" %} | |
| 8610 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8611 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8612 ins_pipe(fcvtL2F); | |
| 8613 %} | |
| 8614 | |
| 8615 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
| 8616 match(Set dst (ConvL2F src)); | |
| 8617 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8618 expand %{ | |
| 8619 regD tmp; | |
| 8620 stkL_to_regD(tmp, src); | |
| 8621 convL2F_helper(dst, tmp); | |
| 8622 %} | |
| 8623 %} | |
| 8624 //----------- | |
| 8625 | |
| 8626 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8627 match(Set dst (ConvL2I src)); | |
| 8628 #ifndef _LP64 | |
| 8629 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8630 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8631 ins_pipe(ialu_move_reg_I_to_L); | |
| 8632 #else | |
| 8633 size(4); | |
| 8634 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8635 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8636 ins_pipe(ialu_reg); | |
| 8637 #endif | |
| 8638 %} | |
| 8639 | |
| 8640 // Register Shift Right Immediate | |
| 8641 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8642 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8643 | |
| 8644 size(4); | |
| 8645 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8646 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8647 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8648 ins_pipe(ialu_reg_imm); | |
| 8649 %} | |
| 8650 | |
| 8651 // Replicate scalar to packed byte values in Double register | |
| 8652 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8653 effect(DEF dst, USE src); | |
| 8654 format %{ "SLLX $src,56,$dst\n\t" | |
| 8655 "SRLX $dst, 8,O7\n\t" | |
| 8656 "OR $dst,O7,$dst\n\t" | |
| 8657 "SRLX $dst,16,O7\n\t" | |
| 8658 "OR $dst,O7,$dst\n\t" | |
| 8659 "SRLX $dst,32,O7\n\t" | |
| 8660 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8661 ins_encode( enc_repl8b(src, dst)); | |
| 8662 ins_pipe(ialu_reg); | |
| 8663 %} | |
| 8664 | |
| 8665 // Replicate scalar to packed byte values in Double register | |
| 8666 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8667 match(Set dst (Replicate8B src)); | |
| 8668 expand %{ | |
| 8669 iRegL tmp; | |
| 8670 Repl8B_reg_helper(tmp, src); | |
| 8671 regL_to_stkD(dst, tmp); | |
| 8672 %} | |
| 8673 %} | |
| 8674 | |
| 8675 // Replicate scalar constant to packed byte values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8676 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
| 2008 | 8677 match(Set dst (Replicate8B con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8678 effect(KILL tmp); |
| 2008 | 8679 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
| 8680 ins_encode %{ | |
| 8681 // XXX This is a quick fix for 6833573. | |
| 8682 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8683 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8684 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8685 %} |
| 0 | 8686 ins_pipe(loadConFD); |
| 8687 %} | |
| 8688 | |
| 8689 // Replicate scalar to packed char values into stack slot | |
| 8690 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8691 effect(DEF dst, USE src); | |
| 8692 format %{ "SLLX $src,48,$dst\n\t" | |
| 8693 "SRLX $dst,16,O7\n\t" | |
| 8694 "OR $dst,O7,$dst\n\t" | |
| 8695 "SRLX $dst,32,O7\n\t" | |
| 8696 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8697 ins_encode( enc_repl4s(src, dst) ); | |
| 8698 ins_pipe(ialu_reg); | |
| 8699 %} | |
| 8700 | |
| 8701 // Replicate scalar to packed char values into stack slot | |
| 8702 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8703 match(Set dst (Replicate4C src)); | |
| 8704 expand %{ | |
| 8705 iRegL tmp; | |
| 8706 Repl4C_reg_helper(tmp, src); | |
| 8707 regL_to_stkD(dst, tmp); | |
| 8708 %} | |
| 8709 %} | |
| 8710 | |
| 8711 // Replicate scalar constant to packed char values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8712 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8713 match(Set dst (Replicate4C con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8714 effect(KILL tmp); |
| 2008 | 8715 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} |
| 8716 ins_encode %{ | |
| 8717 // XXX This is a quick fix for 6833573. | |
| 8718 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8719 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8720 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8721 %} |
| 0 | 8722 ins_pipe(loadConFD); |
| 8723 %} | |
| 8724 | |
| 8725 // Replicate scalar to packed short values into stack slot | |
| 8726 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8727 effect(DEF dst, USE src); | |
| 8728 format %{ "SLLX $src,48,$dst\n\t" | |
| 8729 "SRLX $dst,16,O7\n\t" | |
| 8730 "OR $dst,O7,$dst\n\t" | |
| 8731 "SRLX $dst,32,O7\n\t" | |
| 8732 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8733 ins_encode( enc_repl4s(src, dst) ); | |
| 8734 ins_pipe(ialu_reg); | |
| 8735 %} | |
| 8736 | |
| 8737 // Replicate scalar to packed short values into stack slot | |
| 8738 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8739 match(Set dst (Replicate4S src)); | |
| 8740 expand %{ | |
| 8741 iRegL tmp; | |
| 8742 Repl4S_reg_helper(tmp, src); | |
| 8743 regL_to_stkD(dst, tmp); | |
| 8744 %} | |
| 8745 %} | |
| 8746 | |
| 8747 // Replicate scalar constant to packed short values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8748 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8749 match(Set dst (Replicate4S con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8750 effect(KILL tmp); |
| 2008 | 8751 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
| 8752 ins_encode %{ | |
| 8753 // XXX This is a quick fix for 6833573. | |
| 8754 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8755 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8756 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8757 %} |
| 0 | 8758 ins_pipe(loadConFD); |
| 8759 %} | |
| 8760 | |
| 8761 // Replicate scalar to packed int values in Double register | |
| 8762 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8763 effect(DEF dst, USE src); | |
| 8764 format %{ "SLLX $src,32,$dst\n\t" | |
| 8765 "SRLX $dst,32,O7\n\t" | |
| 8766 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8767 ins_encode( enc_repl2i(src, dst)); | |
| 8768 ins_pipe(ialu_reg); | |
| 8769 %} | |
| 8770 | |
| 8771 // Replicate scalar to packed int values in Double register | |
| 8772 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8773 match(Set dst (Replicate2I src)); | |
| 8774 expand %{ | |
| 8775 iRegL tmp; | |
| 8776 Repl2I_reg_helper(tmp, src); | |
| 8777 regL_to_stkD(dst, tmp); | |
| 8778 %} | |
| 8779 %} | |
| 8780 | |
| 8781 // Replicate scalar zero constant to packed int values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8782 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8783 match(Set dst (Replicate2I con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8784 effect(KILL tmp); |
| 2008 | 8785 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
| 8786 ins_encode %{ | |
| 8787 // XXX This is a quick fix for 6833573. | |
| 8788 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8789 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8790 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8791 %} |
| 0 | 8792 ins_pipe(loadConFD); |
| 8793 %} | |
| 8794 | |
| 8795 //----------Control Flow Instructions------------------------------------------ | |
| 8796 // Compare Instructions | |
| 8797 // Compare Integers | |
| 8798 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8799 match(Set icc (CmpI op1 op2)); | |
| 8800 effect( DEF icc, USE op1, USE op2 ); | |
| 8801 | |
| 8802 size(4); | |
| 8803 format %{ "CMP $op1,$op2" %} | |
| 8804 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8805 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8806 ins_pipe(ialu_cconly_reg_reg); | |
| 8807 %} | |
| 8808 | |
| 8809 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8810 match(Set icc (CmpU op1 op2)); | |
| 8811 | |
| 8812 size(4); | |
| 8813 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8814 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8815 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8816 ins_pipe(ialu_cconly_reg_reg); | |
| 8817 %} | |
| 8818 | |
| 8819 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8820 match(Set icc (CmpI op1 op2)); | |
| 8821 effect( DEF icc, USE op1 ); | |
| 8822 | |
| 8823 size(4); | |
| 8824 format %{ "CMP $op1,$op2" %} | |
| 8825 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8826 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8827 ins_pipe(ialu_cconly_reg_imm); | |
| 8828 %} | |
| 8829 | |
| 8830 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8831 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8832 | |
| 8833 size(4); | |
| 8834 format %{ "BTST $op2,$op1" %} | |
| 8835 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8836 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8837 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8838 %} | |
| 8839 | |
| 8840 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8841 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8842 | |
| 8843 size(4); | |
| 8844 format %{ "BTST $op2,$op1" %} | |
| 8845 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8846 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8847 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8848 %} | |
| 8849 | |
| 8850 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8851 match(Set xcc (CmpL op1 op2)); | |
| 8852 effect( DEF xcc, USE op1, USE op2 ); | |
| 8853 | |
| 8854 size(4); | |
| 8855 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8856 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8857 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8858 ins_pipe(ialu_cconly_reg_reg); | |
| 8859 %} | |
| 8860 | |
| 8861 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8862 match(Set xcc (CmpL op1 con)); | |
| 8863 effect( DEF xcc, USE op1, USE con ); | |
| 8864 | |
| 8865 size(4); | |
| 8866 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8867 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8868 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8869 ins_pipe(ialu_cconly_reg_reg); | |
| 8870 %} | |
| 8871 | |
| 8872 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8873 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8874 effect( DEF xcc, USE op1, USE op2 ); | |
| 8875 | |
| 8876 size(4); | |
| 8877 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8878 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8879 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8880 ins_pipe(ialu_cconly_reg_reg); | |
| 8881 %} | |
| 8882 | |
| 8883 // useful for checking the alignment of a pointer: | |
| 8884 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8885 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8886 effect( DEF xcc, USE op1, USE con ); | |
| 8887 | |
| 8888 size(4); | |
| 8889 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8890 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8891 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8892 ins_pipe(ialu_cconly_reg_reg); | |
| 8893 %} | |
| 8894 | |
| 8895 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8896 match(Set icc (CmpU op1 op2)); | |
| 8897 | |
| 8898 size(4); | |
| 8899 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8900 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8901 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8902 ins_pipe(ialu_cconly_reg_imm); | |
| 8903 %} | |
| 8904 | |
| 8905 // Compare Pointers | |
| 8906 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8907 match(Set pcc (CmpP op1 op2)); | |
| 8908 | |
| 8909 size(4); | |
| 8910 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8911 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8912 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8913 ins_pipe(ialu_cconly_reg_reg); | |
| 8914 %} | |
| 8915 | |
| 8916 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8917 match(Set pcc (CmpP op1 op2)); | |
| 8918 | |
| 8919 size(4); | |
| 8920 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8921 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8922 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8923 ins_pipe(ialu_cconly_reg_imm); | |
| 8924 %} | |
| 8925 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8926 // Compare Narrow oops |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8927 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8928 match(Set icc (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8929 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8930 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8931 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8932 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8933 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8934 ins_pipe(ialu_cconly_reg_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8935 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8936 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8937 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8938 match(Set icc (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8939 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8940 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8941 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8942 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8943 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8944 ins_pipe(ialu_cconly_reg_imm); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8945 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8946 |
| 0 | 8947 //----------Max and Min-------------------------------------------------------- |
| 8948 // Min Instructions | |
| 8949 // Conditional move for min | |
| 8950 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8951 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8952 | |
| 8953 size(4); | |
| 8954 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 8955 opcode(Assembler::less); | |
| 8956 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8957 ins_pipe(ialu_reg_flags); | |
| 8958 %} | |
| 8959 | |
| 8960 // Min Register with Register. | |
| 8961 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 8962 match(Set op2 (MinI op1 op2)); | |
| 8963 ins_cost(DEFAULT_COST*2); | |
| 8964 expand %{ | |
| 8965 flagsReg icc; | |
| 8966 compI_iReg(icc,op1,op2); | |
| 8967 cmovI_reg_lt(op2,op1,icc); | |
| 8968 %} | |
| 8969 %} | |
| 8970 | |
| 8971 // Max Instructions | |
| 8972 // Conditional move for max | |
| 8973 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8974 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8975 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 8976 opcode(Assembler::greater); | |
| 8977 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8978 ins_pipe(ialu_reg_flags); | |
| 8979 %} | |
| 8980 | |
| 8981 // Max Register with Register | |
| 8982 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 8983 match(Set op2 (MaxI op1 op2)); | |
| 8984 ins_cost(DEFAULT_COST*2); | |
| 8985 expand %{ | |
| 8986 flagsReg icc; | |
| 8987 compI_iReg(icc,op1,op2); | |
| 8988 cmovI_reg_gt(op2,op1,icc); | |
| 8989 %} | |
| 8990 %} | |
| 8991 | |
| 8992 | |
| 8993 //----------Float Compares---------------------------------------------------- | |
| 8994 // Compare floating, generate condition code | |
| 8995 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 8996 match(Set fcc (CmpF src1 src2)); | |
| 8997 | |
| 8998 size(4); | |
| 8999 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 9000 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 9001 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 9002 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 9003 %} | |
| 9004 | |
| 9005 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 9006 match(Set fcc (CmpD src1 src2)); | |
| 9007 | |
| 9008 size(4); | |
| 9009 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 9010 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 9011 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 9012 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 9013 %} | |
| 9014 | |
| 9015 | |
| 9016 // Compare floating, generate -1,0,1 | |
| 9017 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 9018 match(Set dst (CmpF3 src1 src2)); | |
| 9019 effect(KILL fcc0); | |
| 9020 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9021 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 9022 // Primary = float | |
| 9023 opcode( true ); | |
| 9024 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9025 ins_pipe( floating_cmp ); | |
| 9026 %} | |
| 9027 | |
| 9028 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 9029 match(Set dst (CmpD3 src1 src2)); | |
| 9030 effect(KILL fcc0); | |
| 9031 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9032 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 9033 // Primary = double (not float) | |
| 9034 opcode( false ); | |
| 9035 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9036 ins_pipe( floating_cmp ); | |
| 9037 %} | |
| 9038 | |
| 9039 //----------Branches--------------------------------------------------------- | |
| 9040 // Jump | |
| 9041 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9042 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9043 match(Jump switch_val); | |
| 9044 | |
| 9045 ins_cost(350); | |
| 9046 | |
| 2008 | 9047 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9048 "LD [O7 + $switch_val], O7\n\t" | |
| 0 | 9049 "JUMP O7" |
| 9050 %} | |
| 2008 | 9051 ins_encode %{ |
| 9052 // Calculate table address into a register. | |
| 9053 Register table_reg; | |
| 9054 Register label_reg = O7; | |
| 9055 if (constant_offset() == 0) { | |
| 9056 table_reg = $constanttablebase; | |
| 9057 } else { | |
| 9058 table_reg = O7; | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
9059 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
9060 __ add($constanttablebase, con_offset, table_reg); |
| 2008 | 9061 } |
| 9062 | |
| 9063 // Jump to base address + switch value | |
| 9064 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9065 __ jmp(label_reg, G0); | |
| 9066 __ delayed()->nop(); | |
| 9067 %} | |
| 0 | 9068 ins_pc_relative(1); |
| 9069 ins_pipe(ialu_reg_reg); | |
| 9070 %} | |
| 9071 | |
| 9072 // Direct Branch. Use V8 version with longer range. | |
| 9073 instruct branch(label labl) %{ | |
| 9074 match(Goto); | |
| 9075 effect(USE labl); | |
| 9076 | |
| 9077 size(8); | |
| 9078 ins_cost(BRANCH_COST); | |
| 9079 format %{ "BA $labl" %} | |
| 9080 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
| 9081 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
| 9082 ins_encode( enc_ba( labl ) ); | |
| 9083 ins_pc_relative(1); | |
| 9084 ins_pipe(br); | |
| 9085 %} | |
| 9086 | |
| 9087 // Conditional Direct Branch | |
| 9088 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9089 match(If cmp icc); | |
| 9090 effect(USE labl); | |
| 9091 | |
| 9092 size(8); | |
| 9093 ins_cost(BRANCH_COST); | |
| 9094 format %{ "BP$cmp $icc,$labl" %} | |
| 9095 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9096 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9097 ins_pc_relative(1); | |
| 9098 ins_pipe(br_cc); | |
| 9099 %} | |
| 9100 | |
| 9101 // Branch-on-register tests all 64 bits. We assume that values | |
| 9102 // in 64-bit registers always remains zero or sign extended | |
| 9103 // unless our code munges the high bits. Interrupts can chop | |
| 9104 // the high order bits to zero or sign at any time. | |
| 9105 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9106 match(If cmp (CmpI op1 zero)); | |
| 9107 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9108 effect(USE labl); | |
| 9109 | |
| 9110 size(8); | |
| 9111 ins_cost(BRANCH_COST); | |
| 9112 format %{ "BR$cmp $op1,$labl" %} | |
| 9113 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9114 ins_pc_relative(1); | |
| 9115 ins_pipe(br_reg); | |
| 9116 %} | |
| 9117 | |
| 9118 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9119 match(If cmp (CmpP op1 null)); | |
| 9120 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9121 effect(USE labl); | |
| 9122 | |
| 9123 size(8); | |
| 9124 ins_cost(BRANCH_COST); | |
| 9125 format %{ "BR$cmp $op1,$labl" %} | |
| 9126 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9127 ins_pc_relative(1); | |
| 9128 ins_pipe(br_reg); | |
| 9129 %} | |
| 9130 | |
| 9131 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9132 match(If cmp (CmpL op1 zero)); | |
| 9133 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9134 effect(USE labl); | |
| 9135 | |
| 9136 size(8); | |
| 9137 ins_cost(BRANCH_COST); | |
| 9138 format %{ "BR$cmp $op1,$labl" %} | |
| 9139 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9140 ins_pc_relative(1); | |
| 9141 ins_pipe(br_reg); | |
| 9142 %} | |
| 9143 | |
| 9144 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9145 match(If cmp icc); | |
| 9146 effect(USE labl); | |
| 9147 | |
| 9148 format %{ "BP$cmp $icc,$labl" %} | |
| 9149 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9150 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9151 ins_pc_relative(1); | |
| 9152 ins_pipe(br_cc); | |
| 9153 %} | |
| 9154 | |
| 9155 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9156 match(If cmp pcc); | |
| 9157 effect(USE labl); | |
| 9158 | |
| 9159 size(8); | |
| 9160 ins_cost(BRANCH_COST); | |
| 9161 format %{ "BP$cmp $pcc,$labl" %} | |
| 9162 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9163 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
| 9164 ins_pc_relative(1); | |
| 9165 ins_pipe(br_cc); | |
| 9166 %} | |
| 9167 | |
| 9168 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9169 match(If cmp fcc); | |
| 9170 effect(USE labl); | |
| 9171 | |
| 9172 size(8); | |
| 9173 ins_cost(BRANCH_COST); | |
| 9174 format %{ "FBP$cmp $fcc,$labl" %} | |
| 9175 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9176 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
| 9177 ins_pc_relative(1); | |
| 9178 ins_pipe(br_fcc); | |
| 9179 %} | |
| 9180 | |
| 9181 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9182 match(CountedLoopEnd cmp icc); | |
| 9183 effect(USE labl); | |
| 9184 | |
| 9185 size(8); | |
| 9186 ins_cost(BRANCH_COST); | |
| 9187 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9188 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9189 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9190 ins_pc_relative(1); | |
| 9191 ins_pipe(br_cc); | |
| 9192 %} | |
| 9193 | |
| 9194 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9195 match(CountedLoopEnd cmp icc); | |
| 9196 effect(USE labl); | |
| 9197 | |
| 9198 size(8); | |
| 9199 ins_cost(BRANCH_COST); | |
| 9200 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9201 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9202 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9203 ins_pc_relative(1); | |
| 9204 ins_pipe(br_cc); | |
| 9205 %} | |
| 9206 | |
| 9207 // ============================================================================ | |
| 9208 // Long Compare | |
| 9209 // | |
| 9210 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9211 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9212 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9213 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9214 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9215 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9216 // NE test is negated from that. | |
| 9217 | |
| 9218 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9219 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9220 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9221 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9222 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9223 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9224 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9225 // both forms beat the trinary form of long-compare and both are very useful | |
| 9226 // on Intel which has so few registers. | |
| 9227 | |
| 9228 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9229 match(If cmp xcc); | |
| 9230 effect(USE labl); | |
| 9231 | |
| 9232 size(8); | |
| 9233 ins_cost(BRANCH_COST); | |
| 9234 format %{ "BP$cmp $xcc,$labl" %} | |
| 9235 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9236 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
| 9237 ins_pc_relative(1); | |
| 9238 ins_pipe(br_cc); | |
| 9239 %} | |
| 9240 | |
| 9241 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9242 // This is the test to avoid. | |
| 9243 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9244 match(Set dst (CmpL3 src1 src2) ); | |
| 9245 effect( KILL ccr ); | |
| 9246 ins_cost(6*DEFAULT_COST); | |
| 9247 size(24); | |
| 9248 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9249 "\tBLT,a,pn done\n" | |
| 9250 "\tMOV -1,$dst\t! delay slot\n" | |
| 9251 "\tBGT,a,pn done\n" | |
| 9252 "\tMOV 1,$dst\t! delay slot\n" | |
| 9253 "\tCLR $dst\n" | |
| 9254 "done:" %} | |
| 9255 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9256 ins_pipe(cmpL_reg); | |
| 9257 %} | |
| 9258 | |
| 9259 // Conditional move | |
| 9260 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9261 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9262 ins_cost(150); | |
| 9263 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9264 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9265 ins_pipe(ialu_reg); | |
| 9266 %} | |
| 9267 | |
| 9268 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9269 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9270 ins_cost(140); | |
| 9271 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9272 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9273 ins_pipe(ialu_imm); | |
| 9274 %} | |
| 9275 | |
| 9276 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9277 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9278 ins_cost(150); | |
| 9279 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9280 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9281 ins_pipe(ialu_reg); | |
| 9282 %} | |
| 9283 | |
| 9284 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9285 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9286 ins_cost(140); | |
| 9287 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9288 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9289 ins_pipe(ialu_imm); | |
| 9290 %} | |
| 9291 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9292 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9293 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9294 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9295 format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9296 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9297 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9298 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9299 |
| 0 | 9300 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9301 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9302 ins_cost(150); | |
| 9303 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9304 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9305 ins_pipe(ialu_reg); | |
| 9306 %} | |
| 9307 | |
| 9308 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9309 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9310 ins_cost(140); | |
| 9311 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9312 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9313 ins_pipe(ialu_imm); | |
| 9314 %} | |
| 9315 | |
| 9316 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9317 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9318 ins_cost(150); | |
| 9319 opcode(0x101); | |
| 9320 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9321 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9322 ins_pipe(int_conditional_float_move); | |
| 9323 %} | |
| 9324 | |
| 9325 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9326 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9327 ins_cost(150); | |
| 9328 opcode(0x102); | |
| 9329 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9330 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9331 ins_pipe(int_conditional_float_move); | |
| 9332 %} | |
| 9333 | |
| 9334 // ============================================================================ | |
| 9335 // Safepoint Instruction | |
| 9336 instruct safePoint_poll(iRegP poll) %{ | |
| 9337 match(SafePoint poll); | |
| 9338 effect(USE poll); | |
| 9339 | |
| 9340 size(4); | |
| 9341 #ifdef _LP64 | |
| 9342 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9343 #else | |
| 9344 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9345 #endif | |
| 9346 ins_encode %{ | |
| 9347 __ relocate(relocInfo::poll_type); | |
| 9348 __ ld_ptr($poll$$Register, 0, G0); | |
| 9349 %} | |
| 9350 ins_pipe(loadPollP); | |
| 9351 %} | |
| 9352 | |
| 9353 // ============================================================================ | |
| 9354 // Call Instructions | |
| 9355 // Call Java Static Instruction | |
| 9356 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9357 match(CallStaticJava); | |
| 1567 | 9358 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9359 effect(USE meth); |
| 9360 | |
| 9361 size(8); | |
| 9362 ins_cost(CALL_COST); | |
| 9363 format %{ "CALL,static ; NOP ==> " %} | |
| 9364 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9365 ins_pc_relative(1); | |
| 9366 ins_pipe(simple_call); | |
| 9367 %} | |
| 9368 | |
| 1567 | 9369 // Call Java Static Instruction (method handle version) |
| 9370 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9371 match(CallStaticJava); | |
| 9372 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9373 effect(USE meth, KILL l7_mh_SP_save); | |
| 9374 | |
| 9375 size(8); | |
| 9376 ins_cost(CALL_COST); | |
| 9377 format %{ "CALL,static/MethodHandle" %} | |
| 9378 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9379 ins_pc_relative(1); | |
| 9380 ins_pipe(simple_call); | |
| 9381 %} | |
| 9382 | |
| 0 | 9383 // Call Java Dynamic Instruction |
| 9384 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9385 match(CallDynamicJava); | |
| 9386 effect(USE meth); | |
| 9387 | |
| 9388 ins_cost(CALL_COST); | |
| 9389 format %{ "SET (empty),R_G5\n\t" | |
| 9390 "CALL,dynamic ; NOP ==> " %} | |
| 9391 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9392 ins_pc_relative(1); | |
| 9393 ins_pipe(call); | |
| 9394 %} | |
| 9395 | |
| 9396 // Call Runtime Instruction | |
| 9397 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9398 match(CallRuntime); | |
| 9399 effect(USE meth, KILL l7); | |
| 9400 ins_cost(CALL_COST); | |
| 9401 format %{ "CALL,runtime" %} | |
| 9402 ins_encode( Java_To_Runtime( meth ), | |
| 9403 call_epilog, adjust_long_from_native_call ); | |
| 9404 ins_pc_relative(1); | |
| 9405 ins_pipe(simple_call); | |
| 9406 %} | |
| 9407 | |
| 9408 // Call runtime without safepoint - same as CallRuntime | |
| 9409 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9410 match(CallLeaf); | |
| 9411 effect(USE meth, KILL l7); | |
| 9412 ins_cost(CALL_COST); | |
| 9413 format %{ "CALL,runtime leaf" %} | |
| 9414 ins_encode( Java_To_Runtime( meth ), | |
| 9415 call_epilog, | |
| 9416 adjust_long_from_native_call ); | |
| 9417 ins_pc_relative(1); | |
| 9418 ins_pipe(simple_call); | |
| 9419 %} | |
| 9420 | |
| 9421 // Call runtime without safepoint - same as CallLeaf | |
| 9422 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9423 match(CallLeafNoFP); | |
| 9424 effect(USE meth, KILL l7); | |
| 9425 ins_cost(CALL_COST); | |
| 9426 format %{ "CALL,runtime leaf nofp" %} | |
| 9427 ins_encode( Java_To_Runtime( meth ), | |
| 9428 call_epilog, | |
| 9429 adjust_long_from_native_call ); | |
| 9430 ins_pc_relative(1); | |
| 9431 ins_pipe(simple_call); | |
| 9432 %} | |
| 9433 | |
| 9434 // Tail Call; Jump from runtime stub to Java code. | |
| 9435 // Also known as an 'interprocedural jump'. | |
| 9436 // Target of jump will eventually return to caller. | |
| 9437 // TailJump below removes the return address. | |
| 9438 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 9439 match(TailCall jump_target method_oop ); | |
| 9440 | |
| 9441 ins_cost(CALL_COST); | |
| 9442 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 9443 ins_encode(form_jmpl(jump_target)); | |
| 9444 ins_pipe(tail_call); | |
| 9445 %} | |
| 9446 | |
| 9447 | |
| 9448 // Return Instruction | |
| 9449 instruct Ret() %{ | |
| 9450 match(Return); | |
| 9451 | |
| 9452 // The epilogue node did the ret already. | |
| 9453 size(0); | |
| 9454 format %{ "! return" %} | |
| 9455 ins_encode(); | |
| 9456 ins_pipe(empty); | |
| 9457 %} | |
| 9458 | |
| 9459 | |
| 9460 // Tail Jump; remove the return address; jump to target. | |
| 9461 // TailCall above leaves the return address around. | |
| 9462 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 9463 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 9464 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 9465 // in %i0. | |
| 9466 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 9467 match( TailJump jump_target ex_oop ); | |
| 9468 ins_cost(CALL_COST); | |
| 9469 format %{ "! discard R_O7\n\t" | |
| 9470 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 9471 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 9472 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 9473 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 9474 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 9475 ins_pipe(tail_call); | |
| 9476 %} | |
| 9477 | |
| 9478 // Create exception oop: created by stack-crawling runtime code. | |
| 9479 // Created exception is now available to this handler, and is setup | |
| 9480 // just prior to jumping to this handler. No code emitted. | |
| 9481 instruct CreateException( o0RegP ex_oop ) | |
| 9482 %{ | |
| 9483 match(Set ex_oop (CreateEx)); | |
| 9484 ins_cost(0); | |
| 9485 | |
| 9486 size(0); | |
| 9487 // use the following format syntax | |
| 9488 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 9489 ins_encode(); | |
| 9490 ins_pipe(empty); | |
| 9491 %} | |
| 9492 | |
| 9493 | |
| 9494 // Rethrow exception: | |
| 9495 // The exception oop will come in the first argument position. | |
| 9496 // Then JUMP (not call) to the rethrow stub code. | |
| 9497 instruct RethrowException() | |
| 9498 %{ | |
| 9499 match(Rethrow); | |
| 9500 ins_cost(CALL_COST); | |
| 9501 | |
| 9502 // use the following format syntax | |
| 9503 format %{ "Jmp rethrow_stub" %} | |
| 9504 ins_encode(enc_rethrow); | |
| 9505 ins_pipe(tail_call); | |
| 9506 %} | |
| 9507 | |
| 9508 | |
| 9509 // Die now | |
| 9510 instruct ShouldNotReachHere( ) | |
| 9511 %{ | |
| 9512 match(Halt); | |
| 9513 ins_cost(CALL_COST); | |
| 9514 | |
| 9515 size(4); | |
| 9516 // Use the following format syntax | |
| 9517 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 9518 ins_encode( form2_illtrap() ); | |
| 9519 ins_pipe(tail_call); | |
| 9520 %} | |
| 9521 | |
| 9522 // ============================================================================ | |
| 9523 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 9524 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 9525 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 9526 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 9527 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 9528 match(Set index (PartialSubtypeCheck sub super)); | |
| 9529 effect( KILL pcc, KILL o7 ); | |
| 9530 ins_cost(DEFAULT_COST*10); | |
| 9531 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 9532 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9533 ins_pipe(partial_subtype_check_pipe); | |
| 9534 %} | |
| 9535 | |
| 9536 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 9537 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 9538 effect( KILL idx, KILL o7 ); | |
| 9539 ins_cost(DEFAULT_COST*10); | |
| 9540 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 9541 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9542 ins_pipe(partial_subtype_check_pipe); | |
| 9543 %} | |
| 9544 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9545 |
| 0 | 9546 // ============================================================================ |
| 9547 // inlined locking and unlocking | |
| 9548 | |
| 9549 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9550 match(Set pcc (FastLock object box)); | |
| 9551 | |
| 9552 effect(KILL scratch, TEMP scratch2); | |
| 9553 ins_cost(100); | |
| 9554 | |
| 9555 size(4*112); // conservative overestimation ... | |
| 9556 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9557 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 9558 ins_pipe(long_memory_op); | |
| 9559 %} | |
| 9560 | |
| 9561 | |
| 9562 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9563 match(Set pcc (FastUnlock object box)); | |
| 9564 effect(KILL scratch, TEMP scratch2); | |
| 9565 ins_cost(100); | |
| 9566 | |
| 9567 size(4*120); // conservative overestimation ... | |
| 9568 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9569 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 9570 ins_pipe(long_memory_op); | |
| 9571 %} | |
| 9572 | |
| 9573 // Count and Base registers are fixed because the allocator cannot | |
| 9574 // kill unknown registers. The encodings are generic. | |
| 9575 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 9576 match(Set dummy (ClearArray cnt base)); | |
| 9577 effect(TEMP temp, KILL ccr); | |
| 9578 ins_cost(300); | |
| 9579 format %{ "MOV $cnt,$temp\n" | |
| 9580 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 9581 " BRge loop\t\t! Clearing loop\n" | |
| 9582 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 9583 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 9584 ins_pipe(long_memory_op); | |
| 9585 %} | |
| 9586 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9587 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9588 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9589 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9590 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 9591 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9592 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9593 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 9594 ins_pipe(long_memory_op); |
| 9595 %} | |
| 9596 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9597 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9598 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9599 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9600 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 9601 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9602 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9603 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 9604 ins_pipe(long_memory_op); |
| 9605 %} | |
| 9606 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9607 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9608 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 9609 match(Set result (AryEq ary1 ary2)); |
| 9610 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 9611 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9612 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9613 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 9614 ins_pipe(long_memory_op); |
| 9615 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9616 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9617 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9618 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9619 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9620 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9621 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9622 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9623 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9624 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9625 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9626 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9627 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9628 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9629 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9630 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9631 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9632 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9633 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9634 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9635 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9636 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9637 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9638 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9639 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9640 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9641 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9642 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9643 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9644 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9645 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9646 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9647 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9648 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9649 __ srl(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9650 __ srl(Rsrc, 0, Rdst); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9651 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9652 __ srl(Rdst, 2, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9653 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9654 __ srl(Rdst, 4, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9655 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9656 __ srl(Rdst, 8, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9657 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9658 __ srl(Rdst, 16, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9659 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9660 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9661 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9662 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9663 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9664 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9665 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9666 |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9667 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9668 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9669 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9670 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9671 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9672 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9673 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9674 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9675 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9676 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9677 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9678 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9679 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9680 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9681 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9682 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9683 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9684 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9685 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9686 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9687 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9688 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9689 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9690 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9691 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9692 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9693 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9694 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9695 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9696 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9697 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9698 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9699 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9700 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9701 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9702 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9703 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9704 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9705 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9706 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9707 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9708 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9709 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9710 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9711 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9712 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9713 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9714 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9715 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9716 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9717 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9718 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9719 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9720 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9721 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9722 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9723 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9724 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9725 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9726 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9727 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9728 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9729 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9730 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9731 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9732 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9733 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9734 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9735 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9736 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9737 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9738 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9739 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9740 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9741 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9742 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9743 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9744 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9745 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9746 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9747 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9748 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9749 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9750 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9751 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9752 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9753 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9754 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9755 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9756 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9757 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9758 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9759 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9760 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9761 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9762 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9763 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9764 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9765 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9766 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9767 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9768 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9769 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9770 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9771 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9772 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9773 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9774 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9775 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9776 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9777 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9778 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9779 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9780 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9781 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9782 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9783 |
| 0 | 9784 // ============================================================================ |
| 9785 //------------Bytes reverse-------------------------------------------------- | |
| 9786 | |
| 9787 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 9788 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9789 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9790 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9791 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9792 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9793 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9794 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9795 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9796 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9797 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9798 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9799 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9800 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9801 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9802 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9803 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9804 match(Set dst (ReverseBytesL src)); |
| 0 | 9805 |
| 9806 // Op cost is artificially doubled to make sure that load or store | |
| 9807 // instructions are preferred over this one which requires a spill | |
| 9808 // onto a stack slot. | |
| 9809 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9810 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9811 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9812 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9813 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9814 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9815 %} |
| 0 | 9816 ins_pipe( iload_mem ); |
| 9817 %} | |
| 9818 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9819 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9820 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9821 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9822 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9823 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9824 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9825 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9826 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9827 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9828 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9829 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9830 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9831 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9832 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9833 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9834 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9835 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9836 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9837 match(Set dst (ReverseBytesS src)); |
| 0 | 9838 |
| 9839 // Op cost is artificially doubled to make sure that load or store | |
| 9840 // instructions are preferred over this one which requires a spill | |
| 9841 // onto a stack slot. | |
| 9842 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9843 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9844 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9845 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9846 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9847 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9848 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9849 %} |
| 0 | 9850 ins_pipe( iload_mem ); |
| 9851 %} | |
| 9852 | |
| 9853 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9854 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 9855 match(Set dst (ReverseBytesI (LoadI src))); |
| 9856 | |
| 9857 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9858 size(4); |
| 0 | 9859 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 9860 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9861 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9862 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9863 %} |
| 0 | 9864 ins_pipe(iload_mem); |
| 9865 %} | |
| 9866 | |
| 9867 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9868 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 9869 match(Set dst (ReverseBytesL (LoadL src))); |
| 9870 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9871 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9872 size(4); |
| 0 | 9873 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 9874 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9875 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9876 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9877 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9878 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9879 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9880 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9881 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9882 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9883 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9884 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9885 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9886 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9887 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9888 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9889 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9890 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9891 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9892 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9893 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9894 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9895 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9896 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9897 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9898 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9899 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9900 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9901 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9902 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9903 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9904 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9905 %} |
| 0 | 9906 ins_pipe(iload_mem); |
| 9907 %} | |
| 9908 | |
| 9909 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9910 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 9911 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 9912 | |
| 9913 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9914 size(4); |
| 0 | 9915 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 9916 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9917 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9918 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9919 %} |
| 0 | 9920 ins_pipe(istore_mem_reg); |
| 9921 %} | |
| 9922 | |
| 9923 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9924 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 9925 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 9926 | |
| 9927 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9928 size(4); |
| 0 | 9929 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 9930 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9931 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9932 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9933 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9934 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9935 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9936 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9937 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9938 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9939 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9940 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9941 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9942 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9943 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9944 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9945 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9946 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9947 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9948 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9949 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9950 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9951 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9952 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9953 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9954 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9955 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9956 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9957 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9958 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9959 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9960 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9961 %} |
| 0 | 9962 ins_pipe(istore_mem_reg); |
| 9963 %} | |
| 9964 | |
| 9965 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 9966 // These must follow all instruction definitions as they use the names | |
| 9967 // defined in the instructions definitions. | |
| 9968 // | |
| 605 | 9969 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 9970 // |
| 9971 // peepconstraint %{ | |
| 9972 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 9973 // [, ...] ); | |
| 9974 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 9975 // | |
| 9976 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 9977 // // provide an instruction_number.operand_name for each operand that appears | |
| 9978 // // in the replacement instruction's match rule | |
| 9979 // | |
| 9980 // ---------VM FLAGS--------------------------------------------------------- | |
| 9981 // | |
| 9982 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 9983 // | |
| 9984 // Each peephole rule is given an identifying number starting with zero and | |
| 9985 // increasing by one in the order seen by the parser. An individual peephole | |
| 9986 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 9987 // on the command-line. | |
| 9988 // | |
| 9989 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 9990 // | |
| 9991 // Only match adjacent instructions in same basic block | |
| 9992 // Only equality constraints | |
| 9993 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 9994 // Only one replacement instruction | |
| 9995 // | |
| 9996 // ---------EXAMPLE---------------------------------------------------------- | |
| 9997 // | |
| 9998 // // pertinent parts of existing instructions in architecture description | |
| 9999 // instruct movI(eRegI dst, eRegI src) %{ | |
| 10000 // match(Set dst (CopyI src)); | |
| 10001 // %} | |
| 10002 // | |
| 10003 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 10004 // match(Set dst (AddI dst src)); | |
| 10005 // effect(KILL cr); | |
| 10006 // %} | |
| 10007 // | |
| 10008 // // Change (inc mov) to lea | |
| 10009 // peephole %{ | |
| 10010 // // increment preceeded by register-register move | |
| 10011 // peepmatch ( incI_eReg movI ); | |
| 10012 // // require that the destination register of the increment | |
| 10013 // // match the destination register of the move | |
| 10014 // peepconstraint ( 0.dst == 1.dst ); | |
| 10015 // // construct a replacement instruction that sets | |
| 10016 // // the destination to ( move's source register + one ) | |
| 10017 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 10018 // %} | |
| 10019 // | |
| 10020 | |
| 10021 // // Change load of spilled value to only a spill | |
| 10022 // instruct storeI(memory mem, eRegI src) %{ | |
| 10023 // match(Set mem (StoreI mem src)); | |
| 10024 // %} | |
| 10025 // | |
| 10026 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10027 // match(Set dst (LoadI mem)); | |
| 10028 // %} | |
| 10029 // | |
| 10030 // peephole %{ | |
| 10031 // peepmatch ( loadI storeI ); | |
| 10032 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10033 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 10034 // %} | |
| 10035 | |
| 10036 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 10037 // These must follow all instruction definitions as they use the names | |
| 10038 // defined in the instructions definitions. | |
| 10039 // | |
| 10040 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 10041 | |
| 10042 //----------PIPELINE----------------------------------------------------------- | |
| 10043 // Rules which define the behavior of the target architectures pipeline. |