Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 6853:d804e148cff8
Merge
| author | kvn |
|---|---|
| date | Fri, 12 Oct 2012 09:22:52 -0700 |
| parents | d8ce2825b193 f6badecb7ea7 |
| children | 00af3a3a8df4 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 4950 | 2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
| 126 // Class for all registers | |
| 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 128 // Class for general registers | |
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129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
| 0 | 130 // Class for general registers which may be used for implicit null checks on win95 |
| 131 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
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132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); |
| 0 | 133 // Class of "X" registers |
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134 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
| 0 | 135 // Class of registers that can appear in an address with no offset. |
| 136 // EBP and ESP require an extra instruction byte for zero offset. | |
| 137 // Used in fast-unlock | |
| 138 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 139 // Class for general registers not including ECX | |
| 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 141 // Class for general registers not including EAX | |
| 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 143 // Class for general registers not including EAX or EBX. | |
| 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 145 // Class of EAX (for multiply and divide operations) | |
| 146 reg_class eax_reg(EAX); | |
| 147 // Class of EBX (for atomic add) | |
| 148 reg_class ebx_reg(EBX); | |
| 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 150 reg_class ecx_reg(ECX); | |
| 151 // Class of EDX (for multiply and divide operations) | |
| 152 reg_class edx_reg(EDX); | |
| 153 // Class of EDI (for synchronization) | |
| 154 reg_class edi_reg(EDI); | |
| 155 // Class of ESI (for synchronization) | |
| 156 reg_class esi_reg(ESI); | |
| 157 // Singleton class for interpreter's stack pointer | |
| 158 reg_class ebp_reg(EBP); | |
| 159 // Singleton class for stack pointer | |
| 160 reg_class sp_reg(ESP); | |
| 161 // Singleton class for instruction pointer | |
| 162 // reg_class ip_reg(EIP); | |
| 163 // Class of integer register pairs | |
| 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 165 // Class of integer register pairs that aligns with calling convention | |
| 166 reg_class eadx_reg( EAX,EDX ); | |
| 167 reg_class ebcx_reg( ECX,EBX ); | |
| 168 // Not AX or DX, used in divides | |
| 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 170 | |
| 171 // Floating point registers. Notice FPR0 is not a choice. | |
| 172 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 173 // a 2-address instructions out of Intels FP stack. | |
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174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
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175 |
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176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
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177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
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178 FPR7L,FPR7H ); |
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179 |
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180 reg_class fp_flt_reg0( FPR1L ); |
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181 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
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182 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
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183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
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184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
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185 |
| 0 | 186 %} |
| 187 | |
| 188 | |
| 189 //----------SOURCE BLOCK------------------------------------------------------- | |
| 190 // This is a block of C++ code which provides values, functions, and | |
| 191 // definitions necessary in the rest of the architecture description | |
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192 source_hpp %{ |
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193 // Must be visible to the DFA in dfa_x86_32.cpp |
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194 extern bool is_operand_hi32_zero(Node* n); |
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195 %} |
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196 |
| 0 | 197 source %{ |
| 304 | 198 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 199 #define RELOC_DISP32 Assembler::disp32_operand |
| 200 | |
| 201 #define __ _masm. | |
| 202 | |
| 203 // How to find the high register of a Long pair, given the low register | |
| 204 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 205 | |
| 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 207 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 208 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 209 | |
| 210 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 213 // of 128-bits operands for SSE instructions. | |
| 214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 215 // Store the value to a 128-bits operand. | |
| 216 operand[0] = lo; | |
| 217 operand[1] = hi; | |
| 218 return operand; | |
| 219 } | |
| 220 | |
| 221 // Buffer for 128-bits masks used by SSE instructions. | |
| 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 223 | |
| 224 // Static initialization during VM startup. | |
| 225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 229 | |
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230 // Offset hacking within calls. |
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231 static int pre_call_FPU_size() { |
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232 if (Compile::current()->in_24_bit_fp_mode()) |
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233 return 6; // fldcw |
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234 return 0; |
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235 } |
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236 |
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237 static int preserve_SP_size() { |
| 4759 | 238 return 2; // op, rm(reg/reg) |
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239 } |
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240 |
| 0 | 241 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 242 // from the start of the call to the point where the return address | |
| 243 // will point. | |
| 244 int MachCallStaticJavaNode::ret_addr_offset() { | |
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245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points |
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246 if (_method_handle_invoke) |
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247 offset += preserve_SP_size(); |
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248 return offset; |
| 0 | 249 } |
| 250 | |
| 251 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points |
| 0 | 253 } |
| 254 | |
| 255 static int sizeof_FFree_Float_Stack_All = -1; | |
| 256 | |
| 257 int MachCallRuntimeNode::ret_addr_offset() { | |
| 258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); |
| 0 | 260 } |
| 261 | |
| 262 // Indicate if the safepoint node needs the polling page as an input. | |
| 263 // Since x86 does have absolute addressing, it doesn't. | |
| 264 bool SafePointNode::needs_polling_address_input() { | |
| 265 return false; | |
| 266 } | |
| 267 | |
| 268 // | |
| 269 // Compute padding required for nodes which need alignment | |
| 270 // | |
| 271 | |
| 272 // The address of the call instruction needs to be 4-byte aligned to | |
| 273 // ensure that it does not span a cache line so that it can be patched. | |
| 274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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275 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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276 current_offset += 1; // skip call opcode byte |
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277 return round_to(current_offset, alignment_required()) - current_offset; |
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278 } |
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279 |
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280 // The address of the call instruction needs to be 4-byte aligned to |
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281 // ensure that it does not span a cache line so that it can be patched. |
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282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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283 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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284 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 285 current_offset += 1; // skip call opcode byte |
| 286 return round_to(current_offset, alignment_required()) - current_offset; | |
| 287 } | |
| 288 | |
| 289 // The address of the call instruction needs to be 4-byte aligned to | |
| 290 // ensure that it does not span a cache line so that it can be patched. | |
| 291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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292 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
| 0 | 293 current_offset += 5; // skip MOV instruction |
| 294 current_offset += 1; // skip call opcode byte | |
| 295 return round_to(current_offset, alignment_required()) - current_offset; | |
| 296 } | |
| 297 | |
| 298 // EMIT_RM() | |
| 299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 301 cbuf.insts()->emit_int8(c); |
| 0 | 302 } |
| 303 | |
| 304 // EMIT_CC() | |
| 305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 306 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 307 cbuf.insts()->emit_int8(c); |
| 0 | 308 } |
| 309 | |
| 310 // EMIT_OPCODE() | |
| 311 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 312 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 313 } |
| 314 | |
| 315 // EMIT_OPCODE() w/ relocation information | |
| 316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 317 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 318 emit_opcode(cbuf, code); |
| 319 } | |
| 320 | |
| 321 // EMIT_D8() | |
| 322 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 323 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 324 } |
| 325 | |
| 326 // EMIT_D16() | |
| 327 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 328 cbuf.insts()->emit_int16(d16); |
| 0 | 329 } |
| 330 | |
| 331 // EMIT_D32() | |
| 332 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 333 cbuf.insts()->emit_int32(d32); |
| 0 | 334 } |
| 335 | |
| 336 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 338 int format) { | |
| 1748 | 339 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 340 cbuf.insts()->emit_int32(d32); | |
| 0 | 341 } |
| 342 | |
| 343 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 345 int format) { | |
| 346 #ifdef ASSERT | |
| 347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 349 } |
| 350 #endif | |
| 1748 | 351 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 352 cbuf.insts()->emit_int32(d32); | |
| 0 | 353 } |
| 354 | |
| 355 // Access stack slot for load or store | |
| 356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 358 if( -128 <= disp && disp <= 127 ) { | |
| 359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 361 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 362 } else { | |
| 363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 365 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 366 } | |
| 367 } | |
| 368 | |
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369 // rRegI ereg, memory mem) %{ // emit_reg_mem |
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370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 371 // There is no index & no scale, use form without SIB byte |
| 372 if ((index == 0x4) && | |
| 373 (scale == 0) && (base != ESP_enc)) { | |
| 374 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 375 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 376 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 377 } | |
| 378 else { // If 8-bit displacement, mode 0x1 | |
| 379 if ((displace >= -128) && (displace <= 127) | |
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380 && (disp_reloc == relocInfo::none) ) { |
| 0 | 381 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 382 emit_d8(cbuf, displace); | |
| 383 } | |
| 384 else { // If 32-bit displacement | |
| 385 if (base == -1) { // Special flag for absolute address | |
| 386 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 387 // (manual lies; no SIB needed here) | |
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388 if ( disp_reloc != relocInfo::none ) { |
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389 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 390 } else { |
| 391 emit_d32 (cbuf, displace); | |
| 392 } | |
| 393 } | |
| 394 else { // Normal base + offset | |
| 395 emit_rm(cbuf, 0x2, reg_encoding, base); | |
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396 if ( disp_reloc != relocInfo::none ) { |
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397 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 398 } else { |
| 399 emit_d32 (cbuf, displace); | |
| 400 } | |
| 401 } | |
| 402 } | |
| 403 } | |
| 404 } | |
| 405 else { // Else, encode with the SIB byte | |
| 406 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 407 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 408 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 409 emit_rm(cbuf, scale, index, base); | |
| 410 } | |
| 411 else { // If 8-bit displacement, mode 0x1 | |
| 412 if ((displace >= -128) && (displace <= 127) | |
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413 && (disp_reloc == relocInfo::none) ) { |
| 0 | 414 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 415 emit_rm(cbuf, scale, index, base); | |
| 416 emit_d8(cbuf, displace); | |
| 417 } | |
| 418 else { // If 32-bit displacement | |
| 419 if (base == 0x04 ) { | |
| 420 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 421 emit_rm(cbuf, scale, index, 0x04); | |
| 422 } else { | |
| 423 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 424 emit_rm(cbuf, scale, index, base); | |
| 425 } | |
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426 if ( disp_reloc != relocInfo::none ) { |
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427 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 428 } else { |
| 429 emit_d32 (cbuf, displace); | |
| 430 } | |
| 431 } | |
| 432 } | |
| 433 } | |
| 434 } | |
| 435 | |
| 436 | |
| 437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 438 if( dst_encoding == src_encoding ) { | |
| 439 // reg-reg copy, use an empty encoding | |
| 440 } else { | |
| 441 emit_opcode( cbuf, 0x8B ); | |
| 442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 443 } | |
| 444 } | |
| 445 | |
| 4759 | 446 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 447 Label exit; | |
| 448 __ jccb(Assembler::noParity, exit); | |
| 449 __ pushf(); | |
| 450 // | |
| 451 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 452 // zero OF,AF,SF for NaN values. | |
| 453 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 454 // values returns 'less than' result (CF is set). | |
| 455 // Leave the rest of flags unchanged. | |
| 456 // | |
| 457 // 7 6 5 4 3 2 1 0 | |
| 458 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 459 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 460 // | |
| 461 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 462 __ popf(); | |
| 463 __ bind(exit); | |
| 464 } | |
| 465 | |
| 466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 467 Label done; | |
| 468 __ movl(dst, -1); | |
| 469 __ jcc(Assembler::parity, done); | |
| 470 __ jcc(Assembler::below, done); | |
| 471 __ setb(Assembler::notEqual, dst); | |
| 472 __ movzbl(dst, dst); | |
| 473 __ bind(done); | |
| 0 | 474 } |
| 475 | |
| 476 | |
| 477 //============================================================================= | |
| 2008 | 478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 479 | |
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480 int Compile::ConstantTable::calculate_table_base_offset() const { |
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481 return 0; // absolute addressing, no offset |
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482 } |
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483 |
| 2008 | 484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 485 // Empty encoding | |
| 486 } | |
| 487 | |
| 488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 489 return 0; | |
| 490 } | |
| 491 | |
| 492 #ifndef PRODUCT | |
| 493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 494 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 495 } | |
| 496 #endif | |
| 497 | |
| 498 | |
| 499 //============================================================================= | |
| 0 | 500 #ifndef PRODUCT |
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501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 502 Compile* C = ra_->C; |
| 503 | |
| 504 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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506 // Remove wordSize for return addr which is already pushed. |
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507 framesize -= wordSize; |
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508 |
| 0 | 509 if (C->need_stack_bang(framesize)) { |
| 510 framesize -= wordSize; | |
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511 st->print("# stack bang"); |
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512 st->print("\n\t"); |
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513 st->print("PUSH EBP\t# Save EBP"); |
| 0 | 514 if (framesize) { |
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515 st->print("\n\t"); |
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516 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 517 } |
| 518 } else { | |
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519 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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520 st->print("\n\t"); |
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521 framesize -= wordSize; |
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522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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523 } |
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524 |
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525 if (VerifyStackAtCalls) { |
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526 st->print("\n\t"); |
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527 framesize -= wordSize; |
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528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 529 } |
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530 |
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531 if( C->in_24_bit_fp_mode() ) { |
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532 st->print("\n\t"); |
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533 st->print("FLDCW \t# load 24 bit fpu control word"); |
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534 } |
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535 if (UseSSE >= 2 && VerifyFPU) { |
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536 st->print("\n\t"); |
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537 st->print("# verify FPU stack (must be clean on entry)"); |
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538 } |
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539 |
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540 #ifdef ASSERT |
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541 if (VerifyStackAtCalls) { |
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542 st->print("\n\t"); |
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543 st->print("# stack alignment check"); |
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544 } |
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545 #endif |
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546 st->cr(); |
| 0 | 547 } |
| 548 #endif | |
| 549 | |
| 550 | |
| 551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 552 Compile* C = ra_->C; | |
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553 MacroAssembler _masm(&cbuf); |
| 0 | 554 |
| 555 int framesize = C->frame_slots() << LogBytesPerInt; | |
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556 |
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557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode()); |
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558 |
| 1748 | 559 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 560 |
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561 if (C->has_mach_constant_base_node()) { |
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562 // NOTE: We set the table base offset here because users might be |
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563 // emitted before MachConstantBaseNode. |
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564 Compile::ConstantTable& constant_table = C->constant_table(); |
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565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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566 } |
| 0 | 567 } |
| 568 | |
| 569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 570 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 571 } | |
| 572 | |
| 573 int MachPrologNode::reloc() const { | |
| 574 return 0; // a large enough number | |
| 575 } | |
| 576 | |
| 577 //============================================================================= | |
| 578 #ifndef PRODUCT | |
| 579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 580 Compile *C = ra_->C; | |
| 581 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 583 // Remove two words for return addr and rbp, | |
| 584 framesize -= 2*wordSize; | |
| 585 | |
| 586 if( C->in_24_bit_fp_mode() ) { | |
| 587 st->print("FLDCW standard control word"); | |
| 588 st->cr(); st->print("\t"); | |
| 589 } | |
| 590 if( framesize ) { | |
| 591 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 592 st->cr(); st->print("\t"); | |
| 593 } | |
| 594 st->print_cr("POPL EBP"); st->print("\t"); | |
| 595 if( do_polling() && C->is_method_compilation() ) { | |
| 596 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 597 st->cr(); st->print("\t"); | |
| 598 } | |
| 599 } | |
| 600 #endif | |
| 601 | |
| 602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 603 Compile *C = ra_->C; | |
| 604 | |
| 605 // If method set FPU control word, restore to standard control word | |
| 606 if( C->in_24_bit_fp_mode() ) { | |
| 607 MacroAssembler masm(&cbuf); | |
| 608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 609 } | |
| 610 | |
| 611 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 613 // Remove two words for return addr and rbp, | |
| 614 framesize -= 2*wordSize; | |
| 615 | |
| 616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 617 | |
| 618 if( framesize >= 128 ) { | |
| 619 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 620 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 621 emit_d32(cbuf, framesize); | |
| 622 } | |
| 623 else if( framesize ) { | |
| 624 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 625 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 626 emit_d8(cbuf, framesize); | |
| 627 } | |
| 628 | |
| 629 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 630 | |
| 631 if( do_polling() && C->is_method_compilation() ) { | |
| 1748 | 632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 633 emit_opcode(cbuf,0x85); |
| 634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 635 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 636 } | |
| 637 } | |
| 638 | |
| 639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 640 Compile *C = ra_->C; | |
| 641 // If method set FPU control word, restore to standard control word | |
| 642 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 643 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 644 | |
| 645 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 647 // Remove two words for return addr and rbp, | |
| 648 framesize -= 2*wordSize; | |
| 649 | |
| 650 size++; // popl rbp, | |
| 651 | |
| 652 if( framesize >= 128 ) { | |
| 653 size += 6; | |
| 654 } else { | |
| 655 size += framesize ? 3 : 0; | |
| 656 } | |
| 657 return size; | |
| 658 } | |
| 659 | |
| 660 int MachEpilogNode::reloc() const { | |
| 661 return 0; // a large enough number | |
| 662 } | |
| 663 | |
| 664 const Pipeline * MachEpilogNode::pipeline() const { | |
| 665 return MachNode::pipeline_class(); | |
| 666 } | |
| 667 | |
| 668 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 669 | |
| 670 //============================================================================= | |
| 671 | |
| 672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 673 static enum RC rc_class( OptoReg::Name reg ) { | |
| 674 | |
| 675 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 676 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 677 | |
| 678 VMReg r = OptoReg::as_VMReg(reg); | |
| 679 if (r->is_Register()) return rc_int; | |
| 680 if (r->is_FloatRegister()) { | |
| 681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 682 return rc_float; | |
| 683 } | |
| 684 assert(r->is_XMMRegister(), "must be"); | |
| 685 return rc_xmm; | |
| 686 } | |
| 687 | |
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688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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689 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 690 if( cbuf ) { |
| 691 emit_opcode (*cbuf, opcode ); | |
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692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 693 #ifndef PRODUCT |
| 694 } else if( !do_size ) { | |
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695 if( size != 0 ) st->print("\n\t"); |
| 0 | 696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
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697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 699 } else { // FLD, FST, PUSH, POP |
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700 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 701 } |
| 702 #endif | |
| 703 } | |
| 704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 705 return size+3+offset_size; | |
| 706 } | |
| 707 | |
| 708 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
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710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 711 if (cbuf) { |
| 712 MacroAssembler _masm(cbuf); | |
| 713 if (reg_lo+1 == reg_hi) { // double move? | |
| 714 if (is_load) { | |
| 715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 716 } else { | |
| 717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 718 } | |
| 0 | 719 } else { |
| 4759 | 720 if (is_load) { |
| 721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 722 } else { | |
| 723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 724 } | |
| 0 | 725 } |
| 726 #ifndef PRODUCT | |
| 4759 | 727 } else if (!do_size) { |
| 728 if (size != 0) st->print("\n\t"); | |
| 729 if (reg_lo+1 == reg_hi) { // double move? | |
| 730 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 732 Matcher::regName[reg_lo], offset); | |
| 733 else st->print("MOVSD [ESP + #%d],%s", | |
| 734 offset, Matcher::regName[reg_lo]); | |
| 0 | 735 } else { |
| 4759 | 736 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 737 Matcher::regName[reg_lo], offset); | |
| 738 else st->print("MOVSS [ESP + #%d],%s", | |
| 739 offset, Matcher::regName[reg_lo]); | |
| 0 | 740 } |
| 741 #endif | |
| 742 } | |
| 743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
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744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 745 return size+5+offset_size; |
| 746 } | |
| 747 | |
| 748 | |
| 749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
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750 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 751 if (cbuf) { |
| 752 MacroAssembler _masm(cbuf); | |
| 753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 755 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 756 } else { | |
| 757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 758 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 759 } | |
| 0 | 760 #ifndef PRODUCT |
| 4759 | 761 } else if (!do_size) { |
| 762 if (size != 0) st->print("\n\t"); | |
| 763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
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765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 766 } else { |
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767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 768 } |
| 4759 | 769 } else { |
| 0 | 770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 772 } else { |
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773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 774 } |
| 4759 | 775 } |
| 0 | 776 #endif |
| 777 } | |
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778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 779 // Only MOVAPS SSE prefix uses 1 byte. |
| 780 int sz = 4; | |
| 781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 783 return size + sz; | |
| 0 | 784 } |
| 785 | |
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786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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787 int src_hi, int dst_hi, int size, outputStream* st ) { |
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788 // 32-bit |
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789 if (cbuf) { |
| 4759 | 790 MacroAssembler _masm(cbuf); |
| 791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 792 as_Register(Matcher::_regEncode[src_lo])); | |
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793 #ifndef PRODUCT |
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794 } else if (!do_size) { |
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795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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796 #endif |
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797 } |
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798 return 4; |
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799 } |
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800 |
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801 |
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802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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803 int src_hi, int dst_hi, int size, outputStream* st ) { |
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804 // 32-bit |
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805 if (cbuf) { |
| 4759 | 806 MacroAssembler _masm(cbuf); |
| 807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 808 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
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809 #ifndef PRODUCT |
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810 } else if (!do_size) { |
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811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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812 #endif |
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813 } |
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814 return 4; |
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815 } |
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816 |
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817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 818 if( cbuf ) { |
| 819 emit_opcode(*cbuf, 0x8B ); | |
| 820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 821 #ifndef PRODUCT | |
| 822 } else if( !do_size ) { | |
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823 if( size != 0 ) st->print("\n\t"); |
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824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 825 #endif |
| 826 } | |
| 827 return size+2; | |
| 828 } | |
| 829 | |
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830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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831 int offset, int size, outputStream* st ) { |
| 0 | 832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 833 if( cbuf ) { | |
| 834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 836 #ifndef PRODUCT | |
| 837 } else if( !do_size ) { | |
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838 if( size != 0 ) st->print("\n\t"); |
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839 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 840 #endif |
| 841 } | |
| 842 size += 2; | |
| 843 } | |
| 844 | |
| 845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 846 const char *op_str; | |
| 847 int op; | |
| 848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 850 op = 0xDD; | |
| 851 } else { // 32-bit store | |
| 852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 853 op = 0xD9; | |
| 854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 855 } | |
| 856 | |
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857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 858 } |
| 859 | |
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860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
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861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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862 int src_hi, int dst_hi, uint ireg, outputStream* st); |
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863 |
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864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
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865 int stack_offset, int reg, uint ireg, outputStream* st); |
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866 |
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867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
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868 int dst_offset, uint ireg, outputStream* st) { |
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|
869 int calc_size = 0; |
|
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|
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
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|
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
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|
872 switch (ireg) { |
|
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|
873 case Op_VecS: |
|
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|
874 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
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|
875 break; |
|
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|
876 case Op_VecD: |
|
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|
877 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
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|
878 src_offset += 4; |
|
8c92982cbbc4
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|
879 dst_offset += 4; |
|
8c92982cbbc4
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|
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
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881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
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|
882 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
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|
883 break; |
|
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|
884 case Op_VecX: |
|
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|
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
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|
886 break; |
|
8c92982cbbc4
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|
887 case Op_VecY: |
|
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|
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
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|
889 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
890 default: |
|
8c92982cbbc4
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|
891 ShouldNotReachHere(); |
|
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|
892 } |
|
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|
893 if (cbuf) { |
|
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|
894 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
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|
895 int offset = __ offset(); |
|
8c92982cbbc4
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|
896 switch (ireg) { |
|
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|
897 case Op_VecS: |
|
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|
898 __ pushl(Address(rsp, src_offset)); |
|
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|
899 __ popl (Address(rsp, dst_offset)); |
|
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|
900 break; |
|
8c92982cbbc4
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kvn
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|
901 case Op_VecD: |
|
8c92982cbbc4
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|
902 __ pushl(Address(rsp, src_offset)); |
|
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|
903 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
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|
904 __ pushl(Address(rsp, src_offset+4)); |
|
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|
905 __ popl (Address(rsp, dst_offset+4)); |
|
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parents:
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|
906 break; |
|
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parents:
6143
diff
changeset
|
907 case Op_VecX: |
|
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|
908 __ movdqu(Address(rsp, -16), xmm0); |
|
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|
909 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
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|
910 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
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|
911 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
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diff
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|
912 break; |
|
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diff
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|
913 case Op_VecY: |
|
8c92982cbbc4
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|
914 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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|
915 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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|
916 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
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|
917 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
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kvn
parents:
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|
918 break; |
|
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diff
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|
919 default: |
|
8c92982cbbc4
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|
920 ShouldNotReachHere(); |
|
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|
921 } |
|
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|
922 int size = __ offset() - offset; |
|
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|
923 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
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|
924 return size; |
|
8c92982cbbc4
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|
925 #ifndef PRODUCT |
|
8c92982cbbc4
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|
926 } else if (!do_size) { |
|
8c92982cbbc4
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|
927 switch (ireg) { |
|
8c92982cbbc4
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parents:
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|
928 case Op_VecS: |
|
8c92982cbbc4
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kvn
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|
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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|
930 "popl [rsp + #%d]", |
|
8c92982cbbc4
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|
931 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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diff
changeset
|
932 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
933 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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|
935 "popq [rsp + #%d]\n\t" |
|
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|
936 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
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|
937 "popq [rsp + #%d]", |
|
8c92982cbbc4
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|
938 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
939 break; |
|
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
940 case Op_VecX: |
|
8c92982cbbc4
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|
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
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|
942 "movdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
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|
943 "movdqu [rsp + #%d], xmm0\n\t" |
|
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|
944 "movdqu xmm0, [rsp - #16]", |
|
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|
945 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
946 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
947 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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changeset
|
949 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
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kvn
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|
950 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
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kvn
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|
951 "vmovdqu xmm0, [rsp - #32]", |
|
8c92982cbbc4
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kvn
parents:
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|
952 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
953 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
954 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
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changeset
|
955 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
956 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
957 #endif |
|
8c92982cbbc4
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|
958 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
959 return calc_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
960 } |
|
8c92982cbbc4
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|
961 |
| 0 | 962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 963 // Get registers to move | |
| 964 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 965 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 966 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 967 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 968 | |
| 969 enum RC src_second_rc = rc_class(src_second); | |
| 970 enum RC src_first_rc = rc_class(src_first); | |
| 971 enum RC dst_second_rc = rc_class(dst_second); | |
| 972 enum RC dst_first_rc = rc_class(dst_first); | |
| 973 | |
| 974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 975 | |
| 976 // Generate spill code! | |
| 977 int size = 0; | |
| 978 | |
| 979 if( src_first == dst_first && src_second == dst_second ) | |
| 980 return size; // Self copy, no move | |
| 981 | |
|
6179
8c92982cbbc4
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982 if (bottom_type()->isa_vect() != NULL) { |
|
8c92982cbbc4
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|
983 uint ireg = ideal_reg(); |
|
8c92982cbbc4
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|
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
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|
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
|
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|
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
8c92982cbbc4
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987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
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|
988 // mem -> mem |
|
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989 int src_offset = ra_->reg2offset(src_first); |
|
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|
990 int dst_offset = ra_->reg2offset(dst_first); |
|
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991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
|
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992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
|
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|
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
|
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|
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
|
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|
995 int stack_offset = ra_->reg2offset(dst_first); |
|
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|
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
|
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|
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
|
8c92982cbbc4
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|
998 int stack_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
|
8c92982cbbc4
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|
1000 } else { |
|
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1001 ShouldNotReachHere(); |
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1002 } |
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1003 } |
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1004 |
| 0 | 1005 // -------------------------------------- |
| 1006 // Check for mem-mem move. push/pop to move. | |
| 1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1008 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
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1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1013 } | |
| 1014 // move low bits | |
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1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
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1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1020 } |
| 1021 return size; | |
| 1022 } | |
| 1023 | |
| 1024 // -------------------------------------- | |
| 1025 // Check for integer reg-reg copy | |
| 1026 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
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1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1028 |
| 1029 // Check for integer store | |
| 1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
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1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1032 |
| 1033 // Check for integer load | |
| 1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
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1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1036 |
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1037 // Check for integer reg-xmm reg copy |
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1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1040 "no 64 bit integer-float reg moves" ); |
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1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1042 } |
| 0 | 1043 // -------------------------------------- |
| 1044 // Check for float reg-reg copy | |
| 1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1048 if( cbuf ) { | |
| 1049 | |
| 1050 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1051 // indexing issue mentioned in a comment in the reg_def sections | |
| 1052 // for FPR registers many lines above here. | |
| 1053 | |
| 1054 if( src_first != FPR1L_num ) { | |
| 1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1059 } else { | |
| 1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1062 } | |
| 1063 #ifndef PRODUCT | |
| 1064 } else if( !do_size ) { | |
| 1065 if( size != 0 ) st->print("\n\t"); | |
| 1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1067 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1068 #endif | |
| 1069 } | |
| 1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1071 } | |
| 1072 | |
| 1073 // Check for float store | |
| 1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
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1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1076 } |
| 1077 | |
| 1078 // Check for float load | |
| 1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1080 int offset = ra_->reg2offset(src_first); | |
| 1081 const char *op_str; | |
| 1082 int op; | |
| 1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1084 op_str = "FLD_D"; | |
| 1085 op = 0xDD; | |
| 1086 } else { // 32-bit load | |
| 1087 op_str = "FLD_S"; | |
| 1088 op = 0xD9; | |
| 1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1090 } | |
| 1091 if( cbuf ) { | |
| 1092 emit_opcode (*cbuf, op ); | |
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1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1096 #ifndef PRODUCT | |
| 1097 } else if( !do_size ) { | |
| 1098 if( size != 0 ) st->print("\n\t"); | |
| 1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1100 #endif | |
| 1101 } | |
| 1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1103 return size + 3+offset_size+2; | |
| 1104 } | |
| 1105 | |
| 1106 // Check for xmm reg-reg copy | |
| 1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1109 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1110 "no non-adjacent float-moves" ); | |
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1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1112 } |
| 1113 | |
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1114 // Check for xmm reg-integer reg copy |
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1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1117 "no 64 bit float-integer reg moves" ); |
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1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1119 } |
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1120 |
| 0 | 1121 // Check for xmm store |
| 1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
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1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1124 } |
| 1125 | |
| 1126 // Check for float xmm load | |
| 1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1129 } |
| 1130 | |
| 1131 // Copy from float reg to xmm reg | |
| 1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1133 // copy to the top of stack from floating point reg | |
| 1134 // and use LEA to preserve flags | |
| 1135 if( cbuf ) { | |
| 1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1139 emit_d8(*cbuf,0xF8); | |
| 1140 #ifndef PRODUCT | |
| 1141 } else if( !do_size ) { | |
| 1142 if( size != 0 ) st->print("\n\t"); | |
| 1143 st->print("LEA ESP,[ESP-8]"); | |
| 1144 #endif | |
| 1145 } | |
| 1146 size += 4; | |
| 1147 | |
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1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1149 |
| 1150 // Copy from the temp memory to the xmm reg. | |
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1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1152 |
| 1153 if( cbuf ) { | |
| 1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1157 emit_d8(*cbuf,0x08); | |
| 1158 #ifndef PRODUCT | |
| 1159 } else if( !do_size ) { | |
| 1160 if( size != 0 ) st->print("\n\t"); | |
| 1161 st->print("LEA ESP,[ESP+8]"); | |
| 1162 #endif | |
| 1163 } | |
| 1164 size += 4; | |
| 1165 return size; | |
| 1166 } | |
| 1167 | |
| 1168 assert( size > 0, "missed a case" ); | |
| 1169 | |
| 1170 // -------------------------------------------------------------------- | |
| 1171 // Check for second bits still needing moving. | |
| 1172 if( src_second == dst_second ) | |
| 1173 return size; // Self copy; no move | |
| 1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1175 | |
| 1176 // Check for second word int-int move | |
| 1177 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1179 |
| 1180 // Check for second word integer store | |
| 1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1183 |
| 1184 // Check for second word integer load | |
| 1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1187 |
| 1188 | |
| 1189 Unimplemented(); | |
| 1190 } | |
| 1191 | |
| 1192 #ifndef PRODUCT | |
| 4950 | 1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1194 implementation( NULL, ra_, false, st ); |
| 1195 } | |
| 1196 #endif | |
| 1197 | |
| 1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1199 implementation( &cbuf, ra_, false, NULL ); | |
| 1200 } | |
| 1201 | |
| 1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1203 return implementation( NULL, ra_, true, NULL ); | |
| 1204 } | |
| 1205 | |
| 1206 | |
| 1207 //============================================================================= | |
| 1208 #ifndef PRODUCT | |
| 1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1211 int reg = ra_->get_reg_first(this); | |
| 1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1213 } | |
| 1214 #endif | |
| 1215 | |
| 1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1218 int reg = ra_->get_encode(this); | |
| 1219 if( offset >= 128 ) { | |
| 1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1221 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1223 emit_d32(cbuf, offset); | |
| 1224 } | |
| 1225 else { | |
| 1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1227 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1229 emit_d8(cbuf, offset); | |
| 1230 } | |
| 1231 } | |
| 1232 | |
| 1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1235 if( offset >= 128 ) { | |
| 1236 return 7; | |
| 1237 } | |
| 1238 else { | |
| 1239 return 4; | |
| 1240 } | |
| 1241 } | |
| 1242 | |
| 1243 //============================================================================= | |
| 1244 | |
| 1245 // emit call stub, compiled java to interpreter | |
| 1246 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1247 // Stub is fixed up when the corresponding call is converted from calling | |
| 1248 // compiled code to calling interpreted code. | |
| 1249 // mov rbx,0 | |
| 1250 // jmp -1 | |
| 1251 | |
| 1748 | 1252 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1253 | |
| 1254 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1255 // That's why we must use the macroassembler to generate a stub. |
| 1256 MacroAssembler _masm(&cbuf); | |
| 1257 | |
| 1258 address base = | |
| 1259 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1260 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1261 // static stub relocation stores the instruction address of the call | |
| 1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
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1263 // static stub relocation also tags the Method* in the code-stream. |
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1264 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time |
| 304 | 1265 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1266 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1267 |
| 1268 __ end_a_stub(); | |
| 1748 | 1269 // Update current stubs pointer and restore insts_end. |
| 0 | 1270 } |
| 1271 // size of call stub, compiled java to interpretor | |
| 1272 uint size_java_to_interp() { | |
| 1273 return 10; // movl; jmp | |
| 1274 } | |
| 1275 // relocation entries for call stub, compiled java to interpretor | |
| 1276 uint reloc_java_to_interp() { | |
| 1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1278 } | |
| 1279 | |
| 1280 //============================================================================= | |
| 1281 #ifndef PRODUCT | |
| 1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1285 st->print_cr("\tNOP"); | |
| 1286 st->print_cr("\tNOP"); | |
| 1287 if( !OptoBreakpoint ) | |
| 1288 st->print_cr("\tNOP"); | |
| 1289 } | |
| 1290 #endif | |
| 1291 | |
| 1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1293 MacroAssembler masm(&cbuf); | |
| 1294 #ifdef ASSERT | |
| 1748 | 1295 uint insts_size = cbuf.insts_size(); |
| 0 | 1296 #endif |
| 304 | 1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1298 masm.jump_cc(Assembler::notEqual, |
| 1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1300 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1301 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1302 int nops_cnt = 2; | |
| 1303 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1304 nops_cnt += 1; | |
| 1305 masm.nop(nops_cnt); | |
| 1306 | |
| 1748 | 1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1308 } |
| 1309 | |
| 1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1311 return OptoBreakpoint ? 11 : 12; | |
| 1312 } | |
| 1313 | |
| 1314 | |
| 1315 //============================================================================= | |
| 1316 uint size_exception_handler() { | |
| 1317 // NativeCall instruction size is the same as NativeJump. | |
| 1318 // exception handler starts out as jump and can be patched to | |
| 1319 // a call be deoptimization. (4932387) | |
| 1320 // Note that this value is also credited (in output.cpp) to | |
| 1321 // the size of the code section. | |
| 1322 return NativeJump::instruction_size; | |
| 1323 } | |
| 1324 | |
| 1325 // Emit exception handler code. Stuff framesize into a register | |
| 1326 // and call a VM stub routine. | |
| 1327 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1328 | |
| 1748 | 1329 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1330 // That's why we must use the macroassembler to generate a handler. |
| 1331 MacroAssembler _masm(&cbuf); | |
| 1332 address base = | |
| 1333 __ start_a_stub(size_exception_handler()); | |
| 1334 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1335 int offset = __ offset(); | |
| 1748 | 1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1338 __ end_a_stub(); | |
| 1339 return offset; | |
| 1340 } | |
| 1341 | |
| 1342 uint size_deopt_handler() { | |
| 1343 // NativeCall instruction size is the same as NativeJump. | |
| 1344 // exception handler starts out as jump and can be patched to | |
| 1345 // a call be deoptimization. (4932387) | |
| 1346 // Note that this value is also credited (in output.cpp) to | |
| 1347 // the size of the code section. | |
| 1348 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1349 } | |
| 1350 | |
| 1351 // Emit deopt handler code. | |
| 1352 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1353 | |
| 1748 | 1354 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1355 // That's why we must use the macroassembler to generate a handler. |
| 1356 MacroAssembler _masm(&cbuf); | |
| 1357 address base = | |
| 1358 __ start_a_stub(size_exception_handler()); | |
| 1359 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1360 int offset = __ offset(); | |
| 1361 InternalAddress here(__ pc()); | |
| 1362 __ pushptr(here.addr()); | |
| 1363 | |
| 1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1366 __ end_a_stub(); | |
| 1367 return offset; | |
| 1368 } | |
| 1369 | |
| 1370 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1371 return regnum - 32; // The FP registers are in the second chunk | |
| 1372 } | |
| 1373 | |
| 1374 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1375 const bool Matcher::convL2FSupported(void) { | |
| 1376 return true; | |
| 1377 } | |
| 1378 | |
| 1379 // Is this branch offset short enough that a short branch can be used? | |
| 1380 // | |
| 1381 // NOTE: If the platform does not provide any short branch variants, then | |
| 1382 // this method should return false for offset 0. | |
| 3851 | 1383 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1384 // The passed offset is relative to address of the branch. | |
| 1385 // On 86 a branch displacement is calculated relative to address | |
| 1386 // of a next instruction. | |
| 1387 offset -= br_size; | |
| 1388 | |
|
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|
1389 // the short version of jmpConUCF2 contains multiple branches, |
|
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|
1390 // making the reach slightly less |
|
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|
1391 if (rule == jmpConUCF2_rule) |
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|
1392 return (-126 <= offset && offset <= 125); |
| 0 | 1393 return (-128 <= offset && offset <= 127); |
| 1394 } | |
| 1395 | |
| 1396 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1397 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1398 return false; | |
| 1399 } | |
| 1400 | |
| 1401 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1402 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1403 | |
| 1404 // Threshold size for cleararray. | |
| 1405 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1406 | |
| 4047 | 1407 // Needs 2 CMOV's for longs. |
| 1408 const int Matcher::long_cmove_cost() { return 1; } | |
| 1409 | |
| 1410 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1411 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1412 | |
| 0 | 1413 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1414 // be subsumed into complex addressing expressions or compute them into | |
| 1415 // registers? True for Intel but false for most RISCs | |
| 1416 const bool Matcher::clone_shift_expressions = true; | |
| 1417 | |
|
2401
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|
1418 // Do we need to mask the count passed to shift instructions or does |
|
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|
1419 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1420 const bool Matcher::need_masked_shift_count = false; |
|
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|
1421 |
|
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|
1422 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1423 ShouldNotCallThis(); |
|
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|
1424 return true; |
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|
1425 } |
|
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|
1426 |
|
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|
1427 bool Matcher::narrow_klass_use_complex_address() { |
|
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|
1428 ShouldNotCallThis(); |
|
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|
1429 return true; |
|
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|
1430 } |
|
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|
1431 |
|
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|
1432 |
| 0 | 1433 // Is it better to copy float constants, or load them directly from memory? |
| 1434 // Intel can load a float constant from a direct address, requiring no | |
| 1435 // extra registers. Most RISCs will have to materialize an address into a | |
| 1436 // register first, so they would do better to copy the constant from stack. | |
| 1437 const bool Matcher::rematerialize_float_constants = true; | |
| 1438 | |
| 1439 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1440 // needed. Else we split the double into 2 integer pieces and move it | |
| 1441 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1442 // Java calling convention forces doubles to be aligned. | |
| 1443 const bool Matcher::misaligned_doubles_ok = true; | |
| 1444 | |
| 1445 | |
| 1446 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1447 // Get the memory operand from the node | |
| 1448 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1449 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1450 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1451 uint opcnt = 1; // First operand | |
| 1452 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1453 while( idx >= skipped+num_edges ) { | |
| 1454 skipped += num_edges; | |
| 1455 opcnt++; // Bump operand count | |
| 1456 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1457 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1458 } | |
| 1459 | |
| 1460 MachOper *memory = node->_opnds[opcnt]; | |
| 1461 MachOper *new_memory = NULL; | |
| 1462 switch (memory->opcode()) { | |
| 1463 case DIRECT: | |
| 1464 case INDOFFSET32X: | |
| 1465 // No transformation necessary. | |
| 1466 return; | |
| 1467 case INDIRECT: | |
| 1468 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1469 break; | |
| 1470 case INDOFFSET8: | |
| 1471 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1472 break; | |
| 1473 case INDOFFSET32: | |
| 1474 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1475 break; | |
| 1476 case INDINDEXOFFSET: | |
| 1477 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1478 break; | |
| 1479 case INDINDEXSCALE: | |
| 1480 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1481 break; | |
| 1482 case INDINDEXSCALEOFFSET: | |
| 1483 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1484 break; | |
| 1485 case LOAD_LONG_INDIRECT: | |
| 1486 case LOAD_LONG_INDOFFSET32: | |
| 1487 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1488 return; | |
| 1489 default: | |
| 1490 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1491 return; | |
| 1492 } | |
| 1493 node->_opnds[opcnt] = new_memory; | |
| 1494 } | |
| 1495 | |
| 1496 // Advertise here if the CPU requires explicit rounding operations | |
| 1497 // to implement the UseStrictFP mode. | |
| 1498 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1499 | |
|
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|
1500 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1501 // On x32 it is stored with convertion only when FPU is used for floats. |
|
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|
1502 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
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|
1503 |
| 0 | 1504 // Do ints take an entire long register or just half? |
| 1505 const bool Matcher::int_in_long = false; | |
| 1506 | |
| 1507 // Return whether or not this register is ever used as an argument. This | |
| 1508 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1509 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1510 // arguments in those registers not be available to the callee. | |
| 1511 bool Matcher::can_be_java_arg( int reg ) { | |
| 1512 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
6179
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|
1513 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1514 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1515 return false; | |
| 1516 } | |
| 1517 | |
| 1518 bool Matcher::is_spillable_arg( int reg ) { | |
| 1519 return can_be_java_arg(reg); | |
| 1520 } | |
| 1521 | |
|
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|
1522 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
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|
1523 // Use hardware integer DIV instruction when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1524 // it is faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1525 // Only when constant divisor fits into 32 bit |
|
ae065c367d93
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|
1526 // (min_jint is excluded to get only correct |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1527 // positive 32 bit values from negative). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1528 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1529 (divisor == (int)divisor && divisor != min_jint); |
|
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|
1530 } |
|
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|
1531 |
| 0 | 1532 // Register for DIVI projection of divmodI |
| 1533 RegMask Matcher::divI_proj_mask() { | |
|
4121
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|
1534 return EAX_REG_mask(); |
| 0 | 1535 } |
| 1536 | |
| 1537 // Register for MODI projection of divmodI | |
| 1538 RegMask Matcher::modI_proj_mask() { | |
|
4121
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|
1539 return EDX_REG_mask(); |
| 0 | 1540 } |
| 1541 | |
| 1542 // Register for DIVL projection of divmodL | |
| 1543 RegMask Matcher::divL_proj_mask() { | |
| 1544 ShouldNotReachHere(); | |
| 1545 return RegMask(); | |
| 1546 } | |
| 1547 | |
| 1548 // Register for MODL projection of divmodL | |
| 1549 RegMask Matcher::modL_proj_mask() { | |
| 1550 ShouldNotReachHere(); | |
| 1551 return RegMask(); | |
| 1552 } | |
| 1553 | |
|
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|
1554 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
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|
1555 return EBP_REG_mask(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
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|
1556 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
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|
1557 |
|
1209
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|
1558 // Returns true if the high 32 bits of the value is known to be zero. |
|
e8443c7be117
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|
1559 bool is_operand_hi32_zero(Node* n) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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|
1560 int opc = n->Opcode(); |
|
e8443c7be117
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|
1561 if (opc == Op_AndL) { |
|
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|
1562 Node* o2 = n->in(2); |
|
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|
1563 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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|
1564 return true; |
|
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|
1565 } |
|
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|
1566 } |
|
1914
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|
1567 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
ae065c367d93
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|
1568 return true; |
|
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|
1569 } |
|
1209
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|
1570 return false; |
|
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|
1571 } |
|
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|
1572 |
| 0 | 1573 %} |
| 1574 | |
| 1575 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1576 // This block specifies the encoding classes used by the compiler to output | |
| 1577 // byte streams. Encoding classes generate functions which are called by | |
| 1578 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1579 // instruction. Operands specify their base encoding interface with the | |
| 1580 // interface keyword. There are currently supported four interfaces, | |
| 1581 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1582 // operand to generate a function which returns its register number when | |
| 1583 // queried. CONST_INTER causes an operand to generate a function which | |
| 1584 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1585 // operand to generate four functions which return the Base Register, the | |
| 1586 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1587 // queried. COND_INTER causes an operand to generate six functions which | |
| 1588 // return the encoding code (ie - encoding bits for the instruction) | |
| 1589 // associated with each basic boolean condition for a conditional instruction. | |
| 1590 // Instructions specify two basic values for encoding. They use the | |
| 1591 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1592 // the class names specified in the encoding block), and they use the | |
| 1593 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1594 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1595 // needs for encoding need to be specified. | |
| 1596 encode %{ | |
| 1597 // Build emit functions for each basic byte or larger field in the intel | |
| 1598 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1599 // code in the enc_class source block. Emit functions will live in the | |
| 1600 // main source block for now. In future, we can generalize this by | |
| 1601 // adding a syntax that specifies the sizes of fields in an order, | |
| 1602 // so that the adlc can build the emit functions automagically | |
|
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|
1603 |
|
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|
1604 // Emit primary opcode |
|
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diff
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|
1605 enc_class OpcP %{ |
|
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diff
changeset
|
1606 emit_opcode(cbuf, $primary); |
|
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|
1607 %} |
|
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diff
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|
1608 |
|
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|
1609 // Emit secondary opcode |
|
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diff
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|
1610 enc_class OpcS %{ |
|
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diff
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|
1611 emit_opcode(cbuf, $secondary); |
|
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1612 %} |
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1613 |
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1614 // Emit opcode directly |
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1615 enc_class Opcode(immI d8) %{ |
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1616 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1617 %} |
| 1618 | |
| 1619 enc_class SizePrefix %{ | |
| 1620 emit_opcode(cbuf,0x66); | |
| 1621 %} | |
| 1622 | |
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1623 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1624 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1625 %} | |
| 1626 | |
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1627 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1628 emit_opcode(cbuf,$opcode$$constant); |
| 1629 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1630 %} | |
| 1631 | |
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1632 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1633 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1634 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1635 %} | |
| 1636 | |
| 1637 enc_class cdq_enc %{ | |
| 1638 // Full implementation of Java idiv and irem; checks for | |
| 1639 // special case as described in JVM spec., p.243 & p.271. | |
| 1640 // | |
| 1641 // normal case special case | |
| 1642 // | |
| 1643 // input : rax,: dividend min_int | |
| 1644 // reg: divisor -1 | |
| 1645 // | |
| 1646 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1647 // rdx: remainder (= rax, irem reg) 0 | |
| 1648 // | |
| 1649 // Code sequnce: | |
| 1650 // | |
| 1651 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1652 // 0F 85 0B 00 00 00 jne normal_case | |
| 1653 // 33 D2 xor rdx,edx | |
| 1654 // 83 F9 FF cmp rcx,0FFh | |
| 1655 // 0F 84 03 00 00 00 je done | |
| 1656 // normal_case: | |
| 1657 // 99 cdq | |
| 1658 // F7 F9 idiv rax,ecx | |
| 1659 // done: | |
| 1660 // | |
| 1661 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1662 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1664 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1665 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1667 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1668 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1669 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1670 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1671 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1672 // normal_case: | |
| 1673 emit_opcode(cbuf,0x99); // cdq | |
| 1674 // idiv (note: must be emitted by the user of this rule) | |
| 1675 // normal: | |
| 1676 %} | |
| 1677 | |
| 1678 // Dense encoding for older common ops | |
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1679 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1680 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1681 %} | |
| 1682 | |
| 1683 | |
| 1684 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1685 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1686 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1687 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1688 emit_opcode(cbuf, $primary | 0x02); | |
| 1689 } | |
| 1690 else { // If 32-bit immediate | |
| 1691 emit_opcode(cbuf, $primary); | |
| 1692 } | |
| 1693 %} | |
| 1694 | |
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1695 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1696 // Emit primary opcode and set sign-extend bit |
| 1697 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1699 emit_opcode(cbuf, $primary | 0x02); } | |
| 1700 else { // If 32-bit immediate | |
| 1701 emit_opcode(cbuf, $primary); | |
| 1702 } | |
| 1703 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1704 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1705 %} | |
| 1706 | |
| 1707 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1708 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1710 $$$emit8$imm$$constant; | |
| 1711 } | |
| 1712 else { // If 32-bit immediate | |
| 1713 // Output immediate | |
| 1714 $$$emit32$imm$$constant; | |
| 1715 } | |
| 1716 %} | |
| 1717 | |
| 1718 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1719 // Emit primary opcode and set sign-extend bit | |
| 1720 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1721 int con = (int)$imm$$constant; // Throw away top bits | |
| 1722 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1723 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1724 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1725 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1726 else emit_d32(cbuf,con); | |
| 1727 %} | |
| 1728 | |
| 1729 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1730 // Emit primary opcode and set sign-extend bit | |
| 1731 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1732 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1734 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1735 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1737 else emit_d32(cbuf,con); | |
| 1738 %} | |
| 1739 | |
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1740 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1741 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1742 %} | |
| 1743 | |
| 1744 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1745 int destlo = $dst$$reg; | |
| 1746 int desthi = HIGH_FROM_LOW(destlo); | |
| 1747 // bswap lo | |
| 1748 emit_opcode(cbuf, 0x0F); | |
| 1749 emit_cc(cbuf, 0xC8, destlo); | |
| 1750 // bswap hi | |
| 1751 emit_opcode(cbuf, 0x0F); | |
| 1752 emit_cc(cbuf, 0xC8, desthi); | |
| 1753 // xchg lo and hi | |
| 1754 emit_opcode(cbuf, 0x87); | |
| 1755 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1756 %} | |
| 1757 | |
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1758 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1759 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1760 %} | |
| 1761 | |
| 1762 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1763 $$$emit8$primary; | |
| 1764 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1765 %} | |
| 1766 | |
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1767 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1768 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1769 emit_d8(cbuf, op >> 8 ); | |
| 1770 emit_d8(cbuf, op & 255); | |
| 1771 %} | |
| 1772 | |
| 1773 // emulate a CMOV with a conditional branch around a MOV | |
| 1774 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1775 // Invert sense of branch from sense of CMOV | |
| 1776 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1777 emit_d8( cbuf, $brOffs$$constant ); | |
| 1778 %} | |
| 1779 | |
| 1780 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1781 Register Redi = as_Register(EDI_enc); // result register | |
| 1782 Register Reax = as_Register(EAX_enc); // super class | |
| 1783 Register Recx = as_Register(ECX_enc); // killed | |
| 1784 Register Resi = as_Register(ESI_enc); // sub class | |
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1785 Label miss; |
| 0 | 1786 |
| 1787 MacroAssembler _masm(&cbuf); | |
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1788 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1789 NULL, &miss, |
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1790 /*set_cond_codes:*/ true); |
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1791 if ($primary) { |
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1792 __ xorptr(Redi, Redi); |
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1793 } |
| 0 | 1794 __ bind(miss); |
| 1795 %} | |
| 1796 | |
| 1797 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1798 MacroAssembler masm(&cbuf); | |
| 1799 int start = masm.offset(); | |
| 1800 if (UseSSE >= 2) { | |
| 1801 if (VerifyFPU) { | |
| 1802 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1803 } | |
| 1804 } else { | |
| 1805 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1806 // Compiled code leaves it dirty. Do cleanup now. | |
| 1807 masm.empty_FPU_stack(); | |
| 1808 } | |
| 1809 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1810 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1811 } else { | |
| 1812 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1813 } | |
| 1814 %} | |
| 1815 | |
| 1816 enc_class Verify_FPU_For_Leaf %{ | |
| 1817 if( VerifyFPU ) { | |
| 1818 MacroAssembler masm(&cbuf); | |
| 1819 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1820 } | |
| 1821 %} | |
| 1822 | |
| 1823 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1824 // This is the instruction starting address for relocation info. | |
| 1748 | 1825 cbuf.set_insts_mark(); |
| 0 | 1826 $$$emit8$primary; |
| 1827 // CALL directly to the runtime | |
| 1748 | 1828 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1829 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1830 | |
| 1831 if (UseSSE >= 2) { | |
| 1832 MacroAssembler _masm(&cbuf); | |
| 1833 BasicType rt = tf()->return_type(); | |
| 1834 | |
| 1835 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1836 // A C runtime call where the return value is unused. In SSE2+ | |
| 1837 // mode the result needs to be removed from the FPU stack. It's | |
| 1838 // likely that this function call could be removed by the | |
| 1839 // optimizer if the C function is a pure function. | |
| 1840 __ ffree(0); | |
| 1841 } else if (rt == T_FLOAT) { | |
| 304 | 1842 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1843 __ fstp_s(Address(rsp, 0)); |
| 1844 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1845 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1846 } else if (rt == T_DOUBLE) { |
| 304 | 1847 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1848 __ fstp_d(Address(rsp, 0)); |
| 1849 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1850 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1851 } |
| 1852 } | |
| 1853 %} | |
| 1854 | |
| 1855 | |
| 1856 enc_class pre_call_FPU %{ | |
| 1857 // If method sets FPU control word restore it here | |
| 1748 | 1858 debug_only(int off0 = cbuf.insts_size()); |
| 0 | 1859 if( Compile::current()->in_24_bit_fp_mode() ) { |
| 1860 MacroAssembler masm(&cbuf); | |
| 1861 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1862 } | |
| 1748 | 1863 debug_only(int off1 = cbuf.insts_size()); |
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1864 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); |
| 0 | 1865 %} |
| 1866 | |
| 1867 enc_class post_call_FPU %{ | |
| 1868 // If method sets FPU control word do it here also | |
| 1869 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1870 MacroAssembler masm(&cbuf); | |
| 1871 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1872 } | |
| 1873 %} | |
| 1874 | |
| 1875 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1876 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1877 // who we intended to call. | |
| 1748 | 1878 cbuf.set_insts_mark(); |
| 0 | 1879 $$$emit8$primary; |
| 1880 if ( !_method ) { | |
| 1748 | 1881 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1882 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1883 } else if(_optimized_virtual) { | |
| 1748 | 1884 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1885 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1886 } else { | |
| 1748 | 1887 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1888 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1889 } | |
| 1890 if( _method ) { // Emit stub for static call | |
| 1891 emit_java_to_interp(cbuf); | |
| 1892 } | |
| 1893 %} | |
| 1894 | |
| 1895 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
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1896 MacroAssembler _masm(&cbuf); |
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1897 __ ic_call((address)$meth$$method); |
| 0 | 1898 %} |
| 1899 | |
| 1900 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
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1901 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1902 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1903 | |
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1904 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1905 cbuf.set_insts_mark(); |
| 0 | 1906 $$$emit8$primary; |
| 1907 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1908 emit_d8(cbuf, disp); // Displacement | |
| 1909 | |
| 1910 %} | |
| 1911 | |
| 1912 // Following encoding is no longer used, but may be restored if calling | |
| 1913 // convention changes significantly. | |
| 1914 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1915 // | |
| 1916 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1917 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1918 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1919 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1920 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1921 // | |
| 1922 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1923 // // // so we load it immediately before the call | |
| 1924 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1925 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1926 // | |
| 1927 // // xor rbp,ebp | |
| 1928 // emit_opcode(cbuf, 0x33); | |
| 1929 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1930 // | |
| 1931 // // CALL to interpreter. | |
| 1748 | 1932 // cbuf.set_insts_mark(); |
| 0 | 1933 // $$$emit8$primary; |
| 1748 | 1934 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1935 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1936 // %} | |
| 1937 | |
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1938 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1939 $$$emit8$primary; |
| 1940 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1941 $$$emit8$shift$$constant; | |
| 1942 %} | |
| 1943 | |
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1944 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1945 // Load immediate does not have a zero or sign extended version |
| 1946 // for 8-bit immediates | |
| 1947 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1948 $$$emit32$src$$constant; | |
| 1949 %} | |
| 1950 | |
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1951 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1952 // Load immediate does not have a zero or sign extended version |
| 1953 // for 8-bit immediates | |
| 1954 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1955 $$$emit32$src$$constant; | |
| 1956 %} | |
| 1957 | |
| 1958 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1959 // Load immediate does not have a zero or sign extended version | |
| 1960 // for 8-bit immediates | |
| 1961 int dst_enc = $dst$$reg; | |
| 1962 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1963 if (src_con == 0) { | |
| 1964 // xor dst, dst | |
| 1965 emit_opcode(cbuf, 0x33); | |
| 1966 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1967 } else { | |
| 1968 emit_opcode(cbuf, $primary + dst_enc); | |
| 1969 emit_d32(cbuf, src_con); | |
| 1970 } | |
| 1971 %} | |
| 1972 | |
| 1973 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1974 // Load immediate does not have a zero or sign extended version | |
| 1975 // for 8-bit immediates | |
| 1976 int dst_enc = $dst$$reg + 2; | |
| 1977 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1978 if (src_con == 0) { | |
| 1979 // xor dst, dst | |
| 1980 emit_opcode(cbuf, 0x33); | |
| 1981 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1982 } else { | |
| 1983 emit_opcode(cbuf, $primary + dst_enc); | |
| 1984 emit_d32(cbuf, src_con); | |
| 1985 } | |
| 1986 %} | |
| 1987 | |
| 1988 | |
| 1989 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
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1990 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1991 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1992 %} | |
| 1993 | |
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1994 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1995 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1996 %} | |
| 1997 | |
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1998 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 2000 %} | |
| 2001 | |
| 2002 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2003 $$$emit8$primary; | |
| 2004 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2005 %} | |
| 2006 | |
| 2007 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2008 $$$emit8$secondary; | |
| 2009 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2010 %} | |
| 2011 | |
| 2012 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2013 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2014 %} | |
| 2015 | |
| 2016 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2017 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2018 %} | |
| 2019 | |
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2020 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 2021 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 2022 %} | |
| 2023 | |
| 2024 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2025 // Output immediate | |
| 2026 $$$emit32$src$$constant; | |
| 2027 %} | |
| 2028 | |
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2029 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 2030 // Output Float immediate bits |
| 2031 jfloat jf = $src$$constant; | |
| 2032 int jf_as_bits = jint_cast( jf ); | |
| 2033 emit_d32(cbuf, jf_as_bits); | |
| 2034 %} | |
| 2035 | |
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2036 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 2037 // Output Float immediate bits |
| 2038 jfloat jf = $src$$constant; | |
| 2039 int jf_as_bits = jint_cast( jf ); | |
| 2040 emit_d32(cbuf, jf_as_bits); | |
| 2041 %} | |
| 2042 | |
| 2043 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2044 // Output immediate | |
| 2045 $$$emit16$src$$constant; | |
| 2046 %} | |
| 2047 | |
| 2048 enc_class Con_d32(immI src) %{ | |
| 2049 emit_d32(cbuf,$src$$constant); | |
| 2050 %} | |
| 2051 | |
| 2052 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2053 // Output immediate memory reference | |
| 2054 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2055 emit_d32(cbuf, 0x00); | |
| 2056 %} | |
| 2057 | |
| 2058 enc_class lock_prefix( ) %{ | |
| 2059 if( os::is_MP() ) | |
| 2060 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2061 %} | |
| 2062 | |
| 2063 // Cmp-xchg long value. | |
| 2064 // Note: we need to swap rbx, and rcx before and after the | |
| 2065 // cmpxchg8 instruction because the instruction uses | |
| 2066 // rcx as the high order word of the new value to store but | |
| 2067 // our register encoding uses rbx,. | |
| 2068 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2069 | |
| 2070 // XCHG rbx,ecx | |
| 2071 emit_opcode(cbuf,0x87); | |
| 2072 emit_opcode(cbuf,0xD9); | |
| 2073 // [Lock] | |
| 2074 if( os::is_MP() ) | |
| 2075 emit_opcode(cbuf,0xF0); | |
| 2076 // CMPXCHG8 [Eptr] | |
| 2077 emit_opcode(cbuf,0x0F); | |
| 2078 emit_opcode(cbuf,0xC7); | |
| 2079 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2080 // XCHG rbx,ecx | |
| 2081 emit_opcode(cbuf,0x87); | |
| 2082 emit_opcode(cbuf,0xD9); | |
| 2083 %} | |
| 2084 | |
| 2085 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2086 // [Lock] | |
| 2087 if( os::is_MP() ) | |
| 2088 emit_opcode(cbuf,0xF0); | |
| 2089 | |
| 2090 // CMPXCHG [Eptr] | |
| 2091 emit_opcode(cbuf,0x0F); | |
| 2092 emit_opcode(cbuf,0xB1); | |
| 2093 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2094 %} | |
| 2095 | |
| 2096 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2097 int res_encoding = $res$$reg; | |
| 2098 | |
| 2099 // MOV res,0 | |
| 2100 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2101 emit_d32( cbuf, 0 ); | |
| 2102 // JNE,s fail | |
| 2103 emit_opcode(cbuf,0x75); | |
| 2104 emit_d8(cbuf, 5 ); | |
| 2105 // MOV res,1 | |
| 2106 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2107 emit_d32( cbuf, 1 ); | |
| 2108 // fail: | |
| 2109 %} | |
| 2110 | |
| 2111 enc_class set_instruction_start( ) %{ | |
| 1748 | 2112 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2113 %} |
| 2114 | |
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2115 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2116 int reg_encoding = $ereg$$reg; |
| 2117 int base = $mem$$base; | |
| 2118 int index = $mem$$index; | |
| 2119 int scale = $mem$$scale; | |
| 2120 int displace = $mem$$disp; | |
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2121 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2122 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2123 %} |
| 2124 | |
| 2125 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2126 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2127 int base = $mem$$base; | |
| 2128 int index = $mem$$index; | |
| 2129 int scale = $mem$$scale; | |
| 2130 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
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2131 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
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2132 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2133 %} |
| 2134 | |
| 2135 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2136 int r1, r2; | |
| 2137 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2138 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2139 emit_opcode(cbuf,0x0F); | |
| 2140 emit_opcode(cbuf,$tertiary); | |
| 2141 emit_rm(cbuf, 0x3, r1, r2); | |
| 2142 emit_d8(cbuf,$cnt$$constant); | |
| 2143 emit_d8(cbuf,$primary); | |
| 2144 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2145 emit_d8(cbuf,$cnt$$constant); | |
| 2146 %} | |
| 2147 | |
| 2148 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2149 emit_opcode( cbuf, 0x8B ); // Move | |
| 2150 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2151 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2152 emit_d8(cbuf,$primary); |
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2153 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2154 emit_d8(cbuf,$cnt$$constant-32); |
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2155 } |
| 0 | 2156 emit_d8(cbuf,$primary); |
| 2157 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2158 emit_d8(cbuf,31); | |
| 2159 %} | |
| 2160 | |
| 2161 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2162 int r1, r2; | |
| 2163 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2164 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2165 | |
| 2166 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2167 emit_rm(cbuf, 0x3, r1, r2); | |
| 2168 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2169 emit_opcode(cbuf,$primary); | |
| 2170 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2171 emit_d8(cbuf,$cnt$$constant-32); | |
| 2172 } | |
| 2173 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2174 emit_rm(cbuf, 0x3, r2, r2); | |
| 2175 %} | |
| 2176 | |
| 2177 // Clone of RegMem but accepts an extra parameter to access each | |
| 2178 // half of a double in memory; it never needs relocation info. | |
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2179 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2180 emit_opcode(cbuf,$opcode$$constant); |
| 2181 int reg_encoding = $rm_reg$$reg; | |
| 2182 int base = $mem$$base; | |
| 2183 int index = $mem$$index; | |
| 2184 int scale = $mem$$scale; | |
| 2185 int displace = $mem$$disp + $disp_for_half$$constant; | |
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2186 relocInfo::relocType disp_reloc = relocInfo::none; |
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2187 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2188 %} |
| 2189 | |
| 2190 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2191 // | |
| 2192 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2193 // and it never needs relocation information. | |
| 2194 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2195 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2196 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2197 int base = $mem$$base; | |
| 2198 int index = $mem$$index; | |
| 2199 int scale = $mem$$scale; | |
| 2200 int displace = $mem$$disp; | |
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2201 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
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2202 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2203 %} |
| 2204 | |
| 2205 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2206 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2207 int base = $mem$$base; | |
| 2208 int index = $mem$$index; | |
| 2209 int scale = $mem$$scale; | |
| 2210 int displace = $mem$$disp; | |
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2211 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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2212 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2213 %} |
| 2214 | |
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2215 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2216 int reg_encoding = $dst$$reg; |
| 2217 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2218 int index = 0x04; // 0x04 indicates no index | |
| 2219 int scale = 0x00; // 0x00 indicates no scale | |
| 2220 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2221 relocInfo::relocType disp_reloc = relocInfo::none; |
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2222 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2223 %} |
| 2224 | |
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2225 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2226 // Compare dst,src |
| 2227 emit_opcode(cbuf,0x3B); | |
| 2228 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2229 // jmp dst < src around move | |
| 2230 emit_opcode(cbuf,0x7C); | |
| 2231 emit_d8(cbuf,2); | |
| 2232 // move dst,src | |
| 2233 emit_opcode(cbuf,0x8B); | |
| 2234 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2235 %} | |
| 2236 | |
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2237 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2238 // Compare dst,src |
| 2239 emit_opcode(cbuf,0x3B); | |
| 2240 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2241 // jmp dst > src around move | |
| 2242 emit_opcode(cbuf,0x7F); | |
| 2243 emit_d8(cbuf,2); | |
| 2244 // move dst,src | |
| 2245 emit_opcode(cbuf,0x8B); | |
| 2246 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2247 %} | |
| 2248 | |
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2249 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2250 // If src is FPR1, we can just FST to store it. |
| 2251 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2252 int reg_encoding = 0x2; // Just store | |
| 2253 int base = $mem$$base; | |
| 2254 int index = $mem$$index; | |
| 2255 int scale = $mem$$scale; | |
| 2256 int displace = $mem$$disp; | |
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2257 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2258 if( $src$$reg != FPR1L_enc ) { |
| 2259 reg_encoding = 0x3; // Store & pop | |
| 2260 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2261 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2262 } | |
| 1748 | 2263 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2264 emit_opcode(cbuf,$primary); |
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2265 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2266 %} |
| 2267 | |
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2268 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2269 // NEG $dst |
| 2270 emit_opcode(cbuf,0xF7); | |
| 2271 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2272 %} | |
| 2273 | |
| 2274 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2275 // SETLT $dst | |
| 2276 emit_opcode(cbuf,0x0F); | |
| 2277 emit_opcode(cbuf,0x9C); | |
| 2278 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2279 %} | |
| 2280 | |
| 2281 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2282 int tmpReg = $tmp$$reg; | |
| 2283 | |
| 2284 // SUB $p,$q | |
| 2285 emit_opcode(cbuf,0x2B); | |
| 2286 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2287 // SBB $tmp,$tmp | |
| 2288 emit_opcode(cbuf,0x1B); | |
| 2289 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2290 // AND $tmp,$y | |
| 2291 emit_opcode(cbuf,0x23); | |
| 2292 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2293 // ADD $p,$tmp | |
| 2294 emit_opcode(cbuf,0x03); | |
| 2295 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2296 %} | |
| 2297 | |
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2298 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT |
| 0 | 2299 int tmpReg = $tmp$$reg; |
| 2300 | |
| 2301 // SUB $p,$q | |
| 2302 emit_opcode(cbuf,0x2B); | |
| 2303 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2304 // SBB $tmp,$tmp | |
| 2305 emit_opcode(cbuf,0x1B); | |
| 2306 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2307 // AND $tmp,$y | |
| 1748 | 2308 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2309 emit_opcode(cbuf,0x23); |
| 2310 int reg_encoding = tmpReg; | |
| 2311 int base = $mem$$base; | |
| 2312 int index = $mem$$index; | |
| 2313 int scale = $mem$$scale; | |
| 2314 int displace = $mem$$disp; | |
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2315 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2316 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2317 // ADD $p,$tmp |
| 2318 emit_opcode(cbuf,0x03); | |
| 2319 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2320 %} | |
| 2321 | |
| 2322 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2323 // TEST shift,32 | |
| 2324 emit_opcode(cbuf,0xF7); | |
| 2325 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2326 emit_d32(cbuf,0x20); | |
| 2327 // JEQ,s small | |
| 2328 emit_opcode(cbuf, 0x74); | |
| 2329 emit_d8(cbuf, 0x04); | |
| 2330 // MOV $dst.hi,$dst.lo | |
| 2331 emit_opcode( cbuf, 0x8B ); | |
| 2332 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2333 // CLR $dst.lo | |
| 2334 emit_opcode(cbuf, 0x33); | |
| 2335 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2336 // small: | |
| 2337 // SHLD $dst.hi,$dst.lo,$shift | |
| 2338 emit_opcode(cbuf,0x0F); | |
| 2339 emit_opcode(cbuf,0xA5); | |
| 2340 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2341 // SHL $dst.lo,$shift" | |
| 2342 emit_opcode(cbuf,0xD3); | |
| 2343 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2344 %} | |
| 2345 | |
| 2346 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2347 // TEST shift,32 | |
| 2348 emit_opcode(cbuf,0xF7); | |
| 2349 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2350 emit_d32(cbuf,0x20); | |
| 2351 // JEQ,s small | |
| 2352 emit_opcode(cbuf, 0x74); | |
| 2353 emit_d8(cbuf, 0x04); | |
| 2354 // MOV $dst.lo,$dst.hi | |
| 2355 emit_opcode( cbuf, 0x8B ); | |
| 2356 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2357 // CLR $dst.hi | |
| 2358 emit_opcode(cbuf, 0x33); | |
| 2359 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2360 // small: | |
| 2361 // SHRD $dst.lo,$dst.hi,$shift | |
| 2362 emit_opcode(cbuf,0x0F); | |
| 2363 emit_opcode(cbuf,0xAD); | |
| 2364 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2365 // SHR $dst.hi,$shift" | |
| 2366 emit_opcode(cbuf,0xD3); | |
| 2367 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2368 %} | |
| 2369 | |
| 2370 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2371 // TEST shift,32 | |
| 2372 emit_opcode(cbuf,0xF7); | |
| 2373 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2374 emit_d32(cbuf,0x20); | |
| 2375 // JEQ,s small | |
| 2376 emit_opcode(cbuf, 0x74); | |
| 2377 emit_d8(cbuf, 0x05); | |
| 2378 // MOV $dst.lo,$dst.hi | |
| 2379 emit_opcode( cbuf, 0x8B ); | |
| 2380 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2381 // SAR $dst.hi,31 | |
| 2382 emit_opcode(cbuf, 0xC1); | |
| 2383 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2384 emit_d8(cbuf, 0x1F ); | |
| 2385 // small: | |
| 2386 // SHRD $dst.lo,$dst.hi,$shift | |
| 2387 emit_opcode(cbuf,0x0F); | |
| 2388 emit_opcode(cbuf,0xAD); | |
| 2389 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2390 // SAR $dst.hi,$shift" | |
| 2391 emit_opcode(cbuf,0xD3); | |
| 2392 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2393 %} | |
| 2394 | |
| 2395 | |
| 2396 // ----------------- Encodings for floating point unit ----------------- | |
| 2397 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2398 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2399 $$$emit8$primary; |
| 2400 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2401 %} | |
| 2402 | |
| 2403 // Pop argument in FPR0 with FSTP ST(0) | |
| 2404 enc_class PopFPU() %{ | |
| 2405 emit_opcode( cbuf, 0xDD ); | |
| 2406 emit_d8( cbuf, 0xD8 ); | |
| 2407 %} | |
| 2408 | |
| 2409 // !!!!! equivalent to Pop_Reg_F | |
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2410 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2411 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2412 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2413 %} | |
| 2414 | |
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2415 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2416 emit_opcode( cbuf, 0xD9 ); |
| 2417 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2418 %} | |
| 2419 | |
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2420 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2421 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2422 emit_opcode( cbuf, 0x2D ); | |
| 2423 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2424 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2425 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2426 %} | |
| 2427 | |
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2428 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2429 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2430 emit_opcode( cbuf, 0x2D ); | |
| 2431 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2432 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2433 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2434 %} | |
| 2435 | |
| 2436 // Special case for moving an integer register to a stack slot. | |
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2437 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2438 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2439 %} | |
| 2440 | |
| 2441 // Special case for moving a register to a stack slot. | |
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2442 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2443 // Opcode already emitted |
| 2444 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2445 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2446 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2447 %} | |
| 2448 | |
| 2449 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2450 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2451 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2452 %} | |
| 2453 | |
| 2454 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2455 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2456 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2457 %} | |
| 2458 | |
| 2459 // Same as Pop_Mem_F except for opcode | |
| 2460 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2461 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2462 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2463 %} | |
| 2464 | |
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2465 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2466 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2467 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2468 %} | |
| 2469 | |
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2470 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2471 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2472 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2473 %} | |
| 2474 | |
| 2475 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2476 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2477 int pop = 0x02; |
| 2478 if ($src$$reg != FPR1L_enc) { | |
| 2479 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2480 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2481 pop = 0x03; | |
| 2482 } | |
| 2483 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2484 %} | |
| 2485 | |
| 2486 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2487 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2488 int pop = 0x02; |
| 2489 if ($src$$reg != FPR1L_enc) { | |
| 2490 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2491 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2492 pop = 0x03; | |
| 2493 } | |
| 2494 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2495 %} | |
| 2496 | |
| 2497 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2498 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2499 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2500 if ($src$$reg != FPR1L_enc) { | |
| 2501 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2502 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2503 pop = 0xD8; | |
| 2504 } | |
| 2505 emit_opcode( cbuf, 0xDD ); | |
| 2506 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2507 %} | |
| 2508 | |
| 2509 | |
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2510 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2511 // load dst in FPR0 |
| 2512 emit_opcode( cbuf, 0xD9 ); | |
| 2513 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2514 if ($src$$reg != FPR1L_enc) { | |
| 2515 // fincstp | |
| 2516 emit_opcode (cbuf, 0xD9); | |
| 2517 emit_opcode (cbuf, 0xF7); | |
| 2518 // swap src with FPR1: | |
| 2519 // FXCH FPR1 with src | |
| 2520 emit_opcode(cbuf, 0xD9); | |
| 2521 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2522 // fdecstp | |
| 2523 emit_opcode (cbuf, 0xD9); | |
| 2524 emit_opcode (cbuf, 0xF6); | |
| 2525 } | |
| 2526 %} | |
| 2527 | |
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2528 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2529 MacroAssembler _masm(&cbuf); |
| 2530 __ subptr(rsp, 8); | |
| 2531 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2532 __ fld_d(Address(rsp, 0)); | |
| 2533 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2534 __ fld_d(Address(rsp, 0)); | |
| 2535 %} | |
| 2536 | |
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2537 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2538 MacroAssembler _masm(&cbuf); |
| 2539 __ subptr(rsp, 4); | |
| 2540 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2541 __ fld_s(Address(rsp, 0)); | |
| 2542 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2543 __ fld_s(Address(rsp, 0)); | |
| 0 | 2544 %} |
| 2545 | |
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2546 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2547 MacroAssembler _masm(&cbuf); |
| 2548 __ fstp_d(Address(rsp, 0)); | |
| 2549 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2550 __ addptr(rsp, 8); | |
| 0 | 2551 %} |
| 2552 | |
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2553 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2554 MacroAssembler _masm(&cbuf); |
| 2555 __ fstp_s(Address(rsp, 0)); | |
| 2556 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2557 __ addptr(rsp, $d8$$constant); | |
| 0 | 2558 %} |
| 2559 | |
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2560 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2561 MacroAssembler _masm(&cbuf); |
| 2562 __ subptr(rsp, 8); | |
| 2563 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2564 __ fld_d(Address(rsp, 0)); | |
| 0 | 2565 %} |
| 2566 | |
| 2567 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2568 MacroAssembler _masm(&cbuf); |
| 2569 __ subptr(rsp, 8); | |
| 0 | 2570 %} |
| 2571 | |
| 2572 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2573 MacroAssembler _masm(&cbuf); |
| 2574 __ addptr(rsp, 8); | |
| 2575 %} | |
| 2576 | |
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2577 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2578 MacroAssembler _masm(&cbuf); |
| 2579 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2580 __ fld_d(Address(rsp, 0)); | |
| 0 | 2581 %} |
| 2582 | |
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2583 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2584 if ($src$$reg != FPR1L_enc) { |
| 2585 // fincstp | |
| 2586 emit_opcode (cbuf, 0xD9); | |
| 2587 emit_opcode (cbuf, 0xF7); | |
| 2588 // FXCH FPR1 with src | |
| 2589 emit_opcode(cbuf, 0xD9); | |
| 2590 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2591 // fdecstp | |
| 2592 emit_opcode (cbuf, 0xD9); | |
| 2593 emit_opcode (cbuf, 0xF6); | |
| 2594 } | |
| 2595 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2596 // // FSTP FPR$dst$$reg | |
| 2597 // emit_opcode( cbuf, 0xDD ); | |
| 2598 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2599 %} | |
| 2600 | |
| 2601 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2602 // fnstsw ax | |
| 2603 emit_opcode( cbuf, 0xDF ); | |
| 2604 emit_opcode( cbuf, 0xE0 ); | |
| 2605 // sahf | |
| 2606 emit_opcode( cbuf, 0x9E ); | |
| 2607 // jnp ::skip | |
| 2608 emit_opcode( cbuf, 0x7B ); | |
| 2609 emit_opcode( cbuf, 0x05 ); | |
| 2610 %} | |
| 2611 | |
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2612 enc_class emitModDPR() %{ |
| 0 | 2613 // fprem must be iterative |
| 2614 // :: loop | |
| 2615 // fprem | |
| 2616 emit_opcode( cbuf, 0xD9 ); | |
| 2617 emit_opcode( cbuf, 0xF8 ); | |
| 2618 // wait | |
| 2619 emit_opcode( cbuf, 0x9b ); | |
| 2620 // fnstsw ax | |
| 2621 emit_opcode( cbuf, 0xDF ); | |
| 2622 emit_opcode( cbuf, 0xE0 ); | |
| 2623 // sahf | |
| 2624 emit_opcode( cbuf, 0x9E ); | |
| 2625 // jp ::loop | |
| 2626 emit_opcode( cbuf, 0x0F ); | |
| 2627 emit_opcode( cbuf, 0x8A ); | |
| 2628 emit_opcode( cbuf, 0xF4 ); | |
| 2629 emit_opcode( cbuf, 0xFF ); | |
| 2630 emit_opcode( cbuf, 0xFF ); | |
| 2631 emit_opcode( cbuf, 0xFF ); | |
| 2632 %} | |
| 2633 | |
| 2634 enc_class fpu_flags() %{ | |
| 2635 // fnstsw_ax | |
| 2636 emit_opcode( cbuf, 0xDF); | |
| 2637 emit_opcode( cbuf, 0xE0); | |
| 2638 // test ax,0x0400 | |
| 2639 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2640 emit_opcode( cbuf, 0xA9 ); | |
| 2641 emit_d16 ( cbuf, 0x0400 ); | |
| 2642 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2643 // // test rax,0x0400 | |
| 2644 // emit_opcode( cbuf, 0xA9 ); | |
| 2645 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2646 // | |
| 2647 // jz exit (no unordered comparison) | |
| 2648 emit_opcode( cbuf, 0x74 ); | |
| 2649 emit_d8 ( cbuf, 0x02 ); | |
| 2650 // mov ah,1 - treat as LT case (set carry flag) | |
| 2651 emit_opcode( cbuf, 0xB4 ); | |
| 2652 emit_d8 ( cbuf, 0x01 ); | |
| 2653 // sahf | |
| 2654 emit_opcode( cbuf, 0x9E); | |
| 2655 %} | |
| 2656 | |
| 2657 enc_class cmpF_P6_fixup() %{ | |
| 2658 // Fixup the integer flags in case comparison involved a NaN | |
| 2659 // | |
| 2660 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2661 emit_opcode( cbuf, 0x7B ); | |
| 2662 emit_d8 ( cbuf, 0x03 ); | |
| 2663 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2664 emit_opcode( cbuf, 0xB4 ); | |
| 2665 emit_d8 ( cbuf, 0x01 ); | |
| 2666 // SAHF | |
| 2667 emit_opcode( cbuf, 0x9E); | |
| 2668 // NOP // target for branch to avoid branch to branch | |
| 2669 emit_opcode( cbuf, 0x90); | |
| 2670 %} | |
| 2671 | |
| 2672 // fnstsw_ax(); | |
| 2673 // sahf(); | |
| 2674 // movl(dst, nan_result); | |
| 2675 // jcc(Assembler::parity, exit); | |
| 2676 // movl(dst, less_result); | |
| 2677 // jcc(Assembler::below, exit); | |
| 2678 // movl(dst, equal_result); | |
| 2679 // jcc(Assembler::equal, exit); | |
| 2680 // movl(dst, greater_result); | |
| 2681 | |
| 2682 // less_result = 1; | |
| 2683 // greater_result = -1; | |
| 2684 // equal_result = 0; | |
| 2685 // nan_result = -1; | |
| 2686 | |
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2687 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2688 // fnstsw_ax(); |
| 2689 emit_opcode( cbuf, 0xDF); | |
| 2690 emit_opcode( cbuf, 0xE0); | |
| 2691 // sahf | |
| 2692 emit_opcode( cbuf, 0x9E); | |
| 2693 // movl(dst, nan_result); | |
| 2694 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2695 emit_d32( cbuf, -1 ); | |
| 2696 // jcc(Assembler::parity, exit); | |
| 2697 emit_opcode( cbuf, 0x7A ); | |
| 2698 emit_d8 ( cbuf, 0x13 ); | |
| 2699 // movl(dst, less_result); | |
| 2700 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2701 emit_d32( cbuf, -1 ); | |
| 2702 // jcc(Assembler::below, exit); | |
| 2703 emit_opcode( cbuf, 0x72 ); | |
| 2704 emit_d8 ( cbuf, 0x0C ); | |
| 2705 // movl(dst, equal_result); | |
| 2706 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2707 emit_d32( cbuf, 0 ); | |
| 2708 // jcc(Assembler::equal, exit); | |
| 2709 emit_opcode( cbuf, 0x74 ); | |
| 2710 emit_d8 ( cbuf, 0x05 ); | |
| 2711 // movl(dst, greater_result); | |
| 2712 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2713 emit_d32( cbuf, 1 ); | |
| 2714 %} | |
| 2715 | |
| 2716 | |
| 2717 // Compare the longs and set flags | |
| 2718 // BROKEN! Do Not use as-is | |
| 2719 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2720 // CMP $src1.hi,$src2.hi | |
| 2721 emit_opcode( cbuf, 0x3B ); | |
| 2722 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2723 // JNE,s done | |
| 2724 emit_opcode(cbuf,0x75); | |
| 2725 emit_d8(cbuf, 2 ); | |
| 2726 // CMP $src1.lo,$src2.lo | |
| 2727 emit_opcode( cbuf, 0x3B ); | |
| 2728 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2729 // done: | |
| 2730 %} | |
| 2731 | |
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2732 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2733 // mov $dst.lo,$src |
| 2734 int dst_encoding = $dst$$reg; | |
| 2735 int src_encoding = $src$$reg; | |
| 2736 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2737 // mov $dst.hi,$src | |
| 2738 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2739 // sar $dst.hi,31 | |
| 2740 emit_opcode( cbuf, 0xC1 ); | |
| 2741 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2742 emit_d8(cbuf, 0x1F ); | |
| 2743 %} | |
| 2744 | |
| 2745 enc_class convert_long_double( eRegL src ) %{ | |
| 2746 // push $src.hi | |
| 2747 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2748 // push $src.lo | |
| 2749 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2750 // fild 64-bits at [SP] | |
| 2751 emit_opcode(cbuf,0xdf); | |
| 2752 emit_d8(cbuf, 0x6C); | |
| 2753 emit_d8(cbuf, 0x24); | |
| 2754 emit_d8(cbuf, 0x00); | |
| 2755 // pop stack | |
| 2756 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2757 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2758 emit_d8(cbuf, 0x8); | |
| 2759 %} | |
| 2760 | |
| 2761 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2762 // IMUL EDX:EAX,$src1 | |
| 2763 emit_opcode( cbuf, 0xF7 ); | |
| 2764 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2765 // SAR EDX,$cnt-32 | |
| 2766 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2767 if (shift_count > 0) { | |
| 2768 emit_opcode(cbuf, 0xC1); | |
| 2769 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2770 emit_d8(cbuf, shift_count); | |
| 2771 } | |
| 2772 %} | |
| 2773 | |
| 2774 // this version doesn't have add sp, 8 | |
| 2775 enc_class convert_long_double2( eRegL src ) %{ | |
| 2776 // push $src.hi | |
| 2777 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2778 // push $src.lo | |
| 2779 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2780 // fild 64-bits at [SP] | |
| 2781 emit_opcode(cbuf,0xdf); | |
| 2782 emit_d8(cbuf, 0x6C); | |
| 2783 emit_d8(cbuf, 0x24); | |
| 2784 emit_d8(cbuf, 0x00); | |
| 2785 %} | |
| 2786 | |
| 2787 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2788 // Basic idea: long = (long)int * (long)int | |
| 2789 // IMUL EDX:EAX, src | |
| 2790 emit_opcode( cbuf, 0xF7 ); | |
| 2791 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2792 %} | |
| 2793 | |
| 2794 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2795 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2796 // MUL EDX:EAX, src | |
| 2797 emit_opcode( cbuf, 0xF7 ); | |
| 2798 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2799 %} | |
| 2800 | |
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2801 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2802 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2803 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2804 // MOV $tmp,$src.lo | |
| 2805 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2806 // IMUL $tmp,EDX | |
| 2807 emit_opcode( cbuf, 0x0F ); | |
| 2808 emit_opcode( cbuf, 0xAF ); | |
| 2809 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2810 // MOV EDX,$src.hi | |
| 2811 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2812 // IMUL EDX,EAX | |
| 2813 emit_opcode( cbuf, 0x0F ); | |
| 2814 emit_opcode( cbuf, 0xAF ); | |
| 2815 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2816 // ADD $tmp,EDX | |
| 2817 emit_opcode( cbuf, 0x03 ); | |
| 2818 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2819 // MUL EDX:EAX,$src.lo | |
| 2820 emit_opcode( cbuf, 0xF7 ); | |
| 2821 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2822 // ADD EDX,ESI | |
| 2823 emit_opcode( cbuf, 0x03 ); | |
| 2824 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2825 %} | |
| 2826 | |
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2827 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2828 // Basic idea: lo(result) = lo(src * y_lo) |
| 2829 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2830 // IMUL $tmp,EDX,$src | |
| 2831 emit_opcode( cbuf, 0x6B ); | |
| 2832 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2833 emit_d8( cbuf, (int)$src$$constant ); | |
| 2834 // MOV EDX,$src | |
| 2835 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2836 emit_d32( cbuf, (int)$src$$constant ); | |
| 2837 // MUL EDX:EAX,EDX | |
| 2838 emit_opcode( cbuf, 0xF7 ); | |
| 2839 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2840 // ADD EDX,ESI | |
| 2841 emit_opcode( cbuf, 0x03 ); | |
| 2842 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2843 %} | |
| 2844 | |
| 2845 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2846 // PUSH src1.hi | |
| 2847 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2848 // PUSH src1.lo | |
| 2849 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2850 // PUSH src2.hi | |
| 2851 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2852 // PUSH src2.lo | |
| 2853 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2854 // CALL directly to the runtime | |
| 1748 | 2855 cbuf.set_insts_mark(); |
| 0 | 2856 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2857 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2858 // Restore stack |
| 2859 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2860 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2861 emit_d8(cbuf, 4*4); | |
| 2862 %} | |
| 2863 | |
| 2864 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2865 // PUSH src1.hi | |
| 2866 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2867 // PUSH src1.lo | |
| 2868 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2869 // PUSH src2.hi | |
| 2870 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2871 // PUSH src2.lo | |
| 2872 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2873 // CALL directly to the runtime | |
| 1748 | 2874 cbuf.set_insts_mark(); |
| 0 | 2875 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2876 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2877 // Restore stack |
| 2878 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2879 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2880 emit_d8(cbuf, 4*4); | |
| 2881 %} | |
| 2882 | |
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2883 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2884 // MOV $tmp,$src.lo |
| 2885 emit_opcode(cbuf, 0x8B); | |
| 2886 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2887 // OR $tmp,$src.hi | |
| 2888 emit_opcode(cbuf, 0x0B); | |
| 2889 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2890 %} | |
| 2891 | |
| 2892 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2893 // CMP $src1.lo,$src2.lo | |
| 2894 emit_opcode( cbuf, 0x3B ); | |
| 2895 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2896 // JNE,s skip | |
| 2897 emit_cc(cbuf, 0x70, 0x5); | |
| 2898 emit_d8(cbuf,2); | |
| 2899 // CMP $src1.hi,$src2.hi | |
| 2900 emit_opcode( cbuf, 0x3B ); | |
| 2901 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2902 %} | |
| 2903 | |
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2904 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2905 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2906 emit_opcode( cbuf, 0x3B ); | |
| 2907 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2908 // MOV $tmp,$src1.hi | |
| 2909 emit_opcode( cbuf, 0x8B ); | |
| 2910 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2911 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2912 emit_opcode( cbuf, 0x1B ); | |
| 2913 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2914 %} | |
| 2915 | |
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2916 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2917 // XOR $tmp,$tmp |
| 2918 emit_opcode(cbuf,0x33); // XOR | |
| 2919 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2920 // CMP $tmp,$src.lo | |
| 2921 emit_opcode( cbuf, 0x3B ); | |
| 2922 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2923 // SBB $tmp,$src.hi | |
| 2924 emit_opcode( cbuf, 0x1B ); | |
| 2925 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2926 %} | |
| 2927 | |
| 2928 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2929 enc_class neg_long( eRegL dst ) %{ | |
| 2930 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2931 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2932 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2933 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2934 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2935 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2936 emit_d8 (cbuf,0 ); | |
| 2937 %} | |
| 2938 | |
| 2939 | |
| 2940 // Because the transitions from emitted code to the runtime | |
| 2941 // monitorenter/exit helper stubs are so slow it's critical that | |
| 2942 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 2943 // | |
| 2944 // See also: cmpFastLock and cmpFastUnlock. | |
| 2945 // | |
| 2946 // What follows is a specialized inline transliteration of the code | |
| 2947 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 2948 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 2949 // at startup-time. These methods would accept arguments as | |
| 2950 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 2951 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 2952 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 2953 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 2954 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 2955 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 2956 // Since the helper routines would be called from multiple synchronization | |
| 2957 // sites. | |
| 2958 // | |
| 2959 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 2960 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 2961 // to those specialized methods. That'd give us a mostly platform-independent | |
| 2962 // implementation that the JITs could optimize and inline at their pleasure. | |
| 2963 // Done correctly, the only time we'd need to cross to native could would be | |
| 2964 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 2965 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 2966 // (b) explicit barriers or fence operations. | |
| 2967 // | |
| 2968 // TODO: | |
| 2969 // | |
| 2970 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 2971 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 2972 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 2973 // the lock operators would typically be faster than reifying Self. | |
| 2974 // | |
| 2975 // * Ideally I'd define the primitives as: | |
| 2976 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 2977 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 2978 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 2979 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 2980 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 2981 // sub-optimal code near the synchronization site. | |
| 2982 // | |
| 2983 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 2984 // Alternately, use a better sp-proximity test. | |
| 2985 // | |
| 2986 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 2987 // Either one is sufficient to uniquely identify a thread. | |
| 2988 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 2989 // | |
| 2990 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 2991 // object is locked by the calling thread but the waitlist is empty. | |
| 2992 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 2993 // | |
| 2994 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 2995 // But beware of excessive branch density on AMD Opterons. | |
| 2996 // | |
| 2997 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 2998 // or failure of the fast-path. If the fast-path fails then we pass | |
| 2999 // control to the slow-path, typically in C. In Fast_Lock and | |
| 3000 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 3001 // will emit a conditional branch immediately after the node. | |
| 3002 // So we have branches to branches and lots of ICC.ZF games. | |
| 3003 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 3004 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 3005 // will drop through the node. ICC.ZF is undefined at exit. | |
| 3006 // In the case of failure, the node will branch directly to the | |
| 3007 // FailureLabel | |
| 3008 | |
| 3009 | |
| 3010 // obj: object to lock | |
| 3011 // box: on-stack box address (displaced header location) - KILLED | |
| 3012 // rax,: tmp -- KILLED | |
| 3013 // scr: tmp -- KILLED | |
| 3014 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 3015 | |
| 3016 Register objReg = as_Register($obj$$reg); | |
| 3017 Register boxReg = as_Register($box$$reg); | |
| 3018 Register tmpReg = as_Register($tmp$$reg); | |
| 3019 Register scrReg = as_Register($scr$$reg); | |
| 3020 | |
| 3021 // Ensure the register assignents are disjoint | |
| 3022 guarantee (objReg != boxReg, "") ; | |
| 3023 guarantee (objReg != tmpReg, "") ; | |
| 3024 guarantee (objReg != scrReg, "") ; | |
| 3025 guarantee (boxReg != tmpReg, "") ; | |
| 3026 guarantee (boxReg != scrReg, "") ; | |
| 3027 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 3028 | |
| 3029 MacroAssembler masm(&cbuf); | |
| 3030 | |
| 3031 if (_counters != NULL) { | |
| 3032 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3033 } | |
| 3034 if (EmitSync & 1) { | |
| 3035 // set box->dhw = unused_mark (3) | |
| 304 | 3036 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 3037 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 3038 masm.cmpptr (rsp, (int32_t)0) ; | |
| 3039 } else | |
| 3040 if (EmitSync & 2) { | |
| 3041 Label DONE_LABEL ; | |
| 0 | 3042 if (UseBiasedLocking) { |
| 3043 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3044 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3045 } | |
| 3046 | |
| 304 | 3047 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3048 masm.orptr (tmpReg, 0x1); | |
| 3049 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3050 if (os::is_MP()) { masm.lock(); } |
| 304 | 3051 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3052 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3053 // Recursive locking | |
| 304 | 3054 masm.subptr(tmpReg, rsp); |
| 3055 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3056 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3057 masm.bind(DONE_LABEL) ; | |
| 3058 } else { | |
| 3059 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3060 // ------------------------------------------------ |
| 3061 // * Inflated | |
| 3062 // -- unlocked | |
| 3063 // -- Locked | |
| 3064 // = by self | |
| 3065 // = by other | |
| 3066 // * biased | |
| 3067 // -- by Self | |
| 3068 // -- by other | |
| 3069 // * neutral | |
| 3070 // * stack-locked | |
| 3071 // -- by self | |
| 3072 // = sp-proximity test hits | |
| 3073 // = sp-proximity test generates false-negative | |
| 3074 // -- by other | |
| 3075 // | |
| 3076 | |
| 3077 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3078 | |
| 3079 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3080 // order to reduce the number of conditional branches in the most common cases. | |
| 3081 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3082 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3083 // If this invariant is not held we risk exclusion (safety) failure. | |
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3084 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3085 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3086 } | |
| 3087 | |
| 304 | 3088 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3089 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3090 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3091 | |
| 3092 // Attempt stack-locking ... | |
| 304 | 3093 masm.orptr (tmpReg, 0x1); |
| 3094 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3095 if (os::is_MP()) { masm.lock(); } |
| 304 | 3096 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3097 if (_counters != NULL) { |
| 3098 masm.cond_inc32(Assembler::equal, | |
| 3099 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3100 } | |
| 3101 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3102 | |
| 3103 // Recursive locking | |
| 304 | 3104 masm.subptr(tmpReg, rsp); |
| 3105 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3106 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3107 if (_counters != NULL) { |
| 3108 masm.cond_inc32(Assembler::equal, | |
| 3109 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3110 } | |
| 3111 masm.jmp (DONE_LABEL) ; | |
| 3112 | |
| 3113 masm.bind (IsInflated) ; | |
| 3114 | |
| 3115 // The object is inflated. | |
| 3116 // | |
| 3117 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3118 // Use markOopDesc::monitor_value instead of "2". | |
| 3119 // use markOop::unused_mark() instead of "3". | |
| 3120 // The tmpReg value is an objectMonitor reference ORed with | |
| 3121 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3122 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3123 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3124 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3125 // | |
| 3126 // I use the latter as it avoids AGI stalls. | |
| 3127 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3128 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3129 // | |
| 3130 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3131 | |
| 3132 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3133 // We'd like to write: | |
| 3134 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3135 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3136 // additional latency as we have another ST in the store buffer that must drain. | |
| 3137 | |
| 304 | 3138 if (EmitSync & 8192) { |
| 3139 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3140 masm.get_thread (scrReg) ; | |
| 3141 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
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3142 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3143 if (os::is_MP()) { masm.lock(); } |
| 3144 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3145 } else | |
| 0 | 3146 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3147 masm.movptr(scrReg, boxReg) ; |
| 3148 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3149 |
| 3150 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3151 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3152 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3153 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3154 } |
| 3155 | |
| 3156 if ((EmitSync & 64) == 0) { | |
| 3157 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
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3158 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3159 } else { |
| 0 | 3160 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3161 // Test-And-CAS instead of CAS | |
| 304 | 3162 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3163 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3164 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3165 } |
| 3166 | |
| 3167 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3168 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3169 // to CAS the register containing Self into m->Owner. | |
| 3170 // But we don't have enough registers, so instead we can either try to CAS | |
| 3171 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3172 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3173 // (rsp or the address of the box) into m->owner is harmless. | |
| 3174 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3175 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3176 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3177 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3178 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3179 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3180 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3181 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3182 | |
| 3183 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3184 // We use the latter tactic. | |
| 0 | 3185 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3186 // If the CAS was successful ... | |
| 3187 // Self has acquired the lock | |
| 3188 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3189 // Intentional fall-through into DONE_LABEL ... | |
| 3190 } else { | |
| 304 | 3191 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3192 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3193 |
| 3194 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3195 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3196 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3197 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3198 } |
| 3199 | |
| 3200 if ((EmitSync & 64) == 0) { | |
| 3201 // Optimistic form | |
| 304 | 3202 masm.xorptr (tmpReg, tmpReg) ; |
| 3203 } else { | |
| 0 | 3204 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3205 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3206 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3207 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3208 } |
| 3209 | |
| 3210 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3211 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3212 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3213 masm.get_thread (scrReg) ; | |
| 3214 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3215 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3216 |
| 3217 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3218 // We use the latter tactic. | |
| 3219 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3220 // If the CAS was successful ... | |
| 3221 // Self has acquired the lock | |
| 3222 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3223 // Intentional fall-through into DONE_LABEL ... | |
| 3224 } | |
| 3225 | |
| 3226 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3227 // start of cache line by padding with NOPs. | |
| 3228 // See the AMD and Intel software optimization manuals for the | |
| 3229 // most efficient "long" NOP encodings. | |
| 3230 // Unfortunately none of our alignment mechanisms suffice. | |
| 3231 masm.bind(DONE_LABEL); | |
| 3232 | |
| 3233 // Avoid branch-to-branch on AMD processors | |
| 3234 // This appears to be superstition. | |
| 3235 if (EmitSync & 32) masm.nop() ; | |
| 3236 | |
| 3237 | |
| 3238 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3239 // Fast_Unlock uses the same protocol. | |
| 3240 // ZFlag == 1 -> Success | |
| 3241 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3242 } | |
| 3243 %} | |
| 3244 | |
| 3245 // obj: object to unlock | |
| 3246 // box: box address (displaced header location), killed. Must be EAX. | |
| 3247 // rbx,: killed tmp; cannot be obj nor box. | |
| 3248 // | |
| 3249 // Some commentary on balanced locking: | |
| 3250 // | |
| 3251 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3252 // Methods that don't have provably balanced locking are forced to run in the | |
| 3253 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3254 // The interpreter provides two properties: | |
| 3255 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3256 // objects acquired the current activation (frame). Recall that the | |
| 3257 // interpreter maintains an on-stack list of locks currently held by | |
| 3258 // a frame. | |
| 3259 // I2: If a method attempts to unlock an object that is not held by the | |
| 3260 // the frame the interpreter throws IMSX. | |
| 3261 // | |
| 3262 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3263 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3264 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3265 // is still locked by A(). | |
| 3266 // | |
| 3267 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3268 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3269 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3270 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3271 | |
| 3272 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3273 | |
| 3274 Register objReg = as_Register($obj$$reg); | |
| 3275 Register boxReg = as_Register($box$$reg); | |
| 3276 Register tmpReg = as_Register($tmp$$reg); | |
| 3277 | |
| 3278 guarantee (objReg != boxReg, "") ; | |
| 3279 guarantee (objReg != tmpReg, "") ; | |
| 3280 guarantee (boxReg != tmpReg, "") ; | |
| 3281 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3282 MacroAssembler masm(&cbuf); | |
| 3283 | |
| 3284 if (EmitSync & 4) { | |
| 3285 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3286 masm.cmpptr (rsp, 0) ; |
| 3287 } else | |
| 0 | 3288 if (EmitSync & 8) { |
| 3289 Label DONE_LABEL ; | |
| 3290 if (UseBiasedLocking) { | |
| 3291 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3292 } | |
| 3293 // classic stack-locking code ... | |
| 304 | 3294 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3295 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3296 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3297 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3298 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3299 masm.bind(DONE_LABEL); |
| 3300 } else { | |
| 3301 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3302 | |
| 3303 // Critically, the biased locking test must have precedence over | |
| 3304 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
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3305 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3306 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3307 } | |
| 304 | 3308 |
| 3309 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3310 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3311 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3312 | |
| 304 | 3313 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3314 masm.jccb (Assembler::zero, Stacked) ; |
| 3315 | |
| 3316 masm.bind (Inflated) ; | |
| 3317 // It's inflated. | |
| 3318 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3319 // as java routines or native JNI code called by this thread might | |
| 3320 // have released the lock. | |
| 3321 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3322 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3323 // | |
| 3324 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3325 // such as recursive enter and exit -- but we have to be wary of | |
| 3326 // I$ bloat, T$ effects and BP$ effects. | |
| 3327 // | |
| 3328 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3329 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3330 // we detect and recover from the race that the 1-0 exit admits. | |
| 3331 // | |
| 3332 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3333 // before it STs null into _owner, releasing the lock. Updates | |
| 3334 // to data protected by the critical section must be visible before | |
| 3335 // we drop the lock (and thus before any other thread could acquire | |
| 3336 // the lock and observe the fields protected by the lock). | |
| 3337 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3338 // each other and there's no need for an explicit barrier (fence). | |
| 3339 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3340 | |
| 3341 masm.get_thread (boxReg) ; | |
| 2479 | 3342 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 304 | 3343 // prefetchw [ebx + Offset(_owner)-2] |
| 3344 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3345 } |
| 3346 | |
| 3347 // Note that we could employ various encoding schemes to reduce | |
| 3348 // the number of loads below (currently 4) to just 2 or 3. | |
| 3349 // Refer to the comments in synchronizer.cpp. | |
| 3350 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3351 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3352 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3353 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3354 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3355 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3356 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3357 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
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3358 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3359 masm.jmpb (DONE_LABEL) ; |
| 3360 } else { | |
| 3361 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3362 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3363 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3364 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3365 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3366 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
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|
3367 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3368 masm.jmpb (DONE_LABEL) ; |
| 0 | 3369 } |
| 3370 | |
| 3371 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3372 // contended applications and contended synchronization microbenchmarks. | |
| 3373 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3374 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3375 // with an equal number of never-executed NOPs results in the same regression. | |
| 3376 // We leave it off by default. | |
| 3377 | |
| 3378 if ((EmitSync & 65536) != 0) { | |
| 3379 Label LSuccess, LGoSlowPath ; | |
| 3380 | |
| 3381 masm.bind (CheckSucc) ; | |
| 3382 | |
| 3383 // Optional pre-test ... it's safe to elide this | |
| 304 | 3384 if ((EmitSync & 16) == 0) { |
| 3385 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3386 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3387 } |
| 3388 | |
| 3389 // We have a classic Dekker-style idiom: | |
| 3390 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3391 // There are a number of ways to implement the barrier: | |
| 3392 // (1) lock:andl &m->_owner, 0 | |
| 3393 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3394 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3395 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3396 // (2) If supported, an explicit MFENCE is appealing. | |
| 3397 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3398 // particularly if the write-buffer is full as might be the case if | |
| 3399 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3400 // In more modern implementations MFENCE appears faster, however. | |
| 3401 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3402 // The $lines underlying the top-of-stack should be in M-state. | |
| 3403 // The locked add instruction is serializing, of course. | |
| 3404 // (4) Use xchg, which is serializing | |
| 3405 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3406 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3407 // The integer condition codes will tell us if succ was 0. | |
| 3408 // Since _succ and _owner should reside in the same $line and | |
| 3409 // we just stored into _owner, it's likely that the $line | |
| 3410 // remains in M-state for the lock:orl. | |
| 3411 // | |
| 3412 // We currently use (3), although it's likely that switching to (2) | |
| 3413 // is correct for the future. | |
| 304 | 3414 |
|
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3415 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3416 if (os::is_MP()) { |
| 3417 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3418 masm.mfence(); | |
| 3419 } else { | |
| 3420 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3421 } |
| 3422 } | |
| 3423 // Ratify _succ remains non-null | |
| 304 | 3424 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3425 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3426 | |
| 3427 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3428 if (os::is_MP()) { masm.lock(); } |
| 304 | 3429 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3430 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3431 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3432 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3433 // non-null to non=null | |
| 3434 masm.get_thread (boxReg) ; | |
| 304 | 3435 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3436 // Intentional fall-through into LGoSlowPath ... |
| 3437 | |
| 304 | 3438 masm.bind (LGoSlowPath) ; |
| 3439 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3440 masm.jmpb (DONE_LABEL) ; | |
| 3441 | |
| 3442 masm.bind (LSuccess) ; | |
| 3443 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3444 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3445 } |
| 3446 | |
| 3447 masm.bind (Stacked) ; | |
| 3448 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3449 // It must be stack-locked. | |
| 3450 // Try to reset the header to displaced header. | |
| 3451 // The "box" value on the stack is stable, so we can reload | |
| 3452 // and be assured we observe the same value as above. | |
| 304 | 3453 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3454 if (os::is_MP()) { masm.lock(); } |
| 304 | 3455 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3456 // Intention fall-thru into DONE_LABEL |
| 3457 | |
| 3458 | |
| 3459 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3460 // start of cache line by padding with NOPs. | |
| 3461 // See the AMD and Intel software optimization manuals for the | |
| 3462 // most efficient "long" NOP encodings. | |
| 3463 // Unfortunately none of our alignment mechanisms suffice. | |
| 3464 if ((EmitSync & 65536) == 0) { | |
| 3465 masm.bind (CheckSucc) ; | |
| 3466 } | |
| 3467 masm.bind(DONE_LABEL); | |
| 3468 | |
| 3469 // Avoid branch to branch on AMD processors | |
| 3470 if (EmitSync & 32768) { masm.nop() ; } | |
| 3471 } | |
| 3472 %} | |
| 3473 | |
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3474 |
| 0 | 3475 enc_class enc_pop_rdx() %{ |
| 3476 emit_opcode(cbuf,0x5A); | |
| 3477 %} | |
| 3478 | |
| 3479 enc_class enc_rethrow() %{ | |
| 1748 | 3480 cbuf.set_insts_mark(); |
| 0 | 3481 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 3482 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 3483 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 3484 %} | |
| 3485 | |
| 3486 | |
| 3487 // Convert a double to an int. Java semantics require we do complex | |
| 3488 // manglelations in the corner cases. So we set the rounding mode to | |
| 3489 // 'zero', store the darned double down as an int, and reset the | |
| 3490 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3491 // patches up the correct value directly to the stack. | |
|
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3492 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 3493 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 3494 // exceptions here, so that a NAN or other corner-case value will | |
| 3495 // thrown an exception (but normal values get converted at full speed). | |
| 3496 // However, I2C adapters and other float-stack manglers leave pending | |
| 3497 // invalid-op exceptions hanging. We would have to clear them before | |
| 3498 // enabling them and that is more expensive than just testing for the | |
| 3499 // invalid value Intel stores down in the corner cases. | |
| 3500 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3501 emit_opcode(cbuf,0x2D); | |
| 3502 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3503 // Allocate a word | |
| 3504 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3505 emit_opcode(cbuf,0xEC); | |
| 3506 emit_d8(cbuf,0x04); | |
| 3507 // Encoding assumes a double has been pushed into FPR0. | |
| 3508 // Store down the double as an int, popping the FPU stack | |
| 3509 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3510 emit_opcode(cbuf,0x1C); | |
| 3511 emit_d8(cbuf,0x24); | |
| 3512 // Restore the rounding mode; mask the exception | |
| 3513 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3514 emit_opcode(cbuf,0x2D); | |
| 3515 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3516 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3517 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3518 | |
| 3519 // Load the converted int; adjust CPU stack | |
| 3520 emit_opcode(cbuf,0x58); // POP EAX | |
| 3521 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3522 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3523 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3524 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3525 // Push src onto stack slow-path | |
| 3526 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3527 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3528 // CALL directly to the runtime | |
| 1748 | 3529 cbuf.set_insts_mark(); |
| 0 | 3530 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3531 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3532 // Carry on here... |
| 3533 %} | |
| 3534 | |
|
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3535 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 3536 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 3537 emit_opcode(cbuf,0x2D); | |
| 3538 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3539 // Allocate a word | |
| 3540 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3541 emit_opcode(cbuf,0xEC); | |
| 3542 emit_d8(cbuf,0x08); | |
| 3543 // Encoding assumes a double has been pushed into FPR0. | |
| 3544 // Store down the double as a long, popping the FPU stack | |
| 3545 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3546 emit_opcode(cbuf,0x3C); | |
| 3547 emit_d8(cbuf,0x24); | |
| 3548 // Restore the rounding mode; mask the exception | |
| 3549 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3550 emit_opcode(cbuf,0x2D); | |
| 3551 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3552 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3553 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3554 | |
| 3555 // Load the converted int; adjust CPU stack | |
| 3556 emit_opcode(cbuf,0x58); // POP EAX | |
| 3557 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3558 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3559 emit_d8 (cbuf,0xFA); // rdx | |
| 3560 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3561 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3562 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3563 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3564 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3565 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3566 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3567 // Push src onto stack slow-path | |
| 3568 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3569 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3570 // CALL directly to the runtime | |
| 1748 | 3571 cbuf.set_insts_mark(); |
| 0 | 3572 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3573 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3574 // Carry on here... |
| 3575 %} | |
| 3576 | |
|
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3577 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3578 // Operand was loaded from memory into fp ST (stack top) |
| 3579 // FMUL ST,$src /* D8 C8+i */ | |
| 3580 emit_opcode(cbuf, 0xD8); | |
| 3581 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3582 %} | |
| 3583 | |
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3584 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3585 // FADDP ST,src2 /* D8 C0+i */ |
| 3586 emit_opcode(cbuf, 0xD8); | |
| 3587 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3588 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3589 %} | |
| 3590 | |
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3591 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3592 // FADDP src2,ST /* DE C0+i */ |
| 3593 emit_opcode(cbuf, 0xDE); | |
| 3594 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3595 %} | |
| 3596 | |
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3597 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3598 // Operand has been loaded into fp ST (stack top) |
| 3599 // FSUB ST,$src1 | |
| 3600 emit_opcode(cbuf, 0xD8); | |
| 3601 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3602 | |
| 3603 // FDIV | |
| 3604 emit_opcode(cbuf, 0xD8); | |
| 3605 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3606 %} | |
| 3607 | |
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3608 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3609 // Operand was loaded from memory into fp ST (stack top) |
| 3610 // FADD ST,$src /* D8 C0+i */ | |
| 3611 emit_opcode(cbuf, 0xD8); | |
| 3612 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3613 | |
| 3614 // FMUL ST,src2 /* D8 C*+i */ | |
| 3615 emit_opcode(cbuf, 0xD8); | |
| 3616 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3617 %} | |
| 3618 | |
| 3619 | |
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3620 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3621 // Operand was loaded from memory into fp ST (stack top) |
| 3622 // FADD ST,$src /* D8 C0+i */ | |
| 3623 emit_opcode(cbuf, 0xD8); | |
| 3624 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3625 | |
| 3626 // FMULP src2,ST /* DE C8+i */ | |
| 3627 emit_opcode(cbuf, 0xDE); | |
| 3628 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3629 %} | |
| 3630 | |
| 3631 // Atomically load the volatile long | |
| 3632 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3633 emit_opcode(cbuf,0xDF); | |
| 3634 int rm_byte_opcode = 0x05; | |
| 3635 int base = $mem$$base; | |
| 3636 int index = $mem$$index; | |
| 3637 int scale = $mem$$scale; | |
| 3638 int displace = $mem$$disp; | |
|
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3639 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3640 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3641 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3642 %} | |
| 3643 | |
| 3644 // Volatile Store Long. Must be atomic, so move it into | |
| 3645 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3646 // target address before the store (for null-ptr checks) | |
| 3647 // so the memory operand is used twice in the encoding. | |
| 3648 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3649 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3650 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3651 emit_opcode(cbuf,0xDF); |
| 3652 int rm_byte_opcode = 0x07; | |
| 3653 int base = $mem$$base; | |
| 3654 int index = $mem$$index; | |
| 3655 int scale = $mem$$scale; | |
| 3656 int displace = $mem$$disp; | |
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3657 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3658 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3659 %} |
| 3660 | |
| 3661 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3662 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3663 // in the process | |
| 3664 // We current use TESTL [spp],EDI | |
| 3665 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3666 | |
| 3667 enc_class Safepoint_Poll() %{ | |
| 1748 | 3668 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3669 emit_opcode(cbuf,0x85); |
| 3670 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3671 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3672 %} | |
| 3673 %} | |
| 3674 | |
| 3675 | |
| 3676 //----------FRAME-------------------------------------------------------------- | |
| 3677 // Definition of frame structure and management information. | |
| 3678 // | |
| 3679 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3680 // | (to get allocators register number | |
| 3681 // G Owned by | | v add OptoReg::stack0()) | |
| 3682 // r CALLER | | | |
| 3683 // o | +--------+ pad to even-align allocators stack-slot | |
| 3684 // w V | pad0 | numbers; owned by CALLER | |
| 3685 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3686 // h ^ | in | 5 | |
| 3687 // | | args | 4 Holes in incoming args owned by SELF | |
| 3688 // | | | | 3 | |
| 3689 // | | +--------+ | |
| 3690 // V | | old out| Empty on Intel, window on Sparc | |
| 3691 // | old |preserve| Must be even aligned. | |
| 3692 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3693 // | | in | 3 area for Intel ret address | |
| 3694 // Owned by |preserve| Empty on Sparc. | |
| 3695 // SELF +--------+ | |
| 3696 // | | pad2 | 2 pad to align old SP | |
| 3697 // | +--------+ 1 | |
| 3698 // | | locks | 0 | |
| 3699 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3700 // | | pad1 | 11 pad to align new SP | |
| 3701 // | +--------+ | |
| 3702 // | | | 10 | |
| 3703 // | | spills | 9 spills | |
| 3704 // V | | 8 (pad0 slot for callee) | |
| 3705 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3706 // ^ | out | 7 | |
| 3707 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3708 // Owned by +--------+ | |
| 3709 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3710 // | new |preserve| Must be even-aligned. | |
| 3711 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3712 // | | | | |
| 3713 // | |
| 3714 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3715 // known from SELF's arguments and the Java calling convention. | |
| 3716 // Region 6-7 is determined per call site. | |
| 3717 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3718 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3719 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3720 // incoming area, as the Java calling convention is completely under | |
| 3721 // the control of the AD file. Doubles can be sorted and packed to | |
| 3722 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3723 // varargs C calling conventions. | |
| 3724 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3725 // even aligned with pad0 as needed. | |
| 3726 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3727 // region 6-11 is even aligned; it may be padded out more so that | |
| 3728 // the region from SP to FP meets the minimum stack alignment. | |
| 3729 | |
| 3730 frame %{ | |
| 3731 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3732 stack_direction(TOWARDS_LOW); | |
| 3733 | |
| 3734 // These three registers define part of the calling convention | |
| 3735 // between compiled code and the interpreter. | |
| 3736 inline_cache_reg(EAX); // Inline Cache Register | |
| 3737 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3738 | |
| 3739 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3740 cisc_spilling_operand_name(indOffset32); | |
| 3741 | |
| 3742 // Number of stack slots consumed by locking an object | |
| 3743 sync_stack_slots(1); | |
| 3744 | |
| 3745 // Compiled code's Frame Pointer | |
| 3746 frame_pointer(ESP); | |
| 3747 // Interpreter stores its frame pointer in a register which is | |
| 3748 // stored to the stack by I2CAdaptors. | |
| 3749 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3750 interpreter_frame_pointer(EBP); | |
| 3751 | |
| 3752 // Stack alignment requirement | |
| 3753 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3754 stack_alignment(StackAlignmentInBytes); | |
| 3755 | |
| 3756 // Number of stack slots between incoming argument block and the start of | |
| 3757 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3758 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3759 // return address and one for rbp, (must save rbp) | |
| 3760 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3761 | |
| 3762 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3763 // for calls to C. Supports the var-args backing area for register parms. | |
| 3764 varargs_C_out_slots_killed(0); | |
| 3765 | |
| 3766 // The after-PROLOG location of the return address. Location of | |
| 3767 // return address specifies a type (REG or STACK) and a number | |
| 3768 // representing the register number (i.e. - use a register name) or | |
| 3769 // stack slot. | |
| 3770 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3771 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3772 return_addr(STACK - 1 + | |
| 4950 | 3773 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3774 Compile::current()->fixed_slots()), | |
| 3775 stack_alignment_in_slots())); | |
| 0 | 3776 |
| 3777 // Body of function which returns an integer array locating | |
| 3778 // arguments either in registers or in stack slots. Passed an array | |
| 3779 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3780 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3781 // arguments for a CALLEE. Incoming stack arguments are | |
| 3782 // automatically biased by the preserve_stack_slots field above. | |
| 3783 calling_convention %{ | |
| 3784 // No difference between ingoing/outgoing just pass false | |
| 3785 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3786 %} | |
| 3787 | |
| 3788 | |
| 3789 // Body of function which returns an integer array locating | |
| 3790 // arguments either in registers or in stack slots. Passed an array | |
| 3791 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3792 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3793 // arguments for a CALLEE. Incoming stack arguments are | |
| 3794 // automatically biased by the preserve_stack_slots field above. | |
| 3795 c_calling_convention %{ | |
| 3796 // This is obviously always outgoing | |
| 3797 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3798 %} | |
| 3799 | |
| 3800 // Location of C & interpreter return values | |
| 3801 c_return_value %{ | |
| 3802 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3803 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3804 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3805 |
| 3806 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3807 // that C functions return float and double results in XMM0. | |
| 3808 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
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3809 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3810 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
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3811 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3812 |
| 3813 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3814 %} | |
| 3815 | |
| 3816 // Location of return values | |
| 3817 return_value %{ | |
| 3818 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3819 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3820 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3821 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
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3822 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3823 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
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3824 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3825 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3826 %} | |
| 3827 | |
| 3828 %} | |
| 3829 | |
| 3830 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3831 //----------Operand Attributes------------------------------------------------- | |
| 3832 op_attrib op_cost(0); // Required cost attribute | |
| 3833 | |
| 3834 //----------Instruction Attributes--------------------------------------------- | |
| 3835 ins_attrib ins_cost(100); // Required cost attribute | |
| 3836 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3837 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3838 // non-matching short branch variant of some | |
| 3839 // long branch? | |
| 3840 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3841 // specifies the alignment that some part of the instruction (not | |
| 3842 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3843 // function must be provided for the instruction | |
| 3844 | |
| 3845 //----------OPERANDS----------------------------------------------------------- | |
| 3846 // Operand definitions must precede instruction definitions for correct parsing | |
| 3847 // in the ADLC because operands constitute user defined types which are used in | |
| 3848 // instruction definitions. | |
| 3849 | |
| 3850 //----------Simple Operands---------------------------------------------------- | |
| 3851 // Immediate Operands | |
| 3852 // Integer Immediate | |
| 3853 operand immI() %{ | |
| 3854 match(ConI); | |
| 3855 | |
| 3856 op_cost(10); | |
| 3857 format %{ %} | |
| 3858 interface(CONST_INTER); | |
| 3859 %} | |
| 3860 | |
| 3861 // Constant for test vs zero | |
| 3862 operand immI0() %{ | |
| 3863 predicate(n->get_int() == 0); | |
| 3864 match(ConI); | |
| 3865 | |
| 3866 op_cost(0); | |
| 3867 format %{ %} | |
| 3868 interface(CONST_INTER); | |
| 3869 %} | |
| 3870 | |
| 3871 // Constant for increment | |
| 3872 operand immI1() %{ | |
| 3873 predicate(n->get_int() == 1); | |
| 3874 match(ConI); | |
| 3875 | |
| 3876 op_cost(0); | |
| 3877 format %{ %} | |
| 3878 interface(CONST_INTER); | |
| 3879 %} | |
| 3880 | |
| 3881 // Constant for decrement | |
| 3882 operand immI_M1() %{ | |
| 3883 predicate(n->get_int() == -1); | |
| 3884 match(ConI); | |
| 3885 | |
| 3886 op_cost(0); | |
| 3887 format %{ %} | |
| 3888 interface(CONST_INTER); | |
| 3889 %} | |
| 3890 | |
| 3891 // Valid scale values for addressing modes | |
| 3892 operand immI2() %{ | |
| 3893 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3894 match(ConI); | |
| 3895 | |
| 3896 format %{ %} | |
| 3897 interface(CONST_INTER); | |
| 3898 %} | |
| 3899 | |
| 3900 operand immI8() %{ | |
| 3901 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3902 match(ConI); | |
| 3903 | |
| 3904 op_cost(5); | |
| 3905 format %{ %} | |
| 3906 interface(CONST_INTER); | |
| 3907 %} | |
| 3908 | |
| 3909 operand immI16() %{ | |
| 3910 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3911 match(ConI); | |
| 3912 | |
| 3913 op_cost(10); | |
| 3914 format %{ %} | |
| 3915 interface(CONST_INTER); | |
| 3916 %} | |
| 3917 | |
| 3918 // Constant for long shifts | |
| 3919 operand immI_32() %{ | |
| 3920 predicate( n->get_int() == 32 ); | |
| 3921 match(ConI); | |
| 3922 | |
| 3923 op_cost(0); | |
| 3924 format %{ %} | |
| 3925 interface(CONST_INTER); | |
| 3926 %} | |
| 3927 | |
| 3928 operand immI_1_31() %{ | |
| 3929 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3930 match(ConI); | |
| 3931 | |
| 3932 op_cost(0); | |
| 3933 format %{ %} | |
| 3934 interface(CONST_INTER); | |
| 3935 %} | |
| 3936 | |
| 3937 operand immI_32_63() %{ | |
| 3938 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3939 match(ConI); | |
| 3940 op_cost(0); | |
| 3941 | |
| 3942 format %{ %} | |
| 3943 interface(CONST_INTER); | |
| 3944 %} | |
| 3945 | |
| 219 | 3946 operand immI_1() %{ |
| 3947 predicate( n->get_int() == 1 ); | |
| 3948 match(ConI); | |
| 3949 | |
| 3950 op_cost(0); | |
| 3951 format %{ %} | |
| 3952 interface(CONST_INTER); | |
| 3953 %} | |
| 3954 | |
| 3955 operand immI_2() %{ | |
| 3956 predicate( n->get_int() == 2 ); | |
| 3957 match(ConI); | |
| 3958 | |
| 3959 op_cost(0); | |
| 3960 format %{ %} | |
| 3961 interface(CONST_INTER); | |
| 3962 %} | |
| 3963 | |
| 3964 operand immI_3() %{ | |
| 3965 predicate( n->get_int() == 3 ); | |
| 3966 match(ConI); | |
| 3967 | |
| 3968 op_cost(0); | |
| 3969 format %{ %} | |
| 3970 interface(CONST_INTER); | |
| 3971 %} | |
| 3972 | |
| 0 | 3973 // Pointer Immediate |
| 3974 operand immP() %{ | |
| 3975 match(ConP); | |
| 3976 | |
| 3977 op_cost(10); | |
| 3978 format %{ %} | |
| 3979 interface(CONST_INTER); | |
| 3980 %} | |
| 3981 | |
| 3982 // NULL Pointer Immediate | |
| 3983 operand immP0() %{ | |
| 3984 predicate( n->get_ptr() == 0 ); | |
| 3985 match(ConP); | |
| 3986 op_cost(0); | |
| 3987 | |
| 3988 format %{ %} | |
| 3989 interface(CONST_INTER); | |
| 3990 %} | |
| 3991 | |
| 3992 // Long Immediate | |
| 3993 operand immL() %{ | |
| 3994 match(ConL); | |
| 3995 | |
| 3996 op_cost(20); | |
| 3997 format %{ %} | |
| 3998 interface(CONST_INTER); | |
| 3999 %} | |
| 4000 | |
| 4001 // Long Immediate zero | |
| 4002 operand immL0() %{ | |
| 4003 predicate( n->get_long() == 0L ); | |
| 4004 match(ConL); | |
| 4005 op_cost(0); | |
| 4006 | |
| 4007 format %{ %} | |
| 4008 interface(CONST_INTER); | |
| 4009 %} | |
| 4010 | |
| 403 | 4011 // Long Immediate zero |
| 4012 operand immL_M1() %{ | |
| 4013 predicate( n->get_long() == -1L ); | |
| 4014 match(ConL); | |
| 4015 op_cost(0); | |
| 4016 | |
| 4017 format %{ %} | |
| 4018 interface(CONST_INTER); | |
| 4019 %} | |
| 4020 | |
| 0 | 4021 // Long immediate from 0 to 127. |
| 4022 // Used for a shorter form of long mul by 10. | |
| 4023 operand immL_127() %{ | |
| 4024 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 4025 match(ConL); | |
| 4026 op_cost(0); | |
| 4027 | |
| 4028 format %{ %} | |
| 4029 interface(CONST_INTER); | |
| 4030 %} | |
| 4031 | |
| 4032 // Long Immediate: low 32-bit mask | |
| 4033 operand immL_32bits() %{ | |
| 4034 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4035 match(ConL); | |
| 4036 op_cost(0); | |
| 4037 | |
| 4038 format %{ %} | |
| 4039 interface(CONST_INTER); | |
| 4040 %} | |
| 4041 | |
| 4042 // Long Immediate: low 32-bit mask | |
| 4043 operand immL32() %{ | |
| 4044 predicate(n->get_long() == (int)(n->get_long())); | |
| 4045 match(ConL); | |
| 4046 op_cost(20); | |
| 4047 | |
| 4048 format %{ %} | |
| 4049 interface(CONST_INTER); | |
| 4050 %} | |
| 4051 | |
| 4052 //Double Immediate zero | |
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4053 operand immDPR0() %{ |
| 0 | 4054 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4055 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4056 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4057 match(ConD); | |
| 4058 | |
| 4059 op_cost(5); | |
| 4060 format %{ %} | |
| 4061 interface(CONST_INTER); | |
| 4062 %} | |
| 4063 | |
| 2008 | 4064 // Double Immediate one |
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4065 operand immDPR1() %{ |
| 0 | 4066 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 4067 match(ConD); | |
| 4068 | |
| 4069 op_cost(5); | |
| 4070 format %{ %} | |
| 4071 interface(CONST_INTER); | |
| 4072 %} | |
| 4073 | |
| 4074 // Double Immediate | |
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4075 operand immDPR() %{ |
| 0 | 4076 predicate(UseSSE<=1); |
| 4077 match(ConD); | |
| 4078 | |
| 4079 op_cost(5); | |
| 4080 format %{ %} | |
| 4081 interface(CONST_INTER); | |
| 4082 %} | |
| 4083 | |
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4084 operand immD() %{ |
| 0 | 4085 predicate(UseSSE>=2); |
| 4086 match(ConD); | |
| 4087 | |
| 4088 op_cost(5); | |
| 4089 format %{ %} | |
| 4090 interface(CONST_INTER); | |
| 4091 %} | |
| 4092 | |
| 4093 // Double Immediate zero | |
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4094 operand immD0() %{ |
| 0 | 4095 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4096 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4097 // compare equal to -0.0. | |
| 4098 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4099 match(ConD); | |
| 4100 | |
| 4101 format %{ %} | |
| 4102 interface(CONST_INTER); | |
| 4103 %} | |
| 4104 | |
| 4105 // Float Immediate zero | |
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4106 operand immFPR0() %{ |
| 2008 | 4107 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 4108 match(ConF); | |
| 4109 | |
| 4110 op_cost(5); | |
| 4111 format %{ %} | |
| 4112 interface(CONST_INTER); | |
| 4113 %} | |
| 4114 | |
| 4115 // Float Immediate one | |
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4116 operand immFPR1() %{ |
| 2008 | 4117 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 4118 match(ConF); |
| 4119 | |
| 4120 op_cost(5); | |
| 4121 format %{ %} | |
| 4122 interface(CONST_INTER); | |
| 4123 %} | |
| 4124 | |
| 4125 // Float Immediate | |
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4126 operand immFPR() %{ |
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4127 predicate( UseSSE == 0 ); |
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4128 match(ConF); |
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4129 |
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4130 op_cost(5); |
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4131 format %{ %} |
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4132 interface(CONST_INTER); |
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4133 %} |
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4134 |
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4135 // Float Immediate |
| 0 | 4136 operand immF() %{ |
| 4137 predicate(UseSSE >= 1); | |
| 4138 match(ConF); | |
| 4139 | |
| 4140 op_cost(5); | |
| 4141 format %{ %} | |
| 4142 interface(CONST_INTER); | |
| 4143 %} | |
| 4144 | |
| 4145 // Float Immediate zero. Zero and not -0.0 | |
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4146 operand immF0() %{ |
| 0 | 4147 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 4148 match(ConF); | |
| 4149 | |
| 4150 op_cost(5); | |
| 4151 format %{ %} | |
| 4152 interface(CONST_INTER); | |
| 4153 %} | |
| 4154 | |
| 4155 // Immediates for special shifts (sign extend) | |
| 4156 | |
| 4157 // Constants for increment | |
| 4158 operand immI_16() %{ | |
| 4159 predicate( n->get_int() == 16 ); | |
| 4160 match(ConI); | |
| 4161 | |
| 4162 format %{ %} | |
| 4163 interface(CONST_INTER); | |
| 4164 %} | |
| 4165 | |
| 4166 operand immI_24() %{ | |
| 4167 predicate( n->get_int() == 24 ); | |
| 4168 match(ConI); | |
| 4169 | |
| 4170 format %{ %} | |
| 4171 interface(CONST_INTER); | |
| 4172 %} | |
| 4173 | |
| 4174 // Constant for byte-wide masking | |
| 4175 operand immI_255() %{ | |
| 4176 predicate( n->get_int() == 255 ); | |
| 4177 match(ConI); | |
| 4178 | |
| 4179 format %{ %} | |
| 4180 interface(CONST_INTER); | |
| 4181 %} | |
| 4182 | |
| 785 | 4183 // Constant for short-wide masking |
| 4184 operand immI_65535() %{ | |
| 4185 predicate(n->get_int() == 65535); | |
| 4186 match(ConI); | |
| 4187 | |
| 4188 format %{ %} | |
| 4189 interface(CONST_INTER); | |
| 4190 %} | |
| 4191 | |
| 0 | 4192 // Register Operands |
| 4193 // Integer Register | |
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4194 operand rRegI() %{ |
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4195 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4196 match(RegI); |
| 4197 match(xRegI); | |
| 4198 match(eAXRegI); | |
| 4199 match(eBXRegI); | |
| 4200 match(eCXRegI); | |
| 4201 match(eDXRegI); | |
| 4202 match(eDIRegI); | |
| 4203 match(eSIRegI); | |
| 4204 | |
| 4205 format %{ %} | |
| 4206 interface(REG_INTER); | |
| 4207 %} | |
| 4208 | |
| 4209 // Subset of Integer Register | |
|
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4210 operand xRegI(rRegI reg) %{ |
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4211 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 4212 match(reg); |
| 4213 match(eAXRegI); | |
| 4214 match(eBXRegI); | |
| 4215 match(eCXRegI); | |
| 4216 match(eDXRegI); | |
| 4217 | |
| 4218 format %{ %} | |
| 4219 interface(REG_INTER); | |
| 4220 %} | |
| 4221 | |
| 4222 // Special Registers | |
| 4223 operand eAXRegI(xRegI reg) %{ | |
| 4224 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4225 match(reg); | |
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4226 match(rRegI); |
| 0 | 4227 |
| 4228 format %{ "EAX" %} | |
| 4229 interface(REG_INTER); | |
| 4230 %} | |
| 4231 | |
| 4232 // Special Registers | |
| 4233 operand eBXRegI(xRegI reg) %{ | |
| 4234 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4235 match(reg); | |
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4236 match(rRegI); |
| 0 | 4237 |
| 4238 format %{ "EBX" %} | |
| 4239 interface(REG_INTER); | |
| 4240 %} | |
| 4241 | |
| 4242 operand eCXRegI(xRegI reg) %{ | |
| 4243 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4244 match(reg); | |
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4245 match(rRegI); |
| 0 | 4246 |
| 4247 format %{ "ECX" %} | |
| 4248 interface(REG_INTER); | |
| 4249 %} | |
| 4250 | |
| 4251 operand eDXRegI(xRegI reg) %{ | |
| 4252 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4253 match(reg); | |
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4254 match(rRegI); |
| 0 | 4255 |
| 4256 format %{ "EDX" %} | |
| 4257 interface(REG_INTER); | |
| 4258 %} | |
| 4259 | |
| 4260 operand eDIRegI(xRegI reg) %{ | |
| 4261 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4262 match(reg); | |
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4263 match(rRegI); |
| 0 | 4264 |
| 4265 format %{ "EDI" %} | |
| 4266 interface(REG_INTER); | |
| 4267 %} | |
| 4268 | |
| 4269 operand naxRegI() %{ | |
| 4270 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4271 match(RegI); | |
| 4272 match(eCXRegI); | |
| 4273 match(eDXRegI); | |
| 4274 match(eSIRegI); | |
| 4275 match(eDIRegI); | |
| 4276 | |
| 4277 format %{ %} | |
| 4278 interface(REG_INTER); | |
| 4279 %} | |
| 4280 | |
| 4281 operand nadxRegI() %{ | |
| 4282 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4283 match(RegI); | |
| 4284 match(eBXRegI); | |
| 4285 match(eCXRegI); | |
| 4286 match(eSIRegI); | |
| 4287 match(eDIRegI); | |
| 4288 | |
| 4289 format %{ %} | |
| 4290 interface(REG_INTER); | |
| 4291 %} | |
| 4292 | |
| 4293 operand ncxRegI() %{ | |
| 4294 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4295 match(RegI); | |
| 4296 match(eAXRegI); | |
| 4297 match(eDXRegI); | |
| 4298 match(eSIRegI); | |
| 4299 match(eDIRegI); | |
| 4300 | |
| 4301 format %{ %} | |
| 4302 interface(REG_INTER); | |
| 4303 %} | |
| 4304 | |
| 4305 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4306 // // | |
| 4307 operand eSIRegI(xRegI reg) %{ | |
| 4308 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4309 match(reg); | |
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4310 match(rRegI); |
| 0 | 4311 |
| 4312 format %{ "ESI" %} | |
| 4313 interface(REG_INTER); | |
| 4314 %} | |
| 4315 | |
| 4316 // Pointer Register | |
| 4317 operand anyRegP() %{ | |
| 4318 constraint(ALLOC_IN_RC(any_reg)); | |
| 4319 match(RegP); | |
| 4320 match(eAXRegP); | |
| 4321 match(eBXRegP); | |
| 4322 match(eCXRegP); | |
| 4323 match(eDIRegP); | |
| 4324 match(eRegP); | |
| 4325 | |
| 4326 format %{ %} | |
| 4327 interface(REG_INTER); | |
| 4328 %} | |
| 4329 | |
| 4330 operand eRegP() %{ | |
|
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4331 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4332 match(RegP); |
| 4333 match(eAXRegP); | |
| 4334 match(eBXRegP); | |
| 4335 match(eCXRegP); | |
| 4336 match(eDIRegP); | |
| 4337 | |
| 4338 format %{ %} | |
| 4339 interface(REG_INTER); | |
| 4340 %} | |
| 4341 | |
| 4342 // On windows95, EBP is not safe to use for implicit null tests. | |
| 4343 operand eRegP_no_EBP() %{ | |
|
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4344 constraint(ALLOC_IN_RC(int_reg_no_rbp)); |
| 0 | 4345 match(RegP); |
| 4346 match(eAXRegP); | |
| 4347 match(eBXRegP); | |
| 4348 match(eCXRegP); | |
| 4349 match(eDIRegP); | |
| 4350 | |
| 4351 op_cost(100); | |
| 4352 format %{ %} | |
| 4353 interface(REG_INTER); | |
| 4354 %} | |
| 4355 | |
| 4356 operand naxRegP() %{ | |
| 4357 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4358 match(RegP); | |
| 4359 match(eBXRegP); | |
| 4360 match(eDXRegP); | |
| 4361 match(eCXRegP); | |
| 4362 match(eSIRegP); | |
| 4363 match(eDIRegP); | |
| 4364 | |
| 4365 format %{ %} | |
| 4366 interface(REG_INTER); | |
| 4367 %} | |
| 4368 | |
| 4369 operand nabxRegP() %{ | |
| 4370 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 4371 match(RegP); | |
| 4372 match(eCXRegP); | |
| 4373 match(eDXRegP); | |
| 4374 match(eSIRegP); | |
| 4375 match(eDIRegP); | |
| 4376 | |
| 4377 format %{ %} | |
| 4378 interface(REG_INTER); | |
| 4379 %} | |
| 4380 | |
| 4381 operand pRegP() %{ | |
| 4382 constraint(ALLOC_IN_RC(p_reg)); | |
| 4383 match(RegP); | |
| 4384 match(eBXRegP); | |
| 4385 match(eDXRegP); | |
| 4386 match(eSIRegP); | |
| 4387 match(eDIRegP); | |
| 4388 | |
| 4389 format %{ %} | |
| 4390 interface(REG_INTER); | |
| 4391 %} | |
| 4392 | |
| 4393 // Special Registers | |
| 4394 // Return a pointer value | |
| 4395 operand eAXRegP(eRegP reg) %{ | |
| 4396 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4397 match(reg); | |
| 4398 format %{ "EAX" %} | |
| 4399 interface(REG_INTER); | |
| 4400 %} | |
| 4401 | |
| 4402 // Used in AtomicAdd | |
| 4403 operand eBXRegP(eRegP reg) %{ | |
| 4404 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4405 match(reg); | |
| 4406 format %{ "EBX" %} | |
| 4407 interface(REG_INTER); | |
| 4408 %} | |
| 4409 | |
| 4410 // Tail-call (interprocedural jump) to interpreter | |
| 4411 operand eCXRegP(eRegP reg) %{ | |
| 4412 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4413 match(reg); | |
| 4414 format %{ "ECX" %} | |
| 4415 interface(REG_INTER); | |
| 4416 %} | |
| 4417 | |
| 4418 operand eSIRegP(eRegP reg) %{ | |
| 4419 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4420 match(reg); | |
| 4421 format %{ "ESI" %} | |
| 4422 interface(REG_INTER); | |
| 4423 %} | |
| 4424 | |
| 4425 // Used in rep stosw | |
| 4426 operand eDIRegP(eRegP reg) %{ | |
| 4427 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4428 match(reg); | |
| 4429 format %{ "EDI" %} | |
| 4430 interface(REG_INTER); | |
| 4431 %} | |
| 4432 | |
| 4433 operand eBPRegP() %{ | |
| 4434 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 4435 match(RegP); | |
| 4436 format %{ "EBP" %} | |
| 4437 interface(REG_INTER); | |
| 4438 %} | |
| 4439 | |
| 4440 operand eRegL() %{ | |
| 4441 constraint(ALLOC_IN_RC(long_reg)); | |
| 4442 match(RegL); | |
| 4443 match(eADXRegL); | |
| 4444 | |
| 4445 format %{ %} | |
| 4446 interface(REG_INTER); | |
| 4447 %} | |
| 4448 | |
| 4449 operand eADXRegL( eRegL reg ) %{ | |
| 4450 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4451 match(reg); | |
| 4452 | |
| 4453 format %{ "EDX:EAX" %} | |
| 4454 interface(REG_INTER); | |
| 4455 %} | |
| 4456 | |
| 4457 operand eBCXRegL( eRegL reg ) %{ | |
| 4458 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 4459 match(reg); | |
| 4460 | |
| 4461 format %{ "EBX:ECX" %} | |
| 4462 interface(REG_INTER); | |
| 4463 %} | |
| 4464 | |
| 4465 // Special case for integer high multiply | |
| 4466 operand eADXRegL_low_only() %{ | |
| 4467 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4468 match(RegL); | |
| 4469 | |
| 4470 format %{ "EAX" %} | |
| 4471 interface(REG_INTER); | |
| 4472 %} | |
| 4473 | |
| 4474 // Flags register, used as output of compare instructions | |
| 4475 operand eFlagsReg() %{ | |
| 4476 constraint(ALLOC_IN_RC(int_flags)); | |
| 4477 match(RegFlags); | |
| 4478 | |
| 4479 format %{ "EFLAGS" %} | |
| 4480 interface(REG_INTER); | |
| 4481 %} | |
| 4482 | |
| 4483 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4484 operand eFlagsRegU() %{ | |
| 4485 constraint(ALLOC_IN_RC(int_flags)); | |
| 4486 match(RegFlags); | |
| 4487 | |
| 4488 format %{ "EFLAGS_U" %} | |
| 4489 interface(REG_INTER); | |
| 4490 %} | |
| 4491 | |
|
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|
4492 operand eFlagsRegUCF() %{ |
|
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|
4493 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
4494 match(RegFlags); |
|
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|
4495 predicate(false); |
|
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|
4496 |
|
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|
4497 format %{ "EFLAGS_U_CF" %} |
|
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|
4498 interface(REG_INTER); |
|
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|
4499 %} |
|
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|
4500 |
| 0 | 4501 // Condition Code Register used by long compare |
| 4502 operand flagsReg_long_LTGE() %{ | |
| 4503 constraint(ALLOC_IN_RC(int_flags)); | |
| 4504 match(RegFlags); | |
| 4505 format %{ "FLAGS_LTGE" %} | |
| 4506 interface(REG_INTER); | |
| 4507 %} | |
| 4508 operand flagsReg_long_EQNE() %{ | |
| 4509 constraint(ALLOC_IN_RC(int_flags)); | |
| 4510 match(RegFlags); | |
| 4511 format %{ "FLAGS_EQNE" %} | |
| 4512 interface(REG_INTER); | |
| 4513 %} | |
| 4514 operand flagsReg_long_LEGT() %{ | |
| 4515 constraint(ALLOC_IN_RC(int_flags)); | |
| 4516 match(RegFlags); | |
| 4517 format %{ "FLAGS_LEGT" %} | |
| 4518 interface(REG_INTER); | |
| 4519 %} | |
| 4520 | |
| 4521 // Float register operands | |
|
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|
4522 operand regDPR() %{ |
| 0 | 4523 predicate( UseSSE < 2 ); |
|
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|
4524 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 4525 match(RegD); |
| 4526 match(regDPR1); | |
| 4527 match(regDPR2); | |
| 4528 format %{ %} | |
| 4529 interface(REG_INTER); | |
| 4530 %} | |
| 4531 | |
|
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|
4532 operand regDPR1(regDPR reg) %{ |
| 0 | 4533 predicate( UseSSE < 2 ); |
|
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|
4534 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 4535 match(reg); |
| 4536 format %{ "FPR1" %} | |
| 4537 interface(REG_INTER); | |
| 4538 %} | |
| 4539 | |
|
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|
4540 operand regDPR2(regDPR reg) %{ |
| 0 | 4541 predicate( UseSSE < 2 ); |
|
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|
4542 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 4543 match(reg); |
| 4544 format %{ "FPR2" %} | |
| 4545 interface(REG_INTER); | |
| 4546 %} | |
| 4547 | |
|
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|
4548 operand regnotDPR1(regDPR reg) %{ |
| 0 | 4549 predicate( UseSSE < 2 ); |
|
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|
4550 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 4551 match(reg); |
| 4552 format %{ %} | |
| 4553 interface(REG_INTER); | |
| 4554 %} | |
| 4555 | |
| 4556 // Float register operands | |
|
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|
4557 operand regFPR() %{ |
| 0 | 4558 predicate( UseSSE < 2 ); |
|
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|
4559 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 4560 match(RegF); |
| 4561 match(regFPR1); | |
| 4562 format %{ %} | |
| 4563 interface(REG_INTER); | |
| 4564 %} | |
| 4565 | |
| 4566 // Float register operands | |
|
4761
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|
4567 operand regFPR1(regFPR reg) %{ |
| 0 | 4568 predicate( UseSSE < 2 ); |
|
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|
4569 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 4570 match(reg); |
| 4571 format %{ "FPR1" %} | |
| 4572 interface(REG_INTER); | |
| 4573 %} | |
| 4574 | |
|
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|
4575 // XMM Float register operands |
|
4761
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|
4576 operand regF() %{ |
| 0 | 4577 predicate( UseSSE>=1 ); |
|
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|
4578 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4579 match(RegF); |
| 4580 format %{ %} | |
| 4581 interface(REG_INTER); | |
| 4582 %} | |
| 4583 | |
|
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|
4584 // XMM Double register operands |
|
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|
4585 operand regD() %{ |
|
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|
4586 predicate( UseSSE>=2 ); |
|
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|
4587 constraint(ALLOC_IN_RC(double_reg)); |
|
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|
4588 match(RegD); |
|
8c92982cbbc4
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|
4589 format %{ %} |
|
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|
4590 interface(REG_INTER); |
|
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|
4591 %} |
|
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|
4592 |
| 0 | 4593 |
| 4594 //----------Memory Operands---------------------------------------------------- | |
| 4595 // Direct Memory Operand | |
| 4596 operand direct(immP addr) %{ | |
| 4597 match(addr); | |
| 4598 | |
| 4599 format %{ "[$addr]" %} | |
| 4600 interface(MEMORY_INTER) %{ | |
| 4601 base(0xFFFFFFFF); | |
| 4602 index(0x4); | |
| 4603 scale(0x0); | |
| 4604 disp($addr); | |
| 4605 %} | |
| 4606 %} | |
| 4607 | |
| 4608 // Indirect Memory Operand | |
| 4609 operand indirect(eRegP reg) %{ | |
|
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|
4610 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4611 match(reg); |
| 4612 | |
| 4613 format %{ "[$reg]" %} | |
| 4614 interface(MEMORY_INTER) %{ | |
| 4615 base($reg); | |
| 4616 index(0x4); | |
| 4617 scale(0x0); | |
| 4618 disp(0x0); | |
| 4619 %} | |
| 4620 %} | |
| 4621 | |
| 4622 // Indirect Memory Plus Short Offset Operand | |
| 4623 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4624 match(AddP reg off); | |
| 4625 | |
| 4626 format %{ "[$reg + $off]" %} | |
| 4627 interface(MEMORY_INTER) %{ | |
| 4628 base($reg); | |
| 4629 index(0x4); | |
| 4630 scale(0x0); | |
| 4631 disp($off); | |
| 4632 %} | |
| 4633 %} | |
| 4634 | |
| 4635 // Indirect Memory Plus Long Offset Operand | |
| 4636 operand indOffset32(eRegP reg, immI off) %{ | |
| 4637 match(AddP reg off); | |
| 4638 | |
| 4639 format %{ "[$reg + $off]" %} | |
| 4640 interface(MEMORY_INTER) %{ | |
| 4641 base($reg); | |
| 4642 index(0x4); | |
| 4643 scale(0x0); | |
| 4644 disp($off); | |
| 4645 %} | |
| 4646 %} | |
| 4647 | |
| 4648 // Indirect Memory Plus Long Offset Operand | |
|
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|
4649 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4650 match(AddP off reg); |
| 4651 | |
| 4652 format %{ "[$reg + $off]" %} | |
| 4653 interface(MEMORY_INTER) %{ | |
| 4654 base($reg); | |
| 4655 index(0x4); | |
| 4656 scale(0x0); | |
| 4657 disp($off); | |
| 4658 %} | |
| 4659 %} | |
| 4660 | |
| 4661 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4662 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4663 match(AddP (AddP reg ireg) off); |
| 4664 | |
| 4665 op_cost(10); | |
| 4666 format %{"[$reg + $off + $ireg]" %} | |
| 4667 interface(MEMORY_INTER) %{ | |
| 4668 base($reg); | |
| 4669 index($ireg); | |
| 4670 scale(0x0); | |
| 4671 disp($off); | |
| 4672 %} | |
| 4673 %} | |
| 4674 | |
| 4675 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4676 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4677 match(AddP reg ireg); |
| 4678 | |
| 4679 op_cost(10); | |
| 4680 format %{"[$reg + $ireg]" %} | |
| 4681 interface(MEMORY_INTER) %{ | |
| 4682 base($reg); | |
| 4683 index($ireg); | |
| 4684 scale(0x0); | |
| 4685 disp(0x0); | |
| 4686 %} | |
| 4687 %} | |
| 4688 | |
| 4689 // // ------------------------------------------------------------------------- | |
| 4690 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4691 // // ------------------------------------------------------------------------- | |
| 4692 // // Scaled Memory Operands | |
| 4693 // // Indirect Memory Times Scale Plus Offset Operand | |
|
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|
4694 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4695 // match(AddP off (LShiftI ireg scale)); |
| 4696 // | |
| 4697 // op_cost(10); | |
| 4698 // format %{"[$off + $ireg << $scale]" %} | |
| 4699 // interface(MEMORY_INTER) %{ | |
| 4700 // base(0x4); | |
| 4701 // index($ireg); | |
| 4702 // scale($scale); | |
| 4703 // disp($off); | |
| 4704 // %} | |
| 4705 // %} | |
| 4706 | |
| 4707 // Indirect Memory Times Scale Plus Index Register | |
|
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|
4708 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4709 match(AddP reg (LShiftI ireg scale)); |
| 4710 | |
| 4711 op_cost(10); | |
| 4712 format %{"[$reg + $ireg << $scale]" %} | |
| 4713 interface(MEMORY_INTER) %{ | |
| 4714 base($reg); | |
| 4715 index($ireg); | |
| 4716 scale($scale); | |
| 4717 disp(0x0); | |
| 4718 %} | |
| 4719 %} | |
| 4720 | |
| 4721 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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|
4722 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4723 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4724 | |
| 4725 op_cost(10); | |
| 4726 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4727 interface(MEMORY_INTER) %{ | |
| 4728 base($reg); | |
| 4729 index($ireg); | |
| 4730 scale($scale); | |
| 4731 disp($off); | |
| 4732 %} | |
| 4733 %} | |
| 4734 | |
| 4735 //----------Load Long Memory Operands------------------------------------------ | |
| 4736 // The load-long idiom will use it's address expression again after loading | |
| 4737 // the first word of the long. If the load-long destination overlaps with | |
| 4738 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4739 // from a clobbered address. Fix this by requiring that load-long use | |
| 4740 // address registers that do not overlap with the load-long target. | |
| 4741 | |
| 4742 // load-long support | |
| 4743 operand load_long_RegP() %{ | |
| 4744 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4745 match(RegP); | |
| 4746 match(eSIRegP); | |
| 4747 op_cost(100); | |
| 4748 format %{ %} | |
| 4749 interface(REG_INTER); | |
| 4750 %} | |
| 4751 | |
| 4752 // Indirect Memory Operand Long | |
| 4753 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4754 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4755 match(reg); | |
| 4756 | |
| 4757 format %{ "[$reg]" %} | |
| 4758 interface(MEMORY_INTER) %{ | |
| 4759 base($reg); | |
| 4760 index(0x4); | |
| 4761 scale(0x0); | |
| 4762 disp(0x0); | |
| 4763 %} | |
| 4764 %} | |
| 4765 | |
| 4766 // Indirect Memory Plus Long Offset Operand | |
| 4767 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4768 match(AddP reg off); | |
| 4769 | |
| 4770 format %{ "[$reg + $off]" %} | |
| 4771 interface(MEMORY_INTER) %{ | |
| 4772 base($reg); | |
| 4773 index(0x4); | |
| 4774 scale(0x0); | |
| 4775 disp($off); | |
| 4776 %} | |
| 4777 %} | |
| 4778 | |
| 4779 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4780 | |
| 4781 | |
| 4782 //----------Special Memory Operands-------------------------------------------- | |
| 4783 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4784 // values on the stack where a match requires a value to | |
| 4785 // flow through memory. | |
| 4786 operand stackSlotP(sRegP reg) %{ | |
| 4787 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4788 // No match rule because this operand is only generated in matching | |
| 4789 format %{ "[$reg]" %} | |
| 4790 interface(MEMORY_INTER) %{ | |
| 4791 base(0x4); // ESP | |
| 4792 index(0x4); // No Index | |
| 4793 scale(0x0); // No Scale | |
| 4794 disp($reg); // Stack Offset | |
| 4795 %} | |
| 4796 %} | |
| 4797 | |
| 4798 operand stackSlotI(sRegI reg) %{ | |
| 4799 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4800 // No match rule because this operand is only generated in matching | |
| 4801 format %{ "[$reg]" %} | |
| 4802 interface(MEMORY_INTER) %{ | |
| 4803 base(0x4); // ESP | |
| 4804 index(0x4); // No Index | |
| 4805 scale(0x0); // No Scale | |
| 4806 disp($reg); // Stack Offset | |
| 4807 %} | |
| 4808 %} | |
| 4809 | |
| 4810 operand stackSlotF(sRegF reg) %{ | |
| 4811 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4812 // No match rule because this operand is only generated in matching | |
| 4813 format %{ "[$reg]" %} | |
| 4814 interface(MEMORY_INTER) %{ | |
| 4815 base(0x4); // ESP | |
| 4816 index(0x4); // No Index | |
| 4817 scale(0x0); // No Scale | |
| 4818 disp($reg); // Stack Offset | |
| 4819 %} | |
| 4820 %} | |
| 4821 | |
| 4822 operand stackSlotD(sRegD reg) %{ | |
| 4823 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4824 // No match rule because this operand is only generated in matching | |
| 4825 format %{ "[$reg]" %} | |
| 4826 interface(MEMORY_INTER) %{ | |
| 4827 base(0x4); // ESP | |
| 4828 index(0x4); // No Index | |
| 4829 scale(0x0); // No Scale | |
| 4830 disp($reg); // Stack Offset | |
| 4831 %} | |
| 4832 %} | |
| 4833 | |
| 4834 operand stackSlotL(sRegL reg) %{ | |
| 4835 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4836 // No match rule because this operand is only generated in matching | |
| 4837 format %{ "[$reg]" %} | |
| 4838 interface(MEMORY_INTER) %{ | |
| 4839 base(0x4); // ESP | |
| 4840 index(0x4); // No Index | |
| 4841 scale(0x0); // No Scale | |
| 4842 disp($reg); // Stack Offset | |
| 4843 %} | |
| 4844 %} | |
| 4845 | |
| 4846 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4847 // Indirect Memory Operand | |
| 4848 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4849 %{ | |
|
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4850 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4851 match(reg); |
| 4852 | |
| 4853 op_cost(100); | |
| 4854 format %{ "[$reg]" %} | |
| 4855 interface(MEMORY_INTER) %{ | |
| 4856 base($reg); | |
| 4857 index(0x4); | |
| 4858 scale(0x0); | |
| 4859 disp(0x0); | |
| 4860 %} | |
| 4861 %} | |
| 4862 | |
| 4863 // Indirect Memory Plus Short Offset Operand | |
| 4864 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4865 %{ | |
| 4866 match(AddP reg off); | |
| 4867 | |
| 4868 op_cost(100); | |
| 4869 format %{ "[$reg + $off]" %} | |
| 4870 interface(MEMORY_INTER) %{ | |
| 4871 base($reg); | |
| 4872 index(0x4); | |
| 4873 scale(0x0); | |
| 4874 disp($off); | |
| 4875 %} | |
| 4876 %} | |
| 4877 | |
| 4878 // Indirect Memory Plus Long Offset Operand | |
| 4879 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4880 %{ | |
| 4881 match(AddP reg off); | |
| 4882 | |
| 4883 op_cost(100); | |
| 4884 format %{ "[$reg + $off]" %} | |
| 4885 interface(MEMORY_INTER) %{ | |
| 4886 base($reg); | |
| 4887 index(0x4); | |
| 4888 scale(0x0); | |
| 4889 disp($off); | |
| 4890 %} | |
| 4891 %} | |
| 4892 | |
| 4893 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4894 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4895 %{ |
| 4896 match(AddP (AddP reg ireg) off); | |
| 4897 | |
| 4898 op_cost(100); | |
| 4899 format %{"[$reg + $off + $ireg]" %} | |
| 4900 interface(MEMORY_INTER) %{ | |
| 4901 base($reg); | |
| 4902 index($ireg); | |
| 4903 scale(0x0); | |
| 4904 disp($off); | |
| 4905 %} | |
| 4906 %} | |
| 4907 | |
| 4908 // Indirect Memory Times Scale Plus Index Register | |
|
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4909 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4910 %{ |
| 4911 match(AddP reg (LShiftI ireg scale)); | |
| 4912 | |
| 4913 op_cost(100); | |
| 4914 format %{"[$reg + $ireg << $scale]" %} | |
| 4915 interface(MEMORY_INTER) %{ | |
| 4916 base($reg); | |
| 4917 index($ireg); | |
| 4918 scale($scale); | |
| 4919 disp(0x0); | |
| 4920 %} | |
| 4921 %} | |
| 4922 | |
| 4923 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4924 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4925 %{ |
| 4926 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4927 | |
| 4928 op_cost(100); | |
| 4929 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4930 interface(MEMORY_INTER) %{ | |
| 4931 base($reg); | |
| 4932 index($ireg); | |
| 4933 scale($scale); | |
| 4934 disp($off); | |
| 4935 %} | |
| 4936 %} | |
| 4937 | |
| 4938 //----------Conditional Branch Operands---------------------------------------- | |
| 4939 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4940 // the following set of codes: | |
| 4941 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4942 // | |
| 4943 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4944 // by the comparison instruction that sets a condition code flags register. | |
| 4945 // That result is represented by a flags operand whose subtype is appropriate | |
| 4946 // to the unsignedness (etc.) of the comparison. | |
| 4947 // | |
| 4948 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4949 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4950 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4951 | |
| 4952 // Comparision Code | |
| 4953 operand cmpOp() %{ | |
| 4954 match(Bool); | |
| 4955 | |
| 4956 format %{ "" %} | |
| 4957 interface(COND_INTER) %{ | |
|
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4958 equal(0x4, "e"); |
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4959 not_equal(0x5, "ne"); |
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4960 less(0xC, "l"); |
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4961 greater_equal(0xD, "ge"); |
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4962 less_equal(0xE, "le"); |
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4963 greater(0xF, "g"); |
| 0 | 4964 %} |
| 4965 %} | |
| 4966 | |
| 4967 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4968 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4969 // C0 and C3 are turned into Carry & Zero flags. | |
| 4970 operand cmpOpU() %{ | |
| 4971 match(Bool); | |
| 4972 | |
| 4973 format %{ "" %} | |
| 4974 interface(COND_INTER) %{ | |
|
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4975 equal(0x4, "e"); |
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|
4976 not_equal(0x5, "ne"); |
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4977 less(0x2, "b"); |
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4978 greater_equal(0x3, "nb"); |
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4979 less_equal(0x6, "be"); |
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|
4980 greater(0x7, "nbe"); |
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4981 %} |
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4982 %} |
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|
4983 |
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4984 // Floating comparisons that don't require any fixup for the unordered case |
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4985 operand cmpOpUCF() %{ |
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4986 match(Bool); |
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4987 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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4988 n->as_Bool()->_test._test == BoolTest::ge || |
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4989 n->as_Bool()->_test._test == BoolTest::le || |
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|
4990 n->as_Bool()->_test._test == BoolTest::gt); |
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|
4991 format %{ "" %} |
|
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|
4992 interface(COND_INTER) %{ |
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|
4993 equal(0x4, "e"); |
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4994 not_equal(0x5, "ne"); |
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4995 less(0x2, "b"); |
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4996 greater_equal(0x3, "nb"); |
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4997 less_equal(0x6, "be"); |
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4998 greater(0x7, "nbe"); |
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|
4999 %} |
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5000 %} |
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|
5001 |
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|
5002 |
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5003 // Floating comparisons that can be fixed up with extra conditional jumps |
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5004 operand cmpOpUCF2() %{ |
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5005 match(Bool); |
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5006 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
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5007 n->as_Bool()->_test._test == BoolTest::eq); |
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5008 format %{ "" %} |
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|
5009 interface(COND_INTER) %{ |
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|
5010 equal(0x4, "e"); |
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|
5011 not_equal(0x5, "ne"); |
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5012 less(0x2, "b"); |
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5013 greater_equal(0x3, "nb"); |
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|
5014 less_equal(0x6, "be"); |
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5015 greater(0x7, "nbe"); |
| 0 | 5016 %} |
| 5017 %} | |
| 5018 | |
| 5019 // Comparison Code for FP conditional move | |
| 5020 operand cmpOp_fcmov() %{ | |
| 5021 match(Bool); | |
| 5022 | |
| 5023 format %{ "" %} | |
| 5024 interface(COND_INTER) %{ | |
| 5025 equal (0x0C8); | |
| 5026 not_equal (0x1C8); | |
| 5027 less (0x0C0); | |
| 5028 greater_equal(0x1C0); | |
| 5029 less_equal (0x0D0); | |
| 5030 greater (0x1D0); | |
| 5031 %} | |
| 5032 %} | |
| 5033 | |
| 5034 // Comparision Code used in long compares | |
| 5035 operand cmpOp_commute() %{ | |
| 5036 match(Bool); | |
| 5037 | |
| 5038 format %{ "" %} | |
| 5039 interface(COND_INTER) %{ | |
|
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|
5040 equal(0x4, "e"); |
|
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|
5041 not_equal(0x5, "ne"); |
|
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|
5042 less(0xF, "g"); |
|
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|
5043 greater_equal(0xE, "le"); |
|
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|
5044 less_equal(0xD, "ge"); |
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|
5045 greater(0xC, "l"); |
| 0 | 5046 %} |
| 5047 %} | |
| 5048 | |
| 5049 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5050 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5051 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5052 // instructions for every form of operand when the instruction accepts |
| 5053 // multiple operand types with the same basic encoding and format. The classic | |
| 5054 // case of this is memory operands. | |
| 5055 | |
| 5056 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5057 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5058 | |
| 5059 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5060 // This means some kind of offset is always required and you cannot use | |
| 5061 // an oop as the offset (done when working on static globals). | |
| 5062 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5063 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5064 | |
| 5065 | |
| 5066 //----------PIPELINE----------------------------------------------------------- | |
| 5067 // Rules which define the behavior of the target architectures pipeline. | |
| 5068 pipeline %{ | |
| 5069 | |
| 5070 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5071 attributes %{ | |
| 5072 variable_size_instructions; // Fixed size instructions | |
| 5073 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5074 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5075 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5076 instruction_fetch_units = 1; // of 16 bytes | |
| 5077 | |
| 5078 // List of nop instructions | |
| 5079 nops( MachNop ); | |
| 5080 %} | |
| 5081 | |
| 5082 //----------RESOURCES---------------------------------------------------------- | |
| 5083 // Resources are the functional units available to the machine | |
| 5084 | |
| 5085 // Generic P2/P3 pipeline | |
| 5086 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5087 // 3 instructions decoded per cycle. | |
| 5088 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5089 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5090 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5091 MS0, MS1, MEM = MS0 | MS1, | |
| 5092 BR, FPU, | |
| 5093 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5094 | |
| 5095 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5096 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5097 | |
| 5098 // Generic P2/P3 pipeline | |
| 5099 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5100 | |
| 5101 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5102 // Pipeline Classes describe the stages in which input and output are | |
| 5103 // referenced by the hardware pipeline. | |
| 5104 | |
| 5105 // Naming convention: ialu or fpu | |
| 5106 // Then: _reg | |
| 5107 // Then: _reg if there is a 2nd register | |
| 5108 // Then: _long if it's a pair of instructions implementing a long | |
| 5109 // Then: _fat if it requires the big decoder | |
| 5110 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5111 | |
| 5112 // Integer ALU reg operation | |
|
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5113 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 5114 single_instruction; |
| 5115 dst : S4(write); | |
| 5116 dst : S3(read); | |
| 5117 DECODE : S0; // any decoder | |
| 5118 ALU : S3; // any alu | |
| 5119 %} | |
| 5120 | |
| 5121 // Long ALU reg operation | |
| 5122 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5123 instruction_count(2); | |
| 5124 dst : S4(write); | |
| 5125 dst : S3(read); | |
| 5126 DECODE : S0(2); // any 2 decoders | |
| 5127 ALU : S3(2); // both alus | |
| 5128 %} | |
| 5129 | |
| 5130 // Integer ALU reg operation using big decoder | |
|
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5131 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 5132 single_instruction; |
| 5133 dst : S4(write); | |
| 5134 dst : S3(read); | |
| 5135 D0 : S0; // big decoder only | |
| 5136 ALU : S3; // any alu | |
| 5137 %} | |
| 5138 | |
| 5139 // Long ALU reg operation using big decoder | |
| 5140 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5141 instruction_count(2); | |
| 5142 dst : S4(write); | |
| 5143 dst : S3(read); | |
| 5144 D0 : S0(2); // big decoder only; twice | |
| 5145 ALU : S3(2); // any 2 alus | |
| 5146 %} | |
| 5147 | |
| 5148 // Integer ALU reg-reg operation | |
|
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5149 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 5150 single_instruction; |
| 5151 dst : S4(write); | |
| 5152 src : S3(read); | |
| 5153 DECODE : S0; // any decoder | |
| 5154 ALU : S3; // any alu | |
| 5155 %} | |
| 5156 | |
| 5157 // Long ALU reg-reg operation | |
| 5158 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5159 instruction_count(2); | |
| 5160 dst : S4(write); | |
| 5161 src : S3(read); | |
| 5162 DECODE : S0(2); // any 2 decoders | |
| 5163 ALU : S3(2); // both alus | |
| 5164 %} | |
| 5165 | |
| 5166 // Integer ALU reg-reg operation | |
|
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5167 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 5168 single_instruction; |
| 5169 dst : S4(write); | |
| 5170 src : S3(read); | |
| 5171 D0 : S0; // big decoder only | |
| 5172 ALU : S3; // any alu | |
| 5173 %} | |
| 5174 | |
| 5175 // Long ALU reg-reg operation | |
| 5176 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5177 instruction_count(2); | |
| 5178 dst : S4(write); | |
| 5179 src : S3(read); | |
| 5180 D0 : S0(2); // big decoder only; twice | |
| 5181 ALU : S3(2); // both alus | |
| 5182 %} | |
| 5183 | |
| 5184 // Integer ALU reg-mem operation | |
|
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5185 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 5186 single_instruction; |
| 5187 dst : S5(write); | |
| 5188 mem : S3(read); | |
| 5189 D0 : S0; // big decoder only | |
| 5190 ALU : S4; // any alu | |
| 5191 MEM : S3; // any mem | |
| 5192 %} | |
| 5193 | |
| 5194 // Long ALU reg-mem operation | |
| 5195 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5196 instruction_count(2); | |
| 5197 dst : S5(write); | |
| 5198 mem : S3(read); | |
| 5199 D0 : S0(2); // big decoder only; twice | |
| 5200 ALU : S4(2); // any 2 alus | |
| 5201 MEM : S3(2); // both mems | |
| 5202 %} | |
| 5203 | |
| 5204 // Integer mem operation (prefetch) | |
| 5205 pipe_class ialu_mem(memory mem) | |
| 5206 %{ | |
| 5207 single_instruction; | |
| 5208 mem : S3(read); | |
| 5209 D0 : S0; // big decoder only | |
| 5210 MEM : S3; // any mem | |
| 5211 %} | |
| 5212 | |
| 5213 // Integer Store to Memory | |
|
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5214 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 5215 single_instruction; |
| 5216 mem : S3(read); | |
| 5217 src : S5(read); | |
| 5218 D0 : S0; // big decoder only | |
| 5219 ALU : S4; // any alu | |
| 5220 MEM : S3; | |
| 5221 %} | |
| 5222 | |
| 5223 // Long Store to Memory | |
| 5224 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5225 instruction_count(2); | |
| 5226 mem : S3(read); | |
| 5227 src : S5(read); | |
| 5228 D0 : S0(2); // big decoder only; twice | |
| 5229 ALU : S4(2); // any 2 alus | |
| 5230 MEM : S3(2); // Both mems | |
| 5231 %} | |
| 5232 | |
| 5233 // Integer Store to Memory | |
| 5234 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5235 single_instruction; | |
| 5236 mem : S3(read); | |
| 5237 D0 : S0; // big decoder only | |
| 5238 ALU : S4; // any alu | |
| 5239 MEM : S3; | |
| 5240 %} | |
| 5241 | |
| 5242 // Integer ALU0 reg-reg operation | |
|
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5243 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 5244 single_instruction; |
| 5245 dst : S4(write); | |
| 5246 src : S3(read); | |
| 5247 D0 : S0; // Big decoder only | |
| 5248 ALU0 : S3; // only alu0 | |
| 5249 %} | |
| 5250 | |
| 5251 // Integer ALU0 reg-mem operation | |
|
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5252 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 5253 single_instruction; |
| 5254 dst : S5(write); | |
| 5255 mem : S3(read); | |
| 5256 D0 : S0; // big decoder only | |
| 5257 ALU0 : S4; // ALU0 only | |
| 5258 MEM : S3; // any mem | |
| 5259 %} | |
| 5260 | |
| 5261 // Integer ALU reg-reg operation | |
|
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5262 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 5263 single_instruction; |
| 5264 cr : S4(write); | |
| 5265 src1 : S3(read); | |
| 5266 src2 : S3(read); | |
| 5267 DECODE : S0; // any decoder | |
| 5268 ALU : S3; // any alu | |
| 5269 %} | |
| 5270 | |
| 5271 // Integer ALU reg-imm operation | |
|
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5272 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 5273 single_instruction; |
| 5274 cr : S4(write); | |
| 5275 src1 : S3(read); | |
| 5276 DECODE : S0; // any decoder | |
| 5277 ALU : S3; // any alu | |
| 5278 %} | |
| 5279 | |
| 5280 // Integer ALU reg-mem operation | |
|
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5281 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 5282 single_instruction; |
| 5283 cr : S4(write); | |
| 5284 src1 : S3(read); | |
| 5285 src2 : S3(read); | |
| 5286 D0 : S0; // big decoder only | |
| 5287 ALU : S4; // any alu | |
| 5288 MEM : S3; | |
| 5289 %} | |
| 5290 | |
| 5291 // Conditional move reg-reg | |
|
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5292 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 5293 instruction_count(4); |
| 5294 y : S4(read); | |
| 5295 q : S3(read); | |
| 5296 p : S3(read); | |
| 5297 DECODE : S0(4); // any decoder | |
| 5298 %} | |
| 5299 | |
| 5300 // Conditional move reg-reg | |
|
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5301 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 5302 single_instruction; |
| 5303 dst : S4(write); | |
| 5304 src : S3(read); | |
| 5305 cr : S3(read); | |
| 5306 DECODE : S0; // any decoder | |
| 5307 %} | |
| 5308 | |
| 5309 // Conditional move reg-mem | |
|
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5310 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 5311 single_instruction; |
| 5312 dst : S4(write); | |
| 5313 src : S3(read); | |
| 5314 cr : S3(read); | |
| 5315 DECODE : S0; // any decoder | |
| 5316 MEM : S3; | |
| 5317 %} | |
| 5318 | |
| 5319 // Conditional move reg-reg long | |
| 5320 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 5321 single_instruction; | |
| 5322 dst : S4(write); | |
| 5323 src : S3(read); | |
| 5324 cr : S3(read); | |
| 5325 DECODE : S0(2); // any 2 decoders | |
| 5326 %} | |
| 5327 | |
| 5328 // Conditional move double reg-reg | |
|
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5329 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 5330 single_instruction; |
| 5331 dst : S4(write); | |
| 5332 src : S3(read); | |
| 5333 cr : S3(read); | |
| 5334 DECODE : S0; // any decoder | |
| 5335 %} | |
| 5336 | |
| 5337 // Float reg-reg operation | |
|
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5338 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 5339 instruction_count(2); |
| 5340 dst : S3(read); | |
| 5341 DECODE : S0(2); // any 2 decoders | |
| 5342 FPU : S3; | |
| 5343 %} | |
| 5344 | |
| 5345 // Float reg-reg operation | |
|
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5346 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 5347 instruction_count(2); |
| 5348 dst : S4(write); | |
| 5349 src : S3(read); | |
| 5350 DECODE : S0(2); // any 2 decoders | |
| 5351 FPU : S3; | |
| 5352 %} | |
| 5353 | |
| 5354 // Float reg-reg operation | |
|
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5355 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 5356 instruction_count(3); |
| 5357 dst : S4(write); | |
| 5358 src1 : S3(read); | |
| 5359 src2 : S3(read); | |
| 5360 DECODE : S0(3); // any 3 decoders | |
| 5361 FPU : S3(2); | |
| 5362 %} | |
| 5363 | |
| 5364 // Float reg-reg operation | |
|
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5365 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 5366 instruction_count(4); |
| 5367 dst : S4(write); | |
| 5368 src1 : S3(read); | |
| 5369 src2 : S3(read); | |
| 5370 src3 : S3(read); | |
| 5371 DECODE : S0(4); // any 3 decoders | |
| 5372 FPU : S3(2); | |
| 5373 %} | |
| 5374 | |
| 5375 // Float reg-reg operation | |
|
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5376 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 5377 instruction_count(4); |
| 5378 dst : S4(write); | |
| 5379 src1 : S3(read); | |
| 5380 src2 : S3(read); | |
| 5381 src3 : S3(read); | |
| 5382 DECODE : S1(3); // any 3 decoders | |
| 5383 D0 : S0; // Big decoder only | |
| 5384 FPU : S3(2); | |
| 5385 MEM : S3; | |
| 5386 %} | |
| 5387 | |
| 5388 // Float reg-mem operation | |
|
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5389 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 5390 instruction_count(2); |
| 5391 dst : S5(write); | |
| 5392 mem : S3(read); | |
| 5393 D0 : S0; // big decoder only | |
| 5394 DECODE : S1; // any decoder for FPU POP | |
| 5395 FPU : S4; | |
| 5396 MEM : S3; // any mem | |
| 5397 %} | |
| 5398 | |
| 5399 // Float reg-mem operation | |
|
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5400 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 5401 instruction_count(3); |
| 5402 dst : S5(write); | |
| 5403 src1 : S3(read); | |
| 5404 mem : S3(read); | |
| 5405 D0 : S0; // big decoder only | |
| 5406 DECODE : S1(2); // any decoder for FPU POP | |
| 5407 FPU : S4; | |
| 5408 MEM : S3; // any mem | |
| 5409 %} | |
| 5410 | |
| 5411 // Float mem-reg operation | |
|
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5412 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 5413 instruction_count(2); |
| 5414 src : S5(read); | |
| 5415 mem : S3(read); | |
| 5416 DECODE : S0; // any decoder for FPU PUSH | |
| 5417 D0 : S1; // big decoder only | |
| 5418 FPU : S4; | |
| 5419 MEM : S3; // any mem | |
| 5420 %} | |
| 5421 | |
|
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5422 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 5423 instruction_count(3); |
| 5424 src1 : S3(read); | |
| 5425 src2 : S3(read); | |
| 5426 mem : S3(read); | |
| 5427 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5428 D0 : S1; // big decoder only | |
| 5429 FPU : S4; | |
| 5430 MEM : S3; // any mem | |
| 5431 %} | |
| 5432 | |
|
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5433 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 5434 instruction_count(3); |
| 5435 src1 : S3(read); | |
| 5436 src2 : S3(read); | |
| 5437 mem : S4(read); | |
| 5438 DECODE : S0; // any decoder for FPU PUSH | |
| 5439 D0 : S0(2); // big decoder only | |
| 5440 FPU : S4; | |
| 5441 MEM : S3(2); // any mem | |
| 5442 %} | |
| 5443 | |
| 5444 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 5445 instruction_count(2); | |
| 5446 src1 : S3(read); | |
| 5447 dst : S4(read); | |
| 5448 D0 : S0(2); // big decoder only | |
| 5449 MEM : S3(2); // any mem | |
| 5450 %} | |
| 5451 | |
| 5452 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 5453 instruction_count(3); | |
| 5454 src1 : S3(read); | |
| 5455 src2 : S3(read); | |
| 5456 dst : S4(read); | |
| 5457 D0 : S0(3); // big decoder only | |
| 5458 FPU : S4; | |
| 5459 MEM : S3(3); // any mem | |
| 5460 %} | |
| 5461 | |
|
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5462 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 5463 instruction_count(3); |
| 5464 src1 : S4(read); | |
| 5465 mem : S4(read); | |
| 5466 DECODE : S0; // any decoder for FPU PUSH | |
| 5467 D0 : S0(2); // big decoder only | |
| 5468 FPU : S4; | |
| 5469 MEM : S3(2); // any mem | |
| 5470 %} | |
| 5471 | |
| 5472 // Float load constant | |
|
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5473 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 5474 instruction_count(2); |
| 5475 dst : S5(write); | |
| 5476 D0 : S0; // big decoder only for the load | |
| 5477 DECODE : S1; // any decoder for FPU POP | |
| 5478 FPU : S4; | |
| 5479 MEM : S3; // any mem | |
| 5480 %} | |
| 5481 | |
| 5482 // Float load constant | |
|
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5483 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 5484 instruction_count(3); |
| 5485 dst : S5(write); | |
| 5486 src : S3(read); | |
| 5487 D0 : S0; // big decoder only for the load | |
| 5488 DECODE : S1(2); // any decoder for FPU POP | |
| 5489 FPU : S4; | |
| 5490 MEM : S3; // any mem | |
| 5491 %} | |
| 5492 | |
| 5493 // UnConditional branch | |
| 5494 pipe_class pipe_jmp( label labl ) %{ | |
| 5495 single_instruction; | |
| 5496 BR : S3; | |
| 5497 %} | |
| 5498 | |
| 5499 // Conditional branch | |
| 5500 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 5501 single_instruction; | |
| 5502 cr : S1(read); | |
| 5503 BR : S3; | |
| 5504 %} | |
| 5505 | |
| 5506 // Allocation idiom | |
| 5507 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 5508 instruction_count(1); force_serialization; | |
| 5509 fixed_latency(6); | |
| 5510 heap_ptr : S3(read); | |
| 5511 DECODE : S0(3); | |
| 5512 D0 : S2; | |
| 5513 MEM : S3; | |
| 5514 ALU : S3(2); | |
| 5515 dst : S5(write); | |
| 5516 BR : S5; | |
| 5517 %} | |
| 5518 | |
| 5519 // Generic big/slow expanded idiom | |
| 5520 pipe_class pipe_slow( ) %{ | |
| 5521 instruction_count(10); multiple_bundles; force_serialization; | |
| 5522 fixed_latency(100); | |
| 5523 D0 : S0(2); | |
| 5524 MEM : S3(2); | |
| 5525 %} | |
| 5526 | |
| 5527 // The real do-nothing guy | |
| 5528 pipe_class empty( ) %{ | |
| 5529 instruction_count(0); | |
| 5530 %} | |
| 5531 | |
| 5532 // Define the class for the Nop node | |
| 5533 define %{ | |
| 5534 MachNop = empty; | |
| 5535 %} | |
| 5536 | |
| 5537 %} | |
| 5538 | |
| 5539 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5540 // | |
| 5541 // match -- States which machine-independent subtree may be replaced | |
| 5542 // by this instruction. | |
| 5543 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5544 // selection to identify a minimum cost tree of machine | |
| 5545 // instructions that matches a tree of machine-independent | |
| 5546 // instructions. | |
| 5547 // format -- A string providing the disassembly for this instruction. | |
| 5548 // The value of an instruction's operand may be inserted | |
| 5549 // by referring to it with a '$' prefix. | |
| 5550 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5551 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5552 // respectively. The primary opcode is commonly used to | |
| 5553 // indicate the type of machine instruction, while secondary | |
| 5554 // and tertiary are often used for prefix options or addressing | |
| 5555 // modes. | |
| 5556 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5557 // name must have been defined in an 'enc_class' specification | |
| 5558 // in the encode section of the architecture description. | |
| 5559 | |
| 5560 //----------BSWAP-Instruction-------------------------------------------------- | |
|
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5561 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 5562 match(Set dst (ReverseBytesI dst)); |
| 5563 | |
| 5564 format %{ "BSWAP $dst" %} | |
| 5565 opcode(0x0F, 0xC8); | |
| 5566 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5567 ins_pipe( ialu_reg ); | |
| 5568 %} | |
| 5569 | |
| 5570 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5571 match(Set dst (ReverseBytesL dst)); | |
| 5572 | |
| 5573 format %{ "BSWAP $dst.lo\n\t" | |
| 5574 "BSWAP $dst.hi\n\t" | |
| 5575 "XCHG $dst.lo $dst.hi" %} | |
| 5576 | |
| 5577 ins_cost(125); | |
| 5578 ins_encode( bswap_long_bytes(dst) ); | |
| 5579 ins_pipe( ialu_reg_reg); | |
| 5580 %} | |
| 5581 | |
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changeset
|
5582 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5583 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5584 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5585 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5586 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5587 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5588 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5589 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5590 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5591 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5592 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5593 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5594 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5595 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5596 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5597 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5598 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5599 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5600 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5601 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5602 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5603 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5604 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5605 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5606 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5607 |
| 0 | 5608 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5609 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5610 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5611 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5612 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5613 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5614 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5615 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5616 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5617 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5618 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5619 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5620 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5621 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5622 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5623 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5624 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5625 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5626 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5627 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5628 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5629 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5630 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5631 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5632 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5633 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5634 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5635 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5636 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5637 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5638 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5639 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5640 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5641 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5642 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5643 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5644 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5645 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5646 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5647 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5648 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5649 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5650 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5651 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5652 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5653 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5654 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5655 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5656 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5657 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5658 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5659 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5660 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5661 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5662 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5663 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5664 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5665 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5666 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5667 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5668 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5669 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5670 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5671 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5672 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5673 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5674 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5675 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5676 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5677 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5678 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5679 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5680 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5681 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5682 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5683 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5684 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5685 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5686 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5687 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5688 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5689 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5690 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5691 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5692 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5693 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5694 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5695 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5696 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5697 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5698 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5699 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5700 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5701 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5702 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5703 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5704 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5705 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5706 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5707 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5708 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5709 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5710 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5711 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5712 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5713 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5714 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5715 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5716 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5717 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5718 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5719 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5720 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5721 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5722 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5723 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5724 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5725 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5726 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5727 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5728 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5729 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5730 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5731 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5732 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5733 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5734 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5735 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5736 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5737 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5738 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5739 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5740 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5741 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5742 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5743 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5744 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5745 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5746 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5747 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5748 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5749 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5750 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5751 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5752 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5753 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5754 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5755 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5756 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5757 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5758 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5759 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5760 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5761 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5762 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5763 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5764 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5765 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5766 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5767 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5768 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5769 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5770 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5771 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5772 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5773 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5774 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5775 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5776 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5777 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5778 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5779 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5780 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5781 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5782 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5783 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5784 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5785 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5786 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5787 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5788 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5789 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5790 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5791 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5792 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5793 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5794 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5795 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5796 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5797 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5798 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5799 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
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5800 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
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5801 predicate(UsePopCountInstruction); |
|
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5802 match(Set dst (PopCountL (LoadL mem))); |
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|
5803 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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5804 |
|
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|
5805 format %{ "POPCNT $dst, $mem\n\t" |
|
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5806 "POPCNT $tmp, $mem+4\n\t" |
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5807 "ADD $dst, $tmp" %} |
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|
5808 ins_encode %{ |
|
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5809 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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5810 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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5811 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
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5812 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
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5813 __ addl($dst$$Register, $tmp$$Register); |
|
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|
5814 %} |
|
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|
5815 ins_pipe(ialu_reg); |
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|
5816 %} |
|
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|
5817 |
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|
5818 |
| 0 | 5819 //----------Load/Store/Move Instructions--------------------------------------- |
| 5820 //----------Load Instructions-------------------------------------------------- | |
| 5821 // Load Byte (8bit signed) | |
| 5822 instruct loadB(xRegI dst, memory mem) %{ | |
| 5823 match(Set dst (LoadB mem)); | |
| 5824 | |
| 5825 ins_cost(125); | |
| 624 | 5826 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5827 | |
| 5828 ins_encode %{ | |
| 5829 __ movsbl($dst$$Register, $mem$$Address); | |
| 5830 %} | |
| 5831 | |
| 5832 ins_pipe(ialu_reg_mem); | |
| 5833 %} | |
| 5834 | |
| 5835 // Load Byte (8bit signed) into Long Register | |
| 824 | 5836 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5837 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5838 effect(KILL cr); |
| 624 | 5839 |
| 5840 ins_cost(375); | |
| 5841 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5842 "MOV $dst.hi,$dst.lo\n\t" | |
| 5843 "SAR $dst.hi,7" %} | |
| 5844 | |
| 5845 ins_encode %{ | |
| 5846 __ movsbl($dst$$Register, $mem$$Address); | |
| 5847 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5848 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5849 %} | |
| 5850 | |
| 5851 ins_pipe(ialu_reg_mem); | |
| 5852 %} | |
| 5853 | |
| 5854 // Load Unsigned Byte (8bit UNsigned) | |
| 5855 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5856 match(Set dst (LoadUB mem)); | |
| 0 | 5857 |
| 5858 ins_cost(125); | |
| 624 | 5859 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5860 | |
| 5861 ins_encode %{ | |
| 5862 __ movzbl($dst$$Register, $mem$$Address); | |
| 5863 %} | |
| 5864 | |
| 5865 ins_pipe(ialu_reg_mem); | |
| 5866 %} | |
| 5867 | |
| 5868 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5869 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5870 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5871 effect(KILL cr); |
| 624 | 5872 |
| 5873 ins_cost(250); | |
| 5874 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5875 "XOR $dst.hi,$dst.hi" %} | |
| 5876 | |
| 5877 ins_encode %{ | |
| 824 | 5878 Register Rdst = $dst$$Register; |
| 5879 __ movzbl(Rdst, $mem$$Address); | |
| 5880 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5881 %} | |
| 5882 | |
| 5883 ins_pipe(ialu_reg_mem); | |
| 5884 %} | |
| 5885 | |
| 5886 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5887 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5888 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5889 effect(KILL cr); | |
| 5890 | |
| 5891 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5892 "XOR $dst.hi,$dst.hi\n\t" | |
| 5893 "AND $dst.lo,$mask" %} | |
| 5894 ins_encode %{ | |
| 5895 Register Rdst = $dst$$Register; | |
| 5896 __ movzbl(Rdst, $mem$$Address); | |
| 5897 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5898 __ andl(Rdst, $mask$$constant); | |
| 5899 %} | |
| 624 | 5900 ins_pipe(ialu_reg_mem); |
| 5901 %} | |
| 5902 | |
| 5903 // Load Short (16bit signed) | |
|
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5904 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5905 match(Set dst (LoadS mem)); |
| 5906 | |
| 5907 ins_cost(125); | |
| 5908 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5909 | |
| 5910 ins_encode %{ | |
| 5911 __ movswl($dst$$Register, $mem$$Address); | |
| 5912 %} | |
| 5913 | |
| 5914 ins_pipe(ialu_reg_mem); | |
| 5915 %} | |
| 5916 | |
| 785 | 5917 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
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5918 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5919 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5920 | |
| 5921 ins_cost(125); | |
| 5922 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5923 ins_encode %{ | |
| 5924 __ movsbl($dst$$Register, $mem$$Address); | |
| 5925 %} | |
| 5926 ins_pipe(ialu_reg_mem); | |
| 5927 %} | |
| 5928 | |
| 624 | 5929 // Load Short (16bit signed) into Long Register |
| 824 | 5930 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5931 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5932 effect(KILL cr); |
| 624 | 5933 |
| 5934 ins_cost(375); | |
| 5935 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5936 "MOV $dst.hi,$dst.lo\n\t" | |
| 5937 "SAR $dst.hi,15" %} | |
| 5938 | |
| 5939 ins_encode %{ | |
| 5940 __ movswl($dst$$Register, $mem$$Address); | |
| 5941 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5942 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5943 %} | |
| 5944 | |
| 5945 ins_pipe(ialu_reg_mem); | |
| 0 | 5946 %} |
| 5947 | |
|
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5948 // Load Unsigned Short/Char (16bit unsigned) |
|
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5949 instruct loadUS(rRegI dst, memory mem) %{ |
|
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5950 match(Set dst (LoadUS mem)); |
| 0 | 5951 |
| 5952 ins_cost(125); | |
| 624 | 5953 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5954 | |
| 5955 ins_encode %{ | |
| 5956 __ movzwl($dst$$Register, $mem$$Address); | |
| 5957 %} | |
| 5958 | |
| 5959 ins_pipe(ialu_reg_mem); | |
| 5960 %} | |
| 5961 | |
| 785 | 5962 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
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5963 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5964 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5965 | |
| 5966 ins_cost(125); | |
| 5967 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5968 ins_encode %{ | |
| 5969 __ movsbl($dst$$Register, $mem$$Address); | |
| 5970 %} | |
| 5971 ins_pipe(ialu_reg_mem); | |
| 5972 %} | |
| 5973 | |
| 624 | 5974 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5975 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5976 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5977 effect(KILL cr); |
| 624 | 5978 |
| 5979 ins_cost(250); | |
| 5980 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5981 "XOR $dst.hi,$dst.hi" %} | |
| 5982 | |
| 5983 ins_encode %{ | |
| 5984 __ movzwl($dst$$Register, $mem$$Address); | |
| 5985 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5986 %} | |
| 5987 | |
| 5988 ins_pipe(ialu_reg_mem); | |
| 0 | 5989 %} |
| 5990 | |
| 824 | 5991 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5992 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5993 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5994 effect(KILL cr); | |
| 5995 | |
| 5996 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5997 "XOR $dst.hi,$dst.hi" %} | |
| 5998 ins_encode %{ | |
| 5999 Register Rdst = $dst$$Register; | |
| 6000 __ movzbl(Rdst, $mem$$Address); | |
| 6001 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6002 %} | |
| 6003 ins_pipe(ialu_reg_mem); | |
| 6004 %} | |
| 6005 | |
| 6006 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 6007 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 6008 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6009 effect(KILL cr); | |
| 6010 | |
| 6011 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6012 "XOR $dst.hi,$dst.hi\n\t" | |
| 6013 "AND $dst.lo,$mask" %} | |
| 6014 ins_encode %{ | |
| 6015 Register Rdst = $dst$$Register; | |
| 6016 __ movzwl(Rdst, $mem$$Address); | |
| 6017 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6018 __ andl(Rdst, $mask$$constant); | |
| 6019 %} | |
| 6020 ins_pipe(ialu_reg_mem); | |
| 6021 %} | |
| 6022 | |
| 0 | 6023 // Load Integer |
|
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6024 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 6025 match(Set dst (LoadI mem)); |
| 6026 | |
| 6027 ins_cost(125); | |
| 624 | 6028 format %{ "MOV $dst,$mem\t# int" %} |
| 6029 | |
| 6030 ins_encode %{ | |
| 6031 __ movl($dst$$Register, $mem$$Address); | |
| 6032 %} | |
| 6033 | |
| 6034 ins_pipe(ialu_reg_mem); | |
| 6035 %} | |
| 6036 | |
| 785 | 6037 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
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6038 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 6039 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 6040 | |
| 6041 ins_cost(125); | |
| 6042 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 6043 ins_encode %{ | |
| 6044 __ movsbl($dst$$Register, $mem$$Address); | |
| 6045 %} | |
| 6046 ins_pipe(ialu_reg_mem); | |
| 6047 %} | |
| 6048 | |
| 6049 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
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6050 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 6051 match(Set dst (AndI (LoadI mem) mask)); |
| 6052 | |
| 6053 ins_cost(125); | |
| 6054 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6055 ins_encode %{ | |
| 6056 __ movzbl($dst$$Register, $mem$$Address); | |
| 6057 %} | |
| 6058 ins_pipe(ialu_reg_mem); | |
| 6059 %} | |
| 6060 | |
| 6061 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
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|
6062 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 6063 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 6064 | |
| 6065 ins_cost(125); | |
| 6066 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6067 ins_encode %{ | |
| 6068 __ movswl($dst$$Register, $mem$$Address); | |
| 6069 %} | |
| 6070 ins_pipe(ialu_reg_mem); | |
| 6071 %} | |
| 6072 | |
| 6073 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
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6074 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 6075 match(Set dst (AndI (LoadI mem) mask)); |
| 6076 | |
| 6077 ins_cost(125); | |
| 6078 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6079 ins_encode %{ | |
| 6080 __ movzwl($dst$$Register, $mem$$Address); | |
| 6081 %} | |
| 6082 ins_pipe(ialu_reg_mem); | |
| 6083 %} | |
| 6084 | |
| 624 | 6085 // Load Integer into Long Register |
| 824 | 6086 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6087 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6088 effect(KILL cr); |
| 624 | 6089 |
| 6090 ins_cost(375); | |
| 6091 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6092 "MOV $dst.hi,$dst.lo\n\t" | |
| 6093 "SAR $dst.hi,31" %} | |
| 6094 | |
| 6095 ins_encode %{ | |
| 6096 __ movl($dst$$Register, $mem$$Address); | |
| 6097 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6098 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6099 %} | |
| 6100 | |
| 6101 ins_pipe(ialu_reg_mem); | |
| 6102 %} | |
| 6103 | |
| 824 | 6104 // Load Integer with mask 0xFF into Long Register |
| 6105 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6106 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6107 effect(KILL cr); | |
| 6108 | |
| 6109 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6110 "XOR $dst.hi,$dst.hi" %} | |
| 6111 ins_encode %{ | |
| 6112 Register Rdst = $dst$$Register; | |
| 6113 __ movzbl(Rdst, $mem$$Address); | |
| 6114 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6115 %} | |
| 6116 ins_pipe(ialu_reg_mem); | |
| 6117 %} | |
| 6118 | |
| 6119 // Load Integer with mask 0xFFFF into Long Register | |
| 6120 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6121 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6122 effect(KILL cr); | |
| 6123 | |
| 6124 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6125 "XOR $dst.hi,$dst.hi" %} | |
| 6126 ins_encode %{ | |
| 6127 Register Rdst = $dst$$Register; | |
| 6128 __ movzwl(Rdst, $mem$$Address); | |
| 6129 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6130 %} | |
| 6131 ins_pipe(ialu_reg_mem); | |
| 6132 %} | |
| 6133 | |
| 6134 // Load Integer with 32-bit mask into Long Register | |
| 6135 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ | |
| 6136 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6137 effect(KILL cr); | |
| 6138 | |
| 6139 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" | |
| 6140 "XOR $dst.hi,$dst.hi\n\t" | |
| 6141 "AND $dst.lo,$mask" %} | |
| 6142 ins_encode %{ | |
| 6143 Register Rdst = $dst$$Register; | |
| 6144 __ movl(Rdst, $mem$$Address); | |
| 6145 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6146 __ andl(Rdst, $mask$$constant); | |
| 6147 %} | |
| 6148 ins_pipe(ialu_reg_mem); | |
| 6149 %} | |
| 6150 | |
| 624 | 6151 // Load Unsigned Integer into Long Register |
| 6849 | 6152 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 6153 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 6154 effect(KILL cr); |
| 624 | 6155 |
| 6156 ins_cost(250); | |
| 6157 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6158 "XOR $dst.hi,$dst.hi" %} | |
| 6159 | |
| 6160 ins_encode %{ | |
| 6161 __ movl($dst$$Register, $mem$$Address); | |
| 6162 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6163 %} | |
| 6164 | |
| 6165 ins_pipe(ialu_reg_mem); | |
| 0 | 6166 %} |
| 6167 | |
| 6168 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6169 // register to ESI | |
| 6170 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6171 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6172 match(Set dst (LoadL mem)); | |
| 6173 | |
| 6174 ins_cost(250); | |
| 624 | 6175 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6176 "MOV $dst.hi,$mem+4" %} |
| 624 | 6177 |
| 6178 ins_encode %{ | |
|
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6179 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
|
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6180 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 6181 __ movl($dst$$Register, Amemlo); |
| 6182 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6183 %} | |
| 6184 | |
| 6185 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6186 %} |
| 6187 | |
| 6188 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6189 // then store it down to the stack and reload on the int | |
| 6190 // side. | |
| 6191 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6192 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6193 match(Set dst (LoadL mem)); | |
| 6194 | |
| 6195 ins_cost(200); | |
| 6196 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6197 "FISTp $dst" %} | |
| 6198 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6199 ins_pipe( fpu_reg_mem ); | |
| 6200 %} | |
| 6201 | |
|
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6202 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 6203 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6204 match(Set dst (LoadL mem)); | |
| 6205 effect(TEMP tmp); | |
| 6206 ins_cost(180); | |
| 6207 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6208 "MOVSD $dst,$tmp" %} | |
| 4759 | 6209 ins_encode %{ |
| 6210 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6211 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 6212 %} | |
| 0 | 6213 ins_pipe( pipe_slow ); |
| 6214 %} | |
| 6215 | |
|
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6216 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 6217 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6218 match(Set dst (LoadL mem)); | |
| 6219 effect(TEMP tmp); | |
| 6220 ins_cost(160); | |
| 6221 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6222 "MOVD $dst.lo,$tmp\n\t" | |
| 6223 "PSRLQ $tmp,32\n\t" | |
| 6224 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 6225 ins_encode %{ |
| 6226 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6227 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 6228 __ psrlq($tmp$$XMMRegister, 32); | |
| 6229 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 6230 %} | |
| 0 | 6231 ins_pipe( pipe_slow ); |
| 6232 %} | |
| 6233 | |
| 6234 // Load Range | |
|
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6235 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 6236 match(Set dst (LoadRange mem)); |
| 6237 | |
| 6238 ins_cost(125); | |
| 6239 format %{ "MOV $dst,$mem" %} | |
| 6240 opcode(0x8B); | |
| 6241 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6242 ins_pipe( ialu_reg_mem ); | |
| 6243 %} | |
| 6244 | |
| 6245 | |
| 6246 // Load Pointer | |
| 6247 instruct loadP(eRegP dst, memory mem) %{ | |
| 6248 match(Set dst (LoadP mem)); | |
| 6249 | |
| 6250 ins_cost(125); | |
| 6251 format %{ "MOV $dst,$mem" %} | |
| 6252 opcode(0x8B); | |
| 6253 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6254 ins_pipe( ialu_reg_mem ); | |
| 6255 %} | |
| 6256 | |
| 6257 // Load Klass Pointer | |
| 6258 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6259 match(Set dst (LoadKlass mem)); | |
| 6260 | |
| 6261 ins_cost(125); | |
| 6262 format %{ "MOV $dst,$mem" %} | |
| 6263 opcode(0x8B); | |
| 6264 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6265 ins_pipe( ialu_reg_mem ); | |
| 6266 %} | |
| 6267 | |
| 6268 // Load Double | |
|
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6269 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 6270 predicate(UseSSE<=1); |
| 6271 match(Set dst (LoadD mem)); | |
| 6272 | |
| 6273 ins_cost(150); | |
| 6274 format %{ "FLD_D ST,$mem\n\t" | |
| 6275 "FSTP $dst" %} | |
| 6276 opcode(0xDD); /* DD /0 */ | |
| 6277 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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6278 Pop_Reg_DPR(dst) ); |
| 0 | 6279 ins_pipe( fpu_reg_mem ); |
| 6280 %} | |
| 6281 | |
| 6282 // Load Double to XMM | |
|
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6283 instruct loadD(regD dst, memory mem) %{ |
| 0 | 6284 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 6285 match(Set dst (LoadD mem)); | |
| 6286 ins_cost(145); | |
| 6287 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 6288 ins_encode %{ |
| 6289 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6290 %} | |
| 0 | 6291 ins_pipe( pipe_slow ); |
| 6292 %} | |
| 6293 | |
|
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6294 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 6295 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 6296 match(Set dst (LoadD mem)); | |
| 6297 ins_cost(145); | |
| 6298 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 6299 ins_encode %{ |
| 6300 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6301 %} | |
| 0 | 6302 ins_pipe( pipe_slow ); |
| 6303 %} | |
| 6304 | |
| 6305 // Load to XMM register (single-precision floating point) | |
| 6306 // MOVSS instruction | |
|
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6307 instruct loadF(regF dst, memory mem) %{ |
| 0 | 6308 predicate(UseSSE>=1); |
| 6309 match(Set dst (LoadF mem)); | |
| 6310 ins_cost(145); | |
| 6311 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 6312 ins_encode %{ |
| 6313 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 6314 %} | |
| 0 | 6315 ins_pipe( pipe_slow ); |
| 6316 %} | |
| 6317 | |
| 6318 // Load Float | |
|
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6319 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 6320 predicate(UseSSE==0); |
| 6321 match(Set dst (LoadF mem)); | |
| 6322 | |
| 6323 ins_cost(150); | |
| 6324 format %{ "FLD_S ST,$mem\n\t" | |
| 6325 "FSTP $dst" %} | |
| 6326 opcode(0xD9); /* D9 /0 */ | |
| 6327 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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6328 Pop_Reg_FPR(dst) ); |
| 0 | 6329 ins_pipe( fpu_reg_mem ); |
| 6330 %} | |
| 6331 | |
| 6332 // Load Effective Address | |
| 6333 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 6334 match(Set dst mem); | |
| 6335 | |
| 6336 ins_cost(110); | |
| 6337 format %{ "LEA $dst,$mem" %} | |
| 6338 opcode(0x8D); | |
| 6339 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6340 ins_pipe( ialu_reg_reg_fat ); | |
| 6341 %} | |
| 6342 | |
| 6343 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 6344 match(Set dst mem); | |
| 6345 | |
| 6346 ins_cost(110); | |
| 6347 format %{ "LEA $dst,$mem" %} | |
| 6348 opcode(0x8D); | |
| 6349 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6350 ins_pipe( ialu_reg_reg_fat ); | |
| 6351 %} | |
| 6352 | |
| 6353 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 6354 match(Set dst mem); | |
| 6355 | |
| 6356 ins_cost(110); | |
| 6357 format %{ "LEA $dst,$mem" %} | |
| 6358 opcode(0x8D); | |
| 6359 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6360 ins_pipe( ialu_reg_reg_fat ); | |
| 6361 %} | |
| 6362 | |
| 6363 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 6364 match(Set dst mem); | |
| 6365 | |
| 6366 ins_cost(110); | |
| 6367 format %{ "LEA $dst,$mem" %} | |
| 6368 opcode(0x8D); | |
| 6369 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6370 ins_pipe( ialu_reg_reg_fat ); | |
| 6371 %} | |
| 6372 | |
| 6373 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 6374 match(Set dst mem); | |
| 6375 | |
| 6376 ins_cost(110); | |
| 6377 format %{ "LEA $dst,$mem" %} | |
| 6378 opcode(0x8D); | |
| 6379 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6380 ins_pipe( ialu_reg_reg_fat ); | |
| 6381 %} | |
| 6382 | |
| 6383 // Load Constant | |
|
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6384 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 6385 match(Set dst src); |
| 6386 | |
| 6387 format %{ "MOV $dst,$src" %} | |
| 6388 ins_encode( LdImmI(dst, src) ); | |
| 6389 ins_pipe( ialu_reg_fat ); | |
| 6390 %} | |
| 6391 | |
| 6392 // Load Constant zero | |
|
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6393 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 6394 match(Set dst src); |
| 6395 effect(KILL cr); | |
| 6396 | |
| 6397 ins_cost(50); | |
| 6398 format %{ "XOR $dst,$dst" %} | |
| 6399 opcode(0x33); /* + rd */ | |
| 6400 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 6401 ins_pipe( ialu_reg ); | |
| 6402 %} | |
| 6403 | |
| 6404 instruct loadConP(eRegP dst, immP src) %{ | |
| 6405 match(Set dst src); | |
| 6406 | |
| 6407 format %{ "MOV $dst,$src" %} | |
| 6408 opcode(0xB8); /* + rd */ | |
| 6409 ins_encode( LdImmP(dst, src) ); | |
| 6410 ins_pipe( ialu_reg_fat ); | |
| 6411 %} | |
| 6412 | |
| 6413 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 6414 match(Set dst src); | |
| 6415 effect(KILL cr); | |
| 6416 ins_cost(200); | |
| 6417 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 6418 "MOV $dst.hi,$src.hi" %} | |
| 6419 opcode(0xB8); | |
| 6420 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 6421 ins_pipe( ialu_reg_long_fat ); | |
| 6422 %} | |
| 6423 | |
| 6424 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 6425 match(Set dst src); | |
| 6426 effect(KILL cr); | |
| 6427 ins_cost(150); | |
| 6428 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 6429 "XOR $dst.hi,$dst.hi" %} | |
| 6430 opcode(0x33,0x33); | |
| 6431 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 6432 ins_pipe( ialu_reg_long ); | |
| 6433 %} | |
| 6434 | |
|
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6435 // The instruction usage is guarded by predicate in operand immFPR(). |
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6436 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 6437 match(Set dst con); |
| 6438 ins_cost(125); | |
| 6439 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 6440 "FSTP $dst" %} | |
| 6441 ins_encode %{ | |
| 6442 __ fld_s($constantaddress($con)); | |
| 6443 __ fstp_d($dst$$reg); | |
| 6444 %} | |
| 6445 ins_pipe(fpu_reg_con); | |
| 6446 %} | |
| 6447 | |
|
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6448 // The instruction usage is guarded by predicate in operand immFPR0(). |
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6449 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 6450 match(Set dst con); |
| 0 | 6451 ins_cost(125); |
| 2008 | 6452 format %{ "FLDZ ST\n\t" |
| 0 | 6453 "FSTP $dst" %} |
| 2008 | 6454 ins_encode %{ |
| 6455 __ fldz(); | |
| 6456 __ fstp_d($dst$$reg); | |
| 6457 %} | |
| 6458 ins_pipe(fpu_reg_con); | |
| 6459 %} | |
| 6460 | |
|
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6461 // The instruction usage is guarded by predicate in operand immFPR1(). |
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6462 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 6463 match(Set dst con); |
| 6464 ins_cost(125); | |
| 6465 format %{ "FLD1 ST\n\t" | |
| 6466 "FSTP $dst" %} | |
| 6467 ins_encode %{ | |
| 6468 __ fld1(); | |
| 6469 __ fstp_d($dst$$reg); | |
| 6470 %} | |
| 6471 ins_pipe(fpu_reg_con); | |
| 0 | 6472 %} |
| 6473 | |
|
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6474 // The instruction usage is guarded by predicate in operand immF(). |
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6475 instruct loadConF(regF dst, immF con) %{ |
| 0 | 6476 match(Set dst con); |
| 6477 ins_cost(125); | |
| 2008 | 6478 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 6479 ins_encode %{ | |
| 6480 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 6481 %} | |
| 6482 ins_pipe(pipe_slow); | |
| 0 | 6483 %} |
| 6484 | |
|
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6485 // The instruction usage is guarded by predicate in operand immF0(). |
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6486 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 6487 match(Set dst src); |
| 6488 ins_cost(100); | |
| 6489 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 6490 ins_encode %{ |
| 6491 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6492 %} | |
| 6493 ins_pipe(pipe_slow); | |
| 0 | 6494 %} |
| 6495 | |
|
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6496 // The instruction usage is guarded by predicate in operand immDPR(). |
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6497 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 6498 match(Set dst con); |
| 6499 ins_cost(125); | |
| 6500 | |
| 6501 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 6502 "FSTP $dst" %} | |
| 6503 ins_encode %{ | |
| 6504 __ fld_d($constantaddress($con)); | |
| 6505 __ fstp_d($dst$$reg); | |
| 6506 %} | |
| 6507 ins_pipe(fpu_reg_con); | |
| 6508 %} | |
| 6509 | |
|
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6510 // The instruction usage is guarded by predicate in operand immDPR0(). |
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6511 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 6512 match(Set dst con); |
| 0 | 6513 ins_cost(125); |
| 6514 | |
| 2008 | 6515 format %{ "FLDZ ST\n\t" |
| 0 | 6516 "FSTP $dst" %} |
| 2008 | 6517 ins_encode %{ |
| 6518 __ fldz(); | |
| 6519 __ fstp_d($dst$$reg); | |
| 6520 %} | |
| 6521 ins_pipe(fpu_reg_con); | |
| 6522 %} | |
| 6523 | |
|
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6524 // The instruction usage is guarded by predicate in operand immDPR1(). |
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6525 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 6526 match(Set dst con); |
| 6527 ins_cost(125); | |
| 6528 | |
| 6529 format %{ "FLD1 ST\n\t" | |
| 6530 "FSTP $dst" %} | |
| 6531 ins_encode %{ | |
| 6532 __ fld1(); | |
| 6533 __ fstp_d($dst$$reg); | |
| 6534 %} | |
| 6535 ins_pipe(fpu_reg_con); | |
| 0 | 6536 %} |
| 6537 | |
|
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6538 // The instruction usage is guarded by predicate in operand immD(). |
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6539 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6540 match(Set dst con); |
| 6541 ins_cost(125); | |
| 2008 | 6542 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6543 ins_encode %{ | |
| 6544 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6545 %} | |
| 6546 ins_pipe(pipe_slow); | |
| 0 | 6547 %} |
| 6548 | |
|
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6549 // The instruction usage is guarded by predicate in operand immD0(). |
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6550 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6551 match(Set dst src); |
| 6552 ins_cost(100); | |
| 6553 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6554 ins_encode %{ |
| 6555 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6556 %} | |
| 0 | 6557 ins_pipe( pipe_slow ); |
| 6558 %} | |
| 6559 | |
| 6560 // Load Stack Slot | |
|
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6561 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6562 match(Set dst src); |
| 6563 ins_cost(125); | |
| 6564 | |
| 6565 format %{ "MOV $dst,$src" %} | |
| 6566 opcode(0x8B); | |
| 6567 ins_encode( OpcP, RegMem(dst,src)); | |
| 6568 ins_pipe( ialu_reg_mem ); | |
| 6569 %} | |
| 6570 | |
| 6571 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6572 match(Set dst src); | |
| 6573 | |
| 6574 ins_cost(200); | |
| 6575 format %{ "MOV $dst,$src.lo\n\t" | |
| 6576 "MOV $dst+4,$src.hi" %} | |
| 6577 opcode(0x8B, 0x8B); | |
| 6578 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6579 ins_pipe( ialu_mem_long_reg ); | |
| 6580 %} | |
| 6581 | |
| 6582 // Load Stack Slot | |
| 6583 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6584 match(Set dst src); | |
| 6585 ins_cost(125); | |
| 6586 | |
| 6587 format %{ "MOV $dst,$src" %} | |
| 6588 opcode(0x8B); | |
| 6589 ins_encode( OpcP, RegMem(dst,src)); | |
| 6590 ins_pipe( ialu_reg_mem ); | |
| 6591 %} | |
| 6592 | |
| 6593 // Load Stack Slot | |
|
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6594 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6595 match(Set dst src); |
| 6596 ins_cost(125); | |
| 6597 | |
| 6598 format %{ "FLD_S $src\n\t" | |
| 6599 "FSTP $dst" %} | |
| 6600 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6601 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6602 Pop_Reg_FPR(dst) ); |
| 0 | 6603 ins_pipe( fpu_reg_mem ); |
| 6604 %} | |
| 6605 | |
| 6606 // Load Stack Slot | |
|
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6607 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6608 match(Set dst src); |
| 6609 ins_cost(125); | |
| 6610 | |
| 6611 format %{ "FLD_D $src\n\t" | |
| 6612 "FSTP $dst" %} | |
| 6613 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6614 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6615 Pop_Reg_DPR(dst) ); |
| 0 | 6616 ins_pipe( fpu_reg_mem ); |
| 6617 %} | |
| 6618 | |
| 6619 // Prefetch instructions. | |
| 6620 // Must be safe to execute with invalid address (cannot fault). | |
| 6621 | |
| 6622 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6623 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6624 match(PrefetchRead mem); |
| 6625 ins_cost(0); | |
| 6626 size(0); | |
| 6627 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6628 ins_encode(); | |
| 6629 ins_pipe(empty); | |
| 6630 %} | |
| 6631 | |
| 6632 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6633 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6634 match(PrefetchRead mem); |
| 6635 ins_cost(100); | |
| 6636 | |
| 6637 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6638 ins_encode %{ |
| 6639 __ prefetchr($mem$$Address); | |
| 6640 %} | |
| 0 | 6641 ins_pipe(ialu_mem); |
| 6642 %} | |
| 6643 | |
| 6644 instruct prefetchrNTA( memory mem ) %{ | |
| 6645 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6646 match(PrefetchRead mem); | |
| 6647 ins_cost(100); | |
| 6648 | |
| 6649 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6650 ins_encode %{ |
| 6651 __ prefetchnta($mem$$Address); | |
| 6652 %} | |
| 0 | 6653 ins_pipe(ialu_mem); |
| 6654 %} | |
| 6655 | |
| 6656 instruct prefetchrT0( memory mem ) %{ | |
| 6657 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6658 match(PrefetchRead mem); | |
| 6659 ins_cost(100); | |
| 6660 | |
| 6661 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6662 ins_encode %{ |
| 6663 __ prefetcht0($mem$$Address); | |
| 6664 %} | |
| 0 | 6665 ins_pipe(ialu_mem); |
| 6666 %} | |
| 6667 | |
| 6668 instruct prefetchrT2( memory mem ) %{ | |
| 6669 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6670 match(PrefetchRead mem); | |
| 6671 ins_cost(100); | |
| 6672 | |
| 6673 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6674 ins_encode %{ |
| 6675 __ prefetcht2($mem$$Address); | |
| 6676 %} | |
| 0 | 6677 ins_pipe(ialu_mem); |
| 6678 %} | |
| 6679 | |
| 6680 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6681 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6682 match(PrefetchWrite mem); |
| 6683 ins_cost(0); | |
| 6684 size(0); | |
| 6685 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6686 ins_encode(); | |
| 6687 ins_pipe(empty); | |
| 6688 %} | |
| 6689 | |
| 6690 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6691 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6692 match( PrefetchWrite mem ); |
| 6693 ins_cost(100); | |
| 6694 | |
| 6695 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6696 ins_encode %{ |
| 6697 __ prefetchw($mem$$Address); | |
| 6698 %} | |
| 0 | 6699 ins_pipe(ialu_mem); |
| 6700 %} | |
| 6701 | |
| 6702 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6703 predicate(UseSSE>=1); |
| 0 | 6704 match(PrefetchWrite mem); |
| 6705 ins_cost(100); | |
| 6706 | |
| 6707 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6708 ins_encode %{ |
| 6709 __ prefetchnta($mem$$Address); | |
| 6710 %} | |
| 0 | 6711 ins_pipe(ialu_mem); |
| 6712 %} | |
| 6713 | |
| 3854 | 6714 // Prefetch instructions for allocation. |
| 6715 | |
| 6716 instruct prefetchAlloc0( memory mem ) %{ | |
| 6717 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6718 match(PrefetchAllocation mem); | |
| 6719 ins_cost(0); | |
| 6720 size(0); | |
| 6721 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6722 ins_encode(); | |
| 6723 ins_pipe(empty); | |
| 6724 %} | |
| 6725 | |
| 6726 instruct prefetchAlloc( memory mem ) %{ | |
| 6727 predicate(AllocatePrefetchInstr==3); | |
| 6728 match( PrefetchAllocation mem ); | |
| 0 | 6729 ins_cost(100); |
| 6730 | |
| 3854 | 6731 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6732 ins_encode %{ | |
| 6733 __ prefetchw($mem$$Address); | |
| 6734 %} | |
| 6735 ins_pipe(ialu_mem); | |
| 6736 %} | |
| 6737 | |
| 6738 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6739 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6740 match(PrefetchAllocation mem); | |
| 6741 ins_cost(100); | |
| 6742 | |
| 6743 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6744 ins_encode %{ | |
| 6745 __ prefetchnta($mem$$Address); | |
| 6746 %} | |
| 0 | 6747 ins_pipe(ialu_mem); |
| 6748 %} | |
| 6749 | |
| 3854 | 6750 instruct prefetchAllocT0( memory mem ) %{ |
| 6751 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6752 match(PrefetchAllocation mem); | |
| 0 | 6753 ins_cost(100); |
| 6754 | |
| 3854 | 6755 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6756 ins_encode %{ | |
| 6757 __ prefetcht0($mem$$Address); | |
| 6758 %} | |
| 6759 ins_pipe(ialu_mem); | |
| 6760 %} | |
| 6761 | |
| 6762 instruct prefetchAllocT2( memory mem ) %{ | |
| 6763 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6764 match(PrefetchAllocation mem); | |
| 6765 ins_cost(100); | |
| 6766 | |
| 6767 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6768 ins_encode %{ | |
| 6769 __ prefetcht2($mem$$Address); | |
| 6770 %} | |
| 0 | 6771 ins_pipe(ialu_mem); |
| 6772 %} | |
| 6773 | |
| 6774 //----------Store Instructions------------------------------------------------- | |
| 6775 | |
| 6776 // Store Byte | |
| 6777 instruct storeB(memory mem, xRegI src) %{ | |
| 6778 match(Set mem (StoreB mem src)); | |
| 6779 | |
| 6780 ins_cost(125); | |
| 6781 format %{ "MOV8 $mem,$src" %} | |
| 6782 opcode(0x88); | |
| 6783 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6784 ins_pipe( ialu_mem_reg ); | |
| 6785 %} | |
| 6786 | |
| 6787 // Store Char/Short | |
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6788 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6789 match(Set mem (StoreC mem src)); |
| 6790 | |
| 6791 ins_cost(125); | |
| 6792 format %{ "MOV16 $mem,$src" %} | |
| 6793 opcode(0x89, 0x66); | |
| 6794 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6795 ins_pipe( ialu_mem_reg ); | |
| 6796 %} | |
| 6797 | |
| 6798 // Store Integer | |
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6799 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6800 match(Set mem (StoreI mem src)); |
| 6801 | |
| 6802 ins_cost(125); | |
| 6803 format %{ "MOV $mem,$src" %} | |
| 6804 opcode(0x89); | |
| 6805 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6806 ins_pipe( ialu_mem_reg ); | |
| 6807 %} | |
| 6808 | |
| 6809 // Store Long | |
| 6810 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6811 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6812 match(Set mem (StoreL mem src)); | |
| 6813 | |
| 6814 ins_cost(200); | |
| 6815 format %{ "MOV $mem,$src.lo\n\t" | |
| 6816 "MOV $mem+4,$src.hi" %} | |
| 6817 opcode(0x89, 0x89); | |
| 6818 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6819 ins_pipe( ialu_mem_long_reg ); | |
| 6820 %} | |
| 6821 | |
| 824 | 6822 // Store Long to Integer |
| 6823 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6824 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6825 | |
| 6826 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6827 ins_encode %{ | |
| 6828 __ movl($mem$$Address, $src$$Register); | |
| 6829 %} | |
| 6830 ins_pipe(ialu_mem_reg); | |
| 6831 %} | |
| 6832 | |
| 0 | 6833 // Volatile Store Long. Must be atomic, so move it into |
| 6834 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6835 // target address before the store (for null-ptr checks) | |
| 6836 // so the memory operand is used twice in the encoding. | |
| 6837 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6838 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6839 match(Set mem (StoreL mem src)); | |
| 6840 effect( KILL cr ); | |
| 6841 ins_cost(400); | |
| 6842 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6843 "FILD $src\n\t" | |
| 6844 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6845 opcode(0x3B); | |
| 6846 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6847 ins_pipe( fpu_reg_mem ); | |
| 6848 %} | |
| 6849 | |
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6850 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6851 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6852 match(Set mem (StoreL mem src)); | |
| 6853 effect( TEMP tmp, KILL cr ); | |
| 6854 ins_cost(380); | |
| 6855 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6856 "MOVSD $tmp,$src\n\t" | |
| 6857 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6858 ins_encode %{ |
| 6859 __ cmpl(rax, $mem$$Address); | |
| 6860 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6861 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6862 %} | |
| 0 | 6863 ins_pipe( pipe_slow ); |
| 6864 %} | |
| 6865 | |
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6866 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6867 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6868 match(Set mem (StoreL mem src)); | |
| 6869 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6870 ins_cost(360); | |
| 6871 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6872 "MOVD $tmp,$src.lo\n\t" | |
| 6873 "MOVD $tmp2,$src.hi\n\t" | |
| 6874 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6875 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6876 ins_encode %{ |
| 6877 __ cmpl(rax, $mem$$Address); | |
| 6878 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6879 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6880 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6881 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6882 %} | |
| 0 | 6883 ins_pipe( pipe_slow ); |
| 6884 %} | |
| 6885 | |
| 6886 // Store Pointer; for storing unknown oops and raw pointers | |
| 6887 instruct storeP(memory mem, anyRegP src) %{ | |
| 6888 match(Set mem (StoreP mem src)); | |
| 6889 | |
| 6890 ins_cost(125); | |
| 6891 format %{ "MOV $mem,$src" %} | |
| 6892 opcode(0x89); | |
| 6893 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6894 ins_pipe( ialu_mem_reg ); | |
| 6895 %} | |
| 6896 | |
| 6897 // Store Integer Immediate | |
| 6898 instruct storeImmI(memory mem, immI src) %{ | |
| 6899 match(Set mem (StoreI mem src)); | |
| 6900 | |
| 6901 ins_cost(150); | |
| 6902 format %{ "MOV $mem,$src" %} | |
| 6903 opcode(0xC7); /* C7 /0 */ | |
| 6904 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6905 ins_pipe( ialu_mem_imm ); | |
| 6906 %} | |
| 6907 | |
| 6908 // Store Short/Char Immediate | |
| 6909 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6910 predicate(UseStoreImmI16); | |
| 6911 match(Set mem (StoreC mem src)); | |
| 6912 | |
| 6913 ins_cost(150); | |
| 6914 format %{ "MOV16 $mem,$src" %} | |
| 6915 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6916 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6917 ins_pipe( ialu_mem_imm ); | |
| 6918 %} | |
| 6919 | |
| 6920 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6921 // need card-mark barriers. | |
| 6922 instruct storeImmP(memory mem, immP src) %{ | |
| 6923 match(Set mem (StoreP mem src)); | |
| 6924 | |
| 6925 ins_cost(150); | |
| 6926 format %{ "MOV $mem,$src" %} | |
| 6927 opcode(0xC7); /* C7 /0 */ | |
| 6928 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6929 ins_pipe( ialu_mem_imm ); | |
| 6930 %} | |
| 6931 | |
| 6932 // Store Byte Immediate | |
| 6933 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6934 match(Set mem (StoreB mem src)); | |
| 6935 | |
| 6936 ins_cost(150); | |
| 6937 format %{ "MOV8 $mem,$src" %} | |
| 6938 opcode(0xC6); /* C6 /0 */ | |
| 6939 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6940 ins_pipe( ialu_mem_imm ); | |
| 6941 %} | |
| 6942 | |
| 6943 // Store CMS card-mark Immediate | |
| 6944 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6945 match(Set mem (StoreCM mem src)); | |
| 6946 | |
| 6947 ins_cost(150); | |
| 6948 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6949 opcode(0xC6); /* C6 /0 */ | |
| 6950 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6951 ins_pipe( ialu_mem_imm ); | |
| 6952 %} | |
| 6953 | |
| 6954 // Store Double | |
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6955 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6956 predicate(UseSSE<=1); |
| 6957 match(Set mem (StoreD mem src)); | |
| 6958 | |
| 6959 ins_cost(100); | |
| 6960 format %{ "FST_D $mem,$src" %} | |
| 6961 opcode(0xDD); /* DD /2 */ | |
|
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6962 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6963 ins_pipe( fpu_mem_reg ); |
| 6964 %} | |
| 6965 | |
| 6966 // Store double does rounding on x86 | |
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6967 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6968 predicate(UseSSE<=1); |
| 6969 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6970 | |
| 6971 ins_cost(100); | |
| 6972 format %{ "FST_D $mem,$src\t# round" %} | |
| 6973 opcode(0xDD); /* DD /2 */ | |
|
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6974 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6975 ins_pipe( fpu_mem_reg ); |
| 6976 %} | |
| 6977 | |
| 6978 // Store XMM register to memory (double-precision floating points) | |
| 6979 // MOVSD instruction | |
|
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6980 instruct storeD(memory mem, regD src) %{ |
| 0 | 6981 predicate(UseSSE>=2); |
| 6982 match(Set mem (StoreD mem src)); | |
| 6983 ins_cost(95); | |
| 6984 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6985 ins_encode %{ |
| 6986 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6987 %} | |
| 0 | 6988 ins_pipe( pipe_slow ); |
| 6989 %} | |
| 6990 | |
| 6991 // Store XMM register to memory (single-precision floating point) | |
| 6992 // MOVSS instruction | |
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6993 instruct storeF(memory mem, regF src) %{ |
| 0 | 6994 predicate(UseSSE>=1); |
| 6995 match(Set mem (StoreF mem src)); | |
| 6996 ins_cost(95); | |
| 6997 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6998 ins_encode %{ |
| 6999 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 7000 %} | |
| 0 | 7001 ins_pipe( pipe_slow ); |
| 7002 %} | |
| 7003 | |
| 7004 // Store Float | |
|
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7005 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 7006 predicate(UseSSE==0); |
| 7007 match(Set mem (StoreF mem src)); | |
| 7008 | |
| 7009 ins_cost(100); | |
| 7010 format %{ "FST_S $mem,$src" %} | |
| 7011 opcode(0xD9); /* D9 /2 */ | |
|
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7012 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7013 ins_pipe( fpu_mem_reg ); |
| 7014 %} | |
| 7015 | |
| 7016 // Store Float does rounding on x86 | |
|
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7017 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 7018 predicate(UseSSE==0); |
| 7019 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7020 | |
| 7021 ins_cost(100); | |
| 7022 format %{ "FST_S $mem,$src\t# round" %} | |
| 7023 opcode(0xD9); /* D9 /2 */ | |
|
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7024 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7025 ins_pipe( fpu_mem_reg ); |
| 7026 %} | |
| 7027 | |
| 7028 // Store Float does rounding on x86 | |
|
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7029 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 7030 predicate(UseSSE<=1); |
| 7031 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7032 | |
| 7033 ins_cost(100); | |
| 7034 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7035 opcode(0xD9); /* D9 /2 */ | |
|
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7036 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7037 ins_pipe( fpu_mem_reg ); |
| 7038 %} | |
| 7039 | |
| 7040 // Store immediate Float value (it is faster than store from FPU register) | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7041 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7042 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7043 match(Set mem (StoreF mem src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7044 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7045 ins_cost(50); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7046 format %{ "MOV $mem,$src\t# store float" %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7047 opcode(0xC7); /* C7 /0 */ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7048 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7049 ins_pipe( ialu_mem_imm ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7050 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7051 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7052 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 7053 // The instruction usage is guarded by predicate in operand immF(). |
| 7054 instruct storeF_imm( memory mem, immF src) %{ | |
| 7055 match(Set mem (StoreF mem src)); | |
| 7056 | |
| 7057 ins_cost(50); | |
| 7058 format %{ "MOV $mem,$src\t# store float" %} | |
| 7059 opcode(0xC7); /* C7 /0 */ | |
| 7060 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7061 ins_pipe( ialu_mem_imm ); | |
| 7062 %} | |
| 7063 | |
| 7064 // Store Integer to stack slot | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
7065 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 7066 match(Set dst src); |
| 7067 | |
| 7068 ins_cost(100); | |
| 7069 format %{ "MOV $dst,$src" %} | |
| 7070 opcode(0x89); | |
| 7071 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7072 ins_pipe( ialu_mem_reg ); | |
| 7073 %} | |
| 7074 | |
| 7075 // Store Integer to stack slot | |
| 7076 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7077 match(Set dst src); | |
| 7078 | |
| 7079 ins_cost(100); | |
| 7080 format %{ "MOV $dst,$src" %} | |
| 7081 opcode(0x89); | |
| 7082 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7083 ins_pipe( ialu_mem_reg ); | |
| 7084 %} | |
| 7085 | |
| 7086 // Store Long to stack slot | |
| 7087 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7088 match(Set dst src); | |
| 7089 | |
| 7090 ins_cost(200); | |
| 7091 format %{ "MOV $dst,$src.lo\n\t" | |
| 7092 "MOV $dst+4,$src.hi" %} | |
| 7093 opcode(0x89, 0x89); | |
| 7094 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7095 ins_pipe( ialu_mem_long_reg ); | |
| 7096 %} | |
| 7097 | |
| 7098 //----------MemBar Instructions----------------------------------------------- | |
| 7099 // Memory barrier flavors | |
| 7100 | |
| 7101 instruct membar_acquire() %{ | |
| 7102 match(MemBarAcquire); | |
| 7103 ins_cost(400); | |
| 7104 | |
| 7105 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7106 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7107 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7108 ins_pipe(empty); |
| 0 | 7109 %} |
| 7110 | |
| 7111 instruct membar_acquire_lock() %{ | |
|
3849
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7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
7112 match(MemBarAcquireLock); |
| 0 | 7113 ins_cost(0); |
| 7114 | |
| 7115 size(0); | |
| 7116 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7117 ins_encode( ); | |
| 7118 ins_pipe(empty); | |
| 7119 %} | |
| 7120 | |
| 7121 instruct membar_release() %{ | |
| 7122 match(MemBarRelease); | |
| 7123 ins_cost(400); | |
| 7124 | |
| 7125 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7126 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7127 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7128 ins_pipe(empty); |
| 0 | 7129 %} |
| 7130 | |
| 7131 instruct membar_release_lock() %{ | |
|
3849
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7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
7132 match(MemBarReleaseLock); |
| 0 | 7133 ins_cost(0); |
| 7134 | |
| 7135 size(0); | |
| 7136 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7137 ins_encode( ); | |
| 7138 ins_pipe(empty); | |
| 7139 %} | |
| 7140 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7141 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7142 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7143 effect(KILL cr); |
| 0 | 7144 ins_cost(400); |
| 7145 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7146 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7147 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7148 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7149 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7150 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7151 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7152 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7153 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7154 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7155 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7156 %} |
| 0 | 7157 ins_pipe(pipe_slow); |
| 7158 %} | |
| 7159 | |
| 7160 instruct unnecessary_membar_volatile() %{ | |
| 7161 match(MemBarVolatile); | |
| 7162 predicate(Matcher::post_store_load_barrier(n)); | |
| 7163 ins_cost(0); | |
| 7164 | |
| 7165 size(0); | |
| 7166 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7167 ins_encode( ); | |
| 7168 ins_pipe(empty); | |
| 7169 %} | |
| 7170 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7171 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7172 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7173 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7174 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7175 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7176 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7177 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7178 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7179 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7180 |
| 0 | 7181 //----------Move Instructions-------------------------------------------------- |
| 7182 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7183 match(Set dst (CastX2P src)); | |
| 7184 format %{ "# X2P $dst, $src" %} | |
| 7185 ins_encode( /*empty encoding*/ ); | |
| 7186 ins_cost(0); | |
| 7187 ins_pipe(empty); | |
| 7188 %} | |
| 7189 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7190 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 7191 match(Set dst (CastP2X src)); |
| 7192 ins_cost(50); | |
| 7193 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7194 ins_encode( enc_Copy( dst, src) ); | |
| 7195 ins_pipe( ialu_reg_reg ); | |
| 7196 %} | |
| 7197 | |
| 7198 //----------Conditional Move--------------------------------------------------- | |
| 7199 // Conditional move | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7200 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 7201 predicate(!VM_Version::supports_cmov() ); |
| 7202 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7203 ins_cost(200); | |
| 7204 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 7205 "MOV $dst,$src\n" | |
| 7206 "skip:" %} | |
| 7207 ins_encode %{ | |
| 7208 Label Lskip; | |
| 7209 // Invert sense of branch from sense of CMOV | |
| 7210 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7211 __ movl($dst$$Register, $src$$Register); | |
| 7212 __ bind(Lskip); | |
| 7213 %} | |
| 7214 ins_pipe( pipe_cmov_reg ); | |
| 7215 %} | |
| 7216 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7217 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 7218 predicate(!VM_Version::supports_cmov() ); |
| 7219 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7220 ins_cost(200); | |
| 7221 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 7222 "MOV $dst,$src\n" | |
| 7223 "skip:" %} | |
| 7224 ins_encode %{ | |
| 7225 Label Lskip; | |
| 7226 // Invert sense of branch from sense of CMOV | |
| 7227 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7228 __ movl($dst$$Register, $src$$Register); | |
| 7229 __ bind(Lskip); | |
| 7230 %} | |
| 7231 ins_pipe( pipe_cmov_reg ); | |
| 7232 %} | |
| 7233 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7234 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 7235 predicate(VM_Version::supports_cmov() ); |
| 7236 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7237 ins_cost(200); | |
| 7238 format %{ "CMOV$cop $dst,$src" %} | |
| 7239 opcode(0x0F,0x40); | |
| 7240 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7241 ins_pipe( pipe_cmov_reg ); | |
| 7242 %} | |
| 7243 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7244 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 7245 predicate(VM_Version::supports_cmov() ); |
| 7246 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7247 ins_cost(200); | |
| 7248 format %{ "CMOV$cop $dst,$src" %} | |
| 7249 opcode(0x0F,0x40); | |
| 7250 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7251 ins_pipe( pipe_cmov_reg ); | |
| 7252 %} | |
| 7253 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7254 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7255 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7256 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7257 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7258 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7259 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7260 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7261 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7262 |
| 0 | 7263 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7264 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7265 predicate(VM_Version::supports_cmov() ); |
| 7266 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7267 ins_cost(250); | |
| 7268 format %{ "CMOV$cop $dst,$src" %} | |
| 7269 opcode(0x0F,0x40); | |
| 7270 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7271 ins_pipe( pipe_cmov_mem ); | |
| 7272 %} | |
| 7273 | |
| 7274 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7275 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 7276 predicate(VM_Version::supports_cmov() ); |
| 7277 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7278 ins_cost(250); | |
| 7279 format %{ "CMOV$cop $dst,$src" %} | |
| 7280 opcode(0x0F,0x40); | |
| 7281 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7282 ins_pipe( pipe_cmov_mem ); | |
| 7283 %} | |
| 7284 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7285 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7286 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7287 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7288 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7289 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7290 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7291 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7292 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7293 |
| 0 | 7294 // Conditional move |
| 7295 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7296 predicate(VM_Version::supports_cmov() ); | |
| 7297 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7298 ins_cost(200); | |
| 7299 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7300 opcode(0x0F,0x40); | |
| 7301 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7302 ins_pipe( pipe_cmov_reg ); | |
| 7303 %} | |
| 7304 | |
| 7305 // Conditional move (non-P6 version) | |
| 7306 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7307 // regardless of whether we are on a P6, so we | |
| 7308 // emulate a cmov here | |
| 7309 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7310 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7311 ins_cost(300); | |
| 7312 format %{ "Jn$cop skip\n\t" | |
| 7313 "MOV $dst,$src\t# pointer\n" | |
| 7314 "skip:" %} | |
| 7315 opcode(0x8b); | |
| 7316 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7317 ins_pipe( pipe_cmov_reg ); | |
| 7318 %} | |
| 7319 | |
| 7320 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
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changeset
|
7321 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7322 predicate(VM_Version::supports_cmov() ); |
| 7323 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7324 ins_cost(200); | |
| 7325 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7326 opcode(0x0F,0x40); | |
| 7327 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7328 ins_pipe( pipe_cmov_reg ); | |
| 7329 %} | |
| 7330 | |
|
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|
7331 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
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changeset
|
7332 predicate(VM_Version::supports_cmov() ); |
|
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|
7333 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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|
7334 ins_cost(200); |
|
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diff
changeset
|
7335 expand %{ |
|
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diff
changeset
|
7336 cmovP_regU(cop, cr, dst, src); |
|
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changeset
|
7337 %} |
|
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diff
changeset
|
7338 %} |
|
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diff
changeset
|
7339 |
| 0 | 7340 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7341 // correctly meets the two pointer arguments; one is an incoming | |
| 7342 // register but the other is a memory operand. ALSO appears to | |
| 7343 // be buggy with implicit null checks. | |
| 7344 // | |
| 7345 //// Conditional move | |
| 7346 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7347 // predicate(VM_Version::supports_cmov() ); | |
| 7348 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7349 // ins_cost(250); | |
| 7350 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7351 // opcode(0x0F,0x40); | |
| 7352 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7353 // ins_pipe( pipe_cmov_mem ); | |
| 7354 //%} | |
| 7355 // | |
| 7356 //// Conditional move | |
| 7357 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 7358 // predicate(VM_Version::supports_cmov() ); | |
| 7359 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7360 // ins_cost(250); | |
| 7361 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7362 // opcode(0x0F,0x40); | |
| 7363 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7364 // ins_pipe( pipe_cmov_mem ); | |
| 7365 //%} | |
| 7366 | |
| 7367 // Conditional move | |
|
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|
7368 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 7369 predicate(UseSSE<=1); |
| 7370 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7371 ins_cost(200); | |
| 7372 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 7373 opcode(0xDA); | |
|
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|
7374 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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|
7375 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7376 %} |
| 7377 | |
| 7378 // Conditional move | |
|
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|
7379 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 7380 predicate(UseSSE==0); |
| 7381 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7382 ins_cost(200); | |
| 7383 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 7384 opcode(0xDA); | |
|
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changeset
|
7385 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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changeset
|
7386 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7387 %} |
| 7388 | |
| 7389 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
7390 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 7391 predicate(UseSSE<=1); |
| 7392 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7393 ins_cost(200); | |
| 7394 format %{ "Jn$cop skip\n\t" | |
| 7395 "MOV $dst,$src\t# double\n" | |
| 7396 "skip:" %} | |
| 7397 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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changeset
|
7398 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
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|
7399 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7400 %} |
| 7401 | |
| 7402 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
7403 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 7404 predicate(UseSSE==0); |
| 7405 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7406 ins_cost(200); | |
| 7407 format %{ "Jn$cop skip\n\t" | |
| 7408 "MOV $dst,$src\t# float\n" | |
| 7409 "skip:" %} | |
| 7410 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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diff
changeset
|
7411 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
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diff
changeset
|
7412 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7413 %} |
| 7414 | |
| 7415 // No CMOVE with SSE/SSE2 | |
|
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changeset
|
7416 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 7417 predicate (UseSSE>=1); |
| 7418 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7419 ins_cost(200); | |
| 7420 format %{ "Jn$cop skip\n\t" | |
| 7421 "MOVSS $dst,$src\t# float\n" | |
| 7422 "skip:" %} | |
| 7423 ins_encode %{ | |
| 7424 Label skip; | |
| 7425 // Invert sense of branch from sense of CMOV | |
| 7426 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7427 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7428 __ bind(skip); | |
| 7429 %} | |
| 7430 ins_pipe( pipe_slow ); | |
| 7431 %} | |
| 7432 | |
| 7433 // No CMOVE with SSE/SSE2 | |
|
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changeset
|
7434 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 7435 predicate (UseSSE>=2); |
| 7436 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7437 ins_cost(200); | |
| 7438 format %{ "Jn$cop skip\n\t" | |
| 7439 "MOVSD $dst,$src\t# float\n" | |
| 7440 "skip:" %} | |
| 7441 ins_encode %{ | |
| 7442 Label skip; | |
| 7443 // Invert sense of branch from sense of CMOV | |
| 7444 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7445 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7446 __ bind(skip); | |
| 7447 %} | |
| 7448 ins_pipe( pipe_slow ); | |
| 7449 %} | |
| 7450 | |
| 7451 // unsigned version | |
|
4761
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diff
changeset
|
7452 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 7453 predicate (UseSSE>=1); |
| 7454 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7455 ins_cost(200); | |
| 7456 format %{ "Jn$cop skip\n\t" | |
| 7457 "MOVSS $dst,$src\t# float\n" | |
| 7458 "skip:" %} | |
| 7459 ins_encode %{ | |
| 7460 Label skip; | |
| 7461 // Invert sense of branch from sense of CMOV | |
| 7462 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7463 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7464 __ bind(skip); | |
| 7465 %} | |
| 7466 ins_pipe( pipe_slow ); | |
| 7467 %} | |
| 7468 | |
|
4761
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kvn
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diff
changeset
|
7469 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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403
diff
changeset
|
7470 predicate (UseSSE>=1); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7471 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7472 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7473 expand %{ |
|
4761
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kvn
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diff
changeset
|
7474 fcmovF_regU(cop, cr, dst, src); |
|
415
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parents:
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diff
changeset
|
7475 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7476 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7477 |
| 0 | 7478 // unsigned version |
|
4761
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diff
changeset
|
7479 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 7480 predicate (UseSSE>=2); |
| 7481 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7482 ins_cost(200); | |
| 7483 format %{ "Jn$cop skip\n\t" | |
| 7484 "MOVSD $dst,$src\t# float\n" | |
| 7485 "skip:" %} | |
| 7486 ins_encode %{ | |
| 7487 Label skip; | |
| 7488 // Invert sense of branch from sense of CMOV | |
| 7489 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7490 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7491 __ bind(skip); | |
| 7492 %} | |
| 7493 ins_pipe( pipe_slow ); | |
| 7494 %} | |
| 7495 | |
|
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diff
changeset
|
7496 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
4d9884b01ba6
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parents:
403
diff
changeset
|
7497 predicate (UseSSE>=2); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7498 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7499 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7500 expand %{ |
|
4761
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diff
changeset
|
7501 fcmovD_regU(cop, cr, dst, src); |
|
415
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parents:
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diff
changeset
|
7502 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7503 %} |
|
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parents:
403
diff
changeset
|
7504 |
| 0 | 7505 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 7506 predicate(VM_Version::supports_cmov() ); | |
| 7507 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7508 ins_cost(200); | |
| 7509 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7510 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7511 opcode(0x0F,0x40); | |
| 7512 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7513 ins_pipe( pipe_cmov_reg_long ); | |
| 7514 %} | |
| 7515 | |
| 7516 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 7517 predicate(VM_Version::supports_cmov() ); | |
| 7518 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7519 ins_cost(200); | |
| 7520 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7521 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7522 opcode(0x0F,0x40); | |
| 7523 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7524 ins_pipe( pipe_cmov_reg_long ); | |
| 7525 %} | |
| 7526 | |
|
415
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403
diff
changeset
|
7527 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7528 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7529 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7530 ins_cost(200); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7531 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7532 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7533 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7534 %} |
|
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403
diff
changeset
|
7535 |
| 0 | 7536 //----------Arithmetic Instructions-------------------------------------------- |
| 7537 //----------Addition Instructions---------------------------------------------- | |
| 7538 // Integer Addition Instructions | |
|
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changeset
|
7539 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7540 match(Set dst (AddI dst src)); |
| 7541 effect(KILL cr); | |
| 7542 | |
| 7543 size(2); | |
| 7544 format %{ "ADD $dst,$src" %} | |
| 7545 opcode(0x03); | |
| 7546 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7547 ins_pipe( ialu_reg_reg ); | |
| 7548 %} | |
| 7549 | |
|
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diff
changeset
|
7550 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7551 match(Set dst (AddI dst src)); |
| 7552 effect(KILL cr); | |
| 7553 | |
| 7554 format %{ "ADD $dst,$src" %} | |
| 7555 opcode(0x81, 0x00); /* /0 id */ | |
| 7556 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7557 ins_pipe( ialu_reg ); | |
| 7558 %} | |
| 7559 | |
|
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diff
changeset
|
7560 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7561 predicate(UseIncDec); |
| 7562 match(Set dst (AddI dst src)); | |
| 7563 effect(KILL cr); | |
| 7564 | |
| 7565 size(1); | |
| 7566 format %{ "INC $dst" %} | |
| 7567 opcode(0x40); /* */ | |
| 7568 ins_encode( Opc_plus( primary, dst ) ); | |
| 7569 ins_pipe( ialu_reg ); | |
| 7570 %} | |
| 7571 | |
|
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changeset
|
7572 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7573 match(Set dst (AddI src0 src1)); |
| 7574 ins_cost(110); | |
| 7575 | |
| 7576 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7577 opcode(0x8D); /* 0x8D /r */ | |
| 7578 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7579 ins_pipe( ialu_reg_reg ); | |
| 7580 %} | |
| 7581 | |
| 7582 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7583 match(Set dst (AddP src0 src1)); | |
| 7584 ins_cost(110); | |
| 7585 | |
| 7586 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7587 opcode(0x8D); /* 0x8D /r */ | |
| 7588 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7589 ins_pipe( ialu_reg_reg ); | |
| 7590 %} | |
| 7591 | |
|
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diff
changeset
|
7592 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7593 predicate(UseIncDec); |
| 7594 match(Set dst (AddI dst src)); | |
| 7595 effect(KILL cr); | |
| 7596 | |
| 7597 size(1); | |
| 7598 format %{ "DEC $dst" %} | |
| 7599 opcode(0x48); /* */ | |
| 7600 ins_encode( Opc_plus( primary, dst ) ); | |
| 7601 ins_pipe( ialu_reg ); | |
| 7602 %} | |
| 7603 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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|
7604 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7605 match(Set dst (AddP dst src)); |
| 7606 effect(KILL cr); | |
| 7607 | |
| 7608 size(2); | |
| 7609 format %{ "ADD $dst,$src" %} | |
| 7610 opcode(0x03); | |
| 7611 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7612 ins_pipe( ialu_reg_reg ); | |
| 7613 %} | |
| 7614 | |
| 7615 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7616 match(Set dst (AddP dst src)); | |
| 7617 effect(KILL cr); | |
| 7618 | |
| 7619 format %{ "ADD $dst,$src" %} | |
| 7620 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7621 // ins_encode( RegImm( dst, src) ); | |
| 7622 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7623 ins_pipe( ialu_reg ); | |
| 7624 %} | |
| 7625 | |
|
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|
7626 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7627 match(Set dst (AddI dst (LoadI src))); |
| 7628 effect(KILL cr); | |
| 7629 | |
| 7630 ins_cost(125); | |
| 7631 format %{ "ADD $dst,$src" %} | |
| 7632 opcode(0x03); | |
| 7633 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7634 ins_pipe( ialu_reg_mem ); | |
| 7635 %} | |
| 7636 | |
|
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7637 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7638 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7639 effect(KILL cr); | |
| 7640 | |
| 7641 ins_cost(150); | |
| 7642 format %{ "ADD $dst,$src" %} | |
| 7643 opcode(0x01); /* Opcode 01 /r */ | |
| 7644 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7645 ins_pipe( ialu_mem_reg ); | |
| 7646 %} | |
| 7647 | |
| 7648 // Add Memory with Immediate | |
| 7649 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7650 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7651 effect(KILL cr); | |
| 7652 | |
| 7653 ins_cost(125); | |
| 7654 format %{ "ADD $dst,$src" %} | |
| 7655 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7656 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7657 ins_pipe( ialu_mem_imm ); | |
| 7658 %} | |
| 7659 | |
| 7660 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7661 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7662 effect(KILL cr); | |
| 7663 | |
| 7664 ins_cost(125); | |
| 7665 format %{ "INC $dst" %} | |
| 7666 opcode(0xFF); /* Opcode FF /0 */ | |
| 7667 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7668 ins_pipe( ialu_mem_imm ); | |
| 7669 %} | |
| 7670 | |
| 7671 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7672 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7673 effect(KILL cr); | |
| 7674 | |
| 7675 ins_cost(125); | |
| 7676 format %{ "DEC $dst" %} | |
| 7677 opcode(0xFF); /* Opcode FF /1 */ | |
| 7678 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7679 ins_pipe( ialu_mem_imm ); | |
| 7680 %} | |
| 7681 | |
| 7682 | |
| 7683 instruct checkCastPP( eRegP dst ) %{ | |
| 7684 match(Set dst (CheckCastPP dst)); | |
| 7685 | |
| 7686 size(0); | |
| 7687 format %{ "#checkcastPP of $dst" %} | |
| 7688 ins_encode( /*empty encoding*/ ); | |
| 7689 ins_pipe( empty ); | |
| 7690 %} | |
| 7691 | |
| 7692 instruct castPP( eRegP dst ) %{ | |
| 7693 match(Set dst (CastPP dst)); | |
| 7694 format %{ "#castPP of $dst" %} | |
| 7695 ins_encode( /*empty encoding*/ ); | |
| 7696 ins_pipe( empty ); | |
| 7697 %} | |
| 7698 | |
|
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7699 instruct castII( rRegI dst ) %{ |
| 0 | 7700 match(Set dst (CastII dst)); |
| 7701 format %{ "#castII of $dst" %} | |
| 7702 ins_encode( /*empty encoding*/ ); | |
| 7703 ins_cost(0); | |
| 7704 ins_pipe( empty ); | |
| 7705 %} | |
| 7706 | |
| 7707 | |
| 7708 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7709 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7710 match(Set dst (LoadPLocked mem)); | |
| 7711 | |
| 7712 ins_cost(125); | |
| 7713 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7714 opcode(0x8B); | |
| 7715 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7716 ins_pipe( ialu_reg_mem ); | |
| 7717 %} | |
| 7718 | |
| 7719 // Conditional-store of the updated heap-top. | |
| 7720 // Used during allocation of the shared heap. | |
| 7721 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7722 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7723 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7724 // EAX is killed if there is contention, but then it's also unused. | |
| 7725 // In the common case of no contention, EAX holds the new oop address. | |
| 7726 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7727 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7728 ins_pipe( pipe_cmpxchg ); | |
| 7729 %} | |
| 7730 | |
|
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|
7731 // Conditional-store of an int value. |
|
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|
7732 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
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7733 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
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|
7734 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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|
7735 effect(KILL oldval); |
|
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|
7736 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
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|
7737 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7738 ins_pipe( pipe_cmpxchg ); |
| 7739 %} | |
| 7740 | |
|
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|
7741 // Conditional-store of a long value. |
|
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|
7742 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
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|
7743 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
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|
7744 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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|
7745 effect(KILL oldval); |
|
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|
7746 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
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|
7747 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
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|
7748 "XCHG EBX,ECX" |
|
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|
7749 %} |
|
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|
7750 ins_encode %{ |
|
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|
7751 // Note: we need to swap rbx, and rcx before and after the |
|
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|
7752 // cmpxchg8 instruction because the instruction uses |
|
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|
7753 // rcx as the high order word of the new value to store but |
|
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|
7754 // our register encoding uses rbx. |
|
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|
7755 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
7756 if( os::is_MP() ) |
|
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|
7757 __ lock(); |
| 624 | 7758 __ cmpxchg8($mem$$Address); |
|
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|
7759 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
7760 %} |
| 0 | 7761 ins_pipe( pipe_cmpxchg ); |
| 7762 %} | |
| 7763 | |
| 7764 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7765 | |
|
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7766 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
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|
7767 predicate(VM_Version::supports_cx8()); |
| 0 | 7768 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7769 effect(KILL cr, KILL oldval); | |
| 7770 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7771 "MOV $res,0\n\t" | |
| 7772 "JNE,s fail\n\t" | |
| 7773 "MOV $res,1\n" | |
| 7774 "fail:" %} | |
| 7775 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7776 enc_flags_ne_to_boolean(res) ); | |
| 7777 ins_pipe( pipe_cmpxchg ); | |
| 7778 %} | |
| 7779 | |
|
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|
7780 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7781 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7782 effect(KILL cr, KILL oldval); | |
| 7783 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7784 "MOV $res,0\n\t" | |
| 7785 "JNE,s fail\n\t" | |
| 7786 "MOV $res,1\n" | |
| 7787 "fail:" %} | |
| 7788 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7789 ins_pipe( pipe_cmpxchg ); | |
| 7790 %} | |
| 7791 | |
|
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|
7792 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7793 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7794 effect(KILL cr, KILL oldval); | |
| 7795 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7796 "MOV $res,0\n\t" | |
| 7797 "JNE,s fail\n\t" | |
| 7798 "MOV $res,1\n" | |
| 7799 "fail:" %} | |
| 7800 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7801 ins_pipe( pipe_cmpxchg ); | |
| 7802 %} | |
| 7803 | |
|
6795
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|
7804 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
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|
7805 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
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|
7806 match(Set dummy (GetAndAddI mem add)); |
|
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|
7807 effect(KILL cr); |
|
7eca5de9e0b6
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|
7808 format %{ "ADDL [$mem],$add" %} |
|
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|
7809 ins_encode %{ |
|
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|
7810 if (os::is_MP()) { __ lock(); } |
|
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|
7811 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7812 %} |
|
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changeset
|
7813 ins_pipe( pipe_cmpxchg ); |
|
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|
7814 %} |
|
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|
7815 |
|
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|
7816 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
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|
7817 match(Set newval (GetAndAddI mem newval)); |
|
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|
7818 effect(KILL cr); |
|
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|
7819 format %{ "XADDL [$mem],$newval" %} |
|
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|
7820 ins_encode %{ |
|
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|
7821 if (os::is_MP()) { __ lock(); } |
|
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|
7822 __ xaddl($mem$$Address, $newval$$Register); |
|
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|
7823 %} |
|
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changeset
|
7824 ins_pipe( pipe_cmpxchg ); |
|
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|
7825 %} |
|
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changeset
|
7826 |
|
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changeset
|
7827 instruct xchgI( memory mem, rRegI newval) %{ |
|
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|
7828 match(Set newval (GetAndSetI mem newval)); |
|
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|
7829 format %{ "XCHGL $newval,[$mem]" %} |
|
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|
7830 ins_encode %{ |
|
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|
7831 __ xchgl($newval$$Register, $mem$$Address); |
|
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|
7832 %} |
|
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changeset
|
7833 ins_pipe( pipe_cmpxchg ); |
|
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|
7834 %} |
|
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changeset
|
7835 |
|
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changeset
|
7836 instruct xchgP( memory mem, pRegP newval) %{ |
|
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|
7837 match(Set newval (GetAndSetP mem newval)); |
|
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changeset
|
7838 format %{ "XCHGL $newval,[$mem]" %} |
|
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|
7839 ins_encode %{ |
|
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changeset
|
7840 __ xchgl($newval$$Register, $mem$$Address); |
|
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|
7841 %} |
|
7eca5de9e0b6
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changeset
|
7842 ins_pipe( pipe_cmpxchg ); |
|
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7843 %} |
|
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|
7844 |
| 0 | 7845 //----------Subtraction Instructions------------------------------------------- |
| 7846 // Integer Subtraction Instructions | |
|
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7847 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7848 match(Set dst (SubI dst src)); |
| 7849 effect(KILL cr); | |
| 7850 | |
| 7851 size(2); | |
| 7852 format %{ "SUB $dst,$src" %} | |
| 7853 opcode(0x2B); | |
| 7854 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7855 ins_pipe( ialu_reg_reg ); | |
| 7856 %} | |
| 7857 | |
|
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7858 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7859 match(Set dst (SubI dst src)); |
| 7860 effect(KILL cr); | |
| 7861 | |
| 7862 format %{ "SUB $dst,$src" %} | |
| 7863 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7864 // ins_encode( RegImm( dst, src) ); | |
| 7865 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7866 ins_pipe( ialu_reg ); | |
| 7867 %} | |
| 7868 | |
|
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|
7869 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7870 match(Set dst (SubI dst (LoadI src))); |
| 7871 effect(KILL cr); | |
| 7872 | |
| 7873 ins_cost(125); | |
| 7874 format %{ "SUB $dst,$src" %} | |
| 7875 opcode(0x2B); | |
| 7876 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7877 ins_pipe( ialu_reg_mem ); | |
| 7878 %} | |
| 7879 | |
|
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7880 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7881 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7882 effect(KILL cr); | |
| 7883 | |
| 7884 ins_cost(150); | |
| 7885 format %{ "SUB $dst,$src" %} | |
| 7886 opcode(0x29); /* Opcode 29 /r */ | |
| 7887 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7888 ins_pipe( ialu_mem_reg ); | |
| 7889 %} | |
| 7890 | |
| 7891 // Subtract from a pointer | |
|
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7892 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7893 match(Set dst (AddP dst (SubI zero src))); |
| 7894 effect(KILL cr); | |
| 7895 | |
| 7896 size(2); | |
| 7897 format %{ "SUB $dst,$src" %} | |
| 7898 opcode(0x2B); | |
| 7899 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7900 ins_pipe( ialu_reg_reg ); | |
| 7901 %} | |
| 7902 | |
|
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7903 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7904 match(Set dst (SubI zero dst)); |
| 7905 effect(KILL cr); | |
| 7906 | |
| 7907 size(2); | |
| 7908 format %{ "NEG $dst" %} | |
| 7909 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7910 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7911 ins_pipe( ialu_reg ); | |
| 7912 %} | |
| 7913 | |
| 7914 | |
| 7915 //----------Multiplication/Division Instructions------------------------------- | |
| 7916 // Integer Multiplication Instructions | |
| 7917 // Multiply Register | |
|
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7918 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7919 match(Set dst (MulI dst src)); |
| 7920 effect(KILL cr); | |
| 7921 | |
| 7922 size(3); | |
| 7923 ins_cost(300); | |
| 7924 format %{ "IMUL $dst,$src" %} | |
| 7925 opcode(0xAF, 0x0F); | |
| 7926 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7927 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7928 %} | |
| 7929 | |
| 7930 // Multiply 32-bit Immediate | |
|
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7931 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7932 match(Set dst (MulI src imm)); |
| 7933 effect(KILL cr); | |
| 7934 | |
| 7935 ins_cost(300); | |
| 7936 format %{ "IMUL $dst,$src,$imm" %} | |
| 7937 opcode(0x69); /* 69 /r id */ | |
| 7938 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7939 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7940 %} | |
| 7941 | |
| 7942 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7943 match(Set dst src); | |
| 7944 effect(KILL cr); | |
| 7945 | |
| 7946 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7947 ins_cost(250); | |
| 7948 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7949 opcode(0xB8); | |
| 7950 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7951 ins_pipe( ialu_reg_fat ); | |
| 7952 %} | |
| 7953 | |
| 7954 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7955 // (special case for shift by 32) | |
| 7956 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7957 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7958 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7959 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7960 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7961 effect(USE src1, KILL cr); | |
| 7962 | |
| 7963 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7964 ins_cost(0*100 + 1*400 - 150); | |
| 7965 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7966 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7967 ins_pipe( pipe_slow ); | |
| 7968 %} | |
| 7969 | |
| 7970 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7971 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7972 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7973 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7974 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7975 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7976 effect(USE src1, KILL cr); | |
| 7977 | |
| 7978 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7979 ins_cost(1*100 + 1*400 - 150); | |
| 7980 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7981 "SAR EDX,$cnt-32" %} | |
| 7982 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7983 ins_pipe( pipe_slow ); | |
| 7984 %} | |
| 7985 | |
| 7986 // Multiply Memory 32-bit Immediate | |
|
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7987 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7988 match(Set dst (MulI (LoadI src) imm)); |
| 7989 effect(KILL cr); | |
| 7990 | |
| 7991 ins_cost(300); | |
| 7992 format %{ "IMUL $dst,$src,$imm" %} | |
| 7993 opcode(0x69); /* 69 /r id */ | |
| 7994 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7995 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7996 %} | |
| 7997 | |
| 7998 // Multiply Memory | |
|
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7999 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8000 match(Set dst (MulI dst (LoadI src))); |
| 8001 effect(KILL cr); | |
| 8002 | |
| 8003 ins_cost(350); | |
| 8004 format %{ "IMUL $dst,$src" %} | |
| 8005 opcode(0xAF, 0x0F); | |
| 8006 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8007 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8008 %} | |
| 8009 | |
| 8010 // Multiply Register Int to Long | |
| 8011 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8012 // Basic Idea: long = (long)int * (long)int | |
| 8013 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8014 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8015 | |
| 8016 ins_cost(300); | |
| 8017 format %{ "IMUL $dst,$src1" %} | |
| 8018 | |
| 8019 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8020 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8021 %} | |
| 8022 | |
| 8023 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8024 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8025 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8026 effect(KILL flags); | |
| 8027 | |
| 8028 ins_cost(300); | |
| 8029 format %{ "MUL $dst,$src1" %} | |
| 8030 | |
| 8031 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8032 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8033 %} | |
| 8034 | |
| 8035 // Multiply Register Long | |
|
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8036 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 8037 match(Set dst (MulL dst src)); |
| 8038 effect(KILL cr, TEMP tmp); | |
| 8039 ins_cost(4*100+3*400); | |
| 8040 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8041 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8042 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8043 "IMUL $tmp,EDX\n\t" | |
| 8044 "MOV EDX,$src.hi\n\t" | |
| 8045 "IMUL EDX,EAX\n\t" | |
| 8046 "ADD $tmp,EDX\n\t" | |
| 8047 "MUL EDX:EAX,$src.lo\n\t" | |
| 8048 "ADD EDX,$tmp" %} | |
| 8049 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8050 ins_pipe( pipe_slow ); | |
| 8051 %} | |
| 8052 | |
|
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8053 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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8054 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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8055 predicate(is_operand_hi32_zero(n->in(1))); |
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|
8056 match(Set dst (MulL dst src)); |
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|
8057 effect(KILL cr, TEMP tmp); |
|
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|
8058 ins_cost(2*100+2*400); |
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|
8059 // Basic idea: lo(result) = lo(x_lo * y_lo) |
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8060 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
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8061 format %{ "MOV $tmp,$src.hi\n\t" |
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|
8062 "IMUL $tmp,EAX\n\t" |
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|
8063 "MUL EDX:EAX,$src.lo\n\t" |
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|
8064 "ADD EDX,$tmp" %} |
|
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|
8065 ins_encode %{ |
|
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|
8066 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
8067 __ imull($tmp$$Register, rax); |
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|
8068 __ mull($src$$Register); |
|
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|
8069 __ addl(rdx, $tmp$$Register); |
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|
8070 %} |
|
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|
8071 ins_pipe( pipe_slow ); |
|
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|
8072 %} |
|
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|
8073 |
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8074 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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8075 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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8076 predicate(is_operand_hi32_zero(n->in(2))); |
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|
8077 match(Set dst (MulL dst src)); |
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8078 effect(KILL cr, TEMP tmp); |
|
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|
8079 ins_cost(2*100+2*400); |
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8080 // Basic idea: lo(result) = lo(x_lo * y_lo) |
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8081 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
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8082 format %{ "MOV $tmp,$src.lo\n\t" |
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8083 "IMUL $tmp,EDX\n\t" |
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8084 "MUL EDX:EAX,$src.lo\n\t" |
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8085 "ADD EDX,$tmp" %} |
|
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|
8086 ins_encode %{ |
|
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|
8087 __ movl($tmp$$Register, $src$$Register); |
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8088 __ imull($tmp$$Register, rdx); |
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8089 __ mull($src$$Register); |
|
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8090 __ addl(rdx, $tmp$$Register); |
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|
8091 %} |
|
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|
8092 ins_pipe( pipe_slow ); |
|
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|
8093 %} |
|
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|
8094 |
|
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8095 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
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8096 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
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8097 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
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|
8098 match(Set dst (MulL dst src)); |
|
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|
8099 effect(KILL cr); |
|
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|
8100 ins_cost(1*400); |
|
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|
8101 // Basic idea: lo(result) = lo(x_lo * y_lo) |
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8102 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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|
8103 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
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8104 ins_encode %{ |
|
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8105 __ mull($src$$Register); |
|
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8106 %} |
|
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|
8107 ins_pipe( pipe_slow ); |
|
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changeset
|
8108 %} |
|
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|
8109 |
| 0 | 8110 // Multiply Register Long by small constant |
|
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|
8111 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 8112 match(Set dst (MulL dst src)); |
| 8113 effect(KILL cr, TEMP tmp); | |
| 8114 ins_cost(2*100+2*400); | |
| 8115 size(12); | |
| 8116 // Basic idea: lo(result) = lo(src * EAX) | |
| 8117 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8118 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8119 "MOV EDX,$src\n\t" | |
| 8120 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8121 "ADD EDX,$tmp" %} | |
| 8122 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8123 ins_pipe( pipe_slow ); | |
| 8124 %} | |
| 8125 | |
| 8126 // Integer DIV with Register | |
| 8127 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8128 match(Set rax (DivI rax div)); | |
| 8129 effect(KILL rdx, KILL cr); | |
| 8130 size(26); | |
| 8131 ins_cost(30*100+10*100); | |
| 8132 format %{ "CMP EAX,0x80000000\n\t" | |
| 8133 "JNE,s normal\n\t" | |
| 8134 "XOR EDX,EDX\n\t" | |
| 8135 "CMP ECX,-1\n\t" | |
| 8136 "JE,s done\n" | |
| 8137 "normal: CDQ\n\t" | |
| 8138 "IDIV $div\n\t" | |
| 8139 "done:" %} | |
| 8140 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8141 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8142 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8143 %} | |
| 8144 | |
| 8145 // Divide Register Long | |
| 8146 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8147 match(Set dst (DivL src1 src2)); | |
| 8148 effect( KILL cr, KILL cx, KILL bx ); | |
| 8149 ins_cost(10000); | |
| 8150 format %{ "PUSH $src1.hi\n\t" | |
| 8151 "PUSH $src1.lo\n\t" | |
| 8152 "PUSH $src2.hi\n\t" | |
| 8153 "PUSH $src2.lo\n\t" | |
| 8154 "CALL SharedRuntime::ldiv\n\t" | |
| 8155 "ADD ESP,16" %} | |
| 8156 ins_encode( long_div(src1,src2) ); | |
| 8157 ins_pipe( pipe_slow ); | |
| 8158 %} | |
| 8159 | |
| 8160 // Integer DIVMOD with Register, both quotient and mod results | |
| 8161 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8162 match(DivModI rax div); | |
| 8163 effect(KILL cr); | |
| 8164 size(26); | |
| 8165 ins_cost(30*100+10*100); | |
| 8166 format %{ "CMP EAX,0x80000000\n\t" | |
| 8167 "JNE,s normal\n\t" | |
| 8168 "XOR EDX,EDX\n\t" | |
| 8169 "CMP ECX,-1\n\t" | |
| 8170 "JE,s done\n" | |
| 8171 "normal: CDQ\n\t" | |
| 8172 "IDIV $div\n\t" | |
| 8173 "done:" %} | |
| 8174 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8175 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8176 ins_pipe( pipe_slow ); | |
| 8177 %} | |
| 8178 | |
| 8179 // Integer MOD with Register | |
| 8180 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8181 match(Set rdx (ModI rax div)); | |
| 8182 effect(KILL rax, KILL cr); | |
| 8183 | |
| 8184 size(26); | |
| 8185 ins_cost(300); | |
| 8186 format %{ "CDQ\n\t" | |
| 8187 "IDIV $div" %} | |
| 8188 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8189 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8190 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8191 %} | |
| 8192 | |
| 8193 // Remainder Register Long | |
| 8194 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8195 match(Set dst (ModL src1 src2)); | |
| 8196 effect( KILL cr, KILL cx, KILL bx ); | |
| 8197 ins_cost(10000); | |
| 8198 format %{ "PUSH $src1.hi\n\t" | |
| 8199 "PUSH $src1.lo\n\t" | |
| 8200 "PUSH $src2.hi\n\t" | |
| 8201 "PUSH $src2.lo\n\t" | |
| 8202 "CALL SharedRuntime::lrem\n\t" | |
| 8203 "ADD ESP,16" %} | |
| 8204 ins_encode( long_mod(src1,src2) ); | |
| 8205 ins_pipe( pipe_slow ); | |
| 8206 %} | |
| 8207 | |
|
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|
8208 // Divide Register Long (no special case since divisor != -1) |
|
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|
8209 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
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|
8210 match(Set dst (DivL dst imm)); |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8211 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
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|
8212 ins_cost(1000); |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8213 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 8214 "XOR $tmp2,$tmp2\n\t" |
|
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|
8215 "CMP $tmp,EDX\n\t" |
|
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|
8216 "JA,s fast\n\t" |
|
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|
8217 "MOV $tmp2,EAX\n\t" |
|
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|
8218 "MOV EAX,EDX\n\t" |
| 1920 | 8219 "MOV EDX,0\n\t" |
| 8220 "JLE,s pos\n\t" | |
| 8221 "LNEG EAX : $tmp2\n\t" | |
| 8222 "DIV $tmp # unsigned division\n\t" | |
| 8223 "XCHG EAX,$tmp2\n\t" | |
| 8224 "DIV $tmp\n\t" | |
| 8225 "LNEG $tmp2 : EAX\n\t" | |
|
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|
8226 "JMP,s done\n" |
| 1920 | 8227 "pos:\n\t" |
| 8228 "DIV $tmp\n\t" | |
| 8229 "XCHG EAX,$tmp2\n" | |
|
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|
8230 "fast:\n\t" |
| 1920 | 8231 "DIV $tmp\n" |
|
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|
8232 "done:\n\t" |
| 1920 | 8233 "MOV EDX,$tmp2\n\t" |
|
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|
8234 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
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|
8235 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8236 int con = (int)$imm$$constant; |
|
ae065c367d93
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|
8237 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
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|
8238 int pcon = (con > 0) ? con : -con; |
| 1920 | 8239 Label Lfast, Lpos, Ldone; |
|
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|
8240 |
|
ae065c367d93
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|
8241 __ movl($tmp$$Register, pcon); |
| 1920 | 8242 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
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|
8243 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8244 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
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|
8245 |
|
ae065c367d93
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|
8246 __ movl($tmp2$$Register, $dst$$Register); // save |
|
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kvn
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|
8247 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8248 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8249 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8250 | |
| 8251 // Negative dividend. | |
| 8252 // convert value to positive to use unsigned division | |
| 8253 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8254 __ divl($tmp$$Register); | |
|
1914
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|
8255 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 8256 __ divl($tmp$$Register); |
| 8257 // revert result back to negative | |
| 8258 __ lneg($tmp2$$Register, $dst$$Register); | |
|
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|
8259 __ jmpb(Ldone); |
|
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|
8260 |
| 1920 | 8261 __ bind(Lpos); |
| 8262 __ divl($tmp$$Register); // Use unsigned division | |
| 8263 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 8264 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 8265 | |
|
1914
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|
8266 __ bind(Lfast); |
| 1920 | 8267 // fast path: src is positive |
| 8268 __ divl($tmp$$Register); // Use unsigned division | |
|
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|
8269 |
|
ae065c367d93
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|
8270 __ bind(Ldone); |
| 1920 | 8271 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
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|
8272 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8273 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
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|
8274 } |
|
ae065c367d93
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kvn
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|
8275 %} |
|
ae065c367d93
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kvn
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|
8276 ins_pipe( pipe_slow ); |
|
ae065c367d93
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kvn
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|
8277 %} |
|
ae065c367d93
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|
8278 |
|
ae065c367d93
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|
8279 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
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|
8280 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
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|
8281 match(Set dst (ModL dst imm)); |
|
ae065c367d93
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|
8282 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
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|
8283 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8284 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
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|
8285 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
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|
8286 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8287 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
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|
8288 "MOV EAX,EDX\n\t" |
| 1920 | 8289 "MOV EDX,0\n\t" |
| 8290 "JLE,s pos\n\t" | |
| 8291 "LNEG EAX : $tmp2\n\t" | |
| 8292 "DIV $tmp # unsigned division\n\t" | |
| 8293 "MOV EAX,$tmp2\n\t" | |
| 8294 "DIV $tmp\n\t" | |
| 8295 "NEG EDX\n\t" | |
| 8296 "JMP,s done\n" | |
| 8297 "pos:\n\t" | |
| 8298 "DIV $tmp\n\t" | |
|
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|
8299 "MOV EAX,$tmp2\n" |
|
ae065c367d93
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|
8300 "fast:\n\t" |
| 1920 | 8301 "DIV $tmp\n" |
| 8302 "done:\n\t" | |
|
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|
8303 "MOV EAX,EDX\n\t" |
|
ae065c367d93
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|
8304 "SAR EDX,31\n\t" %} |
|
ae065c367d93
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|
8305 ins_encode %{ |
|
ae065c367d93
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|
8306 int con = (int)$imm$$constant; |
|
ae065c367d93
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|
8307 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
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|
8308 int pcon = (con > 0) ? con : -con; |
| 1920 | 8309 Label Lfast, Lpos, Ldone; |
|
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|
8310 |
|
ae065c367d93
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|
8311 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8312 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
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|
8313 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
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|
8314 |
|
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|
8315 __ movl($tmp2$$Register, $dst$$Register); // save |
|
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|
8316 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8317 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8318 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8319 | |
| 8320 // Negative dividend. | |
| 8321 // convert value to positive to use unsigned division | |
| 8322 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8323 __ divl($tmp$$Register); | |
| 8324 __ movl($dst$$Register, $tmp2$$Register); | |
| 8325 __ divl($tmp$$Register); | |
| 8326 // revert remainder back to negative | |
| 8327 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 8328 __ jmpb(Ldone); | |
| 8329 | |
| 8330 __ bind(Lpos); | |
| 8331 __ divl($tmp$$Register); | |
|
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|
8332 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
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|
8333 |
|
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|
8334 __ bind(Lfast); |
| 1920 | 8335 // fast path: src is positive |
| 8336 __ divl($tmp$$Register); | |
| 8337 | |
| 8338 __ bind(Ldone); | |
|
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changeset
|
8339 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
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|
8340 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
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|
8341 |
|
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|
8342 %} |
|
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|
8343 ins_pipe( pipe_slow ); |
|
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|
8344 %} |
|
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|
8345 |
| 0 | 8346 // Integer Shift Instructions |
| 8347 // Shift Left by one | |
|
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8348 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8349 match(Set dst (LShiftI dst shift)); |
| 8350 effect(KILL cr); | |
| 8351 | |
| 8352 size(2); | |
| 8353 format %{ "SHL $dst,$shift" %} | |
| 8354 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8355 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8356 ins_pipe( ialu_reg ); | |
| 8357 %} | |
| 8358 | |
| 8359 // Shift Left by 8-bit immediate | |
|
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|
8360 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8361 match(Set dst (LShiftI dst shift)); |
| 8362 effect(KILL cr); | |
| 8363 | |
| 8364 size(3); | |
| 8365 format %{ "SHL $dst,$shift" %} | |
| 8366 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8367 ins_encode( RegOpcImm( dst, shift) ); | |
| 8368 ins_pipe( ialu_reg ); | |
| 8369 %} | |
| 8370 | |
| 8371 // Shift Left by variable | |
|
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|
8372 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8373 match(Set dst (LShiftI dst shift)); |
| 8374 effect(KILL cr); | |
| 8375 | |
| 8376 size(2); | |
| 8377 format %{ "SHL $dst,$shift" %} | |
| 8378 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8379 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8380 ins_pipe( ialu_reg_reg ); | |
| 8381 %} | |
| 8382 | |
| 8383 // Arithmetic shift right by one | |
|
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|
8384 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8385 match(Set dst (RShiftI dst shift)); |
| 8386 effect(KILL cr); | |
| 8387 | |
| 8388 size(2); | |
| 8389 format %{ "SAR $dst,$shift" %} | |
| 8390 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8391 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8392 ins_pipe( ialu_reg ); | |
| 8393 %} | |
| 8394 | |
| 8395 // Arithmetic shift right by one | |
| 8396 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 8397 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8398 effect(KILL cr); | |
| 8399 format %{ "SAR $dst,$shift" %} | |
| 8400 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8401 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 8402 ins_pipe( ialu_mem_imm ); | |
| 8403 %} | |
| 8404 | |
| 8405 // Arithmetic Shift Right by 8-bit immediate | |
|
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8406 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8407 match(Set dst (RShiftI dst shift)); |
| 8408 effect(KILL cr); | |
| 8409 | |
| 8410 size(3); | |
| 8411 format %{ "SAR $dst,$shift" %} | |
| 8412 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8413 ins_encode( RegOpcImm( dst, shift ) ); | |
| 8414 ins_pipe( ialu_mem_imm ); | |
| 8415 %} | |
| 8416 | |
| 8417 // Arithmetic Shift Right by 8-bit immediate | |
| 8418 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 8419 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8420 effect(KILL cr); | |
| 8421 | |
| 8422 format %{ "SAR $dst,$shift" %} | |
| 8423 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8424 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 8425 ins_pipe( ialu_mem_imm ); | |
| 8426 %} | |
| 8427 | |
| 8428 // Arithmetic Shift Right by variable | |
|
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|
8429 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8430 match(Set dst (RShiftI dst shift)); |
| 8431 effect(KILL cr); | |
| 8432 | |
| 8433 size(2); | |
| 8434 format %{ "SAR $dst,$shift" %} | |
| 8435 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8436 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8437 ins_pipe( ialu_reg_reg ); | |
| 8438 %} | |
| 8439 | |
| 8440 // Logical shift right by one | |
|
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|
8441 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8442 match(Set dst (URShiftI dst shift)); |
| 8443 effect(KILL cr); | |
| 8444 | |
| 8445 size(2); | |
| 8446 format %{ "SHR $dst,$shift" %} | |
| 8447 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8448 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8449 ins_pipe( ialu_reg ); | |
| 8450 %} | |
| 8451 | |
| 8452 // Logical Shift Right by 8-bit immediate | |
|
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|
8453 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8454 match(Set dst (URShiftI dst shift)); |
| 8455 effect(KILL cr); | |
| 8456 | |
| 8457 size(3); | |
| 8458 format %{ "SHR $dst,$shift" %} | |
| 8459 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8460 ins_encode( RegOpcImm( dst, shift) ); | |
| 8461 ins_pipe( ialu_reg ); | |
| 8462 %} | |
| 8463 | |
|
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|
8464 |
| 0 | 8465 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 8466 // This idiom is used by the compiler for the i2b bytecode. | |
|
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|
8467 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 8468 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 8469 | |
| 8470 size(3); | |
| 8471 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 8472 ins_encode %{ |
| 8473 __ movsbl($dst$$Register, $src$$Register); | |
| 8474 %} | |
| 8475 ins_pipe(ialu_reg_reg); | |
| 0 | 8476 %} |
| 8477 | |
| 8478 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8479 // This idiom is used by the compiler the i2s bytecode. | |
|
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|
8480 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 8481 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 8482 | |
| 8483 size(3); | |
| 8484 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 8485 ins_encode %{ |
| 8486 __ movswl($dst$$Register, $src$$Register); | |
| 8487 %} | |
| 8488 ins_pipe(ialu_reg_reg); | |
| 0 | 8489 %} |
| 8490 | |
| 8491 | |
| 8492 // Logical Shift Right by variable | |
|
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8493 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8494 match(Set dst (URShiftI dst shift)); |
| 8495 effect(KILL cr); | |
| 8496 | |
| 8497 size(2); | |
| 8498 format %{ "SHR $dst,$shift" %} | |
| 8499 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8500 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8501 ins_pipe( ialu_reg_reg ); | |
| 8502 %} | |
| 8503 | |
| 8504 | |
| 8505 //----------Logical Instructions----------------------------------------------- | |
| 8506 //----------Integer Logical Instructions--------------------------------------- | |
| 8507 // And Instructions | |
| 8508 // And Register with Register | |
|
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|
8509 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8510 match(Set dst (AndI dst src)); |
| 8511 effect(KILL cr); | |
| 8512 | |
| 8513 size(2); | |
| 8514 format %{ "AND $dst,$src" %} | |
| 8515 opcode(0x23); | |
| 8516 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8517 ins_pipe( ialu_reg_reg ); | |
| 8518 %} | |
| 8519 | |
| 8520 // And Register with Immediate | |
|
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|
8521 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8522 match(Set dst (AndI dst src)); |
| 8523 effect(KILL cr); | |
| 8524 | |
| 8525 format %{ "AND $dst,$src" %} | |
| 8526 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8527 // ins_encode( RegImm( dst, src) ); | |
| 8528 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8529 ins_pipe( ialu_reg ); | |
| 8530 %} | |
| 8531 | |
| 8532 // And Register with Memory | |
|
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|
8533 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8534 match(Set dst (AndI dst (LoadI src))); |
| 8535 effect(KILL cr); | |
| 8536 | |
| 8537 ins_cost(125); | |
| 8538 format %{ "AND $dst,$src" %} | |
| 8539 opcode(0x23); | |
| 8540 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8541 ins_pipe( ialu_reg_mem ); | |
| 8542 %} | |
| 8543 | |
| 8544 // And Memory with Register | |
|
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|
8545 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8546 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8547 effect(KILL cr); | |
| 8548 | |
| 8549 ins_cost(150); | |
| 8550 format %{ "AND $dst,$src" %} | |
| 8551 opcode(0x21); /* Opcode 21 /r */ | |
| 8552 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8553 ins_pipe( ialu_mem_reg ); | |
| 8554 %} | |
| 8555 | |
| 8556 // And Memory with Immediate | |
| 8557 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8558 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8559 effect(KILL cr); | |
| 8560 | |
| 8561 ins_cost(125); | |
| 8562 format %{ "AND $dst,$src" %} | |
| 8563 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8564 // ins_encode( MemImm( dst, src) ); | |
| 8565 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8566 ins_pipe( ialu_mem_imm ); | |
| 8567 %} | |
| 8568 | |
| 8569 // Or Instructions | |
| 8570 // Or Register with Register | |
|
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|
8571 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8572 match(Set dst (OrI dst src)); |
| 8573 effect(KILL cr); | |
| 8574 | |
| 8575 size(2); | |
| 8576 format %{ "OR $dst,$src" %} | |
| 8577 opcode(0x0B); | |
| 8578 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8579 ins_pipe( ialu_reg_reg ); | |
| 8580 %} | |
| 8581 | |
|
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|
8582 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
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|
8583 match(Set dst (OrI dst (CastP2X src))); |
|
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|
8584 effect(KILL cr); |
|
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|
8585 |
|
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|
8586 size(2); |
|
a1980da045cc
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|
8587 format %{ "OR $dst,$src" %} |
|
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|
8588 opcode(0x0B); |
|
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|
8589 ins_encode( OpcP, RegReg( dst, src) ); |
|
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|
8590 ins_pipe( ialu_reg_reg ); |
|
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|
8591 %} |
|
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|
8592 |
|
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|
8593 |
| 0 | 8594 // Or Register with Immediate |
|
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|
8595 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8596 match(Set dst (OrI dst src)); |
| 8597 effect(KILL cr); | |
| 8598 | |
| 8599 format %{ "OR $dst,$src" %} | |
| 8600 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8601 // ins_encode( RegImm( dst, src) ); | |
| 8602 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8603 ins_pipe( ialu_reg ); | |
| 8604 %} | |
| 8605 | |
| 8606 // Or Register with Memory | |
|
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|
8607 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8608 match(Set dst (OrI dst (LoadI src))); |
| 8609 effect(KILL cr); | |
| 8610 | |
| 8611 ins_cost(125); | |
| 8612 format %{ "OR $dst,$src" %} | |
| 8613 opcode(0x0B); | |
| 8614 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8615 ins_pipe( ialu_reg_mem ); | |
| 8616 %} | |
| 8617 | |
| 8618 // Or Memory with Register | |
|
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8619 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8620 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8621 effect(KILL cr); | |
| 8622 | |
| 8623 ins_cost(150); | |
| 8624 format %{ "OR $dst,$src" %} | |
| 8625 opcode(0x09); /* Opcode 09 /r */ | |
| 8626 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8627 ins_pipe( ialu_mem_reg ); | |
| 8628 %} | |
| 8629 | |
| 8630 // Or Memory with Immediate | |
| 8631 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8632 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8633 effect(KILL cr); | |
| 8634 | |
| 8635 ins_cost(125); | |
| 8636 format %{ "OR $dst,$src" %} | |
| 8637 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8638 // ins_encode( MemImm( dst, src) ); | |
| 8639 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8640 ins_pipe( ialu_mem_imm ); | |
| 8641 %} | |
| 8642 | |
| 8643 // ROL/ROR | |
| 8644 // ROL expand | |
|
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8645 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8646 effect(USE_DEF dst, USE shift, KILL cr); |
| 8647 | |
| 8648 format %{ "ROL $dst, $shift" %} | |
| 8649 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8650 ins_encode( OpcP, RegOpc( dst )); | |
| 8651 ins_pipe( ialu_reg ); | |
| 8652 %} | |
| 8653 | |
|
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8654 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8655 effect(USE_DEF dst, USE shift, KILL cr); |
| 8656 | |
| 8657 format %{ "ROL $dst, $shift" %} | |
| 8658 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8659 ins_encode( RegOpcImm(dst, shift) ); | |
| 8660 ins_pipe(ialu_reg); | |
| 8661 %} | |
| 8662 | |
| 8663 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8664 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8665 | |
| 8666 format %{ "ROL $dst, $shift" %} | |
| 8667 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8668 ins_encode(OpcP, RegOpc(dst)); | |
| 8669 ins_pipe( ialu_reg_reg ); | |
| 8670 %} | |
| 8671 // end of ROL expand | |
| 8672 | |
| 8673 // ROL 32bit by one once | |
|
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8674 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8675 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8676 | |
| 8677 expand %{ | |
| 8678 rolI_eReg_imm1(dst, lshift, cr); | |
| 8679 %} | |
| 8680 %} | |
| 8681 | |
| 8682 // ROL 32bit var by imm8 once | |
|
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8683 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8684 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8685 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8686 | |
| 8687 expand %{ | |
| 8688 rolI_eReg_imm8(dst, lshift, cr); | |
| 8689 %} | |
| 8690 %} | |
| 8691 | |
| 8692 // ROL 32bit var by var once | |
| 8693 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8694 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8695 | |
| 8696 expand %{ | |
| 8697 rolI_eReg_CL(dst, shift, cr); | |
| 8698 %} | |
| 8699 %} | |
| 8700 | |
| 8701 // ROL 32bit var by var once | |
| 8702 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8703 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8704 | |
| 8705 expand %{ | |
| 8706 rolI_eReg_CL(dst, shift, cr); | |
| 8707 %} | |
| 8708 %} | |
| 8709 | |
| 8710 // ROR expand | |
|
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8711 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8712 effect(USE_DEF dst, USE shift, KILL cr); |
| 8713 | |
| 8714 format %{ "ROR $dst, $shift" %} | |
| 8715 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8716 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8717 ins_pipe( ialu_reg ); | |
| 8718 %} | |
| 8719 | |
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8720 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8721 effect (USE_DEF dst, USE shift, KILL cr); |
| 8722 | |
| 8723 format %{ "ROR $dst, $shift" %} | |
| 8724 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8725 ins_encode( RegOpcImm(dst, shift) ); | |
| 8726 ins_pipe( ialu_reg ); | |
| 8727 %} | |
| 8728 | |
| 8729 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8730 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8731 | |
| 8732 format %{ "ROR $dst, $shift" %} | |
| 8733 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8734 ins_encode(OpcP, RegOpc(dst)); | |
| 8735 ins_pipe( ialu_reg_reg ); | |
| 8736 %} | |
| 8737 // end of ROR expand | |
| 8738 | |
| 8739 // ROR right once | |
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8740 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8741 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8742 | |
| 8743 expand %{ | |
| 8744 rorI_eReg_imm1(dst, rshift, cr); | |
| 8745 %} | |
| 8746 %} | |
| 8747 | |
| 8748 // ROR 32bit by immI8 once | |
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8749 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8750 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8751 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8752 | |
| 8753 expand %{ | |
| 8754 rorI_eReg_imm8(dst, rshift, cr); | |
| 8755 %} | |
| 8756 %} | |
| 8757 | |
| 8758 // ROR 32bit var by var once | |
| 8759 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8760 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8761 | |
| 8762 expand %{ | |
| 8763 rorI_eReg_CL(dst, shift, cr); | |
| 8764 %} | |
| 8765 %} | |
| 8766 | |
| 8767 // ROR 32bit var by var once | |
| 8768 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8769 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8770 | |
| 8771 expand %{ | |
| 8772 rorI_eReg_CL(dst, shift, cr); | |
| 8773 %} | |
| 8774 %} | |
| 8775 | |
| 8776 // Xor Instructions | |
| 8777 // Xor Register with Register | |
|
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8778 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8779 match(Set dst (XorI dst src)); |
| 8780 effect(KILL cr); | |
| 8781 | |
| 8782 size(2); | |
| 8783 format %{ "XOR $dst,$src" %} | |
| 8784 opcode(0x33); | |
| 8785 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8786 ins_pipe( ialu_reg_reg ); | |
| 8787 %} | |
| 8788 | |
| 403 | 8789 // Xor Register with Immediate -1 |
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8790 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8791 match(Set dst (XorI dst imm)); |
| 8792 | |
| 8793 size(2); | |
| 8794 format %{ "NOT $dst" %} | |
| 8795 ins_encode %{ | |
| 8796 __ notl($dst$$Register); | |
| 8797 %} | |
| 8798 ins_pipe( ialu_reg ); | |
| 8799 %} | |
| 8800 | |
| 0 | 8801 // Xor Register with Immediate |
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8802 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8803 match(Set dst (XorI dst src)); |
| 8804 effect(KILL cr); | |
| 8805 | |
| 8806 format %{ "XOR $dst,$src" %} | |
| 8807 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8808 // ins_encode( RegImm( dst, src) ); | |
| 8809 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8810 ins_pipe( ialu_reg ); | |
| 8811 %} | |
| 8812 | |
| 8813 // Xor Register with Memory | |
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8814 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8815 match(Set dst (XorI dst (LoadI src))); |
| 8816 effect(KILL cr); | |
| 8817 | |
| 8818 ins_cost(125); | |
| 8819 format %{ "XOR $dst,$src" %} | |
| 8820 opcode(0x33); | |
| 8821 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8822 ins_pipe( ialu_reg_mem ); | |
| 8823 %} | |
| 8824 | |
| 8825 // Xor Memory with Register | |
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8826 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8827 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8828 effect(KILL cr); | |
| 8829 | |
| 8830 ins_cost(150); | |
| 8831 format %{ "XOR $dst,$src" %} | |
| 8832 opcode(0x31); /* Opcode 31 /r */ | |
| 8833 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8834 ins_pipe( ialu_mem_reg ); | |
| 8835 %} | |
| 8836 | |
| 8837 // Xor Memory with Immediate | |
| 8838 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8839 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8840 effect(KILL cr); | |
| 8841 | |
| 8842 ins_cost(125); | |
| 8843 format %{ "XOR $dst,$src" %} | |
| 8844 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8845 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8846 ins_pipe( ialu_mem_imm ); | |
| 8847 %} | |
| 8848 | |
| 8849 //----------Convert Int to Boolean--------------------------------------------- | |
| 8850 | |
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8851 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8852 effect( DEF dst, USE src ); |
| 8853 format %{ "MOV $dst,$src" %} | |
| 8854 ins_encode( enc_Copy( dst, src) ); | |
| 8855 ins_pipe( ialu_reg_reg ); | |
| 8856 %} | |
| 8857 | |
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8858 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8859 effect( USE_DEF dst, USE src, KILL cr ); |
| 8860 | |
| 8861 size(4); | |
| 8862 format %{ "NEG $dst\n\t" | |
| 8863 "ADC $dst,$src" %} | |
| 8864 ins_encode( neg_reg(dst), | |
| 8865 OpcRegReg(0x13,dst,src) ); | |
| 8866 ins_pipe( ialu_reg_reg_long ); | |
| 8867 %} | |
| 8868 | |
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8869 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8870 match(Set dst (Conv2B src)); |
| 8871 | |
| 8872 expand %{ | |
| 8873 movI_nocopy(dst,src); | |
| 8874 ci2b(dst,src,cr); | |
| 8875 %} | |
| 8876 %} | |
| 8877 | |
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8878 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8879 effect( DEF dst, USE src ); |
| 8880 format %{ "MOV $dst,$src" %} | |
| 8881 ins_encode( enc_Copy( dst, src) ); | |
| 8882 ins_pipe( ialu_reg_reg ); | |
| 8883 %} | |
| 8884 | |
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8885 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8886 effect( USE_DEF dst, USE src, KILL cr ); |
| 8887 format %{ "NEG $dst\n\t" | |
| 8888 "ADC $dst,$src" %} | |
| 8889 ins_encode( neg_reg(dst), | |
| 8890 OpcRegReg(0x13,dst,src) ); | |
| 8891 ins_pipe( ialu_reg_reg_long ); | |
| 8892 %} | |
| 8893 | |
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8894 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8895 match(Set dst (Conv2B src)); |
| 8896 | |
| 8897 expand %{ | |
| 8898 movP_nocopy(dst,src); | |
| 8899 cp2b(dst,src,cr); | |
| 8900 %} | |
| 8901 %} | |
| 8902 | |
| 8903 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 8904 match(Set dst (CmpLTMask p q)); | |
| 8905 effect( KILL cr ); | |
| 8906 ins_cost(400); | |
| 8907 | |
| 8908 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8909 format %{ "XOR $dst,$dst\n\t" | |
| 8910 "CMP $p,$q\n\t" | |
| 8911 "SETlt $dst\n\t" | |
| 8912 "NEG $dst" %} | |
| 8913 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 8914 OpcRegReg(0x3B,p,q), | |
| 8915 setLT_reg(dst), neg_reg(dst) ); | |
| 8916 ins_pipe( pipe_slow ); | |
| 8917 %} | |
| 8918 | |
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8919 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{ |
| 0 | 8920 match(Set dst (CmpLTMask dst zero)); |
| 8921 effect( DEF dst, KILL cr ); | |
| 8922 ins_cost(100); | |
| 8923 | |
| 8924 format %{ "SAR $dst,31" %} | |
| 8925 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8926 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 8927 ins_pipe( ialu_reg ); | |
| 8928 %} | |
| 8929 | |
| 8930 | |
| 8931 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 8932 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8933 effect( KILL tmp, KILL cr ); | |
| 8934 ins_cost(400); | |
| 8935 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 8936 // any format or encoding | |
| 8937 format %{ "SUB $p,$q\n\t" | |
| 8938 "SBB ECX,ECX\n\t" | |
| 8939 "AND ECX,$y\n\t" | |
| 8940 "ADD $p,ECX" %} | |
| 8941 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 8942 ins_pipe( pipe_cmplt ); | |
| 8943 %} | |
| 8944 | |
| 8945 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 8946 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 8947 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 8948 effect( USE_KILL tmp, KILL cr ); | |
| 8949 ins_cost(400); | |
| 8950 | |
| 8951 format %{ "SUB $p,$q\n\t" | |
| 8952 "SBB ECX,ECX\n\t" | |
| 8953 "AND ECX,$y\n\t" | |
| 8954 "ADD $p,ECX" %} | |
| 8955 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 8956 %} | |
| 8957 */ | |
| 8958 | |
| 8959 //----------Long Instructions------------------------------------------------ | |
| 8960 // Add Long Register with Register | |
| 8961 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8962 match(Set dst (AddL dst src)); | |
| 8963 effect(KILL cr); | |
| 8964 ins_cost(200); | |
| 8965 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8966 "ADC $dst.hi,$src.hi" %} | |
| 8967 opcode(0x03, 0x13); | |
| 8968 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8969 ins_pipe( ialu_reg_reg_long ); | |
| 8970 %} | |
| 8971 | |
| 8972 // Add Long Register with Immediate | |
| 8973 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8974 match(Set dst (AddL dst src)); | |
| 8975 effect(KILL cr); | |
| 8976 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8977 "ADC $dst.hi,$src.hi" %} | |
| 8978 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8979 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8980 ins_pipe( ialu_reg_long ); | |
| 8981 %} | |
| 8982 | |
| 8983 // Add Long Register with Memory | |
| 8984 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8985 match(Set dst (AddL dst (LoadL mem))); | |
| 8986 effect(KILL cr); | |
| 8987 ins_cost(125); | |
| 8988 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8989 "ADC $dst.hi,$mem+4" %} | |
| 8990 opcode(0x03, 0x13); | |
| 8991 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8992 ins_pipe( ialu_reg_long_mem ); | |
| 8993 %} | |
| 8994 | |
| 8995 // Subtract Long Register with Register. | |
| 8996 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8997 match(Set dst (SubL dst src)); | |
| 8998 effect(KILL cr); | |
| 8999 ins_cost(200); | |
| 9000 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9001 "SBB $dst.hi,$src.hi" %} | |
| 9002 opcode(0x2B, 0x1B); | |
| 9003 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9004 ins_pipe( ialu_reg_reg_long ); | |
| 9005 %} | |
| 9006 | |
| 9007 // Subtract Long Register with Immediate | |
| 9008 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9009 match(Set dst (SubL dst src)); | |
| 9010 effect(KILL cr); | |
| 9011 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9012 "SBB $dst.hi,$src.hi" %} | |
| 9013 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9014 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9015 ins_pipe( ialu_reg_long ); | |
| 9016 %} | |
| 9017 | |
| 9018 // Subtract Long Register with Memory | |
| 9019 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9020 match(Set dst (SubL dst (LoadL mem))); | |
| 9021 effect(KILL cr); | |
| 9022 ins_cost(125); | |
| 9023 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9024 "SBB $dst.hi,$mem+4" %} | |
| 9025 opcode(0x2B, 0x1B); | |
| 9026 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9027 ins_pipe( ialu_reg_long_mem ); | |
| 9028 %} | |
| 9029 | |
| 9030 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9031 match(Set dst (SubL zero dst)); | |
| 9032 effect(KILL cr); | |
| 9033 ins_cost(300); | |
| 9034 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9035 ins_encode( neg_long(dst) ); | |
| 9036 ins_pipe( ialu_reg_reg_long ); | |
| 9037 %} | |
| 9038 | |
| 9039 // And Long Register with Register | |
| 9040 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9041 match(Set dst (AndL dst src)); | |
| 9042 effect(KILL cr); | |
| 9043 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9044 "AND $dst.hi,$src.hi" %} | |
| 9045 opcode(0x23,0x23); | |
| 9046 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9047 ins_pipe( ialu_reg_reg_long ); | |
| 9048 %} | |
| 9049 | |
| 9050 // And Long Register with Immediate | |
| 9051 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9052 match(Set dst (AndL dst src)); | |
| 9053 effect(KILL cr); | |
| 9054 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9055 "AND $dst.hi,$src.hi" %} | |
| 9056 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9057 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9058 ins_pipe( ialu_reg_long ); | |
| 9059 %} | |
| 9060 | |
| 9061 // And Long Register with Memory | |
| 9062 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9063 match(Set dst (AndL dst (LoadL mem))); | |
| 9064 effect(KILL cr); | |
| 9065 ins_cost(125); | |
| 9066 format %{ "AND $dst.lo,$mem\n\t" | |
| 9067 "AND $dst.hi,$mem+4" %} | |
| 9068 opcode(0x23, 0x23); | |
| 9069 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9070 ins_pipe( ialu_reg_long_mem ); | |
| 9071 %} | |
| 9072 | |
| 9073 // Or Long Register with Register | |
| 9074 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9075 match(Set dst (OrL dst src)); | |
| 9076 effect(KILL cr); | |
| 9077 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9078 "OR $dst.hi,$src.hi" %} | |
| 9079 opcode(0x0B,0x0B); | |
| 9080 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9081 ins_pipe( ialu_reg_reg_long ); | |
| 9082 %} | |
| 9083 | |
| 9084 // Or Long Register with Immediate | |
| 9085 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9086 match(Set dst (OrL dst src)); | |
| 9087 effect(KILL cr); | |
| 9088 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9089 "OR $dst.hi,$src.hi" %} | |
| 9090 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9091 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9092 ins_pipe( ialu_reg_long ); | |
| 9093 %} | |
| 9094 | |
| 9095 // Or Long Register with Memory | |
| 9096 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9097 match(Set dst (OrL dst (LoadL mem))); | |
| 9098 effect(KILL cr); | |
| 9099 ins_cost(125); | |
| 9100 format %{ "OR $dst.lo,$mem\n\t" | |
| 9101 "OR $dst.hi,$mem+4" %} | |
| 9102 opcode(0x0B,0x0B); | |
| 9103 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9104 ins_pipe( ialu_reg_long_mem ); | |
| 9105 %} | |
| 9106 | |
| 9107 // Xor Long Register with Register | |
| 9108 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9109 match(Set dst (XorL dst src)); | |
| 9110 effect(KILL cr); | |
| 9111 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9112 "XOR $dst.hi,$src.hi" %} | |
| 9113 opcode(0x33,0x33); | |
| 9114 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9115 ins_pipe( ialu_reg_reg_long ); | |
| 9116 %} | |
| 9117 | |
| 403 | 9118 // Xor Long Register with Immediate -1 |
| 9119 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9120 match(Set dst (XorL dst imm)); | |
| 9121 format %{ "NOT $dst.lo\n\t" | |
| 9122 "NOT $dst.hi" %} | |
| 9123 ins_encode %{ | |
| 9124 __ notl($dst$$Register); | |
| 9125 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9126 %} | |
| 9127 ins_pipe( ialu_reg_long ); | |
| 9128 %} | |
| 9129 | |
| 0 | 9130 // Xor Long Register with Immediate |
| 9131 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9132 match(Set dst (XorL dst src)); | |
| 9133 effect(KILL cr); | |
| 9134 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9135 "XOR $dst.hi,$src.hi" %} | |
| 9136 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9137 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9138 ins_pipe( ialu_reg_long ); | |
| 9139 %} | |
| 9140 | |
| 9141 // Xor Long Register with Memory | |
| 9142 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9143 match(Set dst (XorL dst (LoadL mem))); | |
| 9144 effect(KILL cr); | |
| 9145 ins_cost(125); | |
| 9146 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9147 "XOR $dst.hi,$mem+4" %} | |
| 9148 opcode(0x33,0x33); | |
| 9149 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9150 ins_pipe( ialu_reg_long_mem ); | |
| 9151 %} | |
| 9152 | |
| 219 | 9153 // Shift Left Long by 1 |
| 9154 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9155 predicate(UseNewLongLShift); | |
| 9156 match(Set dst (LShiftL dst cnt)); | |
| 9157 effect(KILL cr); | |
| 9158 ins_cost(100); | |
| 9159 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9160 "ADC $dst.hi,$dst.hi" %} | |
| 9161 ins_encode %{ | |
| 9162 __ addl($dst$$Register,$dst$$Register); | |
| 9163 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9164 %} | |
| 9165 ins_pipe( ialu_reg_long ); | |
| 9166 %} | |
| 9167 | |
| 9168 // Shift Left Long by 2 | |
| 9169 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9170 predicate(UseNewLongLShift); | |
| 9171 match(Set dst (LShiftL dst cnt)); | |
| 9172 effect(KILL cr); | |
| 9173 ins_cost(100); | |
| 9174 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9175 "ADC $dst.hi,$dst.hi\n\t" | |
| 9176 "ADD $dst.lo,$dst.lo\n\t" | |
| 9177 "ADC $dst.hi,$dst.hi" %} | |
| 9178 ins_encode %{ | |
| 9179 __ addl($dst$$Register,$dst$$Register); | |
| 9180 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9181 __ addl($dst$$Register,$dst$$Register); | |
| 9182 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9183 %} | |
| 9184 ins_pipe( ialu_reg_long ); | |
| 9185 %} | |
| 9186 | |
| 9187 // Shift Left Long by 3 | |
| 9188 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9189 predicate(UseNewLongLShift); | |
| 9190 match(Set dst (LShiftL dst cnt)); | |
| 9191 effect(KILL cr); | |
| 9192 ins_cost(100); | |
| 9193 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9194 "ADC $dst.hi,$dst.hi\n\t" | |
| 9195 "ADD $dst.lo,$dst.lo\n\t" | |
| 9196 "ADC $dst.hi,$dst.hi\n\t" | |
| 9197 "ADD $dst.lo,$dst.lo\n\t" | |
| 9198 "ADC $dst.hi,$dst.hi" %} | |
| 9199 ins_encode %{ | |
| 9200 __ addl($dst$$Register,$dst$$Register); | |
| 9201 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9202 __ addl($dst$$Register,$dst$$Register); | |
| 9203 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9204 __ addl($dst$$Register,$dst$$Register); | |
| 9205 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9206 %} | |
| 9207 ins_pipe( ialu_reg_long ); | |
| 9208 %} | |
| 9209 | |
| 0 | 9210 // Shift Left Long by 1-31 |
| 9211 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9212 match(Set dst (LShiftL dst cnt)); | |
| 9213 effect(KILL cr); | |
| 9214 ins_cost(200); | |
| 9215 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9216 "SHL $dst.lo,$cnt" %} | |
| 9217 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9218 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9219 ins_pipe( ialu_reg_long ); | |
| 9220 %} | |
| 9221 | |
| 9222 // Shift Left Long by 32-63 | |
| 9223 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9224 match(Set dst (LShiftL dst cnt)); | |
| 9225 effect(KILL cr); | |
| 9226 ins_cost(300); | |
| 9227 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9228 "\tSHL $dst.hi,$cnt-32\n" | |
| 9229 "\tXOR $dst.lo,$dst.lo" %} | |
| 9230 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9231 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9232 ins_pipe( ialu_reg_long ); | |
| 9233 %} | |
| 9234 | |
| 9235 // Shift Left Long by variable | |
| 9236 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9237 match(Set dst (LShiftL dst shift)); | |
| 9238 effect(KILL cr); | |
| 9239 ins_cost(500+200); | |
| 9240 size(17); | |
| 9241 format %{ "TEST $shift,32\n\t" | |
| 9242 "JEQ,s small\n\t" | |
| 9243 "MOV $dst.hi,$dst.lo\n\t" | |
| 9244 "XOR $dst.lo,$dst.lo\n" | |
| 9245 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9246 "SHL $dst.lo,$shift" %} | |
| 9247 ins_encode( shift_left_long( dst, shift ) ); | |
| 9248 ins_pipe( pipe_slow ); | |
| 9249 %} | |
| 9250 | |
| 9251 // Shift Right Long by 1-31 | |
| 9252 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9253 match(Set dst (URShiftL dst cnt)); | |
| 9254 effect(KILL cr); | |
| 9255 ins_cost(200); | |
| 9256 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9257 "SHR $dst.hi,$cnt" %} | |
| 9258 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9259 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9260 ins_pipe( ialu_reg_long ); | |
| 9261 %} | |
| 9262 | |
| 9263 // Shift Right Long by 32-63 | |
| 9264 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9265 match(Set dst (URShiftL dst cnt)); | |
| 9266 effect(KILL cr); | |
| 9267 ins_cost(300); | |
| 9268 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9269 "\tSHR $dst.lo,$cnt-32\n" | |
| 9270 "\tXOR $dst.hi,$dst.hi" %} | |
| 9271 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9272 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9273 ins_pipe( ialu_reg_long ); | |
| 9274 %} | |
| 9275 | |
| 9276 // Shift Right Long by variable | |
| 9277 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9278 match(Set dst (URShiftL dst shift)); | |
| 9279 effect(KILL cr); | |
| 9280 ins_cost(600); | |
| 9281 size(17); | |
| 9282 format %{ "TEST $shift,32\n\t" | |
| 9283 "JEQ,s small\n\t" | |
| 9284 "MOV $dst.lo,$dst.hi\n\t" | |
| 9285 "XOR $dst.hi,$dst.hi\n" | |
| 9286 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9287 "SHR $dst.hi,$shift" %} | |
| 9288 ins_encode( shift_right_long( dst, shift ) ); | |
| 9289 ins_pipe( pipe_slow ); | |
| 9290 %} | |
| 9291 | |
| 9292 // Shift Right Long by 1-31 | |
| 9293 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9294 match(Set dst (RShiftL dst cnt)); | |
| 9295 effect(KILL cr); | |
| 9296 ins_cost(200); | |
| 9297 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9298 "SAR $dst.hi,$cnt" %} | |
| 9299 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9300 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9301 ins_pipe( ialu_reg_long ); | |
| 9302 %} | |
| 9303 | |
| 9304 // Shift Right Long by 32-63 | |
| 9305 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9306 match(Set dst (RShiftL dst cnt)); | |
| 9307 effect(KILL cr); | |
| 9308 ins_cost(300); | |
| 9309 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9310 "\tSAR $dst.lo,$cnt-32\n" | |
| 9311 "\tSAR $dst.hi,31" %} | |
| 9312 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9313 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9314 ins_pipe( ialu_reg_long ); | |
| 9315 %} | |
| 9316 | |
| 9317 // Shift Right arithmetic Long by variable | |
| 9318 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9319 match(Set dst (RShiftL dst shift)); | |
| 9320 effect(KILL cr); | |
| 9321 ins_cost(600); | |
| 9322 size(18); | |
| 9323 format %{ "TEST $shift,32\n\t" | |
| 9324 "JEQ,s small\n\t" | |
| 9325 "MOV $dst.lo,$dst.hi\n\t" | |
| 9326 "SAR $dst.hi,31\n" | |
| 9327 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9328 "SAR $dst.hi,$shift" %} | |
| 9329 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9330 ins_pipe( pipe_slow ); | |
| 9331 %} | |
| 9332 | |
| 9333 | |
| 9334 //----------Double Instructions------------------------------------------------ | |
| 9335 // Double Math | |
| 9336 | |
| 9337 // Compare & branch | |
| 9338 | |
| 9339 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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9340 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9341 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9342 match(Set cr (CmpD src1 src2)); | |
| 9343 effect(KILL rax); | |
| 9344 ins_cost(150); | |
| 9345 format %{ "FLD $src1\n\t" | |
| 9346 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9347 "JNP exit\n\t" | |
| 9348 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9349 "SAHF\n" | |
| 9350 "exit:\tNOP // avoid branch to branch" %} | |
| 9351 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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9352 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9353 OpcP, RegOpc(src2), |
| 9354 cmpF_P6_fixup ); | |
| 9355 ins_pipe( pipe_slow ); | |
| 9356 %} | |
| 9357 | |
|
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9358 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
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9359 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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9360 match(Set cr (CmpD src1 src2)); |
|
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9361 ins_cost(150); |
|
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9362 format %{ "FLD $src1\n\t" |
|
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9363 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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9364 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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9365 ins_encode( Push_Reg_DPR(src1), |
|
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9366 OpcP, RegOpc(src2)); |
|
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9367 ins_pipe( pipe_slow ); |
|
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|
9368 %} |
|
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9369 |
| 0 | 9370 // Compare & branch |
|
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9371 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9372 predicate(UseSSE<=1); |
| 9373 match(Set cr (CmpD src1 src2)); | |
| 9374 effect(KILL rax); | |
| 9375 ins_cost(200); | |
| 9376 format %{ "FLD $src1\n\t" | |
| 9377 "FCOMp $src2\n\t" | |
| 9378 "FNSTSW AX\n\t" | |
| 9379 "TEST AX,0x400\n\t" | |
| 9380 "JZ,s flags\n\t" | |
| 9381 "MOV AH,1\t# unordered treat as LT\n" | |
| 9382 "flags:\tSAHF" %} | |
| 9383 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9384 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9385 OpcP, RegOpc(src2), |
| 9386 fpu_flags); | |
| 9387 ins_pipe( pipe_slow ); | |
| 9388 %} | |
| 9389 | |
| 9390 // Compare vs zero into -1,0,1 | |
|
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9391 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9392 predicate(UseSSE<=1); |
| 9393 match(Set dst (CmpD3 src1 zero)); | |
| 9394 effect(KILL cr, KILL rax); | |
| 9395 ins_cost(280); | |
| 9396 format %{ "FTSTD $dst,$src1" %} | |
| 9397 opcode(0xE4, 0xD9); | |
|
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9398 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9399 OpcS, OpcP, PopFPU, |
| 9400 CmpF_Result(dst)); | |
| 9401 ins_pipe( pipe_slow ); | |
| 9402 %} | |
| 9403 | |
| 9404 // Compare into -1,0,1 | |
|
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9405 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9406 predicate(UseSSE<=1); |
| 9407 match(Set dst (CmpD3 src1 src2)); | |
| 9408 effect(KILL cr, KILL rax); | |
| 9409 ins_cost(300); | |
| 9410 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9411 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9412 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9413 OpcP, RegOpc(src2), |
| 9414 CmpF_Result(dst)); | |
| 9415 ins_pipe( pipe_slow ); | |
| 9416 %} | |
| 9417 | |
| 9418 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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9419 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9420 predicate(UseSSE>=2); |
| 4759 | 9421 match(Set cr (CmpD src1 src2)); |
| 9422 ins_cost(145); | |
| 9423 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9424 "JNP,s exit\n\t" | |
| 9425 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9426 "AND [rsp], #0xffffff2b\n\t" | |
| 9427 "POPF\n" | |
| 9428 "exit:" %} | |
| 9429 ins_encode %{ | |
| 9430 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9431 emit_cmpfp_fixup(_masm); | |
| 9432 %} | |
| 9433 ins_pipe( pipe_slow ); | |
| 9434 %} | |
| 9435 | |
|
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9436 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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9437 predicate(UseSSE>=2); |
| 4759 | 9438 match(Set cr (CmpD src1 src2)); |
|
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|
9439 ins_cost(100); |
| 4759 | 9440 format %{ "UCOMISD $src1,$src2" %} |
| 9441 ins_encode %{ | |
| 9442 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9443 %} | |
|
415
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|
9444 ins_pipe( pipe_slow ); |
|
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diff
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|
9445 %} |
|
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|
9446 |
| 0 | 9447 // float compare and set condition codes in EFLAGS by XMM regs |
|
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9448 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9449 predicate(UseSSE>=2); |
| 4759 | 9450 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9451 ins_cost(145); |
| 4759 | 9452 format %{ "UCOMISD $src1,$src2\n\t" |
| 9453 "JNP,s exit\n\t" | |
| 9454 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9455 "AND [rsp], #0xffffff2b\n\t" | |
| 9456 "POPF\n" | |
| 9457 "exit:" %} | |
| 9458 ins_encode %{ | |
| 9459 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9460 emit_cmpfp_fixup(_masm); | |
| 9461 %} | |
| 9462 ins_pipe( pipe_slow ); | |
| 9463 %} | |
| 9464 | |
|
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9465 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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|
9466 predicate(UseSSE>=2); |
| 4759 | 9467 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
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|
9468 ins_cost(100); |
| 4759 | 9469 format %{ "UCOMISD $src1,$src2" %} |
| 9470 ins_encode %{ | |
| 9471 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9472 %} | |
|
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|
9473 ins_pipe( pipe_slow ); |
|
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|
9474 %} |
|
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|
9475 |
| 0 | 9476 // Compare into -1,0,1 in XMM |
|
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9477 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9478 predicate(UseSSE>=2); |
| 9479 match(Set dst (CmpD3 src1 src2)); | |
| 9480 effect(KILL cr); | |
| 9481 ins_cost(255); | |
| 4759 | 9482 format %{ "UCOMISD $src1, $src2\n\t" |
| 9483 "MOV $dst, #-1\n\t" | |
| 9484 "JP,s done\n\t" | |
| 9485 "JB,s done\n\t" | |
| 9486 "SETNE $dst\n\t" | |
| 9487 "MOVZB $dst, $dst\n" | |
| 9488 "done:" %} | |
| 9489 ins_encode %{ | |
| 9490 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9491 emit_cmpfp3(_masm, $dst$$Register); | |
| 9492 %} | |
| 0 | 9493 ins_pipe( pipe_slow ); |
| 9494 %} | |
| 9495 | |
| 9496 // Compare into -1,0,1 in XMM and memory | |
|
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9497 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9498 predicate(UseSSE>=2); |
| 4759 | 9499 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9500 effect(KILL cr); |
| 9501 ins_cost(275); | |
| 4759 | 9502 format %{ "UCOMISD $src1, $src2\n\t" |
| 9503 "MOV $dst, #-1\n\t" | |
| 9504 "JP,s done\n\t" | |
| 9505 "JB,s done\n\t" | |
| 9506 "SETNE $dst\n\t" | |
| 9507 "MOVZB $dst, $dst\n" | |
| 9508 "done:" %} | |
| 9509 ins_encode %{ | |
| 9510 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9511 emit_cmpfp3(_masm, $dst$$Register); | |
| 9512 %} | |
| 0 | 9513 ins_pipe( pipe_slow ); |
| 9514 %} | |
| 9515 | |
| 9516 | |
|
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9517 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9518 predicate (UseSSE <=1); |
| 9519 match(Set dst (SubD dst src)); | |
| 9520 | |
| 9521 format %{ "FLD $src\n\t" | |
| 9522 "DSUBp $dst,ST" %} | |
| 9523 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9524 ins_cost(150); | |
|
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9525 ins_encode( Push_Reg_DPR(src), |
| 0 | 9526 OpcP, RegOpc(dst) ); |
| 9527 ins_pipe( fpu_reg_reg ); | |
| 9528 %} | |
| 9529 | |
|
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9530 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9531 predicate (UseSSE <=1); |
| 9532 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9533 ins_cost(250); | |
| 9534 | |
| 9535 format %{ "FLD $src2\n\t" | |
| 9536 "DSUB ST,$src1\n\t" | |
| 9537 "FSTP_D $dst\t# D-round" %} | |
| 9538 opcode(0xD8, 0x5); | |
|
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9539 ins_encode( Push_Reg_DPR(src2), |
|
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9540 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9541 ins_pipe( fpu_mem_reg_reg ); |
| 9542 %} | |
| 9543 | |
| 9544 | |
|
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9545 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9546 predicate (UseSSE <=1); |
| 9547 match(Set dst (SubD dst (LoadD src))); | |
| 9548 ins_cost(150); | |
| 9549 | |
| 9550 format %{ "FLD $src\n\t" | |
| 9551 "DSUBp $dst,ST" %} | |
| 9552 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9553 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9554 OpcP, RegOpc(dst) ); | |
| 9555 ins_pipe( fpu_reg_mem ); | |
| 9556 %} | |
| 9557 | |
|
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9558 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9559 predicate (UseSSE<=1); |
| 9560 match(Set dst (AbsD src)); | |
| 9561 ins_cost(100); | |
| 9562 format %{ "FABS" %} | |
| 9563 opcode(0xE1, 0xD9); | |
| 9564 ins_encode( OpcS, OpcP ); | |
| 9565 ins_pipe( fpu_reg_reg ); | |
| 9566 %} | |
| 9567 | |
|
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9568 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9569 predicate(UseSSE<=1); |
| 9570 match(Set dst (NegD src)); | |
| 9571 ins_cost(100); | |
| 9572 format %{ "FCHS" %} | |
| 9573 opcode(0xE0, 0xD9); | |
| 9574 ins_encode( OpcS, OpcP ); | |
| 9575 ins_pipe( fpu_reg_reg ); | |
| 9576 %} | |
| 9577 | |
|
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9578 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9579 predicate(UseSSE<=1); |
| 9580 match(Set dst (AddD dst src)); | |
| 9581 format %{ "FLD $src\n\t" | |
| 9582 "DADD $dst,ST" %} | |
| 9583 size(4); | |
| 9584 ins_cost(150); | |
| 9585 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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|
9586 ins_encode( Push_Reg_DPR(src), |
| 0 | 9587 OpcP, RegOpc(dst) ); |
| 9588 ins_pipe( fpu_reg_reg ); | |
| 9589 %} | |
| 9590 | |
| 9591 | |
|
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9592 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9593 predicate(UseSSE<=1); |
| 9594 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9595 ins_cost(250); | |
| 9596 | |
| 9597 format %{ "FLD $src2\n\t" | |
| 9598 "DADD ST,$src1\n\t" | |
| 9599 "FSTP_D $dst\t# D-round" %} | |
| 9600 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
|
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|
9601 ins_encode( Push_Reg_DPR(src2), |
|
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|
9602 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9603 ins_pipe( fpu_mem_reg_reg ); |
| 9604 %} | |
| 9605 | |
| 9606 | |
|
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9607 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9608 predicate(UseSSE<=1); |
| 9609 match(Set dst (AddD dst (LoadD src))); | |
| 9610 ins_cost(150); | |
| 9611 | |
| 9612 format %{ "FLD $src\n\t" | |
| 9613 "DADDp $dst,ST" %} | |
| 9614 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9615 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9616 OpcP, RegOpc(dst) ); | |
| 9617 ins_pipe( fpu_reg_mem ); | |
| 9618 %} | |
| 9619 | |
| 9620 // add-to-memory | |
|
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|
9621 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9622 predicate(UseSSE<=1); |
| 9623 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9624 ins_cost(150); | |
| 9625 | |
| 9626 format %{ "FLD_D $dst\n\t" | |
| 9627 "DADD ST,$src\n\t" | |
| 9628 "FST_D $dst" %} | |
| 9629 opcode(0xDD, 0x0); | |
| 9630 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9631 Opcode(0xD8), RegOpc(src), | |
| 9632 set_instruction_start, | |
| 9633 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9634 ins_pipe( fpu_reg_mem ); | |
| 9635 %} | |
| 9636 | |
|
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|
9637 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9638 predicate(UseSSE<=1); |
| 2008 | 9639 match(Set dst (AddD dst con)); |
| 0 | 9640 ins_cost(125); |
| 9641 format %{ "FLD1\n\t" | |
| 9642 "DADDp $dst,ST" %} | |
| 2008 | 9643 ins_encode %{ |
| 9644 __ fld1(); | |
| 9645 __ faddp($dst$$reg); | |
| 9646 %} | |
| 9647 ins_pipe(fpu_reg); | |
| 9648 %} | |
| 9649 | |
|
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|
9650 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9651 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9652 match(Set dst (AddD dst con)); |
| 0 | 9653 ins_cost(200); |
| 2008 | 9654 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9655 "DADDp $dst,ST" %} |
| 2008 | 9656 ins_encode %{ |
| 9657 __ fld_d($constantaddress($con)); | |
| 9658 __ faddp($dst$$reg); | |
| 9659 %} | |
| 9660 ins_pipe(fpu_reg_mem); | |
| 0 | 9661 %} |
| 9662 | |
|
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|
9663 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9664 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9665 match(Set dst (RoundDouble (AddD src con))); | |
| 9666 ins_cost(200); | |
| 2008 | 9667 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9668 "DADD ST,$src\n\t" |
| 9669 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9670 ins_encode %{ |
| 9671 __ fld_d($constantaddress($con)); | |
| 9672 __ fadd($src$$reg); | |
| 9673 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9674 %} | |
| 9675 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9676 %} |
| 9677 | |
|
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|
9678 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9679 predicate(UseSSE<=1); |
| 9680 match(Set dst (MulD dst src)); | |
| 9681 format %{ "FLD $src\n\t" | |
| 9682 "DMULp $dst,ST" %} | |
| 9683 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9684 ins_cost(150); | |
|
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|
9685 ins_encode( Push_Reg_DPR(src), |
| 0 | 9686 OpcP, RegOpc(dst) ); |
| 9687 ins_pipe( fpu_reg_reg ); | |
| 9688 %} | |
| 9689 | |
| 9690 // Strict FP instruction biases argument before multiply then | |
| 9691 // biases result to avoid double rounding of subnormals. | |
| 9692 // | |
| 9693 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9694 // load arg2 | |
| 9695 // multiply scaled arg1 by arg2 | |
| 9696 // rescale product by 2^(15360) | |
| 9697 // | |
|
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|
9698 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9699 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9700 match(Set dst (MulD dst src)); | |
| 9701 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9702 | |
| 9703 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9704 "DMULp $dst,ST\n\t" | |
| 9705 "FLD $src\n\t" | |
| 9706 "DMULp $dst,ST\n\t" | |
| 9707 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9708 "DMULp $dst,ST\n\t" %} | |
| 9709 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9710 ins_encode( strictfp_bias1(dst), | |
|
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|
9711 Push_Reg_DPR(src), |
| 0 | 9712 OpcP, RegOpc(dst), |
| 9713 strictfp_bias2(dst) ); | |
| 9714 ins_pipe( fpu_reg_reg ); | |
| 9715 %} | |
| 9716 | |
|
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|
9717 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9718 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9719 match(Set dst (MulD dst con)); |
| 0 | 9720 ins_cost(200); |
| 2008 | 9721 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9722 "DMULp $dst,ST" %} |
| 2008 | 9723 ins_encode %{ |
| 9724 __ fld_d($constantaddress($con)); | |
| 9725 __ fmulp($dst$$reg); | |
| 9726 %} | |
| 9727 ins_pipe(fpu_reg_mem); | |
| 0 | 9728 %} |
| 9729 | |
| 9730 | |
|
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|
9731 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9732 predicate( UseSSE<=1 ); |
| 9733 match(Set dst (MulD dst (LoadD src))); | |
| 9734 ins_cost(200); | |
| 9735 format %{ "FLD_D $src\n\t" | |
| 9736 "DMULp $dst,ST" %} | |
| 9737 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9738 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9739 OpcP, RegOpc(dst) ); | |
| 9740 ins_pipe( fpu_reg_mem ); | |
| 9741 %} | |
| 9742 | |
| 9743 // | |
| 9744 // Cisc-alternate to reg-reg multiply | |
|
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9745 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9746 predicate( UseSSE<=1 ); |
| 9747 match(Set dst (MulD src (LoadD mem))); | |
| 9748 ins_cost(250); | |
| 9749 format %{ "FLD_D $mem\n\t" | |
| 9750 "DMUL ST,$src\n\t" | |
| 9751 "FSTP_D $dst" %} | |
| 9752 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9753 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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|
9754 OpcReg_FPR(src), |
|
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|
9755 Pop_Reg_DPR(dst) ); |
| 0 | 9756 ins_pipe( fpu_reg_reg_mem ); |
| 9757 %} | |
| 9758 | |
| 9759 | |
|
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9760 // MACRO3 -- addDPR a mulDPR |
| 0 | 9761 // This instruction is a '2-address' instruction in that the result goes |
| 9762 // back to src2. This eliminates a move from the macro; possibly the | |
| 9763 // register allocator will have to add it back (and maybe not). | |
|
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9764 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9765 predicate( UseSSE<=1 ); |
| 9766 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9767 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9768 "DMUL ST,$src1\n\t" | |
| 9769 "DADDp $src2,ST" %} | |
| 9770 ins_cost(250); | |
| 9771 opcode(0xDD); /* LoadD DD /0 */ | |
|
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|
9772 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9773 FMul_ST_reg(src1), |
| 9774 FAddP_reg_ST(src2) ); | |
| 9775 ins_pipe( fpu_reg_reg_reg ); | |
| 9776 %} | |
| 9777 | |
| 9778 | |
|
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|
9779 // MACRO3 -- subDPR a mulDPR |
|
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9780 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9781 predicate( UseSSE<=1 ); |
| 9782 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9783 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9784 "DMUL ST,$src1\n\t" | |
| 9785 "DSUBRp $src2,ST" %} | |
| 9786 ins_cost(250); | |
|
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|
9787 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9788 FMul_ST_reg(src1), |
| 9789 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9790 ins_pipe( fpu_reg_reg_reg ); | |
| 9791 %} | |
| 9792 | |
| 9793 | |
|
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9794 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9795 predicate( UseSSE<=1 ); |
| 9796 match(Set dst (DivD dst src)); | |
| 9797 | |
| 9798 format %{ "FLD $src\n\t" | |
| 9799 "FDIVp $dst,ST" %} | |
| 9800 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9801 ins_cost(150); | |
|
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|
9802 ins_encode( Push_Reg_DPR(src), |
| 0 | 9803 OpcP, RegOpc(dst) ); |
| 9804 ins_pipe( fpu_reg_reg ); | |
| 9805 %} | |
| 9806 | |
| 9807 // Strict FP instruction biases argument before division then | |
| 9808 // biases result, to avoid double rounding of subnormals. | |
| 9809 // | |
| 9810 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9811 // load divisor | |
| 9812 // divide scaled dividend by divisor | |
| 9813 // rescale quotient by 2^(15360) | |
| 9814 // | |
|
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|
9815 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9816 predicate (UseSSE<=1); |
| 9817 match(Set dst (DivD dst src)); | |
| 9818 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9819 ins_cost(01); | |
| 9820 | |
| 9821 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9822 "DMULp $dst,ST\n\t" | |
| 9823 "FLD $src\n\t" | |
| 9824 "FDIVp $dst,ST\n\t" | |
| 9825 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9826 "DMULp $dst,ST\n\t" %} | |
| 9827 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9828 ins_encode( strictfp_bias1(dst), | |
|
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|
9829 Push_Reg_DPR(src), |
| 0 | 9830 OpcP, RegOpc(dst), |
| 9831 strictfp_bias2(dst) ); | |
| 9832 ins_pipe( fpu_reg_reg ); | |
| 9833 %} | |
| 9834 | |
|
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|
9835 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9836 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9837 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9838 | |
| 9839 format %{ "FLD $src1\n\t" | |
| 9840 "FDIV ST,$src2\n\t" | |
| 9841 "FSTP_D $dst\t# D-round" %} | |
| 9842 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
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|
9843 ins_encode( Push_Reg_DPR(src1), |
|
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|
9844 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9845 ins_pipe( fpu_mem_reg_reg ); |
| 9846 %} | |
| 9847 | |
| 9848 | |
|
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|
9849 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9850 predicate(UseSSE<=1); |
| 9851 match(Set dst (ModD dst src)); | |
|
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|
9852 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9853 |
| 9854 format %{ "DMOD $dst,$src" %} | |
| 9855 ins_cost(250); | |
|
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|
9856 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
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|
9857 emitModDPR(), |
|
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|
9858 Push_Result_Mod_DPR(src), |
|
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|
9859 Pop_Reg_DPR(dst)); |
|
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|
9860 ins_pipe( pipe_slow ); |
|
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|
9861 %} |
|
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|
9862 |
|
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|
9863 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9864 predicate(UseSSE>=2); |
| 9865 match(Set dst (ModD src0 src1)); | |
| 9866 effect(KILL rax, KILL cr); | |
| 9867 | |
| 9868 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9869 "\tMOVSD [ESP+0],$src1\n" | |
| 9870 "\tFLD_D [ESP+0]\n" | |
| 9871 "\tMOVSD [ESP+0],$src0\n" | |
| 9872 "\tFLD_D [ESP+0]\n" | |
| 9873 "loop:\tFPREM\n" | |
| 9874 "\tFWAIT\n" | |
| 9875 "\tFNSTSW AX\n" | |
| 9876 "\tSAHF\n" | |
| 9877 "\tJP loop\n" | |
| 9878 "\tFSTP_D [ESP+0]\n" | |
| 9879 "\tMOVSD $dst,[ESP+0]\n" | |
| 9880 "\tADD ESP,8\n" | |
| 9881 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9882 %} | |
| 9883 ins_cost(250); | |
|
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|
9884 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
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|
9885 ins_pipe( pipe_slow ); |
|
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|
9886 %} |
|
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|
9887 |
|
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|
9888 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9889 predicate (UseSSE<=1); |
| 9890 match(Set dst (SinD src)); | |
| 9891 ins_cost(1800); | |
| 9892 format %{ "DSIN $dst" %} | |
| 9893 opcode(0xD9, 0xFE); | |
| 9894 ins_encode( OpcP, OpcS ); | |
| 9895 ins_pipe( pipe_slow ); | |
| 9896 %} | |
| 9897 | |
|
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|
9898 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9899 predicate (UseSSE>=2); |
| 9900 match(Set dst (SinD dst)); | |
|
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|
9901 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9902 ins_cost(1800); |
| 9903 format %{ "DSIN $dst" %} | |
| 9904 opcode(0xD9, 0xFE); | |
|
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|
9905 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
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|
9906 ins_pipe( pipe_slow ); |
|
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|
9907 %} |
|
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|
9908 |
|
65149e74c706
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|
9909 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9910 predicate (UseSSE<=1); |
| 9911 match(Set dst (CosD src)); | |
| 9912 ins_cost(1800); | |
| 9913 format %{ "DCOS $dst" %} | |
| 9914 opcode(0xD9, 0xFF); | |
| 9915 ins_encode( OpcP, OpcS ); | |
| 9916 ins_pipe( pipe_slow ); | |
| 9917 %} | |
| 9918 | |
|
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|
9919 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9920 predicate (UseSSE>=2); |
| 9921 match(Set dst (CosD dst)); | |
|
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|
9922 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9923 ins_cost(1800); |
| 9924 format %{ "DCOS $dst" %} | |
| 9925 opcode(0xD9, 0xFF); | |
|
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|
9926 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
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|
9927 ins_pipe( pipe_slow ); |
|
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|
9928 %} |
|
65149e74c706
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changeset
|
9929 |
|
65149e74c706
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|
9930 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9931 predicate (UseSSE<=1); |
| 9932 match(Set dst(TanD src)); | |
| 9933 format %{ "DTAN $dst" %} | |
| 9934 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9935 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9936 ins_pipe( pipe_slow ); | |
| 9937 %} | |
| 9938 | |
|
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|
9939 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9940 predicate (UseSSE>=2); |
| 9941 match(Set dst(TanD dst)); | |
|
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|
9942 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9943 format %{ "DTAN $dst" %} |
|
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|
9944 ins_encode( Push_SrcD(dst), |
| 0 | 9945 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9946 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
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|
9947 Push_ResultD(dst) ); |
|
65149e74c706
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|
9948 ins_pipe( pipe_slow ); |
|
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|
9949 %} |
|
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changeset
|
9950 |
|
65149e74c706
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|
9951 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9952 predicate (UseSSE<=1); |
| 9953 match(Set dst(AtanD dst src)); | |
| 9954 format %{ "DATA $dst,$src" %} | |
| 9955 opcode(0xD9, 0xF3); | |
|
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|
9956 ins_encode( Push_Reg_DPR(src), |
| 0 | 9957 OpcP, OpcS, RegOpc(dst) ); |
| 9958 ins_pipe( pipe_slow ); | |
| 9959 %} | |
| 9960 | |
|
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|
9961 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9962 predicate (UseSSE>=2); |
| 9963 match(Set dst(AtanD dst src)); | |
|
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|
9964 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9965 format %{ "DATA $dst,$src" %} |
| 9966 opcode(0xD9, 0xF3); | |
|
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|
9967 ins_encode( Push_SrcD(src), |
|
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|
9968 OpcP, OpcS, Push_ResultD(dst) ); |
|
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|
9969 ins_pipe( pipe_slow ); |
|
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|
9970 %} |
|
65149e74c706
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|
9971 |
|
65149e74c706
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|
9972 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9973 predicate (UseSSE<=1); |
| 9974 match(Set dst (SqrtD src)); | |
| 9975 format %{ "DSQRT $dst,$src" %} | |
| 9976 opcode(0xFA, 0xD9); | |
|
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|
9977 ins_encode( Push_Reg_DPR(src), |
|
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|
9978 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
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|
9979 ins_pipe( pipe_slow ); |
|
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|
9980 %} |
|
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|
9981 |
|
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|
9982 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9983 predicate (UseSSE<=1); |
| 9984 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
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|
9985 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
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|
9986 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
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|
9987 ins_encode %{ |
|
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|
9988 __ subptr(rsp, 8); |
|
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|
9989 __ fld_s($X$$reg - 1); |
|
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|
9990 __ fast_pow(); |
|
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|
9991 __ addptr(rsp, 8); |
|
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|
9992 %} |
|
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|
9993 ins_pipe( pipe_slow ); |
|
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|
9994 %} |
|
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|
9995 |
|
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|
9996 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9997 predicate (UseSSE>=2); |
| 9998 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
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|
9999 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
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|
10000 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
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|
10001 ins_encode %{ |
|
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|
10002 __ subptr(rsp, 8); |
|
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|
10003 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
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|
10004 __ fld_d(Address(rsp, 0)); |
|
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|
10005 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
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changeset
|
10006 __ fld_d(Address(rsp, 0)); |
|
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|
10007 __ fast_pow(); |
|
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|
10008 __ fstp_d(Address(rsp, 0)); |
|
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|
10009 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
10010 __ addptr(rsp, 8); |
|
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changeset
|
10011 %} |
|
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changeset
|
10012 ins_pipe( pipe_slow ); |
|
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|
10013 %} |
|
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|
10014 |
|
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|
10015 |
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|
10016 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10017 predicate (UseSSE<=1); |
| 10018 match(Set dpr1 (ExpD dpr1)); | |
|
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|
10019 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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|
10020 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
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|
10021 ins_encode %{ |
|
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|
10022 __ fast_exp(); |
|
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|
10023 %} |
|
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|
10024 ins_pipe( pipe_slow ); |
|
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|
10025 %} |
|
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|
10026 |
|
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|
10027 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10028 predicate (UseSSE>=2); |
| 10029 match(Set dst (ExpD src)); | |
|
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|
10030 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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|
10031 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
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|
10032 ins_encode %{ |
|
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|
10033 __ subptr(rsp, 8); |
|
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|
10034 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
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|
10035 __ fld_d(Address(rsp, 0)); |
|
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|
10036 __ fast_exp(); |
|
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|
10037 __ fstp_d(Address(rsp, 0)); |
|
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|
10038 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
10039 __ addptr(rsp, 8); |
|
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|
10040 %} |
|
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|
10041 ins_pipe( pipe_slow ); |
|
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|
10042 %} |
|
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|
10043 |
|
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|
10044 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10045 predicate (UseSSE<=1); |
| 10046 // The source Double operand on FPU stack | |
| 10047 match(Set dst (Log10D src)); | |
| 10048 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10049 // fxch ; swap ST(0) with ST(1) | |
| 10050 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10051 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10052 "FXCH \n\t" | |
| 10053 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10054 %} | |
| 10055 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10056 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10057 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10058 | |
| 10059 ins_pipe( pipe_slow ); | |
| 10060 %} | |
| 10061 | |
|
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|
10062 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10063 predicate (UseSSE>=2); |
| 10064 effect(KILL cr); | |
| 10065 match(Set dst (Log10D src)); | |
| 10066 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10067 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10068 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10069 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10070 %} | |
| 10071 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
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|
10072 Push_SrcD(src), |
| 0 | 10073 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
10074 Push_ResultD(dst)); |
|
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|
10075 |
|
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|
10076 ins_pipe( pipe_slow ); |
|
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|
10077 %} |
|
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|
10078 |
|
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|
10079 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10080 predicate (UseSSE<=1); |
| 10081 // The source Double operand on FPU stack | |
| 10082 match(Set dst (LogD src)); | |
| 10083 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10084 // fxch ; swap ST(0) with ST(1) | |
| 10085 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10086 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10087 "FXCH \n\t" | |
| 10088 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10089 %} | |
| 10090 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10091 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10092 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10093 | |
| 10094 ins_pipe( pipe_slow ); | |
| 10095 %} | |
| 10096 | |
|
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|
10097 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10098 predicate (UseSSE>=2); |
| 10099 effect(KILL cr); | |
| 10100 // The source and result Double operands in XMM registers | |
| 10101 match(Set dst (LogD src)); | |
| 10102 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10103 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10104 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10105 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10106 %} | |
| 10107 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
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|
10108 Push_SrcD(src), |
| 0 | 10109 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
10110 Push_ResultD(dst)); |
| 0 | 10111 ins_pipe( pipe_slow ); |
| 10112 %} | |
| 10113 | |
| 10114 //-------------Float Instructions------------------------------- | |
| 10115 // Float Math | |
| 10116 | |
| 10117 // Code for float compare: | |
| 10118 // fcompp(); | |
| 10119 // fwait(); fnstsw_ax(); | |
| 10120 // sahf(); | |
| 10121 // movl(dst, unordered_result); | |
| 10122 // jcc(Assembler::parity, exit); | |
| 10123 // movl(dst, less_result); | |
| 10124 // jcc(Assembler::below, exit); | |
| 10125 // movl(dst, equal_result); | |
| 10126 // jcc(Assembler::equal, exit); | |
| 10127 // movl(dst, greater_result); | |
| 10128 // exit: | |
| 10129 | |
| 10130 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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|
10131 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10132 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10133 match(Set cr (CmpF src1 src2)); | |
| 10134 effect(KILL rax); | |
| 10135 ins_cost(150); | |
| 10136 format %{ "FLD $src1\n\t" | |
| 10137 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10138 "JNP exit\n\t" | |
| 10139 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10140 "SAHF\n" | |
| 10141 "exit:\tNOP // avoid branch to branch" %} | |
| 10142 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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|
10143 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10144 OpcP, RegOpc(src2), |
| 10145 cmpF_P6_fixup ); | |
| 10146 ins_pipe( pipe_slow ); | |
| 10147 %} | |
| 10148 | |
|
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|
10149 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
415
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changeset
|
10150 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
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|
10151 match(Set cr (CmpF src1 src2)); |
|
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|
10152 ins_cost(100); |
|
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changeset
|
10153 format %{ "FLD $src1\n\t" |
|
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diff
changeset
|
10154 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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diff
changeset
|
10155 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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|
10156 ins_encode( Push_Reg_DPR(src1), |
|
415
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changeset
|
10157 OpcP, RegOpc(src2)); |
|
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diff
changeset
|
10158 ins_pipe( pipe_slow ); |
|
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parents:
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diff
changeset
|
10159 %} |
|
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|
10160 |
| 0 | 10161 |
| 10162 // Compare & branch | |
|
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|
10163 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10164 predicate(UseSSE == 0); |
| 10165 match(Set cr (CmpF src1 src2)); | |
| 10166 effect(KILL rax); | |
| 10167 ins_cost(200); | |
| 10168 format %{ "FLD $src1\n\t" | |
| 10169 "FCOMp $src2\n\t" | |
| 10170 "FNSTSW AX\n\t" | |
| 10171 "TEST AX,0x400\n\t" | |
| 10172 "JZ,s flags\n\t" | |
| 10173 "MOV AH,1\t# unordered treat as LT\n" | |
| 10174 "flags:\tSAHF" %} | |
| 10175 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
10176 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10177 OpcP, RegOpc(src2), |
| 10178 fpu_flags); | |
| 10179 ins_pipe( pipe_slow ); | |
| 10180 %} | |
| 10181 | |
| 10182 // Compare vs zero into -1,0,1 | |
|
6179
8c92982cbbc4
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|
10183 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10184 predicate(UseSSE == 0); |
| 10185 match(Set dst (CmpF3 src1 zero)); | |
| 10186 effect(KILL cr, KILL rax); | |
| 10187 ins_cost(280); | |
| 10188 format %{ "FTSTF $dst,$src1" %} | |
| 10189 opcode(0xE4, 0xD9); | |
|
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|
10190 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10191 OpcS, OpcP, PopFPU, |
| 10192 CmpF_Result(dst)); | |
| 10193 ins_pipe( pipe_slow ); | |
| 10194 %} | |
| 10195 | |
| 10196 // Compare into -1,0,1 | |
|
6179
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|
10197 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10198 predicate(UseSSE == 0); |
| 10199 match(Set dst (CmpF3 src1 src2)); | |
| 10200 effect(KILL cr, KILL rax); | |
| 10201 ins_cost(300); | |
| 10202 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10203 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
10204 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10205 OpcP, RegOpc(src2), |
| 10206 CmpF_Result(dst)); | |
| 10207 ins_pipe( pipe_slow ); | |
| 10208 %} | |
| 10209 | |
| 10210 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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|
10211 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10212 predicate(UseSSE>=1); |
| 4759 | 10213 match(Set cr (CmpF src1 src2)); |
| 0 | 10214 ins_cost(145); |
| 4759 | 10215 format %{ "UCOMISS $src1,$src2\n\t" |
| 10216 "JNP,s exit\n\t" | |
| 10217 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10218 "AND [rsp], #0xffffff2b\n\t" | |
| 10219 "POPF\n" | |
| 10220 "exit:" %} | |
| 10221 ins_encode %{ | |
| 10222 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10223 emit_cmpfp_fixup(_masm); | |
| 10224 %} | |
| 10225 ins_pipe( pipe_slow ); | |
| 10226 %} | |
| 10227 | |
|
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|
10228 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
415
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changeset
|
10229 predicate(UseSSE>=1); |
| 4759 | 10230 match(Set cr (CmpF src1 src2)); |
|
415
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changeset
|
10231 ins_cost(100); |
| 4759 | 10232 format %{ "UCOMISS $src1,$src2" %} |
| 10233 ins_encode %{ | |
| 10234 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10235 %} | |
|
415
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changeset
|
10236 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
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parents:
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changeset
|
10237 %} |
|
4d9884b01ba6
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changeset
|
10238 |
| 0 | 10239 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
10240 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10241 predicate(UseSSE>=1); |
| 4759 | 10242 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10243 ins_cost(165); |
| 4759 | 10244 format %{ "UCOMISS $src1,$src2\n\t" |
| 10245 "JNP,s exit\n\t" | |
| 10246 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10247 "AND [rsp], #0xffffff2b\n\t" | |
| 10248 "POPF\n" | |
| 10249 "exit:" %} | |
| 10250 ins_encode %{ | |
| 10251 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10252 emit_cmpfp_fixup(_masm); | |
| 10253 %} | |
| 10254 ins_pipe( pipe_slow ); | |
| 10255 %} | |
| 10256 | |
|
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|
10257 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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10258 predicate(UseSSE>=1); |
| 4759 | 10259 match(Set cr (CmpF src1 (LoadF src2))); |
|
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10260 ins_cost(100); |
| 4759 | 10261 format %{ "UCOMISS $src1,$src2" %} |
| 10262 ins_encode %{ | |
| 10263 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10264 %} | |
|
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10265 ins_pipe( pipe_slow ); |
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10266 %} |
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10267 |
| 0 | 10268 // Compare into -1,0,1 in XMM |
|
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10269 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10270 predicate(UseSSE>=1); |
| 10271 match(Set dst (CmpF3 src1 src2)); | |
| 10272 effect(KILL cr); | |
| 10273 ins_cost(255); | |
| 4759 | 10274 format %{ "UCOMISS $src1, $src2\n\t" |
| 10275 "MOV $dst, #-1\n\t" | |
| 10276 "JP,s done\n\t" | |
| 10277 "JB,s done\n\t" | |
| 10278 "SETNE $dst\n\t" | |
| 10279 "MOVZB $dst, $dst\n" | |
| 10280 "done:" %} | |
| 10281 ins_encode %{ | |
| 10282 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10283 emit_cmpfp3(_masm, $dst$$Register); | |
| 10284 %} | |
| 0 | 10285 ins_pipe( pipe_slow ); |
| 10286 %} | |
| 10287 | |
| 10288 // Compare into -1,0,1 in XMM and memory | |
|
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10289 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10290 predicate(UseSSE>=1); |
| 4759 | 10291 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10292 effect(KILL cr); |
| 10293 ins_cost(275); | |
| 4759 | 10294 format %{ "UCOMISS $src1, $src2\n\t" |
| 10295 "MOV $dst, #-1\n\t" | |
| 10296 "JP,s done\n\t" | |
| 10297 "JB,s done\n\t" | |
| 10298 "SETNE $dst\n\t" | |
| 10299 "MOVZB $dst, $dst\n" | |
| 10300 "done:" %} | |
| 10301 ins_encode %{ | |
| 10302 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10303 emit_cmpfp3(_masm, $dst$$Register); | |
| 10304 %} | |
| 0 | 10305 ins_pipe( pipe_slow ); |
| 10306 %} | |
| 10307 | |
| 10308 // Spill to obtain 24-bit precision | |
|
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10309 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10310 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10311 match(Set dst (SubF src1 src2)); | |
| 10312 | |
| 10313 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10314 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
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10315 ins_encode( Push_Reg_FPR(src1), |
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10316 OpcReg_FPR(src2), |
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10317 Pop_Mem_FPR(dst) ); |
| 0 | 10318 ins_pipe( fpu_mem_reg_reg ); |
| 10319 %} | |
| 10320 // | |
| 10321 // This instruction does not round to 24-bits | |
|
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10322 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10323 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10324 match(Set dst (SubF dst src)); | |
| 10325 | |
| 10326 format %{ "FSUB $dst,$src" %} | |
| 10327 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
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10328 ins_encode( Push_Reg_FPR(src), |
| 0 | 10329 OpcP, RegOpc(dst) ); |
| 10330 ins_pipe( fpu_reg_reg ); | |
| 10331 %} | |
| 10332 | |
| 10333 // Spill to obtain 24-bit precision | |
|
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10334 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10335 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10336 match(Set dst (AddF src1 src2)); | |
| 10337 | |
| 10338 format %{ "FADD $dst,$src1,$src2" %} | |
| 10339 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
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10340 ins_encode( Push_Reg_FPR(src2), |
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10341 OpcReg_FPR(src1), |
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10342 Pop_Mem_FPR(dst) ); |
| 0 | 10343 ins_pipe( fpu_mem_reg_reg ); |
| 10344 %} | |
| 10345 // | |
| 10346 // This instruction does not round to 24-bits | |
|
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10347 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10348 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10349 match(Set dst (AddF dst src)); | |
| 10350 | |
| 10351 format %{ "FLD $src\n\t" | |
| 10352 "FADDp $dst,ST" %} | |
| 10353 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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10354 ins_encode( Push_Reg_FPR(src), |
| 0 | 10355 OpcP, RegOpc(dst) ); |
| 10356 ins_pipe( fpu_reg_reg ); | |
| 10357 %} | |
| 10358 | |
|
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10359 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10360 predicate(UseSSE==0); |
| 10361 match(Set dst (AbsF src)); | |
| 10362 ins_cost(100); | |
| 10363 format %{ "FABS" %} | |
| 10364 opcode(0xE1, 0xD9); | |
| 10365 ins_encode( OpcS, OpcP ); | |
| 10366 ins_pipe( fpu_reg_reg ); | |
| 10367 %} | |
| 10368 | |
|
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10369 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10370 predicate(UseSSE==0); |
| 10371 match(Set dst (NegF src)); | |
| 10372 ins_cost(100); | |
| 10373 format %{ "FCHS" %} | |
| 10374 opcode(0xE0, 0xD9); | |
| 10375 ins_encode( OpcS, OpcP ); | |
| 10376 ins_pipe( fpu_reg_reg ); | |
| 10377 %} | |
| 10378 | |
|
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10379 // Cisc-alternate to addFPR_reg |
| 0 | 10380 // Spill to obtain 24-bit precision |
|
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10381 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10382 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10383 match(Set dst (AddF src1 (LoadF src2))); | |
| 10384 | |
| 10385 format %{ "FLD $src2\n\t" | |
| 10386 "FADD ST,$src1\n\t" | |
| 10387 "FSTP_S $dst" %} | |
| 10388 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10389 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10390 OpcReg_FPR(src1), |
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10391 Pop_Mem_FPR(dst) ); |
| 0 | 10392 ins_pipe( fpu_mem_reg_mem ); |
| 10393 %} | |
| 10394 // | |
|
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10395 // Cisc-alternate to addFPR_reg |
| 0 | 10396 // This instruction does not round to 24-bits |
|
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10397 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10398 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10399 match(Set dst (AddF dst (LoadF src))); | |
| 10400 | |
| 10401 format %{ "FADD $dst,$src" %} | |
| 10402 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10403 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10404 OpcP, RegOpc(dst) ); | |
| 10405 ins_pipe( fpu_reg_mem ); | |
| 10406 %} | |
| 10407 | |
| 10408 // // Following two instructions for _222_mpegaudio | |
| 10409 // Spill to obtain 24-bit precision | |
|
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10410 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10411 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10412 match(Set dst (AddF src1 src2)); | |
| 10413 | |
| 10414 format %{ "FADD $dst,$src1,$src2" %} | |
| 10415 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10416 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
|
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10417 OpcReg_FPR(src2), |
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10418 Pop_Mem_FPR(dst) ); |
| 0 | 10419 ins_pipe( fpu_mem_reg_mem ); |
| 10420 %} | |
| 10421 | |
| 10422 // Cisc-spill variant | |
| 10423 // Spill to obtain 24-bit precision | |
|
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10424 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10425 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10426 match(Set dst (AddF src1 (LoadF src2))); | |
| 10427 | |
| 10428 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10429 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10430 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10431 set_instruction_start, | |
| 10432 OpcP, RMopc_Mem(secondary,src1), | |
|
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10433 Pop_Mem_FPR(dst) ); |
| 0 | 10434 ins_pipe( fpu_mem_mem_mem ); |
| 10435 %} | |
| 10436 | |
| 10437 // Spill to obtain 24-bit precision | |
|
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10438 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10439 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10440 match(Set dst (AddF src1 src2)); | |
| 10441 | |
| 10442 format %{ "FADD $dst,$src1,$src2" %} | |
| 10443 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10444 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10445 set_instruction_start, | |
| 10446 OpcP, RMopc_Mem(secondary,src1), | |
|
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10447 Pop_Mem_FPR(dst) ); |
| 0 | 10448 ins_pipe( fpu_mem_mem_mem ); |
| 10449 %} | |
| 10450 | |
| 10451 | |
| 10452 // Spill to obtain 24-bit precision | |
|
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10453 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10454 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10455 match(Set dst (AddF src con)); |
| 10456 format %{ "FLD $src\n\t" | |
| 10457 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10458 "FSTP_S $dst" %} |
| 2008 | 10459 ins_encode %{ |
| 10460 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10461 __ fadd_s($constantaddress($con)); | |
| 10462 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10463 %} | |
| 10464 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10465 %} |
| 10466 // | |
| 10467 // This instruction does not round to 24-bits | |
|
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10468 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10469 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10470 match(Set dst (AddF src con)); |
| 10471 format %{ "FLD $src\n\t" | |
| 10472 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10473 "FSTP $dst" %} | |
| 10474 ins_encode %{ | |
| 10475 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10476 __ fadd_s($constantaddress($con)); | |
| 10477 __ fstp_d($dst$$reg); | |
| 10478 %} | |
| 10479 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10480 %} |
| 10481 | |
| 10482 // Spill to obtain 24-bit precision | |
|
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10483 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10484 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10485 match(Set dst (MulF src1 src2)); | |
| 10486 | |
| 10487 format %{ "FLD $src1\n\t" | |
| 10488 "FMUL $src2\n\t" | |
| 10489 "FSTP_S $dst" %} | |
| 10490 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
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10491 ins_encode( Push_Reg_FPR(src1), |
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10492 OpcReg_FPR(src2), |
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10493 Pop_Mem_FPR(dst) ); |
| 0 | 10494 ins_pipe( fpu_mem_reg_reg ); |
| 10495 %} | |
| 10496 // | |
| 10497 // This instruction does not round to 24-bits | |
|
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10498 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10499 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10500 match(Set dst (MulF src1 src2)); | |
| 10501 | |
| 10502 format %{ "FLD $src1\n\t" | |
| 10503 "FMUL $src2\n\t" | |
| 10504 "FSTP_S $dst" %} | |
| 10505 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
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10506 ins_encode( Push_Reg_FPR(src2), |
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10507 OpcReg_FPR(src1), |
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10508 Pop_Reg_FPR(dst) ); |
| 0 | 10509 ins_pipe( fpu_reg_reg_reg ); |
| 10510 %} | |
| 10511 | |
| 10512 | |
| 10513 // Spill to obtain 24-bit precision | |
| 10514 // Cisc-alternate to reg-reg multiply | |
|
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10515 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10516 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10517 match(Set dst (MulF src1 (LoadF src2))); | |
| 10518 | |
| 10519 format %{ "FLD_S $src2\n\t" | |
| 10520 "FMUL $src1\n\t" | |
| 10521 "FSTP_S $dst" %} | |
| 10522 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10523 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10524 OpcReg_FPR(src1), |
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10525 Pop_Mem_FPR(dst) ); |
| 0 | 10526 ins_pipe( fpu_mem_reg_mem ); |
| 10527 %} | |
| 10528 // | |
| 10529 // This instruction does not round to 24-bits | |
| 10530 // Cisc-alternate to reg-reg multiply | |
|
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10531 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10532 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10533 match(Set dst (MulF src1 (LoadF src2))); | |
| 10534 | |
| 10535 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10536 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10537 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10538 OpcReg_FPR(src1), |
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10539 Pop_Reg_FPR(dst) ); |
| 0 | 10540 ins_pipe( fpu_reg_reg_mem ); |
| 10541 %} | |
| 10542 | |
| 10543 // Spill to obtain 24-bit precision | |
|
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10544 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10545 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10546 match(Set dst (MulF src1 src2)); | |
| 10547 | |
| 10548 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10549 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10550 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10551 set_instruction_start, | |
| 10552 OpcP, RMopc_Mem(secondary,src1), | |
|
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10553 Pop_Mem_FPR(dst) ); |
| 0 | 10554 ins_pipe( fpu_mem_mem_mem ); |
| 10555 %} | |
| 10556 | |
| 10557 // Spill to obtain 24-bit precision | |
|
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10558 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10559 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10560 match(Set dst (MulF src con)); |
| 10561 | |
| 10562 format %{ "FLD $src\n\t" | |
| 10563 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10564 "FSTP_S $dst" %} | |
| 10565 ins_encode %{ | |
| 10566 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10567 __ fmul_s($constantaddress($con)); | |
| 10568 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10569 %} | |
| 10570 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10571 %} |
| 10572 // | |
| 10573 // This instruction does not round to 24-bits | |
|
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10574 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10575 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10576 match(Set dst (MulF src con)); |
| 10577 | |
| 10578 format %{ "FLD $src\n\t" | |
| 10579 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10580 "FSTP $dst" %} | |
| 10581 ins_encode %{ | |
| 10582 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10583 __ fmul_s($constantaddress($con)); | |
| 10584 __ fstp_d($dst$$reg); | |
| 10585 %} | |
| 10586 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10587 %} |
| 10588 | |
| 10589 | |
| 10590 // | |
|
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10591 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10592 // This instruction does not round to 24-bits |
|
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10593 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10594 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10595 match(Set dst (MulF (LoadF mem1) src)); | |
| 10596 | |
| 10597 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10598 "FMUL ST,$src\n\t" | |
| 10599 "FSTP $dst" %} | |
| 10600 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10601 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10602 OpcReg_FPR(src), |
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10603 Pop_Reg_FPR(dst) ); |
| 0 | 10604 ins_pipe( fpu_reg_reg_mem ); |
| 10605 %} | |
| 10606 // | |
|
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10607 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10608 // This instruction does not round to 24-bits |
|
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10609 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10610 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10611 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10612 ins_cost(95); | |
| 10613 | |
| 10614 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10615 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10616 "FADD ST,$src2\n\t" |
| 10617 "FSTP $dst" %} | |
| 10618 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10619 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10620 FMul_ST_reg(src1), | |
| 10621 FAdd_ST_reg(src2), | |
|
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10622 Pop_Reg_FPR(dst) ); |
| 0 | 10623 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10624 %} | |
| 10625 | |
|
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10626 // MACRO3 -- addFPR a mulFPR |
| 0 | 10627 // This instruction does not round to 24-bits. It is a '2-address' |
| 10628 // instruction in that the result goes back to src2. This eliminates | |
| 10629 // a move from the macro; possibly the register allocator will have | |
| 10630 // to add it back (and maybe not). | |
|
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10631 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10632 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10633 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10634 | |
| 10635 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10636 "FMUL ST,$src1\n\t" | |
| 10637 "FADDP $src2,ST" %} | |
| 10638 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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10639 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10640 FMul_ST_reg(src1), |
| 10641 FAddP_reg_ST(src2) ); | |
| 10642 ins_pipe( fpu_reg_reg_reg ); | |
| 10643 %} | |
| 10644 | |
|
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10645 // MACRO4 -- divFPR subFPR |
| 0 | 10646 // This instruction does not round to 24-bits |
|
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10647 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10648 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10649 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10650 | |
| 10651 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10652 "FSUB ST,$src1\n\t" | |
| 10653 "FDIV ST,$src3\n\t" | |
| 10654 "FSTP $dst" %} | |
| 10655 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10656 ins_encode( Push_Reg_FPR(src2), |
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10657 subFPR_divFPR_encode(src1,src3), |
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10658 Pop_Reg_FPR(dst) ); |
| 0 | 10659 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10660 %} | |
| 10661 | |
| 10662 // Spill to obtain 24-bit precision | |
|
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10663 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10664 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10665 match(Set dst (DivF src1 src2)); | |
| 10666 | |
| 10667 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10668 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
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10669 ins_encode( Push_Reg_FPR(src1), |
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10670 OpcReg_FPR(src2), |
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10671 Pop_Mem_FPR(dst) ); |
| 0 | 10672 ins_pipe( fpu_mem_reg_reg ); |
| 10673 %} | |
| 10674 // | |
| 10675 // This instruction does not round to 24-bits | |
|
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10676 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10677 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10678 match(Set dst (DivF dst src)); | |
| 10679 | |
| 10680 format %{ "FDIV $dst,$src" %} | |
| 10681 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10682 ins_encode( Push_Reg_FPR(src), |
| 0 | 10683 OpcP, RegOpc(dst) ); |
| 10684 ins_pipe( fpu_reg_reg ); | |
| 10685 %} | |
| 10686 | |
| 10687 | |
| 10688 // Spill to obtain 24-bit precision | |
|
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10689 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10690 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10691 match(Set dst (ModF src1 src2)); | |
|
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10692 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10693 |
| 10694 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10695 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10696 emitModDPR(), |
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10697 Push_Result_Mod_DPR(src2), |
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10698 Pop_Mem_FPR(dst)); |
| 0 | 10699 ins_pipe( pipe_slow ); |
| 10700 %} | |
| 10701 // | |
| 10702 // This instruction does not round to 24-bits | |
|
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10703 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10704 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10705 match(Set dst (ModF dst src)); | |
|
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10706 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10707 |
| 10708 format %{ "FMOD $dst,$src" %} | |
|
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10709 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10710 emitModDPR(), |
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10711 Push_Result_Mod_DPR(src), |
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10712 Pop_Reg_FPR(dst)); |
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10713 ins_pipe( pipe_slow ); |
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10714 %} |
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10715 |
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10716 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10717 predicate(UseSSE>=1); |
| 10718 match(Set dst (ModF src0 src1)); | |
| 10719 effect(KILL rax, KILL cr); | |
| 10720 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10721 "\tMOVSS [ESP+0],$src1\n" | |
| 10722 "\tFLD_S [ESP+0]\n" | |
| 10723 "\tMOVSS [ESP+0],$src0\n" | |
| 10724 "\tFLD_S [ESP+0]\n" | |
| 10725 "loop:\tFPREM\n" | |
| 10726 "\tFWAIT\n" | |
| 10727 "\tFNSTSW AX\n" | |
| 10728 "\tSAHF\n" | |
| 10729 "\tJP loop\n" | |
| 10730 "\tFSTP_S [ESP+0]\n" | |
| 10731 "\tMOVSS $dst,[ESP+0]\n" | |
| 10732 "\tADD ESP,4\n" | |
| 10733 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10734 %} | |
| 10735 ins_cost(250); | |
|
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10736 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10737 ins_pipe( pipe_slow ); |
| 10738 %} | |
| 10739 | |
| 10740 | |
| 10741 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10742 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10743 | |
|
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10744 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10745 predicate(UseSSE==0); |
| 10746 match(Set dst (RoundFloat src)); | |
| 10747 ins_cost(125); | |
| 10748 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
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10749 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10750 ins_pipe( fpu_mem_reg ); |
| 10751 %} | |
| 10752 | |
|
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10753 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10754 predicate(UseSSE<=1); |
| 10755 match(Set dst (RoundDouble src)); | |
| 10756 ins_cost(125); | |
| 10757 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
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10758 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10759 ins_pipe( fpu_mem_reg ); |
| 10760 %} | |
| 10761 | |
| 10762 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10763 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10764 predicate(UseSSE==0); |
| 10765 match(Set dst (ConvD2F src)); | |
| 10766 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10767 expand %{ | |
| 10768 roundFloat_mem_reg(dst,src); | |
| 10769 %} | |
| 10770 %} | |
| 10771 | |
| 10772 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10773 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10774 predicate(UseSSE==1); |
| 10775 match(Set dst (ConvD2F src)); | |
| 10776 effect( KILL cr ); | |
| 10777 format %{ "SUB ESP,4\n\t" | |
| 10778 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10779 "MOVSS $dst,[ESP]\n\t" | |
| 10780 "ADD ESP,4" %} | |
| 4759 | 10781 ins_encode %{ |
| 10782 __ subptr(rsp, 4); | |
| 10783 if ($src$$reg != FPR1L_enc) { | |
| 10784 __ fld_s($src$$reg-1); | |
| 10785 __ fstp_s(Address(rsp, 0)); | |
| 10786 } else { | |
| 10787 __ fst_s(Address(rsp, 0)); | |
| 10788 } | |
| 10789 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10790 __ addptr(rsp, 4); | |
| 10791 %} | |
| 0 | 10792 ins_pipe( pipe_slow ); |
| 10793 %} | |
| 10794 | |
| 10795 // Force rounding double precision to single precision | |
|
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10796 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10797 predicate(UseSSE>=2); |
| 10798 match(Set dst (ConvD2F src)); | |
| 10799 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10800 ins_encode %{ |
| 10801 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10802 %} | |
| 0 | 10803 ins_pipe( pipe_slow ); |
| 10804 %} | |
| 10805 | |
|
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10806 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10807 predicate(UseSSE==0); |
| 10808 match(Set dst (ConvF2D src)); | |
| 10809 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
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10810 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10811 ins_pipe( fpu_reg_reg ); |
| 10812 %} | |
| 10813 | |
|
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10814 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10815 predicate(UseSSE==1); |
| 10816 match(Set dst (ConvF2D src)); | |
| 10817 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10818 expand %{ | |
| 10819 roundDouble_mem_reg(dst,src); | |
| 10820 %} | |
| 10821 %} | |
| 10822 | |
|
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10823 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10824 predicate(UseSSE==1); |
| 10825 match(Set dst (ConvF2D src)); | |
| 10826 effect( KILL cr ); | |
| 10827 format %{ "SUB ESP,4\n\t" | |
| 10828 "MOVSS [ESP] $src\n\t" | |
| 10829 "FLD_S [ESP]\n\t" | |
| 10830 "ADD ESP,4\n\t" | |
| 10831 "FSTP $dst\t# D-round" %} | |
| 4759 | 10832 ins_encode %{ |
| 10833 __ subptr(rsp, 4); | |
| 10834 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10835 __ fld_s(Address(rsp, 0)); | |
| 10836 __ addptr(rsp, 4); | |
| 10837 __ fstp_d($dst$$reg); | |
| 10838 %} | |
| 0 | 10839 ins_pipe( pipe_slow ); |
| 10840 %} | |
| 10841 | |
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10842 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10843 predicate(UseSSE>=2); |
| 10844 match(Set dst (ConvF2D src)); | |
| 10845 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10846 ins_encode %{ |
| 10847 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10848 %} | |
| 0 | 10849 ins_pipe( pipe_slow ); |
| 10850 %} | |
| 10851 | |
| 10852 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
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10853 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10854 predicate(UseSSE<=1); |
| 10855 match(Set dst (ConvD2I src)); | |
| 10856 effect( KILL tmp, KILL cr ); | |
| 10857 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10858 "FLDCW trunc mode\n\t" | |
| 10859 "SUB ESP,4\n\t" | |
| 10860 "FISTp [ESP + #0]\n\t" | |
| 10861 "FLDCW std/24-bit mode\n\t" | |
| 10862 "POP EAX\n\t" | |
| 10863 "CMP EAX,0x80000000\n\t" | |
| 10864 "JNE,s fast\n\t" | |
| 10865 "FLD_D $src\n\t" | |
| 10866 "CALL d2i_wrapper\n" | |
| 10867 "fast:" %} | |
|
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10868 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10869 ins_pipe( pipe_slow ); |
| 10870 %} | |
| 10871 | |
| 10872 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
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10873 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10874 predicate(UseSSE>=2); |
| 10875 match(Set dst (ConvD2I src)); | |
| 10876 effect( KILL tmp, KILL cr ); | |
| 10877 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10878 "CMP $dst,0x80000000\n\t" | |
| 10879 "JNE,s fast\n\t" | |
| 10880 "SUB ESP, 8\n\t" | |
| 10881 "MOVSD [ESP], $src\n\t" | |
| 10882 "FLD_D [ESP]\n\t" | |
| 10883 "ADD ESP, 8\n\t" | |
| 10884 "CALL d2i_wrapper\n" | |
| 10885 "fast:" %} | |
| 4759 | 10886 ins_encode %{ |
| 10887 Label fast; | |
| 10888 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10889 __ cmpl($dst$$Register, 0x80000000); | |
| 10890 __ jccb(Assembler::notEqual, fast); | |
| 10891 __ subptr(rsp, 8); | |
| 10892 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10893 __ fld_d(Address(rsp, 0)); | |
| 10894 __ addptr(rsp, 8); | |
| 10895 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10896 __ bind(fast); | |
| 10897 %} | |
| 0 | 10898 ins_pipe( pipe_slow ); |
| 10899 %} | |
| 10900 | |
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10901 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10902 predicate(UseSSE<=1); |
| 10903 match(Set dst (ConvD2L src)); | |
| 10904 effect( KILL cr ); | |
| 10905 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10906 "FLDCW trunc mode\n\t" | |
| 10907 "SUB ESP,8\n\t" | |
| 10908 "FISTp [ESP + #0]\n\t" | |
| 10909 "FLDCW std/24-bit mode\n\t" | |
| 10910 "POP EAX\n\t" | |
| 10911 "POP EDX\n\t" | |
| 10912 "CMP EDX,0x80000000\n\t" | |
| 10913 "JNE,s fast\n\t" | |
| 10914 "TEST EAX,EAX\n\t" | |
| 10915 "JNE,s fast\n\t" | |
| 10916 "FLD $src\n\t" | |
| 10917 "CALL d2l_wrapper\n" | |
| 10918 "fast:" %} | |
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10919 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10920 ins_pipe( pipe_slow ); |
| 10921 %} | |
| 10922 | |
| 10923 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10924 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10925 predicate (UseSSE>=2); |
| 10926 match(Set dst (ConvD2L src)); | |
| 10927 effect( KILL cr ); | |
| 10928 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10929 "MOVSD [ESP],$src\n\t" | |
| 10930 "FLD_D [ESP]\n\t" | |
| 10931 "FLDCW trunc mode\n\t" | |
| 10932 "FISTp [ESP + #0]\n\t" | |
| 10933 "FLDCW std/24-bit mode\n\t" | |
| 10934 "POP EAX\n\t" | |
| 10935 "POP EDX\n\t" | |
| 10936 "CMP EDX,0x80000000\n\t" | |
| 10937 "JNE,s fast\n\t" | |
| 10938 "TEST EAX,EAX\n\t" | |
| 10939 "JNE,s fast\n\t" | |
| 10940 "SUB ESP,8\n\t" | |
| 10941 "MOVSD [ESP],$src\n\t" | |
| 10942 "FLD_D [ESP]\n\t" | |
| 4759 | 10943 "ADD ESP,8\n\t" |
| 0 | 10944 "CALL d2l_wrapper\n" |
| 10945 "fast:" %} | |
| 4759 | 10946 ins_encode %{ |
| 10947 Label fast; | |
| 10948 __ subptr(rsp, 8); | |
| 10949 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10950 __ fld_d(Address(rsp, 0)); | |
| 10951 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10952 __ fistp_d(Address(rsp, 0)); | |
| 10953 // Restore the rounding mode, mask the exception | |
| 10954 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10955 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10956 } else { | |
| 10957 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10958 } | |
| 10959 // Load the converted long, adjust CPU stack | |
| 10960 __ pop(rax); | |
| 10961 __ pop(rdx); | |
| 10962 __ cmpl(rdx, 0x80000000); | |
| 10963 __ jccb(Assembler::notEqual, fast); | |
| 10964 __ testl(rax, rax); | |
| 10965 __ jccb(Assembler::notEqual, fast); | |
| 10966 __ subptr(rsp, 8); | |
| 10967 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10968 __ fld_d(Address(rsp, 0)); | |
| 10969 __ addptr(rsp, 8); | |
| 10970 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10971 __ bind(fast); | |
| 10972 %} | |
| 0 | 10973 ins_pipe( pipe_slow ); |
| 10974 %} | |
| 10975 | |
| 10976 // Convert a double to an int. Java semantics require we do complex | |
| 10977 // manglations in the corner cases. So we set the rounding mode to | |
| 10978 // 'zero', store the darned double down as an int, and reset the | |
| 10979 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10980 // if we would overflow or converted a NAN; we check for this and | |
| 10981 // and go the slow path if needed. | |
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10982 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10983 predicate(UseSSE==0); |
| 10984 match(Set dst (ConvF2I src)); | |
| 10985 effect( KILL tmp, KILL cr ); | |
| 10986 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10987 "FLDCW trunc mode\n\t" | |
| 10988 "SUB ESP,4\n\t" | |
| 10989 "FISTp [ESP + #0]\n\t" | |
| 10990 "FLDCW std/24-bit mode\n\t" | |
| 10991 "POP EAX\n\t" | |
| 10992 "CMP EAX,0x80000000\n\t" | |
| 10993 "JNE,s fast\n\t" | |
| 10994 "FLD $src\n\t" | |
| 10995 "CALL d2i_wrapper\n" | |
| 10996 "fast:" %} | |
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10997 // DPR2I_encoding works for FPR2I |
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10998 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10999 ins_pipe( pipe_slow ); |
| 11000 %} | |
| 11001 | |
| 11002 // Convert a float in xmm to an int reg. | |
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11003 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 11004 predicate(UseSSE>=1); |
| 11005 match(Set dst (ConvF2I src)); | |
| 11006 effect( KILL tmp, KILL cr ); | |
| 11007 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11008 "CMP $dst,0x80000000\n\t" | |
| 11009 "JNE,s fast\n\t" | |
| 11010 "SUB ESP, 4\n\t" | |
| 11011 "MOVSS [ESP], $src\n\t" | |
| 11012 "FLD [ESP]\n\t" | |
| 11013 "ADD ESP, 4\n\t" | |
| 11014 "CALL d2i_wrapper\n" | |
| 11015 "fast:" %} | |
| 4759 | 11016 ins_encode %{ |
| 11017 Label fast; | |
| 11018 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 11019 __ cmpl($dst$$Register, 0x80000000); | |
| 11020 __ jccb(Assembler::notEqual, fast); | |
| 11021 __ subptr(rsp, 4); | |
| 11022 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11023 __ fld_s(Address(rsp, 0)); | |
| 11024 __ addptr(rsp, 4); | |
| 11025 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 11026 __ bind(fast); | |
| 11027 %} | |
| 0 | 11028 ins_pipe( pipe_slow ); |
| 11029 %} | |
| 11030 | |
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11031 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 11032 predicate(UseSSE==0); |
| 11033 match(Set dst (ConvF2L src)); | |
| 11034 effect( KILL cr ); | |
| 11035 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11036 "FLDCW trunc mode\n\t" | |
| 11037 "SUB ESP,8\n\t" | |
| 11038 "FISTp [ESP + #0]\n\t" | |
| 11039 "FLDCW std/24-bit mode\n\t" | |
| 11040 "POP EAX\n\t" | |
| 11041 "POP EDX\n\t" | |
| 11042 "CMP EDX,0x80000000\n\t" | |
| 11043 "JNE,s fast\n\t" | |
| 11044 "TEST EAX,EAX\n\t" | |
| 11045 "JNE,s fast\n\t" | |
| 11046 "FLD $src\n\t" | |
| 11047 "CALL d2l_wrapper\n" | |
| 11048 "fast:" %} | |
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11049 // DPR2L_encoding works for FPR2L |
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11050 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 11051 ins_pipe( pipe_slow ); |
| 11052 %} | |
| 11053 | |
| 11054 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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11055 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 11056 predicate (UseSSE>=1); |
| 11057 match(Set dst (ConvF2L src)); | |
| 11058 effect( KILL cr ); | |
| 11059 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11060 "MOVSS [ESP],$src\n\t" | |
| 11061 "FLD_S [ESP]\n\t" | |
| 11062 "FLDCW trunc mode\n\t" | |
| 11063 "FISTp [ESP + #0]\n\t" | |
| 11064 "FLDCW std/24-bit mode\n\t" | |
| 11065 "POP EAX\n\t" | |
| 11066 "POP EDX\n\t" | |
| 11067 "CMP EDX,0x80000000\n\t" | |
| 11068 "JNE,s fast\n\t" | |
| 11069 "TEST EAX,EAX\n\t" | |
| 11070 "JNE,s fast\n\t" | |
| 11071 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11072 "MOVSS [ESP],$src\n\t" | |
| 11073 "FLD_S [ESP]\n\t" | |
| 11074 "ADD ESP,4\n\t" | |
| 11075 "CALL d2l_wrapper\n" | |
| 11076 "fast:" %} | |
| 4759 | 11077 ins_encode %{ |
| 11078 Label fast; | |
| 11079 __ subptr(rsp, 8); | |
| 11080 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11081 __ fld_s(Address(rsp, 0)); | |
| 11082 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11083 __ fistp_d(Address(rsp, 0)); | |
| 11084 // Restore the rounding mode, mask the exception | |
| 11085 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11086 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11087 } else { | |
| 11088 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11089 } | |
| 11090 // Load the converted long, adjust CPU stack | |
| 11091 __ pop(rax); | |
| 11092 __ pop(rdx); | |
| 11093 __ cmpl(rdx, 0x80000000); | |
| 11094 __ jccb(Assembler::notEqual, fast); | |
| 11095 __ testl(rax, rax); | |
| 11096 __ jccb(Assembler::notEqual, fast); | |
| 11097 __ subptr(rsp, 4); | |
| 11098 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11099 __ fld_s(Address(rsp, 0)); | |
| 11100 __ addptr(rsp, 4); | |
| 11101 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11102 __ bind(fast); | |
| 11103 %} | |
| 0 | 11104 ins_pipe( pipe_slow ); |
| 11105 %} | |
| 11106 | |
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11107 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11108 predicate( UseSSE<=1 ); |
| 11109 match(Set dst (ConvI2D src)); | |
| 11110 format %{ "FILD $src\n\t" | |
| 11111 "FSTP $dst" %} | |
| 11112 opcode(0xDB, 0x0); /* DB /0 */ | |
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11113 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11114 ins_pipe( fpu_reg_mem ); |
| 11115 %} | |
| 11116 | |
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11117 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11118 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11119 match(Set dst (ConvI2D src)); |
| 11120 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11121 ins_encode %{ |
| 11122 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11123 %} | |
| 0 | 11124 ins_pipe( pipe_slow ); |
| 11125 %} | |
| 11126 | |
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11127 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11128 predicate( UseSSE>=2 ); |
| 11129 match(Set dst (ConvI2D (LoadI mem))); | |
| 11130 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11131 ins_encode %{ |
| 11132 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11133 %} | |
| 0 | 11134 ins_pipe( pipe_slow ); |
| 11135 %} | |
| 11136 | |
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11137 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11138 %{ |
| 11139 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11140 match(Set dst (ConvI2D src)); | |
| 11141 | |
| 11142 format %{ "MOVD $dst,$src\n\t" | |
| 11143 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11144 ins_encode %{ | |
| 304 | 11145 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11146 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11147 %} | |
| 11148 ins_pipe(pipe_slow); // XXX | |
| 11149 %} | |
| 11150 | |
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11151 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11152 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11153 match(Set dst (ConvI2D (LoadI mem))); | |
| 11154 format %{ "FILD $mem\n\t" | |
| 11155 "FSTP $dst" %} | |
| 11156 opcode(0xDB); /* DB /0 */ | |
| 11157 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11158 Pop_Reg_DPR(dst)); |
| 0 | 11159 ins_pipe( fpu_reg_mem ); |
| 11160 %} | |
| 11161 | |
| 11162 // Convert a byte to a float; no rounding step needed. | |
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11163 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11164 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11165 match(Set dst (ConvI2F src)); | |
| 11166 format %{ "FILD $src\n\t" | |
| 11167 "FSTP $dst" %} | |
| 11168 | |
| 11169 opcode(0xDB, 0x0); /* DB /0 */ | |
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11170 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11171 ins_pipe( fpu_reg_mem ); |
| 11172 %} | |
| 11173 | |
| 11174 // In 24-bit mode, force exponent rounding by storing back out | |
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11175 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11176 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11177 match(Set dst (ConvI2F src)); | |
| 11178 ins_cost(200); | |
| 11179 format %{ "FILD $src\n\t" | |
| 11180 "FSTP_S $dst" %} | |
| 11181 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11182 ins_encode( Push_Mem_I(src), | |
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11183 Pop_Mem_FPR(dst)); |
| 0 | 11184 ins_pipe( fpu_mem_mem ); |
| 11185 %} | |
| 11186 | |
| 11187 // In 24-bit mode, force exponent rounding by storing back out | |
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11188 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11189 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11190 match(Set dst (ConvI2F (LoadI mem))); | |
| 11191 ins_cost(200); | |
| 11192 format %{ "FILD $mem\n\t" | |
| 11193 "FSTP_S $dst" %} | |
| 11194 opcode(0xDB); /* DB /0 */ | |
| 11195 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11196 Pop_Mem_FPR(dst)); |
| 0 | 11197 ins_pipe( fpu_mem_mem ); |
| 11198 %} | |
| 11199 | |
| 11200 // This instruction does not round to 24-bits | |
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11201 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11202 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11203 match(Set dst (ConvI2F src)); | |
| 11204 format %{ "FILD $src\n\t" | |
| 11205 "FSTP $dst" %} | |
| 11206 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11207 ins_encode( Push_Mem_I(src), | |
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11208 Pop_Reg_FPR(dst)); |
| 0 | 11209 ins_pipe( fpu_reg_mem ); |
| 11210 %} | |
| 11211 | |
| 11212 // This instruction does not round to 24-bits | |
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11213 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11214 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11215 match(Set dst (ConvI2F (LoadI mem))); | |
| 11216 format %{ "FILD $mem\n\t" | |
| 11217 "FSTP $dst" %} | |
| 11218 opcode(0xDB); /* DB /0 */ | |
| 11219 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11220 Pop_Reg_FPR(dst)); |
| 0 | 11221 ins_pipe( fpu_reg_mem ); |
| 11222 %} | |
| 11223 | |
| 11224 // Convert an int to a float in xmm; no rounding step needed. | |
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11225 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11226 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11227 match(Set dst (ConvI2F src)); |
| 11228 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11229 ins_encode %{ |
| 11230 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11231 %} | |
| 0 | 11232 ins_pipe( pipe_slow ); |
| 11233 %} | |
| 11234 | |
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11235 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11236 %{ |
| 11237 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11238 match(Set dst (ConvI2F src)); | |
| 11239 | |
| 11240 format %{ "MOVD $dst,$src\n\t" | |
| 11241 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11242 ins_encode %{ | |
| 304 | 11243 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11244 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11245 %} | |
| 11246 ins_pipe(pipe_slow); // XXX | |
| 11247 %} | |
| 11248 | |
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11249 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11250 match(Set dst (ConvI2L src)); |
| 11251 effect(KILL cr); | |
| 624 | 11252 ins_cost(375); |
| 0 | 11253 format %{ "MOV $dst.lo,$src\n\t" |
| 11254 "MOV $dst.hi,$src\n\t" | |
| 11255 "SAR $dst.hi,31" %} | |
| 11256 ins_encode(convert_int_long(dst,src)); | |
| 11257 ins_pipe( ialu_reg_reg_long ); | |
| 11258 %} | |
| 11259 | |
| 11260 // Zero-extend convert int to long | |
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11261 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11262 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11263 effect( KILL flags ); | |
| 624 | 11264 ins_cost(250); |
| 0 | 11265 format %{ "MOV $dst.lo,$src\n\t" |
| 11266 "XOR $dst.hi,$dst.hi" %} | |
| 11267 opcode(0x33); // XOR | |
| 11268 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11269 ins_pipe( ialu_reg_reg_long ); | |
| 11270 %} | |
| 11271 | |
| 11272 // Zero-extend long | |
| 11273 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11274 match(Set dst (AndL src mask) ); | |
| 11275 effect( KILL flags ); | |
| 624 | 11276 ins_cost(250); |
| 0 | 11277 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11278 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11279 opcode(0x33); // XOR | |
| 11280 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11281 ins_pipe( ialu_reg_reg_long ); | |
| 11282 %} | |
| 11283 | |
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11284 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11285 predicate (UseSSE<=1); |
| 11286 match(Set dst (ConvL2D src)); | |
| 11287 effect( KILL cr ); | |
| 11288 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11289 "PUSH $src.lo\n\t" | |
| 11290 "FILD ST,[ESP + #0]\n\t" | |
| 11291 "ADD ESP,8\n\t" | |
| 11292 "FSTP_D $dst\t# D-round" %} | |
| 11293 opcode(0xDF, 0x5); /* DF /5 */ | |
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11294 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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11295 ins_pipe( pipe_slow ); |
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11296 %} |
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11297 |
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11298 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11299 predicate (UseSSE>=2); |
| 11300 match(Set dst (ConvL2D src)); | |
| 11301 effect( KILL cr ); | |
| 11302 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11303 "PUSH $src.lo\n\t" | |
| 11304 "FILD_D [ESP]\n\t" | |
| 11305 "FSTP_D [ESP]\n\t" | |
| 11306 "MOVSD $dst,[ESP]\n\t" | |
| 11307 "ADD ESP,8" %} | |
| 11308 opcode(0xDF, 0x5); /* DF /5 */ | |
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11309 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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11310 ins_pipe( pipe_slow ); |
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11311 %} |
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11312 |
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11313 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11314 predicate (UseSSE>=1); |
| 11315 match(Set dst (ConvL2F src)); | |
| 11316 effect( KILL cr ); | |
| 11317 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11318 "PUSH $src.lo\n\t" | |
| 11319 "FILD_D [ESP]\n\t" | |
| 11320 "FSTP_S [ESP]\n\t" | |
| 11321 "MOVSS $dst,[ESP]\n\t" | |
| 11322 "ADD ESP,8" %} | |
| 11323 opcode(0xDF, 0x5); /* DF /5 */ | |
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11324 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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11325 ins_pipe( pipe_slow ); |
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11326 %} |
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11327 |
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11328 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11329 match(Set dst (ConvL2F src)); |
| 11330 effect( KILL cr ); | |
| 11331 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11332 "PUSH $src.lo\n\t" | |
| 11333 "FILD ST,[ESP + #0]\n\t" | |
| 11334 "ADD ESP,8\n\t" | |
| 11335 "FSTP_S $dst\t# F-round" %} | |
| 11336 opcode(0xDF, 0x5); /* DF /5 */ | |
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11337 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11338 ins_pipe( pipe_slow ); |
| 11339 %} | |
| 11340 | |
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11341 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11342 match(Set dst (ConvL2I src)); |
| 11343 effect( DEF dst, USE src ); | |
| 11344 format %{ "MOV $dst,$src.lo" %} | |
| 11345 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11346 ins_pipe( ialu_reg_reg ); | |
| 11347 %} | |
| 11348 | |
| 11349 | |
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11350 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11351 match(Set dst (MoveF2I src)); |
| 11352 effect( DEF dst, USE src ); | |
| 11353 ins_cost(100); | |
| 11354 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11355 ins_encode %{ |
| 11356 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11357 %} | |
| 0 | 11358 ins_pipe( ialu_reg_mem ); |
| 11359 %} | |
| 11360 | |
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11361 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11362 predicate(UseSSE==0); |
| 11363 match(Set dst (MoveF2I src)); | |
| 11364 effect( DEF dst, USE src ); | |
| 11365 | |
| 11366 ins_cost(125); | |
| 11367 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
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11368 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11369 ins_pipe( fpu_mem_reg ); |
| 11370 %} | |
| 11371 | |
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11372 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11373 predicate(UseSSE>=1); |
| 11374 match(Set dst (MoveF2I src)); | |
| 11375 effect( DEF dst, USE src ); | |
| 11376 | |
| 11377 ins_cost(95); | |
| 11378 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11379 ins_encode %{ |
| 11380 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11381 %} | |
| 0 | 11382 ins_pipe( pipe_slow ); |
| 11383 %} | |
| 11384 | |
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11385 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11386 predicate(UseSSE>=2); |
| 11387 match(Set dst (MoveF2I src)); | |
| 11388 effect( DEF dst, USE src ); | |
| 11389 ins_cost(85); | |
| 11390 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11391 ins_encode %{ |
| 11392 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11393 %} | |
| 0 | 11394 ins_pipe( pipe_slow ); |
| 11395 %} | |
| 11396 | |
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11397 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11398 match(Set dst (MoveI2F src)); |
| 11399 effect( DEF dst, USE src ); | |
| 11400 | |
| 11401 ins_cost(100); | |
| 11402 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11403 ins_encode %{ |
| 11404 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11405 %} | |
| 0 | 11406 ins_pipe( ialu_mem_reg ); |
| 11407 %} | |
| 11408 | |
| 11409 | |
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11410 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11411 predicate(UseSSE==0); |
| 11412 match(Set dst (MoveI2F src)); | |
| 11413 effect(DEF dst, USE src); | |
| 11414 | |
| 11415 ins_cost(125); | |
| 11416 format %{ "FLD_S $src\n\t" | |
| 11417 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11418 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11419 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11420 Pop_Reg_FPR(dst) ); |
| 0 | 11421 ins_pipe( fpu_reg_mem ); |
| 11422 %} | |
| 11423 | |
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11424 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11425 predicate(UseSSE>=1); |
| 11426 match(Set dst (MoveI2F src)); | |
| 11427 effect( DEF dst, USE src ); | |
| 11428 | |
| 11429 ins_cost(95); | |
| 11430 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11431 ins_encode %{ |
| 11432 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11433 %} | |
| 0 | 11434 ins_pipe( pipe_slow ); |
| 11435 %} | |
| 11436 | |
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11437 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11438 predicate(UseSSE>=2); |
| 11439 match(Set dst (MoveI2F src)); | |
| 11440 effect( DEF dst, USE src ); | |
| 11441 | |
| 11442 ins_cost(85); | |
| 11443 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11444 ins_encode %{ |
| 11445 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11446 %} | |
| 0 | 11447 ins_pipe( pipe_slow ); |
| 11448 %} | |
| 11449 | |
| 11450 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11451 match(Set dst (MoveD2L src)); | |
| 11452 effect(DEF dst, USE src); | |
| 11453 | |
| 11454 ins_cost(250); | |
| 11455 format %{ "MOV $dst.lo,$src\n\t" | |
| 11456 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11457 opcode(0x8B, 0x8B); | |
| 11458 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11459 ins_pipe( ialu_mem_long_reg ); | |
| 11460 %} | |
| 11461 | |
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11462 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11463 predicate(UseSSE<=1); |
| 11464 match(Set dst (MoveD2L src)); | |
| 11465 effect(DEF dst, USE src); | |
| 11466 | |
| 11467 ins_cost(125); | |
| 11468 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
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11469 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11470 ins_pipe( fpu_mem_reg ); |
| 11471 %} | |
| 11472 | |
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11473 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11474 predicate(UseSSE>=2); |
| 11475 match(Set dst (MoveD2L src)); | |
| 11476 effect(DEF dst, USE src); | |
| 11477 ins_cost(95); | |
| 11478 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11479 ins_encode %{ |
| 11480 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11481 %} | |
| 0 | 11482 ins_pipe( pipe_slow ); |
| 11483 %} | |
| 11484 | |
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11485 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11486 predicate(UseSSE>=2); |
| 11487 match(Set dst (MoveD2L src)); | |
| 11488 effect(DEF dst, USE src, TEMP tmp); | |
| 11489 ins_cost(85); | |
| 11490 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11491 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11492 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11493 ins_encode %{ |
| 11494 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11495 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11496 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11497 %} | |
| 0 | 11498 ins_pipe( pipe_slow ); |
| 11499 %} | |
| 11500 | |
| 11501 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11502 match(Set dst (MoveL2D src)); | |
| 11503 effect(DEF dst, USE src); | |
| 11504 | |
| 11505 ins_cost(200); | |
| 11506 format %{ "MOV $dst,$src.lo\n\t" | |
| 11507 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11508 opcode(0x89, 0x89); | |
| 11509 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11510 ins_pipe( ialu_mem_long_reg ); | |
| 11511 %} | |
| 11512 | |
| 11513 | |
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11514 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11515 predicate(UseSSE<=1); |
| 11516 match(Set dst (MoveL2D src)); | |
| 11517 effect(DEF dst, USE src); | |
| 11518 ins_cost(125); | |
| 11519 | |
| 11520 format %{ "FLD_D $src\n\t" | |
| 11521 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11522 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11523 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11524 Pop_Reg_DPR(dst) ); |
| 0 | 11525 ins_pipe( fpu_reg_mem ); |
| 11526 %} | |
| 11527 | |
| 11528 | |
|
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|
11529 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11530 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11531 match(Set dst (MoveL2D src)); | |
| 11532 effect(DEF dst, USE src); | |
| 11533 | |
| 11534 ins_cost(95); | |
| 11535 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11536 ins_encode %{ |
| 11537 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11538 %} | |
| 0 | 11539 ins_pipe( pipe_slow ); |
| 11540 %} | |
| 11541 | |
|
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11542 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11543 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11544 match(Set dst (MoveL2D src)); | |
| 11545 effect(DEF dst, USE src); | |
| 11546 | |
| 11547 ins_cost(95); | |
| 11548 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11549 ins_encode %{ |
| 11550 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11551 %} | |
| 0 | 11552 ins_pipe( pipe_slow ); |
| 11553 %} | |
| 11554 | |
|
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11555 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11556 predicate(UseSSE>=2); |
| 11557 match(Set dst (MoveL2D src)); | |
| 11558 effect(TEMP dst, USE src, TEMP tmp); | |
| 11559 ins_cost(85); | |
| 11560 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11561 "MOVD $tmp,$src.hi\n\t" | |
| 11562 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11563 ins_encode %{ |
| 11564 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11565 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11566 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11567 %} | |
| 0 | 11568 ins_pipe( pipe_slow ); |
| 11569 %} | |
| 11570 | |
| 11571 | |
| 11572 // ======================================================================= | |
| 11573 // fast clearing of an array | |
| 11574 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 11575 match(Set dummy (ClearArray cnt base)); | |
| 11576 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11577 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 11578 "XOR EAX,EAX\n\t" | |
| 11579 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 11580 opcode(0,0x4); | |
| 11581 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 11582 OpcRegReg(0x33,EAX,EAX), | |
| 11583 Opcode(0xF3), Opcode(0xAB) ); | |
| 11584 ins_pipe( pipe_slow ); | |
| 11585 %} | |
| 11586 | |
| 2262 | 11587 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
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11588 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
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11589 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11590 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11591 | |
| 11592 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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11593 ins_encode %{ |
|
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11594 __ string_compare($str1$$Register, $str2$$Register, |
|
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11595 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11596 $tmp1$$XMMRegister); |
|
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11597 %} |
| 681 | 11598 ins_pipe( pipe_slow ); |
| 11599 %} | |
| 11600 | |
| 11601 // fast string equals | |
|
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11602 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
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11603 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
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11604 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
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11605 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
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|
11606 |
|
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11607 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
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11608 ins_encode %{ |
|
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|
11609 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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11610 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
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11611 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
11612 %} |
|
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|
11613 ins_pipe( pipe_slow ); |
|
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|
11614 %} |
|
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|
11615 |
|
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|
11616 // fast search of substring with known size. |
|
41d4973cf100
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11617 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
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11618 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
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|
11619 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
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|
11620 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
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|
11621 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
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|
11622 |
|
41d4973cf100
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|
11623 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
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|
11624 ins_encode %{ |
|
41d4973cf100
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|
11625 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
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|
11626 if (icnt2 >= 8) { |
|
41d4973cf100
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|
11627 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
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|
11628 // which don't need to be loaded through stack. |
|
41d4973cf100
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|
11629 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
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|
11630 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
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|
11631 icnt2, $result$$Register, |
|
41d4973cf100
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|
11632 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
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|
11633 } else { |
|
41d4973cf100
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|
11634 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
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|
11635 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
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|
11636 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
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|
11637 icnt2, $result$$Register, |
|
41d4973cf100
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|
11638 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
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|
11639 } |
|
41d4973cf100
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changeset
|
11640 %} |
|
41d4973cf100
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|
11641 ins_pipe( pipe_slow ); |
|
41d4973cf100
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|
11642 %} |
|
41d4973cf100
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|
11643 |
|
986
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|
11644 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
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|
11645 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11646 predicate(UseSSE42Intrinsics); |
|
986
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|
11647 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
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|
11648 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
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|
11649 |
|
41d4973cf100
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|
11650 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
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|
11651 ins_encode %{ |
|
62001a362ce9
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|
11652 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
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|
11653 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
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|
11654 (-1), $result$$Register, |
|
41d4973cf100
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|
11655 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11656 %} |
| 0 | 11657 ins_pipe( pipe_slow ); |
| 11658 %} | |
| 11659 | |
|
169
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|
11660 // fast array equals |
|
986
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|
11661 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
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11662 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
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|
11663 %{ |
|
169
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|
11664 match(Set result (AryEq ary1 ary2)); |
| 681 | 11665 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
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|
11666 //ins_cost(300); |
|
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|
11667 |
|
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|
11668 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
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|
11669 ins_encode %{ |
|
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|
11670 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
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|
11671 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
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|
11672 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
11673 %} |
|
169
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|
11674 ins_pipe( pipe_slow ); |
|
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|
11675 %} |
|
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|
11676 |
| 0 | 11677 //----------Control Flow Instructions------------------------------------------ |
| 11678 // Signed compare Instructions | |
|
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|
11679 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11680 match(Set cr (CmpI op1 op2)); |
| 11681 effect( DEF cr, USE op1, USE op2 ); | |
| 11682 format %{ "CMP $op1,$op2" %} | |
| 11683 opcode(0x3B); /* Opcode 3B /r */ | |
| 11684 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11685 ins_pipe( ialu_cr_reg_reg ); | |
| 11686 %} | |
| 11687 | |
|
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|
11688 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11689 match(Set cr (CmpI op1 op2)); |
| 11690 effect( DEF cr, USE op1 ); | |
| 11691 format %{ "CMP $op1,$op2" %} | |
| 11692 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11693 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11694 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11695 ins_pipe( ialu_cr_reg_imm ); | |
| 11696 %} | |
| 11697 | |
| 11698 // Cisc-spilled version of cmpI_eReg | |
|
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|
11699 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11700 match(Set cr (CmpI op1 (LoadI op2))); |
| 11701 | |
| 11702 format %{ "CMP $op1,$op2" %} | |
| 11703 ins_cost(500); | |
| 11704 opcode(0x3B); /* Opcode 3B /r */ | |
| 11705 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11706 ins_pipe( ialu_cr_reg_mem ); | |
| 11707 %} | |
| 11708 | |
|
6179
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|
11709 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11710 match(Set cr (CmpI src zero)); |
| 11711 effect( DEF cr, USE src ); | |
| 11712 | |
| 11713 format %{ "TEST $src,$src" %} | |
| 11714 opcode(0x85); | |
| 11715 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11716 ins_pipe( ialu_cr_reg_imm ); | |
| 11717 %} | |
| 11718 | |
|
6179
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changeset
|
11719 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11720 match(Set cr (CmpI (AndI src con) zero)); |
| 11721 | |
| 11722 format %{ "TEST $src,$con" %} | |
| 11723 opcode(0xF7,0x00); | |
| 11724 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11725 ins_pipe( ialu_cr_reg_imm ); | |
| 11726 %} | |
| 11727 | |
|
6179
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|
11728 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11729 match(Set cr (CmpI (AndI src mem) zero)); |
| 11730 | |
| 11731 format %{ "TEST $src,$mem" %} | |
| 11732 opcode(0x85); | |
| 11733 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11734 ins_pipe( ialu_cr_reg_mem ); | |
| 11735 %} | |
| 11736 | |
| 11737 // Unsigned compare Instructions; really, same as signed except they | |
| 11738 // produce an eFlagsRegU instead of eFlagsReg. | |
|
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11739 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11740 match(Set cr (CmpU op1 op2)); |
| 11741 | |
| 11742 format %{ "CMPu $op1,$op2" %} | |
| 11743 opcode(0x3B); /* Opcode 3B /r */ | |
| 11744 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11745 ins_pipe( ialu_cr_reg_reg ); | |
| 11746 %} | |
| 11747 | |
|
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11748 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11749 match(Set cr (CmpU op1 op2)); |
| 11750 | |
| 11751 format %{ "CMPu $op1,$op2" %} | |
| 11752 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11753 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11754 ins_pipe( ialu_cr_reg_imm ); | |
| 11755 %} | |
| 11756 | |
| 11757 // // Cisc-spilled version of cmpU_eReg | |
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11758 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11759 match(Set cr (CmpU op1 (LoadI op2))); |
| 11760 | |
| 11761 format %{ "CMPu $op1,$op2" %} | |
| 11762 ins_cost(500); | |
| 11763 opcode(0x3B); /* Opcode 3B /r */ | |
| 11764 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11765 ins_pipe( ialu_cr_reg_mem ); | |
| 11766 %} | |
| 11767 | |
| 11768 // // Cisc-spilled version of cmpU_eReg | |
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11769 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11770 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11771 // | |
| 11772 // format %{ "CMPu $op1,$op2" %} | |
| 11773 // ins_cost(500); | |
| 11774 // opcode(0x39); /* Opcode 39 /r */ | |
| 11775 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11776 //%} | |
| 11777 | |
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11778 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11779 match(Set cr (CmpU src zero)); |
| 11780 | |
| 11781 format %{ "TESTu $src,$src" %} | |
| 11782 opcode(0x85); | |
| 11783 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11784 ins_pipe( ialu_cr_reg_imm ); | |
| 11785 %} | |
| 11786 | |
| 11787 // Unsigned pointer compare Instructions | |
| 11788 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11789 match(Set cr (CmpP op1 op2)); | |
| 11790 | |
| 11791 format %{ "CMPu $op1,$op2" %} | |
| 11792 opcode(0x3B); /* Opcode 3B /r */ | |
| 11793 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11794 ins_pipe( ialu_cr_reg_reg ); | |
| 11795 %} | |
| 11796 | |
| 11797 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11798 match(Set cr (CmpP op1 op2)); | |
| 11799 | |
| 11800 format %{ "CMPu $op1,$op2" %} | |
| 11801 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11802 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11803 ins_pipe( ialu_cr_reg_imm ); | |
| 11804 %} | |
| 11805 | |
| 11806 // // Cisc-spilled version of cmpP_eReg | |
| 11807 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11808 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11809 | |
| 11810 format %{ "CMPu $op1,$op2" %} | |
| 11811 ins_cost(500); | |
| 11812 opcode(0x3B); /* Opcode 3B /r */ | |
| 11813 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11814 ins_pipe( ialu_cr_reg_mem ); | |
| 11815 %} | |
| 11816 | |
| 11817 // // Cisc-spilled version of cmpP_eReg | |
| 11818 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11819 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11820 // | |
| 11821 // format %{ "CMPu $op1,$op2" %} | |
| 11822 // ins_cost(500); | |
| 11823 // opcode(0x39); /* Opcode 39 /r */ | |
| 11824 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11825 //%} | |
| 11826 | |
| 11827 // Compare raw pointer (used in out-of-heap check). | |
| 11828 // Only works because non-oop pointers must be raw pointers | |
| 11829 // and raw pointers have no anti-dependencies. | |
| 11830 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
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11831 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11832 match(Set cr (CmpP op1 (LoadP op2))); |
| 11833 | |
| 11834 format %{ "CMPu $op1,$op2" %} | |
| 11835 opcode(0x3B); /* Opcode 3B /r */ | |
| 11836 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11837 ins_pipe( ialu_cr_reg_mem ); | |
| 11838 %} | |
| 11839 | |
| 11840 // | |
| 11841 // This will generate a signed flags result. This should be ok | |
| 11842 // since any compare to a zero should be eq/neq. | |
| 11843 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11844 match(Set cr (CmpP src zero)); | |
| 11845 | |
| 11846 format %{ "TEST $src,$src" %} | |
| 11847 opcode(0x85); | |
| 11848 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11849 ins_pipe( ialu_cr_reg_imm ); | |
| 11850 %} | |
| 11851 | |
| 11852 // Cisc-spilled version of testP_reg | |
| 11853 // This will generate a signed flags result. This should be ok | |
| 11854 // since any compare to a zero should be eq/neq. | |
| 11855 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11856 match(Set cr (CmpP (LoadP op) zero)); | |
| 11857 | |
| 11858 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11859 ins_cost(500); | |
| 11860 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11861 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11862 ins_pipe( ialu_cr_reg_imm ); | |
| 11863 %} | |
| 11864 | |
| 11865 // Yanked all unsigned pointer compare operations. | |
| 11866 // Pointer compares are done with CmpP which is already unsigned. | |
| 11867 | |
| 11868 //----------Max and Min-------------------------------------------------------- | |
| 11869 // Min Instructions | |
| 11870 //// | |
| 11871 // *** Min and Max using the conditional move are slower than the | |
| 11872 // *** branch version on a Pentium III. | |
| 11873 // // Conditional move for min | |
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11874 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11875 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11876 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11877 // opcode(0x4C,0x0F); | |
| 11878 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11879 // ins_pipe( pipe_cmov_reg ); | |
| 11880 //%} | |
| 11881 // | |
| 11882 //// Min Register with Register (P6 version) | |
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11883 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11884 // predicate(VM_Version::supports_cmov() ); |
| 11885 // match(Set op2 (MinI op1 op2)); | |
| 11886 // ins_cost(200); | |
| 11887 // expand %{ | |
| 11888 // eFlagsReg cr; | |
| 11889 // compI_eReg(cr,op1,op2); | |
| 11890 // cmovI_reg_lt(op2,op1,cr); | |
| 11891 // %} | |
| 11892 //%} | |
| 11893 | |
| 11894 // Min Register with Register (generic version) | |
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11895 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11896 match(Set dst (MinI dst src)); |
| 11897 effect(KILL flags); | |
| 11898 ins_cost(300); | |
| 11899 | |
| 11900 format %{ "MIN $dst,$src" %} | |
| 11901 opcode(0xCC); | |
| 11902 ins_encode( min_enc(dst,src) ); | |
| 11903 ins_pipe( pipe_slow ); | |
| 11904 %} | |
| 11905 | |
| 11906 // Max Register with Register | |
| 11907 // *** Min and Max using the conditional move are slower than the | |
| 11908 // *** branch version on a Pentium III. | |
| 11909 // // Conditional move for max | |
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11910 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11911 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11912 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11913 // opcode(0x4F,0x0F); | |
| 11914 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11915 // ins_pipe( pipe_cmov_reg ); | |
| 11916 //%} | |
| 11917 // | |
| 11918 // // Max Register with Register (P6 version) | |
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11919 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11920 // predicate(VM_Version::supports_cmov() ); |
| 11921 // match(Set op2 (MaxI op1 op2)); | |
| 11922 // ins_cost(200); | |
| 11923 // expand %{ | |
| 11924 // eFlagsReg cr; | |
| 11925 // compI_eReg(cr,op1,op2); | |
| 11926 // cmovI_reg_gt(op2,op1,cr); | |
| 11927 // %} | |
| 11928 //%} | |
| 11929 | |
| 11930 // Max Register with Register (generic version) | |
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11931 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11932 match(Set dst (MaxI dst src)); |
| 11933 effect(KILL flags); | |
| 11934 ins_cost(300); | |
| 11935 | |
| 11936 format %{ "MAX $dst,$src" %} | |
| 11937 opcode(0xCC); | |
| 11938 ins_encode( max_enc(dst,src) ); | |
| 11939 ins_pipe( pipe_slow ); | |
| 11940 %} | |
| 11941 | |
| 11942 // ============================================================================ | |
| 3345 | 11943 // Counted Loop limit node which represents exact final iterator value. |
| 11944 // Note: the resulting value should fit into integer range since | |
| 11945 // counted loops have limit check on overflow. | |
| 11946 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11947 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11948 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11949 ins_cost(300); | |
| 11950 | |
| 11951 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11952 ins_encode %{ | |
| 11953 int strd = (int)$stride$$constant; | |
| 11954 assert(strd != 1 && strd != -1, "sanity"); | |
| 11955 int m1 = (strd > 0) ? 1 : -1; | |
| 11956 // Convert limit to long (EAX:EDX) | |
| 11957 __ cdql(); | |
| 11958 // Convert init to long (init:tmp) | |
| 11959 __ movl($tmp$$Register, $init$$Register); | |
| 11960 __ sarl($tmp$$Register, 31); | |
| 11961 // $limit - $init | |
| 11962 __ subl($limit$$Register, $init$$Register); | |
| 11963 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11964 // + ($stride - 1) | |
| 11965 if (strd > 0) { | |
| 11966 __ addl($limit$$Register, (strd - 1)); | |
| 11967 __ adcl($limit_hi$$Register, 0); | |
| 11968 __ movl($tmp$$Register, strd); | |
| 11969 } else { | |
| 11970 __ addl($limit$$Register, (strd + 1)); | |
| 11971 __ adcl($limit_hi$$Register, -1); | |
| 11972 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11973 __ movl($tmp$$Register, -strd); | |
| 11974 } | |
| 11975 // signed devision: (EAX:EDX) / pos_stride | |
| 11976 __ idivl($tmp$$Register); | |
| 11977 if (strd < 0) { | |
| 11978 // restore sign | |
| 11979 __ negl($tmp$$Register); | |
| 11980 } | |
| 11981 // (EAX) * stride | |
| 11982 __ mull($tmp$$Register); | |
| 11983 // + init (ignore upper bits) | |
| 11984 __ addl($limit$$Register, $init$$Register); | |
| 11985 %} | |
| 11986 ins_pipe( pipe_slow ); | |
| 11987 %} | |
| 11988 | |
| 11989 // ============================================================================ | |
| 0 | 11990 // Branch Instructions |
| 11991 // Jump Table | |
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11992 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11993 match(Jump switch_val); |
| 11994 ins_cost(350); | |
| 2008 | 11995 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11996 ins_encode %{ | |
| 0 | 11997 // Jump to Address(table_base + switch_reg) |
| 11998 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11999 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 12000 %} |
| 12001 ins_pipe(pipe_jmp); | |
| 12002 %} | |
| 12003 | |
| 12004 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12005 instruct jmpDir(label labl) %{ | |
| 12006 match(Goto); | |
| 12007 effect(USE labl); | |
| 12008 | |
| 12009 ins_cost(300); | |
| 12010 format %{ "JMP $labl" %} | |
| 12011 size(5); | |
| 3851 | 12012 ins_encode %{ |
| 12013 Label* L = $labl$$label; | |
| 12014 __ jmp(*L, false); // Always long jump | |
| 12015 %} | |
| 0 | 12016 ins_pipe( pipe_jmp ); |
| 12017 %} | |
| 12018 | |
| 12019 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12020 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12021 match(If cop cr); | |
| 12022 effect(USE labl); | |
| 12023 | |
| 12024 ins_cost(300); | |
| 12025 format %{ "J$cop $labl" %} | |
| 12026 size(6); | |
| 3851 | 12027 ins_encode %{ |
| 12028 Label* L = $labl$$label; | |
| 12029 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12030 %} | |
| 0 | 12031 ins_pipe( pipe_jcc ); |
| 12032 %} | |
| 12033 | |
| 12034 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12035 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12036 match(CountedLoopEnd cop cr); | |
| 12037 effect(USE labl); | |
| 12038 | |
| 12039 ins_cost(300); | |
| 12040 format %{ "J$cop $labl\t# Loop end" %} | |
| 12041 size(6); | |
| 3851 | 12042 ins_encode %{ |
| 12043 Label* L = $labl$$label; | |
| 12044 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12045 %} | |
| 0 | 12046 ins_pipe( pipe_jcc ); |
| 12047 %} | |
| 12048 | |
| 12049 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12050 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12051 match(CountedLoopEnd cop cmp); | |
| 12052 effect(USE labl); | |
| 12053 | |
| 12054 ins_cost(300); | |
| 12055 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12056 size(6); | |
| 3851 | 12057 ins_encode %{ |
| 12058 Label* L = $labl$$label; | |
| 12059 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12060 %} | |
| 0 | 12061 ins_pipe( pipe_jcc ); |
| 12062 %} | |
| 12063 | |
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12064 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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12065 match(CountedLoopEnd cop cmp); |
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12066 effect(USE labl); |
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12067 |
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12068 ins_cost(200); |
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12069 format %{ "J$cop,u $labl\t# Loop end" %} |
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12070 size(6); |
| 3851 | 12071 ins_encode %{ |
| 12072 Label* L = $labl$$label; | |
| 12073 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12074 %} | |
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12075 ins_pipe( pipe_jcc ); |
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12076 %} |
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12077 |
| 0 | 12078 // Jump Direct Conditional - using unsigned comparison |
| 12079 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12080 match(If cop cmp); | |
| 12081 effect(USE labl); | |
| 12082 | |
| 12083 ins_cost(300); | |
| 12084 format %{ "J$cop,u $labl" %} | |
| 12085 size(6); | |
| 3851 | 12086 ins_encode %{ |
| 12087 Label* L = $labl$$label; | |
| 12088 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12089 %} | |
|
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12090 ins_pipe(pipe_jcc); |
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12091 %} |
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12092 |
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12093 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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12094 match(If cop cmp); |
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12095 effect(USE labl); |
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12096 |
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12097 ins_cost(200); |
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12098 format %{ "J$cop,u $labl" %} |
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12099 size(6); |
| 3851 | 12100 ins_encode %{ |
| 12101 Label* L = $labl$$label; | |
| 12102 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12103 %} | |
|
415
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|
12104 ins_pipe(pipe_jcc); |
|
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|
12105 %} |
|
4d9884b01ba6
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changeset
|
12106 |
|
4d9884b01ba6
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|
12107 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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|
12108 match(If cop cmp); |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
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|
12109 effect(USE labl); |
|
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diff
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|
12110 |
|
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diff
changeset
|
12111 ins_cost(200); |
|
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403
diff
changeset
|
12112 format %{ $$template |
|
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diff
changeset
|
12113 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12114 $$emit$$"JP,u $labl\n\t" |
|
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|
12115 $$emit$$"J$cop,u $labl" |
|
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changeset
|
12116 } else { |
|
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changeset
|
12117 $$emit$$"JP,u done\n\t" |
|
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|
12118 $$emit$$"J$cop,u $labl\n\t" |
|
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|
12119 $$emit$$"done:" |
|
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changeset
|
12120 } |
|
4d9884b01ba6
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never
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changeset
|
12121 %} |
|
4d9884b01ba6
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diff
changeset
|
12122 ins_encode %{ |
|
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changeset
|
12123 Label* l = $labl$$label; |
|
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|
12124 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12125 __ jcc(Assembler::parity, *l, false); |
| 12126 __ jcc(Assembler::notEqual, *l, false); | |
|
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|
12127 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12128 Label done; |
| 12129 __ jccb(Assembler::parity, done); | |
| 12130 __ jcc(Assembler::equal, *l, false); | |
| 12131 __ bind(done); | |
|
415
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|
12132 } else { |
|
4d9884b01ba6
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changeset
|
12133 ShouldNotReachHere(); |
|
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|
12134 } |
|
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|
12135 %} |
|
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|
12136 ins_pipe(pipe_jcc); |
| 0 | 12137 %} |
| 12138 | |
| 12139 // ============================================================================ | |
| 12140 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12141 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12142 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12143 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12144 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12145 match(Set result (PartialSubtypeCheck sub super)); | |
| 12146 effect( KILL rcx, KILL cr ); | |
| 12147 | |
| 12148 ins_cost(1100); // slightly larger than the next version | |
|
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
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changeset
|
12149 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
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8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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|
12150 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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|
12151 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12152 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12153 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12154 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12155 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12156 "miss:\t" %} | |
| 12157 | |
| 12158 opcode(0x1); // Force a XOR of EDI | |
| 12159 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12160 ins_pipe( pipe_slow ); | |
| 12161 %} | |
| 12162 | |
| 12163 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12164 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12165 effect( KILL rcx, KILL result ); | |
| 12166 | |
| 12167 ins_cost(1000); | |
|
644
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jrose
parents:
643
diff
changeset
|
12168 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12169 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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changeset
|
12170 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12171 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12172 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12173 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12174 "miss:\t" %} | |
| 12175 | |
| 12176 opcode(0x0); // No need to XOR EDI | |
| 12177 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12178 ins_pipe( pipe_slow ); | |
| 12179 %} | |
| 12180 | |
| 12181 // ============================================================================ | |
| 12182 // Branch Instructions -- short offset versions | |
| 12183 // | |
| 12184 // These instructions are used to replace jumps of a long offset (the default | |
| 12185 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12186 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12187 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12188 // method in the MachNode which can be used to do in-place replacement of the | |
| 12189 // long variant with the shorter variant. The compiler will determine if a | |
| 12190 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12191 // specific code section of the file. | |
| 12192 | |
| 12193 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12194 instruct jmpDir_short(label labl) %{ | |
| 12195 match(Goto); | |
| 12196 effect(USE labl); | |
| 12197 | |
| 12198 ins_cost(300); | |
| 12199 format %{ "JMP,s $labl" %} | |
| 12200 size(2); | |
| 3851 | 12201 ins_encode %{ |
| 12202 Label* L = $labl$$label; | |
| 12203 __ jmpb(*L); | |
| 12204 %} | |
| 0 | 12205 ins_pipe( pipe_jmp ); |
| 12206 ins_short_branch(1); | |
| 12207 %} | |
| 12208 | |
| 12209 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12210 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12211 match(If cop cr); | |
| 12212 effect(USE labl); | |
| 12213 | |
| 12214 ins_cost(300); | |
| 12215 format %{ "J$cop,s $labl" %} | |
| 12216 size(2); | |
| 3851 | 12217 ins_encode %{ |
| 12218 Label* L = $labl$$label; | |
| 12219 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12220 %} | |
| 0 | 12221 ins_pipe( pipe_jcc ); |
| 12222 ins_short_branch(1); | |
| 12223 %} | |
| 12224 | |
| 12225 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12226 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12227 match(CountedLoopEnd cop cr); | |
| 12228 effect(USE labl); | |
| 12229 | |
| 12230 ins_cost(300); | |
|
415
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diff
changeset
|
12231 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12232 size(2); |
| 3851 | 12233 ins_encode %{ |
| 12234 Label* L = $labl$$label; | |
| 12235 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12236 %} | |
| 0 | 12237 ins_pipe( pipe_jcc ); |
| 12238 ins_short_branch(1); | |
| 12239 %} | |
| 12240 | |
| 12241 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12242 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12243 match(CountedLoopEnd cop cmp); | |
| 12244 effect(USE labl); | |
| 12245 | |
| 12246 ins_cost(300); | |
|
415
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diff
changeset
|
12247 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12248 size(2); |
| 3851 | 12249 ins_encode %{ |
| 12250 Label* L = $labl$$label; | |
| 12251 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12252 %} | |
|
415
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diff
changeset
|
12253 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12254 ins_short_branch(1); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12255 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12256 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12257 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12258 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12259 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12260 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12261 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12262 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12263 size(2); |
| 3851 | 12264 ins_encode %{ |
| 12265 Label* L = $labl$$label; | |
| 12266 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12267 %} | |
| 0 | 12268 ins_pipe( pipe_jcc ); |
| 12269 ins_short_branch(1); | |
| 12270 %} | |
| 12271 | |
| 12272 // Jump Direct Conditional - using unsigned comparison | |
| 12273 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12274 match(If cop cmp); | |
| 12275 effect(USE labl); | |
| 12276 | |
| 12277 ins_cost(300); | |
| 12278 format %{ "J$cop,us $labl" %} | |
| 12279 size(2); | |
| 3851 | 12280 ins_encode %{ |
| 12281 Label* L = $labl$$label; | |
| 12282 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12283 %} | |
| 0 | 12284 ins_pipe( pipe_jcc ); |
| 12285 ins_short_branch(1); | |
| 12286 %} | |
| 12287 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12288 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12289 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12290 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12291 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12292 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12293 format %{ "J$cop,us $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12294 size(2); |
| 3851 | 12295 ins_encode %{ |
| 12296 Label* L = $labl$$label; | |
| 12297 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12298 %} | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
12299 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12300 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12301 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12302 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12303 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12304 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12305 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12306 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12307 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12308 format %{ $$template |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12309 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12310 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12311 $$emit$$"J$cop,u,s $labl" |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12312 } else { |
|
4d9884b01ba6
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never
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403
diff
changeset
|
12313 $$emit$$"JP,u,s done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12314 $$emit$$"J$cop,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12315 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12316 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12317 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12318 size(4); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12319 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12320 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12321 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12322 __ jccb(Assembler::parity, *l); |
| 12323 __ jccb(Assembler::notEqual, *l); | |
|
415
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parents:
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diff
changeset
|
12324 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12325 Label done; |
| 12326 __ jccb(Assembler::parity, done); | |
| 12327 __ jccb(Assembler::equal, *l); | |
| 12328 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12329 } else { |
| 3851 | 12330 ShouldNotReachHere(); |
| 12331 } | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12332 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12333 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
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|
12334 ins_short_branch(1); |
|
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|
12335 %} |
|
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|
12336 |
| 0 | 12337 // ============================================================================ |
| 12338 // Long Compare | |
| 12339 // | |
| 12340 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12341 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12342 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12343 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12344 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12345 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12346 // NE test is negated from that. | |
| 12347 | |
| 12348 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12349 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12350 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12351 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12352 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12353 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12354 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12355 // both forms beat the trinary form of long-compare and both are very useful | |
| 12356 // on Intel which has so few registers. | |
| 12357 | |
| 12358 // Manifest a CmpL result in an integer register. Very painful. | |
| 12359 // This is the test to avoid. | |
| 12360 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12361 match(Set dst (CmpL3 src1 src2)); | |
| 12362 effect( KILL flags ); | |
| 12363 ins_cost(1000); | |
| 12364 format %{ "XOR $dst,$dst\n\t" | |
| 12365 "CMP $src1.hi,$src2.hi\n\t" | |
| 12366 "JLT,s m_one\n\t" | |
| 12367 "JGT,s p_one\n\t" | |
| 12368 "CMP $src1.lo,$src2.lo\n\t" | |
| 12369 "JB,s m_one\n\t" | |
| 12370 "JEQ,s done\n" | |
| 12371 "p_one:\tINC $dst\n\t" | |
| 12372 "JMP,s done\n" | |
| 12373 "m_one:\tDEC $dst\n" | |
| 12374 "done:" %} | |
| 12375 ins_encode %{ | |
| 12376 Label p_one, m_one, done; | |
| 304 | 12377 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12378 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12379 __ jccb(Assembler::less, m_one); | |
| 12380 __ jccb(Assembler::greater, p_one); | |
| 12381 __ cmpl($src1$$Register, $src2$$Register); | |
| 12382 __ jccb(Assembler::below, m_one); | |
| 12383 __ jccb(Assembler::equal, done); | |
| 12384 __ bind(p_one); | |
| 304 | 12385 __ incrementl($dst$$Register); |
| 0 | 12386 __ jmpb(done); |
| 12387 __ bind(m_one); | |
| 304 | 12388 __ decrementl($dst$$Register); |
| 0 | 12389 __ bind(done); |
| 12390 %} | |
| 12391 ins_pipe( pipe_slow ); | |
| 12392 %} | |
| 12393 | |
| 12394 //====== | |
| 12395 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12396 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12397 // NOT GOOD FOR EQ/NE tests. | |
| 12398 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12399 match( Set flags (CmpL src zero )); | |
| 12400 ins_cost(100); | |
| 12401 format %{ "TEST $src.hi,$src.hi" %} | |
| 12402 opcode(0x85); | |
| 12403 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12404 ins_pipe( ialu_cr_reg_reg ); | |
| 12405 %} | |
| 12406 | |
| 12407 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12408 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12409 // NOT GOOD FOR EQ/NE tests. | |
|
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12410 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12411 match( Set flags (CmpL src1 src2 )); |
| 12412 effect( TEMP tmp ); | |
| 12413 ins_cost(300); | |
| 12414 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12415 "MOV $tmp,$src1.hi\n\t" | |
| 12416 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12417 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12418 ins_pipe( ialu_cr_reg_reg ); | |
| 12419 %} | |
| 12420 | |
| 12421 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12422 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12423 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12424 match(If cmp flags); | |
| 12425 effect(USE labl); | |
| 12426 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12427 expand %{ | |
| 12428 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12429 %} | |
| 12430 %} | |
| 12431 | |
| 12432 // Compare 2 longs and CMOVE longs. | |
| 12433 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12434 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12435 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12436 ins_cost(400); | |
| 12437 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12438 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12439 opcode(0x0F,0x40); | |
| 12440 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12441 ins_pipe( pipe_cmov_reg_long ); | |
| 12442 %} | |
| 12443 | |
| 12444 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12445 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12446 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12447 ins_cost(500); | |
| 12448 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12449 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12450 opcode(0x0F,0x40); | |
| 12451 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12452 ins_pipe( pipe_cmov_reg_long ); | |
| 12453 %} | |
| 12454 | |
| 12455 // Compare 2 longs and CMOVE ints. | |
|
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12456 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12457 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12458 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12459 ins_cost(200); | |
| 12460 format %{ "CMOV$cmp $dst,$src" %} | |
| 12461 opcode(0x0F,0x40); | |
| 12462 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12463 ins_pipe( pipe_cmov_reg ); | |
| 12464 %} | |
| 12465 | |
|
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12466 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12467 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12468 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12469 ins_cost(250); | |
| 12470 format %{ "CMOV$cmp $dst,$src" %} | |
| 12471 opcode(0x0F,0x40); | |
| 12472 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12473 ins_pipe( pipe_cmov_mem ); | |
| 12474 %} | |
| 12475 | |
| 12476 // Compare 2 longs and CMOVE ints. | |
| 12477 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12478 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12479 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12480 ins_cost(200); | |
| 12481 format %{ "CMOV$cmp $dst,$src" %} | |
| 12482 opcode(0x0F,0x40); | |
| 12483 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12484 ins_pipe( pipe_cmov_reg ); | |
| 12485 %} | |
| 12486 | |
| 12487 // Compare 2 longs and CMOVE doubles | |
|
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12488 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12489 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12490 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12491 ins_cost(200); | |
| 12492 expand %{ | |
|
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|
12493 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12494 %} |
| 12495 %} | |
| 12496 | |
| 12497 // Compare 2 longs and CMOVE doubles | |
|
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12498 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12499 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12500 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12501 ins_cost(200); | |
| 12502 expand %{ | |
|
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|
12503 fcmovD_regS(cmp,flags,dst,src); |
|
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|
12504 %} |
|
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|
12505 %} |
|
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|
12506 |
|
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12507 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
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12508 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
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12509 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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|
12510 ins_cost(200); |
|
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|
12511 expand %{ |
|
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|
12512 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12513 %} |
| 12514 %} | |
| 12515 | |
| 12516 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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12517 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12518 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12519 ins_cost(200); | |
| 12520 expand %{ | |
| 12521 fcmovF_regS(cmp,flags,dst,src); | |
| 12522 %} | |
| 12523 %} | |
| 12524 | |
| 12525 //====== | |
| 12526 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
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12527 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12528 match( Set flags (CmpL src zero )); |
| 12529 effect(TEMP tmp); | |
| 12530 ins_cost(200); | |
| 12531 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12532 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12533 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12534 ins_pipe( ialu_reg_reg_long ); | |
| 12535 %} | |
| 12536 | |
| 12537 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12538 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12539 match( Set flags (CmpL src1 src2 )); | |
| 12540 ins_cost(200+300); | |
| 12541 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12542 "JNE,s skip\n\t" | |
| 12543 "CMP $src1.hi,$src2.hi\n\t" | |
| 12544 "skip:\t" %} | |
| 12545 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12546 ins_pipe( ialu_cr_reg_reg ); | |
| 12547 %} | |
| 12548 | |
| 12549 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12550 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12551 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12552 match(If cmp flags); | |
| 12553 effect(USE labl); | |
| 12554 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12555 expand %{ | |
| 12556 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12557 %} | |
| 12558 %} | |
| 12559 | |
| 12560 // Compare 2 longs and CMOVE longs. | |
| 12561 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12562 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12563 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12564 ins_cost(400); | |
| 12565 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12566 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12567 opcode(0x0F,0x40); | |
| 12568 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12569 ins_pipe( pipe_cmov_reg_long ); | |
| 12570 %} | |
| 12571 | |
| 12572 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12573 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12574 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12575 ins_cost(500); | |
| 12576 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12577 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12578 opcode(0x0F,0x40); | |
| 12579 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12580 ins_pipe( pipe_cmov_reg_long ); | |
| 12581 %} | |
| 12582 | |
| 12583 // Compare 2 longs and CMOVE ints. | |
|
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12584 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12585 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12586 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12587 ins_cost(200); | |
| 12588 format %{ "CMOV$cmp $dst,$src" %} | |
| 12589 opcode(0x0F,0x40); | |
| 12590 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12591 ins_pipe( pipe_cmov_reg ); | |
| 12592 %} | |
| 12593 | |
|
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12594 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12595 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12596 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12597 ins_cost(250); | |
| 12598 format %{ "CMOV$cmp $dst,$src" %} | |
| 12599 opcode(0x0F,0x40); | |
| 12600 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12601 ins_pipe( pipe_cmov_mem ); | |
| 12602 %} | |
| 12603 | |
| 12604 // Compare 2 longs and CMOVE ints. | |
| 12605 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12606 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12607 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12608 ins_cost(200); | |
| 12609 format %{ "CMOV$cmp $dst,$src" %} | |
| 12610 opcode(0x0F,0x40); | |
| 12611 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12612 ins_pipe( pipe_cmov_reg ); | |
| 12613 %} | |
| 12614 | |
| 12615 // Compare 2 longs and CMOVE doubles | |
|
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12616 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12617 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12618 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12619 ins_cost(200); | |
| 12620 expand %{ | |
|
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12621 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12622 %} |
| 12623 %} | |
| 12624 | |
| 12625 // Compare 2 longs and CMOVE doubles | |
|
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12626 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12627 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12628 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12629 ins_cost(200); | |
| 12630 expand %{ | |
|
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|
12631 fcmovD_regS(cmp,flags,dst,src); |
|
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12632 %} |
|
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|
12633 %} |
|
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|
12634 |
|
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|
12635 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12636 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
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12637 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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|
12638 ins_cost(200); |
|
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|
12639 expand %{ |
|
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|
12640 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12641 %} |
| 12642 %} | |
| 12643 | |
| 12644 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12645 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12646 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12647 ins_cost(200); | |
| 12648 expand %{ | |
| 12649 fcmovF_regS(cmp,flags,dst,src); | |
| 12650 %} | |
| 12651 %} | |
| 12652 | |
| 12653 //====== | |
| 12654 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12655 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
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12656 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12657 match( Set flags (CmpL src zero )); |
| 12658 effect( TEMP tmp ); | |
| 12659 ins_cost(300); | |
| 12660 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12661 "CMP $tmp,$src.lo\n\t" | |
| 12662 "SBB $tmp,$src.hi\n\t" %} | |
| 12663 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12664 ins_pipe( ialu_reg_reg_long ); | |
| 12665 %} | |
| 12666 | |
| 12667 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12668 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12669 // requires a commuted test to get the same result. | |
|
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12670 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12671 match( Set flags (CmpL src1 src2 )); |
| 12672 effect( TEMP tmp ); | |
| 12673 ins_cost(300); | |
| 12674 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12675 "MOV $tmp,$src2.hi\n\t" | |
| 12676 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12677 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12678 ins_pipe( ialu_cr_reg_reg ); | |
| 12679 %} | |
| 12680 | |
| 12681 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12682 // Just a wrapper for a normal branch, plus the predicate test | |
| 12683 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12684 match(If cmp flags); | |
| 12685 effect(USE labl); | |
| 12686 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12687 ins_cost(300); | |
| 12688 expand %{ | |
| 12689 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12690 %} | |
| 12691 %} | |
| 12692 | |
| 12693 // Compare 2 longs and CMOVE longs. | |
| 12694 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12695 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12696 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12697 ins_cost(400); | |
| 12698 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12699 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12700 opcode(0x0F,0x40); | |
| 12701 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12702 ins_pipe( pipe_cmov_reg_long ); | |
| 12703 %} | |
| 12704 | |
| 12705 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12706 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12707 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12708 ins_cost(500); | |
| 12709 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12710 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12711 opcode(0x0F,0x40); | |
| 12712 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12713 ins_pipe( pipe_cmov_reg_long ); | |
| 12714 %} | |
| 12715 | |
| 12716 // Compare 2 longs and CMOVE ints. | |
|
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12717 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12718 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12719 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12720 ins_cost(200); | |
| 12721 format %{ "CMOV$cmp $dst,$src" %} | |
| 12722 opcode(0x0F,0x40); | |
| 12723 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12724 ins_pipe( pipe_cmov_reg ); | |
| 12725 %} | |
| 12726 | |
|
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12727 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12728 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12729 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12730 ins_cost(250); | |
| 12731 format %{ "CMOV$cmp $dst,$src" %} | |
| 12732 opcode(0x0F,0x40); | |
| 12733 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12734 ins_pipe( pipe_cmov_mem ); | |
| 12735 %} | |
| 12736 | |
| 12737 // Compare 2 longs and CMOVE ptrs. | |
| 12738 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12739 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12740 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12741 ins_cost(200); | |
| 12742 format %{ "CMOV$cmp $dst,$src" %} | |
| 12743 opcode(0x0F,0x40); | |
| 12744 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12745 ins_pipe( pipe_cmov_reg ); | |
| 12746 %} | |
| 12747 | |
| 12748 // Compare 2 longs and CMOVE doubles | |
|
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12749 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12750 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12751 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12752 ins_cost(200); | |
| 12753 expand %{ | |
|
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|
12754 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12755 %} |
| 12756 %} | |
| 12757 | |
| 12758 // Compare 2 longs and CMOVE doubles | |
|
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12759 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12760 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12761 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12762 ins_cost(200); | |
| 12763 expand %{ | |
|
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|
12764 fcmovD_regS(cmp,flags,dst,src); |
|
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|
12765 %} |
|
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|
12766 %} |
|
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|
12767 |
|
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|
12768 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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12769 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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|
12770 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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|
12771 ins_cost(200); |
|
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|
12772 expand %{ |
|
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|
12773 fcmovFPR_regS(cmp,flags,dst,src); |
|
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|
12774 %} |
|
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|
12775 %} |
|
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|
12776 |
| 0 | 12777 |
| 12778 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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|
12779 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12780 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12781 ins_cost(200); | |
| 12782 expand %{ | |
| 12783 fcmovF_regS(cmp,flags,dst,src); | |
| 12784 %} | |
| 12785 %} | |
| 12786 | |
| 12787 | |
| 12788 // ============================================================================ | |
| 12789 // Procedure Call/Return Instructions | |
| 12790 // Call Java Static Instruction | |
| 12791 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12792 // compute_padding() functions will have to be adjusted. | |
| 12793 instruct CallStaticJavaDirect(method meth) %{ | |
| 12794 match(CallStaticJava); | |
|
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|
12795 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 12796 effect(USE meth); |
| 12797 | |
| 12798 ins_cost(300); | |
| 12799 format %{ "CALL,static " %} | |
| 12800 opcode(0xE8); /* E8 cd */ | |
| 12801 ins_encode( pre_call_FPU, | |
| 12802 Java_Static_Call( meth ), | |
| 12803 call_epilog, | |
| 12804 post_call_FPU ); | |
| 12805 ins_pipe( pipe_slow ); | |
| 12806 ins_alignment(4); | |
| 12807 %} | |
| 12808 | |
|
1137
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|
12809 // Call Java Static Instruction (method handle version) |
|
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|
12810 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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|
12811 // compute_padding() functions will have to be adjusted. |
| 1567 | 12812 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
1137
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|
12813 match(CallStaticJava); |
|
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|
12814 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
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|
12815 effect(USE meth); |
|
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|
12816 // EBP is saved by all callees (for interpreter stack correction). |
|
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|
12817 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
12818 |
|
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|
12819 ins_cost(300); |
|
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|
12820 format %{ "CALL,static/MethodHandle " %} |
|
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|
12821 opcode(0xE8); /* E8 cd */ |
|
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|
12822 ins_encode( pre_call_FPU, |
|
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|
12823 preserve_SP, |
|
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|
12824 Java_Static_Call( meth ), |
|
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|
12825 restore_SP, |
|
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|
12826 call_epilog, |
|
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|
12827 post_call_FPU ); |
|
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|
12828 ins_pipe( pipe_slow ); |
|
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|
12829 ins_alignment(4); |
|
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|
12830 %} |
|
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|
12831 |
| 0 | 12832 // Call Java Dynamic Instruction |
| 12833 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12834 // compute_padding() functions will have to be adjusted. | |
| 12835 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12836 match(CallDynamicJava); | |
| 12837 effect(USE meth); | |
| 12838 | |
| 12839 ins_cost(300); | |
| 12840 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12841 "CALL,dynamic" %} | |
| 12842 opcode(0xE8); /* E8 cd */ | |
| 12843 ins_encode( pre_call_FPU, | |
| 12844 Java_Dynamic_Call( meth ), | |
| 12845 call_epilog, | |
| 12846 post_call_FPU ); | |
| 12847 ins_pipe( pipe_slow ); | |
| 12848 ins_alignment(4); | |
| 12849 %} | |
| 12850 | |
| 12851 // Call Runtime Instruction | |
| 12852 instruct CallRuntimeDirect(method meth) %{ | |
| 12853 match(CallRuntime ); | |
| 12854 effect(USE meth); | |
| 12855 | |
| 12856 ins_cost(300); | |
| 12857 format %{ "CALL,runtime " %} | |
| 12858 opcode(0xE8); /* E8 cd */ | |
| 12859 // Use FFREEs to clear entries in float stack | |
| 12860 ins_encode( pre_call_FPU, | |
| 12861 FFree_Float_Stack_All, | |
| 12862 Java_To_Runtime( meth ), | |
| 12863 post_call_FPU ); | |
| 12864 ins_pipe( pipe_slow ); | |
| 12865 %} | |
| 12866 | |
| 12867 // Call runtime without safepoint | |
| 12868 instruct CallLeafDirect(method meth) %{ | |
| 12869 match(CallLeaf); | |
| 12870 effect(USE meth); | |
| 12871 | |
| 12872 ins_cost(300); | |
| 12873 format %{ "CALL_LEAF,runtime " %} | |
| 12874 opcode(0xE8); /* E8 cd */ | |
| 12875 ins_encode( pre_call_FPU, | |
| 12876 FFree_Float_Stack_All, | |
| 12877 Java_To_Runtime( meth ), | |
| 12878 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12879 ins_pipe( pipe_slow ); | |
| 12880 %} | |
| 12881 | |
| 12882 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12883 match(CallLeafNoFP); | |
| 12884 effect(USE meth); | |
| 12885 | |
| 12886 ins_cost(300); | |
| 12887 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12888 opcode(0xE8); /* E8 cd */ | |
| 12889 ins_encode(Java_To_Runtime(meth)); | |
| 12890 ins_pipe( pipe_slow ); | |
| 12891 %} | |
| 12892 | |
| 12893 | |
| 12894 // Return Instruction | |
| 12895 // Remove the return address & jump to it. | |
| 12896 instruct Ret() %{ | |
| 12897 match(Return); | |
| 12898 format %{ "RET" %} | |
| 12899 opcode(0xC3); | |
| 12900 ins_encode(OpcP); | |
| 12901 ins_pipe( pipe_jmp ); | |
| 12902 %} | |
| 12903 | |
| 12904 // Tail Call; Jump from runtime stub to Java code. | |
| 12905 // Also known as an 'interprocedural jump'. | |
| 12906 // Target of jump will eventually return to caller. | |
| 12907 // TailJump below removes the return address. | |
| 12908 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12909 match(TailCall jump_target method_oop ); | |
| 12910 ins_cost(300); | |
| 12911 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12912 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12913 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12914 ins_pipe( pipe_jmp ); | |
| 12915 %} | |
| 12916 | |
| 12917 | |
| 12918 // Tail Jump; remove the return address; jump to target. | |
| 12919 // TailCall above leaves the return address around. | |
| 12920 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 12921 match( TailJump jump_target ex_oop ); | |
| 12922 ins_cost(300); | |
| 12923 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 12924 "JMP $jump_target " %} | |
| 12925 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12926 ins_encode( enc_pop_rdx, | |
| 12927 OpcP, RegOpc(jump_target) ); | |
| 12928 ins_pipe( pipe_jmp ); | |
| 12929 %} | |
| 12930 | |
| 12931 // Create exception oop: created by stack-crawling runtime code. | |
| 12932 // Created exception is now available to this handler, and is setup | |
| 12933 // just prior to jumping to this handler. No code emitted. | |
| 12934 instruct CreateException( eAXRegP ex_oop ) | |
| 12935 %{ | |
| 12936 match(Set ex_oop (CreateEx)); | |
| 12937 | |
| 12938 size(0); | |
| 12939 // use the following format syntax | |
| 12940 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 12941 ins_encode(); | |
| 12942 ins_pipe( empty ); | |
| 12943 %} | |
| 12944 | |
| 12945 | |
| 12946 // Rethrow exception: | |
| 12947 // The exception oop will come in the first argument position. | |
| 12948 // Then JUMP (not call) to the rethrow stub code. | |
| 12949 instruct RethrowException() | |
| 12950 %{ | |
| 12951 match(Rethrow); | |
| 12952 | |
| 12953 // use the following format syntax | |
| 12954 format %{ "JMP rethrow_stub" %} | |
| 12955 ins_encode(enc_rethrow); | |
| 12956 ins_pipe( pipe_jmp ); | |
| 12957 %} | |
| 12958 | |
| 12959 // inlined locking and unlocking | |
| 12960 | |
| 12961 | |
| 4777 | 12962 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 0 | 12963 match( Set cr (FastLock object box) ); |
| 4777 | 12964 effect( TEMP tmp, TEMP scr, USE_KILL box ); |
| 0 | 12965 ins_cost(300); |
| 4777 | 12966 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 12967 ins_encode( Fast_Lock(object,box,tmp,scr) ); |
| 12968 ins_pipe( pipe_slow ); | |
| 12969 %} | |
| 12970 | |
| 12971 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 12972 match( Set cr (FastUnlock object box) ); | |
| 4777 | 12973 effect( TEMP tmp, USE_KILL box ); |
| 0 | 12974 ins_cost(300); |
| 4777 | 12975 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
| 0 | 12976 ins_encode( Fast_Unlock(object,box,tmp) ); |
| 12977 ins_pipe( pipe_slow ); | |
| 12978 %} | |
| 12979 | |
| 12980 | |
| 12981 | |
| 12982 // ============================================================================ | |
| 12983 // Safepoint Instruction | |
| 12984 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 12985 match(SafePoint); | |
| 12986 effect(KILL cr); | |
| 12987 | |
| 12988 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 12989 // On SPARC that might be acceptable as we can generate the address with | |
| 12990 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 12991 // putting additional pressure on the index-0 in the D$. Because of | |
| 12992 // alignment (just like the situation at hand) the lower indices tend | |
| 12993 // to see more traffic. It'd be better to change the polling address | |
| 12994 // to offset 0 of the last $line in the polling page. | |
| 12995 | |
| 12996 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 12997 ins_cost(125); | |
| 12998 size(6) ; | |
| 12999 ins_encode( Safepoint_Poll() ); | |
| 13000 ins_pipe( ialu_reg_mem ); | |
| 13001 %} | |
| 13002 | |
| 4950 | 13003 |
| 13004 // ============================================================================ | |
| 13005 // This name is KNOWN by the ADLC and cannot be changed. | |
| 13006 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 13007 // for this guy. | |
| 13008 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 13009 match(Set dst (ThreadLocal)); | |
| 13010 effect(DEF dst, KILL cr); | |
| 13011 | |
| 13012 format %{ "MOV $dst, Thread::current()" %} | |
| 13013 ins_encode %{ | |
| 13014 Register dstReg = as_Register($dst$$reg); | |
| 13015 __ get_thread(dstReg); | |
| 13016 %} | |
| 13017 ins_pipe( ialu_reg_fat ); | |
| 13018 %} | |
| 13019 | |
| 13020 | |
| 13021 | |
| 0 | 13022 //----------PEEPHOLE RULES----------------------------------------------------- |
| 13023 // These must follow all instruction definitions as they use the names | |
| 13024 // defined in the instructions definitions. | |
| 13025 // | |
| 605 | 13026 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13027 // |
| 13028 // peepconstraint %{ | |
| 13029 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13030 // [, ...] ); | |
| 13031 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13032 // | |
| 13033 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13034 // // provide an instruction_number.operand_name for each operand that appears | |
| 13035 // // in the replacement instruction's match rule | |
| 13036 // | |
| 13037 // ---------VM FLAGS--------------------------------------------------------- | |
| 13038 // | |
| 13039 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 13040 // | |
| 13041 // Each peephole rule is given an identifying number starting with zero and | |
| 13042 // increasing by one in the order seen by the parser. An individual peephole | |
| 13043 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13044 // on the command-line. | |
| 13045 // | |
| 13046 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13047 // | |
| 13048 // Only match adjacent instructions in same basic block | |
| 13049 // Only equality constraints | |
| 13050 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13051 // Only one replacement instruction | |
| 13052 // | |
| 13053 // ---------EXAMPLE---------------------------------------------------------- | |
| 13054 // | |
| 13055 // // pertinent parts of existing instructions in architecture description | |
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13056 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 13057 // match(Set dst (CopyI src)); |
| 13058 // %} | |
| 13059 // | |
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13060 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 13061 // match(Set dst (AddI dst src)); |
| 13062 // effect(KILL cr); | |
| 13063 // %} | |
| 13064 // | |
| 13065 // // Change (inc mov) to lea | |
| 13066 // peephole %{ | |
| 13067 // // increment preceeded by register-register move | |
| 13068 // peepmatch ( incI_eReg movI ); | |
| 13069 // // require that the destination register of the increment | |
| 13070 // // match the destination register of the move | |
| 13071 // peepconstraint ( 0.dst == 1.dst ); | |
| 13072 // // construct a replacement instruction that sets | |
| 13073 // // the destination to ( move's source register + one ) | |
| 13074 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13075 // %} | |
| 13076 // | |
| 13077 // Implementation no longer uses movX instructions since | |
| 13078 // machine-independent system no longer uses CopyX nodes. | |
| 13079 // | |
| 13080 // peephole %{ | |
| 13081 // peepmatch ( incI_eReg movI ); | |
| 13082 // peepconstraint ( 0.dst == 1.dst ); | |
| 13083 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13084 // %} | |
| 13085 // | |
| 13086 // peephole %{ | |
| 13087 // peepmatch ( decI_eReg movI ); | |
| 13088 // peepconstraint ( 0.dst == 1.dst ); | |
| 13089 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13090 // %} | |
| 13091 // | |
| 13092 // peephole %{ | |
| 13093 // peepmatch ( addI_eReg_imm movI ); | |
| 13094 // peepconstraint ( 0.dst == 1.dst ); | |
| 13095 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13096 // %} | |
| 13097 // | |
| 13098 // peephole %{ | |
| 13099 // peepmatch ( addP_eReg_imm movP ); | |
| 13100 // peepconstraint ( 0.dst == 1.dst ); | |
| 13101 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13102 // %} | |
| 13103 | |
| 13104 // // Change load of spilled value to only a spill | |
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13105 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13106 // match(Set mem (StoreI mem src)); |
| 13107 // %} | |
| 13108 // | |
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13109 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13110 // match(Set dst (LoadI mem)); |
| 13111 // %} | |
| 13112 // | |
| 13113 peephole %{ | |
| 13114 peepmatch ( loadI storeI ); | |
| 13115 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13116 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13117 %} | |
| 13118 | |
| 13119 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13120 // These must follow all instruction definitions as they use the names | |
| 13121 // defined in the instructions definitions. |