Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 18857:5214669b01f2
moved generate_deopt_entry_for to InterpreterGenerator for all architectures
Contributed-by: Igor Ignatyev <igor.ignatyev@oracle.com>
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Tue, 13 Jan 2015 13:08:26 +0100 |
| parents | 52b4284cb496 |
| children |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
| 126 // Class for all registers | |
| 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 128 // Class for general registers | |
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129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
| 0 | 130 // Class for general registers which may be used for implicit null checks on win95 |
| 131 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
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132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); |
| 0 | 133 // Class of "X" registers |
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134 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
| 0 | 135 // Class of registers that can appear in an address with no offset. |
| 136 // EBP and ESP require an extra instruction byte for zero offset. | |
| 137 // Used in fast-unlock | |
| 138 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 139 // Class for general registers not including ECX | |
| 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 141 // Class for general registers not including EAX | |
| 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 143 // Class for general registers not including EAX or EBX. | |
| 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 145 // Class of EAX (for multiply and divide operations) | |
| 146 reg_class eax_reg(EAX); | |
| 147 // Class of EBX (for atomic add) | |
| 148 reg_class ebx_reg(EBX); | |
| 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 150 reg_class ecx_reg(ECX); | |
| 151 // Class of EDX (for multiply and divide operations) | |
| 152 reg_class edx_reg(EDX); | |
| 153 // Class of EDI (for synchronization) | |
| 154 reg_class edi_reg(EDI); | |
| 155 // Class of ESI (for synchronization) | |
| 156 reg_class esi_reg(ESI); | |
| 157 // Singleton class for interpreter's stack pointer | |
| 158 reg_class ebp_reg(EBP); | |
| 159 // Singleton class for stack pointer | |
| 160 reg_class sp_reg(ESP); | |
| 161 // Singleton class for instruction pointer | |
| 162 // reg_class ip_reg(EIP); | |
| 163 // Class of integer register pairs | |
| 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 165 // Class of integer register pairs that aligns with calling convention | |
| 166 reg_class eadx_reg( EAX,EDX ); | |
| 167 reg_class ebcx_reg( ECX,EBX ); | |
| 168 // Not AX or DX, used in divides | |
| 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 170 | |
| 171 // Floating point registers. Notice FPR0 is not a choice. | |
| 172 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 173 // a 2-address instructions out of Intels FP stack. | |
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174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
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175 |
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176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
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177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
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178 FPR7L,FPR7H ); |
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179 |
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180 reg_class fp_flt_reg0( FPR1L ); |
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181 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
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182 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
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183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
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184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
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185 |
| 0 | 186 %} |
| 187 | |
| 188 | |
| 189 //----------SOURCE BLOCK------------------------------------------------------- | |
| 190 // This is a block of C++ code which provides values, functions, and | |
| 191 // definitions necessary in the rest of the architecture description | |
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192 source_hpp %{ |
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193 // Must be visible to the DFA in dfa_x86_32.cpp |
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194 extern bool is_operand_hi32_zero(Node* n); |
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195 %} |
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196 |
| 0 | 197 source %{ |
| 304 | 198 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 199 #define RELOC_DISP32 Assembler::disp32_operand |
| 200 | |
| 201 #define __ _masm. | |
| 202 | |
| 203 // How to find the high register of a Long pair, given the low register | |
| 204 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 205 | |
| 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 207 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 208 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 209 | |
| 210 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 213 // of 128-bits operands for SSE instructions. | |
| 214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 215 // Store the value to a 128-bits operand. | |
| 216 operand[0] = lo; | |
| 217 operand[1] = hi; | |
| 218 return operand; | |
| 219 } | |
| 220 | |
| 221 // Buffer for 128-bits masks used by SSE instructions. | |
| 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 223 | |
| 224 // Static initialization during VM startup. | |
| 225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 229 | |
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230 // Offset hacking within calls. |
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231 static int pre_call_resets_size() { |
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232 int size = 0; |
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233 Compile* C = Compile::current(); |
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234 if (C->in_24_bit_fp_mode()) { |
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235 size += 6; // fldcw |
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236 } |
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237 if (C->max_vector_size() > 16) { |
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238 size += 3; // vzeroupper |
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239 } |
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240 return size; |
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241 } |
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242 |
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243 static int preserve_SP_size() { |
| 4759 | 244 return 2; // op, rm(reg/reg) |
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245 } |
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246 |
| 0 | 247 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 248 // from the start of the call to the point where the return address | |
| 249 // will point. | |
| 250 int MachCallStaticJavaNode::ret_addr_offset() { | |
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251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points |
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252 if (_method_handle_invoke) |
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253 offset += preserve_SP_size(); |
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254 return offset; |
| 0 | 255 } |
| 256 | |
| 257 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points |
| 0 | 259 } |
| 260 | |
| 261 static int sizeof_FFree_Float_Stack_All = -1; | |
| 262 | |
| 263 int MachCallRuntimeNode::ret_addr_offset() { | |
| 264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); |
| 0 | 266 } |
| 267 | |
| 268 // Indicate if the safepoint node needs the polling page as an input. | |
| 269 // Since x86 does have absolute addressing, it doesn't. | |
| 270 bool SafePointNode::needs_polling_address_input() { | |
| 271 return false; | |
| 272 } | |
| 273 | |
| 274 // | |
| 275 // Compute padding required for nodes which need alignment | |
| 276 // | |
| 277 | |
| 278 // The address of the call instruction needs to be 4-byte aligned to | |
| 279 // ensure that it does not span a cache line so that it can be patched. | |
| 280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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281 current_offset += pre_call_resets_size(); // skip fldcw, if any |
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282 current_offset += 1; // skip call opcode byte |
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283 return round_to(current_offset, alignment_required()) - current_offset; |
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284 } |
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285 |
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286 // The address of the call instruction needs to be 4-byte aligned to |
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287 // ensure that it does not span a cache line so that it can be patched. |
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288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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289 current_offset += pre_call_resets_size(); // skip fldcw, if any |
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290 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 291 current_offset += 1; // skip call opcode byte |
| 292 return round_to(current_offset, alignment_required()) - current_offset; | |
| 293 } | |
| 294 | |
| 295 // The address of the call instruction needs to be 4-byte aligned to | |
| 296 // ensure that it does not span a cache line so that it can be patched. | |
| 297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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298 current_offset += pre_call_resets_size(); // skip fldcw, if any |
| 0 | 299 current_offset += 5; // skip MOV instruction |
| 300 current_offset += 1; // skip call opcode byte | |
| 301 return round_to(current_offset, alignment_required()) - current_offset; | |
| 302 } | |
| 303 | |
| 304 // EMIT_RM() | |
| 305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 307 cbuf.insts()->emit_int8(c); |
| 0 | 308 } |
| 309 | |
| 310 // EMIT_CC() | |
| 311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 312 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 313 cbuf.insts()->emit_int8(c); |
| 0 | 314 } |
| 315 | |
| 316 // EMIT_OPCODE() | |
| 317 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 318 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 319 } |
| 320 | |
| 321 // EMIT_OPCODE() w/ relocation information | |
| 322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 323 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 324 emit_opcode(cbuf, code); |
| 325 } | |
| 326 | |
| 327 // EMIT_D8() | |
| 328 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 329 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 330 } |
| 331 | |
| 332 // EMIT_D16() | |
| 333 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 334 cbuf.insts()->emit_int16(d16); |
| 0 | 335 } |
| 336 | |
| 337 // EMIT_D32() | |
| 338 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 339 cbuf.insts()->emit_int32(d32); |
| 0 | 340 } |
| 341 | |
| 342 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 344 int format) { | |
| 1748 | 345 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 346 cbuf.insts()->emit_int32(d32); | |
| 0 | 347 } |
| 348 | |
| 349 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 351 int format) { | |
| 352 #ifdef ASSERT | |
| 353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 355 } |
| 356 #endif | |
| 1748 | 357 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 358 cbuf.insts()->emit_int32(d32); | |
| 0 | 359 } |
| 360 | |
| 361 // Access stack slot for load or store | |
| 362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 364 if( -128 <= disp && disp <= 127 ) { | |
| 365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 367 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 368 } else { | |
| 369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 371 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 372 } | |
| 373 } | |
| 374 | |
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375 // rRegI ereg, memory mem) %{ // emit_reg_mem |
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376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 377 // There is no index & no scale, use form without SIB byte |
| 378 if ((index == 0x4) && | |
| 379 (scale == 0) && (base != ESP_enc)) { | |
| 380 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 381 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 382 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 383 } | |
| 384 else { // If 8-bit displacement, mode 0x1 | |
| 385 if ((displace >= -128) && (displace <= 127) | |
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386 && (disp_reloc == relocInfo::none) ) { |
| 0 | 387 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 388 emit_d8(cbuf, displace); | |
| 389 } | |
| 390 else { // If 32-bit displacement | |
| 391 if (base == -1) { // Special flag for absolute address | |
| 392 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 393 // (manual lies; no SIB needed here) | |
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394 if ( disp_reloc != relocInfo::none ) { |
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395 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 396 } else { |
| 397 emit_d32 (cbuf, displace); | |
| 398 } | |
| 399 } | |
| 400 else { // Normal base + offset | |
| 401 emit_rm(cbuf, 0x2, reg_encoding, base); | |
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402 if ( disp_reloc != relocInfo::none ) { |
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403 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 404 } else { |
| 405 emit_d32 (cbuf, displace); | |
| 406 } | |
| 407 } | |
| 408 } | |
| 409 } | |
| 410 } | |
| 411 else { // Else, encode with the SIB byte | |
| 412 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 413 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 414 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 415 emit_rm(cbuf, scale, index, base); | |
| 416 } | |
| 417 else { // If 8-bit displacement, mode 0x1 | |
| 418 if ((displace >= -128) && (displace <= 127) | |
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419 && (disp_reloc == relocInfo::none) ) { |
| 0 | 420 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 421 emit_rm(cbuf, scale, index, base); | |
| 422 emit_d8(cbuf, displace); | |
| 423 } | |
| 424 else { // If 32-bit displacement | |
| 425 if (base == 0x04 ) { | |
| 426 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 427 emit_rm(cbuf, scale, index, 0x04); | |
| 428 } else { | |
| 429 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 430 emit_rm(cbuf, scale, index, base); | |
| 431 } | |
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432 if ( disp_reloc != relocInfo::none ) { |
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433 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 434 } else { |
| 435 emit_d32 (cbuf, displace); | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 } | |
| 440 } | |
| 441 | |
| 442 | |
| 443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 444 if( dst_encoding == src_encoding ) { | |
| 445 // reg-reg copy, use an empty encoding | |
| 446 } else { | |
| 447 emit_opcode( cbuf, 0x8B ); | |
| 448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 449 } | |
| 450 } | |
| 451 | |
| 4759 | 452 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 453 Label exit; | |
| 454 __ jccb(Assembler::noParity, exit); | |
| 455 __ pushf(); | |
| 456 // | |
| 457 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 458 // zero OF,AF,SF for NaN values. | |
| 459 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 460 // values returns 'less than' result (CF is set). | |
| 461 // Leave the rest of flags unchanged. | |
| 462 // | |
| 463 // 7 6 5 4 3 2 1 0 | |
| 464 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 465 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 466 // | |
| 467 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 468 __ popf(); | |
| 469 __ bind(exit); | |
| 470 } | |
| 471 | |
| 472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 473 Label done; | |
| 474 __ movl(dst, -1); | |
| 475 __ jcc(Assembler::parity, done); | |
| 476 __ jcc(Assembler::below, done); | |
| 477 __ setb(Assembler::notEqual, dst); | |
| 478 __ movzbl(dst, dst); | |
| 479 __ bind(done); | |
| 0 | 480 } |
| 481 | |
| 482 | |
| 483 //============================================================================= | |
| 2008 | 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 485 | |
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486 int Compile::ConstantTable::calculate_table_base_offset() const { |
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487 return 0; // absolute addressing, no offset |
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488 } |
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489 |
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490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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492 ShouldNotReachHere(); |
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493 } |
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494 |
| 2008 | 495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 496 // Empty encoding | |
| 497 } | |
| 498 | |
| 499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 500 return 0; | |
| 501 } | |
| 502 | |
| 503 #ifndef PRODUCT | |
| 504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 505 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 506 } | |
| 507 #endif | |
| 508 | |
| 509 | |
| 510 //============================================================================= | |
| 0 | 511 #ifndef PRODUCT |
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512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 513 Compile* C = ra_->C; |
| 514 | |
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515 int framesize = C->frame_size_in_bytes(); |
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516 int bangsize = C->bang_size_in_bytes(); |
| 0 | 517 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
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518 // Remove wordSize for return addr which is already pushed. |
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519 framesize -= wordSize; |
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520 |
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521 if (C->need_stack_bang(bangsize)) { |
| 0 | 522 framesize -= wordSize; |
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523 st->print("# stack bang (%d bytes)", bangsize); |
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524 st->print("\n\t"); |
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525 st->print("PUSH EBP\t# Save EBP"); |
| 0 | 526 if (framesize) { |
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527 st->print("\n\t"); |
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528 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 529 } |
| 530 } else { | |
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531 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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532 st->print("\n\t"); |
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533 framesize -= wordSize; |
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534 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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535 } |
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536 |
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537 if (VerifyStackAtCalls) { |
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538 st->print("\n\t"); |
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539 framesize -= wordSize; |
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540 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 541 } |
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542 |
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543 if( C->in_24_bit_fp_mode() ) { |
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544 st->print("\n\t"); |
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545 st->print("FLDCW \t# load 24 bit fpu control word"); |
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546 } |
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547 if (UseSSE >= 2 && VerifyFPU) { |
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548 st->print("\n\t"); |
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549 st->print("# verify FPU stack (must be clean on entry)"); |
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550 } |
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551 |
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552 #ifdef ASSERT |
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553 if (VerifyStackAtCalls) { |
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554 st->print("\n\t"); |
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555 st->print("# stack alignment check"); |
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556 } |
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557 #endif |
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558 st->cr(); |
| 0 | 559 } |
| 560 #endif | |
| 561 | |
| 562 | |
| 563 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 564 Compile* C = ra_->C; | |
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565 MacroAssembler _masm(&cbuf); |
| 0 | 566 |
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567 int framesize = C->frame_size_in_bytes(); |
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568 int bangsize = C->bang_size_in_bytes(); |
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569 |
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570 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode()); |
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571 |
| 1748 | 572 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 573 |
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574 if (C->has_mach_constant_base_node()) { |
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575 // NOTE: We set the table base offset here because users might be |
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576 // emitted before MachConstantBaseNode. |
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577 Compile::ConstantTable& constant_table = C->constant_table(); |
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578 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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579 } |
| 0 | 580 } |
| 581 | |
| 582 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 583 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 584 } | |
| 585 | |
| 586 int MachPrologNode::reloc() const { | |
| 587 return 0; // a large enough number | |
| 588 } | |
| 589 | |
| 590 //============================================================================= | |
| 591 #ifndef PRODUCT | |
| 592 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 593 Compile *C = ra_->C; | |
|
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594 int framesize = C->frame_size_in_bytes(); |
| 0 | 595 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 596 // Remove two words for return addr and rbp, | |
| 597 framesize -= 2*wordSize; | |
| 598 | |
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599 if (C->max_vector_size() > 16) { |
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600 st->print("VZEROUPPER"); |
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601 st->cr(); st->print("\t"); |
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602 } |
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603 if (C->in_24_bit_fp_mode()) { |
| 0 | 604 st->print("FLDCW standard control word"); |
| 605 st->cr(); st->print("\t"); | |
| 606 } | |
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607 if (framesize) { |
| 0 | 608 st->print("ADD ESP,%d\t# Destroy frame",framesize); |
| 609 st->cr(); st->print("\t"); | |
| 610 } | |
| 611 st->print_cr("POPL EBP"); st->print("\t"); | |
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612 if (do_polling() && C->is_method_compilation()) { |
| 0 | 613 st->print("TEST PollPage,EAX\t! Poll Safepoint"); |
| 614 st->cr(); st->print("\t"); | |
| 615 } | |
| 616 } | |
| 617 #endif | |
| 618 | |
| 619 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 620 Compile *C = ra_->C; | |
| 621 | |
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622 if (C->max_vector_size() > 16) { |
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623 // Clear upper bits of YMM registers when current compiled code uses |
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624 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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625 MacroAssembler masm(&cbuf); |
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626 masm.vzeroupper(); |
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627 } |
| 0 | 628 // If method set FPU control word, restore to standard control word |
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629 if (C->in_24_bit_fp_mode()) { |
| 0 | 630 MacroAssembler masm(&cbuf); |
| 631 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 632 } | |
| 633 | |
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634 int framesize = C->frame_size_in_bytes(); |
| 0 | 635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 636 // Remove two words for return addr and rbp, | |
| 637 framesize -= 2*wordSize; | |
| 638 | |
| 639 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 640 | |
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641 if (framesize >= 128) { |
| 0 | 642 emit_opcode(cbuf, 0x81); // add SP, #framesize |
| 643 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 644 emit_d32(cbuf, framesize); | |
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645 } else if (framesize) { |
| 0 | 646 emit_opcode(cbuf, 0x83); // add SP, #framesize |
| 647 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 648 emit_d8(cbuf, framesize); | |
| 649 } | |
| 650 | |
| 651 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 652 | |
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653 if (do_polling() && C->is_method_compilation()) { |
| 1748 | 654 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 655 emit_opcode(cbuf,0x85); |
| 656 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 657 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 658 } | |
| 659 } | |
| 660 | |
| 661 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 662 Compile *C = ra_->C; | |
| 663 // If method set FPU control word, restore to standard control word | |
| 664 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
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665 if (C->max_vector_size() > 16) size += 3; // vzeroupper |
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666 if (do_polling() && C->is_method_compilation()) size += 6; |
| 0 | 667 |
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668 int framesize = C->frame_size_in_bytes(); |
| 0 | 669 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 670 // Remove two words for return addr and rbp, | |
| 671 framesize -= 2*wordSize; | |
| 672 | |
| 673 size++; // popl rbp, | |
| 674 | |
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675 if (framesize >= 128) { |
| 0 | 676 size += 6; |
| 677 } else { | |
| 678 size += framesize ? 3 : 0; | |
| 679 } | |
| 680 return size; | |
| 681 } | |
| 682 | |
| 683 int MachEpilogNode::reloc() const { | |
| 684 return 0; // a large enough number | |
| 685 } | |
| 686 | |
| 687 const Pipeline * MachEpilogNode::pipeline() const { | |
| 688 return MachNode::pipeline_class(); | |
| 689 } | |
| 690 | |
| 691 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 692 | |
| 693 //============================================================================= | |
| 694 | |
| 695 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 696 static enum RC rc_class( OptoReg::Name reg ) { | |
| 697 | |
| 698 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 699 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 700 | |
| 701 VMReg r = OptoReg::as_VMReg(reg); | |
| 702 if (r->is_Register()) return rc_int; | |
| 703 if (r->is_FloatRegister()) { | |
| 704 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 705 return rc_float; | |
| 706 } | |
| 707 assert(r->is_XMMRegister(), "must be"); | |
| 708 return rc_xmm; | |
| 709 } | |
| 710 | |
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711 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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712 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 713 if( cbuf ) { |
| 714 emit_opcode (*cbuf, opcode ); | |
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715 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 716 #ifndef PRODUCT |
| 717 } else if( !do_size ) { | |
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718 if( size != 0 ) st->print("\n\t"); |
| 0 | 719 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
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720 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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721 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 722 } else { // FLD, FST, PUSH, POP |
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723 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 724 } |
| 725 #endif | |
| 726 } | |
| 727 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 728 return size+3+offset_size; | |
| 729 } | |
| 730 | |
| 731 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 732 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
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733 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 734 if (cbuf) { |
| 735 MacroAssembler _masm(cbuf); | |
| 736 if (reg_lo+1 == reg_hi) { // double move? | |
| 737 if (is_load) { | |
| 738 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 739 } else { | |
| 740 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 741 } | |
| 0 | 742 } else { |
| 4759 | 743 if (is_load) { |
| 744 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 745 } else { | |
| 746 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 747 } | |
| 0 | 748 } |
| 749 #ifndef PRODUCT | |
| 4759 | 750 } else if (!do_size) { |
| 751 if (size != 0) st->print("\n\t"); | |
| 752 if (reg_lo+1 == reg_hi) { // double move? | |
| 753 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 754 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 755 Matcher::regName[reg_lo], offset); | |
| 756 else st->print("MOVSD [ESP + #%d],%s", | |
| 757 offset, Matcher::regName[reg_lo]); | |
| 0 | 758 } else { |
| 4759 | 759 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 760 Matcher::regName[reg_lo], offset); | |
| 761 else st->print("MOVSS [ESP + #%d],%s", | |
| 762 offset, Matcher::regName[reg_lo]); | |
| 0 | 763 } |
| 764 #endif | |
| 765 } | |
| 766 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
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767 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 768 return size+5+offset_size; |
| 769 } | |
| 770 | |
| 771 | |
| 772 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
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773 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 774 if (cbuf) { |
| 775 MacroAssembler _masm(cbuf); | |
| 776 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 777 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 778 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 779 } else { | |
| 780 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 781 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 782 } | |
| 0 | 783 #ifndef PRODUCT |
| 4759 | 784 } else if (!do_size) { |
| 785 if (size != 0) st->print("\n\t"); | |
| 786 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 787 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
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788 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 789 } else { |
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790 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 791 } |
| 4759 | 792 } else { |
| 0 | 793 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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794 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 795 } else { |
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796 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 797 } |
| 4759 | 798 } |
| 0 | 799 #endif |
| 800 } | |
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801 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 802 // Only MOVAPS SSE prefix uses 1 byte. |
| 803 int sz = 4; | |
| 804 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 805 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 806 return size + sz; | |
| 0 | 807 } |
| 808 | |
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809 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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810 int src_hi, int dst_hi, int size, outputStream* st ) { |
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811 // 32-bit |
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812 if (cbuf) { |
| 4759 | 813 MacroAssembler _masm(cbuf); |
| 814 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 815 as_Register(Matcher::_regEncode[src_lo])); | |
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816 #ifndef PRODUCT |
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817 } else if (!do_size) { |
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818 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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819 #endif |
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820 } |
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821 return 4; |
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822 } |
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823 |
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824 |
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825 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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826 int src_hi, int dst_hi, int size, outputStream* st ) { |
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changeset
|
827 // 32-bit |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
828 if (cbuf) { |
| 4759 | 829 MacroAssembler _masm(cbuf); |
| 830 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 831 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
832 #ifndef PRODUCT |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
833 } else if (!do_size) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
834 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
835 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
836 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
837 return 4; |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
838 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
839 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
840 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 841 if( cbuf ) { |
| 842 emit_opcode(*cbuf, 0x8B ); | |
| 843 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 844 #ifndef PRODUCT | |
| 845 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
846 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
847 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 848 #endif |
| 849 } | |
| 850 return size+2; | |
| 851 } | |
| 852 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
853 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
854 int offset, int size, outputStream* st ) { |
| 0 | 855 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 856 if( cbuf ) { | |
| 857 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 858 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 859 #ifndef PRODUCT | |
| 860 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
861 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
862 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 863 #endif |
| 864 } | |
| 865 size += 2; | |
| 866 } | |
| 867 | |
| 868 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 869 const char *op_str; | |
| 870 int op; | |
| 871 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 872 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 873 op = 0xDD; | |
| 874 } else { // 32-bit store | |
| 875 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 876 op = 0xD9; | |
| 877 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 878 } | |
| 879 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
880 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 881 } |
| 882 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
883 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
884 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
885 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
886 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
887 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
888 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
889 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
890 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
891 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
892 int calc_size = 0; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
893 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
894 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
895 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
896 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
897 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
898 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
899 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
900 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
901 src_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
902 dst_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
903 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
904 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
905 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
906 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
907 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
908 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
909 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
910 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
911 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
912 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
913 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
914 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
915 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
916 if (cbuf) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
917 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
918 int offset = __ offset(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
919 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
920 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
921 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
922 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
923 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
924 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
925 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
926 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
927 __ pushl(Address(rsp, src_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
928 __ popl (Address(rsp, dst_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
929 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
930 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
931 __ movdqu(Address(rsp, -16), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
932 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
933 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
934 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
935 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
936 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
937 __ vmovdqu(Address(rsp, -32), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
938 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
939 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
940 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
941 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
942 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
943 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
944 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
945 int size = __ offset() - offset; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
946 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
947 return size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
948 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
949 } else if (!do_size) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
950 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
951 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
952 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
953 "popl [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
954 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
955 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
956 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
957 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
958 "popq [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
959 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
960 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
961 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
962 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
963 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
964 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
965 "movdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
966 "movdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
967 "movdqu xmm0, [rsp - #16]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
968 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
969 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
970 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
971 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
972 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
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973 "vmovdqu [rsp + #%d], xmm0\n\t" |
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974 "vmovdqu xmm0, [rsp - #32]", |
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975 src_offset, dst_offset); |
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976 break; |
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977 default: |
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978 ShouldNotReachHere(); |
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979 } |
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980 #endif |
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981 } |
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982 return calc_size; |
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983 } |
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984 |
| 0 | 985 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 986 // Get registers to move | |
| 987 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 988 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 989 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 990 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 991 | |
| 992 enum RC src_second_rc = rc_class(src_second); | |
| 993 enum RC src_first_rc = rc_class(src_first); | |
| 994 enum RC dst_second_rc = rc_class(dst_second); | |
| 995 enum RC dst_first_rc = rc_class(dst_first); | |
| 996 | |
| 997 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 998 | |
| 999 // Generate spill code! | |
| 1000 int size = 0; | |
| 1001 | |
| 1002 if( src_first == dst_first && src_second == dst_second ) | |
| 1003 return size; // Self copy, no move | |
| 1004 | |
|
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1005 if (bottom_type()->isa_vect() != NULL) { |
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1006 uint ireg = ideal_reg(); |
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1007 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
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1008 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
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1009 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
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1010 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
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1011 // mem -> mem |
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1012 int src_offset = ra_->reg2offset(src_first); |
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1013 int dst_offset = ra_->reg2offset(dst_first); |
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1014 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
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1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
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1016 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
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1017 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
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1018 int stack_offset = ra_->reg2offset(dst_first); |
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1019 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
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1020 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
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1021 int stack_offset = ra_->reg2offset(src_first); |
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1022 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
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1023 } else { |
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1024 ShouldNotReachHere(); |
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1025 } |
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1026 } |
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1027 |
| 0 | 1028 // -------------------------------------- |
| 1029 // Check for mem-mem move. push/pop to move. | |
| 1030 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1031 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1032 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
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1033 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1034 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1035 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1036 } | |
| 1037 // move low bits | |
|
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1038 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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1039 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1040 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
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1041 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1042 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1043 } |
| 1044 return size; | |
| 1045 } | |
| 1046 | |
| 1047 // -------------------------------------- | |
| 1048 // Check for integer reg-reg copy | |
| 1049 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
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1050 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1051 |
| 1052 // Check for integer store | |
| 1053 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
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1054 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1055 |
| 1056 // Check for integer load | |
| 1057 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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1058 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1059 |
|
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1060 // Check for integer reg-xmm reg copy |
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1061 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1063 "no 64 bit integer-float reg moves" ); |
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1064 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1065 } |
| 0 | 1066 // -------------------------------------- |
| 1067 // Check for float reg-reg copy | |
| 1068 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1069 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1070 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1071 if( cbuf ) { | |
| 1072 | |
| 1073 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1074 // indexing issue mentioned in a comment in the reg_def sections | |
| 1075 // for FPR registers many lines above here. | |
| 1076 | |
| 1077 if( src_first != FPR1L_num ) { | |
| 1078 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1079 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1080 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1081 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1082 } else { | |
| 1083 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1084 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1085 } | |
| 1086 #ifndef PRODUCT | |
| 1087 } else if( !do_size ) { | |
| 1088 if( size != 0 ) st->print("\n\t"); | |
| 1089 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1090 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1091 #endif | |
| 1092 } | |
| 1093 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1094 } | |
| 1095 | |
| 1096 // Check for float store | |
| 1097 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
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1098 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1099 } |
| 1100 | |
| 1101 // Check for float load | |
| 1102 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1103 int offset = ra_->reg2offset(src_first); | |
| 1104 const char *op_str; | |
| 1105 int op; | |
| 1106 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1107 op_str = "FLD_D"; | |
| 1108 op = 0xDD; | |
| 1109 } else { // 32-bit load | |
| 1110 op_str = "FLD_S"; | |
| 1111 op = 0xD9; | |
| 1112 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1113 } | |
| 1114 if( cbuf ) { | |
| 1115 emit_opcode (*cbuf, op ); | |
|
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1116 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1117 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1118 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1119 #ifndef PRODUCT | |
| 1120 } else if( !do_size ) { | |
| 1121 if( size != 0 ) st->print("\n\t"); | |
| 1122 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1123 #endif | |
| 1124 } | |
| 1125 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1126 return size + 3+offset_size+2; | |
| 1127 } | |
| 1128 | |
| 1129 // Check for xmm reg-reg copy | |
| 1130 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1131 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1132 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1133 "no non-adjacent float-moves" ); | |
|
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1134 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1135 } |
| 1136 | |
|
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1137 // Check for xmm reg-integer reg copy |
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1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1139 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1140 "no 64 bit float-integer reg moves" ); |
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1141 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1142 } |
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1143 |
| 0 | 1144 // Check for xmm store |
| 1145 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
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1146 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1147 } |
| 1148 | |
| 1149 // Check for float xmm load | |
| 1150 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
|
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1151 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1152 } |
| 1153 | |
| 1154 // Copy from float reg to xmm reg | |
| 1155 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1156 // copy to the top of stack from floating point reg | |
| 1157 // and use LEA to preserve flags | |
| 1158 if( cbuf ) { | |
| 1159 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1160 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1161 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1162 emit_d8(*cbuf,0xF8); | |
| 1163 #ifndef PRODUCT | |
| 1164 } else if( !do_size ) { | |
| 1165 if( size != 0 ) st->print("\n\t"); | |
| 1166 st->print("LEA ESP,[ESP-8]"); | |
| 1167 #endif | |
| 1168 } | |
| 1169 size += 4; | |
| 1170 | |
|
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1171 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1172 |
| 1173 // Copy from the temp memory to the xmm reg. | |
|
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1174 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1175 |
| 1176 if( cbuf ) { | |
| 1177 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1178 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1179 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1180 emit_d8(*cbuf,0x08); | |
| 1181 #ifndef PRODUCT | |
| 1182 } else if( !do_size ) { | |
| 1183 if( size != 0 ) st->print("\n\t"); | |
| 1184 st->print("LEA ESP,[ESP+8]"); | |
| 1185 #endif | |
| 1186 } | |
| 1187 size += 4; | |
| 1188 return size; | |
| 1189 } | |
| 1190 | |
| 1191 assert( size > 0, "missed a case" ); | |
| 1192 | |
| 1193 // -------------------------------------------------------------------- | |
| 1194 // Check for second bits still needing moving. | |
| 1195 if( src_second == dst_second ) | |
| 1196 return size; // Self copy; no move | |
| 1197 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1198 | |
| 1199 // Check for second word int-int move | |
| 1200 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
|
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1201 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1202 |
| 1203 // Check for second word integer store | |
| 1204 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
|
415
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1205 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1206 |
| 1207 // Check for second word integer load | |
| 1208 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
|
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1209 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1210 |
| 1211 | |
| 1212 Unimplemented(); | |
| 1213 } | |
| 1214 | |
| 1215 #ifndef PRODUCT | |
| 4950 | 1216 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1217 implementation( NULL, ra_, false, st ); |
| 1218 } | |
| 1219 #endif | |
| 1220 | |
| 1221 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1222 implementation( &cbuf, ra_, false, NULL ); | |
| 1223 } | |
| 1224 | |
| 1225 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1226 return implementation( NULL, ra_, true, NULL ); | |
| 1227 } | |
| 1228 | |
| 1229 | |
| 1230 //============================================================================= | |
| 1231 #ifndef PRODUCT | |
| 1232 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1234 int reg = ra_->get_reg_first(this); | |
| 1235 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1236 } | |
| 1237 #endif | |
| 1238 | |
| 1239 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1240 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1241 int reg = ra_->get_encode(this); | |
| 1242 if( offset >= 128 ) { | |
| 1243 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1244 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1245 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1246 emit_d32(cbuf, offset); | |
| 1247 } | |
| 1248 else { | |
| 1249 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1250 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1251 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1252 emit_d8(cbuf, offset); | |
| 1253 } | |
| 1254 } | |
| 1255 | |
| 1256 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1257 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1258 if( offset >= 128 ) { | |
| 1259 return 7; | |
| 1260 } | |
| 1261 else { | |
| 1262 return 4; | |
| 1263 } | |
| 1264 } | |
| 1265 | |
| 1266 //============================================================================= | |
| 1267 #ifndef PRODUCT | |
| 1268 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1269 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1270 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1271 st->print_cr("\tNOP"); | |
| 1272 st->print_cr("\tNOP"); | |
| 1273 if( !OptoBreakpoint ) | |
| 1274 st->print_cr("\tNOP"); | |
| 1275 } | |
| 1276 #endif | |
| 1277 | |
| 1278 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1279 MacroAssembler masm(&cbuf); | |
| 1280 #ifdef ASSERT | |
| 1748 | 1281 uint insts_size = cbuf.insts_size(); |
| 0 | 1282 #endif |
| 304 | 1283 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1284 masm.jump_cc(Assembler::notEqual, |
| 1285 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1286 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1287 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1288 int nops_cnt = 2; | |
| 1289 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1290 nops_cnt += 1; | |
| 1291 masm.nop(nops_cnt); | |
| 1292 | |
| 1748 | 1293 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1294 } |
| 1295 | |
| 1296 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1297 return OptoBreakpoint ? 11 : 12; | |
| 1298 } | |
| 1299 | |
| 1300 | |
| 1301 //============================================================================= | |
| 1302 | |
| 1303 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1304 return regnum - 32; // The FP registers are in the second chunk | |
| 1305 } | |
| 1306 | |
| 1307 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1308 const bool Matcher::convL2FSupported(void) { | |
| 1309 return true; | |
| 1310 } | |
| 1311 | |
| 1312 // Is this branch offset short enough that a short branch can be used? | |
| 1313 // | |
| 1314 // NOTE: If the platform does not provide any short branch variants, then | |
| 1315 // this method should return false for offset 0. | |
| 3851 | 1316 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1317 // The passed offset is relative to address of the branch. | |
| 1318 // On 86 a branch displacement is calculated relative to address | |
| 1319 // of a next instruction. | |
| 1320 offset -= br_size; | |
| 1321 | |
|
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1322 // the short version of jmpConUCF2 contains multiple branches, |
|
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1323 // making the reach slightly less |
|
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1324 if (rule == jmpConUCF2_rule) |
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1325 return (-126 <= offset && offset <= 125); |
| 0 | 1326 return (-128 <= offset && offset <= 127); |
| 1327 } | |
| 1328 | |
| 1329 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1330 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1331 return false; | |
| 1332 } | |
| 1333 | |
| 1334 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1335 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1336 | |
| 1337 // Threshold size for cleararray. | |
| 1338 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1339 | |
| 4047 | 1340 // Needs 2 CMOV's for longs. |
| 1341 const int Matcher::long_cmove_cost() { return 1; } | |
| 1342 | |
| 1343 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1344 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1345 | |
|
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1346 // Does the CPU require late expand (see block.cpp for description of late expand)? |
|
044b28168e20
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|
1347 const bool Matcher::require_postalloc_expand = false; |
|
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|
1348 |
| 0 | 1349 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1350 // be subsumed into complex addressing expressions or compute them into | |
| 1351 // registers? True for Intel but false for most RISCs | |
| 1352 const bool Matcher::clone_shift_expressions = true; | |
| 1353 | |
|
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1354 // Do we need to mask the count passed to shift instructions or does |
|
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1355 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1356 const bool Matcher::need_masked_shift_count = false; |
|
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|
1357 |
|
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1358 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1359 ShouldNotCallThis(); |
|
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|
1360 return true; |
|
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|
1361 } |
|
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|
1362 |
|
6848
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|
1363 bool Matcher::narrow_klass_use_complex_address() { |
|
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|
1364 ShouldNotCallThis(); |
|
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|
1365 return true; |
|
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|
1366 } |
|
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|
1367 |
|
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|
1368 |
| 0 | 1369 // Is it better to copy float constants, or load them directly from memory? |
| 1370 // Intel can load a float constant from a direct address, requiring no | |
| 1371 // extra registers. Most RISCs will have to materialize an address into a | |
| 1372 // register first, so they would do better to copy the constant from stack. | |
| 1373 const bool Matcher::rematerialize_float_constants = true; | |
| 1374 | |
| 1375 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1376 // needed. Else we split the double into 2 integer pieces and move it | |
| 1377 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1378 // Java calling convention forces doubles to be aligned. | |
| 1379 const bool Matcher::misaligned_doubles_ok = true; | |
| 1380 | |
| 1381 | |
| 1382 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1383 // Get the memory operand from the node | |
| 1384 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1385 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1386 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1387 uint opcnt = 1; // First operand | |
| 1388 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1389 while( idx >= skipped+num_edges ) { | |
| 1390 skipped += num_edges; | |
| 1391 opcnt++; // Bump operand count | |
| 1392 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1393 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1394 } | |
| 1395 | |
| 1396 MachOper *memory = node->_opnds[opcnt]; | |
| 1397 MachOper *new_memory = NULL; | |
| 1398 switch (memory->opcode()) { | |
| 1399 case DIRECT: | |
| 1400 case INDOFFSET32X: | |
| 1401 // No transformation necessary. | |
| 1402 return; | |
| 1403 case INDIRECT: | |
| 1404 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1405 break; | |
| 1406 case INDOFFSET8: | |
| 1407 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1408 break; | |
| 1409 case INDOFFSET32: | |
| 1410 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1411 break; | |
| 1412 case INDINDEXOFFSET: | |
| 1413 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1414 break; | |
| 1415 case INDINDEXSCALE: | |
| 1416 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1417 break; | |
| 1418 case INDINDEXSCALEOFFSET: | |
| 1419 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1420 break; | |
| 1421 case LOAD_LONG_INDIRECT: | |
| 1422 case LOAD_LONG_INDOFFSET32: | |
| 1423 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1424 return; | |
| 1425 default: | |
| 1426 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1427 return; | |
| 1428 } | |
| 1429 node->_opnds[opcnt] = new_memory; | |
| 1430 } | |
| 1431 | |
| 1432 // Advertise here if the CPU requires explicit rounding operations | |
| 1433 // to implement the UseStrictFP mode. | |
| 1434 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1435 | |
|
1274
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|
1436 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
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|
1437 // On x32 it is stored with convertion only when FPU is used for floats. |
|
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|
1438 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
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|
1439 |
| 0 | 1440 // Do ints take an entire long register or just half? |
| 1441 const bool Matcher::int_in_long = false; | |
| 1442 | |
| 1443 // Return whether or not this register is ever used as an argument. This | |
| 1444 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1445 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1446 // arguments in those registers not be available to the callee. | |
| 1447 bool Matcher::can_be_java_arg( int reg ) { | |
| 1448 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
6179
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1449 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1450 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1451 return false; | |
| 1452 } | |
| 1453 | |
| 1454 bool Matcher::is_spillable_arg( int reg ) { | |
| 1455 return can_be_java_arg(reg); | |
| 1456 } | |
| 1457 | |
|
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|
1458 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
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|
1459 // Use hardware integer DIV instruction when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1460 // it is faster than a code which use multiply. |
|
ae065c367d93
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|
1461 // Only when constant divisor fits into 32 bit |
|
ae065c367d93
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|
1462 // (min_jint is excluded to get only correct |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1463 // positive 32 bit values from negative). |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1464 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
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|
1465 (divisor == (int)divisor && divisor != min_jint); |
|
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|
1466 } |
|
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|
1467 |
| 0 | 1468 // Register for DIVI projection of divmodI |
| 1469 RegMask Matcher::divI_proj_mask() { | |
|
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|
1470 return EAX_REG_mask(); |
| 0 | 1471 } |
| 1472 | |
| 1473 // Register for MODI projection of divmodI | |
| 1474 RegMask Matcher::modI_proj_mask() { | |
|
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|
1475 return EDX_REG_mask(); |
| 0 | 1476 } |
| 1477 | |
| 1478 // Register for DIVL projection of divmodL | |
| 1479 RegMask Matcher::divL_proj_mask() { | |
| 1480 ShouldNotReachHere(); | |
| 1481 return RegMask(); | |
| 1482 } | |
| 1483 | |
| 1484 // Register for MODL projection of divmodL | |
| 1485 RegMask Matcher::modL_proj_mask() { | |
| 1486 ShouldNotReachHere(); | |
| 1487 return RegMask(); | |
| 1488 } | |
| 1489 | |
|
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|
1490 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
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|
1491 return EBP_REG_mask(); |
|
1137
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|
1492 } |
|
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|
1493 |
|
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|
1494 // Returns true if the high 32 bits of the value is known to be zero. |
|
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|
1495 bool is_operand_hi32_zero(Node* n) { |
|
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|
1496 int opc = n->Opcode(); |
|
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|
1497 if (opc == Op_AndL) { |
|
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|
1498 Node* o2 = n->in(2); |
|
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|
1499 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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|
1500 return true; |
|
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|
1501 } |
|
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|
1502 } |
|
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|
1503 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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|
1504 return true; |
|
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|
1505 } |
|
1209
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|
1506 return false; |
|
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|
1507 } |
|
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|
1508 |
| 0 | 1509 %} |
| 1510 | |
| 1511 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1512 // This block specifies the encoding classes used by the compiler to output | |
| 1513 // byte streams. Encoding classes generate functions which are called by | |
| 1514 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1515 // instruction. Operands specify their base encoding interface with the | |
| 1516 // interface keyword. There are currently supported four interfaces, | |
| 1517 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1518 // operand to generate a function which returns its register number when | |
| 1519 // queried. CONST_INTER causes an operand to generate a function which | |
| 1520 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1521 // operand to generate four functions which return the Base Register, the | |
| 1522 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1523 // queried. COND_INTER causes an operand to generate six functions which | |
| 1524 // return the encoding code (ie - encoding bits for the instruction) | |
| 1525 // associated with each basic boolean condition for a conditional instruction. | |
| 1526 // Instructions specify two basic values for encoding. They use the | |
| 1527 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1528 // the class names specified in the encoding block), and they use the | |
| 1529 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1530 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1531 // needs for encoding need to be specified. | |
| 1532 encode %{ | |
| 1533 // Build emit functions for each basic byte or larger field in the intel | |
| 1534 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1535 // code in the enc_class source block. Emit functions will live in the | |
| 1536 // main source block for now. In future, we can generalize this by | |
| 1537 // adding a syntax that specifies the sizes of fields in an order, | |
| 1538 // so that the adlc can build the emit functions automagically | |
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1539 |
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1540 // Emit primary opcode |
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1541 enc_class OpcP %{ |
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1542 emit_opcode(cbuf, $primary); |
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1543 %} |
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1544 |
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1545 // Emit secondary opcode |
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1546 enc_class OpcS %{ |
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1547 emit_opcode(cbuf, $secondary); |
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1548 %} |
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1549 |
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1550 // Emit opcode directly |
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1551 enc_class Opcode(immI d8) %{ |
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1552 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1553 %} |
| 1554 | |
| 1555 enc_class SizePrefix %{ | |
| 1556 emit_opcode(cbuf,0x66); | |
| 1557 %} | |
| 1558 | |
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1559 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1560 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1561 %} | |
| 1562 | |
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1563 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1564 emit_opcode(cbuf,$opcode$$constant); |
| 1565 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1566 %} | |
| 1567 | |
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1568 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1569 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1570 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1571 %} | |
| 1572 | |
| 1573 enc_class cdq_enc %{ | |
| 1574 // Full implementation of Java idiv and irem; checks for | |
| 1575 // special case as described in JVM spec., p.243 & p.271. | |
| 1576 // | |
| 1577 // normal case special case | |
| 1578 // | |
| 1579 // input : rax,: dividend min_int | |
| 1580 // reg: divisor -1 | |
| 1581 // | |
| 1582 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1583 // rdx: remainder (= rax, irem reg) 0 | |
| 1584 // | |
| 1585 // Code sequnce: | |
| 1586 // | |
| 1587 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1588 // 0F 85 0B 00 00 00 jne normal_case | |
| 1589 // 33 D2 xor rdx,edx | |
| 1590 // 83 F9 FF cmp rcx,0FFh | |
| 1591 // 0F 84 03 00 00 00 je done | |
| 1592 // normal_case: | |
| 1593 // 99 cdq | |
| 1594 // F7 F9 idiv rax,ecx | |
| 1595 // done: | |
| 1596 // | |
| 1597 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1598 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1599 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1600 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1601 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1602 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1603 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1604 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1605 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1606 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1607 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1608 // normal_case: | |
| 1609 emit_opcode(cbuf,0x99); // cdq | |
| 1610 // idiv (note: must be emitted by the user of this rule) | |
| 1611 // normal: | |
| 1612 %} | |
| 1613 | |
| 1614 // Dense encoding for older common ops | |
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1615 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1616 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1617 %} | |
| 1618 | |
| 1619 | |
| 1620 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1621 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1622 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1623 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1624 emit_opcode(cbuf, $primary | 0x02); | |
| 1625 } | |
| 1626 else { // If 32-bit immediate | |
| 1627 emit_opcode(cbuf, $primary); | |
| 1628 } | |
| 1629 %} | |
| 1630 | |
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1631 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1632 // Emit primary opcode and set sign-extend bit |
| 1633 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1634 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1635 emit_opcode(cbuf, $primary | 0x02); } | |
| 1636 else { // If 32-bit immediate | |
| 1637 emit_opcode(cbuf, $primary); | |
| 1638 } | |
| 1639 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1640 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1641 %} | |
| 1642 | |
| 1643 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1644 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1645 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1646 $$$emit8$imm$$constant; | |
| 1647 } | |
| 1648 else { // If 32-bit immediate | |
| 1649 // Output immediate | |
| 1650 $$$emit32$imm$$constant; | |
| 1651 } | |
| 1652 %} | |
| 1653 | |
| 1654 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1655 // Emit primary opcode and set sign-extend bit | |
| 1656 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1657 int con = (int)$imm$$constant; // Throw away top bits | |
| 1658 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1659 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1660 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1661 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1662 else emit_d32(cbuf,con); | |
| 1663 %} | |
| 1664 | |
| 1665 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1666 // Emit primary opcode and set sign-extend bit | |
| 1667 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1668 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1669 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1670 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1671 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1672 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1673 else emit_d32(cbuf,con); | |
| 1674 %} | |
| 1675 | |
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1676 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1677 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1678 %} | |
| 1679 | |
| 1680 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1681 int destlo = $dst$$reg; | |
| 1682 int desthi = HIGH_FROM_LOW(destlo); | |
| 1683 // bswap lo | |
| 1684 emit_opcode(cbuf, 0x0F); | |
| 1685 emit_cc(cbuf, 0xC8, destlo); | |
| 1686 // bswap hi | |
| 1687 emit_opcode(cbuf, 0x0F); | |
| 1688 emit_cc(cbuf, 0xC8, desthi); | |
| 1689 // xchg lo and hi | |
| 1690 emit_opcode(cbuf, 0x87); | |
| 1691 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1692 %} | |
| 1693 | |
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1694 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1695 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1696 %} | |
| 1697 | |
| 1698 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1699 $$$emit8$primary; | |
| 1700 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1701 %} | |
| 1702 | |
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1703 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1704 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1705 emit_d8(cbuf, op >> 8 ); | |
| 1706 emit_d8(cbuf, op & 255); | |
| 1707 %} | |
| 1708 | |
| 1709 // emulate a CMOV with a conditional branch around a MOV | |
| 1710 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1711 // Invert sense of branch from sense of CMOV | |
| 1712 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1713 emit_d8( cbuf, $brOffs$$constant ); | |
| 1714 %} | |
| 1715 | |
| 1716 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1717 Register Redi = as_Register(EDI_enc); // result register | |
| 1718 Register Reax = as_Register(EAX_enc); // super class | |
| 1719 Register Recx = as_Register(ECX_enc); // killed | |
| 1720 Register Resi = as_Register(ESI_enc); // sub class | |
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1721 Label miss; |
| 0 | 1722 |
| 1723 MacroAssembler _masm(&cbuf); | |
|
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1724 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1725 NULL, &miss, |
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1726 /*set_cond_codes:*/ true); |
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1727 if ($primary) { |
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1728 __ xorptr(Redi, Redi); |
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1729 } |
| 0 | 1730 __ bind(miss); |
| 1731 %} | |
| 1732 | |
| 1733 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1734 MacroAssembler masm(&cbuf); | |
| 1735 int start = masm.offset(); | |
| 1736 if (UseSSE >= 2) { | |
| 1737 if (VerifyFPU) { | |
| 1738 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1739 } | |
| 1740 } else { | |
| 1741 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1742 // Compiled code leaves it dirty. Do cleanup now. | |
| 1743 masm.empty_FPU_stack(); | |
| 1744 } | |
| 1745 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1746 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1747 } else { | |
| 1748 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1749 } | |
| 1750 %} | |
| 1751 | |
| 1752 enc_class Verify_FPU_For_Leaf %{ | |
| 1753 if( VerifyFPU ) { | |
| 1754 MacroAssembler masm(&cbuf); | |
| 1755 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1756 } | |
| 1757 %} | |
| 1758 | |
| 1759 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1760 // This is the instruction starting address for relocation info. | |
| 1748 | 1761 cbuf.set_insts_mark(); |
| 0 | 1762 $$$emit8$primary; |
| 1763 // CALL directly to the runtime | |
| 1748 | 1764 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1765 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1766 | |
| 1767 if (UseSSE >= 2) { | |
| 1768 MacroAssembler _masm(&cbuf); | |
| 1769 BasicType rt = tf()->return_type(); | |
| 1770 | |
| 1771 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1772 // A C runtime call where the return value is unused. In SSE2+ | |
| 1773 // mode the result needs to be removed from the FPU stack. It's | |
| 1774 // likely that this function call could be removed by the | |
| 1775 // optimizer if the C function is a pure function. | |
| 1776 __ ffree(0); | |
| 1777 } else if (rt == T_FLOAT) { | |
| 304 | 1778 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1779 __ fstp_s(Address(rsp, 0)); |
| 1780 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1781 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1782 } else if (rt == T_DOUBLE) { |
| 304 | 1783 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1784 __ fstp_d(Address(rsp, 0)); |
| 1785 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1786 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1787 } |
| 1788 } | |
| 1789 %} | |
| 1790 | |
| 1791 | |
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1792 enc_class pre_call_resets %{ |
| 0 | 1793 // If method sets FPU control word restore it here |
| 1748 | 1794 debug_only(int off0 = cbuf.insts_size()); |
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1795 if (ra_->C->in_24_bit_fp_mode()) { |
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1796 MacroAssembler _masm(&cbuf); |
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1797 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
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1798 } |
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1799 if (ra_->C->max_vector_size() > 16) { |
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1800 // Clear upper bits of YMM registers when current compiled code uses |
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1801 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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1802 MacroAssembler _masm(&cbuf); |
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1803 __ vzeroupper(); |
| 0 | 1804 } |
| 1748 | 1805 debug_only(int off1 = cbuf.insts_size()); |
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1806 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction"); |
| 0 | 1807 %} |
| 1808 | |
| 1809 enc_class post_call_FPU %{ | |
| 1810 // If method sets FPU control word do it here also | |
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1811 if (Compile::current()->in_24_bit_fp_mode()) { |
| 0 | 1812 MacroAssembler masm(&cbuf); |
| 1813 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1814 } | |
| 1815 %} | |
| 1816 | |
| 1817 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1818 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1819 // who we intended to call. | |
| 1748 | 1820 cbuf.set_insts_mark(); |
| 0 | 1821 $$$emit8$primary; |
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1822 if (!_method) { |
| 1748 | 1823 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1824 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
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1825 } else if (_optimized_virtual) { |
| 1748 | 1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1827 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1828 } else { | |
| 1748 | 1829 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1830 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1831 } | |
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1832 if (_method) { // Emit stub for static call. |
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1833 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 1834 } |
| 1835 %} | |
| 1836 | |
| 1837 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
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1838 MacroAssembler _masm(&cbuf); |
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1839 __ ic_call((address)$meth$$method); |
| 0 | 1840 %} |
| 1841 | |
| 1842 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
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1843 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1844 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1845 | |
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1846 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1847 cbuf.set_insts_mark(); |
| 0 | 1848 $$$emit8$primary; |
| 1849 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1850 emit_d8(cbuf, disp); // Displacement | |
| 1851 | |
| 1852 %} | |
| 1853 | |
| 1854 // Following encoding is no longer used, but may be restored if calling | |
| 1855 // convention changes significantly. | |
| 1856 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1857 // | |
| 1858 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1859 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1860 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1861 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1862 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1863 // | |
| 1864 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1865 // // // so we load it immediately before the call | |
| 1866 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1867 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1868 // | |
| 1869 // // xor rbp,ebp | |
| 1870 // emit_opcode(cbuf, 0x33); | |
| 1871 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1872 // | |
| 1873 // // CALL to interpreter. | |
| 1748 | 1874 // cbuf.set_insts_mark(); |
| 0 | 1875 // $$$emit8$primary; |
| 1748 | 1876 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1877 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1878 // %} | |
| 1879 | |
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1880 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1881 $$$emit8$primary; |
| 1882 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1883 $$$emit8$shift$$constant; | |
| 1884 %} | |
| 1885 | |
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1886 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1887 // Load immediate does not have a zero or sign extended version |
| 1888 // for 8-bit immediates | |
| 1889 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1890 $$$emit32$src$$constant; | |
| 1891 %} | |
| 1892 | |
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1893 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1894 // Load immediate does not have a zero or sign extended version |
| 1895 // for 8-bit immediates | |
| 1896 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1897 $$$emit32$src$$constant; | |
| 1898 %} | |
| 1899 | |
| 1900 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1901 // Load immediate does not have a zero or sign extended version | |
| 1902 // for 8-bit immediates | |
| 1903 int dst_enc = $dst$$reg; | |
| 1904 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1905 if (src_con == 0) { | |
| 1906 // xor dst, dst | |
| 1907 emit_opcode(cbuf, 0x33); | |
| 1908 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1909 } else { | |
| 1910 emit_opcode(cbuf, $primary + dst_enc); | |
| 1911 emit_d32(cbuf, src_con); | |
| 1912 } | |
| 1913 %} | |
| 1914 | |
| 1915 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1916 // Load immediate does not have a zero or sign extended version | |
| 1917 // for 8-bit immediates | |
| 1918 int dst_enc = $dst$$reg + 2; | |
| 1919 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1920 if (src_con == 0) { | |
| 1921 // xor dst, dst | |
| 1922 emit_opcode(cbuf, 0x33); | |
| 1923 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1924 } else { | |
| 1925 emit_opcode(cbuf, $primary + dst_enc); | |
| 1926 emit_d32(cbuf, src_con); | |
| 1927 } | |
| 1928 %} | |
| 1929 | |
| 1930 | |
| 1931 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
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1932 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1933 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1934 %} | |
| 1935 | |
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1936 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1937 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1938 %} | |
| 1939 | |
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1940 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1941 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1942 %} | |
| 1943 | |
| 1944 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1945 $$$emit8$primary; | |
| 1946 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1947 %} | |
| 1948 | |
| 1949 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1950 $$$emit8$secondary; | |
| 1951 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1952 %} | |
| 1953 | |
| 1954 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1956 %} | |
| 1957 | |
| 1958 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1959 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1960 %} | |
| 1961 | |
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1962 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 1963 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 1964 %} | |
| 1965 | |
| 1966 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 1967 // Output immediate | |
| 1968 $$$emit32$src$$constant; | |
| 1969 %} | |
| 1970 | |
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1971 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 1972 // Output Float immediate bits |
| 1973 jfloat jf = $src$$constant; | |
| 1974 int jf_as_bits = jint_cast( jf ); | |
| 1975 emit_d32(cbuf, jf_as_bits); | |
| 1976 %} | |
| 1977 | |
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1978 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 1979 // Output Float immediate bits |
| 1980 jfloat jf = $src$$constant; | |
| 1981 int jf_as_bits = jint_cast( jf ); | |
| 1982 emit_d32(cbuf, jf_as_bits); | |
| 1983 %} | |
| 1984 | |
| 1985 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 1986 // Output immediate | |
| 1987 $$$emit16$src$$constant; | |
| 1988 %} | |
| 1989 | |
| 1990 enc_class Con_d32(immI src) %{ | |
| 1991 emit_d32(cbuf,$src$$constant); | |
| 1992 %} | |
| 1993 | |
| 1994 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 1995 // Output immediate memory reference | |
| 1996 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 1997 emit_d32(cbuf, 0x00); | |
| 1998 %} | |
| 1999 | |
| 2000 enc_class lock_prefix( ) %{ | |
| 2001 if( os::is_MP() ) | |
| 2002 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2003 %} | |
| 2004 | |
| 2005 // Cmp-xchg long value. | |
| 2006 // Note: we need to swap rbx, and rcx before and after the | |
| 2007 // cmpxchg8 instruction because the instruction uses | |
| 2008 // rcx as the high order word of the new value to store but | |
| 2009 // our register encoding uses rbx,. | |
| 2010 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2011 | |
| 2012 // XCHG rbx,ecx | |
| 2013 emit_opcode(cbuf,0x87); | |
| 2014 emit_opcode(cbuf,0xD9); | |
| 2015 // [Lock] | |
| 2016 if( os::is_MP() ) | |
| 2017 emit_opcode(cbuf,0xF0); | |
| 2018 // CMPXCHG8 [Eptr] | |
| 2019 emit_opcode(cbuf,0x0F); | |
| 2020 emit_opcode(cbuf,0xC7); | |
| 2021 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2022 // XCHG rbx,ecx | |
| 2023 emit_opcode(cbuf,0x87); | |
| 2024 emit_opcode(cbuf,0xD9); | |
| 2025 %} | |
| 2026 | |
| 2027 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2028 // [Lock] | |
| 2029 if( os::is_MP() ) | |
| 2030 emit_opcode(cbuf,0xF0); | |
| 2031 | |
| 2032 // CMPXCHG [Eptr] | |
| 2033 emit_opcode(cbuf,0x0F); | |
| 2034 emit_opcode(cbuf,0xB1); | |
| 2035 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2036 %} | |
| 2037 | |
| 2038 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2039 int res_encoding = $res$$reg; | |
| 2040 | |
| 2041 // MOV res,0 | |
| 2042 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2043 emit_d32( cbuf, 0 ); | |
| 2044 // JNE,s fail | |
| 2045 emit_opcode(cbuf,0x75); | |
| 2046 emit_d8(cbuf, 5 ); | |
| 2047 // MOV res,1 | |
| 2048 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2049 emit_d32( cbuf, 1 ); | |
| 2050 // fail: | |
| 2051 %} | |
| 2052 | |
| 2053 enc_class set_instruction_start( ) %{ | |
| 1748 | 2054 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2055 %} |
| 2056 | |
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2057 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2058 int reg_encoding = $ereg$$reg; |
| 2059 int base = $mem$$base; | |
| 2060 int index = $mem$$index; | |
| 2061 int scale = $mem$$scale; | |
| 2062 int displace = $mem$$disp; | |
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2063 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2064 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2065 %} |
| 2066 | |
| 2067 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2068 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2069 int base = $mem$$base; | |
| 2070 int index = $mem$$index; | |
| 2071 int scale = $mem$$scale; | |
| 2072 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
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2073 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
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2074 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2075 %} |
| 2076 | |
| 2077 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2078 int r1, r2; | |
| 2079 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2080 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2081 emit_opcode(cbuf,0x0F); | |
| 2082 emit_opcode(cbuf,$tertiary); | |
| 2083 emit_rm(cbuf, 0x3, r1, r2); | |
| 2084 emit_d8(cbuf,$cnt$$constant); | |
| 2085 emit_d8(cbuf,$primary); | |
| 2086 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2087 emit_d8(cbuf,$cnt$$constant); | |
| 2088 %} | |
| 2089 | |
| 2090 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2091 emit_opcode( cbuf, 0x8B ); // Move | |
| 2092 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2093 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2094 emit_d8(cbuf,$primary); |
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2095 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2096 emit_d8(cbuf,$cnt$$constant-32); |
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2097 } |
| 0 | 2098 emit_d8(cbuf,$primary); |
| 2099 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2100 emit_d8(cbuf,31); | |
| 2101 %} | |
| 2102 | |
| 2103 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2104 int r1, r2; | |
| 2105 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2106 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2107 | |
| 2108 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2109 emit_rm(cbuf, 0x3, r1, r2); | |
| 2110 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2111 emit_opcode(cbuf,$primary); | |
| 2112 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2113 emit_d8(cbuf,$cnt$$constant-32); | |
| 2114 } | |
| 2115 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2116 emit_rm(cbuf, 0x3, r2, r2); | |
| 2117 %} | |
| 2118 | |
| 2119 // Clone of RegMem but accepts an extra parameter to access each | |
| 2120 // half of a double in memory; it never needs relocation info. | |
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2121 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2122 emit_opcode(cbuf,$opcode$$constant); |
| 2123 int reg_encoding = $rm_reg$$reg; | |
| 2124 int base = $mem$$base; | |
| 2125 int index = $mem$$index; | |
| 2126 int scale = $mem$$scale; | |
| 2127 int displace = $mem$$disp + $disp_for_half$$constant; | |
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2128 relocInfo::relocType disp_reloc = relocInfo::none; |
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2129 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2130 %} |
| 2131 | |
| 2132 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2133 // | |
| 2134 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2135 // and it never needs relocation information. | |
| 2136 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2137 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2138 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2139 int base = $mem$$base; | |
| 2140 int index = $mem$$index; | |
| 2141 int scale = $mem$$scale; | |
| 2142 int displace = $mem$$disp; | |
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2143 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
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2144 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2145 %} |
| 2146 | |
| 2147 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2148 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2149 int base = $mem$$base; | |
| 2150 int index = $mem$$index; | |
| 2151 int scale = $mem$$scale; | |
| 2152 int displace = $mem$$disp; | |
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2153 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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2154 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2155 %} |
| 2156 | |
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2157 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2158 int reg_encoding = $dst$$reg; |
| 2159 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2160 int index = 0x04; // 0x04 indicates no index | |
| 2161 int scale = 0x00; // 0x00 indicates no scale | |
| 2162 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2163 relocInfo::relocType disp_reloc = relocInfo::none; |
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2164 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2165 %} |
| 2166 | |
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2167 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2168 // Compare dst,src |
| 2169 emit_opcode(cbuf,0x3B); | |
| 2170 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2171 // jmp dst < src around move | |
| 2172 emit_opcode(cbuf,0x7C); | |
| 2173 emit_d8(cbuf,2); | |
| 2174 // move dst,src | |
| 2175 emit_opcode(cbuf,0x8B); | |
| 2176 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2177 %} | |
| 2178 | |
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2179 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2180 // Compare dst,src |
| 2181 emit_opcode(cbuf,0x3B); | |
| 2182 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2183 // jmp dst > src around move | |
| 2184 emit_opcode(cbuf,0x7F); | |
| 2185 emit_d8(cbuf,2); | |
| 2186 // move dst,src | |
| 2187 emit_opcode(cbuf,0x8B); | |
| 2188 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2189 %} | |
| 2190 | |
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2191 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2192 // If src is FPR1, we can just FST to store it. |
| 2193 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2194 int reg_encoding = 0x2; // Just store | |
| 2195 int base = $mem$$base; | |
| 2196 int index = $mem$$index; | |
| 2197 int scale = $mem$$scale; | |
| 2198 int displace = $mem$$disp; | |
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2199 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2200 if( $src$$reg != FPR1L_enc ) { |
| 2201 reg_encoding = 0x3; // Store & pop | |
| 2202 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2203 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2204 } | |
| 1748 | 2205 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2206 emit_opcode(cbuf,$primary); |
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2207 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2208 %} |
| 2209 | |
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2210 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2211 // NEG $dst |
| 2212 emit_opcode(cbuf,0xF7); | |
| 2213 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2214 %} | |
| 2215 | |
| 2216 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2217 // SETLT $dst | |
| 2218 emit_opcode(cbuf,0x0F); | |
| 2219 emit_opcode(cbuf,0x9C); | |
| 2220 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2221 %} | |
| 2222 | |
| 2223 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2224 int tmpReg = $tmp$$reg; | |
| 2225 | |
| 2226 // SUB $p,$q | |
| 2227 emit_opcode(cbuf,0x2B); | |
| 2228 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2229 // SBB $tmp,$tmp | |
| 2230 emit_opcode(cbuf,0x1B); | |
| 2231 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2232 // AND $tmp,$y | |
| 2233 emit_opcode(cbuf,0x23); | |
| 2234 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2235 // ADD $p,$tmp | |
| 2236 emit_opcode(cbuf,0x03); | |
| 2237 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2238 %} | |
| 2239 | |
| 2240 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2241 // TEST shift,32 | |
| 2242 emit_opcode(cbuf,0xF7); | |
| 2243 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2244 emit_d32(cbuf,0x20); | |
| 2245 // JEQ,s small | |
| 2246 emit_opcode(cbuf, 0x74); | |
| 2247 emit_d8(cbuf, 0x04); | |
| 2248 // MOV $dst.hi,$dst.lo | |
| 2249 emit_opcode( cbuf, 0x8B ); | |
| 2250 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2251 // CLR $dst.lo | |
| 2252 emit_opcode(cbuf, 0x33); | |
| 2253 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2254 // small: | |
| 2255 // SHLD $dst.hi,$dst.lo,$shift | |
| 2256 emit_opcode(cbuf,0x0F); | |
| 2257 emit_opcode(cbuf,0xA5); | |
| 2258 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2259 // SHL $dst.lo,$shift" | |
| 2260 emit_opcode(cbuf,0xD3); | |
| 2261 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2262 %} | |
| 2263 | |
| 2264 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2265 // TEST shift,32 | |
| 2266 emit_opcode(cbuf,0xF7); | |
| 2267 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2268 emit_d32(cbuf,0x20); | |
| 2269 // JEQ,s small | |
| 2270 emit_opcode(cbuf, 0x74); | |
| 2271 emit_d8(cbuf, 0x04); | |
| 2272 // MOV $dst.lo,$dst.hi | |
| 2273 emit_opcode( cbuf, 0x8B ); | |
| 2274 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2275 // CLR $dst.hi | |
| 2276 emit_opcode(cbuf, 0x33); | |
| 2277 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2278 // small: | |
| 2279 // SHRD $dst.lo,$dst.hi,$shift | |
| 2280 emit_opcode(cbuf,0x0F); | |
| 2281 emit_opcode(cbuf,0xAD); | |
| 2282 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2283 // SHR $dst.hi,$shift" | |
| 2284 emit_opcode(cbuf,0xD3); | |
| 2285 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2286 %} | |
| 2287 | |
| 2288 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2289 // TEST shift,32 | |
| 2290 emit_opcode(cbuf,0xF7); | |
| 2291 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2292 emit_d32(cbuf,0x20); | |
| 2293 // JEQ,s small | |
| 2294 emit_opcode(cbuf, 0x74); | |
| 2295 emit_d8(cbuf, 0x05); | |
| 2296 // MOV $dst.lo,$dst.hi | |
| 2297 emit_opcode( cbuf, 0x8B ); | |
| 2298 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2299 // SAR $dst.hi,31 | |
| 2300 emit_opcode(cbuf, 0xC1); | |
| 2301 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2302 emit_d8(cbuf, 0x1F ); | |
| 2303 // small: | |
| 2304 // SHRD $dst.lo,$dst.hi,$shift | |
| 2305 emit_opcode(cbuf,0x0F); | |
| 2306 emit_opcode(cbuf,0xAD); | |
| 2307 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2308 // SAR $dst.hi,$shift" | |
| 2309 emit_opcode(cbuf,0xD3); | |
| 2310 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2311 %} | |
| 2312 | |
| 2313 | |
| 2314 // ----------------- Encodings for floating point unit ----------------- | |
| 2315 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2316 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2317 $$$emit8$primary; |
| 2318 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2319 %} | |
| 2320 | |
| 2321 // Pop argument in FPR0 with FSTP ST(0) | |
| 2322 enc_class PopFPU() %{ | |
| 2323 emit_opcode( cbuf, 0xDD ); | |
| 2324 emit_d8( cbuf, 0xD8 ); | |
| 2325 %} | |
| 2326 | |
| 2327 // !!!!! equivalent to Pop_Reg_F | |
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2328 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2329 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2330 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2331 %} | |
| 2332 | |
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2333 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2334 emit_opcode( cbuf, 0xD9 ); |
| 2335 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2336 %} | |
| 2337 | |
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2338 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2339 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2340 emit_opcode( cbuf, 0x2D ); | |
| 2341 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2342 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2343 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2344 %} | |
| 2345 | |
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2346 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2347 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2348 emit_opcode( cbuf, 0x2D ); | |
| 2349 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2350 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2351 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2352 %} | |
| 2353 | |
| 2354 // Special case for moving an integer register to a stack slot. | |
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2355 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2356 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2357 %} | |
| 2358 | |
| 2359 // Special case for moving a register to a stack slot. | |
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2360 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2361 // Opcode already emitted |
| 2362 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2363 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2364 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2365 %} | |
| 2366 | |
| 2367 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2368 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2369 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2370 %} | |
| 2371 | |
| 2372 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2373 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2374 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2375 %} | |
| 2376 | |
| 2377 // Same as Pop_Mem_F except for opcode | |
| 2378 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2379 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2380 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2381 %} | |
| 2382 | |
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2383 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2384 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2385 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2386 %} | |
| 2387 | |
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2388 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2389 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2390 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2391 %} | |
| 2392 | |
| 2393 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2394 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2395 int pop = 0x02; |
| 2396 if ($src$$reg != FPR1L_enc) { | |
| 2397 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2398 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2399 pop = 0x03; | |
| 2400 } | |
| 2401 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2402 %} | |
| 2403 | |
| 2404 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2405 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2406 int pop = 0x02; |
| 2407 if ($src$$reg != FPR1L_enc) { | |
| 2408 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2409 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2410 pop = 0x03; | |
| 2411 } | |
| 2412 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2413 %} | |
| 2414 | |
| 2415 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2416 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2417 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2418 if ($src$$reg != FPR1L_enc) { | |
| 2419 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2420 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2421 pop = 0xD8; | |
| 2422 } | |
| 2423 emit_opcode( cbuf, 0xDD ); | |
| 2424 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2425 %} | |
| 2426 | |
| 2427 | |
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2428 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2429 // load dst in FPR0 |
| 2430 emit_opcode( cbuf, 0xD9 ); | |
| 2431 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2432 if ($src$$reg != FPR1L_enc) { | |
| 2433 // fincstp | |
| 2434 emit_opcode (cbuf, 0xD9); | |
| 2435 emit_opcode (cbuf, 0xF7); | |
| 2436 // swap src with FPR1: | |
| 2437 // FXCH FPR1 with src | |
| 2438 emit_opcode(cbuf, 0xD9); | |
| 2439 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2440 // fdecstp | |
| 2441 emit_opcode (cbuf, 0xD9); | |
| 2442 emit_opcode (cbuf, 0xF6); | |
| 2443 } | |
| 2444 %} | |
| 2445 | |
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2446 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2447 MacroAssembler _masm(&cbuf); |
| 2448 __ subptr(rsp, 8); | |
| 2449 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2450 __ fld_d(Address(rsp, 0)); | |
| 2451 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2452 __ fld_d(Address(rsp, 0)); | |
| 2453 %} | |
| 2454 | |
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2455 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2456 MacroAssembler _masm(&cbuf); |
| 2457 __ subptr(rsp, 4); | |
| 2458 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2459 __ fld_s(Address(rsp, 0)); | |
| 2460 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2461 __ fld_s(Address(rsp, 0)); | |
| 0 | 2462 %} |
| 2463 | |
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2464 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2465 MacroAssembler _masm(&cbuf); |
| 2466 __ fstp_d(Address(rsp, 0)); | |
| 2467 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2468 __ addptr(rsp, 8); | |
| 0 | 2469 %} |
| 2470 | |
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2471 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2472 MacroAssembler _masm(&cbuf); |
| 2473 __ fstp_s(Address(rsp, 0)); | |
| 2474 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2475 __ addptr(rsp, $d8$$constant); | |
| 0 | 2476 %} |
| 2477 | |
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2478 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2479 MacroAssembler _masm(&cbuf); |
| 2480 __ subptr(rsp, 8); | |
| 2481 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2482 __ fld_d(Address(rsp, 0)); | |
| 0 | 2483 %} |
| 2484 | |
| 2485 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2486 MacroAssembler _masm(&cbuf); |
| 2487 __ subptr(rsp, 8); | |
| 0 | 2488 %} |
| 2489 | |
| 2490 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2491 MacroAssembler _masm(&cbuf); |
| 2492 __ addptr(rsp, 8); | |
| 2493 %} | |
| 2494 | |
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2495 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2496 MacroAssembler _masm(&cbuf); |
| 2497 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2498 __ fld_d(Address(rsp, 0)); | |
| 0 | 2499 %} |
| 2500 | |
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2501 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2502 if ($src$$reg != FPR1L_enc) { |
| 2503 // fincstp | |
| 2504 emit_opcode (cbuf, 0xD9); | |
| 2505 emit_opcode (cbuf, 0xF7); | |
| 2506 // FXCH FPR1 with src | |
| 2507 emit_opcode(cbuf, 0xD9); | |
| 2508 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2509 // fdecstp | |
| 2510 emit_opcode (cbuf, 0xD9); | |
| 2511 emit_opcode (cbuf, 0xF6); | |
| 2512 } | |
| 2513 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2514 // // FSTP FPR$dst$$reg | |
| 2515 // emit_opcode( cbuf, 0xDD ); | |
| 2516 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2517 %} | |
| 2518 | |
| 2519 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2520 // fnstsw ax | |
| 2521 emit_opcode( cbuf, 0xDF ); | |
| 2522 emit_opcode( cbuf, 0xE0 ); | |
| 2523 // sahf | |
| 2524 emit_opcode( cbuf, 0x9E ); | |
| 2525 // jnp ::skip | |
| 2526 emit_opcode( cbuf, 0x7B ); | |
| 2527 emit_opcode( cbuf, 0x05 ); | |
| 2528 %} | |
| 2529 | |
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2530 enc_class emitModDPR() %{ |
| 0 | 2531 // fprem must be iterative |
| 2532 // :: loop | |
| 2533 // fprem | |
| 2534 emit_opcode( cbuf, 0xD9 ); | |
| 2535 emit_opcode( cbuf, 0xF8 ); | |
| 2536 // wait | |
| 2537 emit_opcode( cbuf, 0x9b ); | |
| 2538 // fnstsw ax | |
| 2539 emit_opcode( cbuf, 0xDF ); | |
| 2540 emit_opcode( cbuf, 0xE0 ); | |
| 2541 // sahf | |
| 2542 emit_opcode( cbuf, 0x9E ); | |
| 2543 // jp ::loop | |
| 2544 emit_opcode( cbuf, 0x0F ); | |
| 2545 emit_opcode( cbuf, 0x8A ); | |
| 2546 emit_opcode( cbuf, 0xF4 ); | |
| 2547 emit_opcode( cbuf, 0xFF ); | |
| 2548 emit_opcode( cbuf, 0xFF ); | |
| 2549 emit_opcode( cbuf, 0xFF ); | |
| 2550 %} | |
| 2551 | |
| 2552 enc_class fpu_flags() %{ | |
| 2553 // fnstsw_ax | |
| 2554 emit_opcode( cbuf, 0xDF); | |
| 2555 emit_opcode( cbuf, 0xE0); | |
| 2556 // test ax,0x0400 | |
| 2557 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2558 emit_opcode( cbuf, 0xA9 ); | |
| 2559 emit_d16 ( cbuf, 0x0400 ); | |
| 2560 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2561 // // test rax,0x0400 | |
| 2562 // emit_opcode( cbuf, 0xA9 ); | |
| 2563 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2564 // | |
| 2565 // jz exit (no unordered comparison) | |
| 2566 emit_opcode( cbuf, 0x74 ); | |
| 2567 emit_d8 ( cbuf, 0x02 ); | |
| 2568 // mov ah,1 - treat as LT case (set carry flag) | |
| 2569 emit_opcode( cbuf, 0xB4 ); | |
| 2570 emit_d8 ( cbuf, 0x01 ); | |
| 2571 // sahf | |
| 2572 emit_opcode( cbuf, 0x9E); | |
| 2573 %} | |
| 2574 | |
| 2575 enc_class cmpF_P6_fixup() %{ | |
| 2576 // Fixup the integer flags in case comparison involved a NaN | |
| 2577 // | |
| 2578 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2579 emit_opcode( cbuf, 0x7B ); | |
| 2580 emit_d8 ( cbuf, 0x03 ); | |
| 2581 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2582 emit_opcode( cbuf, 0xB4 ); | |
| 2583 emit_d8 ( cbuf, 0x01 ); | |
| 2584 // SAHF | |
| 2585 emit_opcode( cbuf, 0x9E); | |
| 2586 // NOP // target for branch to avoid branch to branch | |
| 2587 emit_opcode( cbuf, 0x90); | |
| 2588 %} | |
| 2589 | |
| 2590 // fnstsw_ax(); | |
| 2591 // sahf(); | |
| 2592 // movl(dst, nan_result); | |
| 2593 // jcc(Assembler::parity, exit); | |
| 2594 // movl(dst, less_result); | |
| 2595 // jcc(Assembler::below, exit); | |
| 2596 // movl(dst, equal_result); | |
| 2597 // jcc(Assembler::equal, exit); | |
| 2598 // movl(dst, greater_result); | |
| 2599 | |
| 2600 // less_result = 1; | |
| 2601 // greater_result = -1; | |
| 2602 // equal_result = 0; | |
| 2603 // nan_result = -1; | |
| 2604 | |
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2605 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2606 // fnstsw_ax(); |
| 2607 emit_opcode( cbuf, 0xDF); | |
| 2608 emit_opcode( cbuf, 0xE0); | |
| 2609 // sahf | |
| 2610 emit_opcode( cbuf, 0x9E); | |
| 2611 // movl(dst, nan_result); | |
| 2612 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2613 emit_d32( cbuf, -1 ); | |
| 2614 // jcc(Assembler::parity, exit); | |
| 2615 emit_opcode( cbuf, 0x7A ); | |
| 2616 emit_d8 ( cbuf, 0x13 ); | |
| 2617 // movl(dst, less_result); | |
| 2618 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2619 emit_d32( cbuf, -1 ); | |
| 2620 // jcc(Assembler::below, exit); | |
| 2621 emit_opcode( cbuf, 0x72 ); | |
| 2622 emit_d8 ( cbuf, 0x0C ); | |
| 2623 // movl(dst, equal_result); | |
| 2624 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2625 emit_d32( cbuf, 0 ); | |
| 2626 // jcc(Assembler::equal, exit); | |
| 2627 emit_opcode( cbuf, 0x74 ); | |
| 2628 emit_d8 ( cbuf, 0x05 ); | |
| 2629 // movl(dst, greater_result); | |
| 2630 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2631 emit_d32( cbuf, 1 ); | |
| 2632 %} | |
| 2633 | |
| 2634 | |
| 2635 // Compare the longs and set flags | |
| 2636 // BROKEN! Do Not use as-is | |
| 2637 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2638 // CMP $src1.hi,$src2.hi | |
| 2639 emit_opcode( cbuf, 0x3B ); | |
| 2640 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2641 // JNE,s done | |
| 2642 emit_opcode(cbuf,0x75); | |
| 2643 emit_d8(cbuf, 2 ); | |
| 2644 // CMP $src1.lo,$src2.lo | |
| 2645 emit_opcode( cbuf, 0x3B ); | |
| 2646 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2647 // done: | |
| 2648 %} | |
| 2649 | |
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2650 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2651 // mov $dst.lo,$src |
| 2652 int dst_encoding = $dst$$reg; | |
| 2653 int src_encoding = $src$$reg; | |
| 2654 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2655 // mov $dst.hi,$src | |
| 2656 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2657 // sar $dst.hi,31 | |
| 2658 emit_opcode( cbuf, 0xC1 ); | |
| 2659 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2660 emit_d8(cbuf, 0x1F ); | |
| 2661 %} | |
| 2662 | |
| 2663 enc_class convert_long_double( eRegL src ) %{ | |
| 2664 // push $src.hi | |
| 2665 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2666 // push $src.lo | |
| 2667 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2668 // fild 64-bits at [SP] | |
| 2669 emit_opcode(cbuf,0xdf); | |
| 2670 emit_d8(cbuf, 0x6C); | |
| 2671 emit_d8(cbuf, 0x24); | |
| 2672 emit_d8(cbuf, 0x00); | |
| 2673 // pop stack | |
| 2674 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2675 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2676 emit_d8(cbuf, 0x8); | |
| 2677 %} | |
| 2678 | |
| 2679 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2680 // IMUL EDX:EAX,$src1 | |
| 2681 emit_opcode( cbuf, 0xF7 ); | |
| 2682 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2683 // SAR EDX,$cnt-32 | |
| 2684 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2685 if (shift_count > 0) { | |
| 2686 emit_opcode(cbuf, 0xC1); | |
| 2687 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2688 emit_d8(cbuf, shift_count); | |
| 2689 } | |
| 2690 %} | |
| 2691 | |
| 2692 // this version doesn't have add sp, 8 | |
| 2693 enc_class convert_long_double2( eRegL src ) %{ | |
| 2694 // push $src.hi | |
| 2695 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2696 // push $src.lo | |
| 2697 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2698 // fild 64-bits at [SP] | |
| 2699 emit_opcode(cbuf,0xdf); | |
| 2700 emit_d8(cbuf, 0x6C); | |
| 2701 emit_d8(cbuf, 0x24); | |
| 2702 emit_d8(cbuf, 0x00); | |
| 2703 %} | |
| 2704 | |
| 2705 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2706 // Basic idea: long = (long)int * (long)int | |
| 2707 // IMUL EDX:EAX, src | |
| 2708 emit_opcode( cbuf, 0xF7 ); | |
| 2709 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2710 %} | |
| 2711 | |
| 2712 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2713 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2714 // MUL EDX:EAX, src | |
| 2715 emit_opcode( cbuf, 0xF7 ); | |
| 2716 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2717 %} | |
| 2718 | |
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2719 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2720 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2721 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2722 // MOV $tmp,$src.lo | |
| 2723 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2724 // IMUL $tmp,EDX | |
| 2725 emit_opcode( cbuf, 0x0F ); | |
| 2726 emit_opcode( cbuf, 0xAF ); | |
| 2727 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2728 // MOV EDX,$src.hi | |
| 2729 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2730 // IMUL EDX,EAX | |
| 2731 emit_opcode( cbuf, 0x0F ); | |
| 2732 emit_opcode( cbuf, 0xAF ); | |
| 2733 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2734 // ADD $tmp,EDX | |
| 2735 emit_opcode( cbuf, 0x03 ); | |
| 2736 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2737 // MUL EDX:EAX,$src.lo | |
| 2738 emit_opcode( cbuf, 0xF7 ); | |
| 2739 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2740 // ADD EDX,ESI | |
| 2741 emit_opcode( cbuf, 0x03 ); | |
| 2742 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2743 %} | |
| 2744 | |
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2745 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2746 // Basic idea: lo(result) = lo(src * y_lo) |
| 2747 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2748 // IMUL $tmp,EDX,$src | |
| 2749 emit_opcode( cbuf, 0x6B ); | |
| 2750 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2751 emit_d8( cbuf, (int)$src$$constant ); | |
| 2752 // MOV EDX,$src | |
| 2753 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2754 emit_d32( cbuf, (int)$src$$constant ); | |
| 2755 // MUL EDX:EAX,EDX | |
| 2756 emit_opcode( cbuf, 0xF7 ); | |
| 2757 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2758 // ADD EDX,ESI | |
| 2759 emit_opcode( cbuf, 0x03 ); | |
| 2760 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2761 %} | |
| 2762 | |
| 2763 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2764 // PUSH src1.hi | |
| 2765 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2766 // PUSH src1.lo | |
| 2767 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2768 // PUSH src2.hi | |
| 2769 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2770 // PUSH src2.lo | |
| 2771 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2772 // CALL directly to the runtime | |
| 1748 | 2773 cbuf.set_insts_mark(); |
| 0 | 2774 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2775 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2776 // Restore stack |
| 2777 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2778 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2779 emit_d8(cbuf, 4*4); | |
| 2780 %} | |
| 2781 | |
| 2782 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2783 // PUSH src1.hi | |
| 2784 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2785 // PUSH src1.lo | |
| 2786 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2787 // PUSH src2.hi | |
| 2788 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2789 // PUSH src2.lo | |
| 2790 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2791 // CALL directly to the runtime | |
| 1748 | 2792 cbuf.set_insts_mark(); |
| 0 | 2793 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2794 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2795 // Restore stack |
| 2796 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2797 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2798 emit_d8(cbuf, 4*4); | |
| 2799 %} | |
| 2800 | |
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2801 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2802 // MOV $tmp,$src.lo |
| 2803 emit_opcode(cbuf, 0x8B); | |
| 2804 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2805 // OR $tmp,$src.hi | |
| 2806 emit_opcode(cbuf, 0x0B); | |
| 2807 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2808 %} | |
| 2809 | |
| 2810 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2811 // CMP $src1.lo,$src2.lo | |
| 2812 emit_opcode( cbuf, 0x3B ); | |
| 2813 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2814 // JNE,s skip | |
| 2815 emit_cc(cbuf, 0x70, 0x5); | |
| 2816 emit_d8(cbuf,2); | |
| 2817 // CMP $src1.hi,$src2.hi | |
| 2818 emit_opcode( cbuf, 0x3B ); | |
| 2819 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2820 %} | |
| 2821 | |
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2822 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2823 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2824 emit_opcode( cbuf, 0x3B ); | |
| 2825 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2826 // MOV $tmp,$src1.hi | |
| 2827 emit_opcode( cbuf, 0x8B ); | |
| 2828 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2829 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2830 emit_opcode( cbuf, 0x1B ); | |
| 2831 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2832 %} | |
| 2833 | |
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2834 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2835 // XOR $tmp,$tmp |
| 2836 emit_opcode(cbuf,0x33); // XOR | |
| 2837 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2838 // CMP $tmp,$src.lo | |
| 2839 emit_opcode( cbuf, 0x3B ); | |
| 2840 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2841 // SBB $tmp,$src.hi | |
| 2842 emit_opcode( cbuf, 0x1B ); | |
| 2843 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2844 %} | |
| 2845 | |
| 2846 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2847 enc_class neg_long( eRegL dst ) %{ | |
| 2848 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2849 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2850 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2851 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2852 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2853 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2854 emit_d8 (cbuf,0 ); | |
| 2855 %} | |
| 2856 | |
| 2857 enc_class enc_pop_rdx() %{ | |
| 2858 emit_opcode(cbuf,0x5A); | |
| 2859 %} | |
| 2860 | |
| 2861 enc_class enc_rethrow() %{ | |
| 1748 | 2862 cbuf.set_insts_mark(); |
| 0 | 2863 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 2864 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 2865 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 2866 %} | |
| 2867 | |
| 2868 | |
| 2869 // Convert a double to an int. Java semantics require we do complex | |
| 2870 // manglelations in the corner cases. So we set the rounding mode to | |
| 2871 // 'zero', store the darned double down as an int, and reset the | |
| 2872 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 2873 // patches up the correct value directly to the stack. | |
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2874 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 2875 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 2876 // exceptions here, so that a NAN or other corner-case value will | |
| 2877 // thrown an exception (but normal values get converted at full speed). | |
| 2878 // However, I2C adapters and other float-stack manglers leave pending | |
| 2879 // invalid-op exceptions hanging. We would have to clear them before | |
| 2880 // enabling them and that is more expensive than just testing for the | |
| 2881 // invalid value Intel stores down in the corner cases. | |
| 2882 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 2883 emit_opcode(cbuf,0x2D); | |
| 2884 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2885 // Allocate a word | |
| 2886 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2887 emit_opcode(cbuf,0xEC); | |
| 2888 emit_d8(cbuf,0x04); | |
| 2889 // Encoding assumes a double has been pushed into FPR0. | |
| 2890 // Store down the double as an int, popping the FPU stack | |
| 2891 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 2892 emit_opcode(cbuf,0x1C); | |
| 2893 emit_d8(cbuf,0x24); | |
| 2894 // Restore the rounding mode; mask the exception | |
| 2895 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2896 emit_opcode(cbuf,0x2D); | |
| 2897 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2898 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2899 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2900 | |
| 2901 // Load the converted int; adjust CPU stack | |
| 2902 emit_opcode(cbuf,0x58); // POP EAX | |
| 2903 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 2904 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2905 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2906 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2907 // Push src onto stack slow-path | |
| 2908 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2909 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2910 // CALL directly to the runtime | |
| 1748 | 2911 cbuf.set_insts_mark(); |
| 0 | 2912 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2913 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2914 // Carry on here... |
| 2915 %} | |
| 2916 | |
|
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2917 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 2918 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 2919 emit_opcode(cbuf,0x2D); | |
| 2920 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2921 // Allocate a word | |
| 2922 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2923 emit_opcode(cbuf,0xEC); | |
| 2924 emit_d8(cbuf,0x08); | |
| 2925 // Encoding assumes a double has been pushed into FPR0. | |
| 2926 // Store down the double as a long, popping the FPU stack | |
| 2927 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 2928 emit_opcode(cbuf,0x3C); | |
| 2929 emit_d8(cbuf,0x24); | |
| 2930 // Restore the rounding mode; mask the exception | |
| 2931 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2932 emit_opcode(cbuf,0x2D); | |
| 2933 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2934 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2935 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2936 | |
| 2937 // Load the converted int; adjust CPU stack | |
| 2938 emit_opcode(cbuf,0x58); // POP EAX | |
| 2939 emit_opcode(cbuf,0x5A); // POP EDX | |
| 2940 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 2941 emit_d8 (cbuf,0xFA); // rdx | |
| 2942 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2943 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2944 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 2945 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 2946 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 2947 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2948 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2949 // Push src onto stack slow-path | |
| 2950 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2951 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2952 // CALL directly to the runtime | |
| 1748 | 2953 cbuf.set_insts_mark(); |
| 0 | 2954 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2955 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2956 // Carry on here... |
| 2957 %} | |
| 2958 | |
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2959 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 2960 // Operand was loaded from memory into fp ST (stack top) |
| 2961 // FMUL ST,$src /* D8 C8+i */ | |
| 2962 emit_opcode(cbuf, 0xD8); | |
| 2963 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 2964 %} | |
| 2965 | |
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2966 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 2967 // FADDP ST,src2 /* D8 C0+i */ |
| 2968 emit_opcode(cbuf, 0xD8); | |
| 2969 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 2970 //could use FADDP src2,fpST /* DE C0+i */ | |
| 2971 %} | |
| 2972 | |
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2973 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 2974 // FADDP src2,ST /* DE C0+i */ |
| 2975 emit_opcode(cbuf, 0xDE); | |
| 2976 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 2977 %} | |
| 2978 | |
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2979 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 2980 // Operand has been loaded into fp ST (stack top) |
| 2981 // FSUB ST,$src1 | |
| 2982 emit_opcode(cbuf, 0xD8); | |
| 2983 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 2984 | |
| 2985 // FDIV | |
| 2986 emit_opcode(cbuf, 0xD8); | |
| 2987 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 2988 %} | |
| 2989 | |
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2990 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 2991 // Operand was loaded from memory into fp ST (stack top) |
| 2992 // FADD ST,$src /* D8 C0+i */ | |
| 2993 emit_opcode(cbuf, 0xD8); | |
| 2994 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 2995 | |
| 2996 // FMUL ST,src2 /* D8 C*+i */ | |
| 2997 emit_opcode(cbuf, 0xD8); | |
| 2998 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 2999 %} | |
| 3000 | |
| 3001 | |
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3002 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3003 // Operand was loaded from memory into fp ST (stack top) |
| 3004 // FADD ST,$src /* D8 C0+i */ | |
| 3005 emit_opcode(cbuf, 0xD8); | |
| 3006 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3007 | |
| 3008 // FMULP src2,ST /* DE C8+i */ | |
| 3009 emit_opcode(cbuf, 0xDE); | |
| 3010 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3011 %} | |
| 3012 | |
| 3013 // Atomically load the volatile long | |
| 3014 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3015 emit_opcode(cbuf,0xDF); | |
| 3016 int rm_byte_opcode = 0x05; | |
| 3017 int base = $mem$$base; | |
| 3018 int index = $mem$$index; | |
| 3019 int scale = $mem$$scale; | |
| 3020 int displace = $mem$$disp; | |
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3021 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3022 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3023 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3024 %} | |
| 3025 | |
| 3026 // Volatile Store Long. Must be atomic, so move it into | |
| 3027 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3028 // target address before the store (for null-ptr checks) | |
| 3029 // so the memory operand is used twice in the encoding. | |
| 3030 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3031 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3032 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3033 emit_opcode(cbuf,0xDF); |
| 3034 int rm_byte_opcode = 0x07; | |
| 3035 int base = $mem$$base; | |
| 3036 int index = $mem$$index; | |
| 3037 int scale = $mem$$scale; | |
| 3038 int displace = $mem$$disp; | |
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3039 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3040 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3041 %} |
| 3042 | |
| 3043 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3044 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3045 // in the process | |
| 3046 // We current use TESTL [spp],EDI | |
| 3047 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3048 | |
| 3049 enc_class Safepoint_Poll() %{ | |
| 1748 | 3050 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3051 emit_opcode(cbuf,0x85); |
| 3052 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3053 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3054 %} | |
| 3055 %} | |
| 3056 | |
| 3057 | |
| 3058 //----------FRAME-------------------------------------------------------------- | |
| 3059 // Definition of frame structure and management information. | |
| 3060 // | |
| 3061 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3062 // | (to get allocators register number | |
| 3063 // G Owned by | | v add OptoReg::stack0()) | |
| 3064 // r CALLER | | | |
| 3065 // o | +--------+ pad to even-align allocators stack-slot | |
| 3066 // w V | pad0 | numbers; owned by CALLER | |
| 3067 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3068 // h ^ | in | 5 | |
| 3069 // | | args | 4 Holes in incoming args owned by SELF | |
| 3070 // | | | | 3 | |
| 3071 // | | +--------+ | |
| 3072 // V | | old out| Empty on Intel, window on Sparc | |
| 3073 // | old |preserve| Must be even aligned. | |
| 3074 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3075 // | | in | 3 area for Intel ret address | |
| 3076 // Owned by |preserve| Empty on Sparc. | |
| 3077 // SELF +--------+ | |
| 3078 // | | pad2 | 2 pad to align old SP | |
| 3079 // | +--------+ 1 | |
| 3080 // | | locks | 0 | |
| 3081 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3082 // | | pad1 | 11 pad to align new SP | |
| 3083 // | +--------+ | |
| 3084 // | | | 10 | |
| 3085 // | | spills | 9 spills | |
| 3086 // V | | 8 (pad0 slot for callee) | |
| 3087 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3088 // ^ | out | 7 | |
| 3089 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3090 // Owned by +--------+ | |
| 3091 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3092 // | new |preserve| Must be even-aligned. | |
| 3093 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3094 // | | | | |
| 3095 // | |
| 3096 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3097 // known from SELF's arguments and the Java calling convention. | |
| 3098 // Region 6-7 is determined per call site. | |
| 3099 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3100 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3101 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3102 // incoming area, as the Java calling convention is completely under | |
| 3103 // the control of the AD file. Doubles can be sorted and packed to | |
| 3104 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3105 // varargs C calling conventions. | |
| 3106 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3107 // even aligned with pad0 as needed. | |
| 3108 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3109 // region 6-11 is even aligned; it may be padded out more so that | |
| 3110 // the region from SP to FP meets the minimum stack alignment. | |
| 3111 | |
| 3112 frame %{ | |
| 3113 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3114 stack_direction(TOWARDS_LOW); | |
| 3115 | |
| 3116 // These three registers define part of the calling convention | |
| 3117 // between compiled code and the interpreter. | |
| 3118 inline_cache_reg(EAX); // Inline Cache Register | |
| 3119 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3120 | |
| 3121 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3122 cisc_spilling_operand_name(indOffset32); | |
| 3123 | |
| 3124 // Number of stack slots consumed by locking an object | |
| 3125 sync_stack_slots(1); | |
| 3126 | |
| 3127 // Compiled code's Frame Pointer | |
| 3128 frame_pointer(ESP); | |
| 3129 // Interpreter stores its frame pointer in a register which is | |
| 3130 // stored to the stack by I2CAdaptors. | |
| 3131 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3132 interpreter_frame_pointer(EBP); | |
| 3133 | |
| 3134 // Stack alignment requirement | |
| 3135 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3136 stack_alignment(StackAlignmentInBytes); | |
| 3137 | |
| 3138 // Number of stack slots between incoming argument block and the start of | |
| 3139 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3140 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3141 // return address and one for rbp, (must save rbp) | |
| 3142 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3143 | |
| 3144 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3145 // for calls to C. Supports the var-args backing area for register parms. | |
| 3146 varargs_C_out_slots_killed(0); | |
| 3147 | |
| 3148 // The after-PROLOG location of the return address. Location of | |
| 3149 // return address specifies a type (REG or STACK) and a number | |
| 3150 // representing the register number (i.e. - use a register name) or | |
| 3151 // stack slot. | |
| 3152 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3153 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3154 return_addr(STACK - 1 + | |
| 4950 | 3155 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3156 Compile::current()->fixed_slots()), | |
| 3157 stack_alignment_in_slots())); | |
| 0 | 3158 |
| 3159 // Body of function which returns an integer array locating | |
| 3160 // arguments either in registers or in stack slots. Passed an array | |
| 3161 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3162 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3163 // arguments for a CALLEE. Incoming stack arguments are | |
| 3164 // automatically biased by the preserve_stack_slots field above. | |
| 3165 calling_convention %{ | |
| 3166 // No difference between ingoing/outgoing just pass false | |
| 3167 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3168 %} | |
| 3169 | |
| 3170 | |
| 3171 // Body of function which returns an integer array locating | |
| 3172 // arguments either in registers or in stack slots. Passed an array | |
| 3173 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3174 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3175 // arguments for a CALLEE. Incoming stack arguments are | |
| 3176 // automatically biased by the preserve_stack_slots field above. | |
| 3177 c_calling_convention %{ | |
| 3178 // This is obviously always outgoing | |
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3179 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3180 %} |
| 3181 | |
| 3182 // Location of C & interpreter return values | |
| 3183 c_return_value %{ | |
| 3184 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3185 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3186 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3187 |
| 3188 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3189 // that C functions return float and double results in XMM0. | |
| 3190 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
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3191 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3192 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
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3193 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3194 |
| 3195 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3196 %} | |
| 3197 | |
| 3198 // Location of return values | |
| 3199 return_value %{ | |
| 3200 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3201 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3202 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3203 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
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3204 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3205 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
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3206 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3207 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3208 %} | |
| 3209 | |
| 3210 %} | |
| 3211 | |
| 3212 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3213 //----------Operand Attributes------------------------------------------------- | |
| 3214 op_attrib op_cost(0); // Required cost attribute | |
| 3215 | |
| 3216 //----------Instruction Attributes--------------------------------------------- | |
| 3217 ins_attrib ins_cost(100); // Required cost attribute | |
| 3218 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3219 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3220 // non-matching short branch variant of some | |
| 3221 // long branch? | |
| 3222 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3223 // specifies the alignment that some part of the instruction (not | |
| 3224 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3225 // function must be provided for the instruction | |
| 3226 | |
| 3227 //----------OPERANDS----------------------------------------------------------- | |
| 3228 // Operand definitions must precede instruction definitions for correct parsing | |
| 3229 // in the ADLC because operands constitute user defined types which are used in | |
| 3230 // instruction definitions. | |
| 3231 | |
| 3232 //----------Simple Operands---------------------------------------------------- | |
| 3233 // Immediate Operands | |
| 3234 // Integer Immediate | |
| 3235 operand immI() %{ | |
| 3236 match(ConI); | |
| 3237 | |
| 3238 op_cost(10); | |
| 3239 format %{ %} | |
| 3240 interface(CONST_INTER); | |
| 3241 %} | |
| 3242 | |
| 3243 // Constant for test vs zero | |
| 3244 operand immI0() %{ | |
| 3245 predicate(n->get_int() == 0); | |
| 3246 match(ConI); | |
| 3247 | |
| 3248 op_cost(0); | |
| 3249 format %{ %} | |
| 3250 interface(CONST_INTER); | |
| 3251 %} | |
| 3252 | |
| 3253 // Constant for increment | |
| 3254 operand immI1() %{ | |
| 3255 predicate(n->get_int() == 1); | |
| 3256 match(ConI); | |
| 3257 | |
| 3258 op_cost(0); | |
| 3259 format %{ %} | |
| 3260 interface(CONST_INTER); | |
| 3261 %} | |
| 3262 | |
| 3263 // Constant for decrement | |
| 3264 operand immI_M1() %{ | |
| 3265 predicate(n->get_int() == -1); | |
| 3266 match(ConI); | |
| 3267 | |
| 3268 op_cost(0); | |
| 3269 format %{ %} | |
| 3270 interface(CONST_INTER); | |
| 3271 %} | |
| 3272 | |
| 3273 // Valid scale values for addressing modes | |
| 3274 operand immI2() %{ | |
| 3275 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3276 match(ConI); | |
| 3277 | |
| 3278 format %{ %} | |
| 3279 interface(CONST_INTER); | |
| 3280 %} | |
| 3281 | |
| 3282 operand immI8() %{ | |
| 3283 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3284 match(ConI); | |
| 3285 | |
| 3286 op_cost(5); | |
| 3287 format %{ %} | |
| 3288 interface(CONST_INTER); | |
| 3289 %} | |
| 3290 | |
| 3291 operand immI16() %{ | |
| 3292 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3293 match(ConI); | |
| 3294 | |
| 3295 op_cost(10); | |
| 3296 format %{ %} | |
| 3297 interface(CONST_INTER); | |
| 3298 %} | |
| 3299 | |
|
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3300 // Int Immediate non-negative |
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3301 operand immU31() |
|
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|
3302 %{ |
|
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|
3303 predicate(n->get_int() >= 0); |
|
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|
3304 match(ConI); |
|
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|
3305 |
|
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|
3306 op_cost(0); |
|
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|
3307 format %{ %} |
|
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|
3308 interface(CONST_INTER); |
|
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|
3309 %} |
|
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|
3310 |
| 0 | 3311 // Constant for long shifts |
| 3312 operand immI_32() %{ | |
| 3313 predicate( n->get_int() == 32 ); | |
| 3314 match(ConI); | |
| 3315 | |
| 3316 op_cost(0); | |
| 3317 format %{ %} | |
| 3318 interface(CONST_INTER); | |
| 3319 %} | |
| 3320 | |
| 3321 operand immI_1_31() %{ | |
| 3322 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3323 match(ConI); | |
| 3324 | |
| 3325 op_cost(0); | |
| 3326 format %{ %} | |
| 3327 interface(CONST_INTER); | |
| 3328 %} | |
| 3329 | |
| 3330 operand immI_32_63() %{ | |
| 3331 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3332 match(ConI); | |
| 3333 op_cost(0); | |
| 3334 | |
| 3335 format %{ %} | |
| 3336 interface(CONST_INTER); | |
| 3337 %} | |
| 3338 | |
| 219 | 3339 operand immI_1() %{ |
| 3340 predicate( n->get_int() == 1 ); | |
| 3341 match(ConI); | |
| 3342 | |
| 3343 op_cost(0); | |
| 3344 format %{ %} | |
| 3345 interface(CONST_INTER); | |
| 3346 %} | |
| 3347 | |
| 3348 operand immI_2() %{ | |
| 3349 predicate( n->get_int() == 2 ); | |
| 3350 match(ConI); | |
| 3351 | |
| 3352 op_cost(0); | |
| 3353 format %{ %} | |
| 3354 interface(CONST_INTER); | |
| 3355 %} | |
| 3356 | |
| 3357 operand immI_3() %{ | |
| 3358 predicate( n->get_int() == 3 ); | |
| 3359 match(ConI); | |
| 3360 | |
| 3361 op_cost(0); | |
| 3362 format %{ %} | |
| 3363 interface(CONST_INTER); | |
| 3364 %} | |
| 3365 | |
| 0 | 3366 // Pointer Immediate |
| 3367 operand immP() %{ | |
| 3368 match(ConP); | |
| 3369 | |
| 3370 op_cost(10); | |
| 3371 format %{ %} | |
| 3372 interface(CONST_INTER); | |
| 3373 %} | |
| 3374 | |
| 3375 // NULL Pointer Immediate | |
| 3376 operand immP0() %{ | |
| 3377 predicate( n->get_ptr() == 0 ); | |
| 3378 match(ConP); | |
| 3379 op_cost(0); | |
| 3380 | |
| 3381 format %{ %} | |
| 3382 interface(CONST_INTER); | |
| 3383 %} | |
| 3384 | |
| 3385 // Long Immediate | |
| 3386 operand immL() %{ | |
| 3387 match(ConL); | |
| 3388 | |
| 3389 op_cost(20); | |
| 3390 format %{ %} | |
| 3391 interface(CONST_INTER); | |
| 3392 %} | |
| 3393 | |
| 3394 // Long Immediate zero | |
| 3395 operand immL0() %{ | |
| 3396 predicate( n->get_long() == 0L ); | |
| 3397 match(ConL); | |
| 3398 op_cost(0); | |
| 3399 | |
| 3400 format %{ %} | |
| 3401 interface(CONST_INTER); | |
| 3402 %} | |
| 3403 | |
| 403 | 3404 // Long Immediate zero |
| 3405 operand immL_M1() %{ | |
| 3406 predicate( n->get_long() == -1L ); | |
| 3407 match(ConL); | |
| 3408 op_cost(0); | |
| 3409 | |
| 3410 format %{ %} | |
| 3411 interface(CONST_INTER); | |
| 3412 %} | |
| 3413 | |
| 0 | 3414 // Long immediate from 0 to 127. |
| 3415 // Used for a shorter form of long mul by 10. | |
| 3416 operand immL_127() %{ | |
| 3417 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3418 match(ConL); | |
| 3419 op_cost(0); | |
| 3420 | |
| 3421 format %{ %} | |
| 3422 interface(CONST_INTER); | |
| 3423 %} | |
| 3424 | |
| 3425 // Long Immediate: low 32-bit mask | |
| 3426 operand immL_32bits() %{ | |
| 3427 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3428 match(ConL); | |
| 3429 op_cost(0); | |
| 3430 | |
| 3431 format %{ %} | |
| 3432 interface(CONST_INTER); | |
| 3433 %} | |
| 3434 | |
| 3435 // Long Immediate: low 32-bit mask | |
| 3436 operand immL32() %{ | |
| 3437 predicate(n->get_long() == (int)(n->get_long())); | |
| 3438 match(ConL); | |
| 3439 op_cost(20); | |
| 3440 | |
| 3441 format %{ %} | |
| 3442 interface(CONST_INTER); | |
| 3443 %} | |
| 3444 | |
| 3445 //Double Immediate zero | |
|
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3446 operand immDPR0() %{ |
| 0 | 3447 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3448 // bug that generates code such that NaNs compare equal to 0.0 | |
| 3449 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 3450 match(ConD); | |
| 3451 | |
| 3452 op_cost(5); | |
| 3453 format %{ %} | |
| 3454 interface(CONST_INTER); | |
| 3455 %} | |
| 3456 | |
| 2008 | 3457 // Double Immediate one |
|
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|
3458 operand immDPR1() %{ |
| 0 | 3459 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 3460 match(ConD); | |
| 3461 | |
| 3462 op_cost(5); | |
| 3463 format %{ %} | |
| 3464 interface(CONST_INTER); | |
| 3465 %} | |
| 3466 | |
| 3467 // Double Immediate | |
|
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3468 operand immDPR() %{ |
| 0 | 3469 predicate(UseSSE<=1); |
| 3470 match(ConD); | |
| 3471 | |
| 3472 op_cost(5); | |
| 3473 format %{ %} | |
| 3474 interface(CONST_INTER); | |
| 3475 %} | |
| 3476 | |
|
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|
3477 operand immD() %{ |
| 0 | 3478 predicate(UseSSE>=2); |
| 3479 match(ConD); | |
| 3480 | |
| 3481 op_cost(5); | |
| 3482 format %{ %} | |
| 3483 interface(CONST_INTER); | |
| 3484 %} | |
| 3485 | |
| 3486 // Double Immediate zero | |
|
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3487 operand immD0() %{ |
| 0 | 3488 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3489 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 3490 // compare equal to -0.0. | |
| 3491 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 3492 match(ConD); | |
| 3493 | |
| 3494 format %{ %} | |
| 3495 interface(CONST_INTER); | |
| 3496 %} | |
| 3497 | |
| 3498 // Float Immediate zero | |
|
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3499 operand immFPR0() %{ |
| 2008 | 3500 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 3501 match(ConF); | |
| 3502 | |
| 3503 op_cost(5); | |
| 3504 format %{ %} | |
| 3505 interface(CONST_INTER); | |
| 3506 %} | |
| 3507 | |
| 3508 // Float Immediate one | |
|
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3509 operand immFPR1() %{ |
| 2008 | 3510 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 3511 match(ConF); |
| 3512 | |
| 3513 op_cost(5); | |
| 3514 format %{ %} | |
| 3515 interface(CONST_INTER); | |
| 3516 %} | |
| 3517 | |
| 3518 // Float Immediate | |
|
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|
3519 operand immFPR() %{ |
|
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3520 predicate( UseSSE == 0 ); |
|
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|
3521 match(ConF); |
|
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|
3522 |
|
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|
3523 op_cost(5); |
|
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|
3524 format %{ %} |
|
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|
3525 interface(CONST_INTER); |
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|
3526 %} |
|
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|
3527 |
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3528 // Float Immediate |
| 0 | 3529 operand immF() %{ |
| 3530 predicate(UseSSE >= 1); | |
| 3531 match(ConF); | |
| 3532 | |
| 3533 op_cost(5); | |
| 3534 format %{ %} | |
| 3535 interface(CONST_INTER); | |
| 3536 %} | |
| 3537 | |
| 3538 // Float Immediate zero. Zero and not -0.0 | |
|
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3539 operand immF0() %{ |
| 0 | 3540 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 3541 match(ConF); | |
| 3542 | |
| 3543 op_cost(5); | |
| 3544 format %{ %} | |
| 3545 interface(CONST_INTER); | |
| 3546 %} | |
| 3547 | |
| 3548 // Immediates for special shifts (sign extend) | |
| 3549 | |
| 3550 // Constants for increment | |
| 3551 operand immI_16() %{ | |
| 3552 predicate( n->get_int() == 16 ); | |
| 3553 match(ConI); | |
| 3554 | |
| 3555 format %{ %} | |
| 3556 interface(CONST_INTER); | |
| 3557 %} | |
| 3558 | |
| 3559 operand immI_24() %{ | |
| 3560 predicate( n->get_int() == 24 ); | |
| 3561 match(ConI); | |
| 3562 | |
| 3563 format %{ %} | |
| 3564 interface(CONST_INTER); | |
| 3565 %} | |
| 3566 | |
| 3567 // Constant for byte-wide masking | |
| 3568 operand immI_255() %{ | |
| 3569 predicate( n->get_int() == 255 ); | |
| 3570 match(ConI); | |
| 3571 | |
| 3572 format %{ %} | |
| 3573 interface(CONST_INTER); | |
| 3574 %} | |
| 3575 | |
| 785 | 3576 // Constant for short-wide masking |
| 3577 operand immI_65535() %{ | |
| 3578 predicate(n->get_int() == 65535); | |
| 3579 match(ConI); | |
| 3580 | |
| 3581 format %{ %} | |
| 3582 interface(CONST_INTER); | |
| 3583 %} | |
| 3584 | |
| 0 | 3585 // Register Operands |
| 3586 // Integer Register | |
|
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|
3587 operand rRegI() %{ |
|
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|
3588 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3589 match(RegI); |
| 3590 match(xRegI); | |
| 3591 match(eAXRegI); | |
| 3592 match(eBXRegI); | |
| 3593 match(eCXRegI); | |
| 3594 match(eDXRegI); | |
| 3595 match(eDIRegI); | |
| 3596 match(eSIRegI); | |
| 3597 | |
| 3598 format %{ %} | |
| 3599 interface(REG_INTER); | |
| 3600 %} | |
| 3601 | |
| 3602 // Subset of Integer Register | |
|
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|
3603 operand xRegI(rRegI reg) %{ |
|
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|
3604 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 3605 match(reg); |
| 3606 match(eAXRegI); | |
| 3607 match(eBXRegI); | |
| 3608 match(eCXRegI); | |
| 3609 match(eDXRegI); | |
| 3610 | |
| 3611 format %{ %} | |
| 3612 interface(REG_INTER); | |
| 3613 %} | |
| 3614 | |
| 3615 // Special Registers | |
| 3616 operand eAXRegI(xRegI reg) %{ | |
| 3617 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3618 match(reg); | |
|
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|
3619 match(rRegI); |
| 0 | 3620 |
| 3621 format %{ "EAX" %} | |
| 3622 interface(REG_INTER); | |
| 3623 %} | |
| 3624 | |
| 3625 // Special Registers | |
| 3626 operand eBXRegI(xRegI reg) %{ | |
| 3627 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3628 match(reg); | |
|
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|
3629 match(rRegI); |
| 0 | 3630 |
| 3631 format %{ "EBX" %} | |
| 3632 interface(REG_INTER); | |
| 3633 %} | |
| 3634 | |
| 3635 operand eCXRegI(xRegI reg) %{ | |
| 3636 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3637 match(reg); | |
|
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|
3638 match(rRegI); |
| 0 | 3639 |
| 3640 format %{ "ECX" %} | |
| 3641 interface(REG_INTER); | |
| 3642 %} | |
| 3643 | |
| 3644 operand eDXRegI(xRegI reg) %{ | |
| 3645 constraint(ALLOC_IN_RC(edx_reg)); | |
| 3646 match(reg); | |
|
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|
3647 match(rRegI); |
| 0 | 3648 |
| 3649 format %{ "EDX" %} | |
| 3650 interface(REG_INTER); | |
| 3651 %} | |
| 3652 | |
| 3653 operand eDIRegI(xRegI reg) %{ | |
| 3654 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3655 match(reg); | |
|
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3656 match(rRegI); |
| 0 | 3657 |
| 3658 format %{ "EDI" %} | |
| 3659 interface(REG_INTER); | |
| 3660 %} | |
| 3661 | |
| 3662 operand naxRegI() %{ | |
| 3663 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3664 match(RegI); | |
| 3665 match(eCXRegI); | |
| 3666 match(eDXRegI); | |
| 3667 match(eSIRegI); | |
| 3668 match(eDIRegI); | |
| 3669 | |
| 3670 format %{ %} | |
| 3671 interface(REG_INTER); | |
| 3672 %} | |
| 3673 | |
| 3674 operand nadxRegI() %{ | |
| 3675 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 3676 match(RegI); | |
| 3677 match(eBXRegI); | |
| 3678 match(eCXRegI); | |
| 3679 match(eSIRegI); | |
| 3680 match(eDIRegI); | |
| 3681 | |
| 3682 format %{ %} | |
| 3683 interface(REG_INTER); | |
| 3684 %} | |
| 3685 | |
| 3686 operand ncxRegI() %{ | |
| 3687 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 3688 match(RegI); | |
| 3689 match(eAXRegI); | |
| 3690 match(eDXRegI); | |
| 3691 match(eSIRegI); | |
| 3692 match(eDIRegI); | |
| 3693 | |
| 3694 format %{ %} | |
| 3695 interface(REG_INTER); | |
| 3696 %} | |
| 3697 | |
| 3698 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 3699 // // | |
| 3700 operand eSIRegI(xRegI reg) %{ | |
| 3701 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3702 match(reg); | |
|
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3703 match(rRegI); |
| 0 | 3704 |
| 3705 format %{ "ESI" %} | |
| 3706 interface(REG_INTER); | |
| 3707 %} | |
| 3708 | |
| 3709 // Pointer Register | |
| 3710 operand anyRegP() %{ | |
| 3711 constraint(ALLOC_IN_RC(any_reg)); | |
| 3712 match(RegP); | |
| 3713 match(eAXRegP); | |
| 3714 match(eBXRegP); | |
| 3715 match(eCXRegP); | |
| 3716 match(eDIRegP); | |
| 3717 match(eRegP); | |
| 3718 | |
| 3719 format %{ %} | |
| 3720 interface(REG_INTER); | |
| 3721 %} | |
| 3722 | |
| 3723 operand eRegP() %{ | |
|
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3724 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3725 match(RegP); |
| 3726 match(eAXRegP); | |
| 3727 match(eBXRegP); | |
| 3728 match(eCXRegP); | |
| 3729 match(eDIRegP); | |
| 3730 | |
| 3731 format %{ %} | |
| 3732 interface(REG_INTER); | |
| 3733 %} | |
| 3734 | |
| 3735 // On windows95, EBP is not safe to use for implicit null tests. | |
| 3736 operand eRegP_no_EBP() %{ | |
|
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3737 constraint(ALLOC_IN_RC(int_reg_no_rbp)); |
| 0 | 3738 match(RegP); |
| 3739 match(eAXRegP); | |
| 3740 match(eBXRegP); | |
| 3741 match(eCXRegP); | |
| 3742 match(eDIRegP); | |
| 3743 | |
| 3744 op_cost(100); | |
| 3745 format %{ %} | |
| 3746 interface(REG_INTER); | |
| 3747 %} | |
| 3748 | |
| 3749 operand naxRegP() %{ | |
| 3750 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3751 match(RegP); | |
| 3752 match(eBXRegP); | |
| 3753 match(eDXRegP); | |
| 3754 match(eCXRegP); | |
| 3755 match(eSIRegP); | |
| 3756 match(eDIRegP); | |
| 3757 | |
| 3758 format %{ %} | |
| 3759 interface(REG_INTER); | |
| 3760 %} | |
| 3761 | |
| 3762 operand nabxRegP() %{ | |
| 3763 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 3764 match(RegP); | |
| 3765 match(eCXRegP); | |
| 3766 match(eDXRegP); | |
| 3767 match(eSIRegP); | |
| 3768 match(eDIRegP); | |
| 3769 | |
| 3770 format %{ %} | |
| 3771 interface(REG_INTER); | |
| 3772 %} | |
| 3773 | |
| 3774 operand pRegP() %{ | |
| 3775 constraint(ALLOC_IN_RC(p_reg)); | |
| 3776 match(RegP); | |
| 3777 match(eBXRegP); | |
| 3778 match(eDXRegP); | |
| 3779 match(eSIRegP); | |
| 3780 match(eDIRegP); | |
| 3781 | |
| 3782 format %{ %} | |
| 3783 interface(REG_INTER); | |
| 3784 %} | |
| 3785 | |
| 3786 // Special Registers | |
| 3787 // Return a pointer value | |
| 3788 operand eAXRegP(eRegP reg) %{ | |
| 3789 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3790 match(reg); | |
| 3791 format %{ "EAX" %} | |
| 3792 interface(REG_INTER); | |
| 3793 %} | |
| 3794 | |
| 3795 // Used in AtomicAdd | |
| 3796 operand eBXRegP(eRegP reg) %{ | |
| 3797 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3798 match(reg); | |
| 3799 format %{ "EBX" %} | |
| 3800 interface(REG_INTER); | |
| 3801 %} | |
| 3802 | |
| 3803 // Tail-call (interprocedural jump) to interpreter | |
| 3804 operand eCXRegP(eRegP reg) %{ | |
| 3805 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3806 match(reg); | |
| 3807 format %{ "ECX" %} | |
| 3808 interface(REG_INTER); | |
| 3809 %} | |
| 3810 | |
| 3811 operand eSIRegP(eRegP reg) %{ | |
| 3812 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3813 match(reg); | |
| 3814 format %{ "ESI" %} | |
| 3815 interface(REG_INTER); | |
| 3816 %} | |
| 3817 | |
| 3818 // Used in rep stosw | |
| 3819 operand eDIRegP(eRegP reg) %{ | |
| 3820 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3821 match(reg); | |
| 3822 format %{ "EDI" %} | |
| 3823 interface(REG_INTER); | |
| 3824 %} | |
| 3825 | |
| 3826 operand eBPRegP() %{ | |
| 3827 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 3828 match(RegP); | |
| 3829 format %{ "EBP" %} | |
| 3830 interface(REG_INTER); | |
| 3831 %} | |
| 3832 | |
| 3833 operand eRegL() %{ | |
| 3834 constraint(ALLOC_IN_RC(long_reg)); | |
| 3835 match(RegL); | |
| 3836 match(eADXRegL); | |
| 3837 | |
| 3838 format %{ %} | |
| 3839 interface(REG_INTER); | |
| 3840 %} | |
| 3841 | |
| 3842 operand eADXRegL( eRegL reg ) %{ | |
| 3843 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3844 match(reg); | |
| 3845 | |
| 3846 format %{ "EDX:EAX" %} | |
| 3847 interface(REG_INTER); | |
| 3848 %} | |
| 3849 | |
| 3850 operand eBCXRegL( eRegL reg ) %{ | |
| 3851 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 3852 match(reg); | |
| 3853 | |
| 3854 format %{ "EBX:ECX" %} | |
| 3855 interface(REG_INTER); | |
| 3856 %} | |
| 3857 | |
| 3858 // Special case for integer high multiply | |
| 3859 operand eADXRegL_low_only() %{ | |
| 3860 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3861 match(RegL); | |
| 3862 | |
| 3863 format %{ "EAX" %} | |
| 3864 interface(REG_INTER); | |
| 3865 %} | |
| 3866 | |
| 3867 // Flags register, used as output of compare instructions | |
| 3868 operand eFlagsReg() %{ | |
| 3869 constraint(ALLOC_IN_RC(int_flags)); | |
| 3870 match(RegFlags); | |
| 3871 | |
| 3872 format %{ "EFLAGS" %} | |
| 3873 interface(REG_INTER); | |
| 3874 %} | |
| 3875 | |
| 3876 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3877 operand eFlagsRegU() %{ | |
| 3878 constraint(ALLOC_IN_RC(int_flags)); | |
| 3879 match(RegFlags); | |
| 3880 | |
| 3881 format %{ "EFLAGS_U" %} | |
| 3882 interface(REG_INTER); | |
| 3883 %} | |
| 3884 | |
|
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|
3885 operand eFlagsRegUCF() %{ |
|
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|
3886 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3887 match(RegFlags); |
|
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|
3888 predicate(false); |
|
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|
3889 |
|
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|
3890 format %{ "EFLAGS_U_CF" %} |
|
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|
3891 interface(REG_INTER); |
|
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|
3892 %} |
|
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|
3893 |
| 0 | 3894 // Condition Code Register used by long compare |
| 3895 operand flagsReg_long_LTGE() %{ | |
| 3896 constraint(ALLOC_IN_RC(int_flags)); | |
| 3897 match(RegFlags); | |
| 3898 format %{ "FLAGS_LTGE" %} | |
| 3899 interface(REG_INTER); | |
| 3900 %} | |
| 3901 operand flagsReg_long_EQNE() %{ | |
| 3902 constraint(ALLOC_IN_RC(int_flags)); | |
| 3903 match(RegFlags); | |
| 3904 format %{ "FLAGS_EQNE" %} | |
| 3905 interface(REG_INTER); | |
| 3906 %} | |
| 3907 operand flagsReg_long_LEGT() %{ | |
| 3908 constraint(ALLOC_IN_RC(int_flags)); | |
| 3909 match(RegFlags); | |
| 3910 format %{ "FLAGS_LEGT" %} | |
| 3911 interface(REG_INTER); | |
| 3912 %} | |
| 3913 | |
| 3914 // Float register operands | |
|
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|
3915 operand regDPR() %{ |
| 0 | 3916 predicate( UseSSE < 2 ); |
|
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|
3917 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 3918 match(RegD); |
| 3919 match(regDPR1); | |
| 3920 match(regDPR2); | |
| 3921 format %{ %} | |
| 3922 interface(REG_INTER); | |
| 3923 %} | |
| 3924 | |
|
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|
3925 operand regDPR1(regDPR reg) %{ |
| 0 | 3926 predicate( UseSSE < 2 ); |
|
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|
3927 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 3928 match(reg); |
| 3929 format %{ "FPR1" %} | |
| 3930 interface(REG_INTER); | |
| 3931 %} | |
| 3932 | |
|
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|
3933 operand regDPR2(regDPR reg) %{ |
| 0 | 3934 predicate( UseSSE < 2 ); |
|
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|
3935 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 3936 match(reg); |
| 3937 format %{ "FPR2" %} | |
| 3938 interface(REG_INTER); | |
| 3939 %} | |
| 3940 | |
|
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|
3941 operand regnotDPR1(regDPR reg) %{ |
| 0 | 3942 predicate( UseSSE < 2 ); |
|
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|
3943 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 3944 match(reg); |
| 3945 format %{ %} | |
| 3946 interface(REG_INTER); | |
| 3947 %} | |
| 3948 | |
| 3949 // Float register operands | |
|
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3950 operand regFPR() %{ |
| 0 | 3951 predicate( UseSSE < 2 ); |
|
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|
3952 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 3953 match(RegF); |
| 3954 match(regFPR1); | |
| 3955 format %{ %} | |
| 3956 interface(REG_INTER); | |
| 3957 %} | |
| 3958 | |
| 3959 // Float register operands | |
|
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3960 operand regFPR1(regFPR reg) %{ |
| 0 | 3961 predicate( UseSSE < 2 ); |
|
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|
3962 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 3963 match(reg); |
| 3964 format %{ "FPR1" %} | |
| 3965 interface(REG_INTER); | |
| 3966 %} | |
| 3967 | |
|
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|
3968 // XMM Float register operands |
|
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3969 operand regF() %{ |
| 0 | 3970 predicate( UseSSE>=1 ); |
|
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|
3971 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 3972 match(RegF); |
| 3973 format %{ %} | |
| 3974 interface(REG_INTER); | |
| 3975 %} | |
| 3976 | |
|
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|
3977 // XMM Double register operands |
|
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|
3978 operand regD() %{ |
|
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|
3979 predicate( UseSSE>=2 ); |
|
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|
3980 constraint(ALLOC_IN_RC(double_reg)); |
|
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|
3981 match(RegD); |
|
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|
3982 format %{ %} |
|
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|
3983 interface(REG_INTER); |
|
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|
3984 %} |
|
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|
3985 |
| 0 | 3986 |
| 3987 //----------Memory Operands---------------------------------------------------- | |
| 3988 // Direct Memory Operand | |
| 3989 operand direct(immP addr) %{ | |
| 3990 match(addr); | |
| 3991 | |
| 3992 format %{ "[$addr]" %} | |
| 3993 interface(MEMORY_INTER) %{ | |
| 3994 base(0xFFFFFFFF); | |
| 3995 index(0x4); | |
| 3996 scale(0x0); | |
| 3997 disp($addr); | |
| 3998 %} | |
| 3999 %} | |
| 4000 | |
| 4001 // Indirect Memory Operand | |
| 4002 operand indirect(eRegP reg) %{ | |
|
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|
4003 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4004 match(reg); |
| 4005 | |
| 4006 format %{ "[$reg]" %} | |
| 4007 interface(MEMORY_INTER) %{ | |
| 4008 base($reg); | |
| 4009 index(0x4); | |
| 4010 scale(0x0); | |
| 4011 disp(0x0); | |
| 4012 %} | |
| 4013 %} | |
| 4014 | |
| 4015 // Indirect Memory Plus Short Offset Operand | |
| 4016 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4017 match(AddP reg off); | |
| 4018 | |
| 4019 format %{ "[$reg + $off]" %} | |
| 4020 interface(MEMORY_INTER) %{ | |
| 4021 base($reg); | |
| 4022 index(0x4); | |
| 4023 scale(0x0); | |
| 4024 disp($off); | |
| 4025 %} | |
| 4026 %} | |
| 4027 | |
| 4028 // Indirect Memory Plus Long Offset Operand | |
| 4029 operand indOffset32(eRegP reg, immI off) %{ | |
| 4030 match(AddP reg off); | |
| 4031 | |
| 4032 format %{ "[$reg + $off]" %} | |
| 4033 interface(MEMORY_INTER) %{ | |
| 4034 base($reg); | |
| 4035 index(0x4); | |
| 4036 scale(0x0); | |
| 4037 disp($off); | |
| 4038 %} | |
| 4039 %} | |
| 4040 | |
| 4041 // Indirect Memory Plus Long Offset Operand | |
|
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|
4042 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4043 match(AddP off reg); |
| 4044 | |
| 4045 format %{ "[$reg + $off]" %} | |
| 4046 interface(MEMORY_INTER) %{ | |
| 4047 base($reg); | |
| 4048 index(0x4); | |
| 4049 scale(0x0); | |
| 4050 disp($off); | |
| 4051 %} | |
| 4052 %} | |
| 4053 | |
| 4054 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4055 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4056 match(AddP (AddP reg ireg) off); |
| 4057 | |
| 4058 op_cost(10); | |
| 4059 format %{"[$reg + $off + $ireg]" %} | |
| 4060 interface(MEMORY_INTER) %{ | |
| 4061 base($reg); | |
| 4062 index($ireg); | |
| 4063 scale(0x0); | |
| 4064 disp($off); | |
| 4065 %} | |
| 4066 %} | |
| 4067 | |
| 4068 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4069 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4070 match(AddP reg ireg); |
| 4071 | |
| 4072 op_cost(10); | |
| 4073 format %{"[$reg + $ireg]" %} | |
| 4074 interface(MEMORY_INTER) %{ | |
| 4075 base($reg); | |
| 4076 index($ireg); | |
| 4077 scale(0x0); | |
| 4078 disp(0x0); | |
| 4079 %} | |
| 4080 %} | |
| 4081 | |
| 4082 // // ------------------------------------------------------------------------- | |
| 4083 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4084 // // ------------------------------------------------------------------------- | |
| 4085 // // Scaled Memory Operands | |
| 4086 // // Indirect Memory Times Scale Plus Offset Operand | |
|
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|
4087 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4088 // match(AddP off (LShiftI ireg scale)); |
| 4089 // | |
| 4090 // op_cost(10); | |
| 4091 // format %{"[$off + $ireg << $scale]" %} | |
| 4092 // interface(MEMORY_INTER) %{ | |
| 4093 // base(0x4); | |
| 4094 // index($ireg); | |
| 4095 // scale($scale); | |
| 4096 // disp($off); | |
| 4097 // %} | |
| 4098 // %} | |
| 4099 | |
| 4100 // Indirect Memory Times Scale Plus Index Register | |
|
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|
4101 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4102 match(AddP reg (LShiftI ireg scale)); |
| 4103 | |
| 4104 op_cost(10); | |
| 4105 format %{"[$reg + $ireg << $scale]" %} | |
| 4106 interface(MEMORY_INTER) %{ | |
| 4107 base($reg); | |
| 4108 index($ireg); | |
| 4109 scale($scale); | |
| 4110 disp(0x0); | |
| 4111 %} | |
| 4112 %} | |
| 4113 | |
| 4114 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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|
4115 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4116 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4117 | |
| 4118 op_cost(10); | |
| 4119 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4120 interface(MEMORY_INTER) %{ | |
| 4121 base($reg); | |
| 4122 index($ireg); | |
| 4123 scale($scale); | |
| 4124 disp($off); | |
| 4125 %} | |
| 4126 %} | |
| 4127 | |
| 4128 //----------Load Long Memory Operands------------------------------------------ | |
| 4129 // The load-long idiom will use it's address expression again after loading | |
| 4130 // the first word of the long. If the load-long destination overlaps with | |
| 4131 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4132 // from a clobbered address. Fix this by requiring that load-long use | |
| 4133 // address registers that do not overlap with the load-long target. | |
| 4134 | |
| 4135 // load-long support | |
| 4136 operand load_long_RegP() %{ | |
| 4137 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4138 match(RegP); | |
| 4139 match(eSIRegP); | |
| 4140 op_cost(100); | |
| 4141 format %{ %} | |
| 4142 interface(REG_INTER); | |
| 4143 %} | |
| 4144 | |
| 4145 // Indirect Memory Operand Long | |
| 4146 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4147 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4148 match(reg); | |
| 4149 | |
| 4150 format %{ "[$reg]" %} | |
| 4151 interface(MEMORY_INTER) %{ | |
| 4152 base($reg); | |
| 4153 index(0x4); | |
| 4154 scale(0x0); | |
| 4155 disp(0x0); | |
| 4156 %} | |
| 4157 %} | |
| 4158 | |
| 4159 // Indirect Memory Plus Long Offset Operand | |
| 4160 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4161 match(AddP reg off); | |
| 4162 | |
| 4163 format %{ "[$reg + $off]" %} | |
| 4164 interface(MEMORY_INTER) %{ | |
| 4165 base($reg); | |
| 4166 index(0x4); | |
| 4167 scale(0x0); | |
| 4168 disp($off); | |
| 4169 %} | |
| 4170 %} | |
| 4171 | |
| 4172 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4173 | |
| 4174 | |
| 4175 //----------Special Memory Operands-------------------------------------------- | |
| 4176 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4177 // values on the stack where a match requires a value to | |
| 4178 // flow through memory. | |
| 4179 operand stackSlotP(sRegP reg) %{ | |
| 4180 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4181 // No match rule because this operand is only generated in matching | |
| 4182 format %{ "[$reg]" %} | |
| 4183 interface(MEMORY_INTER) %{ | |
| 4184 base(0x4); // ESP | |
| 4185 index(0x4); // No Index | |
| 4186 scale(0x0); // No Scale | |
| 4187 disp($reg); // Stack Offset | |
| 4188 %} | |
| 4189 %} | |
| 4190 | |
| 4191 operand stackSlotI(sRegI reg) %{ | |
| 4192 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4193 // No match rule because this operand is only generated in matching | |
| 4194 format %{ "[$reg]" %} | |
| 4195 interface(MEMORY_INTER) %{ | |
| 4196 base(0x4); // ESP | |
| 4197 index(0x4); // No Index | |
| 4198 scale(0x0); // No Scale | |
| 4199 disp($reg); // Stack Offset | |
| 4200 %} | |
| 4201 %} | |
| 4202 | |
| 4203 operand stackSlotF(sRegF reg) %{ | |
| 4204 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4205 // No match rule because this operand is only generated in matching | |
| 4206 format %{ "[$reg]" %} | |
| 4207 interface(MEMORY_INTER) %{ | |
| 4208 base(0x4); // ESP | |
| 4209 index(0x4); // No Index | |
| 4210 scale(0x0); // No Scale | |
| 4211 disp($reg); // Stack Offset | |
| 4212 %} | |
| 4213 %} | |
| 4214 | |
| 4215 operand stackSlotD(sRegD reg) %{ | |
| 4216 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4217 // No match rule because this operand is only generated in matching | |
| 4218 format %{ "[$reg]" %} | |
| 4219 interface(MEMORY_INTER) %{ | |
| 4220 base(0x4); // ESP | |
| 4221 index(0x4); // No Index | |
| 4222 scale(0x0); // No Scale | |
| 4223 disp($reg); // Stack Offset | |
| 4224 %} | |
| 4225 %} | |
| 4226 | |
| 4227 operand stackSlotL(sRegL reg) %{ | |
| 4228 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4229 // No match rule because this operand is only generated in matching | |
| 4230 format %{ "[$reg]" %} | |
| 4231 interface(MEMORY_INTER) %{ | |
| 4232 base(0x4); // ESP | |
| 4233 index(0x4); // No Index | |
| 4234 scale(0x0); // No Scale | |
| 4235 disp($reg); // Stack Offset | |
| 4236 %} | |
| 4237 %} | |
| 4238 | |
| 4239 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4240 // Indirect Memory Operand | |
| 4241 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4242 %{ | |
|
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4243 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4244 match(reg); |
| 4245 | |
| 4246 op_cost(100); | |
| 4247 format %{ "[$reg]" %} | |
| 4248 interface(MEMORY_INTER) %{ | |
| 4249 base($reg); | |
| 4250 index(0x4); | |
| 4251 scale(0x0); | |
| 4252 disp(0x0); | |
| 4253 %} | |
| 4254 %} | |
| 4255 | |
| 4256 // Indirect Memory Plus Short Offset Operand | |
| 4257 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4258 %{ | |
| 4259 match(AddP reg off); | |
| 4260 | |
| 4261 op_cost(100); | |
| 4262 format %{ "[$reg + $off]" %} | |
| 4263 interface(MEMORY_INTER) %{ | |
| 4264 base($reg); | |
| 4265 index(0x4); | |
| 4266 scale(0x0); | |
| 4267 disp($off); | |
| 4268 %} | |
| 4269 %} | |
| 4270 | |
| 4271 // Indirect Memory Plus Long Offset Operand | |
| 4272 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4273 %{ | |
| 4274 match(AddP reg off); | |
| 4275 | |
| 4276 op_cost(100); | |
| 4277 format %{ "[$reg + $off]" %} | |
| 4278 interface(MEMORY_INTER) %{ | |
| 4279 base($reg); | |
| 4280 index(0x4); | |
| 4281 scale(0x0); | |
| 4282 disp($off); | |
| 4283 %} | |
| 4284 %} | |
| 4285 | |
| 4286 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4287 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4288 %{ |
| 4289 match(AddP (AddP reg ireg) off); | |
| 4290 | |
| 4291 op_cost(100); | |
| 4292 format %{"[$reg + $off + $ireg]" %} | |
| 4293 interface(MEMORY_INTER) %{ | |
| 4294 base($reg); | |
| 4295 index($ireg); | |
| 4296 scale(0x0); | |
| 4297 disp($off); | |
| 4298 %} | |
| 4299 %} | |
| 4300 | |
| 4301 // Indirect Memory Times Scale Plus Index Register | |
|
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4302 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4303 %{ |
| 4304 match(AddP reg (LShiftI ireg scale)); | |
| 4305 | |
| 4306 op_cost(100); | |
| 4307 format %{"[$reg + $ireg << $scale]" %} | |
| 4308 interface(MEMORY_INTER) %{ | |
| 4309 base($reg); | |
| 4310 index($ireg); | |
| 4311 scale($scale); | |
| 4312 disp(0x0); | |
| 4313 %} | |
| 4314 %} | |
| 4315 | |
| 4316 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4317 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4318 %{ |
| 4319 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4320 | |
| 4321 op_cost(100); | |
| 4322 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4323 interface(MEMORY_INTER) %{ | |
| 4324 base($reg); | |
| 4325 index($ireg); | |
| 4326 scale($scale); | |
| 4327 disp($off); | |
| 4328 %} | |
| 4329 %} | |
| 4330 | |
| 4331 //----------Conditional Branch Operands---------------------------------------- | |
| 4332 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4333 // the following set of codes: | |
| 4334 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4335 // | |
| 4336 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4337 // by the comparison instruction that sets a condition code flags register. | |
| 4338 // That result is represented by a flags operand whose subtype is appropriate | |
| 4339 // to the unsignedness (etc.) of the comparison. | |
| 4340 // | |
| 4341 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4342 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4343 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4344 | |
| 4345 // Comparision Code | |
| 4346 operand cmpOp() %{ | |
| 4347 match(Bool); | |
| 4348 | |
| 4349 format %{ "" %} | |
| 4350 interface(COND_INTER) %{ | |
|
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4351 equal(0x4, "e"); |
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|
4352 not_equal(0x5, "ne"); |
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|
4353 less(0xC, "l"); |
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4354 greater_equal(0xD, "ge"); |
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|
4355 less_equal(0xE, "le"); |
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|
4356 greater(0xF, "g"); |
| 12323 | 4357 overflow(0x0, "o"); |
| 4358 no_overflow(0x1, "no"); | |
| 0 | 4359 %} |
| 4360 %} | |
| 4361 | |
| 4362 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4363 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4364 // C0 and C3 are turned into Carry & Zero flags. | |
| 4365 operand cmpOpU() %{ | |
| 4366 match(Bool); | |
| 4367 | |
| 4368 format %{ "" %} | |
| 4369 interface(COND_INTER) %{ | |
|
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|
4370 equal(0x4, "e"); |
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|
4371 not_equal(0x5, "ne"); |
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|
4372 less(0x2, "b"); |
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4373 greater_equal(0x3, "nb"); |
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|
4374 less_equal(0x6, "be"); |
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|
4375 greater(0x7, "nbe"); |
| 12323 | 4376 overflow(0x0, "o"); |
| 4377 no_overflow(0x1, "no"); | |
|
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4378 %} |
|
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|
4379 %} |
|
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|
4380 |
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|
4381 // Floating comparisons that don't require any fixup for the unordered case |
|
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4382 operand cmpOpUCF() %{ |
|
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|
4383 match(Bool); |
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|
4384 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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|
4385 n->as_Bool()->_test._test == BoolTest::ge || |
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4386 n->as_Bool()->_test._test == BoolTest::le || |
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4387 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
4388 format %{ "" %} |
|
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|
4389 interface(COND_INTER) %{ |
|
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|
4390 equal(0x4, "e"); |
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|
4391 not_equal(0x5, "ne"); |
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|
4392 less(0x2, "b"); |
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|
4393 greater_equal(0x3, "nb"); |
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|
4394 less_equal(0x6, "be"); |
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|
4395 greater(0x7, "nbe"); |
| 12323 | 4396 overflow(0x0, "o"); |
| 4397 no_overflow(0x1, "no"); | |
|
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|
4398 %} |
|
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|
4399 %} |
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|
4400 |
|
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|
4401 |
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|
4402 // Floating comparisons that can be fixed up with extra conditional jumps |
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|
4403 operand cmpOpUCF2() %{ |
|
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|
4404 match(Bool); |
|
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|
4405 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
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|
4406 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4407 format %{ "" %} |
|
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|
4408 interface(COND_INTER) %{ |
|
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|
4409 equal(0x4, "e"); |
|
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|
4410 not_equal(0x5, "ne"); |
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|
4411 less(0x2, "b"); |
|
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|
4412 greater_equal(0x3, "nb"); |
|
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|
4413 less_equal(0x6, "be"); |
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|
4414 greater(0x7, "nbe"); |
| 12323 | 4415 overflow(0x0, "o"); |
| 4416 no_overflow(0x1, "no"); | |
| 0 | 4417 %} |
| 4418 %} | |
| 4419 | |
| 4420 // Comparison Code for FP conditional move | |
| 4421 operand cmpOp_fcmov() %{ | |
| 4422 match(Bool); | |
| 4423 | |
| 12323 | 4424 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4425 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4426 format %{ "" %} |
| 4427 interface(COND_INTER) %{ | |
| 4428 equal (0x0C8); | |
| 4429 not_equal (0x1C8); | |
| 4430 less (0x0C0); | |
| 4431 greater_equal(0x1C0); | |
| 4432 less_equal (0x0D0); | |
| 4433 greater (0x1D0); | |
| 12323 | 4434 overflow(0x0, "o"); // not really supported by the instruction |
| 4435 no_overflow(0x1, "no"); // not really supported by the instruction | |
| 0 | 4436 %} |
| 4437 %} | |
| 4438 | |
| 4439 // Comparision Code used in long compares | |
| 4440 operand cmpOp_commute() %{ | |
| 4441 match(Bool); | |
| 4442 | |
| 4443 format %{ "" %} | |
| 4444 interface(COND_INTER) %{ | |
|
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|
4445 equal(0x4, "e"); |
|
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changeset
|
4446 not_equal(0x5, "ne"); |
|
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|
4447 less(0xF, "g"); |
|
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|
4448 greater_equal(0xE, "le"); |
|
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|
4449 less_equal(0xD, "ge"); |
|
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|
4450 greater(0xC, "l"); |
| 12323 | 4451 overflow(0x0, "o"); |
| 4452 no_overflow(0x1, "no"); | |
| 0 | 4453 %} |
| 4454 %} | |
| 4455 | |
| 4456 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4457 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4458 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4459 // instructions for every form of operand when the instruction accepts |
| 4460 // multiple operand types with the same basic encoding and format. The classic | |
| 4461 // case of this is memory operands. | |
| 4462 | |
| 4463 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 4464 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4465 | |
| 4466 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 4467 // This means some kind of offset is always required and you cannot use | |
| 4468 // an oop as the offset (done when working on static globals). | |
| 4469 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 4470 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4471 | |
| 4472 | |
| 4473 //----------PIPELINE----------------------------------------------------------- | |
| 4474 // Rules which define the behavior of the target architectures pipeline. | |
| 4475 pipeline %{ | |
| 4476 | |
| 4477 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4478 attributes %{ | |
| 4479 variable_size_instructions; // Fixed size instructions | |
| 4480 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4481 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4482 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4483 instruction_fetch_units = 1; // of 16 bytes | |
| 4484 | |
| 4485 // List of nop instructions | |
| 4486 nops( MachNop ); | |
| 4487 %} | |
| 4488 | |
| 4489 //----------RESOURCES---------------------------------------------------------- | |
| 4490 // Resources are the functional units available to the machine | |
| 4491 | |
| 4492 // Generic P2/P3 pipeline | |
| 4493 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4494 // 3 instructions decoded per cycle. | |
| 4495 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4496 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 4497 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4498 MS0, MS1, MEM = MS0 | MS1, | |
| 4499 BR, FPU, | |
| 4500 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 4501 | |
| 4502 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4503 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4504 | |
| 4505 // Generic P2/P3 pipeline | |
| 4506 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4507 | |
| 4508 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4509 // Pipeline Classes describe the stages in which input and output are | |
| 4510 // referenced by the hardware pipeline. | |
| 4511 | |
| 4512 // Naming convention: ialu or fpu | |
| 4513 // Then: _reg | |
| 4514 // Then: _reg if there is a 2nd register | |
| 4515 // Then: _long if it's a pair of instructions implementing a long | |
| 4516 // Then: _fat if it requires the big decoder | |
| 4517 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4518 | |
| 4519 // Integer ALU reg operation | |
|
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4520 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 4521 single_instruction; |
| 4522 dst : S4(write); | |
| 4523 dst : S3(read); | |
| 4524 DECODE : S0; // any decoder | |
| 4525 ALU : S3; // any alu | |
| 4526 %} | |
| 4527 | |
| 4528 // Long ALU reg operation | |
| 4529 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 4530 instruction_count(2); | |
| 4531 dst : S4(write); | |
| 4532 dst : S3(read); | |
| 4533 DECODE : S0(2); // any 2 decoders | |
| 4534 ALU : S3(2); // both alus | |
| 4535 %} | |
| 4536 | |
| 4537 // Integer ALU reg operation using big decoder | |
|
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|
4538 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 4539 single_instruction; |
| 4540 dst : S4(write); | |
| 4541 dst : S3(read); | |
| 4542 D0 : S0; // big decoder only | |
| 4543 ALU : S3; // any alu | |
| 4544 %} | |
| 4545 | |
| 4546 // Long ALU reg operation using big decoder | |
| 4547 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 4548 instruction_count(2); | |
| 4549 dst : S4(write); | |
| 4550 dst : S3(read); | |
| 4551 D0 : S0(2); // big decoder only; twice | |
| 4552 ALU : S3(2); // any 2 alus | |
| 4553 %} | |
| 4554 | |
| 4555 // Integer ALU reg-reg operation | |
|
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|
4556 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 4557 single_instruction; |
| 4558 dst : S4(write); | |
| 4559 src : S3(read); | |
| 4560 DECODE : S0; // any decoder | |
| 4561 ALU : S3; // any alu | |
| 4562 %} | |
| 4563 | |
| 4564 // Long ALU reg-reg operation | |
| 4565 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 4566 instruction_count(2); | |
| 4567 dst : S4(write); | |
| 4568 src : S3(read); | |
| 4569 DECODE : S0(2); // any 2 decoders | |
| 4570 ALU : S3(2); // both alus | |
| 4571 %} | |
| 4572 | |
| 4573 // Integer ALU reg-reg operation | |
|
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4574 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 4575 single_instruction; |
| 4576 dst : S4(write); | |
| 4577 src : S3(read); | |
| 4578 D0 : S0; // big decoder only | |
| 4579 ALU : S3; // any alu | |
| 4580 %} | |
| 4581 | |
| 4582 // Long ALU reg-reg operation | |
| 4583 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 4584 instruction_count(2); | |
| 4585 dst : S4(write); | |
| 4586 src : S3(read); | |
| 4587 D0 : S0(2); // big decoder only; twice | |
| 4588 ALU : S3(2); // both alus | |
| 4589 %} | |
| 4590 | |
| 4591 // Integer ALU reg-mem operation | |
|
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4592 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 4593 single_instruction; |
| 4594 dst : S5(write); | |
| 4595 mem : S3(read); | |
| 4596 D0 : S0; // big decoder only | |
| 4597 ALU : S4; // any alu | |
| 4598 MEM : S3; // any mem | |
| 4599 %} | |
| 4600 | |
| 4601 // Long ALU reg-mem operation | |
| 4602 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 4603 instruction_count(2); | |
| 4604 dst : S5(write); | |
| 4605 mem : S3(read); | |
| 4606 D0 : S0(2); // big decoder only; twice | |
| 4607 ALU : S4(2); // any 2 alus | |
| 4608 MEM : S3(2); // both mems | |
| 4609 %} | |
| 4610 | |
| 4611 // Integer mem operation (prefetch) | |
| 4612 pipe_class ialu_mem(memory mem) | |
| 4613 %{ | |
| 4614 single_instruction; | |
| 4615 mem : S3(read); | |
| 4616 D0 : S0; // big decoder only | |
| 4617 MEM : S3; // any mem | |
| 4618 %} | |
| 4619 | |
| 4620 // Integer Store to Memory | |
|
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4621 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 4622 single_instruction; |
| 4623 mem : S3(read); | |
| 4624 src : S5(read); | |
| 4625 D0 : S0; // big decoder only | |
| 4626 ALU : S4; // any alu | |
| 4627 MEM : S3; | |
| 4628 %} | |
| 4629 | |
| 4630 // Long Store to Memory | |
| 4631 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 4632 instruction_count(2); | |
| 4633 mem : S3(read); | |
| 4634 src : S5(read); | |
| 4635 D0 : S0(2); // big decoder only; twice | |
| 4636 ALU : S4(2); // any 2 alus | |
| 4637 MEM : S3(2); // Both mems | |
| 4638 %} | |
| 4639 | |
| 4640 // Integer Store to Memory | |
| 4641 pipe_class ialu_mem_imm(memory mem) %{ | |
| 4642 single_instruction; | |
| 4643 mem : S3(read); | |
| 4644 D0 : S0; // big decoder only | |
| 4645 ALU : S4; // any alu | |
| 4646 MEM : S3; | |
| 4647 %} | |
| 4648 | |
| 4649 // Integer ALU0 reg-reg operation | |
|
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4650 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 4651 single_instruction; |
| 4652 dst : S4(write); | |
| 4653 src : S3(read); | |
| 4654 D0 : S0; // Big decoder only | |
| 4655 ALU0 : S3; // only alu0 | |
| 4656 %} | |
| 4657 | |
| 4658 // Integer ALU0 reg-mem operation | |
|
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4659 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 4660 single_instruction; |
| 4661 dst : S5(write); | |
| 4662 mem : S3(read); | |
| 4663 D0 : S0; // big decoder only | |
| 4664 ALU0 : S4; // ALU0 only | |
| 4665 MEM : S3; // any mem | |
| 4666 %} | |
| 4667 | |
| 4668 // Integer ALU reg-reg operation | |
|
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4669 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 4670 single_instruction; |
| 4671 cr : S4(write); | |
| 4672 src1 : S3(read); | |
| 4673 src2 : S3(read); | |
| 4674 DECODE : S0; // any decoder | |
| 4675 ALU : S3; // any alu | |
| 4676 %} | |
| 4677 | |
| 4678 // Integer ALU reg-imm operation | |
|
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4679 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 4680 single_instruction; |
| 4681 cr : S4(write); | |
| 4682 src1 : S3(read); | |
| 4683 DECODE : S0; // any decoder | |
| 4684 ALU : S3; // any alu | |
| 4685 %} | |
| 4686 | |
| 4687 // Integer ALU reg-mem operation | |
|
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4688 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 4689 single_instruction; |
| 4690 cr : S4(write); | |
| 4691 src1 : S3(read); | |
| 4692 src2 : S3(read); | |
| 4693 D0 : S0; // big decoder only | |
| 4694 ALU : S4; // any alu | |
| 4695 MEM : S3; | |
| 4696 %} | |
| 4697 | |
| 4698 // Conditional move reg-reg | |
|
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4699 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 4700 instruction_count(4); |
| 4701 y : S4(read); | |
| 4702 q : S3(read); | |
| 4703 p : S3(read); | |
| 4704 DECODE : S0(4); // any decoder | |
| 4705 %} | |
| 4706 | |
| 4707 // Conditional move reg-reg | |
|
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4708 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 4709 single_instruction; |
| 4710 dst : S4(write); | |
| 4711 src : S3(read); | |
| 4712 cr : S3(read); | |
| 4713 DECODE : S0; // any decoder | |
| 4714 %} | |
| 4715 | |
| 4716 // Conditional move reg-mem | |
|
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4717 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 4718 single_instruction; |
| 4719 dst : S4(write); | |
| 4720 src : S3(read); | |
| 4721 cr : S3(read); | |
| 4722 DECODE : S0; // any decoder | |
| 4723 MEM : S3; | |
| 4724 %} | |
| 4725 | |
| 4726 // Conditional move reg-reg long | |
| 4727 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 4728 single_instruction; | |
| 4729 dst : S4(write); | |
| 4730 src : S3(read); | |
| 4731 cr : S3(read); | |
| 4732 DECODE : S0(2); // any 2 decoders | |
| 4733 %} | |
| 4734 | |
| 4735 // Conditional move double reg-reg | |
|
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4736 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 4737 single_instruction; |
| 4738 dst : S4(write); | |
| 4739 src : S3(read); | |
| 4740 cr : S3(read); | |
| 4741 DECODE : S0; // any decoder | |
| 4742 %} | |
| 4743 | |
| 4744 // Float reg-reg operation | |
|
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4745 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 4746 instruction_count(2); |
| 4747 dst : S3(read); | |
| 4748 DECODE : S0(2); // any 2 decoders | |
| 4749 FPU : S3; | |
| 4750 %} | |
| 4751 | |
| 4752 // Float reg-reg operation | |
|
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4753 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 4754 instruction_count(2); |
| 4755 dst : S4(write); | |
| 4756 src : S3(read); | |
| 4757 DECODE : S0(2); // any 2 decoders | |
| 4758 FPU : S3; | |
| 4759 %} | |
| 4760 | |
| 4761 // Float reg-reg operation | |
|
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4762 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 4763 instruction_count(3); |
| 4764 dst : S4(write); | |
| 4765 src1 : S3(read); | |
| 4766 src2 : S3(read); | |
| 4767 DECODE : S0(3); // any 3 decoders | |
| 4768 FPU : S3(2); | |
| 4769 %} | |
| 4770 | |
| 4771 // Float reg-reg operation | |
|
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4772 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 4773 instruction_count(4); |
| 4774 dst : S4(write); | |
| 4775 src1 : S3(read); | |
| 4776 src2 : S3(read); | |
| 4777 src3 : S3(read); | |
| 4778 DECODE : S0(4); // any 3 decoders | |
| 4779 FPU : S3(2); | |
| 4780 %} | |
| 4781 | |
| 4782 // Float reg-reg operation | |
|
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4783 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 4784 instruction_count(4); |
| 4785 dst : S4(write); | |
| 4786 src1 : S3(read); | |
| 4787 src2 : S3(read); | |
| 4788 src3 : S3(read); | |
| 4789 DECODE : S1(3); // any 3 decoders | |
| 4790 D0 : S0; // Big decoder only | |
| 4791 FPU : S3(2); | |
| 4792 MEM : S3; | |
| 4793 %} | |
| 4794 | |
| 4795 // Float reg-mem operation | |
|
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4796 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 4797 instruction_count(2); |
| 4798 dst : S5(write); | |
| 4799 mem : S3(read); | |
| 4800 D0 : S0; // big decoder only | |
| 4801 DECODE : S1; // any decoder for FPU POP | |
| 4802 FPU : S4; | |
| 4803 MEM : S3; // any mem | |
| 4804 %} | |
| 4805 | |
| 4806 // Float reg-mem operation | |
|
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4807 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 4808 instruction_count(3); |
| 4809 dst : S5(write); | |
| 4810 src1 : S3(read); | |
| 4811 mem : S3(read); | |
| 4812 D0 : S0; // big decoder only | |
| 4813 DECODE : S1(2); // any decoder for FPU POP | |
| 4814 FPU : S4; | |
| 4815 MEM : S3; // any mem | |
| 4816 %} | |
| 4817 | |
| 4818 // Float mem-reg operation | |
|
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4819 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 4820 instruction_count(2); |
| 4821 src : S5(read); | |
| 4822 mem : S3(read); | |
| 4823 DECODE : S0; // any decoder for FPU PUSH | |
| 4824 D0 : S1; // big decoder only | |
| 4825 FPU : S4; | |
| 4826 MEM : S3; // any mem | |
| 4827 %} | |
| 4828 | |
|
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4829 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 4830 instruction_count(3); |
| 4831 src1 : S3(read); | |
| 4832 src2 : S3(read); | |
| 4833 mem : S3(read); | |
| 4834 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4835 D0 : S1; // big decoder only | |
| 4836 FPU : S4; | |
| 4837 MEM : S3; // any mem | |
| 4838 %} | |
| 4839 | |
|
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4840 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 4841 instruction_count(3); |
| 4842 src1 : S3(read); | |
| 4843 src2 : S3(read); | |
| 4844 mem : S4(read); | |
| 4845 DECODE : S0; // any decoder for FPU PUSH | |
| 4846 D0 : S0(2); // big decoder only | |
| 4847 FPU : S4; | |
| 4848 MEM : S3(2); // any mem | |
| 4849 %} | |
| 4850 | |
| 4851 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 4852 instruction_count(2); | |
| 4853 src1 : S3(read); | |
| 4854 dst : S4(read); | |
| 4855 D0 : S0(2); // big decoder only | |
| 4856 MEM : S3(2); // any mem | |
| 4857 %} | |
| 4858 | |
| 4859 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 4860 instruction_count(3); | |
| 4861 src1 : S3(read); | |
| 4862 src2 : S3(read); | |
| 4863 dst : S4(read); | |
| 4864 D0 : S0(3); // big decoder only | |
| 4865 FPU : S4; | |
| 4866 MEM : S3(3); // any mem | |
| 4867 %} | |
| 4868 | |
|
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4869 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 4870 instruction_count(3); |
| 4871 src1 : S4(read); | |
| 4872 mem : S4(read); | |
| 4873 DECODE : S0; // any decoder for FPU PUSH | |
| 4874 D0 : S0(2); // big decoder only | |
| 4875 FPU : S4; | |
| 4876 MEM : S3(2); // any mem | |
| 4877 %} | |
| 4878 | |
| 4879 // Float load constant | |
|
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4880 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 4881 instruction_count(2); |
| 4882 dst : S5(write); | |
| 4883 D0 : S0; // big decoder only for the load | |
| 4884 DECODE : S1; // any decoder for FPU POP | |
| 4885 FPU : S4; | |
| 4886 MEM : S3; // any mem | |
| 4887 %} | |
| 4888 | |
| 4889 // Float load constant | |
|
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4890 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 4891 instruction_count(3); |
| 4892 dst : S5(write); | |
| 4893 src : S3(read); | |
| 4894 D0 : S0; // big decoder only for the load | |
| 4895 DECODE : S1(2); // any decoder for FPU POP | |
| 4896 FPU : S4; | |
| 4897 MEM : S3; // any mem | |
| 4898 %} | |
| 4899 | |
| 4900 // UnConditional branch | |
| 4901 pipe_class pipe_jmp( label labl ) %{ | |
| 4902 single_instruction; | |
| 4903 BR : S3; | |
| 4904 %} | |
| 4905 | |
| 4906 // Conditional branch | |
| 4907 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 4908 single_instruction; | |
| 4909 cr : S1(read); | |
| 4910 BR : S3; | |
| 4911 %} | |
| 4912 | |
| 4913 // Allocation idiom | |
| 4914 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 4915 instruction_count(1); force_serialization; | |
| 4916 fixed_latency(6); | |
| 4917 heap_ptr : S3(read); | |
| 4918 DECODE : S0(3); | |
| 4919 D0 : S2; | |
| 4920 MEM : S3; | |
| 4921 ALU : S3(2); | |
| 4922 dst : S5(write); | |
| 4923 BR : S5; | |
| 4924 %} | |
| 4925 | |
| 4926 // Generic big/slow expanded idiom | |
| 4927 pipe_class pipe_slow( ) %{ | |
| 4928 instruction_count(10); multiple_bundles; force_serialization; | |
| 4929 fixed_latency(100); | |
| 4930 D0 : S0(2); | |
| 4931 MEM : S3(2); | |
| 4932 %} | |
| 4933 | |
| 4934 // The real do-nothing guy | |
| 4935 pipe_class empty( ) %{ | |
| 4936 instruction_count(0); | |
| 4937 %} | |
| 4938 | |
| 4939 // Define the class for the Nop node | |
| 4940 define %{ | |
| 4941 MachNop = empty; | |
| 4942 %} | |
| 4943 | |
| 4944 %} | |
| 4945 | |
| 4946 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4947 // | |
| 4948 // match -- States which machine-independent subtree may be replaced | |
| 4949 // by this instruction. | |
| 4950 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4951 // selection to identify a minimum cost tree of machine | |
| 4952 // instructions that matches a tree of machine-independent | |
| 4953 // instructions. | |
| 4954 // format -- A string providing the disassembly for this instruction. | |
| 4955 // The value of an instruction's operand may be inserted | |
| 4956 // by referring to it with a '$' prefix. | |
| 4957 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4958 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4959 // respectively. The primary opcode is commonly used to | |
| 4960 // indicate the type of machine instruction, while secondary | |
| 4961 // and tertiary are often used for prefix options or addressing | |
| 4962 // modes. | |
| 4963 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4964 // name must have been defined in an 'enc_class' specification | |
| 4965 // in the encode section of the architecture description. | |
| 4966 | |
| 4967 //----------BSWAP-Instruction-------------------------------------------------- | |
|
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4968 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 4969 match(Set dst (ReverseBytesI dst)); |
| 4970 | |
| 4971 format %{ "BSWAP $dst" %} | |
| 4972 opcode(0x0F, 0xC8); | |
| 4973 ins_encode( OpcP, OpcSReg(dst) ); | |
| 4974 ins_pipe( ialu_reg ); | |
| 4975 %} | |
| 4976 | |
| 4977 instruct bytes_reverse_long(eRegL dst) %{ | |
| 4978 match(Set dst (ReverseBytesL dst)); | |
| 4979 | |
| 4980 format %{ "BSWAP $dst.lo\n\t" | |
| 4981 "BSWAP $dst.hi\n\t" | |
| 4982 "XCHG $dst.lo $dst.hi" %} | |
| 4983 | |
| 4984 ins_cost(125); | |
| 4985 ins_encode( bswap_long_bytes(dst) ); | |
| 4986 ins_pipe( ialu_reg_reg); | |
| 4987 %} | |
| 4988 | |
|
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4989 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
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4990 match(Set dst (ReverseBytesUS dst)); |
|
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4991 effect(KILL cr); |
|
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4992 |
|
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|
4993 format %{ "BSWAP $dst\n\t" |
|
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|
4994 "SHR $dst,16\n\t" %} |
|
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changeset
|
4995 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
4996 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
4997 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
4998 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
4999 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5000 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5001 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5002 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5003 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5004 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5005 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5006 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5007 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5008 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5009 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5010 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5011 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5012 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5013 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5014 |
| 0 | 5015 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5016 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5017 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5018 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5019 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5020 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5021 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5022 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5023 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5024 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5025 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5026 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5027 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5028 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5029 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5030 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5031 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5032 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5033 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5034 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5035 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5036 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5037 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5038 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5039 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5040 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5041 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5042 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5043 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5044 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5045 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5046 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5047 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5048 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5049 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5050 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5051 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5052 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5053 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5054 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5055 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5056 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5057 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5058 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5059 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5060 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5061 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5062 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5063 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5064 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5065 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5066 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5067 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5068 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5069 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5070 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5071 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5072 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5073 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5074 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5075 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5076 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5077 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5078 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5079 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5080 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5081 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5082 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5083 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5084 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5085 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5086 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5087 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5088 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5089 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5090 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5091 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5092 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5093 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5094 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5095 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5096 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5097 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5098 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5099 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5100 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5101 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5102 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5103 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5104 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5105 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5106 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5107 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5108 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5109 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5110 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5111 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5112 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5113 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5114 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5115 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5116 match(Set dst (CountTrailingZerosI src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5117 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5118 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5119 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5120 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5121 __ tzcntl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5122 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5123 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5124 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5125 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5126 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5127 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5128 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5129 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5130 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5131 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5132 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5133 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5134 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5135 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5136 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5137 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5138 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5139 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5140 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5141 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5142 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5143 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5144 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5145 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5146 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5147 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5148 match(Set dst (CountTrailingZerosL src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5149 effect(TEMP dst, KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5150 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5151 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5152 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5153 "TZCNT $dst, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5154 "ADD $dst, 32\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5155 "done:" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5156 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5157 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5158 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5159 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5160 __ tzcntl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5161 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5162 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5163 __ addl(Rdst, BitsPerInt); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5164 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5165 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5166 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5167 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5168 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5169 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5170 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5171 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5172 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5173 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5174 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5175 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5176 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5177 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5178 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5179 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5180 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5181 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5182 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5183 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5184 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5185 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5186 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5187 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5188 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5189 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5190 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5191 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5192 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5193 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5194 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5195 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5196 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5197 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5198 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5199 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5200 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5201 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5202 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5203 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5204 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5205 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5206 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5207 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5208 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5209 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5210 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5211 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5212 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5213 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5214 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5215 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5216 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5217 effect(KILL cr); |
|
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|
5218 |
|
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|
5219 format %{ "POPCNT $dst, $mem" %} |
|
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5220 ins_encode %{ |
|
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|
5221 __ popcntl($dst$$Register, $mem$$Address); |
|
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5222 %} |
|
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5223 ins_pipe(ialu_reg); |
|
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|
5224 %} |
|
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|
5225 |
|
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|
5226 // Note: Long.bitCount(long) returns an int. |
|
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5227 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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|
5228 predicate(UsePopCountInstruction); |
|
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5229 match(Set dst (PopCountL src)); |
|
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5230 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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|
5231 |
|
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5232 format %{ "POPCNT $dst, $src.lo\n\t" |
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5233 "POPCNT $tmp, $src.hi\n\t" |
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5234 "ADD $dst, $tmp" %} |
|
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|
5235 ins_encode %{ |
|
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|
5236 __ popcntl($dst$$Register, $src$$Register); |
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5237 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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5238 __ addl($dst$$Register, $tmp$$Register); |
|
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|
5239 %} |
|
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|
5240 ins_pipe(ialu_reg); |
|
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|
5241 %} |
|
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|
5242 |
|
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|
5243 // Note: Long.bitCount(long) returns an int. |
|
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5244 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
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|
5245 predicate(UsePopCountInstruction); |
|
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5246 match(Set dst (PopCountL (LoadL mem))); |
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|
5247 effect(KILL cr, TEMP tmp, TEMP dst); |
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|
5248 |
|
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|
5249 format %{ "POPCNT $dst, $mem\n\t" |
|
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5250 "POPCNT $tmp, $mem+4\n\t" |
|
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|
5251 "ADD $dst, $tmp" %} |
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|
5252 ins_encode %{ |
|
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5253 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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|
5254 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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5255 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
|
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5256 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
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5257 __ addl($dst$$Register, $tmp$$Register); |
|
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|
5258 %} |
|
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|
5259 ins_pipe(ialu_reg); |
|
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|
5260 %} |
|
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|
5261 |
|
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|
5262 |
| 0 | 5263 //----------Load/Store/Move Instructions--------------------------------------- |
| 5264 //----------Load Instructions-------------------------------------------------- | |
| 5265 // Load Byte (8bit signed) | |
| 5266 instruct loadB(xRegI dst, memory mem) %{ | |
| 5267 match(Set dst (LoadB mem)); | |
| 5268 | |
| 5269 ins_cost(125); | |
| 624 | 5270 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5271 | |
| 5272 ins_encode %{ | |
| 5273 __ movsbl($dst$$Register, $mem$$Address); | |
| 5274 %} | |
| 5275 | |
| 5276 ins_pipe(ialu_reg_mem); | |
| 5277 %} | |
| 5278 | |
| 5279 // Load Byte (8bit signed) into Long Register | |
| 824 | 5280 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5281 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5282 effect(KILL cr); |
| 624 | 5283 |
| 5284 ins_cost(375); | |
| 5285 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5286 "MOV $dst.hi,$dst.lo\n\t" | |
| 5287 "SAR $dst.hi,7" %} | |
| 5288 | |
| 5289 ins_encode %{ | |
| 5290 __ movsbl($dst$$Register, $mem$$Address); | |
| 5291 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5292 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5293 %} | |
| 5294 | |
| 5295 ins_pipe(ialu_reg_mem); | |
| 5296 %} | |
| 5297 | |
| 5298 // Load Unsigned Byte (8bit UNsigned) | |
| 5299 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5300 match(Set dst (LoadUB mem)); | |
| 0 | 5301 |
| 5302 ins_cost(125); | |
| 624 | 5303 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5304 | |
| 5305 ins_encode %{ | |
| 5306 __ movzbl($dst$$Register, $mem$$Address); | |
| 5307 %} | |
| 5308 | |
| 5309 ins_pipe(ialu_reg_mem); | |
| 5310 %} | |
| 5311 | |
| 5312 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5313 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5314 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5315 effect(KILL cr); |
| 624 | 5316 |
| 5317 ins_cost(250); | |
| 5318 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5319 "XOR $dst.hi,$dst.hi" %} | |
| 5320 | |
| 5321 ins_encode %{ | |
| 824 | 5322 Register Rdst = $dst$$Register; |
| 5323 __ movzbl(Rdst, $mem$$Address); | |
| 5324 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5325 %} | |
| 5326 | |
| 5327 ins_pipe(ialu_reg_mem); | |
| 5328 %} | |
| 5329 | |
| 5330 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5331 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5332 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5333 effect(KILL cr); | |
| 5334 | |
| 5335 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5336 "XOR $dst.hi,$dst.hi\n\t" | |
| 5337 "AND $dst.lo,$mask" %} | |
| 5338 ins_encode %{ | |
| 5339 Register Rdst = $dst$$Register; | |
| 5340 __ movzbl(Rdst, $mem$$Address); | |
| 5341 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5342 __ andl(Rdst, $mask$$constant); | |
| 5343 %} | |
| 624 | 5344 ins_pipe(ialu_reg_mem); |
| 5345 %} | |
| 5346 | |
| 5347 // Load Short (16bit signed) | |
|
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|
5348 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5349 match(Set dst (LoadS mem)); |
| 5350 | |
| 5351 ins_cost(125); | |
| 5352 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5353 | |
| 5354 ins_encode %{ | |
| 5355 __ movswl($dst$$Register, $mem$$Address); | |
| 5356 %} | |
| 5357 | |
| 5358 ins_pipe(ialu_reg_mem); | |
| 5359 %} | |
| 5360 | |
| 785 | 5361 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
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|
5362 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5363 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5364 | |
| 5365 ins_cost(125); | |
| 5366 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5367 ins_encode %{ | |
| 5368 __ movsbl($dst$$Register, $mem$$Address); | |
| 5369 %} | |
| 5370 ins_pipe(ialu_reg_mem); | |
| 5371 %} | |
| 5372 | |
| 624 | 5373 // Load Short (16bit signed) into Long Register |
| 824 | 5374 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5375 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5376 effect(KILL cr); |
| 624 | 5377 |
| 5378 ins_cost(375); | |
| 5379 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5380 "MOV $dst.hi,$dst.lo\n\t" | |
| 5381 "SAR $dst.hi,15" %} | |
| 5382 | |
| 5383 ins_encode %{ | |
| 5384 __ movswl($dst$$Register, $mem$$Address); | |
| 5385 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5386 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5387 %} | |
| 5388 | |
| 5389 ins_pipe(ialu_reg_mem); | |
| 0 | 5390 %} |
| 5391 | |
|
558
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|
5392 // Load Unsigned Short/Char (16bit unsigned) |
|
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|
5393 instruct loadUS(rRegI dst, memory mem) %{ |
|
558
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|
5394 match(Set dst (LoadUS mem)); |
| 0 | 5395 |
| 5396 ins_cost(125); | |
| 624 | 5397 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5398 | |
| 5399 ins_encode %{ | |
| 5400 __ movzwl($dst$$Register, $mem$$Address); | |
| 5401 %} | |
| 5402 | |
| 5403 ins_pipe(ialu_reg_mem); | |
| 5404 %} | |
| 5405 | |
| 785 | 5406 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
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|
5407 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5408 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5409 | |
| 5410 ins_cost(125); | |
| 5411 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5412 ins_encode %{ | |
| 5413 __ movsbl($dst$$Register, $mem$$Address); | |
| 5414 %} | |
| 5415 ins_pipe(ialu_reg_mem); | |
| 5416 %} | |
| 5417 | |
| 624 | 5418 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5419 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5420 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5421 effect(KILL cr); |
| 624 | 5422 |
| 5423 ins_cost(250); | |
| 5424 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5425 "XOR $dst.hi,$dst.hi" %} | |
| 5426 | |
| 5427 ins_encode %{ | |
| 5428 __ movzwl($dst$$Register, $mem$$Address); | |
| 5429 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5430 %} | |
| 5431 | |
| 5432 ins_pipe(ialu_reg_mem); | |
| 0 | 5433 %} |
| 5434 | |
| 824 | 5435 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5436 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5437 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5438 effect(KILL cr); | |
| 5439 | |
| 5440 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5441 "XOR $dst.hi,$dst.hi" %} | |
| 5442 ins_encode %{ | |
| 5443 Register Rdst = $dst$$Register; | |
| 5444 __ movzbl(Rdst, $mem$$Address); | |
| 5445 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5446 %} | |
| 5447 ins_pipe(ialu_reg_mem); | |
| 5448 %} | |
| 5449 | |
| 5450 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5451 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5452 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5453 effect(KILL cr); | |
| 5454 | |
| 5455 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5456 "XOR $dst.hi,$dst.hi\n\t" | |
| 5457 "AND $dst.lo,$mask" %} | |
| 5458 ins_encode %{ | |
| 5459 Register Rdst = $dst$$Register; | |
| 5460 __ movzwl(Rdst, $mem$$Address); | |
| 5461 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5462 __ andl(Rdst, $mask$$constant); | |
| 5463 %} | |
| 5464 ins_pipe(ialu_reg_mem); | |
| 5465 %} | |
| 5466 | |
| 0 | 5467 // Load Integer |
|
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|
5468 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 5469 match(Set dst (LoadI mem)); |
| 5470 | |
| 5471 ins_cost(125); | |
| 624 | 5472 format %{ "MOV $dst,$mem\t# int" %} |
| 5473 | |
| 5474 ins_encode %{ | |
| 5475 __ movl($dst$$Register, $mem$$Address); | |
| 5476 %} | |
| 5477 | |
| 5478 ins_pipe(ialu_reg_mem); | |
| 5479 %} | |
| 5480 | |
| 785 | 5481 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
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|
5482 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5483 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 5484 | |
| 5485 ins_cost(125); | |
| 5486 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 5487 ins_encode %{ | |
| 5488 __ movsbl($dst$$Register, $mem$$Address); | |
| 5489 %} | |
| 5490 ins_pipe(ialu_reg_mem); | |
| 5491 %} | |
| 5492 | |
| 5493 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
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|
5494 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 5495 match(Set dst (AndI (LoadI mem) mask)); |
| 5496 | |
| 5497 ins_cost(125); | |
| 5498 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 5499 ins_encode %{ | |
| 5500 __ movzbl($dst$$Register, $mem$$Address); | |
| 5501 %} | |
| 5502 ins_pipe(ialu_reg_mem); | |
| 5503 %} | |
| 5504 | |
| 5505 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
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|
5506 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 5507 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 5508 | |
| 5509 ins_cost(125); | |
| 5510 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 5511 ins_encode %{ | |
| 5512 __ movswl($dst$$Register, $mem$$Address); | |
| 5513 %} | |
| 5514 ins_pipe(ialu_reg_mem); | |
| 5515 %} | |
| 5516 | |
| 5517 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
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|
5518 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 5519 match(Set dst (AndI (LoadI mem) mask)); |
| 5520 | |
| 5521 ins_cost(125); | |
| 5522 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 5523 ins_encode %{ | |
| 5524 __ movzwl($dst$$Register, $mem$$Address); | |
| 5525 %} | |
| 5526 ins_pipe(ialu_reg_mem); | |
| 5527 %} | |
| 5528 | |
| 624 | 5529 // Load Integer into Long Register |
| 824 | 5530 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5531 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 5532 effect(KILL cr); |
| 624 | 5533 |
| 5534 ins_cost(375); | |
| 5535 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 5536 "MOV $dst.hi,$dst.lo\n\t" | |
| 5537 "SAR $dst.hi,31" %} | |
| 5538 | |
| 5539 ins_encode %{ | |
| 5540 __ movl($dst$$Register, $mem$$Address); | |
| 5541 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5542 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 5543 %} | |
| 5544 | |
| 5545 ins_pipe(ialu_reg_mem); | |
| 5546 %} | |
| 5547 | |
| 824 | 5548 // Load Integer with mask 0xFF into Long Register |
| 5549 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5550 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5551 effect(KILL cr); | |
| 5552 | |
| 5553 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 5554 "XOR $dst.hi,$dst.hi" %} | |
| 5555 ins_encode %{ | |
| 5556 Register Rdst = $dst$$Register; | |
| 5557 __ movzbl(Rdst, $mem$$Address); | |
| 5558 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5559 %} | |
| 5560 ins_pipe(ialu_reg_mem); | |
| 5561 %} | |
| 5562 | |
| 5563 // Load Integer with mask 0xFFFF into Long Register | |
| 5564 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 5565 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5566 effect(KILL cr); | |
| 5567 | |
| 5568 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 5569 "XOR $dst.hi,$dst.hi" %} | |
| 5570 ins_encode %{ | |
| 5571 Register Rdst = $dst$$Register; | |
| 5572 __ movzwl(Rdst, $mem$$Address); | |
| 5573 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5574 %} | |
| 5575 ins_pipe(ialu_reg_mem); | |
| 5576 %} | |
| 5577 | |
|
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5578 // Load Integer with 31-bit mask into Long Register |
|
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|
5579 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ |
| 824 | 5580 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5581 effect(KILL cr); | |
| 5582 | |
|
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|
5583 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 5584 "XOR $dst.hi,$dst.hi\n\t" |
| 5585 "AND $dst.lo,$mask" %} | |
| 5586 ins_encode %{ | |
| 5587 Register Rdst = $dst$$Register; | |
| 5588 __ movl(Rdst, $mem$$Address); | |
| 5589 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5590 __ andl(Rdst, $mask$$constant); | |
| 5591 %} | |
| 5592 ins_pipe(ialu_reg_mem); | |
| 5593 %} | |
| 5594 | |
| 624 | 5595 // Load Unsigned Integer into Long Register |
| 6849 | 5596 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 5597 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 5598 effect(KILL cr); |
| 624 | 5599 |
| 5600 ins_cost(250); | |
| 5601 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 5602 "XOR $dst.hi,$dst.hi" %} | |
| 5603 | |
| 5604 ins_encode %{ | |
| 5605 __ movl($dst$$Register, $mem$$Address); | |
| 5606 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5607 %} | |
| 5608 | |
| 5609 ins_pipe(ialu_reg_mem); | |
| 0 | 5610 %} |
| 5611 | |
| 5612 // Load Long. Cannot clobber address while loading, so restrict address | |
| 5613 // register to ESI | |
| 5614 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 5615 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 5616 match(Set dst (LoadL mem)); | |
| 5617 | |
| 5618 ins_cost(250); | |
| 624 | 5619 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 5620 "MOV $dst.hi,$mem+4" %} |
| 624 | 5621 |
| 5622 ins_encode %{ | |
|
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5623 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
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5624 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 5625 __ movl($dst$$Register, Amemlo); |
| 5626 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 5627 %} | |
| 5628 | |
| 5629 ins_pipe(ialu_reg_long_mem); | |
| 0 | 5630 %} |
| 5631 | |
| 5632 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 5633 // then store it down to the stack and reload on the int | |
| 5634 // side. | |
| 5635 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 5636 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 5637 match(Set dst (LoadL mem)); | |
| 5638 | |
| 5639 ins_cost(200); | |
| 5640 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 5641 "FISTp $dst" %} | |
| 5642 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 5643 ins_pipe( fpu_reg_mem ); | |
| 5644 %} | |
| 5645 | |
|
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|
5646 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 5647 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5648 match(Set dst (LoadL mem)); | |
| 5649 effect(TEMP tmp); | |
| 5650 ins_cost(180); | |
| 5651 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5652 "MOVSD $dst,$tmp" %} | |
| 4759 | 5653 ins_encode %{ |
| 5654 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5655 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 5656 %} | |
| 0 | 5657 ins_pipe( pipe_slow ); |
| 5658 %} | |
| 5659 | |
|
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|
5660 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 5661 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5662 match(Set dst (LoadL mem)); | |
| 5663 effect(TEMP tmp); | |
| 5664 ins_cost(160); | |
| 5665 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5666 "MOVD $dst.lo,$tmp\n\t" | |
| 5667 "PSRLQ $tmp,32\n\t" | |
| 5668 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 5669 ins_encode %{ |
| 5670 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5671 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 5672 __ psrlq($tmp$$XMMRegister, 32); | |
| 5673 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 5674 %} | |
| 0 | 5675 ins_pipe( pipe_slow ); |
| 5676 %} | |
| 5677 | |
| 5678 // Load Range | |
|
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|
5679 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 5680 match(Set dst (LoadRange mem)); |
| 5681 | |
| 5682 ins_cost(125); | |
| 5683 format %{ "MOV $dst,$mem" %} | |
| 5684 opcode(0x8B); | |
| 5685 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5686 ins_pipe( ialu_reg_mem ); | |
| 5687 %} | |
| 5688 | |
| 5689 | |
| 5690 // Load Pointer | |
| 5691 instruct loadP(eRegP dst, memory mem) %{ | |
| 5692 match(Set dst (LoadP mem)); | |
| 5693 | |
| 5694 ins_cost(125); | |
| 5695 format %{ "MOV $dst,$mem" %} | |
| 5696 opcode(0x8B); | |
| 5697 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5698 ins_pipe( ialu_reg_mem ); | |
| 5699 %} | |
| 5700 | |
| 5701 // Load Klass Pointer | |
| 5702 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 5703 match(Set dst (LoadKlass mem)); | |
| 5704 | |
| 5705 ins_cost(125); | |
| 5706 format %{ "MOV $dst,$mem" %} | |
| 5707 opcode(0x8B); | |
| 5708 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5709 ins_pipe( ialu_reg_mem ); | |
| 5710 %} | |
| 5711 | |
| 5712 // Load Double | |
|
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|
5713 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 5714 predicate(UseSSE<=1); |
| 5715 match(Set dst (LoadD mem)); | |
| 5716 | |
| 5717 ins_cost(150); | |
| 5718 format %{ "FLD_D ST,$mem\n\t" | |
| 5719 "FSTP $dst" %} | |
| 5720 opcode(0xDD); /* DD /0 */ | |
| 5721 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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|
5722 Pop_Reg_DPR(dst) ); |
| 0 | 5723 ins_pipe( fpu_reg_mem ); |
| 5724 %} | |
| 5725 | |
| 5726 // Load Double to XMM | |
|
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|
5727 instruct loadD(regD dst, memory mem) %{ |
| 0 | 5728 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 5729 match(Set dst (LoadD mem)); | |
| 5730 ins_cost(145); | |
| 5731 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 5732 ins_encode %{ |
| 5733 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5734 %} | |
| 0 | 5735 ins_pipe( pipe_slow ); |
| 5736 %} | |
| 5737 | |
|
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|
5738 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 5739 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 5740 match(Set dst (LoadD mem)); | |
| 5741 ins_cost(145); | |
| 5742 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 5743 ins_encode %{ |
| 5744 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5745 %} | |
| 0 | 5746 ins_pipe( pipe_slow ); |
| 5747 %} | |
| 5748 | |
| 5749 // Load to XMM register (single-precision floating point) | |
| 5750 // MOVSS instruction | |
|
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|
5751 instruct loadF(regF dst, memory mem) %{ |
| 0 | 5752 predicate(UseSSE>=1); |
| 5753 match(Set dst (LoadF mem)); | |
| 5754 ins_cost(145); | |
| 5755 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 5756 ins_encode %{ |
| 5757 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 5758 %} | |
| 0 | 5759 ins_pipe( pipe_slow ); |
| 5760 %} | |
| 5761 | |
| 5762 // Load Float | |
|
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|
5763 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 5764 predicate(UseSSE==0); |
| 5765 match(Set dst (LoadF mem)); | |
| 5766 | |
| 5767 ins_cost(150); | |
| 5768 format %{ "FLD_S ST,$mem\n\t" | |
| 5769 "FSTP $dst" %} | |
| 5770 opcode(0xD9); /* D9 /0 */ | |
| 5771 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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|
5772 Pop_Reg_FPR(dst) ); |
| 0 | 5773 ins_pipe( fpu_reg_mem ); |
| 5774 %} | |
| 5775 | |
| 5776 // Load Effective Address | |
| 5777 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 5778 match(Set dst mem); | |
| 5779 | |
| 5780 ins_cost(110); | |
| 5781 format %{ "LEA $dst,$mem" %} | |
| 5782 opcode(0x8D); | |
| 5783 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5784 ins_pipe( ialu_reg_reg_fat ); | |
| 5785 %} | |
| 5786 | |
| 5787 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 5788 match(Set dst mem); | |
| 5789 | |
| 5790 ins_cost(110); | |
| 5791 format %{ "LEA $dst,$mem" %} | |
| 5792 opcode(0x8D); | |
| 5793 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5794 ins_pipe( ialu_reg_reg_fat ); | |
| 5795 %} | |
| 5796 | |
| 5797 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 5798 match(Set dst mem); | |
| 5799 | |
| 5800 ins_cost(110); | |
| 5801 format %{ "LEA $dst,$mem" %} | |
| 5802 opcode(0x8D); | |
| 5803 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5804 ins_pipe( ialu_reg_reg_fat ); | |
| 5805 %} | |
| 5806 | |
| 5807 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 5808 match(Set dst mem); | |
| 5809 | |
| 5810 ins_cost(110); | |
| 5811 format %{ "LEA $dst,$mem" %} | |
| 5812 opcode(0x8D); | |
| 5813 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5814 ins_pipe( ialu_reg_reg_fat ); | |
| 5815 %} | |
| 5816 | |
| 5817 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 5818 match(Set dst mem); | |
| 5819 | |
| 5820 ins_cost(110); | |
| 5821 format %{ "LEA $dst,$mem" %} | |
| 5822 opcode(0x8D); | |
| 5823 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5824 ins_pipe( ialu_reg_reg_fat ); | |
| 5825 %} | |
| 5826 | |
| 5827 // Load Constant | |
|
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|
5828 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 5829 match(Set dst src); |
| 5830 | |
| 5831 format %{ "MOV $dst,$src" %} | |
| 5832 ins_encode( LdImmI(dst, src) ); | |
| 5833 ins_pipe( ialu_reg_fat ); | |
| 5834 %} | |
| 5835 | |
| 5836 // Load Constant zero | |
|
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|
5837 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 5838 match(Set dst src); |
| 5839 effect(KILL cr); | |
| 5840 | |
| 5841 ins_cost(50); | |
| 5842 format %{ "XOR $dst,$dst" %} | |
| 5843 opcode(0x33); /* + rd */ | |
| 5844 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 5845 ins_pipe( ialu_reg ); | |
| 5846 %} | |
| 5847 | |
| 5848 instruct loadConP(eRegP dst, immP src) %{ | |
| 5849 match(Set dst src); | |
| 5850 | |
| 5851 format %{ "MOV $dst,$src" %} | |
| 5852 opcode(0xB8); /* + rd */ | |
| 5853 ins_encode( LdImmP(dst, src) ); | |
| 5854 ins_pipe( ialu_reg_fat ); | |
| 5855 %} | |
| 5856 | |
| 5857 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 5858 match(Set dst src); | |
| 5859 effect(KILL cr); | |
| 5860 ins_cost(200); | |
| 5861 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 5862 "MOV $dst.hi,$src.hi" %} | |
| 5863 opcode(0xB8); | |
| 5864 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 5865 ins_pipe( ialu_reg_long_fat ); | |
| 5866 %} | |
| 5867 | |
| 5868 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 5869 match(Set dst src); | |
| 5870 effect(KILL cr); | |
| 5871 ins_cost(150); | |
| 5872 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 5873 "XOR $dst.hi,$dst.hi" %} | |
| 5874 opcode(0x33,0x33); | |
| 5875 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 5876 ins_pipe( ialu_reg_long ); | |
| 5877 %} | |
| 5878 | |
|
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5879 // The instruction usage is guarded by predicate in operand immFPR(). |
|
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|
5880 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 5881 match(Set dst con); |
| 5882 ins_cost(125); | |
| 5883 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 5884 "FSTP $dst" %} | |
| 5885 ins_encode %{ | |
| 5886 __ fld_s($constantaddress($con)); | |
| 5887 __ fstp_d($dst$$reg); | |
| 5888 %} | |
| 5889 ins_pipe(fpu_reg_con); | |
| 5890 %} | |
| 5891 | |
|
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|
5892 // The instruction usage is guarded by predicate in operand immFPR0(). |
|
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|
5893 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 5894 match(Set dst con); |
| 0 | 5895 ins_cost(125); |
| 2008 | 5896 format %{ "FLDZ ST\n\t" |
| 0 | 5897 "FSTP $dst" %} |
| 2008 | 5898 ins_encode %{ |
| 5899 __ fldz(); | |
| 5900 __ fstp_d($dst$$reg); | |
| 5901 %} | |
| 5902 ins_pipe(fpu_reg_con); | |
| 5903 %} | |
| 5904 | |
|
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5905 // The instruction usage is guarded by predicate in operand immFPR1(). |
|
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|
5906 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 5907 match(Set dst con); |
| 5908 ins_cost(125); | |
| 5909 format %{ "FLD1 ST\n\t" | |
| 5910 "FSTP $dst" %} | |
| 5911 ins_encode %{ | |
| 5912 __ fld1(); | |
| 5913 __ fstp_d($dst$$reg); | |
| 5914 %} | |
| 5915 ins_pipe(fpu_reg_con); | |
| 0 | 5916 %} |
| 5917 | |
|
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5918 // The instruction usage is guarded by predicate in operand immF(). |
|
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|
5919 instruct loadConF(regF dst, immF con) %{ |
| 0 | 5920 match(Set dst con); |
| 5921 ins_cost(125); | |
| 2008 | 5922 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 5923 ins_encode %{ | |
| 5924 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5925 %} | |
| 5926 ins_pipe(pipe_slow); | |
| 0 | 5927 %} |
| 5928 | |
|
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|
5929 // The instruction usage is guarded by predicate in operand immF0(). |
|
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|
5930 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 5931 match(Set dst src); |
| 5932 ins_cost(100); | |
| 5933 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 5934 ins_encode %{ |
| 5935 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5936 %} | |
| 5937 ins_pipe(pipe_slow); | |
| 0 | 5938 %} |
| 5939 | |
|
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5940 // The instruction usage is guarded by predicate in operand immDPR(). |
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5941 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 5942 match(Set dst con); |
| 5943 ins_cost(125); | |
| 5944 | |
| 5945 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 5946 "FSTP $dst" %} | |
| 5947 ins_encode %{ | |
| 5948 __ fld_d($constantaddress($con)); | |
| 5949 __ fstp_d($dst$$reg); | |
| 5950 %} | |
| 5951 ins_pipe(fpu_reg_con); | |
| 5952 %} | |
| 5953 | |
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5954 // The instruction usage is guarded by predicate in operand immDPR0(). |
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5955 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 5956 match(Set dst con); |
| 0 | 5957 ins_cost(125); |
| 5958 | |
| 2008 | 5959 format %{ "FLDZ ST\n\t" |
| 0 | 5960 "FSTP $dst" %} |
| 2008 | 5961 ins_encode %{ |
| 5962 __ fldz(); | |
| 5963 __ fstp_d($dst$$reg); | |
| 5964 %} | |
| 5965 ins_pipe(fpu_reg_con); | |
| 5966 %} | |
| 5967 | |
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5968 // The instruction usage is guarded by predicate in operand immDPR1(). |
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5969 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 5970 match(Set dst con); |
| 5971 ins_cost(125); | |
| 5972 | |
| 5973 format %{ "FLD1 ST\n\t" | |
| 5974 "FSTP $dst" %} | |
| 5975 ins_encode %{ | |
| 5976 __ fld1(); | |
| 5977 __ fstp_d($dst$$reg); | |
| 5978 %} | |
| 5979 ins_pipe(fpu_reg_con); | |
| 0 | 5980 %} |
| 5981 | |
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5982 // The instruction usage is guarded by predicate in operand immD(). |
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5983 instruct loadConD(regD dst, immD con) %{ |
| 0 | 5984 match(Set dst con); |
| 5985 ins_cost(125); | |
| 2008 | 5986 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 5987 ins_encode %{ | |
| 5988 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5989 %} | |
| 5990 ins_pipe(pipe_slow); | |
| 0 | 5991 %} |
| 5992 | |
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5993 // The instruction usage is guarded by predicate in operand immD0(). |
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5994 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 5995 match(Set dst src); |
| 5996 ins_cost(100); | |
| 5997 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 5998 ins_encode %{ |
| 5999 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6000 %} | |
| 0 | 6001 ins_pipe( pipe_slow ); |
| 6002 %} | |
| 6003 | |
| 6004 // Load Stack Slot | |
|
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6005 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6006 match(Set dst src); |
| 6007 ins_cost(125); | |
| 6008 | |
| 6009 format %{ "MOV $dst,$src" %} | |
| 6010 opcode(0x8B); | |
| 6011 ins_encode( OpcP, RegMem(dst,src)); | |
| 6012 ins_pipe( ialu_reg_mem ); | |
| 6013 %} | |
| 6014 | |
| 6015 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6016 match(Set dst src); | |
| 6017 | |
| 6018 ins_cost(200); | |
| 6019 format %{ "MOV $dst,$src.lo\n\t" | |
| 6020 "MOV $dst+4,$src.hi" %} | |
| 6021 opcode(0x8B, 0x8B); | |
| 6022 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6023 ins_pipe( ialu_mem_long_reg ); | |
| 6024 %} | |
| 6025 | |
| 6026 // Load Stack Slot | |
| 6027 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6028 match(Set dst src); | |
| 6029 ins_cost(125); | |
| 6030 | |
| 6031 format %{ "MOV $dst,$src" %} | |
| 6032 opcode(0x8B); | |
| 6033 ins_encode( OpcP, RegMem(dst,src)); | |
| 6034 ins_pipe( ialu_reg_mem ); | |
| 6035 %} | |
| 6036 | |
| 6037 // Load Stack Slot | |
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6038 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6039 match(Set dst src); |
| 6040 ins_cost(125); | |
| 6041 | |
| 6042 format %{ "FLD_S $src\n\t" | |
| 6043 "FSTP $dst" %} | |
| 6044 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6045 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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6046 Pop_Reg_FPR(dst) ); |
| 0 | 6047 ins_pipe( fpu_reg_mem ); |
| 6048 %} | |
| 6049 | |
| 6050 // Load Stack Slot | |
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6051 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6052 match(Set dst src); |
| 6053 ins_cost(125); | |
| 6054 | |
| 6055 format %{ "FLD_D $src\n\t" | |
| 6056 "FSTP $dst" %} | |
| 6057 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6058 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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6059 Pop_Reg_DPR(dst) ); |
| 0 | 6060 ins_pipe( fpu_reg_mem ); |
| 6061 %} | |
| 6062 | |
| 6063 // Prefetch instructions. | |
| 6064 // Must be safe to execute with invalid address (cannot fault). | |
| 6065 | |
| 6066 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6067 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6068 match(PrefetchRead mem); |
| 6069 ins_cost(0); | |
| 6070 size(0); | |
| 6071 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6072 ins_encode(); | |
| 6073 ins_pipe(empty); | |
| 6074 %} | |
| 6075 | |
| 6076 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6077 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6078 match(PrefetchRead mem); |
| 6079 ins_cost(100); | |
| 6080 | |
| 6081 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6082 ins_encode %{ |
| 6083 __ prefetchr($mem$$Address); | |
| 6084 %} | |
| 0 | 6085 ins_pipe(ialu_mem); |
| 6086 %} | |
| 6087 | |
| 6088 instruct prefetchrNTA( memory mem ) %{ | |
| 6089 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6090 match(PrefetchRead mem); | |
| 6091 ins_cost(100); | |
| 6092 | |
| 6093 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6094 ins_encode %{ |
| 6095 __ prefetchnta($mem$$Address); | |
| 6096 %} | |
| 0 | 6097 ins_pipe(ialu_mem); |
| 6098 %} | |
| 6099 | |
| 6100 instruct prefetchrT0( memory mem ) %{ | |
| 6101 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6102 match(PrefetchRead mem); | |
| 6103 ins_cost(100); | |
| 6104 | |
| 6105 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6106 ins_encode %{ |
| 6107 __ prefetcht0($mem$$Address); | |
| 6108 %} | |
| 0 | 6109 ins_pipe(ialu_mem); |
| 6110 %} | |
| 6111 | |
| 6112 instruct prefetchrT2( memory mem ) %{ | |
| 6113 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6114 match(PrefetchRead mem); | |
| 6115 ins_cost(100); | |
| 6116 | |
| 6117 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6118 ins_encode %{ |
| 6119 __ prefetcht2($mem$$Address); | |
| 6120 %} | |
| 0 | 6121 ins_pipe(ialu_mem); |
| 6122 %} | |
| 6123 | |
| 6124 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6125 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6126 match(PrefetchWrite mem); |
| 6127 ins_cost(0); | |
| 6128 size(0); | |
| 6129 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6130 ins_encode(); | |
| 6131 ins_pipe(empty); | |
| 6132 %} | |
| 6133 | |
| 6134 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6135 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6136 match( PrefetchWrite mem ); |
| 6137 ins_cost(100); | |
| 6138 | |
| 6139 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6140 ins_encode %{ |
| 6141 __ prefetchw($mem$$Address); | |
| 6142 %} | |
| 0 | 6143 ins_pipe(ialu_mem); |
| 6144 %} | |
| 6145 | |
| 6146 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6147 predicate(UseSSE>=1); |
| 0 | 6148 match(PrefetchWrite mem); |
| 6149 ins_cost(100); | |
| 6150 | |
| 6151 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6152 ins_encode %{ |
| 6153 __ prefetchnta($mem$$Address); | |
| 6154 %} | |
| 0 | 6155 ins_pipe(ialu_mem); |
| 6156 %} | |
| 6157 | |
| 3854 | 6158 // Prefetch instructions for allocation. |
| 6159 | |
| 6160 instruct prefetchAlloc0( memory mem ) %{ | |
| 6161 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6162 match(PrefetchAllocation mem); | |
| 6163 ins_cost(0); | |
| 6164 size(0); | |
| 6165 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6166 ins_encode(); | |
| 6167 ins_pipe(empty); | |
| 6168 %} | |
| 6169 | |
| 6170 instruct prefetchAlloc( memory mem ) %{ | |
| 6171 predicate(AllocatePrefetchInstr==3); | |
| 6172 match( PrefetchAllocation mem ); | |
| 0 | 6173 ins_cost(100); |
| 6174 | |
| 3854 | 6175 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6176 ins_encode %{ | |
| 6177 __ prefetchw($mem$$Address); | |
| 6178 %} | |
| 6179 ins_pipe(ialu_mem); | |
| 6180 %} | |
| 6181 | |
| 6182 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6183 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6184 match(PrefetchAllocation mem); | |
| 6185 ins_cost(100); | |
| 6186 | |
| 6187 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6188 ins_encode %{ | |
| 6189 __ prefetchnta($mem$$Address); | |
| 6190 %} | |
| 0 | 6191 ins_pipe(ialu_mem); |
| 6192 %} | |
| 6193 | |
| 3854 | 6194 instruct prefetchAllocT0( memory mem ) %{ |
| 6195 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6196 match(PrefetchAllocation mem); | |
| 0 | 6197 ins_cost(100); |
| 6198 | |
| 3854 | 6199 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6200 ins_encode %{ | |
| 6201 __ prefetcht0($mem$$Address); | |
| 6202 %} | |
| 6203 ins_pipe(ialu_mem); | |
| 6204 %} | |
| 6205 | |
| 6206 instruct prefetchAllocT2( memory mem ) %{ | |
| 6207 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6208 match(PrefetchAllocation mem); | |
| 6209 ins_cost(100); | |
| 6210 | |
| 6211 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6212 ins_encode %{ | |
| 6213 __ prefetcht2($mem$$Address); | |
| 6214 %} | |
| 0 | 6215 ins_pipe(ialu_mem); |
| 6216 %} | |
| 6217 | |
| 6218 //----------Store Instructions------------------------------------------------- | |
| 6219 | |
| 6220 // Store Byte | |
| 6221 instruct storeB(memory mem, xRegI src) %{ | |
| 6222 match(Set mem (StoreB mem src)); | |
| 6223 | |
| 6224 ins_cost(125); | |
| 6225 format %{ "MOV8 $mem,$src" %} | |
| 6226 opcode(0x88); | |
| 6227 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6228 ins_pipe( ialu_mem_reg ); | |
| 6229 %} | |
| 6230 | |
| 6231 // Store Char/Short | |
|
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6232 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6233 match(Set mem (StoreC mem src)); |
| 6234 | |
| 6235 ins_cost(125); | |
| 6236 format %{ "MOV16 $mem,$src" %} | |
| 6237 opcode(0x89, 0x66); | |
| 6238 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6239 ins_pipe( ialu_mem_reg ); | |
| 6240 %} | |
| 6241 | |
| 6242 // Store Integer | |
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6243 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6244 match(Set mem (StoreI mem src)); |
| 6245 | |
| 6246 ins_cost(125); | |
| 6247 format %{ "MOV $mem,$src" %} | |
| 6248 opcode(0x89); | |
| 6249 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6250 ins_pipe( ialu_mem_reg ); | |
| 6251 %} | |
| 6252 | |
| 6253 // Store Long | |
| 6254 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6255 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6256 match(Set mem (StoreL mem src)); | |
| 6257 | |
| 6258 ins_cost(200); | |
| 6259 format %{ "MOV $mem,$src.lo\n\t" | |
| 6260 "MOV $mem+4,$src.hi" %} | |
| 6261 opcode(0x89, 0x89); | |
| 6262 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6263 ins_pipe( ialu_mem_long_reg ); | |
| 6264 %} | |
| 6265 | |
| 824 | 6266 // Store Long to Integer |
| 6267 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6268 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6269 | |
| 6270 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6271 ins_encode %{ | |
| 6272 __ movl($mem$$Address, $src$$Register); | |
| 6273 %} | |
| 6274 ins_pipe(ialu_mem_reg); | |
| 6275 %} | |
| 6276 | |
| 0 | 6277 // Volatile Store Long. Must be atomic, so move it into |
| 6278 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6279 // target address before the store (for null-ptr checks) | |
| 6280 // so the memory operand is used twice in the encoding. | |
| 6281 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6282 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6283 match(Set mem (StoreL mem src)); | |
| 6284 effect( KILL cr ); | |
| 6285 ins_cost(400); | |
| 6286 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6287 "FILD $src\n\t" | |
| 6288 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6289 opcode(0x3B); | |
| 6290 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6291 ins_pipe( fpu_reg_mem ); | |
| 6292 %} | |
| 6293 | |
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6294 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6295 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6296 match(Set mem (StoreL mem src)); | |
| 6297 effect( TEMP tmp, KILL cr ); | |
| 6298 ins_cost(380); | |
| 6299 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6300 "MOVSD $tmp,$src\n\t" | |
| 6301 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6302 ins_encode %{ |
| 6303 __ cmpl(rax, $mem$$Address); | |
| 6304 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6305 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6306 %} | |
| 0 | 6307 ins_pipe( pipe_slow ); |
| 6308 %} | |
| 6309 | |
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6310 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6311 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6312 match(Set mem (StoreL mem src)); | |
| 6313 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6314 ins_cost(360); | |
| 6315 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6316 "MOVD $tmp,$src.lo\n\t" | |
| 6317 "MOVD $tmp2,$src.hi\n\t" | |
| 6318 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6319 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6320 ins_encode %{ |
| 6321 __ cmpl(rax, $mem$$Address); | |
| 6322 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6323 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6324 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6325 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6326 %} | |
| 0 | 6327 ins_pipe( pipe_slow ); |
| 6328 %} | |
| 6329 | |
| 6330 // Store Pointer; for storing unknown oops and raw pointers | |
| 6331 instruct storeP(memory mem, anyRegP src) %{ | |
| 6332 match(Set mem (StoreP mem src)); | |
| 6333 | |
| 6334 ins_cost(125); | |
| 6335 format %{ "MOV $mem,$src" %} | |
| 6336 opcode(0x89); | |
| 6337 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6338 ins_pipe( ialu_mem_reg ); | |
| 6339 %} | |
| 6340 | |
| 6341 // Store Integer Immediate | |
| 6342 instruct storeImmI(memory mem, immI src) %{ | |
| 6343 match(Set mem (StoreI mem src)); | |
| 6344 | |
| 6345 ins_cost(150); | |
| 6346 format %{ "MOV $mem,$src" %} | |
| 6347 opcode(0xC7); /* C7 /0 */ | |
| 6348 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6349 ins_pipe( ialu_mem_imm ); | |
| 6350 %} | |
| 6351 | |
| 6352 // Store Short/Char Immediate | |
| 6353 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6354 predicate(UseStoreImmI16); | |
| 6355 match(Set mem (StoreC mem src)); | |
| 6356 | |
| 6357 ins_cost(150); | |
| 6358 format %{ "MOV16 $mem,$src" %} | |
| 6359 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6360 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6361 ins_pipe( ialu_mem_imm ); | |
| 6362 %} | |
| 6363 | |
| 6364 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6365 // need card-mark barriers. | |
| 6366 instruct storeImmP(memory mem, immP src) %{ | |
| 6367 match(Set mem (StoreP mem src)); | |
| 6368 | |
| 6369 ins_cost(150); | |
| 6370 format %{ "MOV $mem,$src" %} | |
| 6371 opcode(0xC7); /* C7 /0 */ | |
| 6372 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6373 ins_pipe( ialu_mem_imm ); | |
| 6374 %} | |
| 6375 | |
| 6376 // Store Byte Immediate | |
| 6377 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6378 match(Set mem (StoreB mem src)); | |
| 6379 | |
| 6380 ins_cost(150); | |
| 6381 format %{ "MOV8 $mem,$src" %} | |
| 6382 opcode(0xC6); /* C6 /0 */ | |
| 6383 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6384 ins_pipe( ialu_mem_imm ); | |
| 6385 %} | |
| 6386 | |
| 6387 // Store CMS card-mark Immediate | |
| 6388 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6389 match(Set mem (StoreCM mem src)); | |
| 6390 | |
| 6391 ins_cost(150); | |
| 6392 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6393 opcode(0xC6); /* C6 /0 */ | |
| 6394 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6395 ins_pipe( ialu_mem_imm ); | |
| 6396 %} | |
| 6397 | |
| 6398 // Store Double | |
|
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|
6399 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6400 predicate(UseSSE<=1); |
| 6401 match(Set mem (StoreD mem src)); | |
| 6402 | |
| 6403 ins_cost(100); | |
| 6404 format %{ "FST_D $mem,$src" %} | |
| 6405 opcode(0xDD); /* DD /2 */ | |
|
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|
6406 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6407 ins_pipe( fpu_mem_reg ); |
| 6408 %} | |
| 6409 | |
| 6410 // Store double does rounding on x86 | |
|
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|
6411 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6412 predicate(UseSSE<=1); |
| 6413 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6414 | |
| 6415 ins_cost(100); | |
| 6416 format %{ "FST_D $mem,$src\t# round" %} | |
| 6417 opcode(0xDD); /* DD /2 */ | |
|
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|
6418 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6419 ins_pipe( fpu_mem_reg ); |
| 6420 %} | |
| 6421 | |
| 6422 // Store XMM register to memory (double-precision floating points) | |
| 6423 // MOVSD instruction | |
|
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|
6424 instruct storeD(memory mem, regD src) %{ |
| 0 | 6425 predicate(UseSSE>=2); |
| 6426 match(Set mem (StoreD mem src)); | |
| 6427 ins_cost(95); | |
| 6428 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6429 ins_encode %{ |
| 6430 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6431 %} | |
| 0 | 6432 ins_pipe( pipe_slow ); |
| 6433 %} | |
| 6434 | |
| 6435 // Store XMM register to memory (single-precision floating point) | |
| 6436 // MOVSS instruction | |
|
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|
6437 instruct storeF(memory mem, regF src) %{ |
| 0 | 6438 predicate(UseSSE>=1); |
| 6439 match(Set mem (StoreF mem src)); | |
| 6440 ins_cost(95); | |
| 6441 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6442 ins_encode %{ |
| 6443 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6444 %} | |
| 0 | 6445 ins_pipe( pipe_slow ); |
| 6446 %} | |
| 6447 | |
| 6448 // Store Float | |
|
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|
6449 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 6450 predicate(UseSSE==0); |
| 6451 match(Set mem (StoreF mem src)); | |
| 6452 | |
| 6453 ins_cost(100); | |
| 6454 format %{ "FST_S $mem,$src" %} | |
| 6455 opcode(0xD9); /* D9 /2 */ | |
|
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changeset
|
6456 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6457 ins_pipe( fpu_mem_reg ); |
| 6458 %} | |
| 6459 | |
| 6460 // Store Float does rounding on x86 | |
|
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|
6461 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 6462 predicate(UseSSE==0); |
| 6463 match(Set mem (StoreF mem (RoundFloat src))); | |
| 6464 | |
| 6465 ins_cost(100); | |
| 6466 format %{ "FST_S $mem,$src\t# round" %} | |
| 6467 opcode(0xD9); /* D9 /2 */ | |
|
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|
6468 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6469 ins_pipe( fpu_mem_reg ); |
| 6470 %} | |
| 6471 | |
| 6472 // Store Float does rounding on x86 | |
|
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|
6473 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 6474 predicate(UseSSE<=1); |
| 6475 match(Set mem (StoreF mem (ConvD2F src))); | |
| 6476 | |
| 6477 ins_cost(100); | |
| 6478 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 6479 opcode(0xD9); /* D9 /2 */ | |
|
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|
6480 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6481 ins_pipe( fpu_mem_reg ); |
| 6482 %} | |
| 6483 | |
| 6484 // Store immediate Float value (it is faster than store from FPU register) | |
|
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|
6485 // The instruction usage is guarded by predicate in operand immFPR(). |
|
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diff
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|
6486 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
65149e74c706
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|
6487 match(Set mem (StoreF mem src)); |
|
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diff
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|
6488 |
|
65149e74c706
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diff
changeset
|
6489 ins_cost(50); |
|
65149e74c706
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diff
changeset
|
6490 format %{ "MOV $mem,$src\t# store float" %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
6491 opcode(0xC7); /* C7 /0 */ |
|
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|
6492 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
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|
6493 ins_pipe( ialu_mem_imm ); |
|
65149e74c706
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|
6494 %} |
|
65149e74c706
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diff
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|
6495 |
|
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|
6496 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 6497 // The instruction usage is guarded by predicate in operand immF(). |
| 6498 instruct storeF_imm( memory mem, immF src) %{ | |
| 6499 match(Set mem (StoreF mem src)); | |
| 6500 | |
| 6501 ins_cost(50); | |
| 6502 format %{ "MOV $mem,$src\t# store float" %} | |
| 6503 opcode(0xC7); /* C7 /0 */ | |
| 6504 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 6505 ins_pipe( ialu_mem_imm ); | |
| 6506 %} | |
| 6507 | |
| 6508 // Store Integer to stack slot | |
|
6179
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|
6509 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 6510 match(Set dst src); |
| 6511 | |
| 6512 ins_cost(100); | |
| 6513 format %{ "MOV $dst,$src" %} | |
| 6514 opcode(0x89); | |
| 6515 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6516 ins_pipe( ialu_mem_reg ); | |
| 6517 %} | |
| 6518 | |
| 6519 // Store Integer to stack slot | |
| 6520 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 6521 match(Set dst src); | |
| 6522 | |
| 6523 ins_cost(100); | |
| 6524 format %{ "MOV $dst,$src" %} | |
| 6525 opcode(0x89); | |
| 6526 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6527 ins_pipe( ialu_mem_reg ); | |
| 6528 %} | |
| 6529 | |
| 6530 // Store Long to stack slot | |
| 6531 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 6532 match(Set dst src); | |
| 6533 | |
| 6534 ins_cost(200); | |
| 6535 format %{ "MOV $dst,$src.lo\n\t" | |
| 6536 "MOV $dst+4,$src.hi" %} | |
| 6537 opcode(0x89, 0x89); | |
| 6538 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 6539 ins_pipe( ialu_mem_long_reg ); | |
| 6540 %} | |
| 6541 | |
| 6542 //----------MemBar Instructions----------------------------------------------- | |
| 6543 // Memory barrier flavors | |
| 6544 | |
| 6545 instruct membar_acquire() %{ | |
| 6546 match(MemBarAcquire); | |
|
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diff
changeset
|
6547 match(LoadFence); |
| 0 | 6548 ins_cost(400); |
| 6549 | |
| 6550 size(0); | |
|
671
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diff
changeset
|
6551 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6552 ins_encode(); |
|
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never
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647
diff
changeset
|
6553 ins_pipe(empty); |
| 0 | 6554 %} |
| 6555 | |
| 6556 instruct membar_acquire_lock() %{ | |
|
3849
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diff
changeset
|
6557 match(MemBarAcquireLock); |
| 0 | 6558 ins_cost(0); |
| 6559 | |
| 6560 size(0); | |
| 6561 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6562 ins_encode( ); | |
| 6563 ins_pipe(empty); | |
| 6564 %} | |
| 6565 | |
| 6566 instruct membar_release() %{ | |
| 6567 match(MemBarRelease); | |
|
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diff
changeset
|
6568 match(StoreFence); |
| 0 | 6569 ins_cost(400); |
| 6570 | |
| 6571 size(0); | |
|
671
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diff
changeset
|
6572 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6573 ins_encode( ); |
|
d0994e5bebce
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never
parents:
647
diff
changeset
|
6574 ins_pipe(empty); |
| 0 | 6575 %} |
| 6576 | |
| 6577 instruct membar_release_lock() %{ | |
|
3849
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changeset
|
6578 match(MemBarReleaseLock); |
| 0 | 6579 ins_cost(0); |
| 6580 | |
| 6581 size(0); | |
| 6582 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6583 ins_encode( ); | |
| 6584 ins_pipe(empty); | |
| 6585 %} | |
| 6586 | |
|
671
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647
diff
changeset
|
6587 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 6588 match(MemBarVolatile); |
|
671
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never
parents:
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diff
changeset
|
6589 effect(KILL cr); |
| 0 | 6590 ins_cost(400); |
| 6591 | |
|
671
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parents:
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diff
changeset
|
6592 format %{ |
|
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parents:
647
diff
changeset
|
6593 $$template |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
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diff
changeset
|
6594 if (os::is_MP()) { |
|
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parents:
647
diff
changeset
|
6595 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6596 } else { |
|
d0994e5bebce
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never
parents:
647
diff
changeset
|
6597 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6598 } |
|
d0994e5bebce
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never
parents:
647
diff
changeset
|
6599 %} |
|
d0994e5bebce
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never
parents:
647
diff
changeset
|
6600 ins_encode %{ |
|
d0994e5bebce
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never
parents:
647
diff
changeset
|
6601 __ membar(Assembler::StoreLoad); |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
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647
diff
changeset
|
6602 %} |
| 0 | 6603 ins_pipe(pipe_slow); |
| 6604 %} | |
| 6605 | |
| 6606 instruct unnecessary_membar_volatile() %{ | |
| 6607 match(MemBarVolatile); | |
| 6608 predicate(Matcher::post_store_load_barrier(n)); | |
| 6609 ins_cost(0); | |
| 6610 | |
| 6611 size(0); | |
| 6612 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6613 ins_encode( ); | |
| 6614 ins_pipe(empty); | |
| 6615 %} | |
| 6616 | |
|
4763
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changeset
|
6617 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
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diff
changeset
|
6618 match(MemBarStoreStore); |
|
1dc233a8c7fe
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changeset
|
6619 ins_cost(0); |
|
1dc233a8c7fe
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changeset
|
6620 |
|
1dc233a8c7fe
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changeset
|
6621 size(0); |
|
1dc233a8c7fe
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changeset
|
6622 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
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changeset
|
6623 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
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changeset
|
6624 ins_pipe(empty); |
|
1dc233a8c7fe
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changeset
|
6625 %} |
|
1dc233a8c7fe
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diff
changeset
|
6626 |
| 0 | 6627 //----------Move Instructions-------------------------------------------------- |
| 6628 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 6629 match(Set dst (CastX2P src)); | |
| 6630 format %{ "# X2P $dst, $src" %} | |
| 6631 ins_encode( /*empty encoding*/ ); | |
| 6632 ins_cost(0); | |
| 6633 ins_pipe(empty); | |
| 6634 %} | |
| 6635 | |
|
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changeset
|
6636 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 6637 match(Set dst (CastP2X src)); |
| 6638 ins_cost(50); | |
| 6639 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 6640 ins_encode( enc_Copy( dst, src) ); | |
| 6641 ins_pipe( ialu_reg_reg ); | |
| 6642 %} | |
| 6643 | |
| 6644 //----------Conditional Move--------------------------------------------------- | |
| 6645 // Conditional move | |
|
6179
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changeset
|
6646 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 6647 predicate(!VM_Version::supports_cmov() ); |
| 6648 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6649 ins_cost(200); | |
| 6650 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 6651 "MOV $dst,$src\n" | |
| 6652 "skip:" %} | |
| 6653 ins_encode %{ | |
| 6654 Label Lskip; | |
| 6655 // Invert sense of branch from sense of CMOV | |
| 6656 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6657 __ movl($dst$$Register, $src$$Register); | |
| 6658 __ bind(Lskip); | |
| 6659 %} | |
| 6660 ins_pipe( pipe_cmov_reg ); | |
| 6661 %} | |
| 6662 | |
|
6179
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diff
changeset
|
6663 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 6664 predicate(!VM_Version::supports_cmov() ); |
| 6665 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6666 ins_cost(200); | |
| 6667 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 6668 "MOV $dst,$src\n" | |
| 6669 "skip:" %} | |
| 6670 ins_encode %{ | |
| 6671 Label Lskip; | |
| 6672 // Invert sense of branch from sense of CMOV | |
| 6673 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6674 __ movl($dst$$Register, $src$$Register); | |
| 6675 __ bind(Lskip); | |
| 6676 %} | |
| 6677 ins_pipe( pipe_cmov_reg ); | |
| 6678 %} | |
| 6679 | |
|
6179
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diff
changeset
|
6680 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 6681 predicate(VM_Version::supports_cmov() ); |
| 6682 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6683 ins_cost(200); | |
| 6684 format %{ "CMOV$cop $dst,$src" %} | |
| 6685 opcode(0x0F,0x40); | |
| 6686 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6687 ins_pipe( pipe_cmov_reg ); | |
| 6688 %} | |
| 6689 | |
|
6179
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6143
diff
changeset
|
6690 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 6691 predicate(VM_Version::supports_cmov() ); |
| 6692 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6693 ins_cost(200); | |
| 6694 format %{ "CMOV$cop $dst,$src" %} | |
| 6695 opcode(0x0F,0x40); | |
| 6696 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6697 ins_pipe( pipe_cmov_reg ); | |
| 6698 %} | |
| 6699 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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parents:
6143
diff
changeset
|
6700 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
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changeset
|
6701 predicate(VM_Version::supports_cmov() ); |
|
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|
6702 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
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diff
changeset
|
6703 ins_cost(200); |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
6704 expand %{ |
|
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diff
changeset
|
6705 cmovI_regU(cop, cr, dst, src); |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
6706 %} |
|
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never
parents:
403
diff
changeset
|
6707 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
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diff
changeset
|
6708 |
| 0 | 6709 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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6143
diff
changeset
|
6710 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6711 predicate(VM_Version::supports_cmov() ); |
| 6712 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6713 ins_cost(250); | |
| 6714 format %{ "CMOV$cop $dst,$src" %} | |
| 6715 opcode(0x0F,0x40); | |
| 6716 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6717 ins_pipe( pipe_cmov_mem ); | |
| 6718 %} | |
| 6719 | |
| 6720 // Conditional move | |
|
6179
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6143
diff
changeset
|
6721 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 6722 predicate(VM_Version::supports_cmov() ); |
| 6723 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6724 ins_cost(250); | |
| 6725 format %{ "CMOV$cop $dst,$src" %} | |
| 6726 opcode(0x0F,0x40); | |
| 6727 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6728 ins_pipe( pipe_cmov_mem ); | |
| 6729 %} | |
| 6730 | |
|
6179
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diff
changeset
|
6731 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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changeset
|
6732 predicate(VM_Version::supports_cmov() ); |
|
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diff
changeset
|
6733 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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diff
changeset
|
6734 ins_cost(250); |
|
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never
parents:
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diff
changeset
|
6735 expand %{ |
|
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diff
changeset
|
6736 cmovI_memU(cop, cr, dst, src); |
|
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diff
changeset
|
6737 %} |
|
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never
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diff
changeset
|
6738 %} |
|
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diff
changeset
|
6739 |
| 0 | 6740 // Conditional move |
| 6741 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6742 predicate(VM_Version::supports_cmov() ); | |
| 6743 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6744 ins_cost(200); | |
| 6745 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6746 opcode(0x0F,0x40); | |
| 6747 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6748 ins_pipe( pipe_cmov_reg ); | |
| 6749 %} | |
| 6750 | |
| 6751 // Conditional move (non-P6 version) | |
| 6752 // Note: a CMoveP is generated for stubs and native wrappers | |
| 6753 // regardless of whether we are on a P6, so we | |
| 6754 // emulate a cmov here | |
| 6755 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6756 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6757 ins_cost(300); | |
| 6758 format %{ "Jn$cop skip\n\t" | |
| 6759 "MOV $dst,$src\t# pointer\n" | |
| 6760 "skip:" %} | |
| 6761 opcode(0x8b); | |
| 6762 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 6763 ins_pipe( pipe_cmov_reg ); | |
| 6764 %} | |
| 6765 | |
| 6766 // Conditional move | |
|
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|
6767 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 6768 predicate(VM_Version::supports_cmov() ); |
| 6769 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6770 ins_cost(200); | |
| 6771 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6772 opcode(0x0F,0x40); | |
| 6773 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6774 ins_pipe( pipe_cmov_reg ); | |
| 6775 %} | |
| 6776 | |
|
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diff
changeset
|
6777 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
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diff
changeset
|
6778 predicate(VM_Version::supports_cmov() ); |
|
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diff
changeset
|
6779 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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diff
changeset
|
6780 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6781 expand %{ |
|
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403
diff
changeset
|
6782 cmovP_regU(cop, cr, dst, src); |
|
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403
diff
changeset
|
6783 %} |
|
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403
diff
changeset
|
6784 %} |
|
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parents:
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diff
changeset
|
6785 |
| 0 | 6786 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6787 // correctly meets the two pointer arguments; one is an incoming | |
| 6788 // register but the other is a memory operand. ALSO appears to | |
| 6789 // be buggy with implicit null checks. | |
| 6790 // | |
| 6791 //// Conditional move | |
| 6792 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 6793 // predicate(VM_Version::supports_cmov() ); | |
| 6794 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6795 // ins_cost(250); | |
| 6796 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6797 // opcode(0x0F,0x40); | |
| 6798 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6799 // ins_pipe( pipe_cmov_mem ); | |
| 6800 //%} | |
| 6801 // | |
| 6802 //// Conditional move | |
| 6803 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 6804 // predicate(VM_Version::supports_cmov() ); | |
| 6805 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6806 // ins_cost(250); | |
| 6807 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6808 // opcode(0x0F,0x40); | |
| 6809 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6810 // ins_pipe( pipe_cmov_mem ); | |
| 6811 //%} | |
| 6812 | |
| 6813 // Conditional move | |
|
4761
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diff
changeset
|
6814 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 6815 predicate(UseSSE<=1); |
| 6816 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6817 ins_cost(200); | |
| 6818 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 6819 opcode(0xDA); | |
|
4761
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diff
changeset
|
6820 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
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diff
changeset
|
6821 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6822 %} |
| 6823 | |
| 6824 // Conditional move | |
|
4761
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diff
changeset
|
6825 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 6826 predicate(UseSSE==0); |
| 6827 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6828 ins_cost(200); | |
| 6829 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 6830 opcode(0xDA); | |
|
4761
65149e74c706
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diff
changeset
|
6831 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
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diff
changeset
|
6832 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6833 %} |
| 6834 | |
| 6835 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
6836 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 6837 predicate(UseSSE<=1); |
| 6838 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6839 ins_cost(200); | |
| 6840 format %{ "Jn$cop skip\n\t" | |
| 6841 "MOV $dst,$src\t# double\n" | |
| 6842 "skip:" %} | |
| 6843 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6844 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
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kvn
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4759
diff
changeset
|
6845 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6846 %} |
| 6847 | |
| 6848 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
6849 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 6850 predicate(UseSSE==0); |
| 6851 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6852 ins_cost(200); | |
| 6853 format %{ "Jn$cop skip\n\t" | |
| 6854 "MOV $dst,$src\t# float\n" | |
| 6855 "skip:" %} | |
| 6856 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6857 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
6858 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6859 %} |
| 6860 | |
| 6861 // No CMOVE with SSE/SSE2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6862 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 6863 predicate (UseSSE>=1); |
| 6864 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6865 ins_cost(200); | |
| 6866 format %{ "Jn$cop skip\n\t" | |
| 6867 "MOVSS $dst,$src\t# float\n" | |
| 6868 "skip:" %} | |
| 6869 ins_encode %{ | |
| 6870 Label skip; | |
| 6871 // Invert sense of branch from sense of CMOV | |
| 6872 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6873 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6874 __ bind(skip); | |
| 6875 %} | |
| 6876 ins_pipe( pipe_slow ); | |
| 6877 %} | |
| 6878 | |
| 6879 // No CMOVE with SSE/SSE2 | |
|
4761
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diff
changeset
|
6880 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 6881 predicate (UseSSE>=2); |
| 6882 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6883 ins_cost(200); | |
| 6884 format %{ "Jn$cop skip\n\t" | |
| 6885 "MOVSD $dst,$src\t# float\n" | |
| 6886 "skip:" %} | |
| 6887 ins_encode %{ | |
| 6888 Label skip; | |
| 6889 // Invert sense of branch from sense of CMOV | |
| 6890 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6891 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6892 __ bind(skip); | |
| 6893 %} | |
| 6894 ins_pipe( pipe_slow ); | |
| 6895 %} | |
| 6896 | |
| 6897 // unsigned version | |
|
4761
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diff
changeset
|
6898 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 6899 predicate (UseSSE>=1); |
| 6900 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6901 ins_cost(200); | |
| 6902 format %{ "Jn$cop skip\n\t" | |
| 6903 "MOVSS $dst,$src\t# float\n" | |
| 6904 "skip:" %} | |
| 6905 ins_encode %{ | |
| 6906 Label skip; | |
| 6907 // Invert sense of branch from sense of CMOV | |
| 6908 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6909 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6910 __ bind(skip); | |
| 6911 %} | |
| 6912 ins_pipe( pipe_slow ); | |
| 6913 %} | |
| 6914 | |
|
4761
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diff
changeset
|
6915 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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diff
changeset
|
6916 predicate (UseSSE>=1); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
6917 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6918 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6919 expand %{ |
|
4761
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4759
diff
changeset
|
6920 fcmovF_regU(cop, cr, dst, src); |
|
415
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parents:
403
diff
changeset
|
6921 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6922 %} |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
6923 |
| 0 | 6924 // unsigned version |
|
4761
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diff
changeset
|
6925 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 6926 predicate (UseSSE>=2); |
| 6927 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6928 ins_cost(200); | |
| 6929 format %{ "Jn$cop skip\n\t" | |
| 6930 "MOVSD $dst,$src\t# float\n" | |
| 6931 "skip:" %} | |
| 6932 ins_encode %{ | |
| 6933 Label skip; | |
| 6934 // Invert sense of branch from sense of CMOV | |
| 6935 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6936 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6937 __ bind(skip); | |
| 6938 %} | |
| 6939 ins_pipe( pipe_slow ); | |
| 6940 %} | |
| 6941 | |
|
4761
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diff
changeset
|
6942 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
4d9884b01ba6
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parents:
403
diff
changeset
|
6943 predicate (UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6944 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6945 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6946 expand %{ |
|
4761
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diff
changeset
|
6947 fcmovD_regU(cop, cr, dst, src); |
|
415
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diff
changeset
|
6948 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6949 %} |
|
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parents:
403
diff
changeset
|
6950 |
| 0 | 6951 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 6952 predicate(VM_Version::supports_cmov() ); | |
| 6953 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6954 ins_cost(200); | |
| 6955 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6956 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6957 opcode(0x0F,0x40); | |
| 6958 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6959 ins_pipe( pipe_cmov_reg_long ); | |
| 6960 %} | |
| 6961 | |
| 6962 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 6963 predicate(VM_Version::supports_cmov() ); | |
| 6964 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6965 ins_cost(200); | |
| 6966 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6967 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6968 opcode(0x0F,0x40); | |
| 6969 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6970 ins_pipe( pipe_cmov_reg_long ); | |
| 6971 %} | |
| 6972 | |
|
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changeset
|
6973 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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403
diff
changeset
|
6974 predicate(VM_Version::supports_cmov() ); |
|
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changeset
|
6975 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
6976 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
6977 expand %{ |
|
4d9884b01ba6
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parents:
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diff
changeset
|
6978 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
6979 %} |
|
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never
parents:
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diff
changeset
|
6980 %} |
|
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parents:
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diff
changeset
|
6981 |
| 0 | 6982 //----------Arithmetic Instructions-------------------------------------------- |
| 6983 //----------Addition Instructions---------------------------------------------- | |
| 12323 | 6984 |
| 0 | 6985 // Integer Addition Instructions |
|
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|
6986 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 6987 match(Set dst (AddI dst src)); |
| 6988 effect(KILL cr); | |
| 6989 | |
| 6990 size(2); | |
| 6991 format %{ "ADD $dst,$src" %} | |
| 6992 opcode(0x03); | |
| 6993 ins_encode( OpcP, RegReg( dst, src) ); | |
| 6994 ins_pipe( ialu_reg_reg ); | |
| 6995 %} | |
| 6996 | |
|
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|
6997 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 6998 match(Set dst (AddI dst src)); |
| 6999 effect(KILL cr); | |
| 7000 | |
| 7001 format %{ "ADD $dst,$src" %} | |
| 7002 opcode(0x81, 0x00); /* /0 id */ | |
| 7003 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7004 ins_pipe( ialu_reg ); | |
| 7005 %} | |
| 7006 | |
|
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|
7007 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7008 predicate(UseIncDec); |
| 7009 match(Set dst (AddI dst src)); | |
| 7010 effect(KILL cr); | |
| 7011 | |
| 7012 size(1); | |
| 7013 format %{ "INC $dst" %} | |
| 7014 opcode(0x40); /* */ | |
| 7015 ins_encode( Opc_plus( primary, dst ) ); | |
| 7016 ins_pipe( ialu_reg ); | |
| 7017 %} | |
| 7018 | |
|
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|
7019 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7020 match(Set dst (AddI src0 src1)); |
| 7021 ins_cost(110); | |
| 7022 | |
| 7023 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7024 opcode(0x8D); /* 0x8D /r */ | |
| 7025 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7026 ins_pipe( ialu_reg_reg ); | |
| 7027 %} | |
| 7028 | |
| 7029 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7030 match(Set dst (AddP src0 src1)); | |
| 7031 ins_cost(110); | |
| 7032 | |
| 7033 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7034 opcode(0x8D); /* 0x8D /r */ | |
| 7035 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7036 ins_pipe( ialu_reg_reg ); | |
| 7037 %} | |
| 7038 | |
|
6179
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|
7039 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7040 predicate(UseIncDec); |
| 7041 match(Set dst (AddI dst src)); | |
| 7042 effect(KILL cr); | |
| 7043 | |
| 7044 size(1); | |
| 7045 format %{ "DEC $dst" %} | |
| 7046 opcode(0x48); /* */ | |
| 7047 ins_encode( Opc_plus( primary, dst ) ); | |
| 7048 ins_pipe( ialu_reg ); | |
| 7049 %} | |
| 7050 | |
|
6179
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|
7051 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7052 match(Set dst (AddP dst src)); |
| 7053 effect(KILL cr); | |
| 7054 | |
| 7055 size(2); | |
| 7056 format %{ "ADD $dst,$src" %} | |
| 7057 opcode(0x03); | |
| 7058 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7059 ins_pipe( ialu_reg_reg ); | |
| 7060 %} | |
| 7061 | |
| 7062 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7063 match(Set dst (AddP dst src)); | |
| 7064 effect(KILL cr); | |
| 7065 | |
| 7066 format %{ "ADD $dst,$src" %} | |
| 7067 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7068 // ins_encode( RegImm( dst, src) ); | |
| 7069 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7070 ins_pipe( ialu_reg ); | |
| 7071 %} | |
| 7072 | |
|
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|
7073 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7074 match(Set dst (AddI dst (LoadI src))); |
| 7075 effect(KILL cr); | |
| 7076 | |
| 7077 ins_cost(125); | |
| 7078 format %{ "ADD $dst,$src" %} | |
| 7079 opcode(0x03); | |
| 7080 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7081 ins_pipe( ialu_reg_mem ); | |
| 7082 %} | |
| 7083 | |
|
6179
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|
7084 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7085 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7086 effect(KILL cr); | |
| 7087 | |
| 7088 ins_cost(150); | |
| 7089 format %{ "ADD $dst,$src" %} | |
| 7090 opcode(0x01); /* Opcode 01 /r */ | |
| 7091 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7092 ins_pipe( ialu_mem_reg ); | |
| 7093 %} | |
| 7094 | |
| 7095 // Add Memory with Immediate | |
| 7096 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7097 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7098 effect(KILL cr); | |
| 7099 | |
| 7100 ins_cost(125); | |
| 7101 format %{ "ADD $dst,$src" %} | |
| 7102 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7103 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7104 ins_pipe( ialu_mem_imm ); | |
| 7105 %} | |
| 7106 | |
| 7107 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7108 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7109 effect(KILL cr); | |
| 7110 | |
| 7111 ins_cost(125); | |
| 7112 format %{ "INC $dst" %} | |
| 7113 opcode(0xFF); /* Opcode FF /0 */ | |
| 7114 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7115 ins_pipe( ialu_mem_imm ); | |
| 7116 %} | |
| 7117 | |
| 7118 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7119 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7120 effect(KILL cr); | |
| 7121 | |
| 7122 ins_cost(125); | |
| 7123 format %{ "DEC $dst" %} | |
| 7124 opcode(0xFF); /* Opcode FF /1 */ | |
| 7125 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7126 ins_pipe( ialu_mem_imm ); | |
| 7127 %} | |
| 7128 | |
| 7129 | |
| 7130 instruct checkCastPP( eRegP dst ) %{ | |
| 7131 match(Set dst (CheckCastPP dst)); | |
| 7132 | |
| 7133 size(0); | |
| 7134 format %{ "#checkcastPP of $dst" %} | |
| 7135 ins_encode( /*empty encoding*/ ); | |
| 7136 ins_pipe( empty ); | |
| 7137 %} | |
| 7138 | |
| 7139 instruct castPP( eRegP dst ) %{ | |
| 7140 match(Set dst (CastPP dst)); | |
| 7141 format %{ "#castPP of $dst" %} | |
| 7142 ins_encode( /*empty encoding*/ ); | |
| 7143 ins_pipe( empty ); | |
| 7144 %} | |
| 7145 | |
|
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diff
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|
7146 instruct castII( rRegI dst ) %{ |
| 0 | 7147 match(Set dst (CastII dst)); |
| 7148 format %{ "#castII of $dst" %} | |
| 7149 ins_encode( /*empty encoding*/ ); | |
| 7150 ins_cost(0); | |
| 7151 ins_pipe( empty ); | |
| 7152 %} | |
| 7153 | |
| 7154 | |
| 7155 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7156 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7157 match(Set dst (LoadPLocked mem)); | |
| 7158 | |
| 7159 ins_cost(125); | |
| 7160 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7161 opcode(0x8B); | |
| 7162 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7163 ins_pipe( ialu_reg_mem ); | |
| 7164 %} | |
| 7165 | |
| 7166 // Conditional-store of the updated heap-top. | |
| 7167 // Used during allocation of the shared heap. | |
| 7168 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7169 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7170 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7171 // EAX is killed if there is contention, but then it's also unused. | |
| 7172 // In the common case of no contention, EAX holds the new oop address. | |
| 7173 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7174 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7175 ins_pipe( pipe_cmpxchg ); | |
| 7176 %} | |
| 7177 | |
|
420
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415
diff
changeset
|
7178 // Conditional-store of an int value. |
|
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diff
changeset
|
7179 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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|
7180 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7181 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7182 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7183 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7184 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7185 ins_pipe( pipe_cmpxchg ); |
| 7186 %} | |
| 7187 | |
|
420
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diff
changeset
|
7188 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7189 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
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changeset
|
7190 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
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changeset
|
7191 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7192 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7193 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7194 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7195 "XCHG EBX,ECX" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7196 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7197 ins_encode %{ |
|
a1980da045cc
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changeset
|
7198 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
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|
7199 // cmpxchg8 instruction because the instruction uses |
|
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|
7200 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7201 // our register encoding uses rbx. |
|
a1980da045cc
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changeset
|
7202 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7203 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7204 __ lock(); |
| 624 | 7205 __ cmpxchg8($mem$$Address); |
|
420
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changeset
|
7206 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
7207 %} |
| 0 | 7208 ins_pipe( pipe_cmpxchg ); |
| 7209 %} | |
| 7210 | |
| 7211 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7212 | |
|
6179
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|
7213 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7214 predicate(VM_Version::supports_cx8()); |
| 0 | 7215 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7216 effect(KILL cr, KILL oldval); | |
| 7217 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7218 "MOV $res,0\n\t" | |
| 7219 "JNE,s fail\n\t" | |
| 7220 "MOV $res,1\n" | |
| 7221 "fail:" %} | |
| 7222 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7223 enc_flags_ne_to_boolean(res) ); | |
| 7224 ins_pipe( pipe_cmpxchg ); | |
| 7225 %} | |
| 7226 | |
|
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|
7227 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7228 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7229 effect(KILL cr, KILL oldval); | |
| 7230 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7231 "MOV $res,0\n\t" | |
| 7232 "JNE,s fail\n\t" | |
| 7233 "MOV $res,1\n" | |
| 7234 "fail:" %} | |
| 7235 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7236 ins_pipe( pipe_cmpxchg ); | |
| 7237 %} | |
| 7238 | |
|
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|
7239 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7240 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7241 effect(KILL cr, KILL oldval); | |
| 7242 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7243 "MOV $res,0\n\t" | |
| 7244 "JNE,s fail\n\t" | |
| 7245 "MOV $res,1\n" | |
| 7246 "fail:" %} | |
| 7247 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7248 ins_pipe( pipe_cmpxchg ); | |
| 7249 %} | |
| 7250 | |
|
6795
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|
7251 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
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|
7252 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
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|
7253 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
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|
7254 effect(KILL cr); |
|
7eca5de9e0b6
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|
7255 format %{ "ADDL [$mem],$add" %} |
|
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|
7256 ins_encode %{ |
|
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|
7257 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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|
7258 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7259 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7260 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7261 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7262 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7263 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7264 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7265 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7266 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7267 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7268 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7269 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7270 %} |
|
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diff
changeset
|
7271 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7272 %} |
|
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7273 |
|
7eca5de9e0b6
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parents:
6725
diff
changeset
|
7274 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7275 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7276 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7277 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7278 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7279 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7280 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7281 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7282 |
|
7eca5de9e0b6
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roland
parents:
6725
diff
changeset
|
7283 instruct xchgP( memory mem, pRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7284 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7285 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7286 ins_encode %{ |
|
7eca5de9e0b6
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6725
diff
changeset
|
7287 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7288 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7289 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7290 %} |
|
7eca5de9e0b6
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changeset
|
7291 |
| 0 | 7292 //----------Subtraction Instructions------------------------------------------- |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7293 |
| 0 | 7294 // Integer Subtraction Instructions |
|
6179
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diff
changeset
|
7295 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7296 match(Set dst (SubI dst src)); |
| 7297 effect(KILL cr); | |
| 7298 | |
| 7299 size(2); | |
| 7300 format %{ "SUB $dst,$src" %} | |
| 7301 opcode(0x2B); | |
| 7302 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7303 ins_pipe( ialu_reg_reg ); | |
| 7304 %} | |
| 7305 | |
|
6179
8c92982cbbc4
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diff
changeset
|
7306 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7307 match(Set dst (SubI dst src)); |
| 7308 effect(KILL cr); | |
| 7309 | |
| 7310 format %{ "SUB $dst,$src" %} | |
| 7311 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7312 // ins_encode( RegImm( dst, src) ); | |
| 7313 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7314 ins_pipe( ialu_reg ); | |
| 7315 %} | |
| 7316 | |
|
6179
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diff
changeset
|
7317 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7318 match(Set dst (SubI dst (LoadI src))); |
| 7319 effect(KILL cr); | |
| 7320 | |
| 7321 ins_cost(125); | |
| 7322 format %{ "SUB $dst,$src" %} | |
| 7323 opcode(0x2B); | |
| 7324 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7325 ins_pipe( ialu_reg_mem ); | |
| 7326 %} | |
| 7327 | |
|
6179
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diff
changeset
|
7328 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7329 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7330 effect(KILL cr); | |
| 7331 | |
| 7332 ins_cost(150); | |
| 7333 format %{ "SUB $dst,$src" %} | |
| 7334 opcode(0x29); /* Opcode 29 /r */ | |
| 7335 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7336 ins_pipe( ialu_mem_reg ); | |
| 7337 %} | |
| 7338 | |
| 7339 // Subtract from a pointer | |
|
6179
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kvn
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diff
changeset
|
7340 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7341 match(Set dst (AddP dst (SubI zero src))); |
| 7342 effect(KILL cr); | |
| 7343 | |
| 7344 size(2); | |
| 7345 format %{ "SUB $dst,$src" %} | |
| 7346 opcode(0x2B); | |
| 7347 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7348 ins_pipe( ialu_reg_reg ); | |
| 7349 %} | |
| 7350 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7351 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7352 match(Set dst (SubI zero dst)); |
| 7353 effect(KILL cr); | |
| 7354 | |
| 7355 size(2); | |
| 7356 format %{ "NEG $dst" %} | |
| 7357 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7358 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7359 ins_pipe( ialu_reg ); | |
| 7360 %} | |
| 7361 | |
| 7362 //----------Multiplication/Division Instructions------------------------------- | |
| 7363 // Integer Multiplication Instructions | |
| 7364 // Multiply Register | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
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6143
diff
changeset
|
7365 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7366 match(Set dst (MulI dst src)); |
| 7367 effect(KILL cr); | |
| 7368 | |
| 7369 size(3); | |
| 7370 ins_cost(300); | |
| 7371 format %{ "IMUL $dst,$src" %} | |
| 7372 opcode(0xAF, 0x0F); | |
| 7373 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7374 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7375 %} | |
| 7376 | |
| 7377 // Multiply 32-bit Immediate | |
|
6179
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kvn
parents:
6143
diff
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|
7378 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7379 match(Set dst (MulI src imm)); |
| 7380 effect(KILL cr); | |
| 7381 | |
| 7382 ins_cost(300); | |
| 7383 format %{ "IMUL $dst,$src,$imm" %} | |
| 7384 opcode(0x69); /* 69 /r id */ | |
| 7385 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7386 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7387 %} | |
| 7388 | |
| 7389 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7390 match(Set dst src); | |
| 7391 effect(KILL cr); | |
| 7392 | |
| 7393 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7394 ins_cost(250); | |
| 7395 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7396 opcode(0xB8); | |
| 7397 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7398 ins_pipe( ialu_reg_fat ); | |
| 7399 %} | |
| 7400 | |
| 7401 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7402 // (special case for shift by 32) | |
| 7403 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7404 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7405 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7406 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7407 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7408 effect(USE src1, KILL cr); | |
| 7409 | |
| 7410 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7411 ins_cost(0*100 + 1*400 - 150); | |
| 7412 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7413 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7414 ins_pipe( pipe_slow ); | |
| 7415 %} | |
| 7416 | |
| 7417 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7418 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7419 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7420 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7421 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7422 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7423 effect(USE src1, KILL cr); | |
| 7424 | |
| 7425 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7426 ins_cost(1*100 + 1*400 - 150); | |
| 7427 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7428 "SAR EDX,$cnt-32" %} | |
| 7429 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7430 ins_pipe( pipe_slow ); | |
| 7431 %} | |
| 7432 | |
| 7433 // Multiply Memory 32-bit Immediate | |
|
6179
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kvn
parents:
6143
diff
changeset
|
7434 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7435 match(Set dst (MulI (LoadI src) imm)); |
| 7436 effect(KILL cr); | |
| 7437 | |
| 7438 ins_cost(300); | |
| 7439 format %{ "IMUL $dst,$src,$imm" %} | |
| 7440 opcode(0x69); /* 69 /r id */ | |
| 7441 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7442 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7443 %} | |
| 7444 | |
| 7445 // Multiply Memory | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7446 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7447 match(Set dst (MulI dst (LoadI src))); |
| 7448 effect(KILL cr); | |
| 7449 | |
| 7450 ins_cost(350); | |
| 7451 format %{ "IMUL $dst,$src" %} | |
| 7452 opcode(0xAF, 0x0F); | |
| 7453 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 7454 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7455 %} | |
| 7456 | |
| 7457 // Multiply Register Int to Long | |
| 7458 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 7459 // Basic Idea: long = (long)int * (long)int | |
| 7460 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 7461 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 7462 | |
| 7463 ins_cost(300); | |
| 7464 format %{ "IMUL $dst,$src1" %} | |
| 7465 | |
| 7466 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 7467 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7468 %} | |
| 7469 | |
| 7470 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 7471 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 7472 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 7473 effect(KILL flags); | |
| 7474 | |
| 7475 ins_cost(300); | |
| 7476 format %{ "MUL $dst,$src1" %} | |
| 7477 | |
| 7478 ins_encode( long_uint_multiply(dst, src1) ); | |
| 7479 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7480 %} | |
| 7481 | |
| 7482 // Multiply Register Long | |
|
6179
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kvn
parents:
6143
diff
changeset
|
7483 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7484 match(Set dst (MulL dst src)); |
| 7485 effect(KILL cr, TEMP tmp); | |
| 7486 ins_cost(4*100+3*400); | |
| 7487 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 7488 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 7489 format %{ "MOV $tmp,$src.lo\n\t" | |
| 7490 "IMUL $tmp,EDX\n\t" | |
| 7491 "MOV EDX,$src.hi\n\t" | |
| 7492 "IMUL EDX,EAX\n\t" | |
| 7493 "ADD $tmp,EDX\n\t" | |
| 7494 "MUL EDX:EAX,$src.lo\n\t" | |
| 7495 "ADD EDX,$tmp" %} | |
| 7496 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 7497 ins_pipe( pipe_slow ); | |
| 7498 %} | |
| 7499 | |
|
1209
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1137
diff
changeset
|
7500 // Multiply Register Long where the left operand's high 32 bits are zero |
|
6179
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parents:
6143
diff
changeset
|
7501 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
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diff
changeset
|
7502 predicate(is_operand_hi32_zero(n->in(1))); |
|
e8443c7be117
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1137
diff
changeset
|
7503 match(Set dst (MulL dst src)); |
|
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parents:
1137
diff
changeset
|
7504 effect(KILL cr, TEMP tmp); |
|
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parents:
1137
diff
changeset
|
7505 ins_cost(2*100+2*400); |
|
e8443c7be117
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diff
changeset
|
7506 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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diff
changeset
|
7507 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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diff
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|
7508 format %{ "MOV $tmp,$src.hi\n\t" |
|
e8443c7be117
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diff
changeset
|
7509 "IMUL $tmp,EAX\n\t" |
|
e8443c7be117
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diff
changeset
|
7510 "MUL EDX:EAX,$src.lo\n\t" |
|
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1137
diff
changeset
|
7511 "ADD EDX,$tmp" %} |
|
e8443c7be117
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1137
diff
changeset
|
7512 ins_encode %{ |
|
e8443c7be117
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1137
diff
changeset
|
7513 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
e8443c7be117
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parents:
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diff
changeset
|
7514 __ imull($tmp$$Register, rax); |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7515 __ mull($src$$Register); |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7516 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
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diff
changeset
|
7517 %} |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7518 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
7519 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7520 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7521 // Multiply Register Long where the right operand's high 32 bits are zero |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7522 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
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diff
changeset
|
7523 predicate(is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
7524 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7525 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7526 ins_cost(2*100+2*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7527 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7528 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7529 format %{ "MOV $tmp,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7530 "IMUL $tmp,EDX\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7531 "MUL EDX:EAX,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7532 "ADD EDX,$tmp" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7533 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7534 __ movl($tmp$$Register, $src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7535 __ imull($tmp$$Register, rdx); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7536 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7537 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7538 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7539 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7540 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7541 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7542 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7543 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7544 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7545 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7546 effect(KILL cr); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7547 ins_cost(1*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7548 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7549 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7550 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7551 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7552 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7553 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7554 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7555 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7556 |
| 0 | 7557 // Multiply Register Long by small constant |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7558 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7559 match(Set dst (MulL dst src)); |
| 7560 effect(KILL cr, TEMP tmp); | |
| 7561 ins_cost(2*100+2*400); | |
| 7562 size(12); | |
| 7563 // Basic idea: lo(result) = lo(src * EAX) | |
| 7564 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 7565 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 7566 "MOV EDX,$src\n\t" | |
| 7567 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 7568 "ADD EDX,$tmp" %} | |
| 7569 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 7570 ins_pipe( pipe_slow ); | |
| 7571 %} | |
| 7572 | |
| 7573 // Integer DIV with Register | |
| 7574 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7575 match(Set rax (DivI rax div)); | |
| 7576 effect(KILL rdx, KILL cr); | |
| 7577 size(26); | |
| 7578 ins_cost(30*100+10*100); | |
| 7579 format %{ "CMP EAX,0x80000000\n\t" | |
| 7580 "JNE,s normal\n\t" | |
| 7581 "XOR EDX,EDX\n\t" | |
| 7582 "CMP ECX,-1\n\t" | |
| 7583 "JE,s done\n" | |
| 7584 "normal: CDQ\n\t" | |
| 7585 "IDIV $div\n\t" | |
| 7586 "done:" %} | |
| 7587 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7588 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7589 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7590 %} | |
| 7591 | |
| 7592 // Divide Register Long | |
| 7593 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7594 match(Set dst (DivL src1 src2)); | |
| 7595 effect( KILL cr, KILL cx, KILL bx ); | |
| 7596 ins_cost(10000); | |
| 7597 format %{ "PUSH $src1.hi\n\t" | |
| 7598 "PUSH $src1.lo\n\t" | |
| 7599 "PUSH $src2.hi\n\t" | |
| 7600 "PUSH $src2.lo\n\t" | |
| 7601 "CALL SharedRuntime::ldiv\n\t" | |
| 7602 "ADD ESP,16" %} | |
| 7603 ins_encode( long_div(src1,src2) ); | |
| 7604 ins_pipe( pipe_slow ); | |
| 7605 %} | |
| 7606 | |
| 7607 // Integer DIVMOD with Register, both quotient and mod results | |
| 7608 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7609 match(DivModI rax div); | |
| 7610 effect(KILL cr); | |
| 7611 size(26); | |
| 7612 ins_cost(30*100+10*100); | |
| 7613 format %{ "CMP EAX,0x80000000\n\t" | |
| 7614 "JNE,s normal\n\t" | |
| 7615 "XOR EDX,EDX\n\t" | |
| 7616 "CMP ECX,-1\n\t" | |
| 7617 "JE,s done\n" | |
| 7618 "normal: CDQ\n\t" | |
| 7619 "IDIV $div\n\t" | |
| 7620 "done:" %} | |
| 7621 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7622 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7623 ins_pipe( pipe_slow ); | |
| 7624 %} | |
| 7625 | |
| 7626 // Integer MOD with Register | |
| 7627 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 7628 match(Set rdx (ModI rax div)); | |
| 7629 effect(KILL rax, KILL cr); | |
| 7630 | |
| 7631 size(26); | |
| 7632 ins_cost(300); | |
| 7633 format %{ "CDQ\n\t" | |
| 7634 "IDIV $div" %} | |
| 7635 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7636 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7637 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7638 %} | |
| 7639 | |
| 7640 // Remainder Register Long | |
| 7641 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7642 match(Set dst (ModL src1 src2)); | |
| 7643 effect( KILL cr, KILL cx, KILL bx ); | |
| 7644 ins_cost(10000); | |
| 7645 format %{ "PUSH $src1.hi\n\t" | |
| 7646 "PUSH $src1.lo\n\t" | |
| 7647 "PUSH $src2.hi\n\t" | |
| 7648 "PUSH $src2.lo\n\t" | |
| 7649 "CALL SharedRuntime::lrem\n\t" | |
| 7650 "ADD ESP,16" %} | |
| 7651 ins_encode( long_mod(src1,src2) ); | |
| 7652 ins_pipe( pipe_slow ); | |
| 7653 %} | |
| 7654 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7655 // Divide Register Long (no special case since divisor != -1) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7656 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7657 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7658 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7659 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7660 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 7661 "XOR $tmp2,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7662 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7663 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7664 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7665 "MOV EAX,EDX\n\t" |
| 1920 | 7666 "MOV EDX,0\n\t" |
| 7667 "JLE,s pos\n\t" | |
| 7668 "LNEG EAX : $tmp2\n\t" | |
| 7669 "DIV $tmp # unsigned division\n\t" | |
| 7670 "XCHG EAX,$tmp2\n\t" | |
| 7671 "DIV $tmp\n\t" | |
| 7672 "LNEG $tmp2 : EAX\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7673 "JMP,s done\n" |
| 1920 | 7674 "pos:\n\t" |
| 7675 "DIV $tmp\n\t" | |
| 7676 "XCHG EAX,$tmp2\n" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7677 "fast:\n\t" |
| 1920 | 7678 "DIV $tmp\n" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7679 "done:\n\t" |
| 1920 | 7680 "MOV EDX,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7681 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7682 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7683 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7684 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7685 int pcon = (con > 0) ? con : -con; |
| 1920 | 7686 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7687 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7688 __ movl($tmp$$Register, pcon); |
| 1920 | 7689 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7690 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7691 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7692 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7693 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7694 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7695 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7696 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7697 | |
| 7698 // Negative dividend. | |
| 7699 // convert value to positive to use unsigned division | |
| 7700 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7701 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7702 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 7703 __ divl($tmp$$Register); |
| 7704 // revert result back to negative | |
| 7705 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7706 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7707 |
| 1920 | 7708 __ bind(Lpos); |
| 7709 __ divl($tmp$$Register); // Use unsigned division | |
| 7710 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 7711 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 7712 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7713 __ bind(Lfast); |
| 1920 | 7714 // fast path: src is positive |
| 7715 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7716 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7717 __ bind(Ldone); |
| 1920 | 7718 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7719 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7720 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7721 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7722 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7723 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7724 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7725 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7726 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7727 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7728 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7729 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7730 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7731 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
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diff
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|
7732 "CMP $tmp,EDX\n\t" |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
7733 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
7734 "MOV $tmp2,EAX\n\t" |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
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|
7735 "MOV EAX,EDX\n\t" |
| 1920 | 7736 "MOV EDX,0\n\t" |
| 7737 "JLE,s pos\n\t" | |
| 7738 "LNEG EAX : $tmp2\n\t" | |
| 7739 "DIV $tmp # unsigned division\n\t" | |
| 7740 "MOV EAX,$tmp2\n\t" | |
| 7741 "DIV $tmp\n\t" | |
| 7742 "NEG EDX\n\t" | |
| 7743 "JMP,s done\n" | |
| 7744 "pos:\n\t" | |
| 7745 "DIV $tmp\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7746 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7747 "fast:\n\t" |
| 1920 | 7748 "DIV $tmp\n" |
| 7749 "done:\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
7750 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
7751 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
7752 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
changeset
|
7753 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7754 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7755 int pcon = (con > 0) ? con : -con; |
| 1920 | 7756 Label Lfast, Lpos, Ldone; |
|
1914
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diff
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|
7757 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
changeset
|
7758 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7759 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7760 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
7761 |
|
ae065c367d93
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|
7762 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
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|
7763 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7764 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7765 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7766 | |
| 7767 // Negative dividend. | |
| 7768 // convert value to positive to use unsigned division | |
| 7769 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7770 __ divl($tmp$$Register); | |
| 7771 __ movl($dst$$Register, $tmp2$$Register); | |
| 7772 __ divl($tmp$$Register); | |
| 7773 // revert remainder back to negative | |
| 7774 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 7775 __ jmpb(Ldone); | |
| 7776 | |
| 7777 __ bind(Lpos); | |
| 7778 __ divl($tmp$$Register); | |
|
1914
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|
7779 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
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|
7780 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
changeset
|
7781 __ bind(Lfast); |
| 1920 | 7782 // fast path: src is positive |
| 7783 __ divl($tmp$$Register); | |
| 7784 | |
| 7785 __ bind(Ldone); | |
|
1914
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|
7786 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
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|
7787 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
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diff
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|
7788 |
|
ae065c367d93
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kvn
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diff
changeset
|
7789 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7790 ins_pipe( pipe_slow ); |
|
ae065c367d93
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kvn
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1748
diff
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|
7791 %} |
|
ae065c367d93
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|
7792 |
| 0 | 7793 // Integer Shift Instructions |
| 7794 // Shift Left by one | |
|
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|
7795 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7796 match(Set dst (LShiftI dst shift)); |
| 7797 effect(KILL cr); | |
| 7798 | |
| 7799 size(2); | |
| 7800 format %{ "SHL $dst,$shift" %} | |
| 7801 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7802 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7803 ins_pipe( ialu_reg ); | |
| 7804 %} | |
| 7805 | |
| 7806 // Shift Left by 8-bit immediate | |
|
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|
7807 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7808 match(Set dst (LShiftI dst shift)); |
| 7809 effect(KILL cr); | |
| 7810 | |
| 7811 size(3); | |
| 7812 format %{ "SHL $dst,$shift" %} | |
| 7813 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7814 ins_encode( RegOpcImm( dst, shift) ); | |
| 7815 ins_pipe( ialu_reg ); | |
| 7816 %} | |
| 7817 | |
| 7818 // Shift Left by variable | |
|
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|
7819 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7820 match(Set dst (LShiftI dst shift)); |
| 7821 effect(KILL cr); | |
| 7822 | |
| 7823 size(2); | |
| 7824 format %{ "SHL $dst,$shift" %} | |
| 7825 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7826 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7827 ins_pipe( ialu_reg_reg ); | |
| 7828 %} | |
| 7829 | |
| 7830 // Arithmetic shift right by one | |
|
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|
7831 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7832 match(Set dst (RShiftI dst shift)); |
| 7833 effect(KILL cr); | |
| 7834 | |
| 7835 size(2); | |
| 7836 format %{ "SAR $dst,$shift" %} | |
| 7837 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7838 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7839 ins_pipe( ialu_reg ); | |
| 7840 %} | |
| 7841 | |
| 7842 // Arithmetic shift right by one | |
| 7843 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 7844 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7845 effect(KILL cr); | |
| 7846 format %{ "SAR $dst,$shift" %} | |
| 7847 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7848 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 7849 ins_pipe( ialu_mem_imm ); | |
| 7850 %} | |
| 7851 | |
| 7852 // Arithmetic Shift Right by 8-bit immediate | |
|
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|
7853 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7854 match(Set dst (RShiftI dst shift)); |
| 7855 effect(KILL cr); | |
| 7856 | |
| 7857 size(3); | |
| 7858 format %{ "SAR $dst,$shift" %} | |
| 7859 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7860 ins_encode( RegOpcImm( dst, shift ) ); | |
| 7861 ins_pipe( ialu_mem_imm ); | |
| 7862 %} | |
| 7863 | |
| 7864 // Arithmetic Shift Right by 8-bit immediate | |
| 7865 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 7866 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7867 effect(KILL cr); | |
| 7868 | |
| 7869 format %{ "SAR $dst,$shift" %} | |
| 7870 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7871 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 7872 ins_pipe( ialu_mem_imm ); | |
| 7873 %} | |
| 7874 | |
| 7875 // Arithmetic Shift Right by variable | |
|
6179
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|
7876 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7877 match(Set dst (RShiftI dst shift)); |
| 7878 effect(KILL cr); | |
| 7879 | |
| 7880 size(2); | |
| 7881 format %{ "SAR $dst,$shift" %} | |
| 7882 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7883 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7884 ins_pipe( ialu_reg_reg ); | |
| 7885 %} | |
| 7886 | |
| 7887 // Logical shift right by one | |
|
6179
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|
7888 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7889 match(Set dst (URShiftI dst shift)); |
| 7890 effect(KILL cr); | |
| 7891 | |
| 7892 size(2); | |
| 7893 format %{ "SHR $dst,$shift" %} | |
| 7894 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7895 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7896 ins_pipe( ialu_reg ); | |
| 7897 %} | |
| 7898 | |
| 7899 // Logical Shift Right by 8-bit immediate | |
|
6179
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changeset
|
7900 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7901 match(Set dst (URShiftI dst shift)); |
| 7902 effect(KILL cr); | |
| 7903 | |
| 7904 size(3); | |
| 7905 format %{ "SHR $dst,$shift" %} | |
| 7906 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7907 ins_encode( RegOpcImm( dst, shift) ); | |
| 7908 ins_pipe( ialu_reg ); | |
| 7909 %} | |
| 7910 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
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|
7911 |
| 0 | 7912 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 7913 // This idiom is used by the compiler for the i2b bytecode. | |
|
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|
7914 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 7915 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 7916 | |
| 7917 size(3); | |
| 7918 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 7919 ins_encode %{ |
| 7920 __ movsbl($dst$$Register, $src$$Register); | |
| 7921 %} | |
| 7922 ins_pipe(ialu_reg_reg); | |
| 0 | 7923 %} |
| 7924 | |
| 7925 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 7926 // This idiom is used by the compiler the i2s bytecode. | |
|
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|
7927 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 7928 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 7929 | |
| 7930 size(3); | |
| 7931 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 7932 ins_encode %{ |
| 7933 __ movswl($dst$$Register, $src$$Register); | |
| 7934 %} | |
| 7935 ins_pipe(ialu_reg_reg); | |
| 0 | 7936 %} |
| 7937 | |
| 7938 | |
| 7939 // Logical Shift Right by variable | |
|
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|
7940 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7941 match(Set dst (URShiftI dst shift)); |
| 7942 effect(KILL cr); | |
| 7943 | |
| 7944 size(2); | |
| 7945 format %{ "SHR $dst,$shift" %} | |
| 7946 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 7947 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7948 ins_pipe( ialu_reg_reg ); | |
| 7949 %} | |
| 7950 | |
| 7951 | |
| 7952 //----------Logical Instructions----------------------------------------------- | |
| 7953 //----------Integer Logical Instructions--------------------------------------- | |
| 7954 // And Instructions | |
| 7955 // And Register with Register | |
|
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|
7956 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7957 match(Set dst (AndI dst src)); |
| 7958 effect(KILL cr); | |
| 7959 | |
| 7960 size(2); | |
| 7961 format %{ "AND $dst,$src" %} | |
| 7962 opcode(0x23); | |
| 7963 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7964 ins_pipe( ialu_reg_reg ); | |
| 7965 %} | |
| 7966 | |
| 7967 // And Register with Immediate | |
|
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|
7968 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7969 match(Set dst (AndI dst src)); |
| 7970 effect(KILL cr); | |
| 7971 | |
| 7972 format %{ "AND $dst,$src" %} | |
| 7973 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 7974 // ins_encode( RegImm( dst, src) ); | |
| 7975 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7976 ins_pipe( ialu_reg ); | |
| 7977 %} | |
| 7978 | |
| 7979 // And Register with Memory | |
|
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|
7980 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7981 match(Set dst (AndI dst (LoadI src))); |
| 7982 effect(KILL cr); | |
| 7983 | |
| 7984 ins_cost(125); | |
| 7985 format %{ "AND $dst,$src" %} | |
| 7986 opcode(0x23); | |
| 7987 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7988 ins_pipe( ialu_reg_mem ); | |
| 7989 %} | |
| 7990 | |
| 7991 // And Memory with Register | |
|
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|
7992 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7993 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 7994 effect(KILL cr); | |
| 7995 | |
| 7996 ins_cost(150); | |
| 7997 format %{ "AND $dst,$src" %} | |
| 7998 opcode(0x21); /* Opcode 21 /r */ | |
| 7999 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8000 ins_pipe( ialu_mem_reg ); | |
| 8001 %} | |
| 8002 | |
| 8003 // And Memory with Immediate | |
| 8004 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8005 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8006 effect(KILL cr); | |
| 8007 | |
| 8008 ins_cost(125); | |
| 8009 format %{ "AND $dst,$src" %} | |
| 8010 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8011 // ins_encode( MemImm( dst, src) ); | |
| 8012 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8013 ins_pipe( ialu_mem_imm ); | |
| 8014 %} | |
| 8015 | |
|
17729
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|
8016 // BMI1 instructions |
|
8a8ff6b577ed
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|
8017 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
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|
8018 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
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|
8019 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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|
8020 effect(KILL cr); |
|
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|
8021 |
|
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|
8022 format %{ "ANDNL $dst, $src1, $src2" %} |
|
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|
8023 |
|
8a8ff6b577ed
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changeset
|
8024 ins_encode %{ |
|
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changeset
|
8025 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8a8ff6b577ed
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|
8026 %} |
|
8a8ff6b577ed
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|
8027 ins_pipe(ialu_reg); |
|
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|
8028 %} |
|
8a8ff6b577ed
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|
8029 |
|
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changeset
|
8030 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8031 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8032 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8033 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8034 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8035 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8036 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8037 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8038 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8039 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8040 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8041 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8042 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8043 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8044 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8045 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8046 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8047 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8048 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8049 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8050 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8051 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8052 __ blsil($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8053 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8054 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8055 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8056 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8057 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8058 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8059 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8060 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8061 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8062 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8063 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8064 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8065 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8066 __ blsil($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8067 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8068 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8069 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8070 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8071 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8072 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8073 match(Set dst (XorI (AddI src minus_1) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8074 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8075 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8076 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8077 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8078 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8079 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8080 __ blsmskl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8081 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8082 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8083 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8084 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8085 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8086 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8087 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8088 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8089 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8090 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8091 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8092 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8093 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8094 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8095 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8096 __ blsmskl($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8097 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8098 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8099 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8100 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8101 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8102 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8103 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8104 match(Set dst (AndI (AddI src minus_1) src) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8105 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8106 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8107 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8108 format %{ "BLSRL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8109 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8110 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8111 __ blsrl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8112 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8113 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8114 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8115 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8116 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8117 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8118 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8119 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8120 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8121 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8122 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8123 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8124 format %{ "BLSRL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8125 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8126 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8127 __ blsrl($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8128 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8129 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8130 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8131 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8132 |
| 0 | 8133 // Or Instructions |
| 8134 // Or Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8135 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8136 match(Set dst (OrI dst src)); |
| 8137 effect(KILL cr); | |
| 8138 | |
| 8139 size(2); | |
| 8140 format %{ "OR $dst,$src" %} | |
| 8141 opcode(0x0B); | |
| 8142 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8143 ins_pipe( ialu_reg_reg ); | |
| 8144 %} | |
| 8145 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8146 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8147 match(Set dst (OrI dst (CastP2X src))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8148 effect(KILL cr); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8149 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8150 size(2); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8151 format %{ "OR $dst,$src" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8152 opcode(0x0B); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8153 ins_encode( OpcP, RegReg( dst, src) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8154 ins_pipe( ialu_reg_reg ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8155 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8156 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8157 |
| 0 | 8158 // Or Register with Immediate |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8159 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8160 match(Set dst (OrI dst src)); |
| 8161 effect(KILL cr); | |
| 8162 | |
| 8163 format %{ "OR $dst,$src" %} | |
| 8164 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8165 // ins_encode( RegImm( dst, src) ); | |
| 8166 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8167 ins_pipe( ialu_reg ); | |
| 8168 %} | |
| 8169 | |
| 8170 // Or Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8171 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8172 match(Set dst (OrI dst (LoadI src))); |
| 8173 effect(KILL cr); | |
| 8174 | |
| 8175 ins_cost(125); | |
| 8176 format %{ "OR $dst,$src" %} | |
| 8177 opcode(0x0B); | |
| 8178 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8179 ins_pipe( ialu_reg_mem ); | |
| 8180 %} | |
| 8181 | |
| 8182 // Or Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8183 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8184 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8185 effect(KILL cr); | |
| 8186 | |
| 8187 ins_cost(150); | |
| 8188 format %{ "OR $dst,$src" %} | |
| 8189 opcode(0x09); /* Opcode 09 /r */ | |
| 8190 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8191 ins_pipe( ialu_mem_reg ); | |
| 8192 %} | |
| 8193 | |
| 8194 // Or Memory with Immediate | |
| 8195 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8196 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8197 effect(KILL cr); | |
| 8198 | |
| 8199 ins_cost(125); | |
| 8200 format %{ "OR $dst,$src" %} | |
| 8201 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8202 // ins_encode( MemImm( dst, src) ); | |
| 8203 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8204 ins_pipe( ialu_mem_imm ); | |
| 8205 %} | |
| 8206 | |
| 8207 // ROL/ROR | |
| 8208 // ROL expand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8209 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8210 effect(USE_DEF dst, USE shift, KILL cr); |
| 8211 | |
| 8212 format %{ "ROL $dst, $shift" %} | |
| 8213 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8214 ins_encode( OpcP, RegOpc( dst )); | |
| 8215 ins_pipe( ialu_reg ); | |
| 8216 %} | |
| 8217 | |
|
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8218 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8219 effect(USE_DEF dst, USE shift, KILL cr); |
| 8220 | |
| 8221 format %{ "ROL $dst, $shift" %} | |
| 8222 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8223 ins_encode( RegOpcImm(dst, shift) ); | |
| 8224 ins_pipe(ialu_reg); | |
| 8225 %} | |
| 8226 | |
| 8227 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8228 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8229 | |
| 8230 format %{ "ROL $dst, $shift" %} | |
| 8231 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8232 ins_encode(OpcP, RegOpc(dst)); | |
| 8233 ins_pipe( ialu_reg_reg ); | |
| 8234 %} | |
| 8235 // end of ROL expand | |
| 8236 | |
| 8237 // ROL 32bit by one once | |
|
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8238 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8239 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8240 | |
| 8241 expand %{ | |
| 8242 rolI_eReg_imm1(dst, lshift, cr); | |
| 8243 %} | |
| 8244 %} | |
| 8245 | |
| 8246 // ROL 32bit var by imm8 once | |
|
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8247 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8248 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8249 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8250 | |
| 8251 expand %{ | |
| 8252 rolI_eReg_imm8(dst, lshift, cr); | |
| 8253 %} | |
| 8254 %} | |
| 8255 | |
| 8256 // ROL 32bit var by var once | |
| 8257 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8258 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8259 | |
| 8260 expand %{ | |
| 8261 rolI_eReg_CL(dst, shift, cr); | |
| 8262 %} | |
| 8263 %} | |
| 8264 | |
| 8265 // ROL 32bit var by var once | |
| 8266 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8267 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8268 | |
| 8269 expand %{ | |
| 8270 rolI_eReg_CL(dst, shift, cr); | |
| 8271 %} | |
| 8272 %} | |
| 8273 | |
| 8274 // ROR expand | |
|
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8275 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8276 effect(USE_DEF dst, USE shift, KILL cr); |
| 8277 | |
| 8278 format %{ "ROR $dst, $shift" %} | |
| 8279 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8280 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8281 ins_pipe( ialu_reg ); | |
| 8282 %} | |
| 8283 | |
|
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8284 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8285 effect (USE_DEF dst, USE shift, KILL cr); |
| 8286 | |
| 8287 format %{ "ROR $dst, $shift" %} | |
| 8288 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8289 ins_encode( RegOpcImm(dst, shift) ); | |
| 8290 ins_pipe( ialu_reg ); | |
| 8291 %} | |
| 8292 | |
| 8293 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8294 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8295 | |
| 8296 format %{ "ROR $dst, $shift" %} | |
| 8297 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8298 ins_encode(OpcP, RegOpc(dst)); | |
| 8299 ins_pipe( ialu_reg_reg ); | |
| 8300 %} | |
| 8301 // end of ROR expand | |
| 8302 | |
| 8303 // ROR right once | |
|
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8304 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8305 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8306 | |
| 8307 expand %{ | |
| 8308 rorI_eReg_imm1(dst, rshift, cr); | |
| 8309 %} | |
| 8310 %} | |
| 8311 | |
| 8312 // ROR 32bit by immI8 once | |
|
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8313 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8314 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8315 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8316 | |
| 8317 expand %{ | |
| 8318 rorI_eReg_imm8(dst, rshift, cr); | |
| 8319 %} | |
| 8320 %} | |
| 8321 | |
| 8322 // ROR 32bit var by var once | |
| 8323 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8324 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8325 | |
| 8326 expand %{ | |
| 8327 rorI_eReg_CL(dst, shift, cr); | |
| 8328 %} | |
| 8329 %} | |
| 8330 | |
| 8331 // ROR 32bit var by var once | |
| 8332 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8333 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8334 | |
| 8335 expand %{ | |
| 8336 rorI_eReg_CL(dst, shift, cr); | |
| 8337 %} | |
| 8338 %} | |
| 8339 | |
| 8340 // Xor Instructions | |
| 8341 // Xor Register with Register | |
|
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8342 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8343 match(Set dst (XorI dst src)); |
| 8344 effect(KILL cr); | |
| 8345 | |
| 8346 size(2); | |
| 8347 format %{ "XOR $dst,$src" %} | |
| 8348 opcode(0x33); | |
| 8349 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8350 ins_pipe( ialu_reg_reg ); | |
| 8351 %} | |
| 8352 | |
| 403 | 8353 // Xor Register with Immediate -1 |
|
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8354 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8355 match(Set dst (XorI dst imm)); |
| 8356 | |
| 8357 size(2); | |
| 8358 format %{ "NOT $dst" %} | |
| 8359 ins_encode %{ | |
| 8360 __ notl($dst$$Register); | |
| 8361 %} | |
| 8362 ins_pipe( ialu_reg ); | |
| 8363 %} | |
| 8364 | |
| 0 | 8365 // Xor Register with Immediate |
|
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8366 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8367 match(Set dst (XorI dst src)); |
| 8368 effect(KILL cr); | |
| 8369 | |
| 8370 format %{ "XOR $dst,$src" %} | |
| 8371 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8372 // ins_encode( RegImm( dst, src) ); | |
| 8373 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8374 ins_pipe( ialu_reg ); | |
| 8375 %} | |
| 8376 | |
| 8377 // Xor Register with Memory | |
|
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8378 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8379 match(Set dst (XorI dst (LoadI src))); |
| 8380 effect(KILL cr); | |
| 8381 | |
| 8382 ins_cost(125); | |
| 8383 format %{ "XOR $dst,$src" %} | |
| 8384 opcode(0x33); | |
| 8385 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8386 ins_pipe( ialu_reg_mem ); | |
| 8387 %} | |
| 8388 | |
| 8389 // Xor Memory with Register | |
|
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8390 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8391 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8392 effect(KILL cr); | |
| 8393 | |
| 8394 ins_cost(150); | |
| 8395 format %{ "XOR $dst,$src" %} | |
| 8396 opcode(0x31); /* Opcode 31 /r */ | |
| 8397 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8398 ins_pipe( ialu_mem_reg ); | |
| 8399 %} | |
| 8400 | |
| 8401 // Xor Memory with Immediate | |
| 8402 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8403 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8404 effect(KILL cr); | |
| 8405 | |
| 8406 ins_cost(125); | |
| 8407 format %{ "XOR $dst,$src" %} | |
| 8408 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8409 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8410 ins_pipe( ialu_mem_imm ); | |
| 8411 %} | |
| 8412 | |
| 8413 //----------Convert Int to Boolean--------------------------------------------- | |
| 8414 | |
|
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8415 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8416 effect( DEF dst, USE src ); |
| 8417 format %{ "MOV $dst,$src" %} | |
| 8418 ins_encode( enc_Copy( dst, src) ); | |
| 8419 ins_pipe( ialu_reg_reg ); | |
| 8420 %} | |
| 8421 | |
|
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8422 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8423 effect( USE_DEF dst, USE src, KILL cr ); |
| 8424 | |
| 8425 size(4); | |
| 8426 format %{ "NEG $dst\n\t" | |
| 8427 "ADC $dst,$src" %} | |
| 8428 ins_encode( neg_reg(dst), | |
| 8429 OpcRegReg(0x13,dst,src) ); | |
| 8430 ins_pipe( ialu_reg_reg_long ); | |
| 8431 %} | |
| 8432 | |
|
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8433 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8434 match(Set dst (Conv2B src)); |
| 8435 | |
| 8436 expand %{ | |
| 8437 movI_nocopy(dst,src); | |
| 8438 ci2b(dst,src,cr); | |
| 8439 %} | |
| 8440 %} | |
| 8441 | |
|
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8442 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8443 effect( DEF dst, USE src ); |
| 8444 format %{ "MOV $dst,$src" %} | |
| 8445 ins_encode( enc_Copy( dst, src) ); | |
| 8446 ins_pipe( ialu_reg_reg ); | |
| 8447 %} | |
| 8448 | |
|
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8449 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8450 effect( USE_DEF dst, USE src, KILL cr ); |
| 8451 format %{ "NEG $dst\n\t" | |
| 8452 "ADC $dst,$src" %} | |
| 8453 ins_encode( neg_reg(dst), | |
| 8454 OpcRegReg(0x13,dst,src) ); | |
| 8455 ins_pipe( ialu_reg_reg_long ); | |
| 8456 %} | |
| 8457 | |
|
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8458 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8459 match(Set dst (Conv2B src)); |
| 8460 | |
| 8461 expand %{ | |
| 8462 movP_nocopy(dst,src); | |
| 8463 cp2b(dst,src,cr); | |
| 8464 %} | |
| 8465 %} | |
| 8466 | |
| 9154 | 8467 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{ |
| 0 | 8468 match(Set dst (CmpLTMask p q)); |
| 9154 | 8469 effect(KILL cr); |
| 0 | 8470 ins_cost(400); |
| 8471 | |
| 8472 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8473 format %{ "XOR $dst,$dst\n\t" | |
| 8474 "CMP $p,$q\n\t" | |
| 8475 "SETlt $dst\n\t" | |
| 8476 "NEG $dst" %} | |
| 9154 | 8477 ins_encode %{ |
| 8478 Register Rp = $p$$Register; | |
| 8479 Register Rq = $q$$Register; | |
| 8480 Register Rd = $dst$$Register; | |
| 8481 Label done; | |
| 8482 __ xorl(Rd, Rd); | |
| 8483 __ cmpl(Rp, Rq); | |
| 8484 __ setb(Assembler::less, Rd); | |
| 8485 __ negl(Rd); | |
| 8486 %} | |
| 8487 | |
| 8488 ins_pipe(pipe_slow); | |
| 8489 %} | |
| 8490 | |
| 8491 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 0 | 8492 match(Set dst (CmpLTMask dst zero)); |
| 9154 | 8493 effect(DEF dst, KILL cr); |
| 0 | 8494 ins_cost(100); |
| 8495 | |
| 9154 | 8496 format %{ "SAR $dst,31\t# cmpLTMask0" %} |
| 8497 ins_encode %{ | |
| 8498 __ sarl($dst$$Register, 31); | |
| 8499 %} | |
| 8500 ins_pipe(ialu_reg); | |
| 8501 %} | |
| 8502 | |
| 8503 /* better to save a register than avoid a branch */ | |
| 8504 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 0 | 8505 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
| 9154 | 8506 effect(KILL cr); |
| 0 | 8507 ins_cost(400); |
| 9154 | 8508 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t" |
| 8509 "JGE done\n\t" | |
| 8510 "ADD $p,$y\n" | |
| 8511 "done: " %} | |
| 8512 ins_encode %{ | |
| 8513 Register Rp = $p$$Register; | |
| 8514 Register Rq = $q$$Register; | |
| 8515 Register Ry = $y$$Register; | |
| 8516 Label done; | |
| 8517 __ subl(Rp, Rq); | |
| 8518 __ jccb(Assembler::greaterEqual, done); | |
| 8519 __ addl(Rp, Ry); | |
| 8520 __ bind(done); | |
| 8521 %} | |
| 8522 | |
| 8523 ins_pipe(pipe_cmplt); | |
| 8524 %} | |
| 8525 | |
| 8526 /* better to save a register than avoid a branch */ | |
| 8527 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 8528 match(Set y (AndI (CmpLTMask p q) y)); | |
| 8529 effect(KILL cr); | |
| 8530 | |
| 8531 ins_cost(300); | |
| 8532 | |
| 8533 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t" | |
| 8534 "JLT done\n\t" | |
| 8535 "XORL $y, $y\n" | |
| 8536 "done: " %} | |
| 8537 ins_encode %{ | |
| 8538 Register Rp = $p$$Register; | |
| 8539 Register Rq = $q$$Register; | |
| 8540 Register Ry = $y$$Register; | |
| 8541 Label done; | |
| 8542 __ cmpl(Rp, Rq); | |
| 8543 __ jccb(Assembler::less, done); | |
| 8544 __ xorl(Ry, Ry); | |
| 8545 __ bind(done); | |
| 8546 %} | |
| 8547 | |
| 8548 ins_pipe(pipe_cmplt); | |
| 0 | 8549 %} |
| 8550 | |
| 8551 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9154 | 8552 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
| 0 | 8553 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
| 8554 */ | |
|
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8555 //----------Overflow Math Instructions----------------------------------------- |
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8556 |
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8557 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
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8558 %{ |
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8559 match(Set cr (OverflowAddI op1 op2)); |
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8560 effect(DEF cr, USE_KILL op1, USE op2); |
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8561 |
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8562 format %{ "ADD $op1, $op2\t# overflow check int" %} |
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8563 |
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8564 ins_encode %{ |
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8565 __ addl($op1$$Register, $op2$$Register); |
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8566 %} |
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8567 ins_pipe(ialu_reg_reg); |
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8568 %} |
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8569 |
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8570 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) |
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8571 %{ |
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8572 match(Set cr (OverflowAddI op1 op2)); |
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8573 effect(DEF cr, USE_KILL op1, USE op2); |
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8574 |
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8575 format %{ "ADD $op1, $op2\t# overflow check int" %} |
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8576 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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17714
diff
changeset
|
8577 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8578 __ addl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8579 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8580 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8581 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8582 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8583 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8584 %{ |
|
085b304a1cc5
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rbackman
parents:
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diff
changeset
|
8585 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8586 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8587 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8588 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
8589 __ cmpl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8590 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8591 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8592 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8593 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8594 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8595 %{ |
|
085b304a1cc5
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rbackman
parents:
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diff
changeset
|
8596 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8597 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8598 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8599 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
8600 __ cmpl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8601 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8602 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8603 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8604 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8605 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8606 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
8607 match(Set cr (OverflowSubI zero op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
8608 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8609 |
|
085b304a1cc5
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rbackman
parents:
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diff
changeset
|
8610 format %{ "NEG $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8611 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
8612 __ negl($op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8613 %} |
|
085b304a1cc5
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rbackman
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17714
diff
changeset
|
8614 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8615 %} |
|
085b304a1cc5
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rbackman
parents:
17714
diff
changeset
|
8616 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8617 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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|
8618 %{ |
|
085b304a1cc5
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rbackman
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diff
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|
8619 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
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rbackman
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changeset
|
8620 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8621 |
|
085b304a1cc5
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rbackman
parents:
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diff
changeset
|
8622 format %{ "IMUL $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8623 ins_encode %{ |
|
085b304a1cc5
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rbackman
parents:
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diff
changeset
|
8624 __ imull($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8625 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8626 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8627 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8628 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8629 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8630 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8631 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
8632 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8633 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8634 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8635 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8636 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8637 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8638 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8639 %} |
| 0 | 8640 |
| 8641 //----------Long Instructions------------------------------------------------ | |
| 8642 // Add Long Register with Register | |
| 8643 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8644 match(Set dst (AddL dst src)); | |
| 8645 effect(KILL cr); | |
| 8646 ins_cost(200); | |
| 8647 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8648 "ADC $dst.hi,$src.hi" %} | |
| 8649 opcode(0x03, 0x13); | |
| 8650 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8651 ins_pipe( ialu_reg_reg_long ); | |
| 8652 %} | |
| 8653 | |
| 8654 // Add Long Register with Immediate | |
| 8655 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8656 match(Set dst (AddL dst src)); | |
| 8657 effect(KILL cr); | |
| 8658 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8659 "ADC $dst.hi,$src.hi" %} | |
| 8660 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8661 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8662 ins_pipe( ialu_reg_long ); | |
| 8663 %} | |
| 8664 | |
| 8665 // Add Long Register with Memory | |
| 8666 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8667 match(Set dst (AddL dst (LoadL mem))); | |
| 8668 effect(KILL cr); | |
| 8669 ins_cost(125); | |
| 8670 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8671 "ADC $dst.hi,$mem+4" %} | |
| 8672 opcode(0x03, 0x13); | |
| 8673 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8674 ins_pipe( ialu_reg_long_mem ); | |
| 8675 %} | |
| 8676 | |
| 8677 // Subtract Long Register with Register. | |
| 8678 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8679 match(Set dst (SubL dst src)); | |
| 8680 effect(KILL cr); | |
| 8681 ins_cost(200); | |
| 8682 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8683 "SBB $dst.hi,$src.hi" %} | |
| 8684 opcode(0x2B, 0x1B); | |
| 8685 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8686 ins_pipe( ialu_reg_reg_long ); | |
| 8687 %} | |
| 8688 | |
| 8689 // Subtract Long Register with Immediate | |
| 8690 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8691 match(Set dst (SubL dst src)); | |
| 8692 effect(KILL cr); | |
| 8693 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8694 "SBB $dst.hi,$src.hi" %} | |
| 8695 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 8696 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8697 ins_pipe( ialu_reg_long ); | |
| 8698 %} | |
| 8699 | |
| 8700 // Subtract Long Register with Memory | |
| 8701 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8702 match(Set dst (SubL dst (LoadL mem))); | |
| 8703 effect(KILL cr); | |
| 8704 ins_cost(125); | |
| 8705 format %{ "SUB $dst.lo,$mem\n\t" | |
| 8706 "SBB $dst.hi,$mem+4" %} | |
| 8707 opcode(0x2B, 0x1B); | |
| 8708 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8709 ins_pipe( ialu_reg_long_mem ); | |
| 8710 %} | |
| 8711 | |
| 8712 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 8713 match(Set dst (SubL zero dst)); | |
| 8714 effect(KILL cr); | |
| 8715 ins_cost(300); | |
| 8716 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 8717 ins_encode( neg_long(dst) ); | |
| 8718 ins_pipe( ialu_reg_reg_long ); | |
| 8719 %} | |
| 8720 | |
| 8721 // And Long Register with Register | |
| 8722 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8723 match(Set dst (AndL dst src)); | |
| 8724 effect(KILL cr); | |
| 8725 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8726 "AND $dst.hi,$src.hi" %} | |
| 8727 opcode(0x23,0x23); | |
| 8728 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8729 ins_pipe( ialu_reg_reg_long ); | |
| 8730 %} | |
| 8731 | |
| 8732 // And Long Register with Immediate | |
| 8733 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8734 match(Set dst (AndL dst src)); | |
| 8735 effect(KILL cr); | |
| 8736 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8737 "AND $dst.hi,$src.hi" %} | |
| 8738 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 8739 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8740 ins_pipe( ialu_reg_long ); | |
| 8741 %} | |
| 8742 | |
| 8743 // And Long Register with Memory | |
| 8744 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8745 match(Set dst (AndL dst (LoadL mem))); | |
| 8746 effect(KILL cr); | |
| 8747 ins_cost(125); | |
| 8748 format %{ "AND $dst.lo,$mem\n\t" | |
| 8749 "AND $dst.hi,$mem+4" %} | |
| 8750 opcode(0x23, 0x23); | |
| 8751 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8752 ins_pipe( ialu_reg_long_mem ); | |
| 8753 %} | |
| 8754 | |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8755 // BMI1 instructions |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8756 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8757 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8758 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8759 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8760 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8761 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8762 "ANDNL $dst.hi, $src1.hi, $src2.hi" |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8763 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8764 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8765 ins_encode %{ |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8766 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8767 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8768 Register Rsrc2 = $src2$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8769 __ andnl(Rdst, Rsrc1, Rsrc2); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8770 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8771 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8772 ins_pipe(ialu_reg_reg_long); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8773 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8774 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8775 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8776 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8777 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8778 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8779 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8780 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8781 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8782 "ANDNL $dst.hi, $src1.hi, $src2+4" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8783 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8784 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8785 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8786 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8787 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8788 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8789 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8790 __ andnl(Rdst, Rsrc1, $src2$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8791 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8792 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8793 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8794 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8795 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8796 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8797 match(Set dst (AndL (SubL imm_zero src) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8798 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8799 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8800 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8801 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8802 "BLSIL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8803 "JNZ done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8804 "BLSIL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8805 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8806 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8807 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8808 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8809 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8810 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8811 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8812 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8813 __ blsil(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8814 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8815 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8816 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8817 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8818 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8819 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8820 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8821 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8822 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8823 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8824 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8825 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8826 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8827 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8828 "BLSIL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8829 "JNZ done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8830 "BLSIL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8831 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8832 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8833 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8834 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8835 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8836 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8837 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8838 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8839 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8840 __ blsil(Rdst, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8841 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8842 __ blsil(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8843 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8844 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8845 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8846 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8847 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8848 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8849 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8850 match(Set dst (XorL (AddL src minus_1) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8851 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8852 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8853 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8854 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8855 "BLSMSKL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8856 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8857 "BLSMSKL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8858 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8859 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8860 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8861 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8862 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8863 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8864 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8865 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8866 __ blsmskl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8867 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8868 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8869 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8870 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8871 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8872 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8873 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8874 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8875 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8876 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8877 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8878 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8879 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8880 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8881 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8882 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8883 "BLSMSKL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8884 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8885 "BLSMSKL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8886 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8887 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8888 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8889 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8890 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8891 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8892 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8893 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8894 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8895 __ blsmskl(Rdst, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8896 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8897 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8898 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8899 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8900 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8901 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8902 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8903 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8904 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8905 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8906 match(Set dst (AndL (AddL src minus_1) src) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8907 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8908 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8909 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8910 format %{ "MOVL $dst.hi, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8911 "BLSRL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8912 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8913 "BLSRL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8914 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8915 %} |
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8916 |
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8917 ins_encode %{ |
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8918 Label done; |
|
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8919 Register Rdst = $dst$$Register; |
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8920 Register Rsrc = $src$$Register; |
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|
8921 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
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8922 __ blsrl(Rdst, Rsrc); |
|
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8923 __ jccb(Assembler::carryClear, done); |
|
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8924 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
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8925 __ bind(done); |
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|
8926 %} |
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|
8927 |
|
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|
8928 ins_pipe(ialu_reg); |
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|
8929 %} |
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|
8930 |
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8931 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
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8932 %{ |
|
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8933 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
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8934 predicate(UseBMI1Instructions); |
|
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8935 effect(KILL cr, TEMP dst); |
|
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|
8936 |
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|
8937 ins_cost(125); |
|
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8938 format %{ "MOVL $dst.hi, $src+4\n\t" |
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8939 "BLSRL $dst.lo, $src\n\t" |
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8940 "JNC done\n\t" |
|
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8941 "BLSRL $dst.hi, $src+4\n" |
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8942 "done:" |
|
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|
8943 %} |
|
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|
8944 |
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|
8945 ins_encode %{ |
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|
8946 Label done; |
|
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|
8947 Register Rdst = $dst$$Register; |
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8948 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
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8949 __ movl(HIGH_FROM_LOW(Rdst), src_hi); |
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|
8950 __ blsrl(Rdst, $src$$Address); |
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|
8951 __ jccb(Assembler::carryClear, done); |
|
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|
8952 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi); |
|
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|
8953 __ bind(done); |
|
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|
8954 %} |
|
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|
8955 |
|
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|
8956 ins_pipe(ialu_reg_mem); |
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|
8957 %} |
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|
8958 |
| 0 | 8959 // Or Long Register with Register |
| 8960 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8961 match(Set dst (OrL dst src)); | |
| 8962 effect(KILL cr); | |
| 8963 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 8964 "OR $dst.hi,$src.hi" %} | |
| 8965 opcode(0x0B,0x0B); | |
| 8966 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8967 ins_pipe( ialu_reg_reg_long ); | |
| 8968 %} | |
| 8969 | |
| 8970 // Or Long Register with Immediate | |
| 8971 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8972 match(Set dst (OrL dst src)); | |
| 8973 effect(KILL cr); | |
| 8974 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 8975 "OR $dst.hi,$src.hi" %} | |
| 8976 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 8977 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8978 ins_pipe( ialu_reg_long ); | |
| 8979 %} | |
| 8980 | |
| 8981 // Or Long Register with Memory | |
| 8982 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8983 match(Set dst (OrL dst (LoadL mem))); | |
| 8984 effect(KILL cr); | |
| 8985 ins_cost(125); | |
| 8986 format %{ "OR $dst.lo,$mem\n\t" | |
| 8987 "OR $dst.hi,$mem+4" %} | |
| 8988 opcode(0x0B,0x0B); | |
| 8989 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8990 ins_pipe( ialu_reg_long_mem ); | |
| 8991 %} | |
| 8992 | |
| 8993 // Xor Long Register with Register | |
| 8994 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8995 match(Set dst (XorL dst src)); | |
| 8996 effect(KILL cr); | |
| 8997 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 8998 "XOR $dst.hi,$src.hi" %} | |
| 8999 opcode(0x33,0x33); | |
| 9000 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9001 ins_pipe( ialu_reg_reg_long ); | |
| 9002 %} | |
| 9003 | |
| 403 | 9004 // Xor Long Register with Immediate -1 |
| 9005 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9006 match(Set dst (XorL dst imm)); | |
| 9007 format %{ "NOT $dst.lo\n\t" | |
| 9008 "NOT $dst.hi" %} | |
| 9009 ins_encode %{ | |
| 9010 __ notl($dst$$Register); | |
| 9011 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9012 %} | |
| 9013 ins_pipe( ialu_reg_long ); | |
| 9014 %} | |
| 9015 | |
| 0 | 9016 // Xor Long Register with Immediate |
| 9017 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9018 match(Set dst (XorL dst src)); | |
| 9019 effect(KILL cr); | |
| 9020 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9021 "XOR $dst.hi,$src.hi" %} | |
| 9022 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9023 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9024 ins_pipe( ialu_reg_long ); | |
| 9025 %} | |
| 9026 | |
| 9027 // Xor Long Register with Memory | |
| 9028 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9029 match(Set dst (XorL dst (LoadL mem))); | |
| 9030 effect(KILL cr); | |
| 9031 ins_cost(125); | |
| 9032 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9033 "XOR $dst.hi,$mem+4" %} | |
| 9034 opcode(0x33,0x33); | |
| 9035 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9036 ins_pipe( ialu_reg_long_mem ); | |
| 9037 %} | |
| 9038 | |
| 219 | 9039 // Shift Left Long by 1 |
| 9040 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9041 predicate(UseNewLongLShift); | |
| 9042 match(Set dst (LShiftL dst cnt)); | |
| 9043 effect(KILL cr); | |
| 9044 ins_cost(100); | |
| 9045 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9046 "ADC $dst.hi,$dst.hi" %} | |
| 9047 ins_encode %{ | |
| 9048 __ addl($dst$$Register,$dst$$Register); | |
| 9049 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9050 %} | |
| 9051 ins_pipe( ialu_reg_long ); | |
| 9052 %} | |
| 9053 | |
| 9054 // Shift Left Long by 2 | |
| 9055 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9056 predicate(UseNewLongLShift); | |
| 9057 match(Set dst (LShiftL dst cnt)); | |
| 9058 effect(KILL cr); | |
| 9059 ins_cost(100); | |
| 9060 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9061 "ADC $dst.hi,$dst.hi\n\t" | |
| 9062 "ADD $dst.lo,$dst.lo\n\t" | |
| 9063 "ADC $dst.hi,$dst.hi" %} | |
| 9064 ins_encode %{ | |
| 9065 __ addl($dst$$Register,$dst$$Register); | |
| 9066 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9067 __ addl($dst$$Register,$dst$$Register); | |
| 9068 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9069 %} | |
| 9070 ins_pipe( ialu_reg_long ); | |
| 9071 %} | |
| 9072 | |
| 9073 // Shift Left Long by 3 | |
| 9074 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9075 predicate(UseNewLongLShift); | |
| 9076 match(Set dst (LShiftL dst cnt)); | |
| 9077 effect(KILL cr); | |
| 9078 ins_cost(100); | |
| 9079 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9080 "ADC $dst.hi,$dst.hi\n\t" | |
| 9081 "ADD $dst.lo,$dst.lo\n\t" | |
| 9082 "ADC $dst.hi,$dst.hi\n\t" | |
| 9083 "ADD $dst.lo,$dst.lo\n\t" | |
| 9084 "ADC $dst.hi,$dst.hi" %} | |
| 9085 ins_encode %{ | |
| 9086 __ addl($dst$$Register,$dst$$Register); | |
| 9087 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9088 __ addl($dst$$Register,$dst$$Register); | |
| 9089 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9090 __ addl($dst$$Register,$dst$$Register); | |
| 9091 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9092 %} | |
| 9093 ins_pipe( ialu_reg_long ); | |
| 9094 %} | |
| 9095 | |
| 0 | 9096 // Shift Left Long by 1-31 |
| 9097 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9098 match(Set dst (LShiftL dst cnt)); | |
| 9099 effect(KILL cr); | |
| 9100 ins_cost(200); | |
| 9101 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9102 "SHL $dst.lo,$cnt" %} | |
| 9103 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9104 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9105 ins_pipe( ialu_reg_long ); | |
| 9106 %} | |
| 9107 | |
| 9108 // Shift Left Long by 32-63 | |
| 9109 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9110 match(Set dst (LShiftL dst cnt)); | |
| 9111 effect(KILL cr); | |
| 9112 ins_cost(300); | |
| 9113 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9114 "\tSHL $dst.hi,$cnt-32\n" | |
| 9115 "\tXOR $dst.lo,$dst.lo" %} | |
| 9116 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9117 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9118 ins_pipe( ialu_reg_long ); | |
| 9119 %} | |
| 9120 | |
| 9121 // Shift Left Long by variable | |
| 9122 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9123 match(Set dst (LShiftL dst shift)); | |
| 9124 effect(KILL cr); | |
| 9125 ins_cost(500+200); | |
| 9126 size(17); | |
| 9127 format %{ "TEST $shift,32\n\t" | |
| 9128 "JEQ,s small\n\t" | |
| 9129 "MOV $dst.hi,$dst.lo\n\t" | |
| 9130 "XOR $dst.lo,$dst.lo\n" | |
| 9131 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9132 "SHL $dst.lo,$shift" %} | |
| 9133 ins_encode( shift_left_long( dst, shift ) ); | |
| 9134 ins_pipe( pipe_slow ); | |
| 9135 %} | |
| 9136 | |
| 9137 // Shift Right Long by 1-31 | |
| 9138 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9139 match(Set dst (URShiftL dst cnt)); | |
| 9140 effect(KILL cr); | |
| 9141 ins_cost(200); | |
| 9142 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9143 "SHR $dst.hi,$cnt" %} | |
| 9144 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9145 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9146 ins_pipe( ialu_reg_long ); | |
| 9147 %} | |
| 9148 | |
| 9149 // Shift Right Long by 32-63 | |
| 9150 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9151 match(Set dst (URShiftL dst cnt)); | |
| 9152 effect(KILL cr); | |
| 9153 ins_cost(300); | |
| 9154 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9155 "\tSHR $dst.lo,$cnt-32\n" | |
| 9156 "\tXOR $dst.hi,$dst.hi" %} | |
| 9157 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9158 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9159 ins_pipe( ialu_reg_long ); | |
| 9160 %} | |
| 9161 | |
| 9162 // Shift Right Long by variable | |
| 9163 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9164 match(Set dst (URShiftL dst shift)); | |
| 9165 effect(KILL cr); | |
| 9166 ins_cost(600); | |
| 9167 size(17); | |
| 9168 format %{ "TEST $shift,32\n\t" | |
| 9169 "JEQ,s small\n\t" | |
| 9170 "MOV $dst.lo,$dst.hi\n\t" | |
| 9171 "XOR $dst.hi,$dst.hi\n" | |
| 9172 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9173 "SHR $dst.hi,$shift" %} | |
| 9174 ins_encode( shift_right_long( dst, shift ) ); | |
| 9175 ins_pipe( pipe_slow ); | |
| 9176 %} | |
| 9177 | |
| 9178 // Shift Right Long by 1-31 | |
| 9179 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9180 match(Set dst (RShiftL dst cnt)); | |
| 9181 effect(KILL cr); | |
| 9182 ins_cost(200); | |
| 9183 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9184 "SAR $dst.hi,$cnt" %} | |
| 9185 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9186 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9187 ins_pipe( ialu_reg_long ); | |
| 9188 %} | |
| 9189 | |
| 9190 // Shift Right Long by 32-63 | |
| 9191 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9192 match(Set dst (RShiftL dst cnt)); | |
| 9193 effect(KILL cr); | |
| 9194 ins_cost(300); | |
| 9195 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9196 "\tSAR $dst.lo,$cnt-32\n" | |
| 9197 "\tSAR $dst.hi,31" %} | |
| 9198 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9199 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9200 ins_pipe( ialu_reg_long ); | |
| 9201 %} | |
| 9202 | |
| 9203 // Shift Right arithmetic Long by variable | |
| 9204 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9205 match(Set dst (RShiftL dst shift)); | |
| 9206 effect(KILL cr); | |
| 9207 ins_cost(600); | |
| 9208 size(18); | |
| 9209 format %{ "TEST $shift,32\n\t" | |
| 9210 "JEQ,s small\n\t" | |
| 9211 "MOV $dst.lo,$dst.hi\n\t" | |
| 9212 "SAR $dst.hi,31\n" | |
| 9213 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9214 "SAR $dst.hi,$shift" %} | |
| 9215 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9216 ins_pipe( pipe_slow ); | |
| 9217 %} | |
| 9218 | |
| 9219 | |
| 9220 //----------Double Instructions------------------------------------------------ | |
| 9221 // Double Math | |
| 9222 | |
| 9223 // Compare & branch | |
| 9224 | |
| 9225 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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|
9226 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9227 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9228 match(Set cr (CmpD src1 src2)); | |
| 9229 effect(KILL rax); | |
| 9230 ins_cost(150); | |
| 9231 format %{ "FLD $src1\n\t" | |
| 9232 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9233 "JNP exit\n\t" | |
| 9234 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9235 "SAHF\n" | |
| 9236 "exit:\tNOP // avoid branch to branch" %} | |
| 9237 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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|
9238 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9239 OpcP, RegOpc(src2), |
| 9240 cmpF_P6_fixup ); | |
| 9241 ins_pipe( pipe_slow ); | |
| 9242 %} | |
| 9243 | |
|
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|
9244 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
415
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403
diff
changeset
|
9245 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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|
9246 match(Set cr (CmpD src1 src2)); |
|
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|
9247 ins_cost(150); |
|
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|
9248 format %{ "FLD $src1\n\t" |
|
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changeset
|
9249 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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diff
changeset
|
9250 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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|
9251 ins_encode( Push_Reg_DPR(src1), |
|
415
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|
9252 OpcP, RegOpc(src2)); |
|
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|
9253 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9254 %} |
|
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|
9255 |
| 0 | 9256 // Compare & branch |
|
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|
9257 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9258 predicate(UseSSE<=1); |
| 9259 match(Set cr (CmpD src1 src2)); | |
| 9260 effect(KILL rax); | |
| 9261 ins_cost(200); | |
| 9262 format %{ "FLD $src1\n\t" | |
| 9263 "FCOMp $src2\n\t" | |
| 9264 "FNSTSW AX\n\t" | |
| 9265 "TEST AX,0x400\n\t" | |
| 9266 "JZ,s flags\n\t" | |
| 9267 "MOV AH,1\t# unordered treat as LT\n" | |
| 9268 "flags:\tSAHF" %} | |
| 9269 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
9270 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9271 OpcP, RegOpc(src2), |
| 9272 fpu_flags); | |
| 9273 ins_pipe( pipe_slow ); | |
| 9274 %} | |
| 9275 | |
| 9276 // Compare vs zero into -1,0,1 | |
|
6179
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|
9277 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9278 predicate(UseSSE<=1); |
| 9279 match(Set dst (CmpD3 src1 zero)); | |
| 9280 effect(KILL cr, KILL rax); | |
| 9281 ins_cost(280); | |
| 9282 format %{ "FTSTD $dst,$src1" %} | |
| 9283 opcode(0xE4, 0xD9); | |
|
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|
9284 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9285 OpcS, OpcP, PopFPU, |
| 9286 CmpF_Result(dst)); | |
| 9287 ins_pipe( pipe_slow ); | |
| 9288 %} | |
| 9289 | |
| 9290 // Compare into -1,0,1 | |
|
6179
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|
9291 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9292 predicate(UseSSE<=1); |
| 9293 match(Set dst (CmpD3 src1 src2)); | |
| 9294 effect(KILL cr, KILL rax); | |
| 9295 ins_cost(300); | |
| 9296 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9297 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
9298 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9299 OpcP, RegOpc(src2), |
| 9300 CmpF_Result(dst)); | |
| 9301 ins_pipe( pipe_slow ); | |
| 9302 %} | |
| 9303 | |
| 9304 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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|
9305 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9306 predicate(UseSSE>=2); |
| 4759 | 9307 match(Set cr (CmpD src1 src2)); |
| 9308 ins_cost(145); | |
| 9309 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9310 "JNP,s exit\n\t" | |
| 9311 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9312 "AND [rsp], #0xffffff2b\n\t" | |
| 9313 "POPF\n" | |
| 9314 "exit:" %} | |
| 9315 ins_encode %{ | |
| 9316 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9317 emit_cmpfp_fixup(_masm); | |
| 9318 %} | |
| 9319 ins_pipe( pipe_slow ); | |
| 9320 %} | |
| 9321 | |
|
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|
9322 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
415
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changeset
|
9323 predicate(UseSSE>=2); |
| 4759 | 9324 match(Set cr (CmpD src1 src2)); |
|
415
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|
9325 ins_cost(100); |
| 4759 | 9326 format %{ "UCOMISD $src1,$src2" %} |
| 9327 ins_encode %{ | |
| 9328 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9329 %} | |
|
415
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diff
changeset
|
9330 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9331 %} |
|
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|
9332 |
| 0 | 9333 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
9334 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9335 predicate(UseSSE>=2); |
| 4759 | 9336 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9337 ins_cost(145); |
| 4759 | 9338 format %{ "UCOMISD $src1,$src2\n\t" |
| 9339 "JNP,s exit\n\t" | |
| 9340 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9341 "AND [rsp], #0xffffff2b\n\t" | |
| 9342 "POPF\n" | |
| 9343 "exit:" %} | |
| 9344 ins_encode %{ | |
| 9345 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9346 emit_cmpfp_fixup(_masm); | |
| 9347 %} | |
| 9348 ins_pipe( pipe_slow ); | |
| 9349 %} | |
| 9350 | |
|
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|
9351 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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changeset
|
9352 predicate(UseSSE>=2); |
| 4759 | 9353 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
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changeset
|
9354 ins_cost(100); |
| 4759 | 9355 format %{ "UCOMISD $src1,$src2" %} |
| 9356 ins_encode %{ | |
| 9357 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9358 %} | |
|
415
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changeset
|
9359 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9360 %} |
|
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changeset
|
9361 |
| 0 | 9362 // Compare into -1,0,1 in XMM |
|
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|
9363 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9364 predicate(UseSSE>=2); |
| 9365 match(Set dst (CmpD3 src1 src2)); | |
| 9366 effect(KILL cr); | |
| 9367 ins_cost(255); | |
| 4759 | 9368 format %{ "UCOMISD $src1, $src2\n\t" |
| 9369 "MOV $dst, #-1\n\t" | |
| 9370 "JP,s done\n\t" | |
| 9371 "JB,s done\n\t" | |
| 9372 "SETNE $dst\n\t" | |
| 9373 "MOVZB $dst, $dst\n" | |
| 9374 "done:" %} | |
| 9375 ins_encode %{ | |
| 9376 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9377 emit_cmpfp3(_masm, $dst$$Register); | |
| 9378 %} | |
| 0 | 9379 ins_pipe( pipe_slow ); |
| 9380 %} | |
| 9381 | |
| 9382 // Compare into -1,0,1 in XMM and memory | |
|
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|
9383 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9384 predicate(UseSSE>=2); |
| 4759 | 9385 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9386 effect(KILL cr); |
| 9387 ins_cost(275); | |
| 4759 | 9388 format %{ "UCOMISD $src1, $src2\n\t" |
| 9389 "MOV $dst, #-1\n\t" | |
| 9390 "JP,s done\n\t" | |
| 9391 "JB,s done\n\t" | |
| 9392 "SETNE $dst\n\t" | |
| 9393 "MOVZB $dst, $dst\n" | |
| 9394 "done:" %} | |
| 9395 ins_encode %{ | |
| 9396 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9397 emit_cmpfp3(_masm, $dst$$Register); | |
| 9398 %} | |
| 0 | 9399 ins_pipe( pipe_slow ); |
| 9400 %} | |
| 9401 | |
| 9402 | |
|
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|
9403 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9404 predicate (UseSSE <=1); |
| 9405 match(Set dst (SubD dst src)); | |
| 9406 | |
| 9407 format %{ "FLD $src\n\t" | |
| 9408 "DSUBp $dst,ST" %} | |
| 9409 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9410 ins_cost(150); | |
|
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|
9411 ins_encode( Push_Reg_DPR(src), |
| 0 | 9412 OpcP, RegOpc(dst) ); |
| 9413 ins_pipe( fpu_reg_reg ); | |
| 9414 %} | |
| 9415 | |
|
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|
9416 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9417 predicate (UseSSE <=1); |
| 9418 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9419 ins_cost(250); | |
| 9420 | |
| 9421 format %{ "FLD $src2\n\t" | |
| 9422 "DSUB ST,$src1\n\t" | |
| 9423 "FSTP_D $dst\t# D-round" %} | |
| 9424 opcode(0xD8, 0x5); | |
|
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|
9425 ins_encode( Push_Reg_DPR(src2), |
|
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|
9426 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9427 ins_pipe( fpu_mem_reg_reg ); |
| 9428 %} | |
| 9429 | |
| 9430 | |
|
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changeset
|
9431 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9432 predicate (UseSSE <=1); |
| 9433 match(Set dst (SubD dst (LoadD src))); | |
| 9434 ins_cost(150); | |
| 9435 | |
| 9436 format %{ "FLD $src\n\t" | |
| 9437 "DSUBp $dst,ST" %} | |
| 9438 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9439 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9440 OpcP, RegOpc(dst) ); | |
| 9441 ins_pipe( fpu_reg_mem ); | |
| 9442 %} | |
| 9443 | |
|
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|
9444 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9445 predicate (UseSSE<=1); |
| 9446 match(Set dst (AbsD src)); | |
| 9447 ins_cost(100); | |
| 9448 format %{ "FABS" %} | |
| 9449 opcode(0xE1, 0xD9); | |
| 9450 ins_encode( OpcS, OpcP ); | |
| 9451 ins_pipe( fpu_reg_reg ); | |
| 9452 %} | |
| 9453 | |
|
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|
9454 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9455 predicate(UseSSE<=1); |
| 9456 match(Set dst (NegD src)); | |
| 9457 ins_cost(100); | |
| 9458 format %{ "FCHS" %} | |
| 9459 opcode(0xE0, 0xD9); | |
| 9460 ins_encode( OpcS, OpcP ); | |
| 9461 ins_pipe( fpu_reg_reg ); | |
| 9462 %} | |
| 9463 | |
|
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|
9464 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9465 predicate(UseSSE<=1); |
| 9466 match(Set dst (AddD dst src)); | |
| 9467 format %{ "FLD $src\n\t" | |
| 9468 "DADD $dst,ST" %} | |
| 9469 size(4); | |
| 9470 ins_cost(150); | |
| 9471 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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changeset
|
9472 ins_encode( Push_Reg_DPR(src), |
| 0 | 9473 OpcP, RegOpc(dst) ); |
| 9474 ins_pipe( fpu_reg_reg ); | |
| 9475 %} | |
| 9476 | |
| 9477 | |
|
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|
9478 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9479 predicate(UseSSE<=1); |
| 9480 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9481 ins_cost(250); | |
| 9482 | |
| 9483 format %{ "FLD $src2\n\t" | |
| 9484 "DADD ST,$src1\n\t" | |
| 9485 "FSTP_D $dst\t# D-round" %} | |
| 9486 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
|
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changeset
|
9487 ins_encode( Push_Reg_DPR(src2), |
|
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|
9488 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9489 ins_pipe( fpu_mem_reg_reg ); |
| 9490 %} | |
| 9491 | |
| 9492 | |
|
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|
9493 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9494 predicate(UseSSE<=1); |
| 9495 match(Set dst (AddD dst (LoadD src))); | |
| 9496 ins_cost(150); | |
| 9497 | |
| 9498 format %{ "FLD $src\n\t" | |
| 9499 "DADDp $dst,ST" %} | |
| 9500 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9501 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9502 OpcP, RegOpc(dst) ); | |
| 9503 ins_pipe( fpu_reg_mem ); | |
| 9504 %} | |
| 9505 | |
| 9506 // add-to-memory | |
|
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|
9507 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9508 predicate(UseSSE<=1); |
| 9509 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9510 ins_cost(150); | |
| 9511 | |
| 9512 format %{ "FLD_D $dst\n\t" | |
| 9513 "DADD ST,$src\n\t" | |
| 9514 "FST_D $dst" %} | |
| 9515 opcode(0xDD, 0x0); | |
| 9516 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9517 Opcode(0xD8), RegOpc(src), | |
| 9518 set_instruction_start, | |
| 9519 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9520 ins_pipe( fpu_reg_mem ); | |
| 9521 %} | |
| 9522 | |
|
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|
9523 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9524 predicate(UseSSE<=1); |
| 2008 | 9525 match(Set dst (AddD dst con)); |
| 0 | 9526 ins_cost(125); |
| 9527 format %{ "FLD1\n\t" | |
| 9528 "DADDp $dst,ST" %} | |
| 2008 | 9529 ins_encode %{ |
| 9530 __ fld1(); | |
| 9531 __ faddp($dst$$reg); | |
| 9532 %} | |
| 9533 ins_pipe(fpu_reg); | |
| 9534 %} | |
| 9535 | |
|
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|
9536 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9537 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9538 match(Set dst (AddD dst con)); |
| 0 | 9539 ins_cost(200); |
| 2008 | 9540 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9541 "DADDp $dst,ST" %} |
| 2008 | 9542 ins_encode %{ |
| 9543 __ fld_d($constantaddress($con)); | |
| 9544 __ faddp($dst$$reg); | |
| 9545 %} | |
| 9546 ins_pipe(fpu_reg_mem); | |
| 0 | 9547 %} |
| 9548 | |
|
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|
9549 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9550 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9551 match(Set dst (RoundDouble (AddD src con))); | |
| 9552 ins_cost(200); | |
| 2008 | 9553 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9554 "DADD ST,$src\n\t" |
| 9555 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9556 ins_encode %{ |
| 9557 __ fld_d($constantaddress($con)); | |
| 9558 __ fadd($src$$reg); | |
| 9559 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9560 %} | |
| 9561 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9562 %} |
| 9563 | |
|
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9564 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9565 predicate(UseSSE<=1); |
| 9566 match(Set dst (MulD dst src)); | |
| 9567 format %{ "FLD $src\n\t" | |
| 9568 "DMULp $dst,ST" %} | |
| 9569 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9570 ins_cost(150); | |
|
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9571 ins_encode( Push_Reg_DPR(src), |
| 0 | 9572 OpcP, RegOpc(dst) ); |
| 9573 ins_pipe( fpu_reg_reg ); | |
| 9574 %} | |
| 9575 | |
| 9576 // Strict FP instruction biases argument before multiply then | |
| 9577 // biases result to avoid double rounding of subnormals. | |
| 9578 // | |
| 9579 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9580 // load arg2 | |
| 9581 // multiply scaled arg1 by arg2 | |
| 9582 // rescale product by 2^(15360) | |
| 9583 // | |
|
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9584 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9585 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9586 match(Set dst (MulD dst src)); | |
| 9587 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9588 | |
| 9589 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9590 "DMULp $dst,ST\n\t" | |
| 9591 "FLD $src\n\t" | |
| 9592 "DMULp $dst,ST\n\t" | |
| 9593 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9594 "DMULp $dst,ST\n\t" %} | |
| 9595 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9596 ins_encode( strictfp_bias1(dst), | |
|
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9597 Push_Reg_DPR(src), |
| 0 | 9598 OpcP, RegOpc(dst), |
| 9599 strictfp_bias2(dst) ); | |
| 9600 ins_pipe( fpu_reg_reg ); | |
| 9601 %} | |
| 9602 | |
|
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9603 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9604 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9605 match(Set dst (MulD dst con)); |
| 0 | 9606 ins_cost(200); |
| 2008 | 9607 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9608 "DMULp $dst,ST" %} |
| 2008 | 9609 ins_encode %{ |
| 9610 __ fld_d($constantaddress($con)); | |
| 9611 __ fmulp($dst$$reg); | |
| 9612 %} | |
| 9613 ins_pipe(fpu_reg_mem); | |
| 0 | 9614 %} |
| 9615 | |
| 9616 | |
|
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9617 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9618 predicate( UseSSE<=1 ); |
| 9619 match(Set dst (MulD dst (LoadD src))); | |
| 9620 ins_cost(200); | |
| 9621 format %{ "FLD_D $src\n\t" | |
| 9622 "DMULp $dst,ST" %} | |
| 9623 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9624 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9625 OpcP, RegOpc(dst) ); | |
| 9626 ins_pipe( fpu_reg_mem ); | |
| 9627 %} | |
| 9628 | |
| 9629 // | |
| 9630 // Cisc-alternate to reg-reg multiply | |
|
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9631 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9632 predicate( UseSSE<=1 ); |
| 9633 match(Set dst (MulD src (LoadD mem))); | |
| 9634 ins_cost(250); | |
| 9635 format %{ "FLD_D $mem\n\t" | |
| 9636 "DMUL ST,$src\n\t" | |
| 9637 "FSTP_D $dst" %} | |
| 9638 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9639 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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9640 OpcReg_FPR(src), |
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9641 Pop_Reg_DPR(dst) ); |
| 0 | 9642 ins_pipe( fpu_reg_reg_mem ); |
| 9643 %} | |
| 9644 | |
| 9645 | |
|
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9646 // MACRO3 -- addDPR a mulDPR |
| 0 | 9647 // This instruction is a '2-address' instruction in that the result goes |
| 9648 // back to src2. This eliminates a move from the macro; possibly the | |
| 9649 // register allocator will have to add it back (and maybe not). | |
|
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9650 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9651 predicate( UseSSE<=1 ); |
| 9652 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9653 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9654 "DMUL ST,$src1\n\t" | |
| 9655 "DADDp $src2,ST" %} | |
| 9656 ins_cost(250); | |
| 9657 opcode(0xDD); /* LoadD DD /0 */ | |
|
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9658 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9659 FMul_ST_reg(src1), |
| 9660 FAddP_reg_ST(src2) ); | |
| 9661 ins_pipe( fpu_reg_reg_reg ); | |
| 9662 %} | |
| 9663 | |
| 9664 | |
|
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9665 // MACRO3 -- subDPR a mulDPR |
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9666 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9667 predicate( UseSSE<=1 ); |
| 9668 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9669 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9670 "DMUL ST,$src1\n\t" | |
| 9671 "DSUBRp $src2,ST" %} | |
| 9672 ins_cost(250); | |
|
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9673 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9674 FMul_ST_reg(src1), |
| 9675 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9676 ins_pipe( fpu_reg_reg_reg ); | |
| 9677 %} | |
| 9678 | |
| 9679 | |
|
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9680 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9681 predicate( UseSSE<=1 ); |
| 9682 match(Set dst (DivD dst src)); | |
| 9683 | |
| 9684 format %{ "FLD $src\n\t" | |
| 9685 "FDIVp $dst,ST" %} | |
| 9686 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9687 ins_cost(150); | |
|
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9688 ins_encode( Push_Reg_DPR(src), |
| 0 | 9689 OpcP, RegOpc(dst) ); |
| 9690 ins_pipe( fpu_reg_reg ); | |
| 9691 %} | |
| 9692 | |
| 9693 // Strict FP instruction biases argument before division then | |
| 9694 // biases result, to avoid double rounding of subnormals. | |
| 9695 // | |
| 9696 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9697 // load divisor | |
| 9698 // divide scaled dividend by divisor | |
| 9699 // rescale quotient by 2^(15360) | |
| 9700 // | |
|
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9701 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9702 predicate (UseSSE<=1); |
| 9703 match(Set dst (DivD dst src)); | |
| 9704 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9705 ins_cost(01); | |
| 9706 | |
| 9707 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9708 "DMULp $dst,ST\n\t" | |
| 9709 "FLD $src\n\t" | |
| 9710 "FDIVp $dst,ST\n\t" | |
| 9711 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9712 "DMULp $dst,ST\n\t" %} | |
| 9713 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9714 ins_encode( strictfp_bias1(dst), | |
|
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9715 Push_Reg_DPR(src), |
| 0 | 9716 OpcP, RegOpc(dst), |
| 9717 strictfp_bias2(dst) ); | |
| 9718 ins_pipe( fpu_reg_reg ); | |
| 9719 %} | |
| 9720 | |
|
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9721 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9722 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9723 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9724 | |
| 9725 format %{ "FLD $src1\n\t" | |
| 9726 "FDIV ST,$src2\n\t" | |
| 9727 "FSTP_D $dst\t# D-round" %} | |
| 9728 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
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9729 ins_encode( Push_Reg_DPR(src1), |
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9730 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9731 ins_pipe( fpu_mem_reg_reg ); |
| 9732 %} | |
| 9733 | |
| 9734 | |
|
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9735 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9736 predicate(UseSSE<=1); |
| 9737 match(Set dst (ModD dst src)); | |
|
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9738 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9739 |
| 9740 format %{ "DMOD $dst,$src" %} | |
| 9741 ins_cost(250); | |
|
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9742 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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9743 emitModDPR(), |
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9744 Push_Result_Mod_DPR(src), |
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9745 Pop_Reg_DPR(dst)); |
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9746 ins_pipe( pipe_slow ); |
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|
9747 %} |
|
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|
9748 |
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9749 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9750 predicate(UseSSE>=2); |
| 9751 match(Set dst (ModD src0 src1)); | |
| 9752 effect(KILL rax, KILL cr); | |
| 9753 | |
| 9754 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9755 "\tMOVSD [ESP+0],$src1\n" | |
| 9756 "\tFLD_D [ESP+0]\n" | |
| 9757 "\tMOVSD [ESP+0],$src0\n" | |
| 9758 "\tFLD_D [ESP+0]\n" | |
| 9759 "loop:\tFPREM\n" | |
| 9760 "\tFWAIT\n" | |
| 9761 "\tFNSTSW AX\n" | |
| 9762 "\tSAHF\n" | |
| 9763 "\tJP loop\n" | |
| 9764 "\tFSTP_D [ESP+0]\n" | |
| 9765 "\tMOVSD $dst,[ESP+0]\n" | |
| 9766 "\tADD ESP,8\n" | |
| 9767 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9768 %} | |
| 9769 ins_cost(250); | |
|
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9770 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
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9771 ins_pipe( pipe_slow ); |
|
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|
9772 %} |
|
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|
9773 |
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9774 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9775 predicate (UseSSE<=1); |
| 9776 match(Set dst (SinD src)); | |
| 9777 ins_cost(1800); | |
| 9778 format %{ "DSIN $dst" %} | |
| 9779 opcode(0xD9, 0xFE); | |
| 9780 ins_encode( OpcP, OpcS ); | |
| 9781 ins_pipe( pipe_slow ); | |
| 9782 %} | |
| 9783 | |
|
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9784 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9785 predicate (UseSSE>=2); |
| 9786 match(Set dst (SinD dst)); | |
|
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9787 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9788 ins_cost(1800); |
| 9789 format %{ "DSIN $dst" %} | |
| 9790 opcode(0xD9, 0xFE); | |
|
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9791 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
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9792 ins_pipe( pipe_slow ); |
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9793 %} |
|
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9794 |
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9795 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9796 predicate (UseSSE<=1); |
| 9797 match(Set dst (CosD src)); | |
| 9798 ins_cost(1800); | |
| 9799 format %{ "DCOS $dst" %} | |
| 9800 opcode(0xD9, 0xFF); | |
| 9801 ins_encode( OpcP, OpcS ); | |
| 9802 ins_pipe( pipe_slow ); | |
| 9803 %} | |
| 9804 | |
|
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9805 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9806 predicate (UseSSE>=2); |
| 9807 match(Set dst (CosD dst)); | |
|
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9808 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9809 ins_cost(1800); |
| 9810 format %{ "DCOS $dst" %} | |
| 9811 opcode(0xD9, 0xFF); | |
|
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9812 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
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9813 ins_pipe( pipe_slow ); |
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9814 %} |
|
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9815 |
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9816 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9817 predicate (UseSSE<=1); |
| 9818 match(Set dst(TanD src)); | |
| 9819 format %{ "DTAN $dst" %} | |
| 9820 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9821 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9822 ins_pipe( pipe_slow ); | |
| 9823 %} | |
| 9824 | |
|
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9825 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9826 predicate (UseSSE>=2); |
| 9827 match(Set dst(TanD dst)); | |
|
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9828 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9829 format %{ "DTAN $dst" %} |
|
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9830 ins_encode( Push_SrcD(dst), |
| 0 | 9831 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9832 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
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9833 Push_ResultD(dst) ); |
|
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9834 ins_pipe( pipe_slow ); |
|
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|
9835 %} |
|
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4759
diff
changeset
|
9836 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
9837 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9838 predicate (UseSSE<=1); |
| 9839 match(Set dst(AtanD dst src)); | |
| 9840 format %{ "DATA $dst,$src" %} | |
| 9841 opcode(0xD9, 0xF3); | |
|
4761
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|
9842 ins_encode( Push_Reg_DPR(src), |
| 0 | 9843 OpcP, OpcS, RegOpc(dst) ); |
| 9844 ins_pipe( pipe_slow ); | |
| 9845 %} | |
| 9846 | |
|
4761
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
9847 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9848 predicate (UseSSE>=2); |
| 9849 match(Set dst(AtanD dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9850 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9851 format %{ "DATA $dst,$src" %} |
| 9852 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
9853 ins_encode( Push_SrcD(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
9854 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9855 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9856 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
9857 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9858 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9859 predicate (UseSSE<=1); |
| 9860 match(Set dst (SqrtD src)); | |
| 9861 format %{ "DSQRT $dst,$src" %} | |
| 9862 opcode(0xFA, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9863 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
9864 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9865 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
9866 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9867 |
|
6084
6759698e3140
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diff
changeset
|
9868 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9869 predicate (UseSSE<=1); |
| 9870 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
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roland
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|
9871 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
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roland
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|
9872 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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roland
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5934
diff
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|
9873 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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diff
changeset
|
9874 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
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|
9875 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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changeset
|
9876 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5934
diff
changeset
|
9877 __ addptr(rsp, 8); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9878 %} |
|
6759698e3140
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5934
diff
changeset
|
9879 ins_pipe( pipe_slow ); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9880 %} |
|
6759698e3140
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roland
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5934
diff
changeset
|
9881 |
|
6759698e3140
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roland
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5934
diff
changeset
|
9882 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9883 predicate (UseSSE>=2); |
| 9884 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
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roland
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diff
changeset
|
9885 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9886 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5934
diff
changeset
|
9887 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9888 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
changeset
|
9889 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9890 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9891 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5934
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changeset
|
9892 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9893 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9894 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
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diff
changeset
|
9895 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9896 __ addptr(rsp, 8); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9897 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9898 ins_pipe( pipe_slow ); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9899 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9900 |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9901 |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9902 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9903 predicate (UseSSE<=1); |
| 9904 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9905 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
changeset
|
9906 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9907 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9908 __ fast_exp(); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9909 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9910 ins_pipe( pipe_slow ); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9911 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9912 |
|
6759698e3140
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roland
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5934
diff
changeset
|
9913 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9914 predicate (UseSSE>=2); |
| 9915 match(Set dst (ExpD src)); | |
|
6084
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diff
changeset
|
9916 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
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roland
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diff
changeset
|
9917 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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roland
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5934
diff
changeset
|
9918 ins_encode %{ |
|
6759698e3140
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parents:
5934
diff
changeset
|
9919 __ subptr(rsp, 8); |
|
6759698e3140
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roland
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diff
changeset
|
9920 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
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roland
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diff
changeset
|
9921 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9922 __ fast_exp(); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9923 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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diff
changeset
|
9924 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
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changeset
|
9925 __ addptr(rsp, 8); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9926 %} |
|
6759698e3140
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roland
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diff
changeset
|
9927 ins_pipe( pipe_slow ); |
|
6759698e3140
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roland
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diff
changeset
|
9928 %} |
|
4761
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diff
changeset
|
9929 |
|
65149e74c706
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changeset
|
9930 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9931 predicate (UseSSE<=1); |
| 9932 // The source Double operand on FPU stack | |
| 9933 match(Set dst (Log10D src)); | |
| 9934 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9935 // fxch ; swap ST(0) with ST(1) | |
| 9936 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9937 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9938 "FXCH \n\t" | |
| 9939 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9940 %} | |
| 9941 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9942 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 9943 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 9944 | |
| 9945 ins_pipe( pipe_slow ); | |
| 9946 %} | |
| 9947 | |
|
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|
9948 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9949 predicate (UseSSE>=2); |
| 9950 effect(KILL cr); | |
| 9951 match(Set dst (Log10D src)); | |
| 9952 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9953 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9954 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9955 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9956 %} | |
| 9957 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
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|
9958 Push_SrcD(src), |
| 0 | 9959 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
9960 Push_ResultD(dst)); |
|
65149e74c706
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changeset
|
9961 |
|
65149e74c706
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changeset
|
9962 ins_pipe( pipe_slow ); |
|
65149e74c706
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|
9963 %} |
|
65149e74c706
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changeset
|
9964 |
|
65149e74c706
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changeset
|
9965 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9966 predicate (UseSSE<=1); |
| 9967 // The source Double operand on FPU stack | |
| 9968 match(Set dst (LogD src)); | |
| 9969 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9970 // fxch ; swap ST(0) with ST(1) | |
| 9971 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9972 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 9973 "FXCH \n\t" | |
| 9974 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 9975 %} | |
| 9976 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9977 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 9978 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 9979 | |
| 9980 ins_pipe( pipe_slow ); | |
| 9981 %} | |
| 9982 | |
|
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|
9983 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9984 predicate (UseSSE>=2); |
| 9985 effect(KILL cr); | |
| 9986 // The source and result Double operands in XMM registers | |
| 9987 match(Set dst (LogD src)); | |
| 9988 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9989 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9990 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 9991 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 9992 %} | |
| 9993 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
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changeset
|
9994 Push_SrcD(src), |
| 0 | 9995 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
9996 Push_ResultD(dst)); |
| 0 | 9997 ins_pipe( pipe_slow ); |
| 9998 %} | |
| 9999 | |
| 10000 //-------------Float Instructions------------------------------- | |
| 10001 // Float Math | |
| 10002 | |
| 10003 // Code for float compare: | |
| 10004 // fcompp(); | |
| 10005 // fwait(); fnstsw_ax(); | |
| 10006 // sahf(); | |
| 10007 // movl(dst, unordered_result); | |
| 10008 // jcc(Assembler::parity, exit); | |
| 10009 // movl(dst, less_result); | |
| 10010 // jcc(Assembler::below, exit); | |
| 10011 // movl(dst, equal_result); | |
| 10012 // jcc(Assembler::equal, exit); | |
| 10013 // movl(dst, greater_result); | |
| 10014 // exit: | |
| 10015 | |
| 10016 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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|
10017 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10018 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10019 match(Set cr (CmpF src1 src2)); | |
| 10020 effect(KILL rax); | |
| 10021 ins_cost(150); | |
| 10022 format %{ "FLD $src1\n\t" | |
| 10023 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10024 "JNP exit\n\t" | |
| 10025 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10026 "SAHF\n" | |
| 10027 "exit:\tNOP // avoid branch to branch" %} | |
| 10028 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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kvn
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changeset
|
10029 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10030 OpcP, RegOpc(src2), |
| 10031 cmpF_P6_fixup ); | |
| 10032 ins_pipe( pipe_slow ); | |
| 10033 %} | |
| 10034 | |
|
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65149e74c706
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|
10035 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
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10036 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
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10037 match(Set cr (CmpF src1 src2)); |
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10038 ins_cost(100); |
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10039 format %{ "FLD $src1\n\t" |
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10040 "FUCOMIP ST,$src2 // P6 instruction" %} |
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10041 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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10042 ins_encode( Push_Reg_DPR(src1), |
|
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10043 OpcP, RegOpc(src2)); |
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10044 ins_pipe( pipe_slow ); |
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10045 %} |
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10046 |
| 0 | 10047 |
| 10048 // Compare & branch | |
|
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10049 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10050 predicate(UseSSE == 0); |
| 10051 match(Set cr (CmpF src1 src2)); | |
| 10052 effect(KILL rax); | |
| 10053 ins_cost(200); | |
| 10054 format %{ "FLD $src1\n\t" | |
| 10055 "FCOMp $src2\n\t" | |
| 10056 "FNSTSW AX\n\t" | |
| 10057 "TEST AX,0x400\n\t" | |
| 10058 "JZ,s flags\n\t" | |
| 10059 "MOV AH,1\t# unordered treat as LT\n" | |
| 10060 "flags:\tSAHF" %} | |
| 10061 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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10062 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10063 OpcP, RegOpc(src2), |
| 10064 fpu_flags); | |
| 10065 ins_pipe( pipe_slow ); | |
| 10066 %} | |
| 10067 | |
| 10068 // Compare vs zero into -1,0,1 | |
|
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10069 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10070 predicate(UseSSE == 0); |
| 10071 match(Set dst (CmpF3 src1 zero)); | |
| 10072 effect(KILL cr, KILL rax); | |
| 10073 ins_cost(280); | |
| 10074 format %{ "FTSTF $dst,$src1" %} | |
| 10075 opcode(0xE4, 0xD9); | |
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10076 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10077 OpcS, OpcP, PopFPU, |
| 10078 CmpF_Result(dst)); | |
| 10079 ins_pipe( pipe_slow ); | |
| 10080 %} | |
| 10081 | |
| 10082 // Compare into -1,0,1 | |
|
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10083 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10084 predicate(UseSSE == 0); |
| 10085 match(Set dst (CmpF3 src1 src2)); | |
| 10086 effect(KILL cr, KILL rax); | |
| 10087 ins_cost(300); | |
| 10088 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10089 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
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10090 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10091 OpcP, RegOpc(src2), |
| 10092 CmpF_Result(dst)); | |
| 10093 ins_pipe( pipe_slow ); | |
| 10094 %} | |
| 10095 | |
| 10096 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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10097 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10098 predicate(UseSSE>=1); |
| 4759 | 10099 match(Set cr (CmpF src1 src2)); |
| 0 | 10100 ins_cost(145); |
| 4759 | 10101 format %{ "UCOMISS $src1,$src2\n\t" |
| 10102 "JNP,s exit\n\t" | |
| 10103 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10104 "AND [rsp], #0xffffff2b\n\t" | |
| 10105 "POPF\n" | |
| 10106 "exit:" %} | |
| 10107 ins_encode %{ | |
| 10108 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10109 emit_cmpfp_fixup(_masm); | |
| 10110 %} | |
| 10111 ins_pipe( pipe_slow ); | |
| 10112 %} | |
| 10113 | |
|
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10114 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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10115 predicate(UseSSE>=1); |
| 4759 | 10116 match(Set cr (CmpF src1 src2)); |
|
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10117 ins_cost(100); |
| 4759 | 10118 format %{ "UCOMISS $src1,$src2" %} |
| 10119 ins_encode %{ | |
| 10120 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10121 %} | |
|
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|
10122 ins_pipe( pipe_slow ); |
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10123 %} |
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|
10124 |
| 0 | 10125 // float compare and set condition codes in EFLAGS by XMM regs |
|
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10126 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10127 predicate(UseSSE>=1); |
| 4759 | 10128 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10129 ins_cost(165); |
| 4759 | 10130 format %{ "UCOMISS $src1,$src2\n\t" |
| 10131 "JNP,s exit\n\t" | |
| 10132 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10133 "AND [rsp], #0xffffff2b\n\t" | |
| 10134 "POPF\n" | |
| 10135 "exit:" %} | |
| 10136 ins_encode %{ | |
| 10137 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10138 emit_cmpfp_fixup(_masm); | |
| 10139 %} | |
| 10140 ins_pipe( pipe_slow ); | |
| 10141 %} | |
| 10142 | |
|
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10143 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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|
10144 predicate(UseSSE>=1); |
| 4759 | 10145 match(Set cr (CmpF src1 (LoadF src2))); |
|
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|
10146 ins_cost(100); |
| 4759 | 10147 format %{ "UCOMISS $src1,$src2" %} |
| 10148 ins_encode %{ | |
| 10149 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10150 %} | |
|
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|
10151 ins_pipe( pipe_slow ); |
|
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|
10152 %} |
|
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|
10153 |
| 0 | 10154 // Compare into -1,0,1 in XMM |
|
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|
10155 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10156 predicate(UseSSE>=1); |
| 10157 match(Set dst (CmpF3 src1 src2)); | |
| 10158 effect(KILL cr); | |
| 10159 ins_cost(255); | |
| 4759 | 10160 format %{ "UCOMISS $src1, $src2\n\t" |
| 10161 "MOV $dst, #-1\n\t" | |
| 10162 "JP,s done\n\t" | |
| 10163 "JB,s done\n\t" | |
| 10164 "SETNE $dst\n\t" | |
| 10165 "MOVZB $dst, $dst\n" | |
| 10166 "done:" %} | |
| 10167 ins_encode %{ | |
| 10168 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10169 emit_cmpfp3(_masm, $dst$$Register); | |
| 10170 %} | |
| 0 | 10171 ins_pipe( pipe_slow ); |
| 10172 %} | |
| 10173 | |
| 10174 // Compare into -1,0,1 in XMM and memory | |
|
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10175 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10176 predicate(UseSSE>=1); |
| 4759 | 10177 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10178 effect(KILL cr); |
| 10179 ins_cost(275); | |
| 4759 | 10180 format %{ "UCOMISS $src1, $src2\n\t" |
| 10181 "MOV $dst, #-1\n\t" | |
| 10182 "JP,s done\n\t" | |
| 10183 "JB,s done\n\t" | |
| 10184 "SETNE $dst\n\t" | |
| 10185 "MOVZB $dst, $dst\n" | |
| 10186 "done:" %} | |
| 10187 ins_encode %{ | |
| 10188 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10189 emit_cmpfp3(_masm, $dst$$Register); | |
| 10190 %} | |
| 0 | 10191 ins_pipe( pipe_slow ); |
| 10192 %} | |
| 10193 | |
| 10194 // Spill to obtain 24-bit precision | |
|
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10195 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10196 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10197 match(Set dst (SubF src1 src2)); | |
| 10198 | |
| 10199 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10200 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
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10201 ins_encode( Push_Reg_FPR(src1), |
|
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10202 OpcReg_FPR(src2), |
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10203 Pop_Mem_FPR(dst) ); |
| 0 | 10204 ins_pipe( fpu_mem_reg_reg ); |
| 10205 %} | |
| 10206 // | |
| 10207 // This instruction does not round to 24-bits | |
|
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10208 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10209 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10210 match(Set dst (SubF dst src)); | |
| 10211 | |
| 10212 format %{ "FSUB $dst,$src" %} | |
| 10213 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
|
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|
10214 ins_encode( Push_Reg_FPR(src), |
| 0 | 10215 OpcP, RegOpc(dst) ); |
| 10216 ins_pipe( fpu_reg_reg ); | |
| 10217 %} | |
| 10218 | |
| 10219 // Spill to obtain 24-bit precision | |
|
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10220 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10221 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10222 match(Set dst (AddF src1 src2)); | |
| 10223 | |
| 10224 format %{ "FADD $dst,$src1,$src2" %} | |
| 10225 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
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10226 ins_encode( Push_Reg_FPR(src2), |
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10227 OpcReg_FPR(src1), |
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10228 Pop_Mem_FPR(dst) ); |
| 0 | 10229 ins_pipe( fpu_mem_reg_reg ); |
| 10230 %} | |
| 10231 // | |
| 10232 // This instruction does not round to 24-bits | |
|
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10233 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10234 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10235 match(Set dst (AddF dst src)); | |
| 10236 | |
| 10237 format %{ "FLD $src\n\t" | |
| 10238 "FADDp $dst,ST" %} | |
| 10239 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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10240 ins_encode( Push_Reg_FPR(src), |
| 0 | 10241 OpcP, RegOpc(dst) ); |
| 10242 ins_pipe( fpu_reg_reg ); | |
| 10243 %} | |
| 10244 | |
|
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10245 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10246 predicate(UseSSE==0); |
| 10247 match(Set dst (AbsF src)); | |
| 10248 ins_cost(100); | |
| 10249 format %{ "FABS" %} | |
| 10250 opcode(0xE1, 0xD9); | |
| 10251 ins_encode( OpcS, OpcP ); | |
| 10252 ins_pipe( fpu_reg_reg ); | |
| 10253 %} | |
| 10254 | |
|
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10255 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10256 predicate(UseSSE==0); |
| 10257 match(Set dst (NegF src)); | |
| 10258 ins_cost(100); | |
| 10259 format %{ "FCHS" %} | |
| 10260 opcode(0xE0, 0xD9); | |
| 10261 ins_encode( OpcS, OpcP ); | |
| 10262 ins_pipe( fpu_reg_reg ); | |
| 10263 %} | |
| 10264 | |
|
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10265 // Cisc-alternate to addFPR_reg |
| 0 | 10266 // Spill to obtain 24-bit precision |
|
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10267 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10268 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10269 match(Set dst (AddF src1 (LoadF src2))); | |
| 10270 | |
| 10271 format %{ "FLD $src2\n\t" | |
| 10272 "FADD ST,$src1\n\t" | |
| 10273 "FSTP_S $dst" %} | |
| 10274 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10275 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10276 OpcReg_FPR(src1), |
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10277 Pop_Mem_FPR(dst) ); |
| 0 | 10278 ins_pipe( fpu_mem_reg_mem ); |
| 10279 %} | |
| 10280 // | |
|
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10281 // Cisc-alternate to addFPR_reg |
| 0 | 10282 // This instruction does not round to 24-bits |
|
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10283 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10284 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10285 match(Set dst (AddF dst (LoadF src))); | |
| 10286 | |
| 10287 format %{ "FADD $dst,$src" %} | |
| 10288 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10289 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10290 OpcP, RegOpc(dst) ); | |
| 10291 ins_pipe( fpu_reg_mem ); | |
| 10292 %} | |
| 10293 | |
| 10294 // // Following two instructions for _222_mpegaudio | |
| 10295 // Spill to obtain 24-bit precision | |
|
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10296 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10297 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10298 match(Set dst (AddF src1 src2)); | |
| 10299 | |
| 10300 format %{ "FADD $dst,$src1,$src2" %} | |
| 10301 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10302 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
|
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10303 OpcReg_FPR(src2), |
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10304 Pop_Mem_FPR(dst) ); |
| 0 | 10305 ins_pipe( fpu_mem_reg_mem ); |
| 10306 %} | |
| 10307 | |
| 10308 // Cisc-spill variant | |
| 10309 // Spill to obtain 24-bit precision | |
|
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10310 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10311 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10312 match(Set dst (AddF src1 (LoadF src2))); | |
| 10313 | |
| 10314 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10315 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10316 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10317 set_instruction_start, | |
| 10318 OpcP, RMopc_Mem(secondary,src1), | |
|
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10319 Pop_Mem_FPR(dst) ); |
| 0 | 10320 ins_pipe( fpu_mem_mem_mem ); |
| 10321 %} | |
| 10322 | |
| 10323 // Spill to obtain 24-bit precision | |
|
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10324 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10325 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10326 match(Set dst (AddF src1 src2)); | |
| 10327 | |
| 10328 format %{ "FADD $dst,$src1,$src2" %} | |
| 10329 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10330 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10331 set_instruction_start, | |
| 10332 OpcP, RMopc_Mem(secondary,src1), | |
|
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10333 Pop_Mem_FPR(dst) ); |
| 0 | 10334 ins_pipe( fpu_mem_mem_mem ); |
| 10335 %} | |
| 10336 | |
| 10337 | |
| 10338 // Spill to obtain 24-bit precision | |
|
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10339 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10340 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10341 match(Set dst (AddF src con)); |
| 10342 format %{ "FLD $src\n\t" | |
| 10343 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10344 "FSTP_S $dst" %} |
| 2008 | 10345 ins_encode %{ |
| 10346 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10347 __ fadd_s($constantaddress($con)); | |
| 10348 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10349 %} | |
| 10350 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10351 %} |
| 10352 // | |
| 10353 // This instruction does not round to 24-bits | |
|
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10354 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10355 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10356 match(Set dst (AddF src con)); |
| 10357 format %{ "FLD $src\n\t" | |
| 10358 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10359 "FSTP $dst" %} | |
| 10360 ins_encode %{ | |
| 10361 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10362 __ fadd_s($constantaddress($con)); | |
| 10363 __ fstp_d($dst$$reg); | |
| 10364 %} | |
| 10365 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10366 %} |
| 10367 | |
| 10368 // Spill to obtain 24-bit precision | |
|
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10369 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10370 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10371 match(Set dst (MulF src1 src2)); | |
| 10372 | |
| 10373 format %{ "FLD $src1\n\t" | |
| 10374 "FMUL $src2\n\t" | |
| 10375 "FSTP_S $dst" %} | |
| 10376 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
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10377 ins_encode( Push_Reg_FPR(src1), |
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10378 OpcReg_FPR(src2), |
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10379 Pop_Mem_FPR(dst) ); |
| 0 | 10380 ins_pipe( fpu_mem_reg_reg ); |
| 10381 %} | |
| 10382 // | |
| 10383 // This instruction does not round to 24-bits | |
|
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10384 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10385 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10386 match(Set dst (MulF src1 src2)); | |
| 10387 | |
| 10388 format %{ "FLD $src1\n\t" | |
| 10389 "FMUL $src2\n\t" | |
| 10390 "FSTP_S $dst" %} | |
| 10391 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
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10392 ins_encode( Push_Reg_FPR(src2), |
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10393 OpcReg_FPR(src1), |
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10394 Pop_Reg_FPR(dst) ); |
| 0 | 10395 ins_pipe( fpu_reg_reg_reg ); |
| 10396 %} | |
| 10397 | |
| 10398 | |
| 10399 // Spill to obtain 24-bit precision | |
| 10400 // Cisc-alternate to reg-reg multiply | |
|
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10401 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10402 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10403 match(Set dst (MulF src1 (LoadF src2))); | |
| 10404 | |
| 10405 format %{ "FLD_S $src2\n\t" | |
| 10406 "FMUL $src1\n\t" | |
| 10407 "FSTP_S $dst" %} | |
| 10408 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10409 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10410 OpcReg_FPR(src1), |
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10411 Pop_Mem_FPR(dst) ); |
| 0 | 10412 ins_pipe( fpu_mem_reg_mem ); |
| 10413 %} | |
| 10414 // | |
| 10415 // This instruction does not round to 24-bits | |
| 10416 // Cisc-alternate to reg-reg multiply | |
|
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10417 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10418 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10419 match(Set dst (MulF src1 (LoadF src2))); | |
| 10420 | |
| 10421 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10422 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10423 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10424 OpcReg_FPR(src1), |
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10425 Pop_Reg_FPR(dst) ); |
| 0 | 10426 ins_pipe( fpu_reg_reg_mem ); |
| 10427 %} | |
| 10428 | |
| 10429 // Spill to obtain 24-bit precision | |
|
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10430 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10431 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10432 match(Set dst (MulF src1 src2)); | |
| 10433 | |
| 10434 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10435 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10436 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10437 set_instruction_start, | |
| 10438 OpcP, RMopc_Mem(secondary,src1), | |
|
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10439 Pop_Mem_FPR(dst) ); |
| 0 | 10440 ins_pipe( fpu_mem_mem_mem ); |
| 10441 %} | |
| 10442 | |
| 10443 // Spill to obtain 24-bit precision | |
|
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10444 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10445 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10446 match(Set dst (MulF src con)); |
| 10447 | |
| 10448 format %{ "FLD $src\n\t" | |
| 10449 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10450 "FSTP_S $dst" %} | |
| 10451 ins_encode %{ | |
| 10452 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10453 __ fmul_s($constantaddress($con)); | |
| 10454 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10455 %} | |
| 10456 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10457 %} |
| 10458 // | |
| 10459 // This instruction does not round to 24-bits | |
|
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10460 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10461 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10462 match(Set dst (MulF src con)); |
| 10463 | |
| 10464 format %{ "FLD $src\n\t" | |
| 10465 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10466 "FSTP $dst" %} | |
| 10467 ins_encode %{ | |
| 10468 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10469 __ fmul_s($constantaddress($con)); | |
| 10470 __ fstp_d($dst$$reg); | |
| 10471 %} | |
| 10472 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10473 %} |
| 10474 | |
| 10475 | |
| 10476 // | |
|
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10477 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10478 // This instruction does not round to 24-bits |
|
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10479 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10480 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10481 match(Set dst (MulF (LoadF mem1) src)); | |
| 10482 | |
| 10483 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10484 "FMUL ST,$src\n\t" | |
| 10485 "FSTP $dst" %} | |
| 10486 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10487 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10488 OpcReg_FPR(src), |
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10489 Pop_Reg_FPR(dst) ); |
| 0 | 10490 ins_pipe( fpu_reg_reg_mem ); |
| 10491 %} | |
| 10492 // | |
|
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10493 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10494 // This instruction does not round to 24-bits |
|
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10495 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10496 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10497 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10498 ins_cost(95); | |
| 10499 | |
| 10500 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10501 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10502 "FADD ST,$src2\n\t" |
| 10503 "FSTP $dst" %} | |
| 10504 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10505 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10506 FMul_ST_reg(src1), | |
| 10507 FAdd_ST_reg(src2), | |
|
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10508 Pop_Reg_FPR(dst) ); |
| 0 | 10509 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10510 %} | |
| 10511 | |
|
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10512 // MACRO3 -- addFPR a mulFPR |
| 0 | 10513 // This instruction does not round to 24-bits. It is a '2-address' |
| 10514 // instruction in that the result goes back to src2. This eliminates | |
| 10515 // a move from the macro; possibly the register allocator will have | |
| 10516 // to add it back (and maybe not). | |
|
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10517 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10518 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10519 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10520 | |
| 10521 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10522 "FMUL ST,$src1\n\t" | |
| 10523 "FADDP $src2,ST" %} | |
| 10524 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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|
10525 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10526 FMul_ST_reg(src1), |
| 10527 FAddP_reg_ST(src2) ); | |
| 10528 ins_pipe( fpu_reg_reg_reg ); | |
| 10529 %} | |
| 10530 | |
|
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10531 // MACRO4 -- divFPR subFPR |
| 0 | 10532 // This instruction does not round to 24-bits |
|
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10533 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10534 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10535 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10536 | |
| 10537 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10538 "FSUB ST,$src1\n\t" | |
| 10539 "FDIV ST,$src3\n\t" | |
| 10540 "FSTP $dst" %} | |
| 10541 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10542 ins_encode( Push_Reg_FPR(src2), |
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10543 subFPR_divFPR_encode(src1,src3), |
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10544 Pop_Reg_FPR(dst) ); |
| 0 | 10545 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10546 %} | |
| 10547 | |
| 10548 // Spill to obtain 24-bit precision | |
|
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10549 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10550 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10551 match(Set dst (DivF src1 src2)); | |
| 10552 | |
| 10553 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10554 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
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10555 ins_encode( Push_Reg_FPR(src1), |
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10556 OpcReg_FPR(src2), |
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10557 Pop_Mem_FPR(dst) ); |
| 0 | 10558 ins_pipe( fpu_mem_reg_reg ); |
| 10559 %} | |
| 10560 // | |
| 10561 // This instruction does not round to 24-bits | |
|
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10562 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10563 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10564 match(Set dst (DivF dst src)); | |
| 10565 | |
| 10566 format %{ "FDIV $dst,$src" %} | |
| 10567 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10568 ins_encode( Push_Reg_FPR(src), |
| 0 | 10569 OpcP, RegOpc(dst) ); |
| 10570 ins_pipe( fpu_reg_reg ); | |
| 10571 %} | |
| 10572 | |
| 10573 | |
| 10574 // Spill to obtain 24-bit precision | |
|
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10575 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10576 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10577 match(Set dst (ModF src1 src2)); | |
|
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10578 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10579 |
| 10580 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10581 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10582 emitModDPR(), |
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10583 Push_Result_Mod_DPR(src2), |
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10584 Pop_Mem_FPR(dst)); |
| 0 | 10585 ins_pipe( pipe_slow ); |
| 10586 %} | |
| 10587 // | |
| 10588 // This instruction does not round to 24-bits | |
|
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10589 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10590 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10591 match(Set dst (ModF dst src)); | |
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10592 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10593 |
| 10594 format %{ "FMOD $dst,$src" %} | |
|
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10595 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10596 emitModDPR(), |
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10597 Push_Result_Mod_DPR(src), |
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10598 Pop_Reg_FPR(dst)); |
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10599 ins_pipe( pipe_slow ); |
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10600 %} |
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10601 |
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10602 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10603 predicate(UseSSE>=1); |
| 10604 match(Set dst (ModF src0 src1)); | |
| 10605 effect(KILL rax, KILL cr); | |
| 10606 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10607 "\tMOVSS [ESP+0],$src1\n" | |
| 10608 "\tFLD_S [ESP+0]\n" | |
| 10609 "\tMOVSS [ESP+0],$src0\n" | |
| 10610 "\tFLD_S [ESP+0]\n" | |
| 10611 "loop:\tFPREM\n" | |
| 10612 "\tFWAIT\n" | |
| 10613 "\tFNSTSW AX\n" | |
| 10614 "\tSAHF\n" | |
| 10615 "\tJP loop\n" | |
| 10616 "\tFSTP_S [ESP+0]\n" | |
| 10617 "\tMOVSS $dst,[ESP+0]\n" | |
| 10618 "\tADD ESP,4\n" | |
| 10619 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10620 %} | |
| 10621 ins_cost(250); | |
|
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10622 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10623 ins_pipe( pipe_slow ); |
| 10624 %} | |
| 10625 | |
| 10626 | |
| 10627 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10628 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10629 | |
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10630 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10631 predicate(UseSSE==0); |
| 10632 match(Set dst (RoundFloat src)); | |
| 10633 ins_cost(125); | |
| 10634 format %{ "FST_S $dst,$src\t# F-round" %} | |
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10635 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10636 ins_pipe( fpu_mem_reg ); |
| 10637 %} | |
| 10638 | |
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10639 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10640 predicate(UseSSE<=1); |
| 10641 match(Set dst (RoundDouble src)); | |
| 10642 ins_cost(125); | |
| 10643 format %{ "FST_D $dst,$src\t# D-round" %} | |
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10644 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10645 ins_pipe( fpu_mem_reg ); |
| 10646 %} | |
| 10647 | |
| 10648 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10649 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10650 predicate(UseSSE==0); |
| 10651 match(Set dst (ConvD2F src)); | |
| 10652 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10653 expand %{ | |
| 10654 roundFloat_mem_reg(dst,src); | |
| 10655 %} | |
| 10656 %} | |
| 10657 | |
| 10658 // Force rounding to 24-bit precision and 6-bit exponent | |
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10659 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10660 predicate(UseSSE==1); |
| 10661 match(Set dst (ConvD2F src)); | |
| 10662 effect( KILL cr ); | |
| 10663 format %{ "SUB ESP,4\n\t" | |
| 10664 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10665 "MOVSS $dst,[ESP]\n\t" | |
| 10666 "ADD ESP,4" %} | |
| 4759 | 10667 ins_encode %{ |
| 10668 __ subptr(rsp, 4); | |
| 10669 if ($src$$reg != FPR1L_enc) { | |
| 10670 __ fld_s($src$$reg-1); | |
| 10671 __ fstp_s(Address(rsp, 0)); | |
| 10672 } else { | |
| 10673 __ fst_s(Address(rsp, 0)); | |
| 10674 } | |
| 10675 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10676 __ addptr(rsp, 4); | |
| 10677 %} | |
| 0 | 10678 ins_pipe( pipe_slow ); |
| 10679 %} | |
| 10680 | |
| 10681 // Force rounding double precision to single precision | |
|
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10682 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10683 predicate(UseSSE>=2); |
| 10684 match(Set dst (ConvD2F src)); | |
| 10685 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10686 ins_encode %{ |
| 10687 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10688 %} | |
| 0 | 10689 ins_pipe( pipe_slow ); |
| 10690 %} | |
| 10691 | |
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10692 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10693 predicate(UseSSE==0); |
| 10694 match(Set dst (ConvF2D src)); | |
| 10695 format %{ "FST_S $dst,$src\t# D-round" %} | |
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10696 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10697 ins_pipe( fpu_reg_reg ); |
| 10698 %} | |
| 10699 | |
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10700 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10701 predicate(UseSSE==1); |
| 10702 match(Set dst (ConvF2D src)); | |
| 10703 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10704 expand %{ | |
| 10705 roundDouble_mem_reg(dst,src); | |
| 10706 %} | |
| 10707 %} | |
| 10708 | |
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10709 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10710 predicate(UseSSE==1); |
| 10711 match(Set dst (ConvF2D src)); | |
| 10712 effect( KILL cr ); | |
| 10713 format %{ "SUB ESP,4\n\t" | |
| 10714 "MOVSS [ESP] $src\n\t" | |
| 10715 "FLD_S [ESP]\n\t" | |
| 10716 "ADD ESP,4\n\t" | |
| 10717 "FSTP $dst\t# D-round" %} | |
| 4759 | 10718 ins_encode %{ |
| 10719 __ subptr(rsp, 4); | |
| 10720 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10721 __ fld_s(Address(rsp, 0)); | |
| 10722 __ addptr(rsp, 4); | |
| 10723 __ fstp_d($dst$$reg); | |
| 10724 %} | |
| 0 | 10725 ins_pipe( pipe_slow ); |
| 10726 %} | |
| 10727 | |
|
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10728 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10729 predicate(UseSSE>=2); |
| 10730 match(Set dst (ConvF2D src)); | |
| 10731 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10732 ins_encode %{ |
| 10733 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10734 %} | |
| 0 | 10735 ins_pipe( pipe_slow ); |
| 10736 %} | |
| 10737 | |
| 10738 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10739 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10740 predicate(UseSSE<=1); |
| 10741 match(Set dst (ConvD2I src)); | |
| 10742 effect( KILL tmp, KILL cr ); | |
| 10743 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10744 "FLDCW trunc mode\n\t" | |
| 10745 "SUB ESP,4\n\t" | |
| 10746 "FISTp [ESP + #0]\n\t" | |
| 10747 "FLDCW std/24-bit mode\n\t" | |
| 10748 "POP EAX\n\t" | |
| 10749 "CMP EAX,0x80000000\n\t" | |
| 10750 "JNE,s fast\n\t" | |
| 10751 "FLD_D $src\n\t" | |
| 10752 "CALL d2i_wrapper\n" | |
| 10753 "fast:" %} | |
|
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10754 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10755 ins_pipe( pipe_slow ); |
| 10756 %} | |
| 10757 | |
| 10758 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
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10759 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10760 predicate(UseSSE>=2); |
| 10761 match(Set dst (ConvD2I src)); | |
| 10762 effect( KILL tmp, KILL cr ); | |
| 10763 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10764 "CMP $dst,0x80000000\n\t" | |
| 10765 "JNE,s fast\n\t" | |
| 10766 "SUB ESP, 8\n\t" | |
| 10767 "MOVSD [ESP], $src\n\t" | |
| 10768 "FLD_D [ESP]\n\t" | |
| 10769 "ADD ESP, 8\n\t" | |
| 10770 "CALL d2i_wrapper\n" | |
| 10771 "fast:" %} | |
| 4759 | 10772 ins_encode %{ |
| 10773 Label fast; | |
| 10774 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10775 __ cmpl($dst$$Register, 0x80000000); | |
| 10776 __ jccb(Assembler::notEqual, fast); | |
| 10777 __ subptr(rsp, 8); | |
| 10778 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10779 __ fld_d(Address(rsp, 0)); | |
| 10780 __ addptr(rsp, 8); | |
| 10781 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10782 __ bind(fast); | |
| 10783 %} | |
| 0 | 10784 ins_pipe( pipe_slow ); |
| 10785 %} | |
| 10786 | |
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10787 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10788 predicate(UseSSE<=1); |
| 10789 match(Set dst (ConvD2L src)); | |
| 10790 effect( KILL cr ); | |
| 10791 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10792 "FLDCW trunc mode\n\t" | |
| 10793 "SUB ESP,8\n\t" | |
| 10794 "FISTp [ESP + #0]\n\t" | |
| 10795 "FLDCW std/24-bit mode\n\t" | |
| 10796 "POP EAX\n\t" | |
| 10797 "POP EDX\n\t" | |
| 10798 "CMP EDX,0x80000000\n\t" | |
| 10799 "JNE,s fast\n\t" | |
| 10800 "TEST EAX,EAX\n\t" | |
| 10801 "JNE,s fast\n\t" | |
| 10802 "FLD $src\n\t" | |
| 10803 "CALL d2l_wrapper\n" | |
| 10804 "fast:" %} | |
|
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10805 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10806 ins_pipe( pipe_slow ); |
| 10807 %} | |
| 10808 | |
| 10809 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
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10810 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10811 predicate (UseSSE>=2); |
| 10812 match(Set dst (ConvD2L src)); | |
| 10813 effect( KILL cr ); | |
| 10814 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10815 "MOVSD [ESP],$src\n\t" | |
| 10816 "FLD_D [ESP]\n\t" | |
| 10817 "FLDCW trunc mode\n\t" | |
| 10818 "FISTp [ESP + #0]\n\t" | |
| 10819 "FLDCW std/24-bit mode\n\t" | |
| 10820 "POP EAX\n\t" | |
| 10821 "POP EDX\n\t" | |
| 10822 "CMP EDX,0x80000000\n\t" | |
| 10823 "JNE,s fast\n\t" | |
| 10824 "TEST EAX,EAX\n\t" | |
| 10825 "JNE,s fast\n\t" | |
| 10826 "SUB ESP,8\n\t" | |
| 10827 "MOVSD [ESP],$src\n\t" | |
| 10828 "FLD_D [ESP]\n\t" | |
| 4759 | 10829 "ADD ESP,8\n\t" |
| 0 | 10830 "CALL d2l_wrapper\n" |
| 10831 "fast:" %} | |
| 4759 | 10832 ins_encode %{ |
| 10833 Label fast; | |
| 10834 __ subptr(rsp, 8); | |
| 10835 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10836 __ fld_d(Address(rsp, 0)); | |
| 10837 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10838 __ fistp_d(Address(rsp, 0)); | |
| 10839 // Restore the rounding mode, mask the exception | |
| 10840 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10841 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10842 } else { | |
| 10843 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10844 } | |
| 10845 // Load the converted long, adjust CPU stack | |
| 10846 __ pop(rax); | |
| 10847 __ pop(rdx); | |
| 10848 __ cmpl(rdx, 0x80000000); | |
| 10849 __ jccb(Assembler::notEqual, fast); | |
| 10850 __ testl(rax, rax); | |
| 10851 __ jccb(Assembler::notEqual, fast); | |
| 10852 __ subptr(rsp, 8); | |
| 10853 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10854 __ fld_d(Address(rsp, 0)); | |
| 10855 __ addptr(rsp, 8); | |
| 10856 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10857 __ bind(fast); | |
| 10858 %} | |
| 0 | 10859 ins_pipe( pipe_slow ); |
| 10860 %} | |
| 10861 | |
| 10862 // Convert a double to an int. Java semantics require we do complex | |
| 10863 // manglations in the corner cases. So we set the rounding mode to | |
| 10864 // 'zero', store the darned double down as an int, and reset the | |
| 10865 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10866 // if we would overflow or converted a NAN; we check for this and | |
| 10867 // and go the slow path if needed. | |
|
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10868 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10869 predicate(UseSSE==0); |
| 10870 match(Set dst (ConvF2I src)); | |
| 10871 effect( KILL tmp, KILL cr ); | |
| 10872 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10873 "FLDCW trunc mode\n\t" | |
| 10874 "SUB ESP,4\n\t" | |
| 10875 "FISTp [ESP + #0]\n\t" | |
| 10876 "FLDCW std/24-bit mode\n\t" | |
| 10877 "POP EAX\n\t" | |
| 10878 "CMP EAX,0x80000000\n\t" | |
| 10879 "JNE,s fast\n\t" | |
| 10880 "FLD $src\n\t" | |
| 10881 "CALL d2i_wrapper\n" | |
| 10882 "fast:" %} | |
|
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10883 // DPR2I_encoding works for FPR2I |
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10884 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10885 ins_pipe( pipe_slow ); |
| 10886 %} | |
| 10887 | |
| 10888 // Convert a float in xmm to an int reg. | |
|
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10889 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 10890 predicate(UseSSE>=1); |
| 10891 match(Set dst (ConvF2I src)); | |
| 10892 effect( KILL tmp, KILL cr ); | |
| 10893 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 10894 "CMP $dst,0x80000000\n\t" | |
| 10895 "JNE,s fast\n\t" | |
| 10896 "SUB ESP, 4\n\t" | |
| 10897 "MOVSS [ESP], $src\n\t" | |
| 10898 "FLD [ESP]\n\t" | |
| 10899 "ADD ESP, 4\n\t" | |
| 10900 "CALL d2i_wrapper\n" | |
| 10901 "fast:" %} | |
| 4759 | 10902 ins_encode %{ |
| 10903 Label fast; | |
| 10904 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10905 __ cmpl($dst$$Register, 0x80000000); | |
| 10906 __ jccb(Assembler::notEqual, fast); | |
| 10907 __ subptr(rsp, 4); | |
| 10908 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10909 __ fld_s(Address(rsp, 0)); | |
| 10910 __ addptr(rsp, 4); | |
| 10911 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10912 __ bind(fast); | |
| 10913 %} | |
| 0 | 10914 ins_pipe( pipe_slow ); |
| 10915 %} | |
| 10916 | |
|
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10917 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10918 predicate(UseSSE==0); |
| 10919 match(Set dst (ConvF2L src)); | |
| 10920 effect( KILL cr ); | |
| 10921 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 10922 "FLDCW trunc mode\n\t" | |
| 10923 "SUB ESP,8\n\t" | |
| 10924 "FISTp [ESP + #0]\n\t" | |
| 10925 "FLDCW std/24-bit mode\n\t" | |
| 10926 "POP EAX\n\t" | |
| 10927 "POP EDX\n\t" | |
| 10928 "CMP EDX,0x80000000\n\t" | |
| 10929 "JNE,s fast\n\t" | |
| 10930 "TEST EAX,EAX\n\t" | |
| 10931 "JNE,s fast\n\t" | |
| 10932 "FLD $src\n\t" | |
| 10933 "CALL d2l_wrapper\n" | |
| 10934 "fast:" %} | |
|
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10935 // DPR2L_encoding works for FPR2L |
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10936 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 10937 ins_pipe( pipe_slow ); |
| 10938 %} | |
| 10939 | |
| 10940 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10941 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 10942 predicate (UseSSE>=1); |
| 10943 match(Set dst (ConvF2L src)); | |
| 10944 effect( KILL cr ); | |
| 10945 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 10946 "MOVSS [ESP],$src\n\t" | |
| 10947 "FLD_S [ESP]\n\t" | |
| 10948 "FLDCW trunc mode\n\t" | |
| 10949 "FISTp [ESP + #0]\n\t" | |
| 10950 "FLDCW std/24-bit mode\n\t" | |
| 10951 "POP EAX\n\t" | |
| 10952 "POP EDX\n\t" | |
| 10953 "CMP EDX,0x80000000\n\t" | |
| 10954 "JNE,s fast\n\t" | |
| 10955 "TEST EAX,EAX\n\t" | |
| 10956 "JNE,s fast\n\t" | |
| 10957 "SUB ESP,4\t# Convert float to long\n\t" | |
| 10958 "MOVSS [ESP],$src\n\t" | |
| 10959 "FLD_S [ESP]\n\t" | |
| 10960 "ADD ESP,4\n\t" | |
| 10961 "CALL d2l_wrapper\n" | |
| 10962 "fast:" %} | |
| 4759 | 10963 ins_encode %{ |
| 10964 Label fast; | |
| 10965 __ subptr(rsp, 8); | |
| 10966 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10967 __ fld_s(Address(rsp, 0)); | |
| 10968 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10969 __ fistp_d(Address(rsp, 0)); | |
| 10970 // Restore the rounding mode, mask the exception | |
| 10971 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10972 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10973 } else { | |
| 10974 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10975 } | |
| 10976 // Load the converted long, adjust CPU stack | |
| 10977 __ pop(rax); | |
| 10978 __ pop(rdx); | |
| 10979 __ cmpl(rdx, 0x80000000); | |
| 10980 __ jccb(Assembler::notEqual, fast); | |
| 10981 __ testl(rax, rax); | |
| 10982 __ jccb(Assembler::notEqual, fast); | |
| 10983 __ subptr(rsp, 4); | |
| 10984 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10985 __ fld_s(Address(rsp, 0)); | |
| 10986 __ addptr(rsp, 4); | |
| 10987 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10988 __ bind(fast); | |
| 10989 %} | |
| 0 | 10990 ins_pipe( pipe_slow ); |
| 10991 %} | |
| 10992 | |
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10993 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 10994 predicate( UseSSE<=1 ); |
| 10995 match(Set dst (ConvI2D src)); | |
| 10996 format %{ "FILD $src\n\t" | |
| 10997 "FSTP $dst" %} | |
| 10998 opcode(0xDB, 0x0); /* DB /0 */ | |
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10999 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11000 ins_pipe( fpu_reg_mem ); |
| 11001 %} | |
| 11002 | |
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11003 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11004 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11005 match(Set dst (ConvI2D src)); |
| 11006 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11007 ins_encode %{ |
| 11008 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11009 %} | |
| 0 | 11010 ins_pipe( pipe_slow ); |
| 11011 %} | |
| 11012 | |
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11013 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11014 predicate( UseSSE>=2 ); |
| 11015 match(Set dst (ConvI2D (LoadI mem))); | |
| 11016 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11017 ins_encode %{ |
| 11018 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11019 %} | |
| 0 | 11020 ins_pipe( pipe_slow ); |
| 11021 %} | |
| 11022 | |
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11023 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11024 %{ |
| 11025 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11026 match(Set dst (ConvI2D src)); | |
| 11027 | |
| 11028 format %{ "MOVD $dst,$src\n\t" | |
| 11029 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11030 ins_encode %{ | |
| 304 | 11031 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11032 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11033 %} | |
| 11034 ins_pipe(pipe_slow); // XXX | |
| 11035 %} | |
| 11036 | |
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11037 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11038 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11039 match(Set dst (ConvI2D (LoadI mem))); | |
| 11040 format %{ "FILD $mem\n\t" | |
| 11041 "FSTP $dst" %} | |
| 11042 opcode(0xDB); /* DB /0 */ | |
| 11043 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11044 Pop_Reg_DPR(dst)); |
| 0 | 11045 ins_pipe( fpu_reg_mem ); |
| 11046 %} | |
| 11047 | |
| 11048 // Convert a byte to a float; no rounding step needed. | |
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11049 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11050 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11051 match(Set dst (ConvI2F src)); | |
| 11052 format %{ "FILD $src\n\t" | |
| 11053 "FSTP $dst" %} | |
| 11054 | |
| 11055 opcode(0xDB, 0x0); /* DB /0 */ | |
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11056 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11057 ins_pipe( fpu_reg_mem ); |
| 11058 %} | |
| 11059 | |
| 11060 // In 24-bit mode, force exponent rounding by storing back out | |
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11061 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11062 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11063 match(Set dst (ConvI2F src)); | |
| 11064 ins_cost(200); | |
| 11065 format %{ "FILD $src\n\t" | |
| 11066 "FSTP_S $dst" %} | |
| 11067 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11068 ins_encode( Push_Mem_I(src), | |
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11069 Pop_Mem_FPR(dst)); |
| 0 | 11070 ins_pipe( fpu_mem_mem ); |
| 11071 %} | |
| 11072 | |
| 11073 // In 24-bit mode, force exponent rounding by storing back out | |
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11074 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11075 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11076 match(Set dst (ConvI2F (LoadI mem))); | |
| 11077 ins_cost(200); | |
| 11078 format %{ "FILD $mem\n\t" | |
| 11079 "FSTP_S $dst" %} | |
| 11080 opcode(0xDB); /* DB /0 */ | |
| 11081 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11082 Pop_Mem_FPR(dst)); |
| 0 | 11083 ins_pipe( fpu_mem_mem ); |
| 11084 %} | |
| 11085 | |
| 11086 // This instruction does not round to 24-bits | |
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11087 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11088 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11089 match(Set dst (ConvI2F src)); | |
| 11090 format %{ "FILD $src\n\t" | |
| 11091 "FSTP $dst" %} | |
| 11092 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11093 ins_encode( Push_Mem_I(src), | |
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11094 Pop_Reg_FPR(dst)); |
| 0 | 11095 ins_pipe( fpu_reg_mem ); |
| 11096 %} | |
| 11097 | |
| 11098 // This instruction does not round to 24-bits | |
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11099 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11100 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11101 match(Set dst (ConvI2F (LoadI mem))); | |
| 11102 format %{ "FILD $mem\n\t" | |
| 11103 "FSTP $dst" %} | |
| 11104 opcode(0xDB); /* DB /0 */ | |
| 11105 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11106 Pop_Reg_FPR(dst)); |
| 0 | 11107 ins_pipe( fpu_reg_mem ); |
| 11108 %} | |
| 11109 | |
| 11110 // Convert an int to a float in xmm; no rounding step needed. | |
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11111 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11112 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11113 match(Set dst (ConvI2F src)); |
| 11114 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11115 ins_encode %{ |
| 11116 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11117 %} | |
| 0 | 11118 ins_pipe( pipe_slow ); |
| 11119 %} | |
| 11120 | |
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11121 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11122 %{ |
| 11123 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11124 match(Set dst (ConvI2F src)); | |
| 11125 | |
| 11126 format %{ "MOVD $dst,$src\n\t" | |
| 11127 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11128 ins_encode %{ | |
| 304 | 11129 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11130 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11131 %} | |
| 11132 ins_pipe(pipe_slow); // XXX | |
| 11133 %} | |
| 11134 | |
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11135 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11136 match(Set dst (ConvI2L src)); |
| 11137 effect(KILL cr); | |
| 624 | 11138 ins_cost(375); |
| 0 | 11139 format %{ "MOV $dst.lo,$src\n\t" |
| 11140 "MOV $dst.hi,$src\n\t" | |
| 11141 "SAR $dst.hi,31" %} | |
| 11142 ins_encode(convert_int_long(dst,src)); | |
| 11143 ins_pipe( ialu_reg_reg_long ); | |
| 11144 %} | |
| 11145 | |
| 11146 // Zero-extend convert int to long | |
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11147 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11148 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11149 effect( KILL flags ); | |
| 624 | 11150 ins_cost(250); |
| 0 | 11151 format %{ "MOV $dst.lo,$src\n\t" |
| 11152 "XOR $dst.hi,$dst.hi" %} | |
| 11153 opcode(0x33); // XOR | |
| 11154 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11155 ins_pipe( ialu_reg_reg_long ); | |
| 11156 %} | |
| 11157 | |
| 11158 // Zero-extend long | |
| 11159 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11160 match(Set dst (AndL src mask) ); | |
| 11161 effect( KILL flags ); | |
| 624 | 11162 ins_cost(250); |
| 0 | 11163 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11164 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11165 opcode(0x33); // XOR | |
| 11166 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11167 ins_pipe( ialu_reg_reg_long ); | |
| 11168 %} | |
| 11169 | |
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11170 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11171 predicate (UseSSE<=1); |
| 11172 match(Set dst (ConvL2D src)); | |
| 11173 effect( KILL cr ); | |
| 11174 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11175 "PUSH $src.lo\n\t" | |
| 11176 "FILD ST,[ESP + #0]\n\t" | |
| 11177 "ADD ESP,8\n\t" | |
| 11178 "FSTP_D $dst\t# D-round" %} | |
| 11179 opcode(0xDF, 0x5); /* DF /5 */ | |
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11180 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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11181 ins_pipe( pipe_slow ); |
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11182 %} |
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11183 |
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11184 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11185 predicate (UseSSE>=2); |
| 11186 match(Set dst (ConvL2D src)); | |
| 11187 effect( KILL cr ); | |
| 11188 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11189 "PUSH $src.lo\n\t" | |
| 11190 "FILD_D [ESP]\n\t" | |
| 11191 "FSTP_D [ESP]\n\t" | |
| 11192 "MOVSD $dst,[ESP]\n\t" | |
| 11193 "ADD ESP,8" %} | |
| 11194 opcode(0xDF, 0x5); /* DF /5 */ | |
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11195 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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11196 ins_pipe( pipe_slow ); |
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11197 %} |
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11198 |
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11199 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11200 predicate (UseSSE>=1); |
| 11201 match(Set dst (ConvL2F src)); | |
| 11202 effect( KILL cr ); | |
| 11203 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11204 "PUSH $src.lo\n\t" | |
| 11205 "FILD_D [ESP]\n\t" | |
| 11206 "FSTP_S [ESP]\n\t" | |
| 11207 "MOVSS $dst,[ESP]\n\t" | |
| 11208 "ADD ESP,8" %} | |
| 11209 opcode(0xDF, 0x5); /* DF /5 */ | |
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11210 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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11211 ins_pipe( pipe_slow ); |
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11212 %} |
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11213 |
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11214 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11215 match(Set dst (ConvL2F src)); |
| 11216 effect( KILL cr ); | |
| 11217 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11218 "PUSH $src.lo\n\t" | |
| 11219 "FILD ST,[ESP + #0]\n\t" | |
| 11220 "ADD ESP,8\n\t" | |
| 11221 "FSTP_S $dst\t# F-round" %} | |
| 11222 opcode(0xDF, 0x5); /* DF /5 */ | |
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11223 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11224 ins_pipe( pipe_slow ); |
| 11225 %} | |
| 11226 | |
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11227 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11228 match(Set dst (ConvL2I src)); |
| 11229 effect( DEF dst, USE src ); | |
| 11230 format %{ "MOV $dst,$src.lo" %} | |
| 11231 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11232 ins_pipe( ialu_reg_reg ); | |
| 11233 %} | |
| 11234 | |
| 11235 | |
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11236 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11237 match(Set dst (MoveF2I src)); |
| 11238 effect( DEF dst, USE src ); | |
| 11239 ins_cost(100); | |
| 11240 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11241 ins_encode %{ |
| 11242 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11243 %} | |
| 0 | 11244 ins_pipe( ialu_reg_mem ); |
| 11245 %} | |
| 11246 | |
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11247 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11248 predicate(UseSSE==0); |
| 11249 match(Set dst (MoveF2I src)); | |
| 11250 effect( DEF dst, USE src ); | |
| 11251 | |
| 11252 ins_cost(125); | |
| 11253 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
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11254 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11255 ins_pipe( fpu_mem_reg ); |
| 11256 %} | |
| 11257 | |
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11258 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11259 predicate(UseSSE>=1); |
| 11260 match(Set dst (MoveF2I src)); | |
| 11261 effect( DEF dst, USE src ); | |
| 11262 | |
| 11263 ins_cost(95); | |
| 11264 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11265 ins_encode %{ |
| 11266 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11267 %} | |
| 0 | 11268 ins_pipe( pipe_slow ); |
| 11269 %} | |
| 11270 | |
|
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11271 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11272 predicate(UseSSE>=2); |
| 11273 match(Set dst (MoveF2I src)); | |
| 11274 effect( DEF dst, USE src ); | |
| 11275 ins_cost(85); | |
| 11276 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11277 ins_encode %{ |
| 11278 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11279 %} | |
| 0 | 11280 ins_pipe( pipe_slow ); |
| 11281 %} | |
| 11282 | |
|
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11283 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11284 match(Set dst (MoveI2F src)); |
| 11285 effect( DEF dst, USE src ); | |
| 11286 | |
| 11287 ins_cost(100); | |
| 11288 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11289 ins_encode %{ |
| 11290 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11291 %} | |
| 0 | 11292 ins_pipe( ialu_mem_reg ); |
| 11293 %} | |
| 11294 | |
| 11295 | |
|
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11296 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11297 predicate(UseSSE==0); |
| 11298 match(Set dst (MoveI2F src)); | |
| 11299 effect(DEF dst, USE src); | |
| 11300 | |
| 11301 ins_cost(125); | |
| 11302 format %{ "FLD_S $src\n\t" | |
| 11303 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11304 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11305 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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11306 Pop_Reg_FPR(dst) ); |
| 0 | 11307 ins_pipe( fpu_reg_mem ); |
| 11308 %} | |
| 11309 | |
|
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11310 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11311 predicate(UseSSE>=1); |
| 11312 match(Set dst (MoveI2F src)); | |
| 11313 effect( DEF dst, USE src ); | |
| 11314 | |
| 11315 ins_cost(95); | |
| 11316 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11317 ins_encode %{ |
| 11318 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11319 %} | |
| 0 | 11320 ins_pipe( pipe_slow ); |
| 11321 %} | |
| 11322 | |
|
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11323 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11324 predicate(UseSSE>=2); |
| 11325 match(Set dst (MoveI2F src)); | |
| 11326 effect( DEF dst, USE src ); | |
| 11327 | |
| 11328 ins_cost(85); | |
| 11329 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11330 ins_encode %{ |
| 11331 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11332 %} | |
| 0 | 11333 ins_pipe( pipe_slow ); |
| 11334 %} | |
| 11335 | |
| 11336 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11337 match(Set dst (MoveD2L src)); | |
| 11338 effect(DEF dst, USE src); | |
| 11339 | |
| 11340 ins_cost(250); | |
| 11341 format %{ "MOV $dst.lo,$src\n\t" | |
| 11342 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11343 opcode(0x8B, 0x8B); | |
| 11344 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11345 ins_pipe( ialu_mem_long_reg ); | |
| 11346 %} | |
| 11347 | |
|
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11348 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11349 predicate(UseSSE<=1); |
| 11350 match(Set dst (MoveD2L src)); | |
| 11351 effect(DEF dst, USE src); | |
| 11352 | |
| 11353 ins_cost(125); | |
| 11354 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
|
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11355 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11356 ins_pipe( fpu_mem_reg ); |
| 11357 %} | |
| 11358 | |
|
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11359 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11360 predicate(UseSSE>=2); |
| 11361 match(Set dst (MoveD2L src)); | |
| 11362 effect(DEF dst, USE src); | |
| 11363 ins_cost(95); | |
| 11364 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11365 ins_encode %{ |
| 11366 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11367 %} | |
| 0 | 11368 ins_pipe( pipe_slow ); |
| 11369 %} | |
| 11370 | |
|
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11371 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11372 predicate(UseSSE>=2); |
| 11373 match(Set dst (MoveD2L src)); | |
| 11374 effect(DEF dst, USE src, TEMP tmp); | |
| 11375 ins_cost(85); | |
| 11376 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11377 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11378 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11379 ins_encode %{ |
| 11380 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11381 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11382 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11383 %} | |
| 0 | 11384 ins_pipe( pipe_slow ); |
| 11385 %} | |
| 11386 | |
| 11387 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11388 match(Set dst (MoveL2D src)); | |
| 11389 effect(DEF dst, USE src); | |
| 11390 | |
| 11391 ins_cost(200); | |
| 11392 format %{ "MOV $dst,$src.lo\n\t" | |
| 11393 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11394 opcode(0x89, 0x89); | |
| 11395 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11396 ins_pipe( ialu_mem_long_reg ); | |
| 11397 %} | |
| 11398 | |
| 11399 | |
|
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11400 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11401 predicate(UseSSE<=1); |
| 11402 match(Set dst (MoveL2D src)); | |
| 11403 effect(DEF dst, USE src); | |
| 11404 ins_cost(125); | |
| 11405 | |
| 11406 format %{ "FLD_D $src\n\t" | |
| 11407 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11408 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11409 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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|
11410 Pop_Reg_DPR(dst) ); |
| 0 | 11411 ins_pipe( fpu_reg_mem ); |
| 11412 %} | |
| 11413 | |
| 11414 | |
|
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11415 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11416 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11417 match(Set dst (MoveL2D src)); | |
| 11418 effect(DEF dst, USE src); | |
| 11419 | |
| 11420 ins_cost(95); | |
| 11421 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11422 ins_encode %{ |
| 11423 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11424 %} | |
| 0 | 11425 ins_pipe( pipe_slow ); |
| 11426 %} | |
| 11427 | |
|
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11428 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11429 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11430 match(Set dst (MoveL2D src)); | |
| 11431 effect(DEF dst, USE src); | |
| 11432 | |
| 11433 ins_cost(95); | |
| 11434 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11435 ins_encode %{ |
| 11436 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11437 %} | |
| 0 | 11438 ins_pipe( pipe_slow ); |
| 11439 %} | |
| 11440 | |
|
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11441 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11442 predicate(UseSSE>=2); |
| 11443 match(Set dst (MoveL2D src)); | |
| 11444 effect(TEMP dst, USE src, TEMP tmp); | |
| 11445 ins_cost(85); | |
| 11446 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11447 "MOVD $tmp,$src.hi\n\t" | |
| 11448 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11449 ins_encode %{ |
| 11450 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11451 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11452 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11453 %} | |
| 0 | 11454 ins_pipe( pipe_slow ); |
| 11455 %} | |
| 11456 | |
| 11457 | |
| 11458 // ======================================================================= | |
| 11459 // fast clearing of an array | |
| 11460 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
|
7474
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|
11461 predicate(!UseFastStosb); |
| 0 | 11462 match(Set dummy (ClearArray cnt base)); |
| 11463 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
|
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|
11464 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
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|
11465 "SHL ECX,1\t# Convert doublewords to words\n\t" |
| 0 | 11466 "REP STOS\t# store EAX into [EDI++] while ECX--" %} |
|
7474
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|
11467 ins_encode %{ |
|
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|
11468 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
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|
11469 %} |
|
00af3a3a8df4
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|
11470 ins_pipe( pipe_slow ); |
|
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|
11471 %} |
|
00af3a3a8df4
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|
11472 |
|
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|
11473 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ |
|
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|
11474 predicate(UseFastStosb); |
|
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|
11475 match(Set dummy (ClearArray cnt base)); |
|
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11476 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
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|
11477 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
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|
11478 "SHL ECX,3\t# Convert doublewords to bytes\n\t" |
|
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|
11479 "REP STOSB\t# store EAX into [EDI++] while ECX--" %} |
|
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|
11480 ins_encode %{ |
|
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|
11481 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
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|
11482 %} |
| 0 | 11483 ins_pipe( pipe_slow ); |
| 11484 %} | |
| 11485 | |
| 2262 | 11486 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
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11487 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
986
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|
11488 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11489 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11490 | |
| 11491 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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11492 ins_encode %{ |
|
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11493 __ string_compare($str1$$Register, $str2$$Register, |
|
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11494 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11495 $tmp1$$XMMRegister); |
|
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|
11496 %} |
| 681 | 11497 ins_pipe( pipe_slow ); |
| 11498 %} | |
| 11499 | |
| 11500 // fast string equals | |
|
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11501 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
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11502 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
986
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11503 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
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11504 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
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11505 |
|
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11506 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
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11507 ins_encode %{ |
|
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|
11508 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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11509 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
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11510 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
11511 %} |
|
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|
11512 ins_pipe( pipe_slow ); |
|
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|
11513 %} |
|
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|
11514 |
|
2320
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|
11515 // fast search of substring with known size. |
|
41d4973cf100
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changeset
|
11516 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
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11517 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
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changeset
|
11518 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
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|
11519 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
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|
11520 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
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|
11521 |
|
41d4973cf100
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|
11522 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
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changeset
|
11523 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11524 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11525 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11526 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11527 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11528 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11529 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11530 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11531 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11532 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11533 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11534 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11535 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11536 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11537 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11538 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11539 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11540 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11541 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11542 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11543 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11544 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11545 predicate(UseSSE42Intrinsics); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11546 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11547 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11548 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11549 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11550 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11551 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11552 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11553 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11554 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11555 %} |
| 0 | 11556 ins_pipe( pipe_slow ); |
| 11557 %} | |
| 11558 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11559 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11560 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11561 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11562 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11563 match(Set result (AryEq ary1 ary2)); |
| 681 | 11564 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11565 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11566 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11567 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11568 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11569 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11570 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11571 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11572 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11573 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11574 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11575 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11576 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11577 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11578 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11579 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11580 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11581 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11582 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11583 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11584 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11585 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11586 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11587 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11588 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11589 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11590 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11591 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11592 |
| 0 | 11593 //----------Control Flow Instructions------------------------------------------ |
| 11594 // Signed compare Instructions | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11595 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11596 match(Set cr (CmpI op1 op2)); |
| 11597 effect( DEF cr, USE op1, USE op2 ); | |
| 11598 format %{ "CMP $op1,$op2" %} | |
| 11599 opcode(0x3B); /* Opcode 3B /r */ | |
| 11600 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11601 ins_pipe( ialu_cr_reg_reg ); | |
| 11602 %} | |
| 11603 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11604 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11605 match(Set cr (CmpI op1 op2)); |
| 11606 effect( DEF cr, USE op1 ); | |
| 11607 format %{ "CMP $op1,$op2" %} | |
| 11608 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11609 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11610 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11611 ins_pipe( ialu_cr_reg_imm ); | |
| 11612 %} | |
| 11613 | |
| 11614 // Cisc-spilled version of cmpI_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11615 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11616 match(Set cr (CmpI op1 (LoadI op2))); |
| 11617 | |
| 11618 format %{ "CMP $op1,$op2" %} | |
| 11619 ins_cost(500); | |
| 11620 opcode(0x3B); /* Opcode 3B /r */ | |
| 11621 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11622 ins_pipe( ialu_cr_reg_mem ); | |
| 11623 %} | |
| 11624 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11625 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11626 match(Set cr (CmpI src zero)); |
| 11627 effect( DEF cr, USE src ); | |
| 11628 | |
| 11629 format %{ "TEST $src,$src" %} | |
| 11630 opcode(0x85); | |
| 11631 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11632 ins_pipe( ialu_cr_reg_imm ); | |
| 11633 %} | |
| 11634 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11635 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11636 match(Set cr (CmpI (AndI src con) zero)); |
| 11637 | |
| 11638 format %{ "TEST $src,$con" %} | |
| 11639 opcode(0xF7,0x00); | |
| 11640 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11641 ins_pipe( ialu_cr_reg_imm ); | |
| 11642 %} | |
| 11643 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11644 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11645 match(Set cr (CmpI (AndI src mem) zero)); |
| 11646 | |
| 11647 format %{ "TEST $src,$mem" %} | |
| 11648 opcode(0x85); | |
| 11649 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11650 ins_pipe( ialu_cr_reg_mem ); | |
| 11651 %} | |
| 11652 | |
| 11653 // Unsigned compare Instructions; really, same as signed except they | |
| 11654 // produce an eFlagsRegU instead of eFlagsReg. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11655 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11656 match(Set cr (CmpU op1 op2)); |
| 11657 | |
| 11658 format %{ "CMPu $op1,$op2" %} | |
| 11659 opcode(0x3B); /* Opcode 3B /r */ | |
| 11660 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11661 ins_pipe( ialu_cr_reg_reg ); | |
| 11662 %} | |
| 11663 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11664 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11665 match(Set cr (CmpU op1 op2)); |
| 11666 | |
| 11667 format %{ "CMPu $op1,$op2" %} | |
| 11668 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11669 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11670 ins_pipe( ialu_cr_reg_imm ); | |
| 11671 %} | |
| 11672 | |
| 11673 // // Cisc-spilled version of cmpU_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11674 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11675 match(Set cr (CmpU op1 (LoadI op2))); |
| 11676 | |
| 11677 format %{ "CMPu $op1,$op2" %} | |
| 11678 ins_cost(500); | |
| 11679 opcode(0x3B); /* Opcode 3B /r */ | |
| 11680 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11681 ins_pipe( ialu_cr_reg_mem ); | |
| 11682 %} | |
| 11683 | |
| 11684 // // Cisc-spilled version of cmpU_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11685 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11686 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11687 // | |
| 11688 // format %{ "CMPu $op1,$op2" %} | |
| 11689 // ins_cost(500); | |
| 11690 // opcode(0x39); /* Opcode 39 /r */ | |
| 11691 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11692 //%} | |
| 11693 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11694 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11695 match(Set cr (CmpU src zero)); |
| 11696 | |
| 11697 format %{ "TESTu $src,$src" %} | |
| 11698 opcode(0x85); | |
| 11699 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11700 ins_pipe( ialu_cr_reg_imm ); | |
| 11701 %} | |
| 11702 | |
| 11703 // Unsigned pointer compare Instructions | |
| 11704 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11705 match(Set cr (CmpP op1 op2)); | |
| 11706 | |
| 11707 format %{ "CMPu $op1,$op2" %} | |
| 11708 opcode(0x3B); /* Opcode 3B /r */ | |
| 11709 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11710 ins_pipe( ialu_cr_reg_reg ); | |
| 11711 %} | |
| 11712 | |
| 11713 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11714 match(Set cr (CmpP op1 op2)); | |
| 11715 | |
| 11716 format %{ "CMPu $op1,$op2" %} | |
| 11717 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11718 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11719 ins_pipe( ialu_cr_reg_imm ); | |
| 11720 %} | |
| 11721 | |
| 11722 // // Cisc-spilled version of cmpP_eReg | |
| 11723 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11724 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11725 | |
| 11726 format %{ "CMPu $op1,$op2" %} | |
| 11727 ins_cost(500); | |
| 11728 opcode(0x3B); /* Opcode 3B /r */ | |
| 11729 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11730 ins_pipe( ialu_cr_reg_mem ); | |
| 11731 %} | |
| 11732 | |
| 11733 // // Cisc-spilled version of cmpP_eReg | |
| 11734 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11735 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11736 // | |
| 11737 // format %{ "CMPu $op1,$op2" %} | |
| 11738 // ins_cost(500); | |
| 11739 // opcode(0x39); /* Opcode 39 /r */ | |
| 11740 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11741 //%} | |
| 11742 | |
| 11743 // Compare raw pointer (used in out-of-heap check). | |
| 11744 // Only works because non-oop pointers must be raw pointers | |
| 11745 // and raw pointers have no anti-dependencies. | |
| 11746 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
|
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11747 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11748 match(Set cr (CmpP op1 (LoadP op2))); |
| 11749 | |
| 11750 format %{ "CMPu $op1,$op2" %} | |
| 11751 opcode(0x3B); /* Opcode 3B /r */ | |
| 11752 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11753 ins_pipe( ialu_cr_reg_mem ); | |
| 11754 %} | |
| 11755 | |
| 11756 // | |
| 11757 // This will generate a signed flags result. This should be ok | |
| 11758 // since any compare to a zero should be eq/neq. | |
| 11759 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11760 match(Set cr (CmpP src zero)); | |
| 11761 | |
| 11762 format %{ "TEST $src,$src" %} | |
| 11763 opcode(0x85); | |
| 11764 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11765 ins_pipe( ialu_cr_reg_imm ); | |
| 11766 %} | |
| 11767 | |
| 11768 // Cisc-spilled version of testP_reg | |
| 11769 // This will generate a signed flags result. This should be ok | |
| 11770 // since any compare to a zero should be eq/neq. | |
| 11771 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11772 match(Set cr (CmpP (LoadP op) zero)); | |
| 11773 | |
| 11774 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11775 ins_cost(500); | |
| 11776 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11777 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11778 ins_pipe( ialu_cr_reg_imm ); | |
| 11779 %} | |
| 11780 | |
| 11781 // Yanked all unsigned pointer compare operations. | |
| 11782 // Pointer compares are done with CmpP which is already unsigned. | |
| 11783 | |
| 11784 //----------Max and Min-------------------------------------------------------- | |
| 11785 // Min Instructions | |
| 11786 //// | |
| 11787 // *** Min and Max using the conditional move are slower than the | |
| 11788 // *** branch version on a Pentium III. | |
| 11789 // // Conditional move for min | |
|
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11790 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11791 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11792 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11793 // opcode(0x4C,0x0F); | |
| 11794 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11795 // ins_pipe( pipe_cmov_reg ); | |
| 11796 //%} | |
| 11797 // | |
| 11798 //// Min Register with Register (P6 version) | |
|
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11799 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11800 // predicate(VM_Version::supports_cmov() ); |
| 11801 // match(Set op2 (MinI op1 op2)); | |
| 11802 // ins_cost(200); | |
| 11803 // expand %{ | |
| 11804 // eFlagsReg cr; | |
| 11805 // compI_eReg(cr,op1,op2); | |
| 11806 // cmovI_reg_lt(op2,op1,cr); | |
| 11807 // %} | |
| 11808 //%} | |
| 11809 | |
| 11810 // Min Register with Register (generic version) | |
|
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11811 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11812 match(Set dst (MinI dst src)); |
| 11813 effect(KILL flags); | |
| 11814 ins_cost(300); | |
| 11815 | |
| 11816 format %{ "MIN $dst,$src" %} | |
| 11817 opcode(0xCC); | |
| 11818 ins_encode( min_enc(dst,src) ); | |
| 11819 ins_pipe( pipe_slow ); | |
| 11820 %} | |
| 11821 | |
| 11822 // Max Register with Register | |
| 11823 // *** Min and Max using the conditional move are slower than the | |
| 11824 // *** branch version on a Pentium III. | |
| 11825 // // Conditional move for max | |
|
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11826 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11827 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11828 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11829 // opcode(0x4F,0x0F); | |
| 11830 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11831 // ins_pipe( pipe_cmov_reg ); | |
| 11832 //%} | |
| 11833 // | |
| 11834 // // Max Register with Register (P6 version) | |
|
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11835 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11836 // predicate(VM_Version::supports_cmov() ); |
| 11837 // match(Set op2 (MaxI op1 op2)); | |
| 11838 // ins_cost(200); | |
| 11839 // expand %{ | |
| 11840 // eFlagsReg cr; | |
| 11841 // compI_eReg(cr,op1,op2); | |
| 11842 // cmovI_reg_gt(op2,op1,cr); | |
| 11843 // %} | |
| 11844 //%} | |
| 11845 | |
| 11846 // Max Register with Register (generic version) | |
|
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11847 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11848 match(Set dst (MaxI dst src)); |
| 11849 effect(KILL flags); | |
| 11850 ins_cost(300); | |
| 11851 | |
| 11852 format %{ "MAX $dst,$src" %} | |
| 11853 opcode(0xCC); | |
| 11854 ins_encode( max_enc(dst,src) ); | |
| 11855 ins_pipe( pipe_slow ); | |
| 11856 %} | |
| 11857 | |
| 11858 // ============================================================================ | |
| 3345 | 11859 // Counted Loop limit node which represents exact final iterator value. |
| 11860 // Note: the resulting value should fit into integer range since | |
| 11861 // counted loops have limit check on overflow. | |
| 11862 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11863 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11864 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11865 ins_cost(300); | |
| 11866 | |
| 11867 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11868 ins_encode %{ | |
| 11869 int strd = (int)$stride$$constant; | |
| 11870 assert(strd != 1 && strd != -1, "sanity"); | |
| 11871 int m1 = (strd > 0) ? 1 : -1; | |
| 11872 // Convert limit to long (EAX:EDX) | |
| 11873 __ cdql(); | |
| 11874 // Convert init to long (init:tmp) | |
| 11875 __ movl($tmp$$Register, $init$$Register); | |
| 11876 __ sarl($tmp$$Register, 31); | |
| 11877 // $limit - $init | |
| 11878 __ subl($limit$$Register, $init$$Register); | |
| 11879 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11880 // + ($stride - 1) | |
| 11881 if (strd > 0) { | |
| 11882 __ addl($limit$$Register, (strd - 1)); | |
| 11883 __ adcl($limit_hi$$Register, 0); | |
| 11884 __ movl($tmp$$Register, strd); | |
| 11885 } else { | |
| 11886 __ addl($limit$$Register, (strd + 1)); | |
| 11887 __ adcl($limit_hi$$Register, -1); | |
| 11888 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11889 __ movl($tmp$$Register, -strd); | |
| 11890 } | |
| 11891 // signed devision: (EAX:EDX) / pos_stride | |
| 11892 __ idivl($tmp$$Register); | |
| 11893 if (strd < 0) { | |
| 11894 // restore sign | |
| 11895 __ negl($tmp$$Register); | |
| 11896 } | |
| 11897 // (EAX) * stride | |
| 11898 __ mull($tmp$$Register); | |
| 11899 // + init (ignore upper bits) | |
| 11900 __ addl($limit$$Register, $init$$Register); | |
| 11901 %} | |
| 11902 ins_pipe( pipe_slow ); | |
| 11903 %} | |
| 11904 | |
| 11905 // ============================================================================ | |
| 0 | 11906 // Branch Instructions |
| 11907 // Jump Table | |
|
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11908 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11909 match(Jump switch_val); |
| 11910 ins_cost(350); | |
| 2008 | 11911 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11912 ins_encode %{ | |
| 0 | 11913 // Jump to Address(table_base + switch_reg) |
| 11914 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11915 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 11916 %} |
| 11917 ins_pipe(pipe_jmp); | |
| 11918 %} | |
| 11919 | |
| 11920 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11921 instruct jmpDir(label labl) %{ | |
| 11922 match(Goto); | |
| 11923 effect(USE labl); | |
| 11924 | |
| 11925 ins_cost(300); | |
| 11926 format %{ "JMP $labl" %} | |
| 11927 size(5); | |
| 3851 | 11928 ins_encode %{ |
| 11929 Label* L = $labl$$label; | |
| 11930 __ jmp(*L, false); // Always long jump | |
| 11931 %} | |
| 0 | 11932 ins_pipe( pipe_jmp ); |
| 11933 %} | |
| 11934 | |
| 11935 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11936 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11937 match(If cop cr); | |
| 11938 effect(USE labl); | |
| 11939 | |
| 11940 ins_cost(300); | |
| 11941 format %{ "J$cop $labl" %} | |
| 11942 size(6); | |
| 3851 | 11943 ins_encode %{ |
| 11944 Label* L = $labl$$label; | |
| 11945 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11946 %} | |
| 0 | 11947 ins_pipe( pipe_jcc ); |
| 11948 %} | |
| 11949 | |
| 11950 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11951 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11952 match(CountedLoopEnd cop cr); | |
| 11953 effect(USE labl); | |
| 11954 | |
| 11955 ins_cost(300); | |
| 11956 format %{ "J$cop $labl\t# Loop end" %} | |
| 11957 size(6); | |
| 3851 | 11958 ins_encode %{ |
| 11959 Label* L = $labl$$label; | |
| 11960 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11961 %} | |
| 0 | 11962 ins_pipe( pipe_jcc ); |
| 11963 %} | |
| 11964 | |
| 11965 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11966 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11967 match(CountedLoopEnd cop cmp); | |
| 11968 effect(USE labl); | |
| 11969 | |
| 11970 ins_cost(300); | |
| 11971 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 11972 size(6); | |
| 3851 | 11973 ins_encode %{ |
| 11974 Label* L = $labl$$label; | |
| 11975 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11976 %} | |
| 0 | 11977 ins_pipe( pipe_jcc ); |
| 11978 %} | |
| 11979 | |
|
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11980 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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11981 match(CountedLoopEnd cop cmp); |
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11982 effect(USE labl); |
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11983 |
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11984 ins_cost(200); |
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11985 format %{ "J$cop,u $labl\t# Loop end" %} |
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11986 size(6); |
| 3851 | 11987 ins_encode %{ |
| 11988 Label* L = $labl$$label; | |
| 11989 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11990 %} | |
|
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11991 ins_pipe( pipe_jcc ); |
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11992 %} |
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11993 |
| 0 | 11994 // Jump Direct Conditional - using unsigned comparison |
| 11995 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11996 match(If cop cmp); | |
| 11997 effect(USE labl); | |
| 11998 | |
| 11999 ins_cost(300); | |
| 12000 format %{ "J$cop,u $labl" %} | |
| 12001 size(6); | |
| 3851 | 12002 ins_encode %{ |
| 12003 Label* L = $labl$$label; | |
| 12004 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12005 %} | |
|
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12006 ins_pipe(pipe_jcc); |
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12007 %} |
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12008 |
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12009 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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12010 match(If cop cmp); |
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12011 effect(USE labl); |
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12012 |
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12013 ins_cost(200); |
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12014 format %{ "J$cop,u $labl" %} |
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12015 size(6); |
| 3851 | 12016 ins_encode %{ |
| 12017 Label* L = $labl$$label; | |
| 12018 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12019 %} | |
|
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12020 ins_pipe(pipe_jcc); |
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12021 %} |
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12022 |
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12023 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
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12024 match(If cop cmp); |
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12025 effect(USE labl); |
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12026 |
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12027 ins_cost(200); |
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12028 format %{ $$template |
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12029 if ($cop$$cmpcode == Assembler::notEqual) { |
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12030 $$emit$$"JP,u $labl\n\t" |
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12031 $$emit$$"J$cop,u $labl" |
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12032 } else { |
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12033 $$emit$$"JP,u done\n\t" |
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12034 $$emit$$"J$cop,u $labl\n\t" |
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12035 $$emit$$"done:" |
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12036 } |
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12037 %} |
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12038 ins_encode %{ |
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12039 Label* l = $labl$$label; |
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12040 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12041 __ jcc(Assembler::parity, *l, false); |
| 12042 __ jcc(Assembler::notEqual, *l, false); | |
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12043 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12044 Label done; |
| 12045 __ jccb(Assembler::parity, done); | |
| 12046 __ jcc(Assembler::equal, *l, false); | |
| 12047 __ bind(done); | |
|
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12048 } else { |
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12049 ShouldNotReachHere(); |
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12050 } |
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|
12051 %} |
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|
12052 ins_pipe(pipe_jcc); |
| 0 | 12053 %} |
| 12054 | |
| 12055 // ============================================================================ | |
| 12056 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12057 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12058 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12059 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12060 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12061 match(Set result (PartialSubtypeCheck sub super)); | |
| 12062 effect( KILL rcx, KILL cr ); | |
| 12063 | |
| 12064 ins_cost(1100); // slightly larger than the next version | |
|
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|
12065 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
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|
12066 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
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|
12067 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12068 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12069 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12070 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12071 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12072 "miss:\t" %} | |
| 12073 | |
| 12074 opcode(0x1); // Force a XOR of EDI | |
| 12075 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12076 ins_pipe( pipe_slow ); | |
| 12077 %} | |
| 12078 | |
| 12079 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12080 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12081 effect( KILL rcx, KILL result ); | |
| 12082 | |
| 12083 ins_cost(1000); | |
|
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|
12084 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
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|
12085 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
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|
12086 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12087 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12088 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12089 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12090 "miss:\t" %} | |
| 12091 | |
| 12092 opcode(0x0); // No need to XOR EDI | |
| 12093 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12094 ins_pipe( pipe_slow ); | |
| 12095 %} | |
| 12096 | |
| 12097 // ============================================================================ | |
| 12098 // Branch Instructions -- short offset versions | |
| 12099 // | |
| 12100 // These instructions are used to replace jumps of a long offset (the default | |
| 12101 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12102 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12103 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12104 // method in the MachNode which can be used to do in-place replacement of the | |
| 12105 // long variant with the shorter variant. The compiler will determine if a | |
| 12106 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12107 // specific code section of the file. | |
| 12108 | |
| 12109 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12110 instruct jmpDir_short(label labl) %{ | |
| 12111 match(Goto); | |
| 12112 effect(USE labl); | |
| 12113 | |
| 12114 ins_cost(300); | |
| 12115 format %{ "JMP,s $labl" %} | |
| 12116 size(2); | |
| 3851 | 12117 ins_encode %{ |
| 12118 Label* L = $labl$$label; | |
| 12119 __ jmpb(*L); | |
| 12120 %} | |
| 0 | 12121 ins_pipe( pipe_jmp ); |
| 12122 ins_short_branch(1); | |
| 12123 %} | |
| 12124 | |
| 12125 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12126 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12127 match(If cop cr); | |
| 12128 effect(USE labl); | |
| 12129 | |
| 12130 ins_cost(300); | |
| 12131 format %{ "J$cop,s $labl" %} | |
| 12132 size(2); | |
| 3851 | 12133 ins_encode %{ |
| 12134 Label* L = $labl$$label; | |
| 12135 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12136 %} | |
| 0 | 12137 ins_pipe( pipe_jcc ); |
| 12138 ins_short_branch(1); | |
| 12139 %} | |
| 12140 | |
| 12141 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12142 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12143 match(CountedLoopEnd cop cr); | |
| 12144 effect(USE labl); | |
| 12145 | |
| 12146 ins_cost(300); | |
|
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|
12147 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12148 size(2); |
| 3851 | 12149 ins_encode %{ |
| 12150 Label* L = $labl$$label; | |
| 12151 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12152 %} | |
| 0 | 12153 ins_pipe( pipe_jcc ); |
| 12154 ins_short_branch(1); | |
| 12155 %} | |
| 12156 | |
| 12157 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12158 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12159 match(CountedLoopEnd cop cmp); | |
| 12160 effect(USE labl); | |
| 12161 | |
| 12162 ins_cost(300); | |
|
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|
12163 format %{ "J$cop,us $labl\t# Loop end" %} |
|
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12164 size(2); |
| 3851 | 12165 ins_encode %{ |
| 12166 Label* L = $labl$$label; | |
| 12167 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12168 %} | |
|
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|
12169 ins_pipe( pipe_jcc ); |
|
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|
12170 ins_short_branch(1); |
|
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|
12171 %} |
|
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|
12172 |
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|
12173 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12174 match(CountedLoopEnd cop cmp); |
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|
12175 effect(USE labl); |
|
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|
12176 |
|
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|
12177 ins_cost(300); |
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|
12178 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12179 size(2); |
| 3851 | 12180 ins_encode %{ |
| 12181 Label* L = $labl$$label; | |
| 12182 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12183 %} | |
| 0 | 12184 ins_pipe( pipe_jcc ); |
| 12185 ins_short_branch(1); | |
| 12186 %} | |
| 12187 | |
| 12188 // Jump Direct Conditional - using unsigned comparison | |
| 12189 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12190 match(If cop cmp); | |
| 12191 effect(USE labl); | |
| 12192 | |
| 12193 ins_cost(300); | |
| 12194 format %{ "J$cop,us $labl" %} | |
| 12195 size(2); | |
| 3851 | 12196 ins_encode %{ |
| 12197 Label* L = $labl$$label; | |
| 12198 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12199 %} | |
| 0 | 12200 ins_pipe( pipe_jcc ); |
| 12201 ins_short_branch(1); | |
| 12202 %} | |
| 12203 | |
|
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12204 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12205 match(If cop cmp); |
|
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|
12206 effect(USE labl); |
|
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|
12207 |
|
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|
12208 ins_cost(300); |
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|
12209 format %{ "J$cop,us $labl" %} |
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|
12210 size(2); |
| 3851 | 12211 ins_encode %{ |
| 12212 Label* L = $labl$$label; | |
| 12213 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12214 %} | |
|
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|
12215 ins_pipe( pipe_jcc ); |
|
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|
12216 ins_short_branch(1); |
|
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|
12217 %} |
|
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|
12218 |
|
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|
12219 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12220 match(If cop cmp); |
|
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|
12221 effect(USE labl); |
|
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|
12222 |
|
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|
12223 ins_cost(300); |
|
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|
12224 format %{ $$template |
|
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|
12225 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12226 $$emit$$"JP,u,s $labl\n\t" |
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12227 $$emit$$"J$cop,u,s $labl" |
|
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|
12228 } else { |
|
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|
12229 $$emit$$"JP,u,s done\n\t" |
|
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|
12230 $$emit$$"J$cop,u,s $labl\n\t" |
|
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|
12231 $$emit$$"done:" |
|
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|
12232 } |
|
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|
12233 %} |
|
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|
12234 size(4); |
|
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|
12235 ins_encode %{ |
|
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|
12236 Label* l = $labl$$label; |
|
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|
12237 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12238 __ jccb(Assembler::parity, *l); |
| 12239 __ jccb(Assembler::notEqual, *l); | |
|
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12240 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12241 Label done; |
| 12242 __ jccb(Assembler::parity, done); | |
| 12243 __ jccb(Assembler::equal, *l); | |
| 12244 __ bind(done); | |
|
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|
12245 } else { |
| 3851 | 12246 ShouldNotReachHere(); |
| 12247 } | |
|
415
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|
12248 %} |
|
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|
12249 ins_pipe(pipe_jcc); |
|
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|
12250 ins_short_branch(1); |
|
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|
12251 %} |
|
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|
12252 |
| 0 | 12253 // ============================================================================ |
| 12254 // Long Compare | |
| 12255 // | |
| 12256 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12257 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12258 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12259 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12260 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12261 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12262 // NE test is negated from that. | |
| 12263 | |
| 12264 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12265 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12266 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12267 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12268 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12269 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12270 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12271 // both forms beat the trinary form of long-compare and both are very useful | |
| 12272 // on Intel which has so few registers. | |
| 12273 | |
| 12274 // Manifest a CmpL result in an integer register. Very painful. | |
| 12275 // This is the test to avoid. | |
| 12276 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12277 match(Set dst (CmpL3 src1 src2)); | |
| 12278 effect( KILL flags ); | |
| 12279 ins_cost(1000); | |
| 12280 format %{ "XOR $dst,$dst\n\t" | |
| 12281 "CMP $src1.hi,$src2.hi\n\t" | |
| 12282 "JLT,s m_one\n\t" | |
| 12283 "JGT,s p_one\n\t" | |
| 12284 "CMP $src1.lo,$src2.lo\n\t" | |
| 12285 "JB,s m_one\n\t" | |
| 12286 "JEQ,s done\n" | |
| 12287 "p_one:\tINC $dst\n\t" | |
| 12288 "JMP,s done\n" | |
| 12289 "m_one:\tDEC $dst\n" | |
| 12290 "done:" %} | |
| 12291 ins_encode %{ | |
| 12292 Label p_one, m_one, done; | |
| 304 | 12293 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12294 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12295 __ jccb(Assembler::less, m_one); | |
| 12296 __ jccb(Assembler::greater, p_one); | |
| 12297 __ cmpl($src1$$Register, $src2$$Register); | |
| 12298 __ jccb(Assembler::below, m_one); | |
| 12299 __ jccb(Assembler::equal, done); | |
| 12300 __ bind(p_one); | |
| 304 | 12301 __ incrementl($dst$$Register); |
| 0 | 12302 __ jmpb(done); |
| 12303 __ bind(m_one); | |
| 304 | 12304 __ decrementl($dst$$Register); |
| 0 | 12305 __ bind(done); |
| 12306 %} | |
| 12307 ins_pipe( pipe_slow ); | |
| 12308 %} | |
| 12309 | |
| 12310 //====== | |
| 12311 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12312 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12313 // NOT GOOD FOR EQ/NE tests. | |
| 12314 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12315 match( Set flags (CmpL src zero )); | |
| 12316 ins_cost(100); | |
| 12317 format %{ "TEST $src.hi,$src.hi" %} | |
| 12318 opcode(0x85); | |
| 12319 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12320 ins_pipe( ialu_cr_reg_reg ); | |
| 12321 %} | |
| 12322 | |
| 12323 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12324 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12325 // NOT GOOD FOR EQ/NE tests. | |
|
6179
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|
12326 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12327 match( Set flags (CmpL src1 src2 )); |
| 12328 effect( TEMP tmp ); | |
| 12329 ins_cost(300); | |
| 12330 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12331 "MOV $tmp,$src1.hi\n\t" | |
| 12332 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12333 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12334 ins_pipe( ialu_cr_reg_reg ); | |
| 12335 %} | |
| 12336 | |
| 12337 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12338 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12339 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12340 match(If cmp flags); | |
| 12341 effect(USE labl); | |
| 12342 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12343 expand %{ | |
| 12344 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12345 %} | |
| 12346 %} | |
| 12347 | |
| 12348 // Compare 2 longs and CMOVE longs. | |
| 12349 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12350 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12351 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12352 ins_cost(400); | |
| 12353 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12354 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12355 opcode(0x0F,0x40); | |
| 12356 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12357 ins_pipe( pipe_cmov_reg_long ); | |
| 12358 %} | |
| 12359 | |
| 12360 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12361 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12362 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12363 ins_cost(500); | |
| 12364 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12365 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12366 opcode(0x0F,0x40); | |
| 12367 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12368 ins_pipe( pipe_cmov_reg_long ); | |
| 12369 %} | |
| 12370 | |
| 12371 // Compare 2 longs and CMOVE ints. | |
|
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12372 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12373 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12374 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12375 ins_cost(200); | |
| 12376 format %{ "CMOV$cmp $dst,$src" %} | |
| 12377 opcode(0x0F,0x40); | |
| 12378 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12379 ins_pipe( pipe_cmov_reg ); | |
| 12380 %} | |
| 12381 | |
|
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12382 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12383 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12384 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12385 ins_cost(250); | |
| 12386 format %{ "CMOV$cmp $dst,$src" %} | |
| 12387 opcode(0x0F,0x40); | |
| 12388 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12389 ins_pipe( pipe_cmov_mem ); | |
| 12390 %} | |
| 12391 | |
| 12392 // Compare 2 longs and CMOVE ints. | |
| 12393 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12394 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12395 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12396 ins_cost(200); | |
| 12397 format %{ "CMOV$cmp $dst,$src" %} | |
| 12398 opcode(0x0F,0x40); | |
| 12399 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12400 ins_pipe( pipe_cmov_reg ); | |
| 12401 %} | |
| 12402 | |
| 12403 // Compare 2 longs and CMOVE doubles | |
|
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12404 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12405 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12406 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12407 ins_cost(200); | |
| 12408 expand %{ | |
|
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12409 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12410 %} |
| 12411 %} | |
| 12412 | |
| 12413 // Compare 2 longs and CMOVE doubles | |
|
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12414 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12415 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12416 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12417 ins_cost(200); | |
| 12418 expand %{ | |
|
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12419 fcmovD_regS(cmp,flags,dst,src); |
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12420 %} |
|
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12421 %} |
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12422 |
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12423 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
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12424 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
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12425 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12426 ins_cost(200); |
|
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12427 expand %{ |
|
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12428 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12429 %} |
| 12430 %} | |
| 12431 | |
| 12432 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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12433 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12434 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12435 ins_cost(200); | |
| 12436 expand %{ | |
| 12437 fcmovF_regS(cmp,flags,dst,src); | |
| 12438 %} | |
| 12439 %} | |
| 12440 | |
| 12441 //====== | |
| 12442 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
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12443 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12444 match( Set flags (CmpL src zero )); |
| 12445 effect(TEMP tmp); | |
| 12446 ins_cost(200); | |
| 12447 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12448 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12449 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12450 ins_pipe( ialu_reg_reg_long ); | |
| 12451 %} | |
| 12452 | |
| 12453 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12454 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12455 match( Set flags (CmpL src1 src2 )); | |
| 12456 ins_cost(200+300); | |
| 12457 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12458 "JNE,s skip\n\t" | |
| 12459 "CMP $src1.hi,$src2.hi\n\t" | |
| 12460 "skip:\t" %} | |
| 12461 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12462 ins_pipe( ialu_cr_reg_reg ); | |
| 12463 %} | |
| 12464 | |
| 12465 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12466 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12467 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12468 match(If cmp flags); | |
| 12469 effect(USE labl); | |
| 12470 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12471 expand %{ | |
| 12472 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12473 %} | |
| 12474 %} | |
| 12475 | |
| 12476 // Compare 2 longs and CMOVE longs. | |
| 12477 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12478 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12479 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12480 ins_cost(400); | |
| 12481 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12482 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12483 opcode(0x0F,0x40); | |
| 12484 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12485 ins_pipe( pipe_cmov_reg_long ); | |
| 12486 %} | |
| 12487 | |
| 12488 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12489 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12490 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12491 ins_cost(500); | |
| 12492 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12493 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12494 opcode(0x0F,0x40); | |
| 12495 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12496 ins_pipe( pipe_cmov_reg_long ); | |
| 12497 %} | |
| 12498 | |
| 12499 // Compare 2 longs and CMOVE ints. | |
|
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12500 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12501 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12502 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12503 ins_cost(200); | |
| 12504 format %{ "CMOV$cmp $dst,$src" %} | |
| 12505 opcode(0x0F,0x40); | |
| 12506 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12507 ins_pipe( pipe_cmov_reg ); | |
| 12508 %} | |
| 12509 | |
|
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12510 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12511 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12512 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12513 ins_cost(250); | |
| 12514 format %{ "CMOV$cmp $dst,$src" %} | |
| 12515 opcode(0x0F,0x40); | |
| 12516 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12517 ins_pipe( pipe_cmov_mem ); | |
| 12518 %} | |
| 12519 | |
| 12520 // Compare 2 longs and CMOVE ints. | |
| 12521 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12522 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12523 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12524 ins_cost(200); | |
| 12525 format %{ "CMOV$cmp $dst,$src" %} | |
| 12526 opcode(0x0F,0x40); | |
| 12527 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12528 ins_pipe( pipe_cmov_reg ); | |
| 12529 %} | |
| 12530 | |
| 12531 // Compare 2 longs and CMOVE doubles | |
|
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12532 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12533 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12534 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12535 ins_cost(200); | |
| 12536 expand %{ | |
|
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12537 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12538 %} |
| 12539 %} | |
| 12540 | |
| 12541 // Compare 2 longs and CMOVE doubles | |
|
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12542 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12543 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12544 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12545 ins_cost(200); | |
| 12546 expand %{ | |
|
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12547 fcmovD_regS(cmp,flags,dst,src); |
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12548 %} |
|
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12549 %} |
|
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12550 |
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12551 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12552 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
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12553 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12554 ins_cost(200); |
|
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12555 expand %{ |
|
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12556 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12557 %} |
| 12558 %} | |
| 12559 | |
| 12560 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12561 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12562 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12563 ins_cost(200); | |
| 12564 expand %{ | |
| 12565 fcmovF_regS(cmp,flags,dst,src); | |
| 12566 %} | |
| 12567 %} | |
| 12568 | |
| 12569 //====== | |
| 12570 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12571 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
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12572 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12573 match( Set flags (CmpL src zero )); |
| 12574 effect( TEMP tmp ); | |
| 12575 ins_cost(300); | |
| 12576 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12577 "CMP $tmp,$src.lo\n\t" | |
| 12578 "SBB $tmp,$src.hi\n\t" %} | |
| 12579 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12580 ins_pipe( ialu_reg_reg_long ); | |
| 12581 %} | |
| 12582 | |
| 12583 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12584 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12585 // requires a commuted test to get the same result. | |
|
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12586 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12587 match( Set flags (CmpL src1 src2 )); |
| 12588 effect( TEMP tmp ); | |
| 12589 ins_cost(300); | |
| 12590 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12591 "MOV $tmp,$src2.hi\n\t" | |
| 12592 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12593 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12594 ins_pipe( ialu_cr_reg_reg ); | |
| 12595 %} | |
| 12596 | |
| 12597 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12598 // Just a wrapper for a normal branch, plus the predicate test | |
| 12599 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12600 match(If cmp flags); | |
| 12601 effect(USE labl); | |
| 12602 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12603 ins_cost(300); | |
| 12604 expand %{ | |
| 12605 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12606 %} | |
| 12607 %} | |
| 12608 | |
| 12609 // Compare 2 longs and CMOVE longs. | |
| 12610 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12611 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12612 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12613 ins_cost(400); | |
| 12614 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12615 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12616 opcode(0x0F,0x40); | |
| 12617 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12618 ins_pipe( pipe_cmov_reg_long ); | |
| 12619 %} | |
| 12620 | |
| 12621 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12622 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12623 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12624 ins_cost(500); | |
| 12625 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12626 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12627 opcode(0x0F,0x40); | |
| 12628 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12629 ins_pipe( pipe_cmov_reg_long ); | |
| 12630 %} | |
| 12631 | |
| 12632 // Compare 2 longs and CMOVE ints. | |
|
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12633 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12634 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12635 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12636 ins_cost(200); | |
| 12637 format %{ "CMOV$cmp $dst,$src" %} | |
| 12638 opcode(0x0F,0x40); | |
| 12639 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12640 ins_pipe( pipe_cmov_reg ); | |
| 12641 %} | |
| 12642 | |
|
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12643 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12644 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12645 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12646 ins_cost(250); | |
| 12647 format %{ "CMOV$cmp $dst,$src" %} | |
| 12648 opcode(0x0F,0x40); | |
| 12649 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12650 ins_pipe( pipe_cmov_mem ); | |
| 12651 %} | |
| 12652 | |
| 12653 // Compare 2 longs and CMOVE ptrs. | |
| 12654 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12655 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12656 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12657 ins_cost(200); | |
| 12658 format %{ "CMOV$cmp $dst,$src" %} | |
| 12659 opcode(0x0F,0x40); | |
| 12660 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12661 ins_pipe( pipe_cmov_reg ); | |
| 12662 %} | |
| 12663 | |
| 12664 // Compare 2 longs and CMOVE doubles | |
|
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12665 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12666 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12667 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12668 ins_cost(200); | |
| 12669 expand %{ | |
|
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|
12670 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12671 %} |
| 12672 %} | |
| 12673 | |
| 12674 // Compare 2 longs and CMOVE doubles | |
|
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12675 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12676 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12677 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12678 ins_cost(200); | |
| 12679 expand %{ | |
|
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|
12680 fcmovD_regS(cmp,flags,dst,src); |
|
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|
12681 %} |
|
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|
12682 %} |
|
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|
12683 |
|
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|
12684 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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|
12685 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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|
12686 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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|
12687 ins_cost(200); |
|
65149e74c706
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|
12688 expand %{ |
|
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|
12689 fcmovFPR_regS(cmp,flags,dst,src); |
|
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|
12690 %} |
|
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|
12691 %} |
|
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|
12692 |
| 0 | 12693 |
| 12694 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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|
12695 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12696 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12697 ins_cost(200); | |
| 12698 expand %{ | |
| 12699 fcmovF_regS(cmp,flags,dst,src); | |
| 12700 %} | |
| 12701 %} | |
| 12702 | |
| 12703 | |
| 12704 // ============================================================================ | |
| 12705 // Procedure Call/Return Instructions | |
| 12706 // Call Java Static Instruction | |
| 12707 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12708 // compute_padding() functions will have to be adjusted. | |
| 12709 instruct CallStaticJavaDirect(method meth) %{ | |
| 12710 match(CallStaticJava); | |
|
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|
12711 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 12712 effect(USE meth); |
| 12713 | |
| 12714 ins_cost(300); | |
| 12715 format %{ "CALL,static " %} | |
| 12716 opcode(0xE8); /* E8 cd */ | |
|
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|
12717 ins_encode( pre_call_resets, |
| 0 | 12718 Java_Static_Call( meth ), |
| 12719 call_epilog, | |
| 12720 post_call_FPU ); | |
| 12721 ins_pipe( pipe_slow ); | |
| 12722 ins_alignment(4); | |
| 12723 %} | |
| 12724 | |
|
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|
12725 // Call Java Static Instruction (method handle version) |
|
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|
12726 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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|
12727 // compute_padding() functions will have to be adjusted. |
| 1567 | 12728 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
1137
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|
12729 match(CallStaticJava); |
|
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|
12730 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
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|
12731 effect(USE meth); |
|
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|
12732 // EBP is saved by all callees (for interpreter stack correction). |
|
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|
12733 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
12734 |
|
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|
12735 ins_cost(300); |
|
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|
12736 format %{ "CALL,static/MethodHandle " %} |
|
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|
12737 opcode(0xE8); /* E8 cd */ |
|
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|
12738 ins_encode( pre_call_resets, |
|
1137
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|
12739 preserve_SP, |
|
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|
12740 Java_Static_Call( meth ), |
|
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|
12741 restore_SP, |
|
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|
12742 call_epilog, |
|
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|
12743 post_call_FPU ); |
|
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|
12744 ins_pipe( pipe_slow ); |
|
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|
12745 ins_alignment(4); |
|
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|
12746 %} |
|
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|
12747 |
| 0 | 12748 // Call Java Dynamic Instruction |
| 12749 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12750 // compute_padding() functions will have to be adjusted. | |
| 12751 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12752 match(CallDynamicJava); | |
| 12753 effect(USE meth); | |
| 12754 | |
| 12755 ins_cost(300); | |
| 12756 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12757 "CALL,dynamic" %} | |
| 12758 opcode(0xE8); /* E8 cd */ | |
|
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|
12759 ins_encode( pre_call_resets, |
| 0 | 12760 Java_Dynamic_Call( meth ), |
| 12761 call_epilog, | |
| 12762 post_call_FPU ); | |
| 12763 ins_pipe( pipe_slow ); | |
| 12764 ins_alignment(4); | |
| 12765 %} | |
| 12766 | |
| 12767 // Call Runtime Instruction | |
| 12768 instruct CallRuntimeDirect(method meth) %{ | |
| 12769 match(CallRuntime ); | |
| 12770 effect(USE meth); | |
| 12771 | |
| 12772 ins_cost(300); | |
| 12773 format %{ "CALL,runtime " %} | |
| 12774 opcode(0xE8); /* E8 cd */ | |
| 12775 // Use FFREEs to clear entries in float stack | |
|
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|
12776 ins_encode( pre_call_resets, |
| 0 | 12777 FFree_Float_Stack_All, |
| 12778 Java_To_Runtime( meth ), | |
| 12779 post_call_FPU ); | |
| 12780 ins_pipe( pipe_slow ); | |
| 12781 %} | |
| 12782 | |
| 12783 // Call runtime without safepoint | |
| 12784 instruct CallLeafDirect(method meth) %{ | |
| 12785 match(CallLeaf); | |
| 12786 effect(USE meth); | |
| 12787 | |
| 12788 ins_cost(300); | |
| 12789 format %{ "CALL_LEAF,runtime " %} | |
| 12790 opcode(0xE8); /* E8 cd */ | |
|
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|
12791 ins_encode( pre_call_resets, |
| 0 | 12792 FFree_Float_Stack_All, |
| 12793 Java_To_Runtime( meth ), | |
| 12794 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12795 ins_pipe( pipe_slow ); | |
| 12796 %} | |
| 12797 | |
| 12798 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12799 match(CallLeafNoFP); | |
| 12800 effect(USE meth); | |
| 12801 | |
| 12802 ins_cost(300); | |
| 12803 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12804 opcode(0xE8); /* E8 cd */ | |
| 12805 ins_encode(Java_To_Runtime(meth)); | |
| 12806 ins_pipe( pipe_slow ); | |
| 12807 %} | |
| 12808 | |
| 12809 | |
| 12810 // Return Instruction | |
| 12811 // Remove the return address & jump to it. | |
| 12812 instruct Ret() %{ | |
| 12813 match(Return); | |
| 12814 format %{ "RET" %} | |
| 12815 opcode(0xC3); | |
| 12816 ins_encode(OpcP); | |
| 12817 ins_pipe( pipe_jmp ); | |
| 12818 %} | |
| 12819 | |
| 12820 // Tail Call; Jump from runtime stub to Java code. | |
| 12821 // Also known as an 'interprocedural jump'. | |
| 12822 // Target of jump will eventually return to caller. | |
| 12823 // TailJump below removes the return address. | |
| 12824 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12825 match(TailCall jump_target method_oop ); | |
| 12826 ins_cost(300); | |
| 12827 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12828 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12829 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12830 ins_pipe( pipe_jmp ); | |
| 12831 %} | |
| 12832 | |
| 12833 | |
| 12834 // Tail Jump; remove the return address; jump to target. | |
| 12835 // TailCall above leaves the return address around. | |
| 12836 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 12837 match( TailJump jump_target ex_oop ); | |
| 12838 ins_cost(300); | |
| 12839 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 12840 "JMP $jump_target " %} | |
| 12841 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12842 ins_encode( enc_pop_rdx, | |
| 12843 OpcP, RegOpc(jump_target) ); | |
| 12844 ins_pipe( pipe_jmp ); | |
| 12845 %} | |
| 12846 | |
| 12847 // Create exception oop: created by stack-crawling runtime code. | |
| 12848 // Created exception is now available to this handler, and is setup | |
| 12849 // just prior to jumping to this handler. No code emitted. | |
| 12850 instruct CreateException( eAXRegP ex_oop ) | |
| 12851 %{ | |
| 12852 match(Set ex_oop (CreateEx)); | |
| 12853 | |
| 12854 size(0); | |
| 12855 // use the following format syntax | |
| 12856 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 12857 ins_encode(); | |
| 12858 ins_pipe( empty ); | |
| 12859 %} | |
| 12860 | |
| 12861 | |
| 12862 // Rethrow exception: | |
| 12863 // The exception oop will come in the first argument position. | |
| 12864 // Then JUMP (not call) to the rethrow stub code. | |
| 12865 instruct RethrowException() | |
| 12866 %{ | |
| 12867 match(Rethrow); | |
| 12868 | |
| 12869 // use the following format syntax | |
| 12870 format %{ "JMP rethrow_stub" %} | |
| 12871 ins_encode(enc_rethrow); | |
| 12872 ins_pipe( pipe_jmp ); | |
| 12873 %} | |
| 12874 | |
| 12875 // inlined locking and unlocking | |
| 12876 | |
| 17780 | 12877 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{ |
| 12878 predicate(Compile::current()->use_rtm()); | |
| 12879 match(Set cr (FastLock object box)); | |
| 12880 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); | |
| 12881 ins_cost(300); | |
| 12882 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} | |
| 12883 ins_encode %{ | |
| 12884 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, | |
| 12885 $scr$$Register, $cx1$$Register, $cx2$$Register, | |
| 12886 _counters, _rtm_counters, _stack_rtm_counters, | |
| 12887 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), | |
| 12888 true, ra_->C->profile_rtm()); | |
| 12889 %} | |
| 12890 ins_pipe(pipe_slow); | |
| 12891 %} | |
| 12892 | |
|
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|
12893 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 17780 | 12894 predicate(!Compile::current()->use_rtm()); |
|
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|
12895 match(Set cr (FastLock object box)); |
|
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changeset
|
12896 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 12897 ins_cost(300); |
| 4777 | 12898 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
|
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|
12899 ins_encode %{ |
| 17780 | 12900 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
| 12901 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); | |
|
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|
12902 %} |
|
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changeset
|
12903 ins_pipe(pipe_slow); |
|
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|
12904 %} |
|
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12905 |
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12906 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ |
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12907 match(Set cr (FastUnlock object box)); |
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12908 effect(TEMP tmp, USE_KILL box); |
| 0 | 12909 ins_cost(300); |
| 4777 | 12910 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
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12911 ins_encode %{ |
| 17780 | 12912 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); |
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12913 %} |
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12914 ins_pipe(pipe_slow); |
| 0 | 12915 %} |
| 12916 | |
| 12917 | |
| 12918 | |
| 12919 // ============================================================================ | |
| 12920 // Safepoint Instruction | |
| 12921 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 12922 match(SafePoint); | |
| 12923 effect(KILL cr); | |
| 12924 | |
| 12925 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 12926 // On SPARC that might be acceptable as we can generate the address with | |
| 12927 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 12928 // putting additional pressure on the index-0 in the D$. Because of | |
| 12929 // alignment (just like the situation at hand) the lower indices tend | |
| 12930 // to see more traffic. It'd be better to change the polling address | |
| 12931 // to offset 0 of the last $line in the polling page. | |
| 12932 | |
| 12933 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 12934 ins_cost(125); | |
| 12935 size(6) ; | |
| 12936 ins_encode( Safepoint_Poll() ); | |
| 12937 ins_pipe( ialu_reg_mem ); | |
| 12938 %} | |
| 12939 | |
| 4950 | 12940 |
| 12941 // ============================================================================ | |
| 12942 // This name is KNOWN by the ADLC and cannot be changed. | |
| 12943 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 12944 // for this guy. | |
| 12945 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 12946 match(Set dst (ThreadLocal)); | |
| 12947 effect(DEF dst, KILL cr); | |
| 12948 | |
| 12949 format %{ "MOV $dst, Thread::current()" %} | |
| 12950 ins_encode %{ | |
| 12951 Register dstReg = as_Register($dst$$reg); | |
| 12952 __ get_thread(dstReg); | |
| 12953 %} | |
| 12954 ins_pipe( ialu_reg_fat ); | |
| 12955 %} | |
| 12956 | |
| 12957 | |
| 12958 | |
| 0 | 12959 //----------PEEPHOLE RULES----------------------------------------------------- |
| 12960 // These must follow all instruction definitions as they use the names | |
| 12961 // defined in the instructions definitions. | |
| 12962 // | |
| 605 | 12963 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12964 // |
| 12965 // peepconstraint %{ | |
| 12966 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12967 // [, ...] ); | |
| 12968 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12969 // | |
| 12970 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12971 // // provide an instruction_number.operand_name for each operand that appears | |
| 12972 // // in the replacement instruction's match rule | |
| 12973 // | |
| 12974 // ---------VM FLAGS--------------------------------------------------------- | |
| 12975 // | |
| 12976 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12977 // | |
| 12978 // Each peephole rule is given an identifying number starting with zero and | |
| 12979 // increasing by one in the order seen by the parser. An individual peephole | |
| 12980 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12981 // on the command-line. | |
| 12982 // | |
| 12983 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12984 // | |
| 12985 // Only match adjacent instructions in same basic block | |
| 12986 // Only equality constraints | |
| 12987 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 12988 // Only one replacement instruction | |
| 12989 // | |
| 12990 // ---------EXAMPLE---------------------------------------------------------- | |
| 12991 // | |
| 12992 // // pertinent parts of existing instructions in architecture description | |
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12993 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 12994 // match(Set dst (CopyI src)); |
| 12995 // %} | |
| 12996 // | |
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12997 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 12998 // match(Set dst (AddI dst src)); |
| 12999 // effect(KILL cr); | |
| 13000 // %} | |
| 13001 // | |
| 13002 // // Change (inc mov) to lea | |
| 13003 // peephole %{ | |
| 13004 // // increment preceeded by register-register move | |
| 13005 // peepmatch ( incI_eReg movI ); | |
| 13006 // // require that the destination register of the increment | |
| 13007 // // match the destination register of the move | |
| 13008 // peepconstraint ( 0.dst == 1.dst ); | |
| 13009 // // construct a replacement instruction that sets | |
| 13010 // // the destination to ( move's source register + one ) | |
| 13011 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13012 // %} | |
| 13013 // | |
| 13014 // Implementation no longer uses movX instructions since | |
| 13015 // machine-independent system no longer uses CopyX nodes. | |
| 13016 // | |
| 13017 // peephole %{ | |
| 13018 // peepmatch ( incI_eReg movI ); | |
| 13019 // peepconstraint ( 0.dst == 1.dst ); | |
| 13020 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13021 // %} | |
| 13022 // | |
| 13023 // peephole %{ | |
| 13024 // peepmatch ( decI_eReg movI ); | |
| 13025 // peepconstraint ( 0.dst == 1.dst ); | |
| 13026 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13027 // %} | |
| 13028 // | |
| 13029 // peephole %{ | |
| 13030 // peepmatch ( addI_eReg_imm movI ); | |
| 13031 // peepconstraint ( 0.dst == 1.dst ); | |
| 13032 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13033 // %} | |
| 13034 // | |
| 13035 // peephole %{ | |
| 13036 // peepmatch ( addP_eReg_imm movP ); | |
| 13037 // peepconstraint ( 0.dst == 1.dst ); | |
| 13038 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13039 // %} | |
| 13040 | |
| 13041 // // Change load of spilled value to only a spill | |
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13042 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13043 // match(Set mem (StoreI mem src)); |
| 13044 // %} | |
| 13045 // | |
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13046 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13047 // match(Set dst (LoadI mem)); |
| 13048 // %} | |
| 13049 // | |
| 13050 peephole %{ | |
| 13051 peepmatch ( loadI storeI ); | |
| 13052 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13053 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13054 %} | |
| 13055 | |
| 13056 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13057 // These must follow all instruction definitions as they use the names | |
| 13058 // defined in the instructions definitions. |