Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 17809:a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
Summary: Take into account space needed for "trampoline code" used by calls on PPC64.
Reviewed-by: kvn
Contributed-by: lutz.schmidt@sap.com
| author | goetz |
|---|---|
| date | Tue, 25 Mar 2014 12:54:21 -0700 |
| parents | f040cf9fc9c0 |
| children | 62c54fcc0a35 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
| 126 // Class for all registers | |
| 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 128 // Class for general registers | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
| 0 | 130 // Class for general registers which may be used for implicit null checks on win95 |
| 131 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); |
| 0 | 133 // Class of "X" registers |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
134 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
| 0 | 135 // Class of registers that can appear in an address with no offset. |
| 136 // EBP and ESP require an extra instruction byte for zero offset. | |
| 137 // Used in fast-unlock | |
| 138 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 139 // Class for general registers not including ECX | |
| 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 141 // Class for general registers not including EAX | |
| 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 143 // Class for general registers not including EAX or EBX. | |
| 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 145 // Class of EAX (for multiply and divide operations) | |
| 146 reg_class eax_reg(EAX); | |
| 147 // Class of EBX (for atomic add) | |
| 148 reg_class ebx_reg(EBX); | |
| 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 150 reg_class ecx_reg(ECX); | |
| 151 // Class of EDX (for multiply and divide operations) | |
| 152 reg_class edx_reg(EDX); | |
| 153 // Class of EDI (for synchronization) | |
| 154 reg_class edi_reg(EDI); | |
| 155 // Class of ESI (for synchronization) | |
| 156 reg_class esi_reg(ESI); | |
| 157 // Singleton class for interpreter's stack pointer | |
| 158 reg_class ebp_reg(EBP); | |
| 159 // Singleton class for stack pointer | |
| 160 reg_class sp_reg(ESP); | |
| 161 // Singleton class for instruction pointer | |
| 162 // reg_class ip_reg(EIP); | |
| 163 // Class of integer register pairs | |
| 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 165 // Class of integer register pairs that aligns with calling convention | |
| 166 reg_class eadx_reg( EAX,EDX ); | |
| 167 reg_class ebcx_reg( ECX,EBX ); | |
| 168 // Not AX or DX, used in divides | |
| 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 170 | |
| 171 // Floating point registers. Notice FPR0 is not a choice. | |
| 172 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 173 // a 2-address instructions out of Intels FP stack. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
175 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
178 FPR7L,FPR7H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
179 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
180 reg_class fp_flt_reg0( FPR1L ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
181 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
182 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
185 |
| 0 | 186 %} |
| 187 | |
| 188 | |
| 189 //----------SOURCE BLOCK------------------------------------------------------- | |
| 190 // This is a block of C++ code which provides values, functions, and | |
| 191 // definitions necessary in the rest of the architecture description | |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
192 source_hpp %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
193 // Must be visible to the DFA in dfa_x86_32.cpp |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
194 extern bool is_operand_hi32_zero(Node* n); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
195 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
196 |
| 0 | 197 source %{ |
| 304 | 198 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 199 #define RELOC_DISP32 Assembler::disp32_operand |
| 200 | |
| 201 #define __ _masm. | |
| 202 | |
| 203 // How to find the high register of a Long pair, given the low register | |
| 204 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 205 | |
| 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 207 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 208 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 209 | |
| 210 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 213 // of 128-bits operands for SSE instructions. | |
| 214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 215 // Store the value to a 128-bits operand. | |
| 216 operand[0] = lo; | |
| 217 operand[1] = hi; | |
| 218 return operand; | |
| 219 } | |
| 220 | |
| 221 // Buffer for 128-bits masks used by SSE instructions. | |
| 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 223 | |
| 224 // Static initialization during VM startup. | |
| 225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 229 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
230 // Offset hacking within calls. |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
231 static int pre_call_resets_size() { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
232 int size = 0; |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
233 Compile* C = Compile::current(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
234 if (C->in_24_bit_fp_mode()) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
235 size += 6; // fldcw |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
236 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
237 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
238 size += 3; // vzeroupper |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
239 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
240 return size; |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
241 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
242 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
243 static int preserve_SP_size() { |
| 4759 | 244 return 2; // op, rm(reg/reg) |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
245 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
246 |
| 0 | 247 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 248 // from the start of the call to the point where the return address | |
| 249 // will point. | |
| 250 int MachCallStaticJavaNode::ret_addr_offset() { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
252 if (_method_handle_invoke) |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
253 offset += preserve_SP_size(); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
254 return offset; |
| 0 | 255 } |
| 256 | |
| 257 int MachCallDynamicJavaNode::ret_addr_offset() { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points |
| 0 | 259 } |
| 260 | |
| 261 static int sizeof_FFree_Float_Stack_All = -1; | |
| 262 | |
| 263 int MachCallRuntimeNode::ret_addr_offset() { | |
| 264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); |
| 0 | 266 } |
| 267 | |
| 268 // Indicate if the safepoint node needs the polling page as an input. | |
| 269 // Since x86 does have absolute addressing, it doesn't. | |
| 270 bool SafePointNode::needs_polling_address_input() { | |
| 271 return false; | |
| 272 } | |
| 273 | |
| 274 // | |
| 275 // Compute padding required for nodes which need alignment | |
| 276 // | |
| 277 | |
| 278 // The address of the call instruction needs to be 4-byte aligned to | |
| 279 // ensure that it does not span a cache line so that it can be patched. | |
| 280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
281 current_offset += pre_call_resets_size(); // skip fldcw, if any |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
282 current_offset += 1; // skip call opcode byte |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
283 return round_to(current_offset, alignment_required()) - current_offset; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
284 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
285 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
286 // The address of the call instruction needs to be 4-byte aligned to |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
287 // ensure that it does not span a cache line so that it can be patched. |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
289 current_offset += pre_call_resets_size(); // skip fldcw, if any |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 291 current_offset += 1; // skip call opcode byte |
| 292 return round_to(current_offset, alignment_required()) - current_offset; | |
| 293 } | |
| 294 | |
| 295 // The address of the call instruction needs to be 4-byte aligned to | |
| 296 // ensure that it does not span a cache line so that it can be patched. | |
| 297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
298 current_offset += pre_call_resets_size(); // skip fldcw, if any |
| 0 | 299 current_offset += 5; // skip MOV instruction |
| 300 current_offset += 1; // skip call opcode byte | |
| 301 return round_to(current_offset, alignment_required()) - current_offset; | |
| 302 } | |
| 303 | |
| 304 // EMIT_RM() | |
| 305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 307 cbuf.insts()->emit_int8(c); |
| 0 | 308 } |
| 309 | |
| 310 // EMIT_CC() | |
| 311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 312 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 313 cbuf.insts()->emit_int8(c); |
| 0 | 314 } |
| 315 | |
| 316 // EMIT_OPCODE() | |
| 317 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 318 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 319 } |
| 320 | |
| 321 // EMIT_OPCODE() w/ relocation information | |
| 322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 323 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 324 emit_opcode(cbuf, code); |
| 325 } | |
| 326 | |
| 327 // EMIT_D8() | |
| 328 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 329 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 330 } |
| 331 | |
| 332 // EMIT_D16() | |
| 333 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 334 cbuf.insts()->emit_int16(d16); |
| 0 | 335 } |
| 336 | |
| 337 // EMIT_D32() | |
| 338 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 339 cbuf.insts()->emit_int32(d32); |
| 0 | 340 } |
| 341 | |
| 342 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 344 int format) { | |
| 1748 | 345 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 346 cbuf.insts()->emit_int32(d32); | |
| 0 | 347 } |
| 348 | |
| 349 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 351 int format) { | |
| 352 #ifdef ASSERT | |
| 353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
|
12316
190899198332
7195622: CheckUnhandledOops has limited usefulness now
hseigel
parents:
10169
diff
changeset
|
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 355 } |
| 356 #endif | |
| 1748 | 357 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 358 cbuf.insts()->emit_int32(d32); | |
| 0 | 359 } |
| 360 | |
| 361 // Access stack slot for load or store | |
| 362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 364 if( -128 <= disp && disp <= 127 ) { | |
| 365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 367 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 368 } else { | |
| 369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 371 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 372 } | |
| 373 } | |
| 374 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
375 // rRegI ereg, memory mem) %{ // emit_reg_mem |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 377 // There is no index & no scale, use form without SIB byte |
| 378 if ((index == 0x4) && | |
| 379 (scale == 0) && (base != ESP_enc)) { | |
| 380 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 381 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 382 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 383 } | |
| 384 else { // If 8-bit displacement, mode 0x1 | |
| 385 if ((displace >= -128) && (displace <= 127) | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
386 && (disp_reloc == relocInfo::none) ) { |
| 0 | 387 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 388 emit_d8(cbuf, displace); | |
| 389 } | |
| 390 else { // If 32-bit displacement | |
| 391 if (base == -1) { // Special flag for absolute address | |
| 392 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 393 // (manual lies; no SIB needed here) | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
394 if ( disp_reloc != relocInfo::none ) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 396 } else { |
| 397 emit_d32 (cbuf, displace); | |
| 398 } | |
| 399 } | |
| 400 else { // Normal base + offset | |
| 401 emit_rm(cbuf, 0x2, reg_encoding, base); | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
402 if ( disp_reloc != relocInfo::none ) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 404 } else { |
| 405 emit_d32 (cbuf, displace); | |
| 406 } | |
| 407 } | |
| 408 } | |
| 409 } | |
| 410 } | |
| 411 else { // Else, encode with the SIB byte | |
| 412 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 413 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 414 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 415 emit_rm(cbuf, scale, index, base); | |
| 416 } | |
| 417 else { // If 8-bit displacement, mode 0x1 | |
| 418 if ((displace >= -128) && (displace <= 127) | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
419 && (disp_reloc == relocInfo::none) ) { |
| 0 | 420 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 421 emit_rm(cbuf, scale, index, base); | |
| 422 emit_d8(cbuf, displace); | |
| 423 } | |
| 424 else { // If 32-bit displacement | |
| 425 if (base == 0x04 ) { | |
| 426 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 427 emit_rm(cbuf, scale, index, 0x04); | |
| 428 } else { | |
| 429 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 430 emit_rm(cbuf, scale, index, base); | |
| 431 } | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
432 if ( disp_reloc != relocInfo::none ) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 434 } else { |
| 435 emit_d32 (cbuf, displace); | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 } | |
| 440 } | |
| 441 | |
| 442 | |
| 443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 444 if( dst_encoding == src_encoding ) { | |
| 445 // reg-reg copy, use an empty encoding | |
| 446 } else { | |
| 447 emit_opcode( cbuf, 0x8B ); | |
| 448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 449 } | |
| 450 } | |
| 451 | |
| 4759 | 452 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 453 Label exit; | |
| 454 __ jccb(Assembler::noParity, exit); | |
| 455 __ pushf(); | |
| 456 // | |
| 457 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 458 // zero OF,AF,SF for NaN values. | |
| 459 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 460 // values returns 'less than' result (CF is set). | |
| 461 // Leave the rest of flags unchanged. | |
| 462 // | |
| 463 // 7 6 5 4 3 2 1 0 | |
| 464 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 465 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 466 // | |
| 467 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 468 __ popf(); | |
| 469 __ bind(exit); | |
| 470 } | |
| 471 | |
| 472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 473 Label done; | |
| 474 __ movl(dst, -1); | |
| 475 __ jcc(Assembler::parity, done); | |
| 476 __ jcc(Assembler::below, done); | |
| 477 __ setb(Assembler::notEqual, dst); | |
| 478 __ movzbl(dst, dst); | |
| 479 __ bind(done); | |
| 0 | 480 } |
| 481 | |
| 482 | |
| 483 //============================================================================= | |
| 2008 | 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 485 | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
486 int Compile::ConstantTable::calculate_table_base_offset() const { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
487 return 0; // absolute addressing, no offset |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
488 } |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
489 |
|
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
492 ShouldNotReachHere(); |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
493 } |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
494 |
| 2008 | 495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 496 // Empty encoding | |
| 497 } | |
| 498 | |
| 499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 500 return 0; | |
| 501 } | |
| 502 | |
| 503 #ifndef PRODUCT | |
| 504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 505 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 506 } | |
| 507 #endif | |
| 508 | |
| 509 | |
| 510 //============================================================================= | |
| 0 | 511 #ifndef PRODUCT |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 513 Compile* C = ra_->C; |
| 514 | |
| 515 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
517 // Remove wordSize for return addr which is already pushed. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
518 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
519 |
| 0 | 520 if (C->need_stack_bang(framesize)) { |
| 521 framesize -= wordSize; | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
522 st->print("# stack bang"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
523 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
524 st->print("PUSH EBP\t# Save EBP"); |
| 0 | 525 if (framesize) { |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
526 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
527 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 528 } |
| 529 } else { | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
530 st->print("SUB ESP, #%d\t# Create frame",framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
531 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
532 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
534 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
535 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
536 if (VerifyStackAtCalls) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
537 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
538 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 540 } |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
541 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
542 if( C->in_24_bit_fp_mode() ) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
543 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
544 st->print("FLDCW \t# load 24 bit fpu control word"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
545 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
546 if (UseSSE >= 2 && VerifyFPU) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
547 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
548 st->print("# verify FPU stack (must be clean on entry)"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
549 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
550 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
551 #ifdef ASSERT |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
552 if (VerifyStackAtCalls) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
553 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
554 st->print("# stack alignment check"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
555 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
556 #endif |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
557 st->cr(); |
| 0 | 558 } |
| 559 #endif | |
| 560 | |
| 561 | |
| 562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 563 Compile* C = ra_->C; | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
564 MacroAssembler _masm(&cbuf); |
| 0 | 565 |
| 566 int framesize = C->frame_slots() << LogBytesPerInt; | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
567 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode()); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
569 |
| 1748 | 570 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 571 |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
572 if (C->has_mach_constant_base_node()) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
573 // NOTE: We set the table base offset here because users might be |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
574 // emitted before MachConstantBaseNode. |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
575 Compile::ConstantTable& constant_table = C->constant_table(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
577 } |
| 0 | 578 } |
| 579 | |
| 580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 581 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 582 } | |
| 583 | |
| 584 int MachPrologNode::reloc() const { | |
| 585 return 0; // a large enough number | |
| 586 } | |
| 587 | |
| 588 //============================================================================= | |
| 589 #ifndef PRODUCT | |
| 590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 591 Compile *C = ra_->C; | |
| 592 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 594 // Remove two words for return addr and rbp, | |
| 595 framesize -= 2*wordSize; | |
| 596 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
597 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
598 st->print("VZEROUPPER"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
599 st->cr(); st->print("\t"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
600 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
601 if (C->in_24_bit_fp_mode()) { |
| 0 | 602 st->print("FLDCW standard control word"); |
| 603 st->cr(); st->print("\t"); | |
| 604 } | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
605 if (framesize) { |
| 0 | 606 st->print("ADD ESP,%d\t# Destroy frame",framesize); |
| 607 st->cr(); st->print("\t"); | |
| 608 } | |
| 609 st->print_cr("POPL EBP"); st->print("\t"); | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
610 if (do_polling() && C->is_method_compilation()) { |
| 0 | 611 st->print("TEST PollPage,EAX\t! Poll Safepoint"); |
| 612 st->cr(); st->print("\t"); | |
| 613 } | |
| 614 } | |
| 615 #endif | |
| 616 | |
| 617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 618 Compile *C = ra_->C; | |
| 619 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
620 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
621 // Clear upper bits of YMM registers when current compiled code uses |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
622 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
623 MacroAssembler masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
624 masm.vzeroupper(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
625 } |
| 0 | 626 // If method set FPU control word, restore to standard control word |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
627 if (C->in_24_bit_fp_mode()) { |
| 0 | 628 MacroAssembler masm(&cbuf); |
| 629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 630 } | |
| 631 | |
| 632 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 634 // Remove two words for return addr and rbp, | |
| 635 framesize -= 2*wordSize; | |
| 636 | |
| 637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 638 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
639 if (framesize >= 128) { |
| 0 | 640 emit_opcode(cbuf, 0x81); // add SP, #framesize |
| 641 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 642 emit_d32(cbuf, framesize); | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
643 } else if (framesize) { |
| 0 | 644 emit_opcode(cbuf, 0x83); // add SP, #framesize |
| 645 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 646 emit_d8(cbuf, framesize); | |
| 647 } | |
| 648 | |
| 649 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 650 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
651 if (do_polling() && C->is_method_compilation()) { |
| 1748 | 652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 653 emit_opcode(cbuf,0x85); |
| 654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 655 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 656 } | |
| 657 } | |
| 658 | |
| 659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 660 Compile *C = ra_->C; | |
| 661 // If method set FPU control word, restore to standard control word | |
| 662 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
664 if (do_polling() && C->is_method_compilation()) size += 6; |
| 0 | 665 |
| 666 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 668 // Remove two words for return addr and rbp, | |
| 669 framesize -= 2*wordSize; | |
| 670 | |
| 671 size++; // popl rbp, | |
| 672 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
673 if (framesize >= 128) { |
| 0 | 674 size += 6; |
| 675 } else { | |
| 676 size += framesize ? 3 : 0; | |
| 677 } | |
| 678 return size; | |
| 679 } | |
| 680 | |
| 681 int MachEpilogNode::reloc() const { | |
| 682 return 0; // a large enough number | |
| 683 } | |
| 684 | |
| 685 const Pipeline * MachEpilogNode::pipeline() const { | |
| 686 return MachNode::pipeline_class(); | |
| 687 } | |
| 688 | |
| 689 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 690 | |
| 691 //============================================================================= | |
| 692 | |
| 693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 694 static enum RC rc_class( OptoReg::Name reg ) { | |
| 695 | |
| 696 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 697 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 698 | |
| 699 VMReg r = OptoReg::as_VMReg(reg); | |
| 700 if (r->is_Register()) return rc_int; | |
| 701 if (r->is_FloatRegister()) { | |
| 702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 703 return rc_float; | |
| 704 } | |
| 705 assert(r->is_XMMRegister(), "must be"); | |
| 706 return rc_xmm; | |
| 707 } | |
| 708 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
710 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 711 if( cbuf ) { |
| 712 emit_opcode (*cbuf, opcode ); | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 714 #ifndef PRODUCT |
| 715 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
716 if( size != 0 ) st->print("\n\t"); |
| 0 | 717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 720 } else { // FLD, FST, PUSH, POP |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
721 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 722 } |
| 723 #endif | |
| 724 } | |
| 725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 726 return size+3+offset_size; | |
| 727 } | |
| 728 | |
| 729 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 732 if (cbuf) { |
| 733 MacroAssembler _masm(cbuf); | |
| 734 if (reg_lo+1 == reg_hi) { // double move? | |
| 735 if (is_load) { | |
| 736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 737 } else { | |
| 738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 739 } | |
| 0 | 740 } else { |
| 4759 | 741 if (is_load) { |
| 742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 743 } else { | |
| 744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 745 } | |
| 0 | 746 } |
| 747 #ifndef PRODUCT | |
| 4759 | 748 } else if (!do_size) { |
| 749 if (size != 0) st->print("\n\t"); | |
| 750 if (reg_lo+1 == reg_hi) { // double move? | |
| 751 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 753 Matcher::regName[reg_lo], offset); | |
| 754 else st->print("MOVSD [ESP + #%d],%s", | |
| 755 offset, Matcher::regName[reg_lo]); | |
| 0 | 756 } else { |
| 4759 | 757 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 758 Matcher::regName[reg_lo], offset); | |
| 759 else st->print("MOVSS [ESP + #%d],%s", | |
| 760 offset, Matcher::regName[reg_lo]); | |
| 0 | 761 } |
| 762 #endif | |
| 763 } | |
| 764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 766 return size+5+offset_size; |
| 767 } | |
| 768 | |
| 769 | |
| 770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
771 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 772 if (cbuf) { |
| 773 MacroAssembler _masm(cbuf); | |
| 774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 776 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 777 } else { | |
| 778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 779 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 780 } | |
| 0 | 781 #ifndef PRODUCT |
| 4759 | 782 } else if (!do_size) { |
| 783 if (size != 0) st->print("\n\t"); | |
| 784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 787 } else { |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 789 } |
| 4759 | 790 } else { |
| 0 | 791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 793 } else { |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 795 } |
| 4759 | 796 } |
| 0 | 797 #endif |
| 798 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 800 // Only MOVAPS SSE prefix uses 1 byte. |
| 801 int sz = 4; | |
| 802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 804 return size + sz; | |
| 0 | 805 } |
| 806 | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
808 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
809 // 32-bit |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
810 if (cbuf) { |
| 4759 | 811 MacroAssembler _masm(cbuf); |
| 812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 813 as_Register(Matcher::_regEncode[src_lo])); | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
814 #ifndef PRODUCT |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
815 } else if (!do_size) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
817 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
818 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
819 return 4; |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
820 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
821 |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
822 |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
824 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
825 // 32-bit |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
826 if (cbuf) { |
| 4759 | 827 MacroAssembler _masm(cbuf); |
| 828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 829 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
830 #ifndef PRODUCT |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
831 } else if (!do_size) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
833 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
834 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
835 return 4; |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
836 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
837 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 839 if( cbuf ) { |
| 840 emit_opcode(*cbuf, 0x8B ); | |
| 841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 842 #ifndef PRODUCT | |
| 843 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
844 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 846 #endif |
| 847 } | |
| 848 return size+2; | |
| 849 } | |
| 850 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
852 int offset, int size, outputStream* st ) { |
| 0 | 853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 854 if( cbuf ) { | |
| 855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 857 #ifndef PRODUCT | |
| 858 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
859 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
860 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 861 #endif |
| 862 } | |
| 863 size += 2; | |
| 864 } | |
| 865 | |
| 866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 867 const char *op_str; | |
| 868 int op; | |
| 869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 871 op = 0xDD; | |
| 872 } else { // 32-bit store | |
| 873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 874 op = 0xD9; | |
| 875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 876 } | |
| 877 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 879 } |
| 880 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
883 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
884 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
886 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
887 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
889 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
890 int calc_size = 0; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
893 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
894 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
895 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
896 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
897 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
898 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
899 src_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
900 dst_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
903 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
904 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
905 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
907 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
908 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
910 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
911 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
912 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
913 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
914 if (cbuf) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
915 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
916 int offset = __ offset(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
917 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
918 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
919 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
920 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
921 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
922 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
923 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
924 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
925 __ pushl(Address(rsp, src_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
926 __ popl (Address(rsp, dst_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
927 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
928 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
929 __ movdqu(Address(rsp, -16), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
930 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
931 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
932 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
933 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
934 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
935 __ vmovdqu(Address(rsp, -32), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
936 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
937 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
938 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
939 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
940 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
941 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
942 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
943 int size = __ offset() - offset; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
944 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
945 return size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
946 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
947 } else if (!do_size) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
948 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
949 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
951 "popl [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
952 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
953 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
954 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
956 "popq [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
957 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
958 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
959 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
960 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
961 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
963 "movdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
964 "movdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
965 "movdqu xmm0, [rsp - #16]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
966 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
967 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
968 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
970 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
971 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
972 "vmovdqu xmm0, [rsp - #32]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
973 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
974 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
975 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
976 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
977 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
978 #endif |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
979 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
980 return calc_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
981 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
982 |
| 0 | 983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 984 // Get registers to move | |
| 985 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 986 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 987 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 988 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 989 | |
| 990 enum RC src_second_rc = rc_class(src_second); | |
| 991 enum RC src_first_rc = rc_class(src_first); | |
| 992 enum RC dst_second_rc = rc_class(dst_second); | |
| 993 enum RC dst_first_rc = rc_class(dst_first); | |
| 994 | |
| 995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 996 | |
| 997 // Generate spill code! | |
| 998 int size = 0; | |
| 999 | |
| 1000 if( src_first == dst_first && src_second == dst_second ) | |
| 1001 return size; // Self copy, no move | |
| 1002 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1003 if (bottom_type()->isa_vect() != NULL) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1004 uint ireg = ideal_reg(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1009 // mem -> mem |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1010 int src_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1011 int dst_offset = ra_->reg2offset(dst_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1016 int stack_offset = ra_->reg2offset(dst_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1019 int stack_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1021 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1022 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1023 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1024 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1025 |
| 0 | 1026 // -------------------------------------- |
| 1027 // Check for mem-mem move. push/pop to move. | |
| 1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1029 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1034 } | |
| 1035 // move low bits | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1041 } |
| 1042 return size; | |
| 1043 } | |
| 1044 | |
| 1045 // -------------------------------------- | |
| 1046 // Check for integer reg-reg copy | |
| 1047 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1049 |
| 1050 // Check for integer store | |
| 1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1053 |
| 1054 // Check for integer load | |
| 1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1057 |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1058 // Check for integer reg-xmm reg copy |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1061 "no 64 bit integer-float reg moves" ); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1063 } |
| 0 | 1064 // -------------------------------------- |
| 1065 // Check for float reg-reg copy | |
| 1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1069 if( cbuf ) { | |
| 1070 | |
| 1071 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1072 // indexing issue mentioned in a comment in the reg_def sections | |
| 1073 // for FPR registers many lines above here. | |
| 1074 | |
| 1075 if( src_first != FPR1L_num ) { | |
| 1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1080 } else { | |
| 1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1083 } | |
| 1084 #ifndef PRODUCT | |
| 1085 } else if( !do_size ) { | |
| 1086 if( size != 0 ) st->print("\n\t"); | |
| 1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1088 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1089 #endif | |
| 1090 } | |
| 1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1092 } | |
| 1093 | |
| 1094 // Check for float store | |
| 1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1097 } |
| 1098 | |
| 1099 // Check for float load | |
| 1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1101 int offset = ra_->reg2offset(src_first); | |
| 1102 const char *op_str; | |
| 1103 int op; | |
| 1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1105 op_str = "FLD_D"; | |
| 1106 op = 0xDD; | |
| 1107 } else { // 32-bit load | |
| 1108 op_str = "FLD_S"; | |
| 1109 op = 0xD9; | |
| 1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1111 } | |
| 1112 if( cbuf ) { | |
| 1113 emit_opcode (*cbuf, op ); | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1117 #ifndef PRODUCT | |
| 1118 } else if( !do_size ) { | |
| 1119 if( size != 0 ) st->print("\n\t"); | |
| 1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1121 #endif | |
| 1122 } | |
| 1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1124 return size + 3+offset_size+2; | |
| 1125 } | |
| 1126 | |
| 1127 // Check for xmm reg-reg copy | |
| 1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1130 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1131 "no non-adjacent float-moves" ); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1133 } |
| 1134 | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1135 // Check for xmm reg-integer reg copy |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1138 "no 64 bit float-integer reg moves" ); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1140 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1141 |
| 0 | 1142 // Check for xmm store |
| 1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1145 } |
| 1146 | |
| 1147 // Check for float xmm load | |
| 1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1150 } |
| 1151 | |
| 1152 // Copy from float reg to xmm reg | |
| 1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1154 // copy to the top of stack from floating point reg | |
| 1155 // and use LEA to preserve flags | |
| 1156 if( cbuf ) { | |
| 1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1160 emit_d8(*cbuf,0xF8); | |
| 1161 #ifndef PRODUCT | |
| 1162 } else if( !do_size ) { | |
| 1163 if( size != 0 ) st->print("\n\t"); | |
| 1164 st->print("LEA ESP,[ESP-8]"); | |
| 1165 #endif | |
| 1166 } | |
| 1167 size += 4; | |
| 1168 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1170 |
| 1171 // Copy from the temp memory to the xmm reg. | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1173 |
| 1174 if( cbuf ) { | |
| 1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1178 emit_d8(*cbuf,0x08); | |
| 1179 #ifndef PRODUCT | |
| 1180 } else if( !do_size ) { | |
| 1181 if( size != 0 ) st->print("\n\t"); | |
| 1182 st->print("LEA ESP,[ESP+8]"); | |
| 1183 #endif | |
| 1184 } | |
| 1185 size += 4; | |
| 1186 return size; | |
| 1187 } | |
| 1188 | |
| 1189 assert( size > 0, "missed a case" ); | |
| 1190 | |
| 1191 // -------------------------------------------------------------------- | |
| 1192 // Check for second bits still needing moving. | |
| 1193 if( src_second == dst_second ) | |
| 1194 return size; // Self copy; no move | |
| 1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1196 | |
| 1197 // Check for second word int-int move | |
| 1198 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1200 |
| 1201 // Check for second word integer store | |
| 1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1204 |
| 1205 // Check for second word integer load | |
| 1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1208 |
| 1209 | |
| 1210 Unimplemented(); | |
| 1211 } | |
| 1212 | |
| 1213 #ifndef PRODUCT | |
| 4950 | 1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1215 implementation( NULL, ra_, false, st ); |
| 1216 } | |
| 1217 #endif | |
| 1218 | |
| 1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1220 implementation( &cbuf, ra_, false, NULL ); | |
| 1221 } | |
| 1222 | |
| 1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1224 return implementation( NULL, ra_, true, NULL ); | |
| 1225 } | |
| 1226 | |
| 1227 | |
| 1228 //============================================================================= | |
| 1229 #ifndef PRODUCT | |
| 1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1232 int reg = ra_->get_reg_first(this); | |
| 1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1234 } | |
| 1235 #endif | |
| 1236 | |
| 1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1239 int reg = ra_->get_encode(this); | |
| 1240 if( offset >= 128 ) { | |
| 1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1242 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1244 emit_d32(cbuf, offset); | |
| 1245 } | |
| 1246 else { | |
| 1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1248 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1250 emit_d8(cbuf, offset); | |
| 1251 } | |
| 1252 } | |
| 1253 | |
| 1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1256 if( offset >= 128 ) { | |
| 1257 return 7; | |
| 1258 } | |
| 1259 else { | |
| 1260 return 4; | |
| 1261 } | |
| 1262 } | |
| 1263 | |
| 1264 //============================================================================= | |
| 1265 #ifndef PRODUCT | |
| 1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1269 st->print_cr("\tNOP"); | |
| 1270 st->print_cr("\tNOP"); | |
| 1271 if( !OptoBreakpoint ) | |
| 1272 st->print_cr("\tNOP"); | |
| 1273 } | |
| 1274 #endif | |
| 1275 | |
| 1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1277 MacroAssembler masm(&cbuf); | |
| 1278 #ifdef ASSERT | |
| 1748 | 1279 uint insts_size = cbuf.insts_size(); |
| 0 | 1280 #endif |
| 304 | 1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1282 masm.jump_cc(Assembler::notEqual, |
| 1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1284 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1285 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1286 int nops_cnt = 2; | |
| 1287 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1288 nops_cnt += 1; | |
| 1289 masm.nop(nops_cnt); | |
| 1290 | |
| 1748 | 1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1292 } |
| 1293 | |
| 1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1295 return OptoBreakpoint ? 11 : 12; | |
| 1296 } | |
| 1297 | |
| 1298 | |
| 1299 //============================================================================= | |
| 1300 | |
| 1301 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1302 return regnum - 32; // The FP registers are in the second chunk | |
| 1303 } | |
| 1304 | |
| 1305 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1306 const bool Matcher::convL2FSupported(void) { | |
| 1307 return true; | |
| 1308 } | |
| 1309 | |
| 1310 // Is this branch offset short enough that a short branch can be used? | |
| 1311 // | |
| 1312 // NOTE: If the platform does not provide any short branch variants, then | |
| 1313 // this method should return false for offset 0. | |
| 3851 | 1314 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1315 // The passed offset is relative to address of the branch. | |
| 1316 // On 86 a branch displacement is calculated relative to address | |
| 1317 // of a next instruction. | |
| 1318 offset -= br_size; | |
| 1319 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1320 // the short version of jmpConUCF2 contains multiple branches, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1321 // making the reach slightly less |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1322 if (rule == jmpConUCF2_rule) |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1323 return (-126 <= offset && offset <= 125); |
| 0 | 1324 return (-128 <= offset && offset <= 127); |
| 1325 } | |
| 1326 | |
| 1327 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1328 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1329 return false; | |
| 1330 } | |
| 1331 | |
| 1332 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1333 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1334 | |
| 1335 // Threshold size for cleararray. | |
| 1336 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1337 | |
| 4047 | 1338 // Needs 2 CMOV's for longs. |
| 1339 const int Matcher::long_cmove_cost() { return 1; } | |
| 1340 | |
| 1341 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1342 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1343 | |
|
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1344 // Does the CPU require late expand (see block.cpp for description of late expand)? |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1345 const bool Matcher::require_postalloc_expand = false; |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1346 |
| 0 | 1347 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1348 // be subsumed into complex addressing expressions or compute them into | |
| 1349 // registers? True for Intel but false for most RISCs | |
| 1350 const bool Matcher::clone_shift_expressions = true; | |
| 1351 | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1352 // Do we need to mask the count passed to shift instructions or does |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1353 // the cpu only look at the lower 5/6 bits anyway? |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1354 const bool Matcher::need_masked_shift_count = false; |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1355 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1356 bool Matcher::narrow_oop_use_complex_address() { |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1357 ShouldNotCallThis(); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1358 return true; |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1359 } |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1360 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1361 bool Matcher::narrow_klass_use_complex_address() { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1362 ShouldNotCallThis(); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1363 return true; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1364 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1365 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1366 |
| 0 | 1367 // Is it better to copy float constants, or load them directly from memory? |
| 1368 // Intel can load a float constant from a direct address, requiring no | |
| 1369 // extra registers. Most RISCs will have to materialize an address into a | |
| 1370 // register first, so they would do better to copy the constant from stack. | |
| 1371 const bool Matcher::rematerialize_float_constants = true; | |
| 1372 | |
| 1373 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1374 // needed. Else we split the double into 2 integer pieces and move it | |
| 1375 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1376 // Java calling convention forces doubles to be aligned. | |
| 1377 const bool Matcher::misaligned_doubles_ok = true; | |
| 1378 | |
| 1379 | |
| 1380 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1381 // Get the memory operand from the node | |
| 1382 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1383 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1384 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1385 uint opcnt = 1; // First operand | |
| 1386 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1387 while( idx >= skipped+num_edges ) { | |
| 1388 skipped += num_edges; | |
| 1389 opcnt++; // Bump operand count | |
| 1390 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1391 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1392 } | |
| 1393 | |
| 1394 MachOper *memory = node->_opnds[opcnt]; | |
| 1395 MachOper *new_memory = NULL; | |
| 1396 switch (memory->opcode()) { | |
| 1397 case DIRECT: | |
| 1398 case INDOFFSET32X: | |
| 1399 // No transformation necessary. | |
| 1400 return; | |
| 1401 case INDIRECT: | |
| 1402 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1403 break; | |
| 1404 case INDOFFSET8: | |
| 1405 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1406 break; | |
| 1407 case INDOFFSET32: | |
| 1408 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1409 break; | |
| 1410 case INDINDEXOFFSET: | |
| 1411 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1412 break; | |
| 1413 case INDINDEXSCALE: | |
| 1414 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1415 break; | |
| 1416 case INDINDEXSCALEOFFSET: | |
| 1417 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1418 break; | |
| 1419 case LOAD_LONG_INDIRECT: | |
| 1420 case LOAD_LONG_INDOFFSET32: | |
| 1421 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1422 return; | |
| 1423 default: | |
| 1424 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1425 return; | |
| 1426 } | |
| 1427 node->_opnds[opcnt] = new_memory; | |
| 1428 } | |
| 1429 | |
| 1430 // Advertise here if the CPU requires explicit rounding operations | |
| 1431 // to implement the UseStrictFP mode. | |
| 1432 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1433 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1434 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1435 // On x32 it is stored with convertion only when FPU is used for floats. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1436 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1437 |
| 0 | 1438 // Do ints take an entire long register or just half? |
| 1439 const bool Matcher::int_in_long = false; | |
| 1440 | |
| 1441 // Return whether or not this register is ever used as an argument. This | |
| 1442 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1443 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1444 // arguments in those registers not be available to the callee. | |
| 1445 bool Matcher::can_be_java_arg( int reg ) { | |
| 1446 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1447 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1448 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1449 return false; | |
| 1450 } | |
| 1451 | |
| 1452 bool Matcher::is_spillable_arg( int reg ) { | |
| 1453 return can_be_java_arg(reg); | |
| 1454 } | |
| 1455 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1456 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1457 // Use hardware integer DIV instruction when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1458 // it is faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1459 // Only when constant divisor fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1460 // (min_jint is excluded to get only correct |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1461 // positive 32 bit values from negative). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1462 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1463 (divisor == (int)divisor && divisor != min_jint); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1464 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1465 |
| 0 | 1466 // Register for DIVI projection of divmodI |
| 1467 RegMask Matcher::divI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1468 return EAX_REG_mask(); |
| 0 | 1469 } |
| 1470 | |
| 1471 // Register for MODI projection of divmodI | |
| 1472 RegMask Matcher::modI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1473 return EDX_REG_mask(); |
| 0 | 1474 } |
| 1475 | |
| 1476 // Register for DIVL projection of divmodL | |
| 1477 RegMask Matcher::divL_proj_mask() { | |
| 1478 ShouldNotReachHere(); | |
| 1479 return RegMask(); | |
| 1480 } | |
| 1481 | |
| 1482 // Register for MODL projection of divmodL | |
| 1483 RegMask Matcher::modL_proj_mask() { | |
| 1484 ShouldNotReachHere(); | |
| 1485 return RegMask(); | |
| 1486 } | |
| 1487 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1488 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1489 return EBP_REG_mask(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1490 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1491 |
| 12323 | 1492 const RegMask Matcher::mathExactI_result_proj_mask() { |
| 1493 return EAX_REG_mask(); | |
| 1494 } | |
| 1495 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1496 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1497 ShouldNotReachHere(); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1498 return RegMask(); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1499 } |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1500 |
| 12323 | 1501 const RegMask Matcher::mathExactI_flags_proj_mask() { |
| 1502 return INT_FLAGS_mask(); | |
| 1503 } | |
| 1504 | |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1505 // Returns true if the high 32 bits of the value is known to be zero. |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1506 bool is_operand_hi32_zero(Node* n) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1507 int opc = n->Opcode(); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1508 if (opc == Op_AndL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1509 Node* o2 = n->in(2); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1510 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1511 return true; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1512 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1513 } |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1514 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1515 return true; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1516 } |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1517 return false; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1518 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1519 |
| 0 | 1520 %} |
| 1521 | |
| 1522 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1523 // This block specifies the encoding classes used by the compiler to output | |
| 1524 // byte streams. Encoding classes generate functions which are called by | |
| 1525 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1526 // instruction. Operands specify their base encoding interface with the | |
| 1527 // interface keyword. There are currently supported four interfaces, | |
| 1528 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1529 // operand to generate a function which returns its register number when | |
| 1530 // queried. CONST_INTER causes an operand to generate a function which | |
| 1531 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1532 // operand to generate four functions which return the Base Register, the | |
| 1533 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1534 // queried. COND_INTER causes an operand to generate six functions which | |
| 1535 // return the encoding code (ie - encoding bits for the instruction) | |
| 1536 // associated with each basic boolean condition for a conditional instruction. | |
| 1537 // Instructions specify two basic values for encoding. They use the | |
| 1538 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1539 // the class names specified in the encoding block), and they use the | |
| 1540 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1541 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1542 // needs for encoding need to be specified. | |
| 1543 encode %{ | |
| 1544 // Build emit functions for each basic byte or larger field in the intel | |
| 1545 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1546 // code in the enc_class source block. Emit functions will live in the | |
| 1547 // main source block for now. In future, we can generalize this by | |
| 1548 // adding a syntax that specifies the sizes of fields in an order, | |
| 1549 // so that the adlc can build the emit functions automagically | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1550 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1551 // Emit primary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1552 enc_class OpcP %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1553 emit_opcode(cbuf, $primary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1554 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1555 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1556 // Emit secondary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1557 enc_class OpcS %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1558 emit_opcode(cbuf, $secondary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1559 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1560 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1561 // Emit opcode directly |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1562 enc_class Opcode(immI d8) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1563 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1564 %} |
| 1565 | |
| 1566 enc_class SizePrefix %{ | |
| 1567 emit_opcode(cbuf,0x66); | |
| 1568 %} | |
| 1569 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1570 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1571 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1572 %} | |
| 1573 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1574 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1575 emit_opcode(cbuf,$opcode$$constant); |
| 1576 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1577 %} | |
| 1578 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1579 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1580 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1581 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1582 %} | |
| 1583 | |
| 1584 enc_class cdq_enc %{ | |
| 1585 // Full implementation of Java idiv and irem; checks for | |
| 1586 // special case as described in JVM spec., p.243 & p.271. | |
| 1587 // | |
| 1588 // normal case special case | |
| 1589 // | |
| 1590 // input : rax,: dividend min_int | |
| 1591 // reg: divisor -1 | |
| 1592 // | |
| 1593 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1594 // rdx: remainder (= rax, irem reg) 0 | |
| 1595 // | |
| 1596 // Code sequnce: | |
| 1597 // | |
| 1598 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1599 // 0F 85 0B 00 00 00 jne normal_case | |
| 1600 // 33 D2 xor rdx,edx | |
| 1601 // 83 F9 FF cmp rcx,0FFh | |
| 1602 // 0F 84 03 00 00 00 je done | |
| 1603 // normal_case: | |
| 1604 // 99 cdq | |
| 1605 // F7 F9 idiv rax,ecx | |
| 1606 // done: | |
| 1607 // | |
| 1608 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1609 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1610 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1611 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1612 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1613 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1614 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1615 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1616 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1617 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1618 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1619 // normal_case: | |
| 1620 emit_opcode(cbuf,0x99); // cdq | |
| 1621 // idiv (note: must be emitted by the user of this rule) | |
| 1622 // normal: | |
| 1623 %} | |
| 1624 | |
| 1625 // Dense encoding for older common ops | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1626 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1627 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1628 %} | |
| 1629 | |
| 1630 | |
| 1631 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1632 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1633 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1634 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1635 emit_opcode(cbuf, $primary | 0x02); | |
| 1636 } | |
| 1637 else { // If 32-bit immediate | |
| 1638 emit_opcode(cbuf, $primary); | |
| 1639 } | |
| 1640 %} | |
| 1641 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1642 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1643 // Emit primary opcode and set sign-extend bit |
| 1644 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1645 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1646 emit_opcode(cbuf, $primary | 0x02); } | |
| 1647 else { // If 32-bit immediate | |
| 1648 emit_opcode(cbuf, $primary); | |
| 1649 } | |
| 1650 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1651 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1652 %} | |
| 1653 | |
| 1654 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1655 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1656 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1657 $$$emit8$imm$$constant; | |
| 1658 } | |
| 1659 else { // If 32-bit immediate | |
| 1660 // Output immediate | |
| 1661 $$$emit32$imm$$constant; | |
| 1662 } | |
| 1663 %} | |
| 1664 | |
| 1665 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1666 // Emit primary opcode and set sign-extend bit | |
| 1667 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1668 int con = (int)$imm$$constant; // Throw away top bits | |
| 1669 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1670 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1671 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1672 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1673 else emit_d32(cbuf,con); | |
| 1674 %} | |
| 1675 | |
| 1676 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1677 // Emit primary opcode and set sign-extend bit | |
| 1678 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1679 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1680 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1681 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1682 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1683 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1684 else emit_d32(cbuf,con); | |
| 1685 %} | |
| 1686 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1687 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1688 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1689 %} | |
| 1690 | |
| 1691 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1692 int destlo = $dst$$reg; | |
| 1693 int desthi = HIGH_FROM_LOW(destlo); | |
| 1694 // bswap lo | |
| 1695 emit_opcode(cbuf, 0x0F); | |
| 1696 emit_cc(cbuf, 0xC8, destlo); | |
| 1697 // bswap hi | |
| 1698 emit_opcode(cbuf, 0x0F); | |
| 1699 emit_cc(cbuf, 0xC8, desthi); | |
| 1700 // xchg lo and hi | |
| 1701 emit_opcode(cbuf, 0x87); | |
| 1702 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1703 %} | |
| 1704 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1705 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1706 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1707 %} | |
| 1708 | |
| 1709 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1710 $$$emit8$primary; | |
| 1711 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1712 %} | |
| 1713 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1714 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1715 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1716 emit_d8(cbuf, op >> 8 ); | |
| 1717 emit_d8(cbuf, op & 255); | |
| 1718 %} | |
| 1719 | |
| 1720 // emulate a CMOV with a conditional branch around a MOV | |
| 1721 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1722 // Invert sense of branch from sense of CMOV | |
| 1723 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1724 emit_d8( cbuf, $brOffs$$constant ); | |
| 1725 %} | |
| 1726 | |
| 1727 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1728 Register Redi = as_Register(EDI_enc); // result register | |
| 1729 Register Reax = as_Register(EAX_enc); // super class | |
| 1730 Register Recx = as_Register(ECX_enc); // killed | |
| 1731 Register Resi = as_Register(ESI_enc); // sub class | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1732 Label miss; |
| 0 | 1733 |
| 1734 MacroAssembler _masm(&cbuf); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1735 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1736 NULL, &miss, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1737 /*set_cond_codes:*/ true); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1738 if ($primary) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1739 __ xorptr(Redi, Redi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1740 } |
| 0 | 1741 __ bind(miss); |
| 1742 %} | |
| 1743 | |
| 1744 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1745 MacroAssembler masm(&cbuf); | |
| 1746 int start = masm.offset(); | |
| 1747 if (UseSSE >= 2) { | |
| 1748 if (VerifyFPU) { | |
| 1749 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1750 } | |
| 1751 } else { | |
| 1752 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1753 // Compiled code leaves it dirty. Do cleanup now. | |
| 1754 masm.empty_FPU_stack(); | |
| 1755 } | |
| 1756 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1757 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1758 } else { | |
| 1759 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1760 } | |
| 1761 %} | |
| 1762 | |
| 1763 enc_class Verify_FPU_For_Leaf %{ | |
| 1764 if( VerifyFPU ) { | |
| 1765 MacroAssembler masm(&cbuf); | |
| 1766 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1767 } | |
| 1768 %} | |
| 1769 | |
| 1770 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1771 // This is the instruction starting address for relocation info. | |
| 1748 | 1772 cbuf.set_insts_mark(); |
| 0 | 1773 $$$emit8$primary; |
| 1774 // CALL directly to the runtime | |
| 1748 | 1775 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1776 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1777 | |
| 1778 if (UseSSE >= 2) { | |
| 1779 MacroAssembler _masm(&cbuf); | |
| 1780 BasicType rt = tf()->return_type(); | |
| 1781 | |
| 1782 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1783 // A C runtime call where the return value is unused. In SSE2+ | |
| 1784 // mode the result needs to be removed from the FPU stack. It's | |
| 1785 // likely that this function call could be removed by the | |
| 1786 // optimizer if the C function is a pure function. | |
| 1787 __ ffree(0); | |
| 1788 } else if (rt == T_FLOAT) { | |
| 304 | 1789 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1790 __ fstp_s(Address(rsp, 0)); |
| 1791 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1792 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1793 } else if (rt == T_DOUBLE) { |
| 304 | 1794 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1795 __ fstp_d(Address(rsp, 0)); |
| 1796 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1797 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1798 } |
| 1799 } | |
| 1800 %} | |
| 1801 | |
| 1802 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1803 enc_class pre_call_resets %{ |
| 0 | 1804 // If method sets FPU control word restore it here |
| 1748 | 1805 debug_only(int off0 = cbuf.insts_size()); |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1806 if (ra_->C->in_24_bit_fp_mode()) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1807 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1808 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1809 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1810 if (ra_->C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1811 // Clear upper bits of YMM registers when current compiled code uses |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1812 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1813 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1814 __ vzeroupper(); |
| 0 | 1815 } |
| 1748 | 1816 debug_only(int off1 = cbuf.insts_size()); |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1817 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction"); |
| 0 | 1818 %} |
| 1819 | |
| 1820 enc_class post_call_FPU %{ | |
| 1821 // If method sets FPU control word do it here also | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1822 if (Compile::current()->in_24_bit_fp_mode()) { |
| 0 | 1823 MacroAssembler masm(&cbuf); |
| 1824 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1825 } | |
| 1826 %} | |
| 1827 | |
| 1828 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1829 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1830 // who we intended to call. | |
| 1748 | 1831 cbuf.set_insts_mark(); |
| 0 | 1832 $$$emit8$primary; |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1833 if (!_method) { |
| 1748 | 1834 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1835 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1836 } else if (_optimized_virtual) { |
| 1748 | 1837 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1838 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1839 } else { | |
| 1748 | 1840 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1841 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1842 } | |
|
10168
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
8873
diff
changeset
|
1843 if (_method) { // Emit stub for static call. |
|
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
8873
diff
changeset
|
1844 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 1845 } |
| 1846 %} | |
| 1847 | |
| 1848 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1849 MacroAssembler _masm(&cbuf); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1850 __ ic_call((address)$meth$$method); |
| 0 | 1851 %} |
| 1852 | |
| 1853 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1854 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1855 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1856 | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1857 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1858 cbuf.set_insts_mark(); |
| 0 | 1859 $$$emit8$primary; |
| 1860 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1861 emit_d8(cbuf, disp); // Displacement | |
| 1862 | |
| 1863 %} | |
| 1864 | |
| 1865 // Following encoding is no longer used, but may be restored if calling | |
| 1866 // convention changes significantly. | |
| 1867 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1868 // | |
| 1869 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1870 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1871 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1872 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1873 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1874 // | |
| 1875 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1876 // // // so we load it immediately before the call | |
| 1877 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1878 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1879 // | |
| 1880 // // xor rbp,ebp | |
| 1881 // emit_opcode(cbuf, 0x33); | |
| 1882 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1883 // | |
| 1884 // // CALL to interpreter. | |
| 1748 | 1885 // cbuf.set_insts_mark(); |
| 0 | 1886 // $$$emit8$primary; |
| 1748 | 1887 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1888 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1889 // %} | |
| 1890 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1891 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1892 $$$emit8$primary; |
| 1893 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1894 $$$emit8$shift$$constant; | |
| 1895 %} | |
| 1896 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1897 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1898 // Load immediate does not have a zero or sign extended version |
| 1899 // for 8-bit immediates | |
| 1900 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1901 $$$emit32$src$$constant; | |
| 1902 %} | |
| 1903 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1904 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1905 // Load immediate does not have a zero or sign extended version |
| 1906 // for 8-bit immediates | |
| 1907 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1908 $$$emit32$src$$constant; | |
| 1909 %} | |
| 1910 | |
| 1911 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1912 // Load immediate does not have a zero or sign extended version | |
| 1913 // for 8-bit immediates | |
| 1914 int dst_enc = $dst$$reg; | |
| 1915 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1916 if (src_con == 0) { | |
| 1917 // xor dst, dst | |
| 1918 emit_opcode(cbuf, 0x33); | |
| 1919 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1920 } else { | |
| 1921 emit_opcode(cbuf, $primary + dst_enc); | |
| 1922 emit_d32(cbuf, src_con); | |
| 1923 } | |
| 1924 %} | |
| 1925 | |
| 1926 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1927 // Load immediate does not have a zero or sign extended version | |
| 1928 // for 8-bit immediates | |
| 1929 int dst_enc = $dst$$reg + 2; | |
| 1930 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1931 if (src_con == 0) { | |
| 1932 // xor dst, dst | |
| 1933 emit_opcode(cbuf, 0x33); | |
| 1934 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1935 } else { | |
| 1936 emit_opcode(cbuf, $primary + dst_enc); | |
| 1937 emit_d32(cbuf, src_con); | |
| 1938 } | |
| 1939 %} | |
| 1940 | |
| 1941 | |
| 1942 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1943 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1944 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1945 %} | |
| 1946 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1947 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1948 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1949 %} | |
| 1950 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1951 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1952 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1953 %} | |
| 1954 | |
| 1955 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1956 $$$emit8$primary; | |
| 1957 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1958 %} | |
| 1959 | |
| 1960 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1961 $$$emit8$secondary; | |
| 1962 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1963 %} | |
| 1964 | |
| 1965 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1966 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1967 %} | |
| 1968 | |
| 1969 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1970 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1971 %} | |
| 1972 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1973 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 1974 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 1975 %} | |
| 1976 | |
| 1977 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 1978 // Output immediate | |
| 1979 $$$emit32$src$$constant; | |
| 1980 %} | |
| 1981 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1982 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 1983 // Output Float immediate bits |
| 1984 jfloat jf = $src$$constant; | |
| 1985 int jf_as_bits = jint_cast( jf ); | |
| 1986 emit_d32(cbuf, jf_as_bits); | |
| 1987 %} | |
| 1988 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1989 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 1990 // Output Float immediate bits |
| 1991 jfloat jf = $src$$constant; | |
| 1992 int jf_as_bits = jint_cast( jf ); | |
| 1993 emit_d32(cbuf, jf_as_bits); | |
| 1994 %} | |
| 1995 | |
| 1996 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 1997 // Output immediate | |
| 1998 $$$emit16$src$$constant; | |
| 1999 %} | |
| 2000 | |
| 2001 enc_class Con_d32(immI src) %{ | |
| 2002 emit_d32(cbuf,$src$$constant); | |
| 2003 %} | |
| 2004 | |
| 2005 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2006 // Output immediate memory reference | |
| 2007 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2008 emit_d32(cbuf, 0x00); | |
| 2009 %} | |
| 2010 | |
| 2011 enc_class lock_prefix( ) %{ | |
| 2012 if( os::is_MP() ) | |
| 2013 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2014 %} | |
| 2015 | |
| 2016 // Cmp-xchg long value. | |
| 2017 // Note: we need to swap rbx, and rcx before and after the | |
| 2018 // cmpxchg8 instruction because the instruction uses | |
| 2019 // rcx as the high order word of the new value to store but | |
| 2020 // our register encoding uses rbx,. | |
| 2021 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2022 | |
| 2023 // XCHG rbx,ecx | |
| 2024 emit_opcode(cbuf,0x87); | |
| 2025 emit_opcode(cbuf,0xD9); | |
| 2026 // [Lock] | |
| 2027 if( os::is_MP() ) | |
| 2028 emit_opcode(cbuf,0xF0); | |
| 2029 // CMPXCHG8 [Eptr] | |
| 2030 emit_opcode(cbuf,0x0F); | |
| 2031 emit_opcode(cbuf,0xC7); | |
| 2032 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2033 // XCHG rbx,ecx | |
| 2034 emit_opcode(cbuf,0x87); | |
| 2035 emit_opcode(cbuf,0xD9); | |
| 2036 %} | |
| 2037 | |
| 2038 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2039 // [Lock] | |
| 2040 if( os::is_MP() ) | |
| 2041 emit_opcode(cbuf,0xF0); | |
| 2042 | |
| 2043 // CMPXCHG [Eptr] | |
| 2044 emit_opcode(cbuf,0x0F); | |
| 2045 emit_opcode(cbuf,0xB1); | |
| 2046 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2047 %} | |
| 2048 | |
| 2049 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2050 int res_encoding = $res$$reg; | |
| 2051 | |
| 2052 // MOV res,0 | |
| 2053 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2054 emit_d32( cbuf, 0 ); | |
| 2055 // JNE,s fail | |
| 2056 emit_opcode(cbuf,0x75); | |
| 2057 emit_d8(cbuf, 5 ); | |
| 2058 // MOV res,1 | |
| 2059 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2060 emit_d32( cbuf, 1 ); | |
| 2061 // fail: | |
| 2062 %} | |
| 2063 | |
| 2064 enc_class set_instruction_start( ) %{ | |
| 1748 | 2065 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2066 %} |
| 2067 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2068 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2069 int reg_encoding = $ereg$$reg; |
| 2070 int base = $mem$$base; | |
| 2071 int index = $mem$$index; | |
| 2072 int scale = $mem$$scale; | |
| 2073 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2074 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2075 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2076 %} |
| 2077 | |
| 2078 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2079 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2080 int base = $mem$$base; | |
| 2081 int index = $mem$$index; | |
| 2082 int scale = $mem$$scale; | |
| 2083 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2084 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2085 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2086 %} |
| 2087 | |
| 2088 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2089 int r1, r2; | |
| 2090 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2091 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2092 emit_opcode(cbuf,0x0F); | |
| 2093 emit_opcode(cbuf,$tertiary); | |
| 2094 emit_rm(cbuf, 0x3, r1, r2); | |
| 2095 emit_d8(cbuf,$cnt$$constant); | |
| 2096 emit_d8(cbuf,$primary); | |
| 2097 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2098 emit_d8(cbuf,$cnt$$constant); | |
| 2099 %} | |
| 2100 | |
| 2101 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2102 emit_opcode( cbuf, 0x8B ); // Move | |
| 2103 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2104 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2105 emit_d8(cbuf,$primary); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2106 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2107 emit_d8(cbuf,$cnt$$constant-32); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2108 } |
| 0 | 2109 emit_d8(cbuf,$primary); |
| 2110 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2111 emit_d8(cbuf,31); | |
| 2112 %} | |
| 2113 | |
| 2114 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2115 int r1, r2; | |
| 2116 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2117 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2118 | |
| 2119 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2120 emit_rm(cbuf, 0x3, r1, r2); | |
| 2121 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2122 emit_opcode(cbuf,$primary); | |
| 2123 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2124 emit_d8(cbuf,$cnt$$constant-32); | |
| 2125 } | |
| 2126 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2127 emit_rm(cbuf, 0x3, r2, r2); | |
| 2128 %} | |
| 2129 | |
| 2130 // Clone of RegMem but accepts an extra parameter to access each | |
| 2131 // half of a double in memory; it never needs relocation info. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2132 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2133 emit_opcode(cbuf,$opcode$$constant); |
| 2134 int reg_encoding = $rm_reg$$reg; | |
| 2135 int base = $mem$$base; | |
| 2136 int index = $mem$$index; | |
| 2137 int scale = $mem$$scale; | |
| 2138 int displace = $mem$$disp + $disp_for_half$$constant; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2139 relocInfo::relocType disp_reloc = relocInfo::none; |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2140 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2141 %} |
| 2142 | |
| 2143 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2144 // | |
| 2145 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2146 // and it never needs relocation information. | |
| 2147 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2148 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2149 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2150 int base = $mem$$base; | |
| 2151 int index = $mem$$index; | |
| 2152 int scale = $mem$$scale; | |
| 2153 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2154 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2155 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2156 %} |
| 2157 | |
| 2158 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2159 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2160 int base = $mem$$base; | |
| 2161 int index = $mem$$index; | |
| 2162 int scale = $mem$$scale; | |
| 2163 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2164 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2165 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2166 %} |
| 2167 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2168 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2169 int reg_encoding = $dst$$reg; |
| 2170 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2171 int index = 0x04; // 0x04 indicates no index | |
| 2172 int scale = 0x00; // 0x00 indicates no scale | |
| 2173 int displace = $src1$$constant; // 0x00 indicates no displacement | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2174 relocInfo::relocType disp_reloc = relocInfo::none; |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2175 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2176 %} |
| 2177 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2178 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2179 // Compare dst,src |
| 2180 emit_opcode(cbuf,0x3B); | |
| 2181 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2182 // jmp dst < src around move | |
| 2183 emit_opcode(cbuf,0x7C); | |
| 2184 emit_d8(cbuf,2); | |
| 2185 // move dst,src | |
| 2186 emit_opcode(cbuf,0x8B); | |
| 2187 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2188 %} | |
| 2189 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2190 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2191 // Compare dst,src |
| 2192 emit_opcode(cbuf,0x3B); | |
| 2193 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2194 // jmp dst > src around move | |
| 2195 emit_opcode(cbuf,0x7F); | |
| 2196 emit_d8(cbuf,2); | |
| 2197 // move dst,src | |
| 2198 emit_opcode(cbuf,0x8B); | |
| 2199 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2200 %} | |
| 2201 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2202 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2203 // If src is FPR1, we can just FST to store it. |
| 2204 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2205 int reg_encoding = 0x2; // Just store | |
| 2206 int base = $mem$$base; | |
| 2207 int index = $mem$$index; | |
| 2208 int scale = $mem$$scale; | |
| 2209 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2210 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2211 if( $src$$reg != FPR1L_enc ) { |
| 2212 reg_encoding = 0x3; // Store & pop | |
| 2213 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2214 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2215 } | |
| 1748 | 2216 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2217 emit_opcode(cbuf,$primary); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2218 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2219 %} |
| 2220 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2221 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2222 // NEG $dst |
| 2223 emit_opcode(cbuf,0xF7); | |
| 2224 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2225 %} | |
| 2226 | |
| 2227 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2228 // SETLT $dst | |
| 2229 emit_opcode(cbuf,0x0F); | |
| 2230 emit_opcode(cbuf,0x9C); | |
| 2231 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2232 %} | |
| 2233 | |
| 2234 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2235 int tmpReg = $tmp$$reg; | |
| 2236 | |
| 2237 // SUB $p,$q | |
| 2238 emit_opcode(cbuf,0x2B); | |
| 2239 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2240 // SBB $tmp,$tmp | |
| 2241 emit_opcode(cbuf,0x1B); | |
| 2242 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2243 // AND $tmp,$y | |
| 2244 emit_opcode(cbuf,0x23); | |
| 2245 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2246 // ADD $p,$tmp | |
| 2247 emit_opcode(cbuf,0x03); | |
| 2248 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2249 %} | |
| 2250 | |
| 2251 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2252 // TEST shift,32 | |
| 2253 emit_opcode(cbuf,0xF7); | |
| 2254 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2255 emit_d32(cbuf,0x20); | |
| 2256 // JEQ,s small | |
| 2257 emit_opcode(cbuf, 0x74); | |
| 2258 emit_d8(cbuf, 0x04); | |
| 2259 // MOV $dst.hi,$dst.lo | |
| 2260 emit_opcode( cbuf, 0x8B ); | |
| 2261 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2262 // CLR $dst.lo | |
| 2263 emit_opcode(cbuf, 0x33); | |
| 2264 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2265 // small: | |
| 2266 // SHLD $dst.hi,$dst.lo,$shift | |
| 2267 emit_opcode(cbuf,0x0F); | |
| 2268 emit_opcode(cbuf,0xA5); | |
| 2269 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2270 // SHL $dst.lo,$shift" | |
| 2271 emit_opcode(cbuf,0xD3); | |
| 2272 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2273 %} | |
| 2274 | |
| 2275 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2276 // TEST shift,32 | |
| 2277 emit_opcode(cbuf,0xF7); | |
| 2278 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2279 emit_d32(cbuf,0x20); | |
| 2280 // JEQ,s small | |
| 2281 emit_opcode(cbuf, 0x74); | |
| 2282 emit_d8(cbuf, 0x04); | |
| 2283 // MOV $dst.lo,$dst.hi | |
| 2284 emit_opcode( cbuf, 0x8B ); | |
| 2285 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2286 // CLR $dst.hi | |
| 2287 emit_opcode(cbuf, 0x33); | |
| 2288 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2289 // small: | |
| 2290 // SHRD $dst.lo,$dst.hi,$shift | |
| 2291 emit_opcode(cbuf,0x0F); | |
| 2292 emit_opcode(cbuf,0xAD); | |
| 2293 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2294 // SHR $dst.hi,$shift" | |
| 2295 emit_opcode(cbuf,0xD3); | |
| 2296 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2297 %} | |
| 2298 | |
| 2299 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2300 // TEST shift,32 | |
| 2301 emit_opcode(cbuf,0xF7); | |
| 2302 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2303 emit_d32(cbuf,0x20); | |
| 2304 // JEQ,s small | |
| 2305 emit_opcode(cbuf, 0x74); | |
| 2306 emit_d8(cbuf, 0x05); | |
| 2307 // MOV $dst.lo,$dst.hi | |
| 2308 emit_opcode( cbuf, 0x8B ); | |
| 2309 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2310 // SAR $dst.hi,31 | |
| 2311 emit_opcode(cbuf, 0xC1); | |
| 2312 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2313 emit_d8(cbuf, 0x1F ); | |
| 2314 // small: | |
| 2315 // SHRD $dst.lo,$dst.hi,$shift | |
| 2316 emit_opcode(cbuf,0x0F); | |
| 2317 emit_opcode(cbuf,0xAD); | |
| 2318 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2319 // SAR $dst.hi,$shift" | |
| 2320 emit_opcode(cbuf,0xD3); | |
| 2321 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2322 %} | |
| 2323 | |
| 2324 | |
| 2325 // ----------------- Encodings for floating point unit ----------------- | |
| 2326 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2327 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2328 $$$emit8$primary; |
| 2329 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2330 %} | |
| 2331 | |
| 2332 // Pop argument in FPR0 with FSTP ST(0) | |
| 2333 enc_class PopFPU() %{ | |
| 2334 emit_opcode( cbuf, 0xDD ); | |
| 2335 emit_d8( cbuf, 0xD8 ); | |
| 2336 %} | |
| 2337 | |
| 2338 // !!!!! equivalent to Pop_Reg_F | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2339 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2340 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2341 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2342 %} | |
| 2343 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2344 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2345 emit_opcode( cbuf, 0xD9 ); |
| 2346 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2347 %} | |
| 2348 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2349 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2350 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2351 emit_opcode( cbuf, 0x2D ); | |
| 2352 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2353 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2354 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2355 %} | |
| 2356 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2357 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2358 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2359 emit_opcode( cbuf, 0x2D ); | |
| 2360 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2361 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2362 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2363 %} | |
| 2364 | |
| 2365 // Special case for moving an integer register to a stack slot. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2366 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2367 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2368 %} | |
| 2369 | |
| 2370 // Special case for moving a register to a stack slot. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2371 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2372 // Opcode already emitted |
| 2373 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2374 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2375 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2376 %} | |
| 2377 | |
| 2378 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2379 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2380 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2381 %} | |
| 2382 | |
| 2383 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2384 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2385 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2386 %} | |
| 2387 | |
| 2388 // Same as Pop_Mem_F except for opcode | |
| 2389 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2390 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2391 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2392 %} | |
| 2393 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2394 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2395 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2396 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2397 %} | |
| 2398 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2399 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2400 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2401 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2402 %} | |
| 2403 | |
| 2404 // Push FPU's float to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2405 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2406 int pop = 0x02; |
| 2407 if ($src$$reg != FPR1L_enc) { | |
| 2408 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2409 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2410 pop = 0x03; | |
| 2411 } | |
| 2412 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2413 %} | |
| 2414 | |
| 2415 // Push FPU's double to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2416 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2417 int pop = 0x02; |
| 2418 if ($src$$reg != FPR1L_enc) { | |
| 2419 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2420 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2421 pop = 0x03; | |
| 2422 } | |
| 2423 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2424 %} | |
| 2425 | |
| 2426 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2427 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2428 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2429 if ($src$$reg != FPR1L_enc) { | |
| 2430 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2431 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2432 pop = 0xD8; | |
| 2433 } | |
| 2434 emit_opcode( cbuf, 0xDD ); | |
| 2435 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2436 %} | |
| 2437 | |
| 2438 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2439 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2440 // load dst in FPR0 |
| 2441 emit_opcode( cbuf, 0xD9 ); | |
| 2442 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2443 if ($src$$reg != FPR1L_enc) { | |
| 2444 // fincstp | |
| 2445 emit_opcode (cbuf, 0xD9); | |
| 2446 emit_opcode (cbuf, 0xF7); | |
| 2447 // swap src with FPR1: | |
| 2448 // FXCH FPR1 with src | |
| 2449 emit_opcode(cbuf, 0xD9); | |
| 2450 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2451 // fdecstp | |
| 2452 emit_opcode (cbuf, 0xD9); | |
| 2453 emit_opcode (cbuf, 0xF6); | |
| 2454 } | |
| 2455 %} | |
| 2456 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2457 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2458 MacroAssembler _masm(&cbuf); |
| 2459 __ subptr(rsp, 8); | |
| 2460 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2461 __ fld_d(Address(rsp, 0)); | |
| 2462 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2463 __ fld_d(Address(rsp, 0)); | |
| 2464 %} | |
| 2465 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2466 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2467 MacroAssembler _masm(&cbuf); |
| 2468 __ subptr(rsp, 4); | |
| 2469 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2470 __ fld_s(Address(rsp, 0)); | |
| 2471 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2472 __ fld_s(Address(rsp, 0)); | |
| 0 | 2473 %} |
| 2474 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2475 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2476 MacroAssembler _masm(&cbuf); |
| 2477 __ fstp_d(Address(rsp, 0)); | |
| 2478 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2479 __ addptr(rsp, 8); | |
| 0 | 2480 %} |
| 2481 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2482 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2483 MacroAssembler _masm(&cbuf); |
| 2484 __ fstp_s(Address(rsp, 0)); | |
| 2485 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2486 __ addptr(rsp, $d8$$constant); | |
| 0 | 2487 %} |
| 2488 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2489 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2490 MacroAssembler _masm(&cbuf); |
| 2491 __ subptr(rsp, 8); | |
| 2492 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2493 __ fld_d(Address(rsp, 0)); | |
| 0 | 2494 %} |
| 2495 | |
| 2496 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2497 MacroAssembler _masm(&cbuf); |
| 2498 __ subptr(rsp, 8); | |
| 0 | 2499 %} |
| 2500 | |
| 2501 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2502 MacroAssembler _masm(&cbuf); |
| 2503 __ addptr(rsp, 8); | |
| 2504 %} | |
| 2505 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2506 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2507 MacroAssembler _masm(&cbuf); |
| 2508 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2509 __ fld_d(Address(rsp, 0)); | |
| 0 | 2510 %} |
| 2511 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2512 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2513 if ($src$$reg != FPR1L_enc) { |
| 2514 // fincstp | |
| 2515 emit_opcode (cbuf, 0xD9); | |
| 2516 emit_opcode (cbuf, 0xF7); | |
| 2517 // FXCH FPR1 with src | |
| 2518 emit_opcode(cbuf, 0xD9); | |
| 2519 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2520 // fdecstp | |
| 2521 emit_opcode (cbuf, 0xD9); | |
| 2522 emit_opcode (cbuf, 0xF6); | |
| 2523 } | |
| 2524 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2525 // // FSTP FPR$dst$$reg | |
| 2526 // emit_opcode( cbuf, 0xDD ); | |
| 2527 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2528 %} | |
| 2529 | |
| 2530 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2531 // fnstsw ax | |
| 2532 emit_opcode( cbuf, 0xDF ); | |
| 2533 emit_opcode( cbuf, 0xE0 ); | |
| 2534 // sahf | |
| 2535 emit_opcode( cbuf, 0x9E ); | |
| 2536 // jnp ::skip | |
| 2537 emit_opcode( cbuf, 0x7B ); | |
| 2538 emit_opcode( cbuf, 0x05 ); | |
| 2539 %} | |
| 2540 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2541 enc_class emitModDPR() %{ |
| 0 | 2542 // fprem must be iterative |
| 2543 // :: loop | |
| 2544 // fprem | |
| 2545 emit_opcode( cbuf, 0xD9 ); | |
| 2546 emit_opcode( cbuf, 0xF8 ); | |
| 2547 // wait | |
| 2548 emit_opcode( cbuf, 0x9b ); | |
| 2549 // fnstsw ax | |
| 2550 emit_opcode( cbuf, 0xDF ); | |
| 2551 emit_opcode( cbuf, 0xE0 ); | |
| 2552 // sahf | |
| 2553 emit_opcode( cbuf, 0x9E ); | |
| 2554 // jp ::loop | |
| 2555 emit_opcode( cbuf, 0x0F ); | |
| 2556 emit_opcode( cbuf, 0x8A ); | |
| 2557 emit_opcode( cbuf, 0xF4 ); | |
| 2558 emit_opcode( cbuf, 0xFF ); | |
| 2559 emit_opcode( cbuf, 0xFF ); | |
| 2560 emit_opcode( cbuf, 0xFF ); | |
| 2561 %} | |
| 2562 | |
| 2563 enc_class fpu_flags() %{ | |
| 2564 // fnstsw_ax | |
| 2565 emit_opcode( cbuf, 0xDF); | |
| 2566 emit_opcode( cbuf, 0xE0); | |
| 2567 // test ax,0x0400 | |
| 2568 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2569 emit_opcode( cbuf, 0xA9 ); | |
| 2570 emit_d16 ( cbuf, 0x0400 ); | |
| 2571 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2572 // // test rax,0x0400 | |
| 2573 // emit_opcode( cbuf, 0xA9 ); | |
| 2574 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2575 // | |
| 2576 // jz exit (no unordered comparison) | |
| 2577 emit_opcode( cbuf, 0x74 ); | |
| 2578 emit_d8 ( cbuf, 0x02 ); | |
| 2579 // mov ah,1 - treat as LT case (set carry flag) | |
| 2580 emit_opcode( cbuf, 0xB4 ); | |
| 2581 emit_d8 ( cbuf, 0x01 ); | |
| 2582 // sahf | |
| 2583 emit_opcode( cbuf, 0x9E); | |
| 2584 %} | |
| 2585 | |
| 2586 enc_class cmpF_P6_fixup() %{ | |
| 2587 // Fixup the integer flags in case comparison involved a NaN | |
| 2588 // | |
| 2589 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2590 emit_opcode( cbuf, 0x7B ); | |
| 2591 emit_d8 ( cbuf, 0x03 ); | |
| 2592 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2593 emit_opcode( cbuf, 0xB4 ); | |
| 2594 emit_d8 ( cbuf, 0x01 ); | |
| 2595 // SAHF | |
| 2596 emit_opcode( cbuf, 0x9E); | |
| 2597 // NOP // target for branch to avoid branch to branch | |
| 2598 emit_opcode( cbuf, 0x90); | |
| 2599 %} | |
| 2600 | |
| 2601 // fnstsw_ax(); | |
| 2602 // sahf(); | |
| 2603 // movl(dst, nan_result); | |
| 2604 // jcc(Assembler::parity, exit); | |
| 2605 // movl(dst, less_result); | |
| 2606 // jcc(Assembler::below, exit); | |
| 2607 // movl(dst, equal_result); | |
| 2608 // jcc(Assembler::equal, exit); | |
| 2609 // movl(dst, greater_result); | |
| 2610 | |
| 2611 // less_result = 1; | |
| 2612 // greater_result = -1; | |
| 2613 // equal_result = 0; | |
| 2614 // nan_result = -1; | |
| 2615 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2616 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2617 // fnstsw_ax(); |
| 2618 emit_opcode( cbuf, 0xDF); | |
| 2619 emit_opcode( cbuf, 0xE0); | |
| 2620 // sahf | |
| 2621 emit_opcode( cbuf, 0x9E); | |
| 2622 // movl(dst, nan_result); | |
| 2623 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2624 emit_d32( cbuf, -1 ); | |
| 2625 // jcc(Assembler::parity, exit); | |
| 2626 emit_opcode( cbuf, 0x7A ); | |
| 2627 emit_d8 ( cbuf, 0x13 ); | |
| 2628 // movl(dst, less_result); | |
| 2629 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2630 emit_d32( cbuf, -1 ); | |
| 2631 // jcc(Assembler::below, exit); | |
| 2632 emit_opcode( cbuf, 0x72 ); | |
| 2633 emit_d8 ( cbuf, 0x0C ); | |
| 2634 // movl(dst, equal_result); | |
| 2635 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2636 emit_d32( cbuf, 0 ); | |
| 2637 // jcc(Assembler::equal, exit); | |
| 2638 emit_opcode( cbuf, 0x74 ); | |
| 2639 emit_d8 ( cbuf, 0x05 ); | |
| 2640 // movl(dst, greater_result); | |
| 2641 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2642 emit_d32( cbuf, 1 ); | |
| 2643 %} | |
| 2644 | |
| 2645 | |
| 2646 // Compare the longs and set flags | |
| 2647 // BROKEN! Do Not use as-is | |
| 2648 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2649 // CMP $src1.hi,$src2.hi | |
| 2650 emit_opcode( cbuf, 0x3B ); | |
| 2651 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2652 // JNE,s done | |
| 2653 emit_opcode(cbuf,0x75); | |
| 2654 emit_d8(cbuf, 2 ); | |
| 2655 // CMP $src1.lo,$src2.lo | |
| 2656 emit_opcode( cbuf, 0x3B ); | |
| 2657 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2658 // done: | |
| 2659 %} | |
| 2660 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2661 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2662 // mov $dst.lo,$src |
| 2663 int dst_encoding = $dst$$reg; | |
| 2664 int src_encoding = $src$$reg; | |
| 2665 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2666 // mov $dst.hi,$src | |
| 2667 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2668 // sar $dst.hi,31 | |
| 2669 emit_opcode( cbuf, 0xC1 ); | |
| 2670 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2671 emit_d8(cbuf, 0x1F ); | |
| 2672 %} | |
| 2673 | |
| 2674 enc_class convert_long_double( eRegL src ) %{ | |
| 2675 // push $src.hi | |
| 2676 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2677 // push $src.lo | |
| 2678 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2679 // fild 64-bits at [SP] | |
| 2680 emit_opcode(cbuf,0xdf); | |
| 2681 emit_d8(cbuf, 0x6C); | |
| 2682 emit_d8(cbuf, 0x24); | |
| 2683 emit_d8(cbuf, 0x00); | |
| 2684 // pop stack | |
| 2685 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2686 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2687 emit_d8(cbuf, 0x8); | |
| 2688 %} | |
| 2689 | |
| 2690 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2691 // IMUL EDX:EAX,$src1 | |
| 2692 emit_opcode( cbuf, 0xF7 ); | |
| 2693 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2694 // SAR EDX,$cnt-32 | |
| 2695 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2696 if (shift_count > 0) { | |
| 2697 emit_opcode(cbuf, 0xC1); | |
| 2698 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2699 emit_d8(cbuf, shift_count); | |
| 2700 } | |
| 2701 %} | |
| 2702 | |
| 2703 // this version doesn't have add sp, 8 | |
| 2704 enc_class convert_long_double2( eRegL src ) %{ | |
| 2705 // push $src.hi | |
| 2706 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2707 // push $src.lo | |
| 2708 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2709 // fild 64-bits at [SP] | |
| 2710 emit_opcode(cbuf,0xdf); | |
| 2711 emit_d8(cbuf, 0x6C); | |
| 2712 emit_d8(cbuf, 0x24); | |
| 2713 emit_d8(cbuf, 0x00); | |
| 2714 %} | |
| 2715 | |
| 2716 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2717 // Basic idea: long = (long)int * (long)int | |
| 2718 // IMUL EDX:EAX, src | |
| 2719 emit_opcode( cbuf, 0xF7 ); | |
| 2720 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2721 %} | |
| 2722 | |
| 2723 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2724 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2725 // MUL EDX:EAX, src | |
| 2726 emit_opcode( cbuf, 0xF7 ); | |
| 2727 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2728 %} | |
| 2729 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2730 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2731 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2732 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2733 // MOV $tmp,$src.lo | |
| 2734 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2735 // IMUL $tmp,EDX | |
| 2736 emit_opcode( cbuf, 0x0F ); | |
| 2737 emit_opcode( cbuf, 0xAF ); | |
| 2738 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2739 // MOV EDX,$src.hi | |
| 2740 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2741 // IMUL EDX,EAX | |
| 2742 emit_opcode( cbuf, 0x0F ); | |
| 2743 emit_opcode( cbuf, 0xAF ); | |
| 2744 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2745 // ADD $tmp,EDX | |
| 2746 emit_opcode( cbuf, 0x03 ); | |
| 2747 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2748 // MUL EDX:EAX,$src.lo | |
| 2749 emit_opcode( cbuf, 0xF7 ); | |
| 2750 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2751 // ADD EDX,ESI | |
| 2752 emit_opcode( cbuf, 0x03 ); | |
| 2753 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2754 %} | |
| 2755 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2756 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2757 // Basic idea: lo(result) = lo(src * y_lo) |
| 2758 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2759 // IMUL $tmp,EDX,$src | |
| 2760 emit_opcode( cbuf, 0x6B ); | |
| 2761 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2762 emit_d8( cbuf, (int)$src$$constant ); | |
| 2763 // MOV EDX,$src | |
| 2764 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2765 emit_d32( cbuf, (int)$src$$constant ); | |
| 2766 // MUL EDX:EAX,EDX | |
| 2767 emit_opcode( cbuf, 0xF7 ); | |
| 2768 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2769 // ADD EDX,ESI | |
| 2770 emit_opcode( cbuf, 0x03 ); | |
| 2771 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2772 %} | |
| 2773 | |
| 2774 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2775 // PUSH src1.hi | |
| 2776 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2777 // PUSH src1.lo | |
| 2778 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2779 // PUSH src2.hi | |
| 2780 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2781 // PUSH src2.lo | |
| 2782 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2783 // CALL directly to the runtime | |
| 1748 | 2784 cbuf.set_insts_mark(); |
| 0 | 2785 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2786 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2787 // Restore stack |
| 2788 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2789 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2790 emit_d8(cbuf, 4*4); | |
| 2791 %} | |
| 2792 | |
| 2793 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2794 // PUSH src1.hi | |
| 2795 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2796 // PUSH src1.lo | |
| 2797 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2798 // PUSH src2.hi | |
| 2799 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2800 // PUSH src2.lo | |
| 2801 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2802 // CALL directly to the runtime | |
| 1748 | 2803 cbuf.set_insts_mark(); |
| 0 | 2804 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2805 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2806 // Restore stack |
| 2807 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2808 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2809 emit_d8(cbuf, 4*4); | |
| 2810 %} | |
| 2811 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2812 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2813 // MOV $tmp,$src.lo |
| 2814 emit_opcode(cbuf, 0x8B); | |
| 2815 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2816 // OR $tmp,$src.hi | |
| 2817 emit_opcode(cbuf, 0x0B); | |
| 2818 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2819 %} | |
| 2820 | |
| 2821 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2822 // CMP $src1.lo,$src2.lo | |
| 2823 emit_opcode( cbuf, 0x3B ); | |
| 2824 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2825 // JNE,s skip | |
| 2826 emit_cc(cbuf, 0x70, 0x5); | |
| 2827 emit_d8(cbuf,2); | |
| 2828 // CMP $src1.hi,$src2.hi | |
| 2829 emit_opcode( cbuf, 0x3B ); | |
| 2830 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2831 %} | |
| 2832 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2833 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2834 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2835 emit_opcode( cbuf, 0x3B ); | |
| 2836 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2837 // MOV $tmp,$src1.hi | |
| 2838 emit_opcode( cbuf, 0x8B ); | |
| 2839 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2840 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2841 emit_opcode( cbuf, 0x1B ); | |
| 2842 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2843 %} | |
| 2844 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2845 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2846 // XOR $tmp,$tmp |
| 2847 emit_opcode(cbuf,0x33); // XOR | |
| 2848 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2849 // CMP $tmp,$src.lo | |
| 2850 emit_opcode( cbuf, 0x3B ); | |
| 2851 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2852 // SBB $tmp,$src.hi | |
| 2853 emit_opcode( cbuf, 0x1B ); | |
| 2854 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2855 %} | |
| 2856 | |
| 2857 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2858 enc_class neg_long( eRegL dst ) %{ | |
| 2859 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2860 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2861 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2862 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2863 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2864 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2865 emit_d8 (cbuf,0 ); | |
| 2866 %} | |
| 2867 | |
| 2868 | |
| 2869 // Because the transitions from emitted code to the runtime | |
| 2870 // monitorenter/exit helper stubs are so slow it's critical that | |
| 2871 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 2872 // | |
| 2873 // See also: cmpFastLock and cmpFastUnlock. | |
| 2874 // | |
| 2875 // What follows is a specialized inline transliteration of the code | |
| 2876 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 2877 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 2878 // at startup-time. These methods would accept arguments as | |
| 2879 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 2880 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 2881 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 2882 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 2883 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 2884 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 2885 // Since the helper routines would be called from multiple synchronization | |
| 2886 // sites. | |
| 2887 // | |
| 2888 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 2889 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 2890 // to those specialized methods. That'd give us a mostly platform-independent | |
| 2891 // implementation that the JITs could optimize and inline at their pleasure. | |
| 2892 // Done correctly, the only time we'd need to cross to native could would be | |
| 2893 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 2894 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 2895 // (b) explicit barriers or fence operations. | |
| 2896 // | |
| 2897 // TODO: | |
| 2898 // | |
| 2899 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 2900 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 2901 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 2902 // the lock operators would typically be faster than reifying Self. | |
| 2903 // | |
| 2904 // * Ideally I'd define the primitives as: | |
| 2905 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 2906 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 2907 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 2908 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 2909 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 2910 // sub-optimal code near the synchronization site. | |
| 2911 // | |
| 2912 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 2913 // Alternately, use a better sp-proximity test. | |
| 2914 // | |
| 2915 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 2916 // Either one is sufficient to uniquely identify a thread. | |
| 2917 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 2918 // | |
| 2919 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 2920 // object is locked by the calling thread but the waitlist is empty. | |
| 2921 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 2922 // | |
| 2923 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 2924 // But beware of excessive branch density on AMD Opterons. | |
| 2925 // | |
| 2926 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 2927 // or failure of the fast-path. If the fast-path fails then we pass | |
| 2928 // control to the slow-path, typically in C. In Fast_Lock and | |
| 2929 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 2930 // will emit a conditional branch immediately after the node. | |
| 2931 // So we have branches to branches and lots of ICC.ZF games. | |
| 2932 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 2933 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 2934 // will drop through the node. ICC.ZF is undefined at exit. | |
| 2935 // In the case of failure, the node will branch directly to the | |
| 2936 // FailureLabel | |
| 2937 | |
| 2938 | |
| 2939 // obj: object to lock | |
| 2940 // box: on-stack box address (displaced header location) - KILLED | |
| 2941 // rax,: tmp -- KILLED | |
| 2942 // scr: tmp -- KILLED | |
| 2943 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 2944 | |
| 2945 Register objReg = as_Register($obj$$reg); | |
| 2946 Register boxReg = as_Register($box$$reg); | |
| 2947 Register tmpReg = as_Register($tmp$$reg); | |
| 2948 Register scrReg = as_Register($scr$$reg); | |
| 2949 | |
| 2950 // Ensure the register assignents are disjoint | |
| 2951 guarantee (objReg != boxReg, "") ; | |
| 2952 guarantee (objReg != tmpReg, "") ; | |
| 2953 guarantee (objReg != scrReg, "") ; | |
| 2954 guarantee (boxReg != tmpReg, "") ; | |
| 2955 guarantee (boxReg != scrReg, "") ; | |
| 2956 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 2957 | |
| 2958 MacroAssembler masm(&cbuf); | |
| 2959 | |
| 2960 if (_counters != NULL) { | |
| 2961 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 2962 } | |
| 2963 if (EmitSync & 1) { | |
| 2964 // set box->dhw = unused_mark (3) | |
| 304 | 2965 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 2966 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 2967 masm.cmpptr (rsp, (int32_t)0) ; | |
| 2968 } else | |
| 2969 if (EmitSync & 2) { | |
| 2970 Label DONE_LABEL ; | |
| 0 | 2971 if (UseBiasedLocking) { |
| 2972 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 2973 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 2974 } | |
| 2975 | |
| 304 | 2976 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 2977 masm.orptr (tmpReg, 0x1); | |
| 2978 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 2979 if (os::is_MP()) { masm.lock(); } |
| 304 | 2980 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2981 masm.jcc(Assembler::equal, DONE_LABEL); |
| 2982 // Recursive locking | |
| 304 | 2983 masm.subptr(tmpReg, rsp); |
| 2984 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 2985 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 2986 masm.bind(DONE_LABEL) ; | |
| 2987 } else { | |
| 2988 // Possible cases that we'll encounter in fast_lock | |
| 0 | 2989 // ------------------------------------------------ |
| 2990 // * Inflated | |
| 2991 // -- unlocked | |
| 2992 // -- Locked | |
| 2993 // = by self | |
| 2994 // = by other | |
| 2995 // * biased | |
| 2996 // -- by Self | |
| 2997 // -- by other | |
| 2998 // * neutral | |
| 2999 // * stack-locked | |
| 3000 // -- by self | |
| 3001 // = sp-proximity test hits | |
| 3002 // = sp-proximity test generates false-negative | |
| 3003 // -- by other | |
| 3004 // | |
| 3005 | |
| 3006 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3007 | |
| 3008 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3009 // order to reduce the number of conditional branches in the most common cases. | |
| 3010 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3011 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3012 // If this invariant is not held we risk exclusion (safety) failure. | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3013 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3014 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3015 } | |
| 3016 | |
| 304 | 3017 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3018 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3019 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3020 | |
| 3021 // Attempt stack-locking ... | |
| 304 | 3022 masm.orptr (tmpReg, 0x1); |
| 3023 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3024 if (os::is_MP()) { masm.lock(); } |
| 304 | 3025 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3026 if (_counters != NULL) { |
| 3027 masm.cond_inc32(Assembler::equal, | |
| 3028 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3029 } | |
| 3030 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3031 | |
| 3032 // Recursive locking | |
| 304 | 3033 masm.subptr(tmpReg, rsp); |
| 3034 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3035 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3036 if (_counters != NULL) { |
| 3037 masm.cond_inc32(Assembler::equal, | |
| 3038 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3039 } | |
| 3040 masm.jmp (DONE_LABEL) ; | |
| 3041 | |
| 3042 masm.bind (IsInflated) ; | |
| 3043 | |
| 3044 // The object is inflated. | |
| 3045 // | |
| 3046 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3047 // Use markOopDesc::monitor_value instead of "2". | |
| 3048 // use markOop::unused_mark() instead of "3". | |
| 3049 // The tmpReg value is an objectMonitor reference ORed with | |
| 3050 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3051 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3052 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3053 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3054 // | |
| 3055 // I use the latter as it avoids AGI stalls. | |
| 3056 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3057 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3058 // | |
| 3059 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3060 | |
| 3061 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3062 // We'd like to write: | |
| 3063 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3064 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3065 // additional latency as we have another ST in the store buffer that must drain. | |
| 3066 | |
| 304 | 3067 if (EmitSync & 8192) { |
| 3068 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3069 masm.get_thread (scrReg) ; | |
| 3070 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3071 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3072 if (os::is_MP()) { masm.lock(); } |
| 3073 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3074 } else | |
| 0 | 3075 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3076 masm.movptr(scrReg, boxReg) ; |
| 3077 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3078 |
| 3079 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3080 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3081 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3082 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3083 } |
| 3084 | |
| 3085 if ((EmitSync & 64) == 0) { | |
| 3086 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3087 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3088 } else { |
| 0 | 3089 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3090 // Test-And-CAS instead of CAS | |
| 304 | 3091 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3092 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3093 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3094 } |
| 3095 | |
| 3096 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3097 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3098 // to CAS the register containing Self into m->Owner. | |
| 3099 // But we don't have enough registers, so instead we can either try to CAS | |
| 3100 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3101 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3102 // (rsp or the address of the box) into m->owner is harmless. | |
| 3103 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3104 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3105 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3106 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3107 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3108 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3109 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3110 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3111 | |
| 3112 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3113 // We use the latter tactic. | |
| 0 | 3114 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3115 // If the CAS was successful ... | |
| 3116 // Self has acquired the lock | |
| 3117 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3118 // Intentional fall-through into DONE_LABEL ... | |
| 3119 } else { | |
| 304 | 3120 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3121 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3122 |
| 3123 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3124 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3125 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3126 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3127 } |
| 3128 | |
| 3129 if ((EmitSync & 64) == 0) { | |
| 3130 // Optimistic form | |
| 304 | 3131 masm.xorptr (tmpReg, tmpReg) ; |
| 3132 } else { | |
| 0 | 3133 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3134 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3135 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3136 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3137 } |
| 3138 | |
| 3139 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3140 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3141 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3142 masm.get_thread (scrReg) ; | |
| 3143 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3144 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3145 |
| 3146 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3147 // We use the latter tactic. | |
| 3148 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3149 // If the CAS was successful ... | |
| 3150 // Self has acquired the lock | |
| 3151 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3152 // Intentional fall-through into DONE_LABEL ... | |
| 3153 } | |
| 3154 | |
| 3155 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3156 // start of cache line by padding with NOPs. | |
| 3157 // See the AMD and Intel software optimization manuals for the | |
| 3158 // most efficient "long" NOP encodings. | |
| 3159 // Unfortunately none of our alignment mechanisms suffice. | |
| 3160 masm.bind(DONE_LABEL); | |
| 3161 | |
| 3162 // Avoid branch-to-branch on AMD processors | |
| 3163 // This appears to be superstition. | |
| 3164 if (EmitSync & 32) masm.nop() ; | |
| 3165 | |
| 3166 | |
| 3167 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3168 // Fast_Unlock uses the same protocol. | |
| 3169 // ZFlag == 1 -> Success | |
| 3170 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3171 } | |
| 3172 %} | |
| 3173 | |
| 3174 // obj: object to unlock | |
| 3175 // box: box address (displaced header location), killed. Must be EAX. | |
| 3176 // rbx,: killed tmp; cannot be obj nor box. | |
| 3177 // | |
| 3178 // Some commentary on balanced locking: | |
| 3179 // | |
| 3180 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3181 // Methods that don't have provably balanced locking are forced to run in the | |
| 3182 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3183 // The interpreter provides two properties: | |
| 3184 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3185 // objects acquired the current activation (frame). Recall that the | |
| 3186 // interpreter maintains an on-stack list of locks currently held by | |
| 3187 // a frame. | |
| 3188 // I2: If a method attempts to unlock an object that is not held by the | |
| 3189 // the frame the interpreter throws IMSX. | |
| 3190 // | |
| 3191 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3192 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3193 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3194 // is still locked by A(). | |
| 3195 // | |
| 3196 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3197 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3198 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3199 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3200 | |
| 3201 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3202 | |
| 3203 Register objReg = as_Register($obj$$reg); | |
| 3204 Register boxReg = as_Register($box$$reg); | |
| 3205 Register tmpReg = as_Register($tmp$$reg); | |
| 3206 | |
| 3207 guarantee (objReg != boxReg, "") ; | |
| 3208 guarantee (objReg != tmpReg, "") ; | |
| 3209 guarantee (boxReg != tmpReg, "") ; | |
| 3210 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3211 MacroAssembler masm(&cbuf); | |
| 3212 | |
| 3213 if (EmitSync & 4) { | |
| 3214 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3215 masm.cmpptr (rsp, 0) ; |
| 3216 } else | |
| 0 | 3217 if (EmitSync & 8) { |
| 3218 Label DONE_LABEL ; | |
| 3219 if (UseBiasedLocking) { | |
| 3220 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3221 } | |
| 3222 // classic stack-locking code ... | |
| 304 | 3223 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3224 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3225 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3226 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3227 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3228 masm.bind(DONE_LABEL); |
| 3229 } else { | |
| 3230 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3231 | |
| 3232 // Critically, the biased locking test must have precedence over | |
| 3233 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3234 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3235 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3236 } | |
| 304 | 3237 |
| 3238 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3239 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3240 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3241 | |
| 304 | 3242 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3243 masm.jccb (Assembler::zero, Stacked) ; |
| 3244 | |
| 3245 masm.bind (Inflated) ; | |
| 3246 // It's inflated. | |
| 3247 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3248 // as java routines or native JNI code called by this thread might | |
| 3249 // have released the lock. | |
| 3250 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3251 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3252 // | |
| 3253 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3254 // such as recursive enter and exit -- but we have to be wary of | |
| 3255 // I$ bloat, T$ effects and BP$ effects. | |
| 3256 // | |
| 3257 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3258 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3259 // we detect and recover from the race that the 1-0 exit admits. | |
| 3260 // | |
| 3261 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3262 // before it STs null into _owner, releasing the lock. Updates | |
| 3263 // to data protected by the critical section must be visible before | |
| 3264 // we drop the lock (and thus before any other thread could acquire | |
| 3265 // the lock and observe the fields protected by the lock). | |
| 3266 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3267 // each other and there's no need for an explicit barrier (fence). | |
| 3268 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3269 | |
| 3270 masm.get_thread (boxReg) ; | |
| 2479 | 3271 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 304 | 3272 // prefetchw [ebx + Offset(_owner)-2] |
| 3273 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3274 } |
| 3275 | |
| 3276 // Note that we could employ various encoding schemes to reduce | |
| 3277 // the number of loads below (currently 4) to just 2 or 3. | |
| 3278 // Refer to the comments in synchronizer.cpp. | |
| 3279 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3280 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3281 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3282 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3283 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3284 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3285 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3286 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3287 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3288 masm.jmpb (DONE_LABEL) ; |
| 3289 } else { | |
| 3290 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3291 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3292 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3293 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3294 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3295 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3296 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3297 masm.jmpb (DONE_LABEL) ; |
| 0 | 3298 } |
| 3299 | |
| 3300 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3301 // contended applications and contended synchronization microbenchmarks. | |
| 3302 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3303 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3304 // with an equal number of never-executed NOPs results in the same regression. | |
| 3305 // We leave it off by default. | |
| 3306 | |
| 3307 if ((EmitSync & 65536) != 0) { | |
| 3308 Label LSuccess, LGoSlowPath ; | |
| 3309 | |
| 3310 masm.bind (CheckSucc) ; | |
| 3311 | |
| 3312 // Optional pre-test ... it's safe to elide this | |
| 304 | 3313 if ((EmitSync & 16) == 0) { |
| 3314 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3315 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3316 } |
| 3317 | |
| 3318 // We have a classic Dekker-style idiom: | |
| 3319 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3320 // There are a number of ways to implement the barrier: | |
| 3321 // (1) lock:andl &m->_owner, 0 | |
| 3322 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3323 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3324 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3325 // (2) If supported, an explicit MFENCE is appealing. | |
| 3326 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3327 // particularly if the write-buffer is full as might be the case if | |
| 3328 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3329 // In more modern implementations MFENCE appears faster, however. | |
| 3330 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3331 // The $lines underlying the top-of-stack should be in M-state. | |
| 3332 // The locked add instruction is serializing, of course. | |
| 3333 // (4) Use xchg, which is serializing | |
| 3334 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3335 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3336 // The integer condition codes will tell us if succ was 0. | |
| 3337 // Since _succ and _owner should reside in the same $line and | |
| 3338 // we just stored into _owner, it's likely that the $line | |
| 3339 // remains in M-state for the lock:orl. | |
| 3340 // | |
| 3341 // We currently use (3), although it's likely that switching to (2) | |
| 3342 // is correct for the future. | |
| 304 | 3343 |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3344 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3345 if (os::is_MP()) { |
| 3346 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3347 masm.mfence(); | |
| 3348 } else { | |
| 3349 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3350 } |
| 3351 } | |
| 3352 // Ratify _succ remains non-null | |
| 304 | 3353 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3354 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3355 | |
| 3356 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3357 if (os::is_MP()) { masm.lock(); } |
| 304 | 3358 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3359 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3360 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3361 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3362 // non-null to non=null | |
| 3363 masm.get_thread (boxReg) ; | |
| 304 | 3364 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3365 // Intentional fall-through into LGoSlowPath ... |
| 3366 | |
| 304 | 3367 masm.bind (LGoSlowPath) ; |
| 3368 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3369 masm.jmpb (DONE_LABEL) ; | |
| 3370 | |
| 3371 masm.bind (LSuccess) ; | |
| 3372 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3373 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3374 } |
| 3375 | |
| 3376 masm.bind (Stacked) ; | |
| 3377 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3378 // It must be stack-locked. | |
| 3379 // Try to reset the header to displaced header. | |
| 3380 // The "box" value on the stack is stable, so we can reload | |
| 3381 // and be assured we observe the same value as above. | |
| 304 | 3382 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3383 if (os::is_MP()) { masm.lock(); } |
| 304 | 3384 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3385 // Intention fall-thru into DONE_LABEL |
| 3386 | |
| 3387 | |
| 3388 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3389 // start of cache line by padding with NOPs. | |
| 3390 // See the AMD and Intel software optimization manuals for the | |
| 3391 // most efficient "long" NOP encodings. | |
| 3392 // Unfortunately none of our alignment mechanisms suffice. | |
| 3393 if ((EmitSync & 65536) == 0) { | |
| 3394 masm.bind (CheckSucc) ; | |
| 3395 } | |
| 3396 masm.bind(DONE_LABEL); | |
| 3397 | |
| 3398 // Avoid branch to branch on AMD processors | |
| 3399 if (EmitSync & 32768) { masm.nop() ; } | |
| 3400 } | |
| 3401 %} | |
| 3402 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3403 |
| 0 | 3404 enc_class enc_pop_rdx() %{ |
| 3405 emit_opcode(cbuf,0x5A); | |
| 3406 %} | |
| 3407 | |
| 3408 enc_class enc_rethrow() %{ | |
| 1748 | 3409 cbuf.set_insts_mark(); |
| 0 | 3410 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 3411 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 3412 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 3413 %} | |
| 3414 | |
| 3415 | |
| 3416 // Convert a double to an int. Java semantics require we do complex | |
| 3417 // manglelations in the corner cases. So we set the rounding mode to | |
| 3418 // 'zero', store the darned double down as an int, and reset the | |
| 3419 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3420 // patches up the correct value directly to the stack. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3421 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 3422 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 3423 // exceptions here, so that a NAN or other corner-case value will | |
| 3424 // thrown an exception (but normal values get converted at full speed). | |
| 3425 // However, I2C adapters and other float-stack manglers leave pending | |
| 3426 // invalid-op exceptions hanging. We would have to clear them before | |
| 3427 // enabling them and that is more expensive than just testing for the | |
| 3428 // invalid value Intel stores down in the corner cases. | |
| 3429 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3430 emit_opcode(cbuf,0x2D); | |
| 3431 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3432 // Allocate a word | |
| 3433 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3434 emit_opcode(cbuf,0xEC); | |
| 3435 emit_d8(cbuf,0x04); | |
| 3436 // Encoding assumes a double has been pushed into FPR0. | |
| 3437 // Store down the double as an int, popping the FPU stack | |
| 3438 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3439 emit_opcode(cbuf,0x1C); | |
| 3440 emit_d8(cbuf,0x24); | |
| 3441 // Restore the rounding mode; mask the exception | |
| 3442 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3443 emit_opcode(cbuf,0x2D); | |
| 3444 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3445 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3446 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3447 | |
| 3448 // Load the converted int; adjust CPU stack | |
| 3449 emit_opcode(cbuf,0x58); // POP EAX | |
| 3450 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3451 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3452 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3453 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3454 // Push src onto stack slow-path | |
| 3455 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3456 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3457 // CALL directly to the runtime | |
| 1748 | 3458 cbuf.set_insts_mark(); |
| 0 | 3459 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3460 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3461 // Carry on here... |
| 3462 %} | |
| 3463 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3464 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 3465 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 3466 emit_opcode(cbuf,0x2D); | |
| 3467 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3468 // Allocate a word | |
| 3469 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3470 emit_opcode(cbuf,0xEC); | |
| 3471 emit_d8(cbuf,0x08); | |
| 3472 // Encoding assumes a double has been pushed into FPR0. | |
| 3473 // Store down the double as a long, popping the FPU stack | |
| 3474 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3475 emit_opcode(cbuf,0x3C); | |
| 3476 emit_d8(cbuf,0x24); | |
| 3477 // Restore the rounding mode; mask the exception | |
| 3478 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3479 emit_opcode(cbuf,0x2D); | |
| 3480 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3481 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3482 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3483 | |
| 3484 // Load the converted int; adjust CPU stack | |
| 3485 emit_opcode(cbuf,0x58); // POP EAX | |
| 3486 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3487 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3488 emit_d8 (cbuf,0xFA); // rdx | |
| 3489 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3490 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3491 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3492 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3493 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3494 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3495 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3496 // Push src onto stack slow-path | |
| 3497 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3498 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3499 // CALL directly to the runtime | |
| 1748 | 3500 cbuf.set_insts_mark(); |
| 0 | 3501 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3502 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3503 // Carry on here... |
| 3504 %} | |
| 3505 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3506 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3507 // Operand was loaded from memory into fp ST (stack top) |
| 3508 // FMUL ST,$src /* D8 C8+i */ | |
| 3509 emit_opcode(cbuf, 0xD8); | |
| 3510 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3511 %} | |
| 3512 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3513 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3514 // FADDP ST,src2 /* D8 C0+i */ |
| 3515 emit_opcode(cbuf, 0xD8); | |
| 3516 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3517 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3518 %} | |
| 3519 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3520 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3521 // FADDP src2,ST /* DE C0+i */ |
| 3522 emit_opcode(cbuf, 0xDE); | |
| 3523 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3524 %} | |
| 3525 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3526 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3527 // Operand has been loaded into fp ST (stack top) |
| 3528 // FSUB ST,$src1 | |
| 3529 emit_opcode(cbuf, 0xD8); | |
| 3530 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3531 | |
| 3532 // FDIV | |
| 3533 emit_opcode(cbuf, 0xD8); | |
| 3534 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3535 %} | |
| 3536 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3537 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3538 // Operand was loaded from memory into fp ST (stack top) |
| 3539 // FADD ST,$src /* D8 C0+i */ | |
| 3540 emit_opcode(cbuf, 0xD8); | |
| 3541 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3542 | |
| 3543 // FMUL ST,src2 /* D8 C*+i */ | |
| 3544 emit_opcode(cbuf, 0xD8); | |
| 3545 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3546 %} | |
| 3547 | |
| 3548 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3549 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3550 // Operand was loaded from memory into fp ST (stack top) |
| 3551 // FADD ST,$src /* D8 C0+i */ | |
| 3552 emit_opcode(cbuf, 0xD8); | |
| 3553 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3554 | |
| 3555 // FMULP src2,ST /* DE C8+i */ | |
| 3556 emit_opcode(cbuf, 0xDE); | |
| 3557 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3558 %} | |
| 3559 | |
| 3560 // Atomically load the volatile long | |
| 3561 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3562 emit_opcode(cbuf,0xDF); | |
| 3563 int rm_byte_opcode = 0x05; | |
| 3564 int base = $mem$$base; | |
| 3565 int index = $mem$$index; | |
| 3566 int scale = $mem$$scale; | |
| 3567 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3568 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3569 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3570 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3571 %} | |
| 3572 | |
| 3573 // Volatile Store Long. Must be atomic, so move it into | |
| 3574 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3575 // target address before the store (for null-ptr checks) | |
| 3576 // so the memory operand is used twice in the encoding. | |
| 3577 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3578 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3579 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3580 emit_opcode(cbuf,0xDF); |
| 3581 int rm_byte_opcode = 0x07; | |
| 3582 int base = $mem$$base; | |
| 3583 int index = $mem$$index; | |
| 3584 int scale = $mem$$scale; | |
| 3585 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3586 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3587 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3588 %} |
| 3589 | |
| 3590 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3591 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3592 // in the process | |
| 3593 // We current use TESTL [spp],EDI | |
| 3594 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3595 | |
| 3596 enc_class Safepoint_Poll() %{ | |
| 1748 | 3597 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3598 emit_opcode(cbuf,0x85); |
| 3599 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3600 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3601 %} | |
| 3602 %} | |
| 3603 | |
| 3604 | |
| 3605 //----------FRAME-------------------------------------------------------------- | |
| 3606 // Definition of frame structure and management information. | |
| 3607 // | |
| 3608 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3609 // | (to get allocators register number | |
| 3610 // G Owned by | | v add OptoReg::stack0()) | |
| 3611 // r CALLER | | | |
| 3612 // o | +--------+ pad to even-align allocators stack-slot | |
| 3613 // w V | pad0 | numbers; owned by CALLER | |
| 3614 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3615 // h ^ | in | 5 | |
| 3616 // | | args | 4 Holes in incoming args owned by SELF | |
| 3617 // | | | | 3 | |
| 3618 // | | +--------+ | |
| 3619 // V | | old out| Empty on Intel, window on Sparc | |
| 3620 // | old |preserve| Must be even aligned. | |
| 3621 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3622 // | | in | 3 area for Intel ret address | |
| 3623 // Owned by |preserve| Empty on Sparc. | |
| 3624 // SELF +--------+ | |
| 3625 // | | pad2 | 2 pad to align old SP | |
| 3626 // | +--------+ 1 | |
| 3627 // | | locks | 0 | |
| 3628 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3629 // | | pad1 | 11 pad to align new SP | |
| 3630 // | +--------+ | |
| 3631 // | | | 10 | |
| 3632 // | | spills | 9 spills | |
| 3633 // V | | 8 (pad0 slot for callee) | |
| 3634 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3635 // ^ | out | 7 | |
| 3636 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3637 // Owned by +--------+ | |
| 3638 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3639 // | new |preserve| Must be even-aligned. | |
| 3640 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3641 // | | | | |
| 3642 // | |
| 3643 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3644 // known from SELF's arguments and the Java calling convention. | |
| 3645 // Region 6-7 is determined per call site. | |
| 3646 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3647 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3648 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3649 // incoming area, as the Java calling convention is completely under | |
| 3650 // the control of the AD file. Doubles can be sorted and packed to | |
| 3651 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3652 // varargs C calling conventions. | |
| 3653 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3654 // even aligned with pad0 as needed. | |
| 3655 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3656 // region 6-11 is even aligned; it may be padded out more so that | |
| 3657 // the region from SP to FP meets the minimum stack alignment. | |
| 3658 | |
| 3659 frame %{ | |
| 3660 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3661 stack_direction(TOWARDS_LOW); | |
| 3662 | |
| 3663 // These three registers define part of the calling convention | |
| 3664 // between compiled code and the interpreter. | |
| 3665 inline_cache_reg(EAX); // Inline Cache Register | |
| 3666 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3667 | |
| 3668 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3669 cisc_spilling_operand_name(indOffset32); | |
| 3670 | |
| 3671 // Number of stack slots consumed by locking an object | |
| 3672 sync_stack_slots(1); | |
| 3673 | |
| 3674 // Compiled code's Frame Pointer | |
| 3675 frame_pointer(ESP); | |
| 3676 // Interpreter stores its frame pointer in a register which is | |
| 3677 // stored to the stack by I2CAdaptors. | |
| 3678 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3679 interpreter_frame_pointer(EBP); | |
| 3680 | |
| 3681 // Stack alignment requirement | |
| 3682 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3683 stack_alignment(StackAlignmentInBytes); | |
| 3684 | |
| 3685 // Number of stack slots between incoming argument block and the start of | |
| 3686 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3687 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3688 // return address and one for rbp, (must save rbp) | |
| 3689 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3690 | |
| 3691 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3692 // for calls to C. Supports the var-args backing area for register parms. | |
| 3693 varargs_C_out_slots_killed(0); | |
| 3694 | |
| 3695 // The after-PROLOG location of the return address. Location of | |
| 3696 // return address specifies a type (REG or STACK) and a number | |
| 3697 // representing the register number (i.e. - use a register name) or | |
| 3698 // stack slot. | |
| 3699 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3700 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3701 return_addr(STACK - 1 + | |
| 4950 | 3702 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3703 Compile::current()->fixed_slots()), | |
| 3704 stack_alignment_in_slots())); | |
| 0 | 3705 |
| 3706 // Body of function which returns an integer array locating | |
| 3707 // arguments either in registers or in stack slots. Passed an array | |
| 3708 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3709 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3710 // arguments for a CALLEE. Incoming stack arguments are | |
| 3711 // automatically biased by the preserve_stack_slots field above. | |
| 3712 calling_convention %{ | |
| 3713 // No difference between ingoing/outgoing just pass false | |
| 3714 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3715 %} | |
| 3716 | |
| 3717 | |
| 3718 // Body of function which returns an integer array locating | |
| 3719 // arguments either in registers or in stack slots. Passed an array | |
| 3720 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3721 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3722 // arguments for a CALLEE. Incoming stack arguments are | |
| 3723 // automatically biased by the preserve_stack_slots field above. | |
| 3724 c_calling_convention %{ | |
| 3725 // This is obviously always outgoing | |
|
14416
6a936747b569
8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents:
10169
diff
changeset
|
3726 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3727 %} |
| 3728 | |
| 3729 // Location of C & interpreter return values | |
| 3730 c_return_value %{ | |
| 3731 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3732 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3733 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3734 |
| 3735 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3736 // that C functions return float and double results in XMM0. | |
| 3737 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3738 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3739 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3740 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3741 |
| 3742 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3743 %} | |
| 3744 | |
| 3745 // Location of return values | |
| 3746 return_value %{ | |
| 3747 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3748 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3749 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3750 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3751 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3752 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3753 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3754 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3755 %} | |
| 3756 | |
| 3757 %} | |
| 3758 | |
| 3759 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3760 //----------Operand Attributes------------------------------------------------- | |
| 3761 op_attrib op_cost(0); // Required cost attribute | |
| 3762 | |
| 3763 //----------Instruction Attributes--------------------------------------------- | |
| 3764 ins_attrib ins_cost(100); // Required cost attribute | |
| 3765 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3766 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3767 // non-matching short branch variant of some | |
| 3768 // long branch? | |
| 3769 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3770 // specifies the alignment that some part of the instruction (not | |
| 3771 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3772 // function must be provided for the instruction | |
| 3773 | |
| 3774 //----------OPERANDS----------------------------------------------------------- | |
| 3775 // Operand definitions must precede instruction definitions for correct parsing | |
| 3776 // in the ADLC because operands constitute user defined types which are used in | |
| 3777 // instruction definitions. | |
| 3778 | |
| 3779 //----------Simple Operands---------------------------------------------------- | |
| 3780 // Immediate Operands | |
| 3781 // Integer Immediate | |
| 3782 operand immI() %{ | |
| 3783 match(ConI); | |
| 3784 | |
| 3785 op_cost(10); | |
| 3786 format %{ %} | |
| 3787 interface(CONST_INTER); | |
| 3788 %} | |
| 3789 | |
| 3790 // Constant for test vs zero | |
| 3791 operand immI0() %{ | |
| 3792 predicate(n->get_int() == 0); | |
| 3793 match(ConI); | |
| 3794 | |
| 3795 op_cost(0); | |
| 3796 format %{ %} | |
| 3797 interface(CONST_INTER); | |
| 3798 %} | |
| 3799 | |
| 3800 // Constant for increment | |
| 3801 operand immI1() %{ | |
| 3802 predicate(n->get_int() == 1); | |
| 3803 match(ConI); | |
| 3804 | |
| 3805 op_cost(0); | |
| 3806 format %{ %} | |
| 3807 interface(CONST_INTER); | |
| 3808 %} | |
| 3809 | |
| 3810 // Constant for decrement | |
| 3811 operand immI_M1() %{ | |
| 3812 predicate(n->get_int() == -1); | |
| 3813 match(ConI); | |
| 3814 | |
| 3815 op_cost(0); | |
| 3816 format %{ %} | |
| 3817 interface(CONST_INTER); | |
| 3818 %} | |
| 3819 | |
| 3820 // Valid scale values for addressing modes | |
| 3821 operand immI2() %{ | |
| 3822 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3823 match(ConI); | |
| 3824 | |
| 3825 format %{ %} | |
| 3826 interface(CONST_INTER); | |
| 3827 %} | |
| 3828 | |
| 3829 operand immI8() %{ | |
| 3830 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3831 match(ConI); | |
| 3832 | |
| 3833 op_cost(5); | |
| 3834 format %{ %} | |
| 3835 interface(CONST_INTER); | |
| 3836 %} | |
| 3837 | |
| 3838 operand immI16() %{ | |
| 3839 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3840 match(ConI); | |
| 3841 | |
| 3842 op_cost(10); | |
| 3843 format %{ %} | |
| 3844 interface(CONST_INTER); | |
| 3845 %} | |
| 3846 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3847 // Int Immediate non-negative |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3848 operand immU31() |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3849 %{ |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3850 predicate(n->get_int() >= 0); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3851 match(ConI); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3852 |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3853 op_cost(0); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3854 format %{ %} |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3855 interface(CONST_INTER); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3856 %} |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3857 |
| 0 | 3858 // Constant for long shifts |
| 3859 operand immI_32() %{ | |
| 3860 predicate( n->get_int() == 32 ); | |
| 3861 match(ConI); | |
| 3862 | |
| 3863 op_cost(0); | |
| 3864 format %{ %} | |
| 3865 interface(CONST_INTER); | |
| 3866 %} | |
| 3867 | |
| 3868 operand immI_1_31() %{ | |
| 3869 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3870 match(ConI); | |
| 3871 | |
| 3872 op_cost(0); | |
| 3873 format %{ %} | |
| 3874 interface(CONST_INTER); | |
| 3875 %} | |
| 3876 | |
| 3877 operand immI_32_63() %{ | |
| 3878 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3879 match(ConI); | |
| 3880 op_cost(0); | |
| 3881 | |
| 3882 format %{ %} | |
| 3883 interface(CONST_INTER); | |
| 3884 %} | |
| 3885 | |
| 219 | 3886 operand immI_1() %{ |
| 3887 predicate( n->get_int() == 1 ); | |
| 3888 match(ConI); | |
| 3889 | |
| 3890 op_cost(0); | |
| 3891 format %{ %} | |
| 3892 interface(CONST_INTER); | |
| 3893 %} | |
| 3894 | |
| 3895 operand immI_2() %{ | |
| 3896 predicate( n->get_int() == 2 ); | |
| 3897 match(ConI); | |
| 3898 | |
| 3899 op_cost(0); | |
| 3900 format %{ %} | |
| 3901 interface(CONST_INTER); | |
| 3902 %} | |
| 3903 | |
| 3904 operand immI_3() %{ | |
| 3905 predicate( n->get_int() == 3 ); | |
| 3906 match(ConI); | |
| 3907 | |
| 3908 op_cost(0); | |
| 3909 format %{ %} | |
| 3910 interface(CONST_INTER); | |
| 3911 %} | |
| 3912 | |
| 0 | 3913 // Pointer Immediate |
| 3914 operand immP() %{ | |
| 3915 match(ConP); | |
| 3916 | |
| 3917 op_cost(10); | |
| 3918 format %{ %} | |
| 3919 interface(CONST_INTER); | |
| 3920 %} | |
| 3921 | |
| 3922 // NULL Pointer Immediate | |
| 3923 operand immP0() %{ | |
| 3924 predicate( n->get_ptr() == 0 ); | |
| 3925 match(ConP); | |
| 3926 op_cost(0); | |
| 3927 | |
| 3928 format %{ %} | |
| 3929 interface(CONST_INTER); | |
| 3930 %} | |
| 3931 | |
| 3932 // Long Immediate | |
| 3933 operand immL() %{ | |
| 3934 match(ConL); | |
| 3935 | |
| 3936 op_cost(20); | |
| 3937 format %{ %} | |
| 3938 interface(CONST_INTER); | |
| 3939 %} | |
| 3940 | |
| 3941 // Long Immediate zero | |
| 3942 operand immL0() %{ | |
| 3943 predicate( n->get_long() == 0L ); | |
| 3944 match(ConL); | |
| 3945 op_cost(0); | |
| 3946 | |
| 3947 format %{ %} | |
| 3948 interface(CONST_INTER); | |
| 3949 %} | |
| 3950 | |
| 403 | 3951 // Long Immediate zero |
| 3952 operand immL_M1() %{ | |
| 3953 predicate( n->get_long() == -1L ); | |
| 3954 match(ConL); | |
| 3955 op_cost(0); | |
| 3956 | |
| 3957 format %{ %} | |
| 3958 interface(CONST_INTER); | |
| 3959 %} | |
| 3960 | |
| 0 | 3961 // Long immediate from 0 to 127. |
| 3962 // Used for a shorter form of long mul by 10. | |
| 3963 operand immL_127() %{ | |
| 3964 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3965 match(ConL); | |
| 3966 op_cost(0); | |
| 3967 | |
| 3968 format %{ %} | |
| 3969 interface(CONST_INTER); | |
| 3970 %} | |
| 3971 | |
| 3972 // Long Immediate: low 32-bit mask | |
| 3973 operand immL_32bits() %{ | |
| 3974 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3975 match(ConL); | |
| 3976 op_cost(0); | |
| 3977 | |
| 3978 format %{ %} | |
| 3979 interface(CONST_INTER); | |
| 3980 %} | |
| 3981 | |
| 3982 // Long Immediate: low 32-bit mask | |
| 3983 operand immL32() %{ | |
| 3984 predicate(n->get_long() == (int)(n->get_long())); | |
| 3985 match(ConL); | |
| 3986 op_cost(20); | |
| 3987 | |
| 3988 format %{ %} | |
| 3989 interface(CONST_INTER); | |
| 3990 %} | |
| 3991 | |
| 3992 //Double Immediate zero | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3993 operand immDPR0() %{ |
| 0 | 3994 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3995 // bug that generates code such that NaNs compare equal to 0.0 | |
| 3996 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 3997 match(ConD); | |
| 3998 | |
| 3999 op_cost(5); | |
| 4000 format %{ %} | |
| 4001 interface(CONST_INTER); | |
| 4002 %} | |
| 4003 | |
| 2008 | 4004 // Double Immediate one |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4005 operand immDPR1() %{ |
| 0 | 4006 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 4007 match(ConD); | |
| 4008 | |
| 4009 op_cost(5); | |
| 4010 format %{ %} | |
| 4011 interface(CONST_INTER); | |
| 4012 %} | |
| 4013 | |
| 4014 // Double Immediate | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4015 operand immDPR() %{ |
| 0 | 4016 predicate(UseSSE<=1); |
| 4017 match(ConD); | |
| 4018 | |
| 4019 op_cost(5); | |
| 4020 format %{ %} | |
| 4021 interface(CONST_INTER); | |
| 4022 %} | |
| 4023 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4024 operand immD() %{ |
| 0 | 4025 predicate(UseSSE>=2); |
| 4026 match(ConD); | |
| 4027 | |
| 4028 op_cost(5); | |
| 4029 format %{ %} | |
| 4030 interface(CONST_INTER); | |
| 4031 %} | |
| 4032 | |
| 4033 // Double Immediate zero | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4034 operand immD0() %{ |
| 0 | 4035 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4036 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4037 // compare equal to -0.0. | |
| 4038 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4039 match(ConD); | |
| 4040 | |
| 4041 format %{ %} | |
| 4042 interface(CONST_INTER); | |
| 4043 %} | |
| 4044 | |
| 4045 // Float Immediate zero | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4046 operand immFPR0() %{ |
| 2008 | 4047 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 4048 match(ConF); | |
| 4049 | |
| 4050 op_cost(5); | |
| 4051 format %{ %} | |
| 4052 interface(CONST_INTER); | |
| 4053 %} | |
| 4054 | |
| 4055 // Float Immediate one | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4056 operand immFPR1() %{ |
| 2008 | 4057 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 4058 match(ConF); |
| 4059 | |
| 4060 op_cost(5); | |
| 4061 format %{ %} | |
| 4062 interface(CONST_INTER); | |
| 4063 %} | |
| 4064 | |
| 4065 // Float Immediate | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4066 operand immFPR() %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4067 predicate( UseSSE == 0 ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4068 match(ConF); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4069 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4070 op_cost(5); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4071 format %{ %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4072 interface(CONST_INTER); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4073 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4074 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4075 // Float Immediate |
| 0 | 4076 operand immF() %{ |
| 4077 predicate(UseSSE >= 1); | |
| 4078 match(ConF); | |
| 4079 | |
| 4080 op_cost(5); | |
| 4081 format %{ %} | |
| 4082 interface(CONST_INTER); | |
| 4083 %} | |
| 4084 | |
| 4085 // Float Immediate zero. Zero and not -0.0 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4086 operand immF0() %{ |
| 0 | 4087 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 4088 match(ConF); | |
| 4089 | |
| 4090 op_cost(5); | |
| 4091 format %{ %} | |
| 4092 interface(CONST_INTER); | |
| 4093 %} | |
| 4094 | |
| 4095 // Immediates for special shifts (sign extend) | |
| 4096 | |
| 4097 // Constants for increment | |
| 4098 operand immI_16() %{ | |
| 4099 predicate( n->get_int() == 16 ); | |
| 4100 match(ConI); | |
| 4101 | |
| 4102 format %{ %} | |
| 4103 interface(CONST_INTER); | |
| 4104 %} | |
| 4105 | |
| 4106 operand immI_24() %{ | |
| 4107 predicate( n->get_int() == 24 ); | |
| 4108 match(ConI); | |
| 4109 | |
| 4110 format %{ %} | |
| 4111 interface(CONST_INTER); | |
| 4112 %} | |
| 4113 | |
| 4114 // Constant for byte-wide masking | |
| 4115 operand immI_255() %{ | |
| 4116 predicate( n->get_int() == 255 ); | |
| 4117 match(ConI); | |
| 4118 | |
| 4119 format %{ %} | |
| 4120 interface(CONST_INTER); | |
| 4121 %} | |
| 4122 | |
| 785 | 4123 // Constant for short-wide masking |
| 4124 operand immI_65535() %{ | |
| 4125 predicate(n->get_int() == 65535); | |
| 4126 match(ConI); | |
| 4127 | |
| 4128 format %{ %} | |
| 4129 interface(CONST_INTER); | |
| 4130 %} | |
| 4131 | |
| 0 | 4132 // Register Operands |
| 4133 // Integer Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4134 operand rRegI() %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4135 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4136 match(RegI); |
| 4137 match(xRegI); | |
| 4138 match(eAXRegI); | |
| 4139 match(eBXRegI); | |
| 4140 match(eCXRegI); | |
| 4141 match(eDXRegI); | |
| 4142 match(eDIRegI); | |
| 4143 match(eSIRegI); | |
| 4144 | |
| 4145 format %{ %} | |
| 4146 interface(REG_INTER); | |
| 4147 %} | |
| 4148 | |
| 4149 // Subset of Integer Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4150 operand xRegI(rRegI reg) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4151 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 4152 match(reg); |
| 4153 match(eAXRegI); | |
| 4154 match(eBXRegI); | |
| 4155 match(eCXRegI); | |
| 4156 match(eDXRegI); | |
| 4157 | |
| 4158 format %{ %} | |
| 4159 interface(REG_INTER); | |
| 4160 %} | |
| 4161 | |
| 4162 // Special Registers | |
| 4163 operand eAXRegI(xRegI reg) %{ | |
| 4164 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4165 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4166 match(rRegI); |
| 0 | 4167 |
| 4168 format %{ "EAX" %} | |
| 4169 interface(REG_INTER); | |
| 4170 %} | |
| 4171 | |
| 4172 // Special Registers | |
| 4173 operand eBXRegI(xRegI reg) %{ | |
| 4174 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4175 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4176 match(rRegI); |
| 0 | 4177 |
| 4178 format %{ "EBX" %} | |
| 4179 interface(REG_INTER); | |
| 4180 %} | |
| 4181 | |
| 4182 operand eCXRegI(xRegI reg) %{ | |
| 4183 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4184 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4185 match(rRegI); |
| 0 | 4186 |
| 4187 format %{ "ECX" %} | |
| 4188 interface(REG_INTER); | |
| 4189 %} | |
| 4190 | |
| 4191 operand eDXRegI(xRegI reg) %{ | |
| 4192 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4193 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4194 match(rRegI); |
| 0 | 4195 |
| 4196 format %{ "EDX" %} | |
| 4197 interface(REG_INTER); | |
| 4198 %} | |
| 4199 | |
| 4200 operand eDIRegI(xRegI reg) %{ | |
| 4201 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4202 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4203 match(rRegI); |
| 0 | 4204 |
| 4205 format %{ "EDI" %} | |
| 4206 interface(REG_INTER); | |
| 4207 %} | |
| 4208 | |
| 4209 operand naxRegI() %{ | |
| 4210 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4211 match(RegI); | |
| 4212 match(eCXRegI); | |
| 4213 match(eDXRegI); | |
| 4214 match(eSIRegI); | |
| 4215 match(eDIRegI); | |
| 4216 | |
| 4217 format %{ %} | |
| 4218 interface(REG_INTER); | |
| 4219 %} | |
| 4220 | |
| 4221 operand nadxRegI() %{ | |
| 4222 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4223 match(RegI); | |
| 4224 match(eBXRegI); | |
| 4225 match(eCXRegI); | |
| 4226 match(eSIRegI); | |
| 4227 match(eDIRegI); | |
| 4228 | |
| 4229 format %{ %} | |
| 4230 interface(REG_INTER); | |
| 4231 %} | |
| 4232 | |
| 4233 operand ncxRegI() %{ | |
| 4234 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4235 match(RegI); | |
| 4236 match(eAXRegI); | |
| 4237 match(eDXRegI); | |
| 4238 match(eSIRegI); | |
| 4239 match(eDIRegI); | |
| 4240 | |
| 4241 format %{ %} | |
| 4242 interface(REG_INTER); | |
| 4243 %} | |
| 4244 | |
| 4245 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4246 // // | |
| 4247 operand eSIRegI(xRegI reg) %{ | |
| 4248 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4249 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4250 match(rRegI); |
| 0 | 4251 |
| 4252 format %{ "ESI" %} | |
| 4253 interface(REG_INTER); | |
| 4254 %} | |
| 4255 | |
| 4256 // Pointer Register | |
| 4257 operand anyRegP() %{ | |
| 4258 constraint(ALLOC_IN_RC(any_reg)); | |
| 4259 match(RegP); | |
| 4260 match(eAXRegP); | |
| 4261 match(eBXRegP); | |
| 4262 match(eCXRegP); | |
| 4263 match(eDIRegP); | |
| 4264 match(eRegP); | |
| 4265 | |
| 4266 format %{ %} | |
| 4267 interface(REG_INTER); | |
| 4268 %} | |
| 4269 | |
| 4270 operand eRegP() %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4271 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4272 match(RegP); |
| 4273 match(eAXRegP); | |
| 4274 match(eBXRegP); | |
| 4275 match(eCXRegP); | |
| 4276 match(eDIRegP); | |
| 4277 | |
| 4278 format %{ %} | |
| 4279 interface(REG_INTER); | |
| 4280 %} | |
| 4281 | |
| 4282 // On windows95, EBP is not safe to use for implicit null tests. | |
| 4283 operand eRegP_no_EBP() %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4284 constraint(ALLOC_IN_RC(int_reg_no_rbp)); |
| 0 | 4285 match(RegP); |
| 4286 match(eAXRegP); | |
| 4287 match(eBXRegP); | |
| 4288 match(eCXRegP); | |
| 4289 match(eDIRegP); | |
| 4290 | |
| 4291 op_cost(100); | |
| 4292 format %{ %} | |
| 4293 interface(REG_INTER); | |
| 4294 %} | |
| 4295 | |
| 4296 operand naxRegP() %{ | |
| 4297 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4298 match(RegP); | |
| 4299 match(eBXRegP); | |
| 4300 match(eDXRegP); | |
| 4301 match(eCXRegP); | |
| 4302 match(eSIRegP); | |
| 4303 match(eDIRegP); | |
| 4304 | |
| 4305 format %{ %} | |
| 4306 interface(REG_INTER); | |
| 4307 %} | |
| 4308 | |
| 4309 operand nabxRegP() %{ | |
| 4310 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 4311 match(RegP); | |
| 4312 match(eCXRegP); | |
| 4313 match(eDXRegP); | |
| 4314 match(eSIRegP); | |
| 4315 match(eDIRegP); | |
| 4316 | |
| 4317 format %{ %} | |
| 4318 interface(REG_INTER); | |
| 4319 %} | |
| 4320 | |
| 4321 operand pRegP() %{ | |
| 4322 constraint(ALLOC_IN_RC(p_reg)); | |
| 4323 match(RegP); | |
| 4324 match(eBXRegP); | |
| 4325 match(eDXRegP); | |
| 4326 match(eSIRegP); | |
| 4327 match(eDIRegP); | |
| 4328 | |
| 4329 format %{ %} | |
| 4330 interface(REG_INTER); | |
| 4331 %} | |
| 4332 | |
| 4333 // Special Registers | |
| 4334 // Return a pointer value | |
| 4335 operand eAXRegP(eRegP reg) %{ | |
| 4336 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4337 match(reg); | |
| 4338 format %{ "EAX" %} | |
| 4339 interface(REG_INTER); | |
| 4340 %} | |
| 4341 | |
| 4342 // Used in AtomicAdd | |
| 4343 operand eBXRegP(eRegP reg) %{ | |
| 4344 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4345 match(reg); | |
| 4346 format %{ "EBX" %} | |
| 4347 interface(REG_INTER); | |
| 4348 %} | |
| 4349 | |
| 4350 // Tail-call (interprocedural jump) to interpreter | |
| 4351 operand eCXRegP(eRegP reg) %{ | |
| 4352 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4353 match(reg); | |
| 4354 format %{ "ECX" %} | |
| 4355 interface(REG_INTER); | |
| 4356 %} | |
| 4357 | |
| 4358 operand eSIRegP(eRegP reg) %{ | |
| 4359 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4360 match(reg); | |
| 4361 format %{ "ESI" %} | |
| 4362 interface(REG_INTER); | |
| 4363 %} | |
| 4364 | |
| 4365 // Used in rep stosw | |
| 4366 operand eDIRegP(eRegP reg) %{ | |
| 4367 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4368 match(reg); | |
| 4369 format %{ "EDI" %} | |
| 4370 interface(REG_INTER); | |
| 4371 %} | |
| 4372 | |
| 4373 operand eBPRegP() %{ | |
| 4374 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 4375 match(RegP); | |
| 4376 format %{ "EBP" %} | |
| 4377 interface(REG_INTER); | |
| 4378 %} | |
| 4379 | |
| 4380 operand eRegL() %{ | |
| 4381 constraint(ALLOC_IN_RC(long_reg)); | |
| 4382 match(RegL); | |
| 4383 match(eADXRegL); | |
| 4384 | |
| 4385 format %{ %} | |
| 4386 interface(REG_INTER); | |
| 4387 %} | |
| 4388 | |
| 4389 operand eADXRegL( eRegL reg ) %{ | |
| 4390 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4391 match(reg); | |
| 4392 | |
| 4393 format %{ "EDX:EAX" %} | |
| 4394 interface(REG_INTER); | |
| 4395 %} | |
| 4396 | |
| 4397 operand eBCXRegL( eRegL reg ) %{ | |
| 4398 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 4399 match(reg); | |
| 4400 | |
| 4401 format %{ "EBX:ECX" %} | |
| 4402 interface(REG_INTER); | |
| 4403 %} | |
| 4404 | |
| 4405 // Special case for integer high multiply | |
| 4406 operand eADXRegL_low_only() %{ | |
| 4407 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4408 match(RegL); | |
| 4409 | |
| 4410 format %{ "EAX" %} | |
| 4411 interface(REG_INTER); | |
| 4412 %} | |
| 4413 | |
| 4414 // Flags register, used as output of compare instructions | |
| 4415 operand eFlagsReg() %{ | |
| 4416 constraint(ALLOC_IN_RC(int_flags)); | |
| 4417 match(RegFlags); | |
| 4418 | |
| 4419 format %{ "EFLAGS" %} | |
| 4420 interface(REG_INTER); | |
| 4421 %} | |
| 4422 | |
| 4423 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4424 operand eFlagsRegU() %{ | |
| 4425 constraint(ALLOC_IN_RC(int_flags)); | |
| 4426 match(RegFlags); | |
| 4427 | |
| 4428 format %{ "EFLAGS_U" %} | |
| 4429 interface(REG_INTER); | |
| 4430 %} | |
| 4431 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4432 operand eFlagsRegUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4433 constraint(ALLOC_IN_RC(int_flags)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4434 match(RegFlags); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4435 predicate(false); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4436 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4437 format %{ "EFLAGS_U_CF" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4438 interface(REG_INTER); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4439 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4440 |
| 0 | 4441 // Condition Code Register used by long compare |
| 4442 operand flagsReg_long_LTGE() %{ | |
| 4443 constraint(ALLOC_IN_RC(int_flags)); | |
| 4444 match(RegFlags); | |
| 4445 format %{ "FLAGS_LTGE" %} | |
| 4446 interface(REG_INTER); | |
| 4447 %} | |
| 4448 operand flagsReg_long_EQNE() %{ | |
| 4449 constraint(ALLOC_IN_RC(int_flags)); | |
| 4450 match(RegFlags); | |
| 4451 format %{ "FLAGS_EQNE" %} | |
| 4452 interface(REG_INTER); | |
| 4453 %} | |
| 4454 operand flagsReg_long_LEGT() %{ | |
| 4455 constraint(ALLOC_IN_RC(int_flags)); | |
| 4456 match(RegFlags); | |
| 4457 format %{ "FLAGS_LEGT" %} | |
| 4458 interface(REG_INTER); | |
| 4459 %} | |
| 4460 | |
| 4461 // Float register operands | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4462 operand regDPR() %{ |
| 0 | 4463 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4464 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 4465 match(RegD); |
| 4466 match(regDPR1); | |
| 4467 match(regDPR2); | |
| 4468 format %{ %} | |
| 4469 interface(REG_INTER); | |
| 4470 %} | |
| 4471 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4472 operand regDPR1(regDPR reg) %{ |
| 0 | 4473 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4474 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 4475 match(reg); |
| 4476 format %{ "FPR1" %} | |
| 4477 interface(REG_INTER); | |
| 4478 %} | |
| 4479 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4480 operand regDPR2(regDPR reg) %{ |
| 0 | 4481 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4482 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 4483 match(reg); |
| 4484 format %{ "FPR2" %} | |
| 4485 interface(REG_INTER); | |
| 4486 %} | |
| 4487 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4488 operand regnotDPR1(regDPR reg) %{ |
| 0 | 4489 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4490 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 4491 match(reg); |
| 4492 format %{ %} | |
| 4493 interface(REG_INTER); | |
| 4494 %} | |
| 4495 | |
| 4496 // Float register operands | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4497 operand regFPR() %{ |
| 0 | 4498 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4499 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 4500 match(RegF); |
| 4501 match(regFPR1); | |
| 4502 format %{ %} | |
| 4503 interface(REG_INTER); | |
| 4504 %} | |
| 4505 | |
| 4506 // Float register operands | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4507 operand regFPR1(regFPR reg) %{ |
| 0 | 4508 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4509 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 4510 match(reg); |
| 4511 format %{ "FPR1" %} | |
| 4512 interface(REG_INTER); | |
| 4513 %} | |
| 4514 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4515 // XMM Float register operands |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4516 operand regF() %{ |
| 0 | 4517 predicate( UseSSE>=1 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4518 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4519 match(RegF); |
| 4520 format %{ %} | |
| 4521 interface(REG_INTER); | |
| 4522 %} | |
| 4523 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4524 // XMM Double register operands |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4525 operand regD() %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4526 predicate( UseSSE>=2 ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4527 constraint(ALLOC_IN_RC(double_reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4528 match(RegD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4529 format %{ %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4530 interface(REG_INTER); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4531 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4532 |
| 0 | 4533 |
| 4534 //----------Memory Operands---------------------------------------------------- | |
| 4535 // Direct Memory Operand | |
| 4536 operand direct(immP addr) %{ | |
| 4537 match(addr); | |
| 4538 | |
| 4539 format %{ "[$addr]" %} | |
| 4540 interface(MEMORY_INTER) %{ | |
| 4541 base(0xFFFFFFFF); | |
| 4542 index(0x4); | |
| 4543 scale(0x0); | |
| 4544 disp($addr); | |
| 4545 %} | |
| 4546 %} | |
| 4547 | |
| 4548 // Indirect Memory Operand | |
| 4549 operand indirect(eRegP reg) %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4550 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4551 match(reg); |
| 4552 | |
| 4553 format %{ "[$reg]" %} | |
| 4554 interface(MEMORY_INTER) %{ | |
| 4555 base($reg); | |
| 4556 index(0x4); | |
| 4557 scale(0x0); | |
| 4558 disp(0x0); | |
| 4559 %} | |
| 4560 %} | |
| 4561 | |
| 4562 // Indirect Memory Plus Short Offset Operand | |
| 4563 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4564 match(AddP reg off); | |
| 4565 | |
| 4566 format %{ "[$reg + $off]" %} | |
| 4567 interface(MEMORY_INTER) %{ | |
| 4568 base($reg); | |
| 4569 index(0x4); | |
| 4570 scale(0x0); | |
| 4571 disp($off); | |
| 4572 %} | |
| 4573 %} | |
| 4574 | |
| 4575 // Indirect Memory Plus Long Offset Operand | |
| 4576 operand indOffset32(eRegP reg, immI off) %{ | |
| 4577 match(AddP reg off); | |
| 4578 | |
| 4579 format %{ "[$reg + $off]" %} | |
| 4580 interface(MEMORY_INTER) %{ | |
| 4581 base($reg); | |
| 4582 index(0x4); | |
| 4583 scale(0x0); | |
| 4584 disp($off); | |
| 4585 %} | |
| 4586 %} | |
| 4587 | |
| 4588 // Indirect Memory Plus Long Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4589 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4590 match(AddP off reg); |
| 4591 | |
| 4592 format %{ "[$reg + $off]" %} | |
| 4593 interface(MEMORY_INTER) %{ | |
| 4594 base($reg); | |
| 4595 index(0x4); | |
| 4596 scale(0x0); | |
| 4597 disp($off); | |
| 4598 %} | |
| 4599 %} | |
| 4600 | |
| 4601 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4602 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4603 match(AddP (AddP reg ireg) off); |
| 4604 | |
| 4605 op_cost(10); | |
| 4606 format %{"[$reg + $off + $ireg]" %} | |
| 4607 interface(MEMORY_INTER) %{ | |
| 4608 base($reg); | |
| 4609 index($ireg); | |
| 4610 scale(0x0); | |
| 4611 disp($off); | |
| 4612 %} | |
| 4613 %} | |
| 4614 | |
| 4615 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4616 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4617 match(AddP reg ireg); |
| 4618 | |
| 4619 op_cost(10); | |
| 4620 format %{"[$reg + $ireg]" %} | |
| 4621 interface(MEMORY_INTER) %{ | |
| 4622 base($reg); | |
| 4623 index($ireg); | |
| 4624 scale(0x0); | |
| 4625 disp(0x0); | |
| 4626 %} | |
| 4627 %} | |
| 4628 | |
| 4629 // // ------------------------------------------------------------------------- | |
| 4630 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4631 // // ------------------------------------------------------------------------- | |
| 4632 // // Scaled Memory Operands | |
| 4633 // // Indirect Memory Times Scale Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4634 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4635 // match(AddP off (LShiftI ireg scale)); |
| 4636 // | |
| 4637 // op_cost(10); | |
| 4638 // format %{"[$off + $ireg << $scale]" %} | |
| 4639 // interface(MEMORY_INTER) %{ | |
| 4640 // base(0x4); | |
| 4641 // index($ireg); | |
| 4642 // scale($scale); | |
| 4643 // disp($off); | |
| 4644 // %} | |
| 4645 // %} | |
| 4646 | |
| 4647 // Indirect Memory Times Scale Plus Index Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4648 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4649 match(AddP reg (LShiftI ireg scale)); |
| 4650 | |
| 4651 op_cost(10); | |
| 4652 format %{"[$reg + $ireg << $scale]" %} | |
| 4653 interface(MEMORY_INTER) %{ | |
| 4654 base($reg); | |
| 4655 index($ireg); | |
| 4656 scale($scale); | |
| 4657 disp(0x0); | |
| 4658 %} | |
| 4659 %} | |
| 4660 | |
| 4661 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4662 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4663 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4664 | |
| 4665 op_cost(10); | |
| 4666 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4667 interface(MEMORY_INTER) %{ | |
| 4668 base($reg); | |
| 4669 index($ireg); | |
| 4670 scale($scale); | |
| 4671 disp($off); | |
| 4672 %} | |
| 4673 %} | |
| 4674 | |
| 4675 //----------Load Long Memory Operands------------------------------------------ | |
| 4676 // The load-long idiom will use it's address expression again after loading | |
| 4677 // the first word of the long. If the load-long destination overlaps with | |
| 4678 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4679 // from a clobbered address. Fix this by requiring that load-long use | |
| 4680 // address registers that do not overlap with the load-long target. | |
| 4681 | |
| 4682 // load-long support | |
| 4683 operand load_long_RegP() %{ | |
| 4684 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4685 match(RegP); | |
| 4686 match(eSIRegP); | |
| 4687 op_cost(100); | |
| 4688 format %{ %} | |
| 4689 interface(REG_INTER); | |
| 4690 %} | |
| 4691 | |
| 4692 // Indirect Memory Operand Long | |
| 4693 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4694 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4695 match(reg); | |
| 4696 | |
| 4697 format %{ "[$reg]" %} | |
| 4698 interface(MEMORY_INTER) %{ | |
| 4699 base($reg); | |
| 4700 index(0x4); | |
| 4701 scale(0x0); | |
| 4702 disp(0x0); | |
| 4703 %} | |
| 4704 %} | |
| 4705 | |
| 4706 // Indirect Memory Plus Long Offset Operand | |
| 4707 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4708 match(AddP reg off); | |
| 4709 | |
| 4710 format %{ "[$reg + $off]" %} | |
| 4711 interface(MEMORY_INTER) %{ | |
| 4712 base($reg); | |
| 4713 index(0x4); | |
| 4714 scale(0x0); | |
| 4715 disp($off); | |
| 4716 %} | |
| 4717 %} | |
| 4718 | |
| 4719 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4720 | |
| 4721 | |
| 4722 //----------Special Memory Operands-------------------------------------------- | |
| 4723 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4724 // values on the stack where a match requires a value to | |
| 4725 // flow through memory. | |
| 4726 operand stackSlotP(sRegP reg) %{ | |
| 4727 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4728 // No match rule because this operand is only generated in matching | |
| 4729 format %{ "[$reg]" %} | |
| 4730 interface(MEMORY_INTER) %{ | |
| 4731 base(0x4); // ESP | |
| 4732 index(0x4); // No Index | |
| 4733 scale(0x0); // No Scale | |
| 4734 disp($reg); // Stack Offset | |
| 4735 %} | |
| 4736 %} | |
| 4737 | |
| 4738 operand stackSlotI(sRegI reg) %{ | |
| 4739 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4740 // No match rule because this operand is only generated in matching | |
| 4741 format %{ "[$reg]" %} | |
| 4742 interface(MEMORY_INTER) %{ | |
| 4743 base(0x4); // ESP | |
| 4744 index(0x4); // No Index | |
| 4745 scale(0x0); // No Scale | |
| 4746 disp($reg); // Stack Offset | |
| 4747 %} | |
| 4748 %} | |
| 4749 | |
| 4750 operand stackSlotF(sRegF reg) %{ | |
| 4751 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4752 // No match rule because this operand is only generated in matching | |
| 4753 format %{ "[$reg]" %} | |
| 4754 interface(MEMORY_INTER) %{ | |
| 4755 base(0x4); // ESP | |
| 4756 index(0x4); // No Index | |
| 4757 scale(0x0); // No Scale | |
| 4758 disp($reg); // Stack Offset | |
| 4759 %} | |
| 4760 %} | |
| 4761 | |
| 4762 operand stackSlotD(sRegD reg) %{ | |
| 4763 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4764 // No match rule because this operand is only generated in matching | |
| 4765 format %{ "[$reg]" %} | |
| 4766 interface(MEMORY_INTER) %{ | |
| 4767 base(0x4); // ESP | |
| 4768 index(0x4); // No Index | |
| 4769 scale(0x0); // No Scale | |
| 4770 disp($reg); // Stack Offset | |
| 4771 %} | |
| 4772 %} | |
| 4773 | |
| 4774 operand stackSlotL(sRegL reg) %{ | |
| 4775 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4776 // No match rule because this operand is only generated in matching | |
| 4777 format %{ "[$reg]" %} | |
| 4778 interface(MEMORY_INTER) %{ | |
| 4779 base(0x4); // ESP | |
| 4780 index(0x4); // No Index | |
| 4781 scale(0x0); // No Scale | |
| 4782 disp($reg); // Stack Offset | |
| 4783 %} | |
| 4784 %} | |
| 4785 | |
| 4786 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4787 // Indirect Memory Operand | |
| 4788 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4789 %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4790 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4791 match(reg); |
| 4792 | |
| 4793 op_cost(100); | |
| 4794 format %{ "[$reg]" %} | |
| 4795 interface(MEMORY_INTER) %{ | |
| 4796 base($reg); | |
| 4797 index(0x4); | |
| 4798 scale(0x0); | |
| 4799 disp(0x0); | |
| 4800 %} | |
| 4801 %} | |
| 4802 | |
| 4803 // Indirect Memory Plus Short Offset Operand | |
| 4804 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4805 %{ | |
| 4806 match(AddP reg off); | |
| 4807 | |
| 4808 op_cost(100); | |
| 4809 format %{ "[$reg + $off]" %} | |
| 4810 interface(MEMORY_INTER) %{ | |
| 4811 base($reg); | |
| 4812 index(0x4); | |
| 4813 scale(0x0); | |
| 4814 disp($off); | |
| 4815 %} | |
| 4816 %} | |
| 4817 | |
| 4818 // Indirect Memory Plus Long Offset Operand | |
| 4819 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4820 %{ | |
| 4821 match(AddP reg off); | |
| 4822 | |
| 4823 op_cost(100); | |
| 4824 format %{ "[$reg + $off]" %} | |
| 4825 interface(MEMORY_INTER) %{ | |
| 4826 base($reg); | |
| 4827 index(0x4); | |
| 4828 scale(0x0); | |
| 4829 disp($off); | |
| 4830 %} | |
| 4831 %} | |
| 4832 | |
| 4833 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4834 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4835 %{ |
| 4836 match(AddP (AddP reg ireg) off); | |
| 4837 | |
| 4838 op_cost(100); | |
| 4839 format %{"[$reg + $off + $ireg]" %} | |
| 4840 interface(MEMORY_INTER) %{ | |
| 4841 base($reg); | |
| 4842 index($ireg); | |
| 4843 scale(0x0); | |
| 4844 disp($off); | |
| 4845 %} | |
| 4846 %} | |
| 4847 | |
| 4848 // Indirect Memory Times Scale Plus Index Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4849 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4850 %{ |
| 4851 match(AddP reg (LShiftI ireg scale)); | |
| 4852 | |
| 4853 op_cost(100); | |
| 4854 format %{"[$reg + $ireg << $scale]" %} | |
| 4855 interface(MEMORY_INTER) %{ | |
| 4856 base($reg); | |
| 4857 index($ireg); | |
| 4858 scale($scale); | |
| 4859 disp(0x0); | |
| 4860 %} | |
| 4861 %} | |
| 4862 | |
| 4863 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4864 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4865 %{ |
| 4866 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4867 | |
| 4868 op_cost(100); | |
| 4869 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4870 interface(MEMORY_INTER) %{ | |
| 4871 base($reg); | |
| 4872 index($ireg); | |
| 4873 scale($scale); | |
| 4874 disp($off); | |
| 4875 %} | |
| 4876 %} | |
| 4877 | |
| 4878 //----------Conditional Branch Operands---------------------------------------- | |
| 4879 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4880 // the following set of codes: | |
| 4881 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4882 // | |
| 4883 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4884 // by the comparison instruction that sets a condition code flags register. | |
| 4885 // That result is represented by a flags operand whose subtype is appropriate | |
| 4886 // to the unsignedness (etc.) of the comparison. | |
| 4887 // | |
| 4888 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4889 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4890 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4891 | |
| 4892 // Comparision Code | |
| 4893 operand cmpOp() %{ | |
| 4894 match(Bool); | |
| 4895 | |
| 4896 format %{ "" %} | |
| 4897 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4898 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4899 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4900 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4901 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4902 less_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4903 greater(0xF, "g"); |
| 12323 | 4904 overflow(0x0, "o"); |
| 4905 no_overflow(0x1, "no"); | |
| 0 | 4906 %} |
| 4907 %} | |
| 4908 | |
| 4909 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4910 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4911 // C0 and C3 are turned into Carry & Zero flags. | |
| 4912 operand cmpOpU() %{ | |
| 4913 match(Bool); | |
| 4914 | |
| 4915 format %{ "" %} | |
| 4916 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4917 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4918 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4919 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4920 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4921 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4922 greater(0x7, "nbe"); |
| 12323 | 4923 overflow(0x0, "o"); |
| 4924 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4925 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4926 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4927 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4928 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4929 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4930 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4931 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4932 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4933 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4934 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4935 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4936 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4937 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4938 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4939 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4940 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4941 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4942 greater(0x7, "nbe"); |
| 12323 | 4943 overflow(0x0, "o"); |
| 4944 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4945 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4946 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4947 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4948 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4949 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4950 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4951 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4952 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4953 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4954 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4955 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4956 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4957 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4958 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4959 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4960 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4961 greater(0x7, "nbe"); |
| 12323 | 4962 overflow(0x0, "o"); |
| 4963 no_overflow(0x1, "no"); | |
| 0 | 4964 %} |
| 4965 %} | |
| 4966 | |
| 4967 // Comparison Code for FP conditional move | |
| 4968 operand cmpOp_fcmov() %{ | |
| 4969 match(Bool); | |
| 4970 | |
| 12323 | 4971 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4972 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4973 format %{ "" %} |
| 4974 interface(COND_INTER) %{ | |
| 4975 equal (0x0C8); | |
| 4976 not_equal (0x1C8); | |
| 4977 less (0x0C0); | |
| 4978 greater_equal(0x1C0); | |
| 4979 less_equal (0x0D0); | |
| 4980 greater (0x1D0); | |
| 12323 | 4981 overflow(0x0, "o"); // not really supported by the instruction |
| 4982 no_overflow(0x1, "no"); // not really supported by the instruction | |
| 0 | 4983 %} |
| 4984 %} | |
| 4985 | |
| 4986 // Comparision Code used in long compares | |
| 4987 operand cmpOp_commute() %{ | |
| 4988 match(Bool); | |
| 4989 | |
| 4990 format %{ "" %} | |
| 4991 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4992 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4993 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4994 less(0xF, "g"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4995 greater_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4996 less_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4997 greater(0xC, "l"); |
| 12323 | 4998 overflow(0x0, "o"); |
| 4999 no_overflow(0x1, "no"); | |
| 0 | 5000 %} |
| 5001 %} | |
| 5002 | |
| 5003 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5004 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5005 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5006 // instructions for every form of operand when the instruction accepts |
| 5007 // multiple operand types with the same basic encoding and format. The classic | |
| 5008 // case of this is memory operands. | |
| 5009 | |
| 5010 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5011 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5012 | |
| 5013 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5014 // This means some kind of offset is always required and you cannot use | |
| 5015 // an oop as the offset (done when working on static globals). | |
| 5016 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5017 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5018 | |
| 5019 | |
| 5020 //----------PIPELINE----------------------------------------------------------- | |
| 5021 // Rules which define the behavior of the target architectures pipeline. | |
| 5022 pipeline %{ | |
| 5023 | |
| 5024 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5025 attributes %{ | |
| 5026 variable_size_instructions; // Fixed size instructions | |
| 5027 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5028 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5029 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5030 instruction_fetch_units = 1; // of 16 bytes | |
| 5031 | |
| 5032 // List of nop instructions | |
| 5033 nops( MachNop ); | |
| 5034 %} | |
| 5035 | |
| 5036 //----------RESOURCES---------------------------------------------------------- | |
| 5037 // Resources are the functional units available to the machine | |
| 5038 | |
| 5039 // Generic P2/P3 pipeline | |
| 5040 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5041 // 3 instructions decoded per cycle. | |
| 5042 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5043 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5044 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5045 MS0, MS1, MEM = MS0 | MS1, | |
| 5046 BR, FPU, | |
| 5047 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5048 | |
| 5049 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5050 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5051 | |
| 5052 // Generic P2/P3 pipeline | |
| 5053 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5054 | |
| 5055 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5056 // Pipeline Classes describe the stages in which input and output are | |
| 5057 // referenced by the hardware pipeline. | |
| 5058 | |
| 5059 // Naming convention: ialu or fpu | |
| 5060 // Then: _reg | |
| 5061 // Then: _reg if there is a 2nd register | |
| 5062 // Then: _long if it's a pair of instructions implementing a long | |
| 5063 // Then: _fat if it requires the big decoder | |
| 5064 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5065 | |
| 5066 // Integer ALU reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5067 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 5068 single_instruction; |
| 5069 dst : S4(write); | |
| 5070 dst : S3(read); | |
| 5071 DECODE : S0; // any decoder | |
| 5072 ALU : S3; // any alu | |
| 5073 %} | |
| 5074 | |
| 5075 // Long ALU reg operation | |
| 5076 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5077 instruction_count(2); | |
| 5078 dst : S4(write); | |
| 5079 dst : S3(read); | |
| 5080 DECODE : S0(2); // any 2 decoders | |
| 5081 ALU : S3(2); // both alus | |
| 5082 %} | |
| 5083 | |
| 5084 // Integer ALU reg operation using big decoder | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5085 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 5086 single_instruction; |
| 5087 dst : S4(write); | |
| 5088 dst : S3(read); | |
| 5089 D0 : S0; // big decoder only | |
| 5090 ALU : S3; // any alu | |
| 5091 %} | |
| 5092 | |
| 5093 // Long ALU reg operation using big decoder | |
| 5094 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5095 instruction_count(2); | |
| 5096 dst : S4(write); | |
| 5097 dst : S3(read); | |
| 5098 D0 : S0(2); // big decoder only; twice | |
| 5099 ALU : S3(2); // any 2 alus | |
| 5100 %} | |
| 5101 | |
| 5102 // Integer ALU reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5103 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 5104 single_instruction; |
| 5105 dst : S4(write); | |
| 5106 src : S3(read); | |
| 5107 DECODE : S0; // any decoder | |
| 5108 ALU : S3; // any alu | |
| 5109 %} | |
| 5110 | |
| 5111 // Long ALU reg-reg operation | |
| 5112 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5113 instruction_count(2); | |
| 5114 dst : S4(write); | |
| 5115 src : S3(read); | |
| 5116 DECODE : S0(2); // any 2 decoders | |
| 5117 ALU : S3(2); // both alus | |
| 5118 %} | |
| 5119 | |
| 5120 // Integer ALU reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5121 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 5122 single_instruction; |
| 5123 dst : S4(write); | |
| 5124 src : S3(read); | |
| 5125 D0 : S0; // big decoder only | |
| 5126 ALU : S3; // any alu | |
| 5127 %} | |
| 5128 | |
| 5129 // Long ALU reg-reg operation | |
| 5130 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5131 instruction_count(2); | |
| 5132 dst : S4(write); | |
| 5133 src : S3(read); | |
| 5134 D0 : S0(2); // big decoder only; twice | |
| 5135 ALU : S3(2); // both alus | |
| 5136 %} | |
| 5137 | |
| 5138 // Integer ALU reg-mem operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5139 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 5140 single_instruction; |
| 5141 dst : S5(write); | |
| 5142 mem : S3(read); | |
| 5143 D0 : S0; // big decoder only | |
| 5144 ALU : S4; // any alu | |
| 5145 MEM : S3; // any mem | |
| 5146 %} | |
| 5147 | |
| 5148 // Long ALU reg-mem operation | |
| 5149 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5150 instruction_count(2); | |
| 5151 dst : S5(write); | |
| 5152 mem : S3(read); | |
| 5153 D0 : S0(2); // big decoder only; twice | |
| 5154 ALU : S4(2); // any 2 alus | |
| 5155 MEM : S3(2); // both mems | |
| 5156 %} | |
| 5157 | |
| 5158 // Integer mem operation (prefetch) | |
| 5159 pipe_class ialu_mem(memory mem) | |
| 5160 %{ | |
| 5161 single_instruction; | |
| 5162 mem : S3(read); | |
| 5163 D0 : S0; // big decoder only | |
| 5164 MEM : S3; // any mem | |
| 5165 %} | |
| 5166 | |
| 5167 // Integer Store to Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5168 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 5169 single_instruction; |
| 5170 mem : S3(read); | |
| 5171 src : S5(read); | |
| 5172 D0 : S0; // big decoder only | |
| 5173 ALU : S4; // any alu | |
| 5174 MEM : S3; | |
| 5175 %} | |
| 5176 | |
| 5177 // Long Store to Memory | |
| 5178 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5179 instruction_count(2); | |
| 5180 mem : S3(read); | |
| 5181 src : S5(read); | |
| 5182 D0 : S0(2); // big decoder only; twice | |
| 5183 ALU : S4(2); // any 2 alus | |
| 5184 MEM : S3(2); // Both mems | |
| 5185 %} | |
| 5186 | |
| 5187 // Integer Store to Memory | |
| 5188 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5189 single_instruction; | |
| 5190 mem : S3(read); | |
| 5191 D0 : S0; // big decoder only | |
| 5192 ALU : S4; // any alu | |
| 5193 MEM : S3; | |
| 5194 %} | |
| 5195 | |
| 5196 // Integer ALU0 reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5197 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 5198 single_instruction; |
| 5199 dst : S4(write); | |
| 5200 src : S3(read); | |
| 5201 D0 : S0; // Big decoder only | |
| 5202 ALU0 : S3; // only alu0 | |
| 5203 %} | |
| 5204 | |
| 5205 // Integer ALU0 reg-mem operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5206 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 5207 single_instruction; |
| 5208 dst : S5(write); | |
| 5209 mem : S3(read); | |
| 5210 D0 : S0; // big decoder only | |
| 5211 ALU0 : S4; // ALU0 only | |
| 5212 MEM : S3; // any mem | |
| 5213 %} | |
| 5214 | |
| 5215 // Integer ALU reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5216 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 5217 single_instruction; |
| 5218 cr : S4(write); | |
| 5219 src1 : S3(read); | |
| 5220 src2 : S3(read); | |
| 5221 DECODE : S0; // any decoder | |
| 5222 ALU : S3; // any alu | |
| 5223 %} | |
| 5224 | |
| 5225 // Integer ALU reg-imm operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5226 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 5227 single_instruction; |
| 5228 cr : S4(write); | |
| 5229 src1 : S3(read); | |
| 5230 DECODE : S0; // any decoder | |
| 5231 ALU : S3; // any alu | |
| 5232 %} | |
| 5233 | |
| 5234 // Integer ALU reg-mem operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5235 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 5236 single_instruction; |
| 5237 cr : S4(write); | |
| 5238 src1 : S3(read); | |
| 5239 src2 : S3(read); | |
| 5240 D0 : S0; // big decoder only | |
| 5241 ALU : S4; // any alu | |
| 5242 MEM : S3; | |
| 5243 %} | |
| 5244 | |
| 5245 // Conditional move reg-reg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5246 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 5247 instruction_count(4); |
| 5248 y : S4(read); | |
| 5249 q : S3(read); | |
| 5250 p : S3(read); | |
| 5251 DECODE : S0(4); // any decoder | |
| 5252 %} | |
| 5253 | |
| 5254 // Conditional move reg-reg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5255 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 5256 single_instruction; |
| 5257 dst : S4(write); | |
| 5258 src : S3(read); | |
| 5259 cr : S3(read); | |
| 5260 DECODE : S0; // any decoder | |
| 5261 %} | |
| 5262 | |
| 5263 // Conditional move reg-mem | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5264 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 5265 single_instruction; |
| 5266 dst : S4(write); | |
| 5267 src : S3(read); | |
| 5268 cr : S3(read); | |
| 5269 DECODE : S0; // any decoder | |
| 5270 MEM : S3; | |
| 5271 %} | |
| 5272 | |
| 5273 // Conditional move reg-reg long | |
| 5274 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 5275 single_instruction; | |
| 5276 dst : S4(write); | |
| 5277 src : S3(read); | |
| 5278 cr : S3(read); | |
| 5279 DECODE : S0(2); // any 2 decoders | |
| 5280 %} | |
| 5281 | |
| 5282 // Conditional move double reg-reg | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5283 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 5284 single_instruction; |
| 5285 dst : S4(write); | |
| 5286 src : S3(read); | |
| 5287 cr : S3(read); | |
| 5288 DECODE : S0; // any decoder | |
| 5289 %} | |
| 5290 | |
| 5291 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5292 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 5293 instruction_count(2); |
| 5294 dst : S3(read); | |
| 5295 DECODE : S0(2); // any 2 decoders | |
| 5296 FPU : S3; | |
| 5297 %} | |
| 5298 | |
| 5299 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5300 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 5301 instruction_count(2); |
| 5302 dst : S4(write); | |
| 5303 src : S3(read); | |
| 5304 DECODE : S0(2); // any 2 decoders | |
| 5305 FPU : S3; | |
| 5306 %} | |
| 5307 | |
| 5308 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5309 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 5310 instruction_count(3); |
| 5311 dst : S4(write); | |
| 5312 src1 : S3(read); | |
| 5313 src2 : S3(read); | |
| 5314 DECODE : S0(3); // any 3 decoders | |
| 5315 FPU : S3(2); | |
| 5316 %} | |
| 5317 | |
| 5318 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5319 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 5320 instruction_count(4); |
| 5321 dst : S4(write); | |
| 5322 src1 : S3(read); | |
| 5323 src2 : S3(read); | |
| 5324 src3 : S3(read); | |
| 5325 DECODE : S0(4); // any 3 decoders | |
| 5326 FPU : S3(2); | |
| 5327 %} | |
| 5328 | |
| 5329 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5330 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 5331 instruction_count(4); |
| 5332 dst : S4(write); | |
| 5333 src1 : S3(read); | |
| 5334 src2 : S3(read); | |
| 5335 src3 : S3(read); | |
| 5336 DECODE : S1(3); // any 3 decoders | |
| 5337 D0 : S0; // Big decoder only | |
| 5338 FPU : S3(2); | |
| 5339 MEM : S3; | |
| 5340 %} | |
| 5341 | |
| 5342 // Float reg-mem operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5343 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 5344 instruction_count(2); |
| 5345 dst : S5(write); | |
| 5346 mem : S3(read); | |
| 5347 D0 : S0; // big decoder only | |
| 5348 DECODE : S1; // any decoder for FPU POP | |
| 5349 FPU : S4; | |
| 5350 MEM : S3; // any mem | |
| 5351 %} | |
| 5352 | |
| 5353 // Float reg-mem operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5354 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 5355 instruction_count(3); |
| 5356 dst : S5(write); | |
| 5357 src1 : S3(read); | |
| 5358 mem : S3(read); | |
| 5359 D0 : S0; // big decoder only | |
| 5360 DECODE : S1(2); // any decoder for FPU POP | |
| 5361 FPU : S4; | |
| 5362 MEM : S3; // any mem | |
| 5363 %} | |
| 5364 | |
| 5365 // Float mem-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5366 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 5367 instruction_count(2); |
| 5368 src : S5(read); | |
| 5369 mem : S3(read); | |
| 5370 DECODE : S0; // any decoder for FPU PUSH | |
| 5371 D0 : S1; // big decoder only | |
| 5372 FPU : S4; | |
| 5373 MEM : S3; // any mem | |
| 5374 %} | |
| 5375 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5376 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 5377 instruction_count(3); |
| 5378 src1 : S3(read); | |
| 5379 src2 : S3(read); | |
| 5380 mem : S3(read); | |
| 5381 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5382 D0 : S1; // big decoder only | |
| 5383 FPU : S4; | |
| 5384 MEM : S3; // any mem | |
| 5385 %} | |
| 5386 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5387 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 5388 instruction_count(3); |
| 5389 src1 : S3(read); | |
| 5390 src2 : S3(read); | |
| 5391 mem : S4(read); | |
| 5392 DECODE : S0; // any decoder for FPU PUSH | |
| 5393 D0 : S0(2); // big decoder only | |
| 5394 FPU : S4; | |
| 5395 MEM : S3(2); // any mem | |
| 5396 %} | |
| 5397 | |
| 5398 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 5399 instruction_count(2); | |
| 5400 src1 : S3(read); | |
| 5401 dst : S4(read); | |
| 5402 D0 : S0(2); // big decoder only | |
| 5403 MEM : S3(2); // any mem | |
| 5404 %} | |
| 5405 | |
| 5406 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 5407 instruction_count(3); | |
| 5408 src1 : S3(read); | |
| 5409 src2 : S3(read); | |
| 5410 dst : S4(read); | |
| 5411 D0 : S0(3); // big decoder only | |
| 5412 FPU : S4; | |
| 5413 MEM : S3(3); // any mem | |
| 5414 %} | |
| 5415 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5416 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 5417 instruction_count(3); |
| 5418 src1 : S4(read); | |
| 5419 mem : S4(read); | |
| 5420 DECODE : S0; // any decoder for FPU PUSH | |
| 5421 D0 : S0(2); // big decoder only | |
| 5422 FPU : S4; | |
| 5423 MEM : S3(2); // any mem | |
| 5424 %} | |
| 5425 | |
| 5426 // Float load constant | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5427 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 5428 instruction_count(2); |
| 5429 dst : S5(write); | |
| 5430 D0 : S0; // big decoder only for the load | |
| 5431 DECODE : S1; // any decoder for FPU POP | |
| 5432 FPU : S4; | |
| 5433 MEM : S3; // any mem | |
| 5434 %} | |
| 5435 | |
| 5436 // Float load constant | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5437 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 5438 instruction_count(3); |
| 5439 dst : S5(write); | |
| 5440 src : S3(read); | |
| 5441 D0 : S0; // big decoder only for the load | |
| 5442 DECODE : S1(2); // any decoder for FPU POP | |
| 5443 FPU : S4; | |
| 5444 MEM : S3; // any mem | |
| 5445 %} | |
| 5446 | |
| 5447 // UnConditional branch | |
| 5448 pipe_class pipe_jmp( label labl ) %{ | |
| 5449 single_instruction; | |
| 5450 BR : S3; | |
| 5451 %} | |
| 5452 | |
| 5453 // Conditional branch | |
| 5454 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 5455 single_instruction; | |
| 5456 cr : S1(read); | |
| 5457 BR : S3; | |
| 5458 %} | |
| 5459 | |
| 5460 // Allocation idiom | |
| 5461 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 5462 instruction_count(1); force_serialization; | |
| 5463 fixed_latency(6); | |
| 5464 heap_ptr : S3(read); | |
| 5465 DECODE : S0(3); | |
| 5466 D0 : S2; | |
| 5467 MEM : S3; | |
| 5468 ALU : S3(2); | |
| 5469 dst : S5(write); | |
| 5470 BR : S5; | |
| 5471 %} | |
| 5472 | |
| 5473 // Generic big/slow expanded idiom | |
| 5474 pipe_class pipe_slow( ) %{ | |
| 5475 instruction_count(10); multiple_bundles; force_serialization; | |
| 5476 fixed_latency(100); | |
| 5477 D0 : S0(2); | |
| 5478 MEM : S3(2); | |
| 5479 %} | |
| 5480 | |
| 5481 // The real do-nothing guy | |
| 5482 pipe_class empty( ) %{ | |
| 5483 instruction_count(0); | |
| 5484 %} | |
| 5485 | |
| 5486 // Define the class for the Nop node | |
| 5487 define %{ | |
| 5488 MachNop = empty; | |
| 5489 %} | |
| 5490 | |
| 5491 %} | |
| 5492 | |
| 5493 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5494 // | |
| 5495 // match -- States which machine-independent subtree may be replaced | |
| 5496 // by this instruction. | |
| 5497 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5498 // selection to identify a minimum cost tree of machine | |
| 5499 // instructions that matches a tree of machine-independent | |
| 5500 // instructions. | |
| 5501 // format -- A string providing the disassembly for this instruction. | |
| 5502 // The value of an instruction's operand may be inserted | |
| 5503 // by referring to it with a '$' prefix. | |
| 5504 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5505 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5506 // respectively. The primary opcode is commonly used to | |
| 5507 // indicate the type of machine instruction, while secondary | |
| 5508 // and tertiary are often used for prefix options or addressing | |
| 5509 // modes. | |
| 5510 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5511 // name must have been defined in an 'enc_class' specification | |
| 5512 // in the encode section of the architecture description. | |
| 5513 | |
| 5514 //----------BSWAP-Instruction-------------------------------------------------- | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5515 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 5516 match(Set dst (ReverseBytesI dst)); |
| 5517 | |
| 5518 format %{ "BSWAP $dst" %} | |
| 5519 opcode(0x0F, 0xC8); | |
| 5520 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5521 ins_pipe( ialu_reg ); | |
| 5522 %} | |
| 5523 | |
| 5524 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5525 match(Set dst (ReverseBytesL dst)); | |
| 5526 | |
| 5527 format %{ "BSWAP $dst.lo\n\t" | |
| 5528 "BSWAP $dst.hi\n\t" | |
| 5529 "XCHG $dst.lo $dst.hi" %} | |
| 5530 | |
| 5531 ins_cost(125); | |
| 5532 ins_encode( bswap_long_bytes(dst) ); | |
| 5533 ins_pipe( ialu_reg_reg); | |
| 5534 %} | |
| 5535 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5536 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5537 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5538 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5539 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5540 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5541 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5542 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5543 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5544 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5545 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5546 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5547 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5548 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5549 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5550 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5551 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5552 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5553 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5554 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5555 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5556 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5557 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5558 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5559 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5560 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5561 |
| 0 | 5562 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5563 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5564 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5565 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5566 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5567 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5568 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5569 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5570 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5571 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5572 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5573 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5574 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5575 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5576 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5577 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5578 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5579 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5580 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5581 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5582 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5583 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5584 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5585 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5586 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5587 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5588 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5589 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5590 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5591 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5592 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5593 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5594 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5595 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5596 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5597 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5598 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5599 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5600 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5601 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5602 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5603 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5604 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5605 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5606 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5607 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5608 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5609 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5610 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5611 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5612 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5613 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5614 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5615 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5616 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5617 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5618 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5619 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5620 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5621 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5622 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5623 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5624 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5625 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5626 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5627 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5628 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5629 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5630 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5631 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5632 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5633 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5634 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5635 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5636 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5637 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5638 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5639 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5640 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5641 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5642 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5643 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5644 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5645 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5646 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5647 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5648 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5649 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5650 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5651 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5652 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5653 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5654 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5655 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5656 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5657 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5658 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5659 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5660 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5661 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5662 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5663 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5664 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5665 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5666 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5667 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5668 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5669 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5670 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5671 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5672 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5673 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5674 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5675 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5676 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5677 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5678 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5679 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5680 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5681 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5682 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5683 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5684 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5685 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5686 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5687 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5688 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5689 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5690 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5691 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5692 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5693 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5694 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5695 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5696 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5697 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5698 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5699 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5700 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5701 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5702 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5703 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5704 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5705 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5706 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5707 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5708 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5709 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5710 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5711 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5712 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5713 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5714 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5715 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5716 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5717 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5718 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5719 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5720 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5721 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5722 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5723 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5724 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5725 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5726 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5727 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5728 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5729 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5730 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5731 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5732 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5733 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5734 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5735 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5736 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5737 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5738 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5739 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5740 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5741 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5742 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5743 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5744 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5745 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5746 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5747 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5748 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5749 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5750 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5751 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5752 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5753 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5754 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5755 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5756 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5757 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5758 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5759 format %{ "POPCNT $dst, $mem\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5760 "POPCNT $tmp, $mem+4\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5761 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5762 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5763 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5764 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5765 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5766 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5767 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5768 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5769 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5770 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5771 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5772 |
| 0 | 5773 //----------Load/Store/Move Instructions--------------------------------------- |
| 5774 //----------Load Instructions-------------------------------------------------- | |
| 5775 // Load Byte (8bit signed) | |
| 5776 instruct loadB(xRegI dst, memory mem) %{ | |
| 5777 match(Set dst (LoadB mem)); | |
| 5778 | |
| 5779 ins_cost(125); | |
| 624 | 5780 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5781 | |
| 5782 ins_encode %{ | |
| 5783 __ movsbl($dst$$Register, $mem$$Address); | |
| 5784 %} | |
| 5785 | |
| 5786 ins_pipe(ialu_reg_mem); | |
| 5787 %} | |
| 5788 | |
| 5789 // Load Byte (8bit signed) into Long Register | |
| 824 | 5790 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5791 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5792 effect(KILL cr); |
| 624 | 5793 |
| 5794 ins_cost(375); | |
| 5795 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5796 "MOV $dst.hi,$dst.lo\n\t" | |
| 5797 "SAR $dst.hi,7" %} | |
| 5798 | |
| 5799 ins_encode %{ | |
| 5800 __ movsbl($dst$$Register, $mem$$Address); | |
| 5801 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5802 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5803 %} | |
| 5804 | |
| 5805 ins_pipe(ialu_reg_mem); | |
| 5806 %} | |
| 5807 | |
| 5808 // Load Unsigned Byte (8bit UNsigned) | |
| 5809 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5810 match(Set dst (LoadUB mem)); | |
| 0 | 5811 |
| 5812 ins_cost(125); | |
| 624 | 5813 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5814 | |
| 5815 ins_encode %{ | |
| 5816 __ movzbl($dst$$Register, $mem$$Address); | |
| 5817 %} | |
| 5818 | |
| 5819 ins_pipe(ialu_reg_mem); | |
| 5820 %} | |
| 5821 | |
| 5822 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5823 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5824 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5825 effect(KILL cr); |
| 624 | 5826 |
| 5827 ins_cost(250); | |
| 5828 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5829 "XOR $dst.hi,$dst.hi" %} | |
| 5830 | |
| 5831 ins_encode %{ | |
| 824 | 5832 Register Rdst = $dst$$Register; |
| 5833 __ movzbl(Rdst, $mem$$Address); | |
| 5834 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5835 %} | |
| 5836 | |
| 5837 ins_pipe(ialu_reg_mem); | |
| 5838 %} | |
| 5839 | |
| 5840 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5841 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5842 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5843 effect(KILL cr); | |
| 5844 | |
| 5845 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5846 "XOR $dst.hi,$dst.hi\n\t" | |
| 5847 "AND $dst.lo,$mask" %} | |
| 5848 ins_encode %{ | |
| 5849 Register Rdst = $dst$$Register; | |
| 5850 __ movzbl(Rdst, $mem$$Address); | |
| 5851 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5852 __ andl(Rdst, $mask$$constant); | |
| 5853 %} | |
| 624 | 5854 ins_pipe(ialu_reg_mem); |
| 5855 %} | |
| 5856 | |
| 5857 // Load Short (16bit signed) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5858 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5859 match(Set dst (LoadS mem)); |
| 5860 | |
| 5861 ins_cost(125); | |
| 5862 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5863 | |
| 5864 ins_encode %{ | |
| 5865 __ movswl($dst$$Register, $mem$$Address); | |
| 5866 %} | |
| 5867 | |
| 5868 ins_pipe(ialu_reg_mem); | |
| 5869 %} | |
| 5870 | |
| 785 | 5871 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5872 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5873 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5874 | |
| 5875 ins_cost(125); | |
| 5876 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5877 ins_encode %{ | |
| 5878 __ movsbl($dst$$Register, $mem$$Address); | |
| 5879 %} | |
| 5880 ins_pipe(ialu_reg_mem); | |
| 5881 %} | |
| 5882 | |
| 624 | 5883 // Load Short (16bit signed) into Long Register |
| 824 | 5884 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5885 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5886 effect(KILL cr); |
| 624 | 5887 |
| 5888 ins_cost(375); | |
| 5889 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5890 "MOV $dst.hi,$dst.lo\n\t" | |
| 5891 "SAR $dst.hi,15" %} | |
| 5892 | |
| 5893 ins_encode %{ | |
| 5894 __ movswl($dst$$Register, $mem$$Address); | |
| 5895 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5896 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5897 %} | |
| 5898 | |
| 5899 ins_pipe(ialu_reg_mem); | |
| 0 | 5900 %} |
| 5901 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5902 // Load Unsigned Short/Char (16bit unsigned) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5903 instruct loadUS(rRegI dst, memory mem) %{ |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5904 match(Set dst (LoadUS mem)); |
| 0 | 5905 |
| 5906 ins_cost(125); | |
| 624 | 5907 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5908 | |
| 5909 ins_encode %{ | |
| 5910 __ movzwl($dst$$Register, $mem$$Address); | |
| 5911 %} | |
| 5912 | |
| 5913 ins_pipe(ialu_reg_mem); | |
| 5914 %} | |
| 5915 | |
| 785 | 5916 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5917 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5918 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5919 | |
| 5920 ins_cost(125); | |
| 5921 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5922 ins_encode %{ | |
| 5923 __ movsbl($dst$$Register, $mem$$Address); | |
| 5924 %} | |
| 5925 ins_pipe(ialu_reg_mem); | |
| 5926 %} | |
| 5927 | |
| 624 | 5928 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5929 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5930 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5931 effect(KILL cr); |
| 624 | 5932 |
| 5933 ins_cost(250); | |
| 5934 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5935 "XOR $dst.hi,$dst.hi" %} | |
| 5936 | |
| 5937 ins_encode %{ | |
| 5938 __ movzwl($dst$$Register, $mem$$Address); | |
| 5939 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5940 %} | |
| 5941 | |
| 5942 ins_pipe(ialu_reg_mem); | |
| 0 | 5943 %} |
| 5944 | |
| 824 | 5945 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5946 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5947 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5948 effect(KILL cr); | |
| 5949 | |
| 5950 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5951 "XOR $dst.hi,$dst.hi" %} | |
| 5952 ins_encode %{ | |
| 5953 Register Rdst = $dst$$Register; | |
| 5954 __ movzbl(Rdst, $mem$$Address); | |
| 5955 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5956 %} | |
| 5957 ins_pipe(ialu_reg_mem); | |
| 5958 %} | |
| 5959 | |
| 5960 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5961 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5962 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5963 effect(KILL cr); | |
| 5964 | |
| 5965 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5966 "XOR $dst.hi,$dst.hi\n\t" | |
| 5967 "AND $dst.lo,$mask" %} | |
| 5968 ins_encode %{ | |
| 5969 Register Rdst = $dst$$Register; | |
| 5970 __ movzwl(Rdst, $mem$$Address); | |
| 5971 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5972 __ andl(Rdst, $mask$$constant); | |
| 5973 %} | |
| 5974 ins_pipe(ialu_reg_mem); | |
| 5975 %} | |
| 5976 | |
| 0 | 5977 // Load Integer |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5978 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 5979 match(Set dst (LoadI mem)); |
| 5980 | |
| 5981 ins_cost(125); | |
| 624 | 5982 format %{ "MOV $dst,$mem\t# int" %} |
| 5983 | |
| 5984 ins_encode %{ | |
| 5985 __ movl($dst$$Register, $mem$$Address); | |
| 5986 %} | |
| 5987 | |
| 5988 ins_pipe(ialu_reg_mem); | |
| 5989 %} | |
| 5990 | |
| 785 | 5991 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5992 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5993 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 5994 | |
| 5995 ins_cost(125); | |
| 5996 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 5997 ins_encode %{ | |
| 5998 __ movsbl($dst$$Register, $mem$$Address); | |
| 5999 %} | |
| 6000 ins_pipe(ialu_reg_mem); | |
| 6001 %} | |
| 6002 | |
| 6003 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6004 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 6005 match(Set dst (AndI (LoadI mem) mask)); |
| 6006 | |
| 6007 ins_cost(125); | |
| 6008 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6009 ins_encode %{ | |
| 6010 __ movzbl($dst$$Register, $mem$$Address); | |
| 6011 %} | |
| 6012 ins_pipe(ialu_reg_mem); | |
| 6013 %} | |
| 6014 | |
| 6015 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6016 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 6017 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 6018 | |
| 6019 ins_cost(125); | |
| 6020 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6021 ins_encode %{ | |
| 6022 __ movswl($dst$$Register, $mem$$Address); | |
| 6023 %} | |
| 6024 ins_pipe(ialu_reg_mem); | |
| 6025 %} | |
| 6026 | |
| 6027 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6028 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 6029 match(Set dst (AndI (LoadI mem) mask)); |
| 6030 | |
| 6031 ins_cost(125); | |
| 6032 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6033 ins_encode %{ | |
| 6034 __ movzwl($dst$$Register, $mem$$Address); | |
| 6035 %} | |
| 6036 ins_pipe(ialu_reg_mem); | |
| 6037 %} | |
| 6038 | |
| 624 | 6039 // Load Integer into Long Register |
| 824 | 6040 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6041 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6042 effect(KILL cr); |
| 624 | 6043 |
| 6044 ins_cost(375); | |
| 6045 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6046 "MOV $dst.hi,$dst.lo\n\t" | |
| 6047 "SAR $dst.hi,31" %} | |
| 6048 | |
| 6049 ins_encode %{ | |
| 6050 __ movl($dst$$Register, $mem$$Address); | |
| 6051 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6052 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6053 %} | |
| 6054 | |
| 6055 ins_pipe(ialu_reg_mem); | |
| 6056 %} | |
| 6057 | |
| 824 | 6058 // Load Integer with mask 0xFF into Long Register |
| 6059 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6060 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6061 effect(KILL cr); | |
| 6062 | |
| 6063 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6064 "XOR $dst.hi,$dst.hi" %} | |
| 6065 ins_encode %{ | |
| 6066 Register Rdst = $dst$$Register; | |
| 6067 __ movzbl(Rdst, $mem$$Address); | |
| 6068 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6069 %} | |
| 6070 ins_pipe(ialu_reg_mem); | |
| 6071 %} | |
| 6072 | |
| 6073 // Load Integer with mask 0xFFFF into Long Register | |
| 6074 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6075 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6076 effect(KILL cr); | |
| 6077 | |
| 6078 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6079 "XOR $dst.hi,$dst.hi" %} | |
| 6080 ins_encode %{ | |
| 6081 Register Rdst = $dst$$Register; | |
| 6082 __ movzwl(Rdst, $mem$$Address); | |
| 6083 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6084 %} | |
| 6085 ins_pipe(ialu_reg_mem); | |
| 6086 %} | |
| 6087 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
6088 // Load Integer with 31-bit mask into Long Register |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
6089 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ |
| 824 | 6090 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 6091 effect(KILL cr); | |
| 6092 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
6093 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 6094 "XOR $dst.hi,$dst.hi\n\t" |
| 6095 "AND $dst.lo,$mask" %} | |
| 6096 ins_encode %{ | |
| 6097 Register Rdst = $dst$$Register; | |
| 6098 __ movl(Rdst, $mem$$Address); | |
| 6099 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6100 __ andl(Rdst, $mask$$constant); | |
| 6101 %} | |
| 6102 ins_pipe(ialu_reg_mem); | |
| 6103 %} | |
| 6104 | |
| 624 | 6105 // Load Unsigned Integer into Long Register |
| 6849 | 6106 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 6107 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 6108 effect(KILL cr); |
| 624 | 6109 |
| 6110 ins_cost(250); | |
| 6111 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6112 "XOR $dst.hi,$dst.hi" %} | |
| 6113 | |
| 6114 ins_encode %{ | |
| 6115 __ movl($dst$$Register, $mem$$Address); | |
| 6116 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6117 %} | |
| 6118 | |
| 6119 ins_pipe(ialu_reg_mem); | |
| 0 | 6120 %} |
| 6121 | |
| 6122 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6123 // register to ESI | |
| 6124 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6125 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6126 match(Set dst (LoadL mem)); | |
| 6127 | |
| 6128 ins_cost(250); | |
| 624 | 6129 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6130 "MOV $dst.hi,$mem+4" %} |
| 624 | 6131 |
| 6132 ins_encode %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6133 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6134 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 6135 __ movl($dst$$Register, Amemlo); |
| 6136 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6137 %} | |
| 6138 | |
| 6139 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6140 %} |
| 6141 | |
| 6142 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6143 // then store it down to the stack and reload on the int | |
| 6144 // side. | |
| 6145 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6146 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6147 match(Set dst (LoadL mem)); | |
| 6148 | |
| 6149 ins_cost(200); | |
| 6150 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6151 "FISTp $dst" %} | |
| 6152 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6153 ins_pipe( fpu_reg_mem ); | |
| 6154 %} | |
| 6155 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6156 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 6157 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6158 match(Set dst (LoadL mem)); | |
| 6159 effect(TEMP tmp); | |
| 6160 ins_cost(180); | |
| 6161 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6162 "MOVSD $dst,$tmp" %} | |
| 4759 | 6163 ins_encode %{ |
| 6164 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6165 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 6166 %} | |
| 0 | 6167 ins_pipe( pipe_slow ); |
| 6168 %} | |
| 6169 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6170 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 6171 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6172 match(Set dst (LoadL mem)); | |
| 6173 effect(TEMP tmp); | |
| 6174 ins_cost(160); | |
| 6175 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6176 "MOVD $dst.lo,$tmp\n\t" | |
| 6177 "PSRLQ $tmp,32\n\t" | |
| 6178 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 6179 ins_encode %{ |
| 6180 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6181 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 6182 __ psrlq($tmp$$XMMRegister, 32); | |
| 6183 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 6184 %} | |
| 0 | 6185 ins_pipe( pipe_slow ); |
| 6186 %} | |
| 6187 | |
| 6188 // Load Range | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6189 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 6190 match(Set dst (LoadRange mem)); |
| 6191 | |
| 6192 ins_cost(125); | |
| 6193 format %{ "MOV $dst,$mem" %} | |
| 6194 opcode(0x8B); | |
| 6195 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6196 ins_pipe( ialu_reg_mem ); | |
| 6197 %} | |
| 6198 | |
| 6199 | |
| 6200 // Load Pointer | |
| 6201 instruct loadP(eRegP dst, memory mem) %{ | |
| 6202 match(Set dst (LoadP mem)); | |
| 6203 | |
| 6204 ins_cost(125); | |
| 6205 format %{ "MOV $dst,$mem" %} | |
| 6206 opcode(0x8B); | |
| 6207 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6208 ins_pipe( ialu_reg_mem ); | |
| 6209 %} | |
| 6210 | |
| 6211 // Load Klass Pointer | |
| 6212 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6213 match(Set dst (LoadKlass mem)); | |
| 6214 | |
| 6215 ins_cost(125); | |
| 6216 format %{ "MOV $dst,$mem" %} | |
| 6217 opcode(0x8B); | |
| 6218 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6219 ins_pipe( ialu_reg_mem ); | |
| 6220 %} | |
| 6221 | |
| 6222 // Load Double | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6223 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 6224 predicate(UseSSE<=1); |
| 6225 match(Set dst (LoadD mem)); | |
| 6226 | |
| 6227 ins_cost(150); | |
| 6228 format %{ "FLD_D ST,$mem\n\t" | |
| 6229 "FSTP $dst" %} | |
| 6230 opcode(0xDD); /* DD /0 */ | |
| 6231 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6232 Pop_Reg_DPR(dst) ); |
| 0 | 6233 ins_pipe( fpu_reg_mem ); |
| 6234 %} | |
| 6235 | |
| 6236 // Load Double to XMM | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6237 instruct loadD(regD dst, memory mem) %{ |
| 0 | 6238 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 6239 match(Set dst (LoadD mem)); | |
| 6240 ins_cost(145); | |
| 6241 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 6242 ins_encode %{ |
| 6243 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6244 %} | |
| 0 | 6245 ins_pipe( pipe_slow ); |
| 6246 %} | |
| 6247 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6248 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 6249 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 6250 match(Set dst (LoadD mem)); | |
| 6251 ins_cost(145); | |
| 6252 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 6253 ins_encode %{ |
| 6254 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6255 %} | |
| 0 | 6256 ins_pipe( pipe_slow ); |
| 6257 %} | |
| 6258 | |
| 6259 // Load to XMM register (single-precision floating point) | |
| 6260 // MOVSS instruction | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6261 instruct loadF(regF dst, memory mem) %{ |
| 0 | 6262 predicate(UseSSE>=1); |
| 6263 match(Set dst (LoadF mem)); | |
| 6264 ins_cost(145); | |
| 6265 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 6266 ins_encode %{ |
| 6267 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 6268 %} | |
| 0 | 6269 ins_pipe( pipe_slow ); |
| 6270 %} | |
| 6271 | |
| 6272 // Load Float | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6273 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 6274 predicate(UseSSE==0); |
| 6275 match(Set dst (LoadF mem)); | |
| 6276 | |
| 6277 ins_cost(150); | |
| 6278 format %{ "FLD_S ST,$mem\n\t" | |
| 6279 "FSTP $dst" %} | |
| 6280 opcode(0xD9); /* D9 /0 */ | |
| 6281 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6282 Pop_Reg_FPR(dst) ); |
| 0 | 6283 ins_pipe( fpu_reg_mem ); |
| 6284 %} | |
| 6285 | |
| 6286 // Load Effective Address | |
| 6287 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 6288 match(Set dst mem); | |
| 6289 | |
| 6290 ins_cost(110); | |
| 6291 format %{ "LEA $dst,$mem" %} | |
| 6292 opcode(0x8D); | |
| 6293 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6294 ins_pipe( ialu_reg_reg_fat ); | |
| 6295 %} | |
| 6296 | |
| 6297 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 6298 match(Set dst mem); | |
| 6299 | |
| 6300 ins_cost(110); | |
| 6301 format %{ "LEA $dst,$mem" %} | |
| 6302 opcode(0x8D); | |
| 6303 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6304 ins_pipe( ialu_reg_reg_fat ); | |
| 6305 %} | |
| 6306 | |
| 6307 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 6308 match(Set dst mem); | |
| 6309 | |
| 6310 ins_cost(110); | |
| 6311 format %{ "LEA $dst,$mem" %} | |
| 6312 opcode(0x8D); | |
| 6313 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6314 ins_pipe( ialu_reg_reg_fat ); | |
| 6315 %} | |
| 6316 | |
| 6317 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 6318 match(Set dst mem); | |
| 6319 | |
| 6320 ins_cost(110); | |
| 6321 format %{ "LEA $dst,$mem" %} | |
| 6322 opcode(0x8D); | |
| 6323 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6324 ins_pipe( ialu_reg_reg_fat ); | |
| 6325 %} | |
| 6326 | |
| 6327 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 6328 match(Set dst mem); | |
| 6329 | |
| 6330 ins_cost(110); | |
| 6331 format %{ "LEA $dst,$mem" %} | |
| 6332 opcode(0x8D); | |
| 6333 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6334 ins_pipe( ialu_reg_reg_fat ); | |
| 6335 %} | |
| 6336 | |
| 6337 // Load Constant | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6338 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 6339 match(Set dst src); |
| 6340 | |
| 6341 format %{ "MOV $dst,$src" %} | |
| 6342 ins_encode( LdImmI(dst, src) ); | |
| 6343 ins_pipe( ialu_reg_fat ); | |
| 6344 %} | |
| 6345 | |
| 6346 // Load Constant zero | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6347 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 6348 match(Set dst src); |
| 6349 effect(KILL cr); | |
| 6350 | |
| 6351 ins_cost(50); | |
| 6352 format %{ "XOR $dst,$dst" %} | |
| 6353 opcode(0x33); /* + rd */ | |
| 6354 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 6355 ins_pipe( ialu_reg ); | |
| 6356 %} | |
| 6357 | |
| 6358 instruct loadConP(eRegP dst, immP src) %{ | |
| 6359 match(Set dst src); | |
| 6360 | |
| 6361 format %{ "MOV $dst,$src" %} | |
| 6362 opcode(0xB8); /* + rd */ | |
| 6363 ins_encode( LdImmP(dst, src) ); | |
| 6364 ins_pipe( ialu_reg_fat ); | |
| 6365 %} | |
| 6366 | |
| 6367 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 6368 match(Set dst src); | |
| 6369 effect(KILL cr); | |
| 6370 ins_cost(200); | |
| 6371 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 6372 "MOV $dst.hi,$src.hi" %} | |
| 6373 opcode(0xB8); | |
| 6374 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 6375 ins_pipe( ialu_reg_long_fat ); | |
| 6376 %} | |
| 6377 | |
| 6378 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 6379 match(Set dst src); | |
| 6380 effect(KILL cr); | |
| 6381 ins_cost(150); | |
| 6382 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 6383 "XOR $dst.hi,$dst.hi" %} | |
| 6384 opcode(0x33,0x33); | |
| 6385 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 6386 ins_pipe( ialu_reg_long ); | |
| 6387 %} | |
| 6388 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6389 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6390 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 6391 match(Set dst con); |
| 6392 ins_cost(125); | |
| 6393 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 6394 "FSTP $dst" %} | |
| 6395 ins_encode %{ | |
| 6396 __ fld_s($constantaddress($con)); | |
| 6397 __ fstp_d($dst$$reg); | |
| 6398 %} | |
| 6399 ins_pipe(fpu_reg_con); | |
| 6400 %} | |
| 6401 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6402 // The instruction usage is guarded by predicate in operand immFPR0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6403 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 6404 match(Set dst con); |
| 0 | 6405 ins_cost(125); |
| 2008 | 6406 format %{ "FLDZ ST\n\t" |
| 0 | 6407 "FSTP $dst" %} |
| 2008 | 6408 ins_encode %{ |
| 6409 __ fldz(); | |
| 6410 __ fstp_d($dst$$reg); | |
| 6411 %} | |
| 6412 ins_pipe(fpu_reg_con); | |
| 6413 %} | |
| 6414 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6415 // The instruction usage is guarded by predicate in operand immFPR1(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6416 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 6417 match(Set dst con); |
| 6418 ins_cost(125); | |
| 6419 format %{ "FLD1 ST\n\t" | |
| 6420 "FSTP $dst" %} | |
| 6421 ins_encode %{ | |
| 6422 __ fld1(); | |
| 6423 __ fstp_d($dst$$reg); | |
| 6424 %} | |
| 6425 ins_pipe(fpu_reg_con); | |
| 0 | 6426 %} |
| 6427 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6428 // The instruction usage is guarded by predicate in operand immF(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6429 instruct loadConF(regF dst, immF con) %{ |
| 0 | 6430 match(Set dst con); |
| 6431 ins_cost(125); | |
| 2008 | 6432 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 6433 ins_encode %{ | |
| 6434 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 6435 %} | |
| 6436 ins_pipe(pipe_slow); | |
| 0 | 6437 %} |
| 6438 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6439 // The instruction usage is guarded by predicate in operand immF0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6440 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 6441 match(Set dst src); |
| 6442 ins_cost(100); | |
| 6443 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 6444 ins_encode %{ |
| 6445 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6446 %} | |
| 6447 ins_pipe(pipe_slow); | |
| 0 | 6448 %} |
| 6449 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6450 // The instruction usage is guarded by predicate in operand immDPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6451 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 6452 match(Set dst con); |
| 6453 ins_cost(125); | |
| 6454 | |
| 6455 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 6456 "FSTP $dst" %} | |
| 6457 ins_encode %{ | |
| 6458 __ fld_d($constantaddress($con)); | |
| 6459 __ fstp_d($dst$$reg); | |
| 6460 %} | |
| 6461 ins_pipe(fpu_reg_con); | |
| 6462 %} | |
| 6463 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6464 // The instruction usage is guarded by predicate in operand immDPR0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6465 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 6466 match(Set dst con); |
| 0 | 6467 ins_cost(125); |
| 6468 | |
| 2008 | 6469 format %{ "FLDZ ST\n\t" |
| 0 | 6470 "FSTP $dst" %} |
| 2008 | 6471 ins_encode %{ |
| 6472 __ fldz(); | |
| 6473 __ fstp_d($dst$$reg); | |
| 6474 %} | |
| 6475 ins_pipe(fpu_reg_con); | |
| 6476 %} | |
| 6477 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6478 // The instruction usage is guarded by predicate in operand immDPR1(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6479 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 6480 match(Set dst con); |
| 6481 ins_cost(125); | |
| 6482 | |
| 6483 format %{ "FLD1 ST\n\t" | |
| 6484 "FSTP $dst" %} | |
| 6485 ins_encode %{ | |
| 6486 __ fld1(); | |
| 6487 __ fstp_d($dst$$reg); | |
| 6488 %} | |
| 6489 ins_pipe(fpu_reg_con); | |
| 0 | 6490 %} |
| 6491 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6492 // The instruction usage is guarded by predicate in operand immD(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6493 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6494 match(Set dst con); |
| 6495 ins_cost(125); | |
| 2008 | 6496 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6497 ins_encode %{ | |
| 6498 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6499 %} | |
| 6500 ins_pipe(pipe_slow); | |
| 0 | 6501 %} |
| 6502 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6503 // The instruction usage is guarded by predicate in operand immD0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6504 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6505 match(Set dst src); |
| 6506 ins_cost(100); | |
| 6507 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6508 ins_encode %{ |
| 6509 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6510 %} | |
| 0 | 6511 ins_pipe( pipe_slow ); |
| 6512 %} | |
| 6513 | |
| 6514 // Load Stack Slot | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6515 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6516 match(Set dst src); |
| 6517 ins_cost(125); | |
| 6518 | |
| 6519 format %{ "MOV $dst,$src" %} | |
| 6520 opcode(0x8B); | |
| 6521 ins_encode( OpcP, RegMem(dst,src)); | |
| 6522 ins_pipe( ialu_reg_mem ); | |
| 6523 %} | |
| 6524 | |
| 6525 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6526 match(Set dst src); | |
| 6527 | |
| 6528 ins_cost(200); | |
| 6529 format %{ "MOV $dst,$src.lo\n\t" | |
| 6530 "MOV $dst+4,$src.hi" %} | |
| 6531 opcode(0x8B, 0x8B); | |
| 6532 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6533 ins_pipe( ialu_mem_long_reg ); | |
| 6534 %} | |
| 6535 | |
| 6536 // Load Stack Slot | |
| 6537 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6538 match(Set dst src); | |
| 6539 ins_cost(125); | |
| 6540 | |
| 6541 format %{ "MOV $dst,$src" %} | |
| 6542 opcode(0x8B); | |
| 6543 ins_encode( OpcP, RegMem(dst,src)); | |
| 6544 ins_pipe( ialu_reg_mem ); | |
| 6545 %} | |
| 6546 | |
| 6547 // Load Stack Slot | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6548 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6549 match(Set dst src); |
| 6550 ins_cost(125); | |
| 6551 | |
| 6552 format %{ "FLD_S $src\n\t" | |
| 6553 "FSTP $dst" %} | |
| 6554 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6555 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6556 Pop_Reg_FPR(dst) ); |
| 0 | 6557 ins_pipe( fpu_reg_mem ); |
| 6558 %} | |
| 6559 | |
| 6560 // Load Stack Slot | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6561 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6562 match(Set dst src); |
| 6563 ins_cost(125); | |
| 6564 | |
| 6565 format %{ "FLD_D $src\n\t" | |
| 6566 "FSTP $dst" %} | |
| 6567 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6568 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6569 Pop_Reg_DPR(dst) ); |
| 0 | 6570 ins_pipe( fpu_reg_mem ); |
| 6571 %} | |
| 6572 | |
| 6573 // Prefetch instructions. | |
| 6574 // Must be safe to execute with invalid address (cannot fault). | |
| 6575 | |
| 6576 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6577 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6578 match(PrefetchRead mem); |
| 6579 ins_cost(0); | |
| 6580 size(0); | |
| 6581 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6582 ins_encode(); | |
| 6583 ins_pipe(empty); | |
| 6584 %} | |
| 6585 | |
| 6586 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6587 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6588 match(PrefetchRead mem); |
| 6589 ins_cost(100); | |
| 6590 | |
| 6591 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6592 ins_encode %{ |
| 6593 __ prefetchr($mem$$Address); | |
| 6594 %} | |
| 0 | 6595 ins_pipe(ialu_mem); |
| 6596 %} | |
| 6597 | |
| 6598 instruct prefetchrNTA( memory mem ) %{ | |
| 6599 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6600 match(PrefetchRead mem); | |
| 6601 ins_cost(100); | |
| 6602 | |
| 6603 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6604 ins_encode %{ |
| 6605 __ prefetchnta($mem$$Address); | |
| 6606 %} | |
| 0 | 6607 ins_pipe(ialu_mem); |
| 6608 %} | |
| 6609 | |
| 6610 instruct prefetchrT0( memory mem ) %{ | |
| 6611 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6612 match(PrefetchRead mem); | |
| 6613 ins_cost(100); | |
| 6614 | |
| 6615 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6616 ins_encode %{ |
| 6617 __ prefetcht0($mem$$Address); | |
| 6618 %} | |
| 0 | 6619 ins_pipe(ialu_mem); |
| 6620 %} | |
| 6621 | |
| 6622 instruct prefetchrT2( memory mem ) %{ | |
| 6623 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6624 match(PrefetchRead mem); | |
| 6625 ins_cost(100); | |
| 6626 | |
| 6627 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6628 ins_encode %{ |
| 6629 __ prefetcht2($mem$$Address); | |
| 6630 %} | |
| 0 | 6631 ins_pipe(ialu_mem); |
| 6632 %} | |
| 6633 | |
| 6634 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6635 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6636 match(PrefetchWrite mem); |
| 6637 ins_cost(0); | |
| 6638 size(0); | |
| 6639 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6640 ins_encode(); | |
| 6641 ins_pipe(empty); | |
| 6642 %} | |
| 6643 | |
| 6644 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6645 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6646 match( PrefetchWrite mem ); |
| 6647 ins_cost(100); | |
| 6648 | |
| 6649 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6650 ins_encode %{ |
| 6651 __ prefetchw($mem$$Address); | |
| 6652 %} | |
| 0 | 6653 ins_pipe(ialu_mem); |
| 6654 %} | |
| 6655 | |
| 6656 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6657 predicate(UseSSE>=1); |
| 0 | 6658 match(PrefetchWrite mem); |
| 6659 ins_cost(100); | |
| 6660 | |
| 6661 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6662 ins_encode %{ |
| 6663 __ prefetchnta($mem$$Address); | |
| 6664 %} | |
| 0 | 6665 ins_pipe(ialu_mem); |
| 6666 %} | |
| 6667 | |
| 3854 | 6668 // Prefetch instructions for allocation. |
| 6669 | |
| 6670 instruct prefetchAlloc0( memory mem ) %{ | |
| 6671 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6672 match(PrefetchAllocation mem); | |
| 6673 ins_cost(0); | |
| 6674 size(0); | |
| 6675 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6676 ins_encode(); | |
| 6677 ins_pipe(empty); | |
| 6678 %} | |
| 6679 | |
| 6680 instruct prefetchAlloc( memory mem ) %{ | |
| 6681 predicate(AllocatePrefetchInstr==3); | |
| 6682 match( PrefetchAllocation mem ); | |
| 0 | 6683 ins_cost(100); |
| 6684 | |
| 3854 | 6685 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6686 ins_encode %{ | |
| 6687 __ prefetchw($mem$$Address); | |
| 6688 %} | |
| 6689 ins_pipe(ialu_mem); | |
| 6690 %} | |
| 6691 | |
| 6692 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6693 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6694 match(PrefetchAllocation mem); | |
| 6695 ins_cost(100); | |
| 6696 | |
| 6697 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6698 ins_encode %{ | |
| 6699 __ prefetchnta($mem$$Address); | |
| 6700 %} | |
| 0 | 6701 ins_pipe(ialu_mem); |
| 6702 %} | |
| 6703 | |
| 3854 | 6704 instruct prefetchAllocT0( memory mem ) %{ |
| 6705 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6706 match(PrefetchAllocation mem); | |
| 0 | 6707 ins_cost(100); |
| 6708 | |
| 3854 | 6709 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6710 ins_encode %{ | |
| 6711 __ prefetcht0($mem$$Address); | |
| 6712 %} | |
| 6713 ins_pipe(ialu_mem); | |
| 6714 %} | |
| 6715 | |
| 6716 instruct prefetchAllocT2( memory mem ) %{ | |
| 6717 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6718 match(PrefetchAllocation mem); | |
| 6719 ins_cost(100); | |
| 6720 | |
| 6721 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6722 ins_encode %{ | |
| 6723 __ prefetcht2($mem$$Address); | |
| 6724 %} | |
| 0 | 6725 ins_pipe(ialu_mem); |
| 6726 %} | |
| 6727 | |
| 6728 //----------Store Instructions------------------------------------------------- | |
| 6729 | |
| 6730 // Store Byte | |
| 6731 instruct storeB(memory mem, xRegI src) %{ | |
| 6732 match(Set mem (StoreB mem src)); | |
| 6733 | |
| 6734 ins_cost(125); | |
| 6735 format %{ "MOV8 $mem,$src" %} | |
| 6736 opcode(0x88); | |
| 6737 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6738 ins_pipe( ialu_mem_reg ); | |
| 6739 %} | |
| 6740 | |
| 6741 // Store Char/Short | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6742 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6743 match(Set mem (StoreC mem src)); |
| 6744 | |
| 6745 ins_cost(125); | |
| 6746 format %{ "MOV16 $mem,$src" %} | |
| 6747 opcode(0x89, 0x66); | |
| 6748 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6749 ins_pipe( ialu_mem_reg ); | |
| 6750 %} | |
| 6751 | |
| 6752 // Store Integer | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6753 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6754 match(Set mem (StoreI mem src)); |
| 6755 | |
| 6756 ins_cost(125); | |
| 6757 format %{ "MOV $mem,$src" %} | |
| 6758 opcode(0x89); | |
| 6759 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6760 ins_pipe( ialu_mem_reg ); | |
| 6761 %} | |
| 6762 | |
| 6763 // Store Long | |
| 6764 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6765 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6766 match(Set mem (StoreL mem src)); | |
| 6767 | |
| 6768 ins_cost(200); | |
| 6769 format %{ "MOV $mem,$src.lo\n\t" | |
| 6770 "MOV $mem+4,$src.hi" %} | |
| 6771 opcode(0x89, 0x89); | |
| 6772 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6773 ins_pipe( ialu_mem_long_reg ); | |
| 6774 %} | |
| 6775 | |
| 824 | 6776 // Store Long to Integer |
| 6777 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6778 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6779 | |
| 6780 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6781 ins_encode %{ | |
| 6782 __ movl($mem$$Address, $src$$Register); | |
| 6783 %} | |
| 6784 ins_pipe(ialu_mem_reg); | |
| 6785 %} | |
| 6786 | |
| 0 | 6787 // Volatile Store Long. Must be atomic, so move it into |
| 6788 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6789 // target address before the store (for null-ptr checks) | |
| 6790 // so the memory operand is used twice in the encoding. | |
| 6791 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6792 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6793 match(Set mem (StoreL mem src)); | |
| 6794 effect( KILL cr ); | |
| 6795 ins_cost(400); | |
| 6796 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6797 "FILD $src\n\t" | |
| 6798 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6799 opcode(0x3B); | |
| 6800 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6801 ins_pipe( fpu_reg_mem ); | |
| 6802 %} | |
| 6803 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6804 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6805 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6806 match(Set mem (StoreL mem src)); | |
| 6807 effect( TEMP tmp, KILL cr ); | |
| 6808 ins_cost(380); | |
| 6809 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6810 "MOVSD $tmp,$src\n\t" | |
| 6811 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6812 ins_encode %{ |
| 6813 __ cmpl(rax, $mem$$Address); | |
| 6814 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6815 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6816 %} | |
| 0 | 6817 ins_pipe( pipe_slow ); |
| 6818 %} | |
| 6819 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6820 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6821 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6822 match(Set mem (StoreL mem src)); | |
| 6823 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6824 ins_cost(360); | |
| 6825 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6826 "MOVD $tmp,$src.lo\n\t" | |
| 6827 "MOVD $tmp2,$src.hi\n\t" | |
| 6828 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6829 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6830 ins_encode %{ |
| 6831 __ cmpl(rax, $mem$$Address); | |
| 6832 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6833 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6834 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6835 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6836 %} | |
| 0 | 6837 ins_pipe( pipe_slow ); |
| 6838 %} | |
| 6839 | |
| 6840 // Store Pointer; for storing unknown oops and raw pointers | |
| 6841 instruct storeP(memory mem, anyRegP src) %{ | |
| 6842 match(Set mem (StoreP mem src)); | |
| 6843 | |
| 6844 ins_cost(125); | |
| 6845 format %{ "MOV $mem,$src" %} | |
| 6846 opcode(0x89); | |
| 6847 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6848 ins_pipe( ialu_mem_reg ); | |
| 6849 %} | |
| 6850 | |
| 6851 // Store Integer Immediate | |
| 6852 instruct storeImmI(memory mem, immI src) %{ | |
| 6853 match(Set mem (StoreI mem src)); | |
| 6854 | |
| 6855 ins_cost(150); | |
| 6856 format %{ "MOV $mem,$src" %} | |
| 6857 opcode(0xC7); /* C7 /0 */ | |
| 6858 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6859 ins_pipe( ialu_mem_imm ); | |
| 6860 %} | |
| 6861 | |
| 6862 // Store Short/Char Immediate | |
| 6863 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6864 predicate(UseStoreImmI16); | |
| 6865 match(Set mem (StoreC mem src)); | |
| 6866 | |
| 6867 ins_cost(150); | |
| 6868 format %{ "MOV16 $mem,$src" %} | |
| 6869 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6870 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6871 ins_pipe( ialu_mem_imm ); | |
| 6872 %} | |
| 6873 | |
| 6874 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6875 // need card-mark barriers. | |
| 6876 instruct storeImmP(memory mem, immP src) %{ | |
| 6877 match(Set mem (StoreP mem src)); | |
| 6878 | |
| 6879 ins_cost(150); | |
| 6880 format %{ "MOV $mem,$src" %} | |
| 6881 opcode(0xC7); /* C7 /0 */ | |
| 6882 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6883 ins_pipe( ialu_mem_imm ); | |
| 6884 %} | |
| 6885 | |
| 6886 // Store Byte Immediate | |
| 6887 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6888 match(Set mem (StoreB mem src)); | |
| 6889 | |
| 6890 ins_cost(150); | |
| 6891 format %{ "MOV8 $mem,$src" %} | |
| 6892 opcode(0xC6); /* C6 /0 */ | |
| 6893 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6894 ins_pipe( ialu_mem_imm ); | |
| 6895 %} | |
| 6896 | |
| 6897 // Store CMS card-mark Immediate | |
| 6898 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6899 match(Set mem (StoreCM mem src)); | |
| 6900 | |
| 6901 ins_cost(150); | |
| 6902 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6903 opcode(0xC6); /* C6 /0 */ | |
| 6904 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6905 ins_pipe( ialu_mem_imm ); | |
| 6906 %} | |
| 6907 | |
| 6908 // Store Double | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6909 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6910 predicate(UseSSE<=1); |
| 6911 match(Set mem (StoreD mem src)); | |
| 6912 | |
| 6913 ins_cost(100); | |
| 6914 format %{ "FST_D $mem,$src" %} | |
| 6915 opcode(0xDD); /* DD /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6916 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6917 ins_pipe( fpu_mem_reg ); |
| 6918 %} | |
| 6919 | |
| 6920 // Store double does rounding on x86 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6921 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6922 predicate(UseSSE<=1); |
| 6923 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6924 | |
| 6925 ins_cost(100); | |
| 6926 format %{ "FST_D $mem,$src\t# round" %} | |
| 6927 opcode(0xDD); /* DD /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6928 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6929 ins_pipe( fpu_mem_reg ); |
| 6930 %} | |
| 6931 | |
| 6932 // Store XMM register to memory (double-precision floating points) | |
| 6933 // MOVSD instruction | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6934 instruct storeD(memory mem, regD src) %{ |
| 0 | 6935 predicate(UseSSE>=2); |
| 6936 match(Set mem (StoreD mem src)); | |
| 6937 ins_cost(95); | |
| 6938 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6939 ins_encode %{ |
| 6940 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6941 %} | |
| 0 | 6942 ins_pipe( pipe_slow ); |
| 6943 %} | |
| 6944 | |
| 6945 // Store XMM register to memory (single-precision floating point) | |
| 6946 // MOVSS instruction | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6947 instruct storeF(memory mem, regF src) %{ |
| 0 | 6948 predicate(UseSSE>=1); |
| 6949 match(Set mem (StoreF mem src)); | |
| 6950 ins_cost(95); | |
| 6951 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6952 ins_encode %{ |
| 6953 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6954 %} | |
| 0 | 6955 ins_pipe( pipe_slow ); |
| 6956 %} | |
| 6957 | |
| 6958 // Store Float | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6959 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 6960 predicate(UseSSE==0); |
| 6961 match(Set mem (StoreF mem src)); | |
| 6962 | |
| 6963 ins_cost(100); | |
| 6964 format %{ "FST_S $mem,$src" %} | |
| 6965 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6966 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6967 ins_pipe( fpu_mem_reg ); |
| 6968 %} | |
| 6969 | |
| 6970 // Store Float does rounding on x86 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6971 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 6972 predicate(UseSSE==0); |
| 6973 match(Set mem (StoreF mem (RoundFloat src))); | |
| 6974 | |
| 6975 ins_cost(100); | |
| 6976 format %{ "FST_S $mem,$src\t# round" %} | |
| 6977 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6978 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6979 ins_pipe( fpu_mem_reg ); |
| 6980 %} | |
| 6981 | |
| 6982 // Store Float does rounding on x86 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6983 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 6984 predicate(UseSSE<=1); |
| 6985 match(Set mem (StoreF mem (ConvD2F src))); | |
| 6986 | |
| 6987 ins_cost(100); | |
| 6988 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 6989 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6990 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6991 ins_pipe( fpu_mem_reg ); |
| 6992 %} | |
| 6993 | |
| 6994 // Store immediate Float value (it is faster than store from FPU register) | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6995 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6996 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6997 match(Set mem (StoreF mem src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6998 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6999 ins_cost(50); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7000 format %{ "MOV $mem,$src\t# store float" %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7001 opcode(0xC7); /* C7 /0 */ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7002 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7003 ins_pipe( ialu_mem_imm ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7004 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7005 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7006 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 7007 // The instruction usage is guarded by predicate in operand immF(). |
| 7008 instruct storeF_imm( memory mem, immF src) %{ | |
| 7009 match(Set mem (StoreF mem src)); | |
| 7010 | |
| 7011 ins_cost(50); | |
| 7012 format %{ "MOV $mem,$src\t# store float" %} | |
| 7013 opcode(0xC7); /* C7 /0 */ | |
| 7014 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7015 ins_pipe( ialu_mem_imm ); | |
| 7016 %} | |
| 7017 | |
| 7018 // Store Integer to stack slot | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7019 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 7020 match(Set dst src); |
| 7021 | |
| 7022 ins_cost(100); | |
| 7023 format %{ "MOV $dst,$src" %} | |
| 7024 opcode(0x89); | |
| 7025 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7026 ins_pipe( ialu_mem_reg ); | |
| 7027 %} | |
| 7028 | |
| 7029 // Store Integer to stack slot | |
| 7030 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7031 match(Set dst src); | |
| 7032 | |
| 7033 ins_cost(100); | |
| 7034 format %{ "MOV $dst,$src" %} | |
| 7035 opcode(0x89); | |
| 7036 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7037 ins_pipe( ialu_mem_reg ); | |
| 7038 %} | |
| 7039 | |
| 7040 // Store Long to stack slot | |
| 7041 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7042 match(Set dst src); | |
| 7043 | |
| 7044 ins_cost(200); | |
| 7045 format %{ "MOV $dst,$src.lo\n\t" | |
| 7046 "MOV $dst+4,$src.hi" %} | |
| 7047 opcode(0x89, 0x89); | |
| 7048 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7049 ins_pipe( ialu_mem_long_reg ); | |
| 7050 %} | |
| 7051 | |
| 7052 //----------MemBar Instructions----------------------------------------------- | |
| 7053 // Memory barrier flavors | |
| 7054 | |
| 7055 instruct membar_acquire() %{ | |
| 7056 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
7057 match(LoadFence); |
| 0 | 7058 ins_cost(400); |
| 7059 | |
| 7060 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7061 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7062 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7063 ins_pipe(empty); |
| 0 | 7064 %} |
| 7065 | |
| 7066 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
7067 match(MemBarAcquireLock); |
| 0 | 7068 ins_cost(0); |
| 7069 | |
| 7070 size(0); | |
| 7071 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7072 ins_encode( ); | |
| 7073 ins_pipe(empty); | |
| 7074 %} | |
| 7075 | |
| 7076 instruct membar_release() %{ | |
| 7077 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
7078 match(StoreFence); |
| 0 | 7079 ins_cost(400); |
| 7080 | |
| 7081 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7082 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7083 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7084 ins_pipe(empty); |
| 0 | 7085 %} |
| 7086 | |
| 7087 instruct membar_release_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
7088 match(MemBarReleaseLock); |
| 0 | 7089 ins_cost(0); |
| 7090 | |
| 7091 size(0); | |
| 7092 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7093 ins_encode( ); | |
| 7094 ins_pipe(empty); | |
| 7095 %} | |
| 7096 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7097 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7098 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7099 effect(KILL cr); |
| 0 | 7100 ins_cost(400); |
| 7101 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7102 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7103 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7104 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7105 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7106 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7107 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7108 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7109 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7110 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7111 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7112 %} |
| 0 | 7113 ins_pipe(pipe_slow); |
| 7114 %} | |
| 7115 | |
| 7116 instruct unnecessary_membar_volatile() %{ | |
| 7117 match(MemBarVolatile); | |
| 7118 predicate(Matcher::post_store_load_barrier(n)); | |
| 7119 ins_cost(0); | |
| 7120 | |
| 7121 size(0); | |
| 7122 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7123 ins_encode( ); | |
| 7124 ins_pipe(empty); | |
| 7125 %} | |
| 7126 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7127 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7128 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7129 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7130 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7131 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7132 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7133 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7134 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7135 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7136 |
| 0 | 7137 //----------Move Instructions-------------------------------------------------- |
| 7138 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7139 match(Set dst (CastX2P src)); | |
| 7140 format %{ "# X2P $dst, $src" %} | |
| 7141 ins_encode( /*empty encoding*/ ); | |
| 7142 ins_cost(0); | |
| 7143 ins_pipe(empty); | |
| 7144 %} | |
| 7145 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7146 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 7147 match(Set dst (CastP2X src)); |
| 7148 ins_cost(50); | |
| 7149 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7150 ins_encode( enc_Copy( dst, src) ); | |
| 7151 ins_pipe( ialu_reg_reg ); | |
| 7152 %} | |
| 7153 | |
| 7154 //----------Conditional Move--------------------------------------------------- | |
| 7155 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7156 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 7157 predicate(!VM_Version::supports_cmov() ); |
| 7158 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7159 ins_cost(200); | |
| 7160 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 7161 "MOV $dst,$src\n" | |
| 7162 "skip:" %} | |
| 7163 ins_encode %{ | |
| 7164 Label Lskip; | |
| 7165 // Invert sense of branch from sense of CMOV | |
| 7166 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7167 __ movl($dst$$Register, $src$$Register); | |
| 7168 __ bind(Lskip); | |
| 7169 %} | |
| 7170 ins_pipe( pipe_cmov_reg ); | |
| 7171 %} | |
| 7172 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7173 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 7174 predicate(!VM_Version::supports_cmov() ); |
| 7175 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7176 ins_cost(200); | |
| 7177 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 7178 "MOV $dst,$src\n" | |
| 7179 "skip:" %} | |
| 7180 ins_encode %{ | |
| 7181 Label Lskip; | |
| 7182 // Invert sense of branch from sense of CMOV | |
| 7183 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7184 __ movl($dst$$Register, $src$$Register); | |
| 7185 __ bind(Lskip); | |
| 7186 %} | |
| 7187 ins_pipe( pipe_cmov_reg ); | |
| 7188 %} | |
| 7189 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7190 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 7191 predicate(VM_Version::supports_cmov() ); |
| 7192 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7193 ins_cost(200); | |
| 7194 format %{ "CMOV$cop $dst,$src" %} | |
| 7195 opcode(0x0F,0x40); | |
| 7196 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7197 ins_pipe( pipe_cmov_reg ); | |
| 7198 %} | |
| 7199 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7200 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 7201 predicate(VM_Version::supports_cmov() ); |
| 7202 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7203 ins_cost(200); | |
| 7204 format %{ "CMOV$cop $dst,$src" %} | |
| 7205 opcode(0x0F,0x40); | |
| 7206 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7207 ins_pipe( pipe_cmov_reg ); | |
| 7208 %} | |
| 7209 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7210 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7211 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7212 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7213 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7214 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7215 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7216 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7217 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7218 |
| 0 | 7219 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7220 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7221 predicate(VM_Version::supports_cmov() ); |
| 7222 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7223 ins_cost(250); | |
| 7224 format %{ "CMOV$cop $dst,$src" %} | |
| 7225 opcode(0x0F,0x40); | |
| 7226 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7227 ins_pipe( pipe_cmov_mem ); | |
| 7228 %} | |
| 7229 | |
| 7230 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7231 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 7232 predicate(VM_Version::supports_cmov() ); |
| 7233 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7234 ins_cost(250); | |
| 7235 format %{ "CMOV$cop $dst,$src" %} | |
| 7236 opcode(0x0F,0x40); | |
| 7237 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7238 ins_pipe( pipe_cmov_mem ); | |
| 7239 %} | |
| 7240 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7241 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7242 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7243 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7244 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7245 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7246 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7247 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7248 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7249 |
| 0 | 7250 // Conditional move |
| 7251 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7252 predicate(VM_Version::supports_cmov() ); | |
| 7253 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7254 ins_cost(200); | |
| 7255 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7256 opcode(0x0F,0x40); | |
| 7257 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7258 ins_pipe( pipe_cmov_reg ); | |
| 7259 %} | |
| 7260 | |
| 7261 // Conditional move (non-P6 version) | |
| 7262 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7263 // regardless of whether we are on a P6, so we | |
| 7264 // emulate a cmov here | |
| 7265 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7266 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7267 ins_cost(300); | |
| 7268 format %{ "Jn$cop skip\n\t" | |
| 7269 "MOV $dst,$src\t# pointer\n" | |
| 7270 "skip:" %} | |
| 7271 opcode(0x8b); | |
| 7272 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7273 ins_pipe( pipe_cmov_reg ); | |
| 7274 %} | |
| 7275 | |
| 7276 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7277 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7278 predicate(VM_Version::supports_cmov() ); |
| 7279 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7280 ins_cost(200); | |
| 7281 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7282 opcode(0x0F,0x40); | |
| 7283 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7284 ins_pipe( pipe_cmov_reg ); | |
| 7285 %} | |
| 7286 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7287 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7288 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7289 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7290 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7291 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7292 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7293 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7294 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7295 |
| 0 | 7296 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7297 // correctly meets the two pointer arguments; one is an incoming | |
| 7298 // register but the other is a memory operand. ALSO appears to | |
| 7299 // be buggy with implicit null checks. | |
| 7300 // | |
| 7301 //// Conditional move | |
| 7302 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7303 // predicate(VM_Version::supports_cmov() ); | |
| 7304 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7305 // ins_cost(250); | |
| 7306 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7307 // opcode(0x0F,0x40); | |
| 7308 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7309 // ins_pipe( pipe_cmov_mem ); | |
| 7310 //%} | |
| 7311 // | |
| 7312 //// Conditional move | |
| 7313 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 7314 // predicate(VM_Version::supports_cmov() ); | |
| 7315 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7316 // ins_cost(250); | |
| 7317 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7318 // opcode(0x0F,0x40); | |
| 7319 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7320 // ins_pipe( pipe_cmov_mem ); | |
| 7321 //%} | |
| 7322 | |
| 7323 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7324 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 7325 predicate(UseSSE<=1); |
| 7326 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7327 ins_cost(200); | |
| 7328 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 7329 opcode(0xDA); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7330 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7331 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7332 %} |
| 7333 | |
| 7334 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7335 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 7336 predicate(UseSSE==0); |
| 7337 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7338 ins_cost(200); | |
| 7339 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 7340 opcode(0xDA); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7341 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7342 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7343 %} |
| 7344 | |
| 7345 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7346 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 7347 predicate(UseSSE<=1); |
| 7348 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7349 ins_cost(200); | |
| 7350 format %{ "Jn$cop skip\n\t" | |
| 7351 "MOV $dst,$src\t# double\n" | |
| 7352 "skip:" %} | |
| 7353 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7354 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7355 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7356 %} |
| 7357 | |
| 7358 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7359 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 7360 predicate(UseSSE==0); |
| 7361 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7362 ins_cost(200); | |
| 7363 format %{ "Jn$cop skip\n\t" | |
| 7364 "MOV $dst,$src\t# float\n" | |
| 7365 "skip:" %} | |
| 7366 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7367 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7368 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7369 %} |
| 7370 | |
| 7371 // No CMOVE with SSE/SSE2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7372 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 7373 predicate (UseSSE>=1); |
| 7374 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7375 ins_cost(200); | |
| 7376 format %{ "Jn$cop skip\n\t" | |
| 7377 "MOVSS $dst,$src\t# float\n" | |
| 7378 "skip:" %} | |
| 7379 ins_encode %{ | |
| 7380 Label skip; | |
| 7381 // Invert sense of branch from sense of CMOV | |
| 7382 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7383 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7384 __ bind(skip); | |
| 7385 %} | |
| 7386 ins_pipe( pipe_slow ); | |
| 7387 %} | |
| 7388 | |
| 7389 // No CMOVE with SSE/SSE2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7390 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 7391 predicate (UseSSE>=2); |
| 7392 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7393 ins_cost(200); | |
| 7394 format %{ "Jn$cop skip\n\t" | |
| 7395 "MOVSD $dst,$src\t# float\n" | |
| 7396 "skip:" %} | |
| 7397 ins_encode %{ | |
| 7398 Label skip; | |
| 7399 // Invert sense of branch from sense of CMOV | |
| 7400 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7401 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7402 __ bind(skip); | |
| 7403 %} | |
| 7404 ins_pipe( pipe_slow ); | |
| 7405 %} | |
| 7406 | |
| 7407 // unsigned version | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7408 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 7409 predicate (UseSSE>=1); |
| 7410 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7411 ins_cost(200); | |
| 7412 format %{ "Jn$cop skip\n\t" | |
| 7413 "MOVSS $dst,$src\t# float\n" | |
| 7414 "skip:" %} | |
| 7415 ins_encode %{ | |
| 7416 Label skip; | |
| 7417 // Invert sense of branch from sense of CMOV | |
| 7418 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7419 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7420 __ bind(skip); | |
| 7421 %} | |
| 7422 ins_pipe( pipe_slow ); | |
| 7423 %} | |
| 7424 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7425 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7426 predicate (UseSSE>=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7427 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7428 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7429 expand %{ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7430 fcmovF_regU(cop, cr, dst, src); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7431 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7432 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7433 |
| 0 | 7434 // unsigned version |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7435 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 7436 predicate (UseSSE>=2); |
| 7437 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7438 ins_cost(200); | |
| 7439 format %{ "Jn$cop skip\n\t" | |
| 7440 "MOVSD $dst,$src\t# float\n" | |
| 7441 "skip:" %} | |
| 7442 ins_encode %{ | |
| 7443 Label skip; | |
| 7444 // Invert sense of branch from sense of CMOV | |
| 7445 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7446 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7447 __ bind(skip); | |
| 7448 %} | |
| 7449 ins_pipe( pipe_slow ); | |
| 7450 %} | |
| 7451 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7452 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7453 predicate (UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7454 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7455 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7456 expand %{ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7457 fcmovD_regU(cop, cr, dst, src); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7458 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7459 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7460 |
| 0 | 7461 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 7462 predicate(VM_Version::supports_cmov() ); | |
| 7463 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7464 ins_cost(200); | |
| 7465 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7466 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7467 opcode(0x0F,0x40); | |
| 7468 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7469 ins_pipe( pipe_cmov_reg_long ); | |
| 7470 %} | |
| 7471 | |
| 7472 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 7473 predicate(VM_Version::supports_cmov() ); | |
| 7474 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7475 ins_cost(200); | |
| 7476 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7477 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7478 opcode(0x0F,0x40); | |
| 7479 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7480 ins_pipe( pipe_cmov_reg_long ); | |
| 7481 %} | |
| 7482 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7483 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7484 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7485 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7486 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7487 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7488 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7489 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7490 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7491 |
| 0 | 7492 //----------Arithmetic Instructions-------------------------------------------- |
| 7493 //----------Addition Instructions---------------------------------------------- | |
| 12323 | 7494 |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7495 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) |
| 12323 | 7496 %{ |
| 7497 match(AddExactI dst src); | |
| 7498 effect(DEF cr); | |
| 7499 | |
| 7500 format %{ "ADD $dst, $src\t# addExact int" %} | |
| 7501 ins_encode %{ | |
| 7502 __ addl($dst$$Register, $src$$Register); | |
| 7503 %} | |
| 7504 ins_pipe(ialu_reg_reg); | |
| 7505 %} | |
| 7506 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7507 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) |
| 12323 | 7508 %{ |
| 7509 match(AddExactI dst src); | |
| 7510 effect(DEF cr); | |
| 7511 | |
| 7512 format %{ "ADD $dst, $src\t# addExact int" %} | |
| 7513 ins_encode %{ | |
| 7514 __ addl($dst$$Register, $src$$constant); | |
| 7515 %} | |
| 7516 ins_pipe(ialu_reg_reg); | |
| 7517 %} | |
| 7518 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7519 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7520 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7521 match(AddExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7522 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7523 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7524 ins_cost(125); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7525 format %{ "ADD $dst,$src\t# addExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7526 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7527 __ addl($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7528 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7529 ins_pipe( ialu_reg_mem ); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7530 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7531 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7532 |
| 0 | 7533 // Integer Addition Instructions |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7534 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7535 match(Set dst (AddI dst src)); |
| 7536 effect(KILL cr); | |
| 7537 | |
| 7538 size(2); | |
| 7539 format %{ "ADD $dst,$src" %} | |
| 7540 opcode(0x03); | |
| 7541 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7542 ins_pipe( ialu_reg_reg ); | |
| 7543 %} | |
| 7544 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7545 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7546 match(Set dst (AddI dst src)); |
| 7547 effect(KILL cr); | |
| 7548 | |
| 7549 format %{ "ADD $dst,$src" %} | |
| 7550 opcode(0x81, 0x00); /* /0 id */ | |
| 7551 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7552 ins_pipe( ialu_reg ); | |
| 7553 %} | |
| 7554 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7555 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7556 predicate(UseIncDec); |
| 7557 match(Set dst (AddI dst src)); | |
| 7558 effect(KILL cr); | |
| 7559 | |
| 7560 size(1); | |
| 7561 format %{ "INC $dst" %} | |
| 7562 opcode(0x40); /* */ | |
| 7563 ins_encode( Opc_plus( primary, dst ) ); | |
| 7564 ins_pipe( ialu_reg ); | |
| 7565 %} | |
| 7566 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7567 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7568 match(Set dst (AddI src0 src1)); |
| 7569 ins_cost(110); | |
| 7570 | |
| 7571 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7572 opcode(0x8D); /* 0x8D /r */ | |
| 7573 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7574 ins_pipe( ialu_reg_reg ); | |
| 7575 %} | |
| 7576 | |
| 7577 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7578 match(Set dst (AddP src0 src1)); | |
| 7579 ins_cost(110); | |
| 7580 | |
| 7581 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7582 opcode(0x8D); /* 0x8D /r */ | |
| 7583 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7584 ins_pipe( ialu_reg_reg ); | |
| 7585 %} | |
| 7586 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7587 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7588 predicate(UseIncDec); |
| 7589 match(Set dst (AddI dst src)); | |
| 7590 effect(KILL cr); | |
| 7591 | |
| 7592 size(1); | |
| 7593 format %{ "DEC $dst" %} | |
| 7594 opcode(0x48); /* */ | |
| 7595 ins_encode( Opc_plus( primary, dst ) ); | |
| 7596 ins_pipe( ialu_reg ); | |
| 7597 %} | |
| 7598 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7599 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7600 match(Set dst (AddP dst src)); |
| 7601 effect(KILL cr); | |
| 7602 | |
| 7603 size(2); | |
| 7604 format %{ "ADD $dst,$src" %} | |
| 7605 opcode(0x03); | |
| 7606 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7607 ins_pipe( ialu_reg_reg ); | |
| 7608 %} | |
| 7609 | |
| 7610 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7611 match(Set dst (AddP dst src)); | |
| 7612 effect(KILL cr); | |
| 7613 | |
| 7614 format %{ "ADD $dst,$src" %} | |
| 7615 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7616 // ins_encode( RegImm( dst, src) ); | |
| 7617 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7618 ins_pipe( ialu_reg ); | |
| 7619 %} | |
| 7620 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7621 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7622 match(Set dst (AddI dst (LoadI src))); |
| 7623 effect(KILL cr); | |
| 7624 | |
| 7625 ins_cost(125); | |
| 7626 format %{ "ADD $dst,$src" %} | |
| 7627 opcode(0x03); | |
| 7628 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7629 ins_pipe( ialu_reg_mem ); | |
| 7630 %} | |
| 7631 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7632 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7633 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7634 effect(KILL cr); | |
| 7635 | |
| 7636 ins_cost(150); | |
| 7637 format %{ "ADD $dst,$src" %} | |
| 7638 opcode(0x01); /* Opcode 01 /r */ | |
| 7639 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7640 ins_pipe( ialu_mem_reg ); | |
| 7641 %} | |
| 7642 | |
| 7643 // Add Memory with Immediate | |
| 7644 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7645 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7646 effect(KILL cr); | |
| 7647 | |
| 7648 ins_cost(125); | |
| 7649 format %{ "ADD $dst,$src" %} | |
| 7650 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7651 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7652 ins_pipe( ialu_mem_imm ); | |
| 7653 %} | |
| 7654 | |
| 7655 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7656 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7657 effect(KILL cr); | |
| 7658 | |
| 7659 ins_cost(125); | |
| 7660 format %{ "INC $dst" %} | |
| 7661 opcode(0xFF); /* Opcode FF /0 */ | |
| 7662 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7663 ins_pipe( ialu_mem_imm ); | |
| 7664 %} | |
| 7665 | |
| 7666 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7667 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7668 effect(KILL cr); | |
| 7669 | |
| 7670 ins_cost(125); | |
| 7671 format %{ "DEC $dst" %} | |
| 7672 opcode(0xFF); /* Opcode FF /1 */ | |
| 7673 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7674 ins_pipe( ialu_mem_imm ); | |
| 7675 %} | |
| 7676 | |
| 7677 | |
| 7678 instruct checkCastPP( eRegP dst ) %{ | |
| 7679 match(Set dst (CheckCastPP dst)); | |
| 7680 | |
| 7681 size(0); | |
| 7682 format %{ "#checkcastPP of $dst" %} | |
| 7683 ins_encode( /*empty encoding*/ ); | |
| 7684 ins_pipe( empty ); | |
| 7685 %} | |
| 7686 | |
| 7687 instruct castPP( eRegP dst ) %{ | |
| 7688 match(Set dst (CastPP dst)); | |
| 7689 format %{ "#castPP of $dst" %} | |
| 7690 ins_encode( /*empty encoding*/ ); | |
| 7691 ins_pipe( empty ); | |
| 7692 %} | |
| 7693 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7694 instruct castII( rRegI dst ) %{ |
| 0 | 7695 match(Set dst (CastII dst)); |
| 7696 format %{ "#castII of $dst" %} | |
| 7697 ins_encode( /*empty encoding*/ ); | |
| 7698 ins_cost(0); | |
| 7699 ins_pipe( empty ); | |
| 7700 %} | |
| 7701 | |
| 7702 | |
| 7703 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7704 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7705 match(Set dst (LoadPLocked mem)); | |
| 7706 | |
| 7707 ins_cost(125); | |
| 7708 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7709 opcode(0x8B); | |
| 7710 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7711 ins_pipe( ialu_reg_mem ); | |
| 7712 %} | |
| 7713 | |
| 7714 // Conditional-store of the updated heap-top. | |
| 7715 // Used during allocation of the shared heap. | |
| 7716 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7717 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7718 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7719 // EAX is killed if there is contention, but then it's also unused. | |
| 7720 // In the common case of no contention, EAX holds the new oop address. | |
| 7721 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7722 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7723 ins_pipe( pipe_cmpxchg ); | |
| 7724 %} | |
| 7725 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7726 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7727 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7728 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7729 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7730 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7731 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7732 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7733 ins_pipe( pipe_cmpxchg ); |
| 7734 %} | |
| 7735 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7736 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7737 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7738 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7739 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7740 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7741 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7742 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7743 "XCHG EBX,ECX" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7744 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7745 ins_encode %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7746 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7747 // cmpxchg8 instruction because the instruction uses |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7748 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7749 // our register encoding uses rbx. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7750 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7751 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7752 __ lock(); |
| 624 | 7753 __ cmpxchg8($mem$$Address); |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7754 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7755 %} |
| 0 | 7756 ins_pipe( pipe_cmpxchg ); |
| 7757 %} | |
| 7758 | |
| 7759 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7760 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7761 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7762 predicate(VM_Version::supports_cx8()); |
| 0 | 7763 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7764 effect(KILL cr, KILL oldval); | |
| 7765 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7766 "MOV $res,0\n\t" | |
| 7767 "JNE,s fail\n\t" | |
| 7768 "MOV $res,1\n" | |
| 7769 "fail:" %} | |
| 7770 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7771 enc_flags_ne_to_boolean(res) ); | |
| 7772 ins_pipe( pipe_cmpxchg ); | |
| 7773 %} | |
| 7774 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7775 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7776 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7777 effect(KILL cr, KILL oldval); | |
| 7778 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7779 "MOV $res,0\n\t" | |
| 7780 "JNE,s fail\n\t" | |
| 7781 "MOV $res,1\n" | |
| 7782 "fail:" %} | |
| 7783 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7784 ins_pipe( pipe_cmpxchg ); | |
| 7785 %} | |
| 7786 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7787 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7788 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7789 effect(KILL cr, KILL oldval); | |
| 7790 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7791 "MOV $res,0\n\t" | |
| 7792 "JNE,s fail\n\t" | |
| 7793 "MOV $res,1\n" | |
| 7794 "fail:" %} | |
| 7795 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7796 ins_pipe( pipe_cmpxchg ); | |
| 7797 %} | |
| 7798 | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7799 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7800 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7801 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7802 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7803 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7804 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7805 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7806 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7807 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7808 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7809 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7810 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7811 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7812 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7813 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7814 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7815 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7816 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7817 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7818 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7819 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7820 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7821 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7822 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7823 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7824 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7825 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7826 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7827 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7828 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7829 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7830 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7831 instruct xchgP( memory mem, pRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7832 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7833 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7834 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7835 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7836 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7837 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7838 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7839 |
| 0 | 7840 //----------Subtraction Instructions------------------------------------------- |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7841 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7842 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7843 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7844 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7845 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7846 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7847 format %{ "SUB $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7848 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7849 __ subl($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7850 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7851 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7852 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7853 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7854 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7855 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7856 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7857 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7858 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7859 format %{ "SUB $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7860 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7861 __ subl($dst$$Register, $src$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7862 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7863 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7864 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7865 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7866 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7867 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7868 match(SubExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7869 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7870 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7871 ins_cost(125); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7872 format %{ "SUB $dst,$src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7873 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7874 __ subl($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7875 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7876 ins_pipe( ialu_reg_mem ); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7877 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7878 |
| 0 | 7879 // Integer Subtraction Instructions |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7880 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7881 match(Set dst (SubI dst src)); |
| 7882 effect(KILL cr); | |
| 7883 | |
| 7884 size(2); | |
| 7885 format %{ "SUB $dst,$src" %} | |
| 7886 opcode(0x2B); | |
| 7887 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7888 ins_pipe( ialu_reg_reg ); | |
| 7889 %} | |
| 7890 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7891 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7892 match(Set dst (SubI dst src)); |
| 7893 effect(KILL cr); | |
| 7894 | |
| 7895 format %{ "SUB $dst,$src" %} | |
| 7896 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7897 // ins_encode( RegImm( dst, src) ); | |
| 7898 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7899 ins_pipe( ialu_reg ); | |
| 7900 %} | |
| 7901 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7902 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7903 match(Set dst (SubI dst (LoadI src))); |
| 7904 effect(KILL cr); | |
| 7905 | |
| 7906 ins_cost(125); | |
| 7907 format %{ "SUB $dst,$src" %} | |
| 7908 opcode(0x2B); | |
| 7909 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7910 ins_pipe( ialu_reg_mem ); | |
| 7911 %} | |
| 7912 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7913 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7914 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7915 effect(KILL cr); | |
| 7916 | |
| 7917 ins_cost(150); | |
| 7918 format %{ "SUB $dst,$src" %} | |
| 7919 opcode(0x29); /* Opcode 29 /r */ | |
| 7920 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7921 ins_pipe( ialu_mem_reg ); | |
| 7922 %} | |
| 7923 | |
| 7924 // Subtract from a pointer | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7925 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7926 match(Set dst (AddP dst (SubI zero src))); |
| 7927 effect(KILL cr); | |
| 7928 | |
| 7929 size(2); | |
| 7930 format %{ "SUB $dst,$src" %} | |
| 7931 opcode(0x2B); | |
| 7932 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7933 ins_pipe( ialu_reg_reg ); | |
| 7934 %} | |
| 7935 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7936 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7937 match(Set dst (SubI zero dst)); |
| 7938 effect(KILL cr); | |
| 7939 | |
| 7940 size(2); | |
| 7941 format %{ "NEG $dst" %} | |
| 7942 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7943 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7944 ins_pipe( ialu_reg ); | |
| 7945 %} | |
| 7946 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7947 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7948 match(NegExactI dst); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7949 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7950 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7951 format %{ "NEG $dst\t# negExact int"%} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7952 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7953 __ negl($dst$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7954 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7955 ins_pipe(ialu_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7956 %} |
| 0 | 7957 |
| 7958 //----------Multiplication/Division Instructions------------------------------- | |
| 7959 // Integer Multiplication Instructions | |
| 7960 // Multiply Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7961 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7962 match(Set dst (MulI dst src)); |
| 7963 effect(KILL cr); | |
| 7964 | |
| 7965 size(3); | |
| 7966 ins_cost(300); | |
| 7967 format %{ "IMUL $dst,$src" %} | |
| 7968 opcode(0xAF, 0x0F); | |
| 7969 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7970 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7971 %} | |
| 7972 | |
| 7973 // Multiply 32-bit Immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7974 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7975 match(Set dst (MulI src imm)); |
| 7976 effect(KILL cr); | |
| 7977 | |
| 7978 ins_cost(300); | |
| 7979 format %{ "IMUL $dst,$src,$imm" %} | |
| 7980 opcode(0x69); /* 69 /r id */ | |
| 7981 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7982 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7983 %} | |
| 7984 | |
| 7985 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7986 match(Set dst src); | |
| 7987 effect(KILL cr); | |
| 7988 | |
| 7989 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7990 ins_cost(250); | |
| 7991 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7992 opcode(0xB8); | |
| 7993 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7994 ins_pipe( ialu_reg_fat ); | |
| 7995 %} | |
| 7996 | |
| 7997 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7998 // (special case for shift by 32) | |
| 7999 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 8000 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8001 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8002 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8003 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8004 effect(USE src1, KILL cr); | |
| 8005 | |
| 8006 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8007 ins_cost(0*100 + 1*400 - 150); | |
| 8008 format %{ "IMUL EDX:EAX,$src1" %} | |
| 8009 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8010 ins_pipe( pipe_slow ); | |
| 8011 %} | |
| 8012 | |
| 8013 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8014 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8015 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8016 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8017 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8018 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8019 effect(USE src1, KILL cr); | |
| 8020 | |
| 8021 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8022 ins_cost(1*100 + 1*400 - 150); | |
| 8023 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 8024 "SAR EDX,$cnt-32" %} | |
| 8025 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8026 ins_pipe( pipe_slow ); | |
| 8027 %} | |
| 8028 | |
| 8029 // Multiply Memory 32-bit Immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8030 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 8031 match(Set dst (MulI (LoadI src) imm)); |
| 8032 effect(KILL cr); | |
| 8033 | |
| 8034 ins_cost(300); | |
| 8035 format %{ "IMUL $dst,$src,$imm" %} | |
| 8036 opcode(0x69); /* 69 /r id */ | |
| 8037 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 8038 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8039 %} | |
| 8040 | |
| 8041 // Multiply Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8042 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8043 match(Set dst (MulI dst (LoadI src))); |
| 8044 effect(KILL cr); | |
| 8045 | |
| 8046 ins_cost(350); | |
| 8047 format %{ "IMUL $dst,$src" %} | |
| 8048 opcode(0xAF, 0x0F); | |
| 8049 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8050 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8051 %} | |
| 8052 | |
| 8053 // Multiply Register Int to Long | |
| 8054 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8055 // Basic Idea: long = (long)int * (long)int | |
| 8056 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8057 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8058 | |
| 8059 ins_cost(300); | |
| 8060 format %{ "IMUL $dst,$src1" %} | |
| 8061 | |
| 8062 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8063 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8064 %} | |
| 8065 | |
| 8066 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8067 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8068 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8069 effect(KILL flags); | |
| 8070 | |
| 8071 ins_cost(300); | |
| 8072 format %{ "MUL $dst,$src1" %} | |
| 8073 | |
| 8074 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8075 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8076 %} | |
| 8077 | |
| 8078 // Multiply Register Long | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8079 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 8080 match(Set dst (MulL dst src)); |
| 8081 effect(KILL cr, TEMP tmp); | |
| 8082 ins_cost(4*100+3*400); | |
| 8083 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8084 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8085 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8086 "IMUL $tmp,EDX\n\t" | |
| 8087 "MOV EDX,$src.hi\n\t" | |
| 8088 "IMUL EDX,EAX\n\t" | |
| 8089 "ADD $tmp,EDX\n\t" | |
| 8090 "MUL EDX:EAX,$src.lo\n\t" | |
| 8091 "ADD EDX,$tmp" %} | |
| 8092 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8093 ins_pipe( pipe_slow ); | |
| 8094 %} | |
| 8095 | |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8096 // Multiply Register Long where the left operand's high 32 bits are zero |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8097 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8098 predicate(is_operand_hi32_zero(n->in(1))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8099 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8100 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8101 ins_cost(2*100+2*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8102 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8103 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8104 format %{ "MOV $tmp,$src.hi\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8105 "IMUL $tmp,EAX\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8106 "MUL EDX:EAX,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8107 "ADD EDX,$tmp" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8108 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8109 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8110 __ imull($tmp$$Register, rax); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8111 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8112 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8113 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8114 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8115 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8116 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8117 // Multiply Register Long where the right operand's high 32 bits are zero |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8118 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8119 predicate(is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8120 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8121 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8122 ins_cost(2*100+2*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8123 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8124 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8125 format %{ "MOV $tmp,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8126 "IMUL $tmp,EDX\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8127 "MUL EDX:EAX,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8128 "ADD EDX,$tmp" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8129 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8130 __ movl($tmp$$Register, $src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8131 __ imull($tmp$$Register, rdx); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8132 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8133 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8134 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8135 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8136 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8137 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8138 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8139 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8140 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8141 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8142 effect(KILL cr); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8143 ins_cost(1*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8144 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8145 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8146 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8147 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8148 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8149 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8150 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8151 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8152 |
| 0 | 8153 // Multiply Register Long by small constant |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8154 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 8155 match(Set dst (MulL dst src)); |
| 8156 effect(KILL cr, TEMP tmp); | |
| 8157 ins_cost(2*100+2*400); | |
| 8158 size(12); | |
| 8159 // Basic idea: lo(result) = lo(src * EAX) | |
| 8160 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8161 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8162 "MOV EDX,$src\n\t" | |
| 8163 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8164 "ADD EDX,$tmp" %} | |
| 8165 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8166 ins_pipe( pipe_slow ); | |
| 8167 %} | |
| 8168 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8169 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8170 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8171 match(MulExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8172 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8173 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8174 ins_cost(300); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8175 format %{ "IMUL $dst, $src\t# mulExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8176 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8177 __ imull($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8178 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8179 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8180 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8181 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8182 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8183 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8184 match(MulExactI src imm); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8185 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8186 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8187 ins_cost(300); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8188 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8189 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8190 __ imull($dst$$Register, $src$$Register, $imm$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8191 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8192 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8193 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8194 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8195 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8196 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8197 match(MulExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8198 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8199 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8200 ins_cost(350); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8201 format %{ "IMUL $dst, $src\t# mulExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8202 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8203 __ imull($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8204 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8205 ins_pipe(ialu_reg_mem_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8206 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8207 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
8208 |
| 0 | 8209 // Integer DIV with Register |
| 8210 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8211 match(Set rax (DivI rax div)); | |
| 8212 effect(KILL rdx, KILL cr); | |
| 8213 size(26); | |
| 8214 ins_cost(30*100+10*100); | |
| 8215 format %{ "CMP EAX,0x80000000\n\t" | |
| 8216 "JNE,s normal\n\t" | |
| 8217 "XOR EDX,EDX\n\t" | |
| 8218 "CMP ECX,-1\n\t" | |
| 8219 "JE,s done\n" | |
| 8220 "normal: CDQ\n\t" | |
| 8221 "IDIV $div\n\t" | |
| 8222 "done:" %} | |
| 8223 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8224 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8225 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8226 %} | |
| 8227 | |
| 8228 // Divide Register Long | |
| 8229 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8230 match(Set dst (DivL src1 src2)); | |
| 8231 effect( KILL cr, KILL cx, KILL bx ); | |
| 8232 ins_cost(10000); | |
| 8233 format %{ "PUSH $src1.hi\n\t" | |
| 8234 "PUSH $src1.lo\n\t" | |
| 8235 "PUSH $src2.hi\n\t" | |
| 8236 "PUSH $src2.lo\n\t" | |
| 8237 "CALL SharedRuntime::ldiv\n\t" | |
| 8238 "ADD ESP,16" %} | |
| 8239 ins_encode( long_div(src1,src2) ); | |
| 8240 ins_pipe( pipe_slow ); | |
| 8241 %} | |
| 8242 | |
| 8243 // Integer DIVMOD with Register, both quotient and mod results | |
| 8244 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8245 match(DivModI rax div); | |
| 8246 effect(KILL cr); | |
| 8247 size(26); | |
| 8248 ins_cost(30*100+10*100); | |
| 8249 format %{ "CMP EAX,0x80000000\n\t" | |
| 8250 "JNE,s normal\n\t" | |
| 8251 "XOR EDX,EDX\n\t" | |
| 8252 "CMP ECX,-1\n\t" | |
| 8253 "JE,s done\n" | |
| 8254 "normal: CDQ\n\t" | |
| 8255 "IDIV $div\n\t" | |
| 8256 "done:" %} | |
| 8257 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8258 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8259 ins_pipe( pipe_slow ); | |
| 8260 %} | |
| 8261 | |
| 8262 // Integer MOD with Register | |
| 8263 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8264 match(Set rdx (ModI rax div)); | |
| 8265 effect(KILL rax, KILL cr); | |
| 8266 | |
| 8267 size(26); | |
| 8268 ins_cost(300); | |
| 8269 format %{ "CDQ\n\t" | |
| 8270 "IDIV $div" %} | |
| 8271 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8272 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8273 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8274 %} | |
| 8275 | |
| 8276 // Remainder Register Long | |
| 8277 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8278 match(Set dst (ModL src1 src2)); | |
| 8279 effect( KILL cr, KILL cx, KILL bx ); | |
| 8280 ins_cost(10000); | |
| 8281 format %{ "PUSH $src1.hi\n\t" | |
| 8282 "PUSH $src1.lo\n\t" | |
| 8283 "PUSH $src2.hi\n\t" | |
| 8284 "PUSH $src2.lo\n\t" | |
| 8285 "CALL SharedRuntime::lrem\n\t" | |
| 8286 "ADD ESP,16" %} | |
| 8287 ins_encode( long_mod(src1,src2) ); | |
| 8288 ins_pipe( pipe_slow ); | |
| 8289 %} | |
| 8290 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8291 // Divide Register Long (no special case since divisor != -1) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8292 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8293 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8294 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8295 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8296 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 8297 "XOR $tmp2,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8298 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8299 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8300 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8301 "MOV EAX,EDX\n\t" |
| 1920 | 8302 "MOV EDX,0\n\t" |
| 8303 "JLE,s pos\n\t" | |
| 8304 "LNEG EAX : $tmp2\n\t" | |
| 8305 "DIV $tmp # unsigned division\n\t" | |
| 8306 "XCHG EAX,$tmp2\n\t" | |
| 8307 "DIV $tmp\n\t" | |
| 8308 "LNEG $tmp2 : EAX\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8309 "JMP,s done\n" |
| 1920 | 8310 "pos:\n\t" |
| 8311 "DIV $tmp\n\t" | |
| 8312 "XCHG EAX,$tmp2\n" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8313 "fast:\n\t" |
| 1920 | 8314 "DIV $tmp\n" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8315 "done:\n\t" |
| 1920 | 8316 "MOV EDX,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8317 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8318 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8319 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8320 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8321 int pcon = (con > 0) ? con : -con; |
| 1920 | 8322 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8323 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8324 __ movl($tmp$$Register, pcon); |
| 1920 | 8325 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8326 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8327 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8328 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8329 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8330 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8331 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8332 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8333 | |
| 8334 // Negative dividend. | |
| 8335 // convert value to positive to use unsigned division | |
| 8336 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8337 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8338 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 8339 __ divl($tmp$$Register); |
| 8340 // revert result back to negative | |
| 8341 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8342 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8343 |
| 1920 | 8344 __ bind(Lpos); |
| 8345 __ divl($tmp$$Register); // Use unsigned division | |
| 8346 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 8347 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 8348 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8349 __ bind(Lfast); |
| 1920 | 8350 // fast path: src is positive |
| 8351 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8352 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8353 __ bind(Ldone); |
| 1920 | 8354 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8355 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8356 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8357 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8358 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8359 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8360 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8361 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8362 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8363 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8364 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8365 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8366 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8367 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8368 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8369 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8370 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8371 "MOV EAX,EDX\n\t" |
| 1920 | 8372 "MOV EDX,0\n\t" |
| 8373 "JLE,s pos\n\t" | |
| 8374 "LNEG EAX : $tmp2\n\t" | |
| 8375 "DIV $tmp # unsigned division\n\t" | |
| 8376 "MOV EAX,$tmp2\n\t" | |
| 8377 "DIV $tmp\n\t" | |
| 8378 "NEG EDX\n\t" | |
| 8379 "JMP,s done\n" | |
| 8380 "pos:\n\t" | |
| 8381 "DIV $tmp\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8382 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8383 "fast:\n\t" |
| 1920 | 8384 "DIV $tmp\n" |
| 8385 "done:\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8386 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8387 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8388 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8389 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8390 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8391 int pcon = (con > 0) ? con : -con; |
| 1920 | 8392 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8393 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8394 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8395 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8396 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8397 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8398 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8399 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8400 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8401 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8402 | |
| 8403 // Negative dividend. | |
| 8404 // convert value to positive to use unsigned division | |
| 8405 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8406 __ divl($tmp$$Register); | |
| 8407 __ movl($dst$$Register, $tmp2$$Register); | |
| 8408 __ divl($tmp$$Register); | |
| 8409 // revert remainder back to negative | |
| 8410 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 8411 __ jmpb(Ldone); | |
| 8412 | |
| 8413 __ bind(Lpos); | |
| 8414 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8415 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8416 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8417 __ bind(Lfast); |
| 1920 | 8418 // fast path: src is positive |
| 8419 __ divl($tmp$$Register); | |
| 8420 | |
| 8421 __ bind(Ldone); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8422 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8423 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8424 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8425 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8426 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8427 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8428 |
| 0 | 8429 // Integer Shift Instructions |
| 8430 // Shift Left by one | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8431 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8432 match(Set dst (LShiftI dst shift)); |
| 8433 effect(KILL cr); | |
| 8434 | |
| 8435 size(2); | |
| 8436 format %{ "SHL $dst,$shift" %} | |
| 8437 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8438 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8439 ins_pipe( ialu_reg ); | |
| 8440 %} | |
| 8441 | |
| 8442 // Shift Left by 8-bit immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8443 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8444 match(Set dst (LShiftI dst shift)); |
| 8445 effect(KILL cr); | |
| 8446 | |
| 8447 size(3); | |
| 8448 format %{ "SHL $dst,$shift" %} | |
| 8449 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8450 ins_encode( RegOpcImm( dst, shift) ); | |
| 8451 ins_pipe( ialu_reg ); | |
| 8452 %} | |
| 8453 | |
| 8454 // Shift Left by variable | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8455 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8456 match(Set dst (LShiftI dst shift)); |
| 8457 effect(KILL cr); | |
| 8458 | |
| 8459 size(2); | |
| 8460 format %{ "SHL $dst,$shift" %} | |
| 8461 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8462 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8463 ins_pipe( ialu_reg_reg ); | |
| 8464 %} | |
| 8465 | |
| 8466 // Arithmetic shift right by one | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8467 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8468 match(Set dst (RShiftI dst shift)); |
| 8469 effect(KILL cr); | |
| 8470 | |
| 8471 size(2); | |
| 8472 format %{ "SAR $dst,$shift" %} | |
| 8473 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8474 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8475 ins_pipe( ialu_reg ); | |
| 8476 %} | |
| 8477 | |
| 8478 // Arithmetic shift right by one | |
| 8479 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 8480 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8481 effect(KILL cr); | |
| 8482 format %{ "SAR $dst,$shift" %} | |
| 8483 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8484 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 8485 ins_pipe( ialu_mem_imm ); | |
| 8486 %} | |
| 8487 | |
| 8488 // Arithmetic Shift Right by 8-bit immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8489 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8490 match(Set dst (RShiftI dst shift)); |
| 8491 effect(KILL cr); | |
| 8492 | |
| 8493 size(3); | |
| 8494 format %{ "SAR $dst,$shift" %} | |
| 8495 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8496 ins_encode( RegOpcImm( dst, shift ) ); | |
| 8497 ins_pipe( ialu_mem_imm ); | |
| 8498 %} | |
| 8499 | |
| 8500 // Arithmetic Shift Right by 8-bit immediate | |
| 8501 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 8502 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8503 effect(KILL cr); | |
| 8504 | |
| 8505 format %{ "SAR $dst,$shift" %} | |
| 8506 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8507 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 8508 ins_pipe( ialu_mem_imm ); | |
| 8509 %} | |
| 8510 | |
| 8511 // Arithmetic Shift Right by variable | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8512 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8513 match(Set dst (RShiftI dst shift)); |
| 8514 effect(KILL cr); | |
| 8515 | |
| 8516 size(2); | |
| 8517 format %{ "SAR $dst,$shift" %} | |
| 8518 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8519 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8520 ins_pipe( ialu_reg_reg ); | |
| 8521 %} | |
| 8522 | |
| 8523 // Logical shift right by one | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8524 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8525 match(Set dst (URShiftI dst shift)); |
| 8526 effect(KILL cr); | |
| 8527 | |
| 8528 size(2); | |
| 8529 format %{ "SHR $dst,$shift" %} | |
| 8530 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8531 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8532 ins_pipe( ialu_reg ); | |
| 8533 %} | |
| 8534 | |
| 8535 // Logical Shift Right by 8-bit immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8536 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8537 match(Set dst (URShiftI dst shift)); |
| 8538 effect(KILL cr); | |
| 8539 | |
| 8540 size(3); | |
| 8541 format %{ "SHR $dst,$shift" %} | |
| 8542 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8543 ins_encode( RegOpcImm( dst, shift) ); | |
| 8544 ins_pipe( ialu_reg ); | |
| 8545 %} | |
| 8546 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8547 |
| 0 | 8548 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 8549 // This idiom is used by the compiler for the i2b bytecode. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8550 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 8551 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 8552 | |
| 8553 size(3); | |
| 8554 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 8555 ins_encode %{ |
| 8556 __ movsbl($dst$$Register, $src$$Register); | |
| 8557 %} | |
| 8558 ins_pipe(ialu_reg_reg); | |
| 0 | 8559 %} |
| 8560 | |
| 8561 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8562 // This idiom is used by the compiler the i2s bytecode. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8563 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 8564 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 8565 | |
| 8566 size(3); | |
| 8567 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 8568 ins_encode %{ |
| 8569 __ movswl($dst$$Register, $src$$Register); | |
| 8570 %} | |
| 8571 ins_pipe(ialu_reg_reg); | |
| 0 | 8572 %} |
| 8573 | |
| 8574 | |
| 8575 // Logical Shift Right by variable | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8576 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8577 match(Set dst (URShiftI dst shift)); |
| 8578 effect(KILL cr); | |
| 8579 | |
| 8580 size(2); | |
| 8581 format %{ "SHR $dst,$shift" %} | |
| 8582 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8583 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8584 ins_pipe( ialu_reg_reg ); | |
| 8585 %} | |
| 8586 | |
| 8587 | |
| 8588 //----------Logical Instructions----------------------------------------------- | |
| 8589 //----------Integer Logical Instructions--------------------------------------- | |
| 8590 // And Instructions | |
| 8591 // And Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8592 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8593 match(Set dst (AndI dst src)); |
| 8594 effect(KILL cr); | |
| 8595 | |
| 8596 size(2); | |
| 8597 format %{ "AND $dst,$src" %} | |
| 8598 opcode(0x23); | |
| 8599 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8600 ins_pipe( ialu_reg_reg ); | |
| 8601 %} | |
| 8602 | |
| 8603 // And Register with Immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8604 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8605 match(Set dst (AndI dst src)); |
| 8606 effect(KILL cr); | |
| 8607 | |
| 8608 format %{ "AND $dst,$src" %} | |
| 8609 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8610 // ins_encode( RegImm( dst, src) ); | |
| 8611 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8612 ins_pipe( ialu_reg ); | |
| 8613 %} | |
| 8614 | |
| 8615 // And Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8616 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8617 match(Set dst (AndI dst (LoadI src))); |
| 8618 effect(KILL cr); | |
| 8619 | |
| 8620 ins_cost(125); | |
| 8621 format %{ "AND $dst,$src" %} | |
| 8622 opcode(0x23); | |
| 8623 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8624 ins_pipe( ialu_reg_mem ); | |
| 8625 %} | |
| 8626 | |
| 8627 // And Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8628 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8629 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8630 effect(KILL cr); | |
| 8631 | |
| 8632 ins_cost(150); | |
| 8633 format %{ "AND $dst,$src" %} | |
| 8634 opcode(0x21); /* Opcode 21 /r */ | |
| 8635 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8636 ins_pipe( ialu_mem_reg ); | |
| 8637 %} | |
| 8638 | |
| 8639 // And Memory with Immediate | |
| 8640 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8641 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8642 effect(KILL cr); | |
| 8643 | |
| 8644 ins_cost(125); | |
| 8645 format %{ "AND $dst,$src" %} | |
| 8646 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8647 // ins_encode( MemImm( dst, src) ); | |
| 8648 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8649 ins_pipe( ialu_mem_imm ); | |
| 8650 %} | |
| 8651 | |
| 8652 // Or Instructions | |
| 8653 // Or Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8654 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8655 match(Set dst (OrI dst src)); |
| 8656 effect(KILL cr); | |
| 8657 | |
| 8658 size(2); | |
| 8659 format %{ "OR $dst,$src" %} | |
| 8660 opcode(0x0B); | |
| 8661 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8662 ins_pipe( ialu_reg_reg ); | |
| 8663 %} | |
| 8664 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8665 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8666 match(Set dst (OrI dst (CastP2X src))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8667 effect(KILL cr); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8668 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8669 size(2); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8670 format %{ "OR $dst,$src" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8671 opcode(0x0B); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8672 ins_encode( OpcP, RegReg( dst, src) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8673 ins_pipe( ialu_reg_reg ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8674 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8675 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8676 |
| 0 | 8677 // Or Register with Immediate |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8678 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8679 match(Set dst (OrI dst src)); |
| 8680 effect(KILL cr); | |
| 8681 | |
| 8682 format %{ "OR $dst,$src" %} | |
| 8683 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8684 // ins_encode( RegImm( dst, src) ); | |
| 8685 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8686 ins_pipe( ialu_reg ); | |
| 8687 %} | |
| 8688 | |
| 8689 // Or Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8690 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8691 match(Set dst (OrI dst (LoadI src))); |
| 8692 effect(KILL cr); | |
| 8693 | |
| 8694 ins_cost(125); | |
| 8695 format %{ "OR $dst,$src" %} | |
| 8696 opcode(0x0B); | |
| 8697 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8698 ins_pipe( ialu_reg_mem ); | |
| 8699 %} | |
| 8700 | |
| 8701 // Or Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8702 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8703 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8704 effect(KILL cr); | |
| 8705 | |
| 8706 ins_cost(150); | |
| 8707 format %{ "OR $dst,$src" %} | |
| 8708 opcode(0x09); /* Opcode 09 /r */ | |
| 8709 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8710 ins_pipe( ialu_mem_reg ); | |
| 8711 %} | |
| 8712 | |
| 8713 // Or Memory with Immediate | |
| 8714 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8715 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8716 effect(KILL cr); | |
| 8717 | |
| 8718 ins_cost(125); | |
| 8719 format %{ "OR $dst,$src" %} | |
| 8720 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8721 // ins_encode( MemImm( dst, src) ); | |
| 8722 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8723 ins_pipe( ialu_mem_imm ); | |
| 8724 %} | |
| 8725 | |
| 8726 // ROL/ROR | |
| 8727 // ROL expand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8728 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8729 effect(USE_DEF dst, USE shift, KILL cr); |
| 8730 | |
| 8731 format %{ "ROL $dst, $shift" %} | |
| 8732 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8733 ins_encode( OpcP, RegOpc( dst )); | |
| 8734 ins_pipe( ialu_reg ); | |
| 8735 %} | |
| 8736 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8737 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8738 effect(USE_DEF dst, USE shift, KILL cr); |
| 8739 | |
| 8740 format %{ "ROL $dst, $shift" %} | |
| 8741 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8742 ins_encode( RegOpcImm(dst, shift) ); | |
| 8743 ins_pipe(ialu_reg); | |
| 8744 %} | |
| 8745 | |
| 8746 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8747 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8748 | |
| 8749 format %{ "ROL $dst, $shift" %} | |
| 8750 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8751 ins_encode(OpcP, RegOpc(dst)); | |
| 8752 ins_pipe( ialu_reg_reg ); | |
| 8753 %} | |
| 8754 // end of ROL expand | |
| 8755 | |
| 8756 // ROL 32bit by one once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8757 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8758 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8759 | |
| 8760 expand %{ | |
| 8761 rolI_eReg_imm1(dst, lshift, cr); | |
| 8762 %} | |
| 8763 %} | |
| 8764 | |
| 8765 // ROL 32bit var by imm8 once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8766 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8767 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8768 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8769 | |
| 8770 expand %{ | |
| 8771 rolI_eReg_imm8(dst, lshift, cr); | |
| 8772 %} | |
| 8773 %} | |
| 8774 | |
| 8775 // ROL 32bit var by var once | |
| 8776 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8777 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8778 | |
| 8779 expand %{ | |
| 8780 rolI_eReg_CL(dst, shift, cr); | |
| 8781 %} | |
| 8782 %} | |
| 8783 | |
| 8784 // ROL 32bit var by var once | |
| 8785 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8786 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8787 | |
| 8788 expand %{ | |
| 8789 rolI_eReg_CL(dst, shift, cr); | |
| 8790 %} | |
| 8791 %} | |
| 8792 | |
| 8793 // ROR expand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8794 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8795 effect(USE_DEF dst, USE shift, KILL cr); |
| 8796 | |
| 8797 format %{ "ROR $dst, $shift" %} | |
| 8798 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8799 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8800 ins_pipe( ialu_reg ); | |
| 8801 %} | |
| 8802 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8803 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8804 effect (USE_DEF dst, USE shift, KILL cr); |
| 8805 | |
| 8806 format %{ "ROR $dst, $shift" %} | |
| 8807 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8808 ins_encode( RegOpcImm(dst, shift) ); | |
| 8809 ins_pipe( ialu_reg ); | |
| 8810 %} | |
| 8811 | |
| 8812 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8813 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8814 | |
| 8815 format %{ "ROR $dst, $shift" %} | |
| 8816 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8817 ins_encode(OpcP, RegOpc(dst)); | |
| 8818 ins_pipe( ialu_reg_reg ); | |
| 8819 %} | |
| 8820 // end of ROR expand | |
| 8821 | |
| 8822 // ROR right once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8823 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8824 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8825 | |
| 8826 expand %{ | |
| 8827 rorI_eReg_imm1(dst, rshift, cr); | |
| 8828 %} | |
| 8829 %} | |
| 8830 | |
| 8831 // ROR 32bit by immI8 once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8832 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8833 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8834 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8835 | |
| 8836 expand %{ | |
| 8837 rorI_eReg_imm8(dst, rshift, cr); | |
| 8838 %} | |
| 8839 %} | |
| 8840 | |
| 8841 // ROR 32bit var by var once | |
| 8842 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8843 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8844 | |
| 8845 expand %{ | |
| 8846 rorI_eReg_CL(dst, shift, cr); | |
| 8847 %} | |
| 8848 %} | |
| 8849 | |
| 8850 // ROR 32bit var by var once | |
| 8851 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8852 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8853 | |
| 8854 expand %{ | |
| 8855 rorI_eReg_CL(dst, shift, cr); | |
| 8856 %} | |
| 8857 %} | |
| 8858 | |
| 8859 // Xor Instructions | |
| 8860 // Xor Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8861 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8862 match(Set dst (XorI dst src)); |
| 8863 effect(KILL cr); | |
| 8864 | |
| 8865 size(2); | |
| 8866 format %{ "XOR $dst,$src" %} | |
| 8867 opcode(0x33); | |
| 8868 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8869 ins_pipe( ialu_reg_reg ); | |
| 8870 %} | |
| 8871 | |
| 403 | 8872 // Xor Register with Immediate -1 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8873 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8874 match(Set dst (XorI dst imm)); |
| 8875 | |
| 8876 size(2); | |
| 8877 format %{ "NOT $dst" %} | |
| 8878 ins_encode %{ | |
| 8879 __ notl($dst$$Register); | |
| 8880 %} | |
| 8881 ins_pipe( ialu_reg ); | |
| 8882 %} | |
| 8883 | |
| 0 | 8884 // Xor Register with Immediate |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8885 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8886 match(Set dst (XorI dst src)); |
| 8887 effect(KILL cr); | |
| 8888 | |
| 8889 format %{ "XOR $dst,$src" %} | |
| 8890 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8891 // ins_encode( RegImm( dst, src) ); | |
| 8892 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8893 ins_pipe( ialu_reg ); | |
| 8894 %} | |
| 8895 | |
| 8896 // Xor Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8897 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8898 match(Set dst (XorI dst (LoadI src))); |
| 8899 effect(KILL cr); | |
| 8900 | |
| 8901 ins_cost(125); | |
| 8902 format %{ "XOR $dst,$src" %} | |
| 8903 opcode(0x33); | |
| 8904 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8905 ins_pipe( ialu_reg_mem ); | |
| 8906 %} | |
| 8907 | |
| 8908 // Xor Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8909 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8910 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8911 effect(KILL cr); | |
| 8912 | |
| 8913 ins_cost(150); | |
| 8914 format %{ "XOR $dst,$src" %} | |
| 8915 opcode(0x31); /* Opcode 31 /r */ | |
| 8916 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8917 ins_pipe( ialu_mem_reg ); | |
| 8918 %} | |
| 8919 | |
| 8920 // Xor Memory with Immediate | |
| 8921 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8922 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8923 effect(KILL cr); | |
| 8924 | |
| 8925 ins_cost(125); | |
| 8926 format %{ "XOR $dst,$src" %} | |
| 8927 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8928 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8929 ins_pipe( ialu_mem_imm ); | |
| 8930 %} | |
| 8931 | |
| 8932 //----------Convert Int to Boolean--------------------------------------------- | |
| 8933 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8934 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8935 effect( DEF dst, USE src ); |
| 8936 format %{ "MOV $dst,$src" %} | |
| 8937 ins_encode( enc_Copy( dst, src) ); | |
| 8938 ins_pipe( ialu_reg_reg ); | |
| 8939 %} | |
| 8940 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8941 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8942 effect( USE_DEF dst, USE src, KILL cr ); |
| 8943 | |
| 8944 size(4); | |
| 8945 format %{ "NEG $dst\n\t" | |
| 8946 "ADC $dst,$src" %} | |
| 8947 ins_encode( neg_reg(dst), | |
| 8948 OpcRegReg(0x13,dst,src) ); | |
| 8949 ins_pipe( ialu_reg_reg_long ); | |
| 8950 %} | |
| 8951 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8952 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8953 match(Set dst (Conv2B src)); |
| 8954 | |
| 8955 expand %{ | |
| 8956 movI_nocopy(dst,src); | |
| 8957 ci2b(dst,src,cr); | |
| 8958 %} | |
| 8959 %} | |
| 8960 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8961 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8962 effect( DEF dst, USE src ); |
| 8963 format %{ "MOV $dst,$src" %} | |
| 8964 ins_encode( enc_Copy( dst, src) ); | |
| 8965 ins_pipe( ialu_reg_reg ); | |
| 8966 %} | |
| 8967 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8968 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8969 effect( USE_DEF dst, USE src, KILL cr ); |
| 8970 format %{ "NEG $dst\n\t" | |
| 8971 "ADC $dst,$src" %} | |
| 8972 ins_encode( neg_reg(dst), | |
| 8973 OpcRegReg(0x13,dst,src) ); | |
| 8974 ins_pipe( ialu_reg_reg_long ); | |
| 8975 %} | |
| 8976 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8977 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8978 match(Set dst (Conv2B src)); |
| 8979 | |
| 8980 expand %{ | |
| 8981 movP_nocopy(dst,src); | |
| 8982 cp2b(dst,src,cr); | |
| 8983 %} | |
| 8984 %} | |
| 8985 | |
| 9154 | 8986 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{ |
| 0 | 8987 match(Set dst (CmpLTMask p q)); |
| 9154 | 8988 effect(KILL cr); |
| 0 | 8989 ins_cost(400); |
| 8990 | |
| 8991 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8992 format %{ "XOR $dst,$dst\n\t" | |
| 8993 "CMP $p,$q\n\t" | |
| 8994 "SETlt $dst\n\t" | |
| 8995 "NEG $dst" %} | |
| 9154 | 8996 ins_encode %{ |
| 8997 Register Rp = $p$$Register; | |
| 8998 Register Rq = $q$$Register; | |
| 8999 Register Rd = $dst$$Register; | |
| 9000 Label done; | |
| 9001 __ xorl(Rd, Rd); | |
| 9002 __ cmpl(Rp, Rq); | |
| 9003 __ setb(Assembler::less, Rd); | |
| 9004 __ negl(Rd); | |
| 9005 %} | |
| 9006 | |
| 9007 ins_pipe(pipe_slow); | |
| 9008 %} | |
| 9009 | |
| 9010 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 0 | 9011 match(Set dst (CmpLTMask dst zero)); |
| 9154 | 9012 effect(DEF dst, KILL cr); |
| 0 | 9013 ins_cost(100); |
| 9014 | |
| 9154 | 9015 format %{ "SAR $dst,31\t# cmpLTMask0" %} |
| 9016 ins_encode %{ | |
| 9017 __ sarl($dst$$Register, 31); | |
| 9018 %} | |
| 9019 ins_pipe(ialu_reg); | |
| 9020 %} | |
| 9021 | |
| 9022 /* better to save a register than avoid a branch */ | |
| 9023 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 0 | 9024 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
| 9154 | 9025 effect(KILL cr); |
| 0 | 9026 ins_cost(400); |
| 9154 | 9027 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t" |
| 9028 "JGE done\n\t" | |
| 9029 "ADD $p,$y\n" | |
| 9030 "done: " %} | |
| 9031 ins_encode %{ | |
| 9032 Register Rp = $p$$Register; | |
| 9033 Register Rq = $q$$Register; | |
| 9034 Register Ry = $y$$Register; | |
| 9035 Label done; | |
| 9036 __ subl(Rp, Rq); | |
| 9037 __ jccb(Assembler::greaterEqual, done); | |
| 9038 __ addl(Rp, Ry); | |
| 9039 __ bind(done); | |
| 9040 %} | |
| 9041 | |
| 9042 ins_pipe(pipe_cmplt); | |
| 9043 %} | |
| 9044 | |
| 9045 /* better to save a register than avoid a branch */ | |
| 9046 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 9047 match(Set y (AndI (CmpLTMask p q) y)); | |
| 9048 effect(KILL cr); | |
| 9049 | |
| 9050 ins_cost(300); | |
| 9051 | |
| 9052 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t" | |
| 9053 "JLT done\n\t" | |
| 9054 "XORL $y, $y\n" | |
| 9055 "done: " %} | |
| 9056 ins_encode %{ | |
| 9057 Register Rp = $p$$Register; | |
| 9058 Register Rq = $q$$Register; | |
| 9059 Register Ry = $y$$Register; | |
| 9060 Label done; | |
| 9061 __ cmpl(Rp, Rq); | |
| 9062 __ jccb(Assembler::less, done); | |
| 9063 __ xorl(Ry, Ry); | |
| 9064 __ bind(done); | |
| 9065 %} | |
| 9066 | |
| 9067 ins_pipe(pipe_cmplt); | |
| 0 | 9068 %} |
| 9069 | |
| 9070 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9154 | 9071 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
| 0 | 9072 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
| 9073 */ | |
| 9074 | |
| 9075 //----------Long Instructions------------------------------------------------ | |
| 9076 // Add Long Register with Register | |
| 9077 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9078 match(Set dst (AddL dst src)); | |
| 9079 effect(KILL cr); | |
| 9080 ins_cost(200); | |
| 9081 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9082 "ADC $dst.hi,$src.hi" %} | |
| 9083 opcode(0x03, 0x13); | |
| 9084 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9085 ins_pipe( ialu_reg_reg_long ); | |
| 9086 %} | |
| 9087 | |
| 9088 // Add Long Register with Immediate | |
| 9089 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9090 match(Set dst (AddL dst src)); | |
| 9091 effect(KILL cr); | |
| 9092 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9093 "ADC $dst.hi,$src.hi" %} | |
| 9094 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 9095 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9096 ins_pipe( ialu_reg_long ); | |
| 9097 %} | |
| 9098 | |
| 9099 // Add Long Register with Memory | |
| 9100 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9101 match(Set dst (AddL dst (LoadL mem))); | |
| 9102 effect(KILL cr); | |
| 9103 ins_cost(125); | |
| 9104 format %{ "ADD $dst.lo,$mem\n\t" | |
| 9105 "ADC $dst.hi,$mem+4" %} | |
| 9106 opcode(0x03, 0x13); | |
| 9107 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9108 ins_pipe( ialu_reg_long_mem ); | |
| 9109 %} | |
| 9110 | |
| 9111 // Subtract Long Register with Register. | |
| 9112 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9113 match(Set dst (SubL dst src)); | |
| 9114 effect(KILL cr); | |
| 9115 ins_cost(200); | |
| 9116 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9117 "SBB $dst.hi,$src.hi" %} | |
| 9118 opcode(0x2B, 0x1B); | |
| 9119 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9120 ins_pipe( ialu_reg_reg_long ); | |
| 9121 %} | |
| 9122 | |
| 9123 // Subtract Long Register with Immediate | |
| 9124 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9125 match(Set dst (SubL dst src)); | |
| 9126 effect(KILL cr); | |
| 9127 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9128 "SBB $dst.hi,$src.hi" %} | |
| 9129 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9130 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9131 ins_pipe( ialu_reg_long ); | |
| 9132 %} | |
| 9133 | |
| 9134 // Subtract Long Register with Memory | |
| 9135 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9136 match(Set dst (SubL dst (LoadL mem))); | |
| 9137 effect(KILL cr); | |
| 9138 ins_cost(125); | |
| 9139 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9140 "SBB $dst.hi,$mem+4" %} | |
| 9141 opcode(0x2B, 0x1B); | |
| 9142 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9143 ins_pipe( ialu_reg_long_mem ); | |
| 9144 %} | |
| 9145 | |
| 9146 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9147 match(Set dst (SubL zero dst)); | |
| 9148 effect(KILL cr); | |
| 9149 ins_cost(300); | |
| 9150 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9151 ins_encode( neg_long(dst) ); | |
| 9152 ins_pipe( ialu_reg_reg_long ); | |
| 9153 %} | |
| 9154 | |
| 9155 // And Long Register with Register | |
| 9156 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9157 match(Set dst (AndL dst src)); | |
| 9158 effect(KILL cr); | |
| 9159 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9160 "AND $dst.hi,$src.hi" %} | |
| 9161 opcode(0x23,0x23); | |
| 9162 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9163 ins_pipe( ialu_reg_reg_long ); | |
| 9164 %} | |
| 9165 | |
| 9166 // And Long Register with Immediate | |
| 9167 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9168 match(Set dst (AndL dst src)); | |
| 9169 effect(KILL cr); | |
| 9170 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9171 "AND $dst.hi,$src.hi" %} | |
| 9172 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9173 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9174 ins_pipe( ialu_reg_long ); | |
| 9175 %} | |
| 9176 | |
| 9177 // And Long Register with Memory | |
| 9178 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9179 match(Set dst (AndL dst (LoadL mem))); | |
| 9180 effect(KILL cr); | |
| 9181 ins_cost(125); | |
| 9182 format %{ "AND $dst.lo,$mem\n\t" | |
| 9183 "AND $dst.hi,$mem+4" %} | |
| 9184 opcode(0x23, 0x23); | |
| 9185 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9186 ins_pipe( ialu_reg_long_mem ); | |
| 9187 %} | |
| 9188 | |
| 9189 // Or Long Register with Register | |
| 9190 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9191 match(Set dst (OrL dst src)); | |
| 9192 effect(KILL cr); | |
| 9193 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9194 "OR $dst.hi,$src.hi" %} | |
| 9195 opcode(0x0B,0x0B); | |
| 9196 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9197 ins_pipe( ialu_reg_reg_long ); | |
| 9198 %} | |
| 9199 | |
| 9200 // Or Long Register with Immediate | |
| 9201 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9202 match(Set dst (OrL dst src)); | |
| 9203 effect(KILL cr); | |
| 9204 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9205 "OR $dst.hi,$src.hi" %} | |
| 9206 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9207 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9208 ins_pipe( ialu_reg_long ); | |
| 9209 %} | |
| 9210 | |
| 9211 // Or Long Register with Memory | |
| 9212 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9213 match(Set dst (OrL dst (LoadL mem))); | |
| 9214 effect(KILL cr); | |
| 9215 ins_cost(125); | |
| 9216 format %{ "OR $dst.lo,$mem\n\t" | |
| 9217 "OR $dst.hi,$mem+4" %} | |
| 9218 opcode(0x0B,0x0B); | |
| 9219 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9220 ins_pipe( ialu_reg_long_mem ); | |
| 9221 %} | |
| 9222 | |
| 9223 // Xor Long Register with Register | |
| 9224 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9225 match(Set dst (XorL dst src)); | |
| 9226 effect(KILL cr); | |
| 9227 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9228 "XOR $dst.hi,$src.hi" %} | |
| 9229 opcode(0x33,0x33); | |
| 9230 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9231 ins_pipe( ialu_reg_reg_long ); | |
| 9232 %} | |
| 9233 | |
| 403 | 9234 // Xor Long Register with Immediate -1 |
| 9235 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9236 match(Set dst (XorL dst imm)); | |
| 9237 format %{ "NOT $dst.lo\n\t" | |
| 9238 "NOT $dst.hi" %} | |
| 9239 ins_encode %{ | |
| 9240 __ notl($dst$$Register); | |
| 9241 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9242 %} | |
| 9243 ins_pipe( ialu_reg_long ); | |
| 9244 %} | |
| 9245 | |
| 0 | 9246 // Xor Long Register with Immediate |
| 9247 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9248 match(Set dst (XorL dst src)); | |
| 9249 effect(KILL cr); | |
| 9250 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9251 "XOR $dst.hi,$src.hi" %} | |
| 9252 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9253 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9254 ins_pipe( ialu_reg_long ); | |
| 9255 %} | |
| 9256 | |
| 9257 // Xor Long Register with Memory | |
| 9258 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9259 match(Set dst (XorL dst (LoadL mem))); | |
| 9260 effect(KILL cr); | |
| 9261 ins_cost(125); | |
| 9262 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9263 "XOR $dst.hi,$mem+4" %} | |
| 9264 opcode(0x33,0x33); | |
| 9265 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9266 ins_pipe( ialu_reg_long_mem ); | |
| 9267 %} | |
| 9268 | |
| 219 | 9269 // Shift Left Long by 1 |
| 9270 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9271 predicate(UseNewLongLShift); | |
| 9272 match(Set dst (LShiftL dst cnt)); | |
| 9273 effect(KILL cr); | |
| 9274 ins_cost(100); | |
| 9275 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9276 "ADC $dst.hi,$dst.hi" %} | |
| 9277 ins_encode %{ | |
| 9278 __ addl($dst$$Register,$dst$$Register); | |
| 9279 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9280 %} | |
| 9281 ins_pipe( ialu_reg_long ); | |
| 9282 %} | |
| 9283 | |
| 9284 // Shift Left Long by 2 | |
| 9285 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9286 predicate(UseNewLongLShift); | |
| 9287 match(Set dst (LShiftL dst cnt)); | |
| 9288 effect(KILL cr); | |
| 9289 ins_cost(100); | |
| 9290 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9291 "ADC $dst.hi,$dst.hi\n\t" | |
| 9292 "ADD $dst.lo,$dst.lo\n\t" | |
| 9293 "ADC $dst.hi,$dst.hi" %} | |
| 9294 ins_encode %{ | |
| 9295 __ addl($dst$$Register,$dst$$Register); | |
| 9296 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9297 __ addl($dst$$Register,$dst$$Register); | |
| 9298 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9299 %} | |
| 9300 ins_pipe( ialu_reg_long ); | |
| 9301 %} | |
| 9302 | |
| 9303 // Shift Left Long by 3 | |
| 9304 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9305 predicate(UseNewLongLShift); | |
| 9306 match(Set dst (LShiftL dst cnt)); | |
| 9307 effect(KILL cr); | |
| 9308 ins_cost(100); | |
| 9309 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9310 "ADC $dst.hi,$dst.hi\n\t" | |
| 9311 "ADD $dst.lo,$dst.lo\n\t" | |
| 9312 "ADC $dst.hi,$dst.hi\n\t" | |
| 9313 "ADD $dst.lo,$dst.lo\n\t" | |
| 9314 "ADC $dst.hi,$dst.hi" %} | |
| 9315 ins_encode %{ | |
| 9316 __ addl($dst$$Register,$dst$$Register); | |
| 9317 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9318 __ addl($dst$$Register,$dst$$Register); | |
| 9319 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9320 __ addl($dst$$Register,$dst$$Register); | |
| 9321 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9322 %} | |
| 9323 ins_pipe( ialu_reg_long ); | |
| 9324 %} | |
| 9325 | |
| 0 | 9326 // Shift Left Long by 1-31 |
| 9327 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9328 match(Set dst (LShiftL dst cnt)); | |
| 9329 effect(KILL cr); | |
| 9330 ins_cost(200); | |
| 9331 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9332 "SHL $dst.lo,$cnt" %} | |
| 9333 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9334 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9335 ins_pipe( ialu_reg_long ); | |
| 9336 %} | |
| 9337 | |
| 9338 // Shift Left Long by 32-63 | |
| 9339 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9340 match(Set dst (LShiftL dst cnt)); | |
| 9341 effect(KILL cr); | |
| 9342 ins_cost(300); | |
| 9343 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9344 "\tSHL $dst.hi,$cnt-32\n" | |
| 9345 "\tXOR $dst.lo,$dst.lo" %} | |
| 9346 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9347 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9348 ins_pipe( ialu_reg_long ); | |
| 9349 %} | |
| 9350 | |
| 9351 // Shift Left Long by variable | |
| 9352 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9353 match(Set dst (LShiftL dst shift)); | |
| 9354 effect(KILL cr); | |
| 9355 ins_cost(500+200); | |
| 9356 size(17); | |
| 9357 format %{ "TEST $shift,32\n\t" | |
| 9358 "JEQ,s small\n\t" | |
| 9359 "MOV $dst.hi,$dst.lo\n\t" | |
| 9360 "XOR $dst.lo,$dst.lo\n" | |
| 9361 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9362 "SHL $dst.lo,$shift" %} | |
| 9363 ins_encode( shift_left_long( dst, shift ) ); | |
| 9364 ins_pipe( pipe_slow ); | |
| 9365 %} | |
| 9366 | |
| 9367 // Shift Right Long by 1-31 | |
| 9368 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9369 match(Set dst (URShiftL dst cnt)); | |
| 9370 effect(KILL cr); | |
| 9371 ins_cost(200); | |
| 9372 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9373 "SHR $dst.hi,$cnt" %} | |
| 9374 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9375 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9376 ins_pipe( ialu_reg_long ); | |
| 9377 %} | |
| 9378 | |
| 9379 // Shift Right Long by 32-63 | |
| 9380 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9381 match(Set dst (URShiftL dst cnt)); | |
| 9382 effect(KILL cr); | |
| 9383 ins_cost(300); | |
| 9384 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9385 "\tSHR $dst.lo,$cnt-32\n" | |
| 9386 "\tXOR $dst.hi,$dst.hi" %} | |
| 9387 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9388 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9389 ins_pipe( ialu_reg_long ); | |
| 9390 %} | |
| 9391 | |
| 9392 // Shift Right Long by variable | |
| 9393 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9394 match(Set dst (URShiftL dst shift)); | |
| 9395 effect(KILL cr); | |
| 9396 ins_cost(600); | |
| 9397 size(17); | |
| 9398 format %{ "TEST $shift,32\n\t" | |
| 9399 "JEQ,s small\n\t" | |
| 9400 "MOV $dst.lo,$dst.hi\n\t" | |
| 9401 "XOR $dst.hi,$dst.hi\n" | |
| 9402 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9403 "SHR $dst.hi,$shift" %} | |
| 9404 ins_encode( shift_right_long( dst, shift ) ); | |
| 9405 ins_pipe( pipe_slow ); | |
| 9406 %} | |
| 9407 | |
| 9408 // Shift Right Long by 1-31 | |
| 9409 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9410 match(Set dst (RShiftL dst cnt)); | |
| 9411 effect(KILL cr); | |
| 9412 ins_cost(200); | |
| 9413 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9414 "SAR $dst.hi,$cnt" %} | |
| 9415 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9416 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9417 ins_pipe( ialu_reg_long ); | |
| 9418 %} | |
| 9419 | |
| 9420 // Shift Right Long by 32-63 | |
| 9421 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9422 match(Set dst (RShiftL dst cnt)); | |
| 9423 effect(KILL cr); | |
| 9424 ins_cost(300); | |
| 9425 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9426 "\tSAR $dst.lo,$cnt-32\n" | |
| 9427 "\tSAR $dst.hi,31" %} | |
| 9428 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9429 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9430 ins_pipe( ialu_reg_long ); | |
| 9431 %} | |
| 9432 | |
| 9433 // Shift Right arithmetic Long by variable | |
| 9434 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9435 match(Set dst (RShiftL dst shift)); | |
| 9436 effect(KILL cr); | |
| 9437 ins_cost(600); | |
| 9438 size(18); | |
| 9439 format %{ "TEST $shift,32\n\t" | |
| 9440 "JEQ,s small\n\t" | |
| 9441 "MOV $dst.lo,$dst.hi\n\t" | |
| 9442 "SAR $dst.hi,31\n" | |
| 9443 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9444 "SAR $dst.hi,$shift" %} | |
| 9445 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9446 ins_pipe( pipe_slow ); | |
| 9447 %} | |
| 9448 | |
| 9449 | |
| 9450 //----------Double Instructions------------------------------------------------ | |
| 9451 // Double Math | |
| 9452 | |
| 9453 // Compare & branch | |
| 9454 | |
| 9455 // P6 version of float compare, sets condition codes in EFLAGS | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9456 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9457 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9458 match(Set cr (CmpD src1 src2)); | |
| 9459 effect(KILL rax); | |
| 9460 ins_cost(150); | |
| 9461 format %{ "FLD $src1\n\t" | |
| 9462 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9463 "JNP exit\n\t" | |
| 9464 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9465 "SAHF\n" | |
| 9466 "exit:\tNOP // avoid branch to branch" %} | |
| 9467 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9468 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9469 OpcP, RegOpc(src2), |
| 9470 cmpF_P6_fixup ); | |
| 9471 ins_pipe( pipe_slow ); | |
| 9472 %} | |
| 9473 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9474 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9475 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9476 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9477 ins_cost(150); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9478 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9479 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9480 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9481 ins_encode( Push_Reg_DPR(src1), |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9482 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9483 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9484 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9485 |
| 0 | 9486 // Compare & branch |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9487 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9488 predicate(UseSSE<=1); |
| 9489 match(Set cr (CmpD src1 src2)); | |
| 9490 effect(KILL rax); | |
| 9491 ins_cost(200); | |
| 9492 format %{ "FLD $src1\n\t" | |
| 9493 "FCOMp $src2\n\t" | |
| 9494 "FNSTSW AX\n\t" | |
| 9495 "TEST AX,0x400\n\t" | |
| 9496 "JZ,s flags\n\t" | |
| 9497 "MOV AH,1\t# unordered treat as LT\n" | |
| 9498 "flags:\tSAHF" %} | |
| 9499 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9500 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9501 OpcP, RegOpc(src2), |
| 9502 fpu_flags); | |
| 9503 ins_pipe( pipe_slow ); | |
| 9504 %} | |
| 9505 | |
| 9506 // Compare vs zero into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
9507 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9508 predicate(UseSSE<=1); |
| 9509 match(Set dst (CmpD3 src1 zero)); | |
| 9510 effect(KILL cr, KILL rax); | |
| 9511 ins_cost(280); | |
| 9512 format %{ "FTSTD $dst,$src1" %} | |
| 9513 opcode(0xE4, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9514 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9515 OpcS, OpcP, PopFPU, |
| 9516 CmpF_Result(dst)); | |
| 9517 ins_pipe( pipe_slow ); | |
| 9518 %} | |
| 9519 | |
| 9520 // Compare into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
9521 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9522 predicate(UseSSE<=1); |
| 9523 match(Set dst (CmpD3 src1 src2)); | |
| 9524 effect(KILL cr, KILL rax); | |
| 9525 ins_cost(300); | |
| 9526 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9527 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9528 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9529 OpcP, RegOpc(src2), |
| 9530 CmpF_Result(dst)); | |
| 9531 ins_pipe( pipe_slow ); | |
| 9532 %} | |
| 9533 | |
| 9534 // float compare and set condition codes in EFLAGS by XMM regs | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9535 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9536 predicate(UseSSE>=2); |
| 4759 | 9537 match(Set cr (CmpD src1 src2)); |
| 9538 ins_cost(145); | |
| 9539 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9540 "JNP,s exit\n\t" | |
| 9541 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9542 "AND [rsp], #0xffffff2b\n\t" | |
| 9543 "POPF\n" | |
| 9544 "exit:" %} | |
| 9545 ins_encode %{ | |
| 9546 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9547 emit_cmpfp_fixup(_masm); | |
| 9548 %} | |
| 9549 ins_pipe( pipe_slow ); | |
| 9550 %} | |
| 9551 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9552 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9553 predicate(UseSSE>=2); |
| 4759 | 9554 match(Set cr (CmpD src1 src2)); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9555 ins_cost(100); |
| 4759 | 9556 format %{ "UCOMISD $src1,$src2" %} |
| 9557 ins_encode %{ | |
| 9558 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9559 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9560 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9561 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9562 |
| 0 | 9563 // float compare and set condition codes in EFLAGS by XMM regs |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9564 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9565 predicate(UseSSE>=2); |
| 4759 | 9566 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9567 ins_cost(145); |
| 4759 | 9568 format %{ "UCOMISD $src1,$src2\n\t" |
| 9569 "JNP,s exit\n\t" | |
| 9570 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9571 "AND [rsp], #0xffffff2b\n\t" | |
| 9572 "POPF\n" | |
| 9573 "exit:" %} | |
| 9574 ins_encode %{ | |
| 9575 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9576 emit_cmpfp_fixup(_masm); | |
| 9577 %} | |
| 9578 ins_pipe( pipe_slow ); | |
| 9579 %} | |
| 9580 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9581 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9582 predicate(UseSSE>=2); |
| 4759 | 9583 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9584 ins_cost(100); |
| 4759 | 9585 format %{ "UCOMISD $src1,$src2" %} |
| 9586 ins_encode %{ | |
| 9587 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9588 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9589 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9590 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9591 |
| 0 | 9592 // Compare into -1,0,1 in XMM |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9593 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9594 predicate(UseSSE>=2); |
| 9595 match(Set dst (CmpD3 src1 src2)); | |
| 9596 effect(KILL cr); | |
| 9597 ins_cost(255); | |
| 4759 | 9598 format %{ "UCOMISD $src1, $src2\n\t" |
| 9599 "MOV $dst, #-1\n\t" | |
| 9600 "JP,s done\n\t" | |
| 9601 "JB,s done\n\t" | |
| 9602 "SETNE $dst\n\t" | |
| 9603 "MOVZB $dst, $dst\n" | |
| 9604 "done:" %} | |
| 9605 ins_encode %{ | |
| 9606 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9607 emit_cmpfp3(_masm, $dst$$Register); | |
| 9608 %} | |
| 0 | 9609 ins_pipe( pipe_slow ); |
| 9610 %} | |
| 9611 | |
| 9612 // Compare into -1,0,1 in XMM and memory | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9613 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9614 predicate(UseSSE>=2); |
| 4759 | 9615 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9616 effect(KILL cr); |
| 9617 ins_cost(275); | |
| 4759 | 9618 format %{ "UCOMISD $src1, $src2\n\t" |
| 9619 "MOV $dst, #-1\n\t" | |
| 9620 "JP,s done\n\t" | |
| 9621 "JB,s done\n\t" | |
| 9622 "SETNE $dst\n\t" | |
| 9623 "MOVZB $dst, $dst\n" | |
| 9624 "done:" %} | |
| 9625 ins_encode %{ | |
| 9626 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9627 emit_cmpfp3(_masm, $dst$$Register); | |
| 9628 %} | |
| 0 | 9629 ins_pipe( pipe_slow ); |
| 9630 %} | |
| 9631 | |
| 9632 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9633 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9634 predicate (UseSSE <=1); |
| 9635 match(Set dst (SubD dst src)); | |
| 9636 | |
| 9637 format %{ "FLD $src\n\t" | |
| 9638 "DSUBp $dst,ST" %} | |
| 9639 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9640 ins_cost(150); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9641 ins_encode( Push_Reg_DPR(src), |
| 0 | 9642 OpcP, RegOpc(dst) ); |
| 9643 ins_pipe( fpu_reg_reg ); | |
| 9644 %} | |
| 9645 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9646 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9647 predicate (UseSSE <=1); |
| 9648 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9649 ins_cost(250); | |
| 9650 | |
| 9651 format %{ "FLD $src2\n\t" | |
| 9652 "DSUB ST,$src1\n\t" | |
| 9653 "FSTP_D $dst\t# D-round" %} | |
| 9654 opcode(0xD8, 0x5); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9655 ins_encode( Push_Reg_DPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9656 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9657 ins_pipe( fpu_mem_reg_reg ); |
| 9658 %} | |
| 9659 | |
| 9660 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9661 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9662 predicate (UseSSE <=1); |
| 9663 match(Set dst (SubD dst (LoadD src))); | |
| 9664 ins_cost(150); | |
| 9665 | |
| 9666 format %{ "FLD $src\n\t" | |
| 9667 "DSUBp $dst,ST" %} | |
| 9668 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9669 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9670 OpcP, RegOpc(dst) ); | |
| 9671 ins_pipe( fpu_reg_mem ); | |
| 9672 %} | |
| 9673 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9674 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9675 predicate (UseSSE<=1); |
| 9676 match(Set dst (AbsD src)); | |
| 9677 ins_cost(100); | |
| 9678 format %{ "FABS" %} | |
| 9679 opcode(0xE1, 0xD9); | |
| 9680 ins_encode( OpcS, OpcP ); | |
| 9681 ins_pipe( fpu_reg_reg ); | |
| 9682 %} | |
| 9683 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9684 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9685 predicate(UseSSE<=1); |
| 9686 match(Set dst (NegD src)); | |
| 9687 ins_cost(100); | |
| 9688 format %{ "FCHS" %} | |
| 9689 opcode(0xE0, 0xD9); | |
| 9690 ins_encode( OpcS, OpcP ); | |
| 9691 ins_pipe( fpu_reg_reg ); | |
| 9692 %} | |
| 9693 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9694 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9695 predicate(UseSSE<=1); |
| 9696 match(Set dst (AddD dst src)); | |
| 9697 format %{ "FLD $src\n\t" | |
| 9698 "DADD $dst,ST" %} | |
| 9699 size(4); | |
| 9700 ins_cost(150); | |
| 9701 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9702 ins_encode( Push_Reg_DPR(src), |
| 0 | 9703 OpcP, RegOpc(dst) ); |
| 9704 ins_pipe( fpu_reg_reg ); | |
| 9705 %} | |
| 9706 | |
| 9707 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9708 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9709 predicate(UseSSE<=1); |
| 9710 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9711 ins_cost(250); | |
| 9712 | |
| 9713 format %{ "FLD $src2\n\t" | |
| 9714 "DADD ST,$src1\n\t" | |
| 9715 "FSTP_D $dst\t# D-round" %} | |
| 9716 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9717 ins_encode( Push_Reg_DPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9718 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9719 ins_pipe( fpu_mem_reg_reg ); |
| 9720 %} | |
| 9721 | |
| 9722 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9723 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9724 predicate(UseSSE<=1); |
| 9725 match(Set dst (AddD dst (LoadD src))); | |
| 9726 ins_cost(150); | |
| 9727 | |
| 9728 format %{ "FLD $src\n\t" | |
| 9729 "DADDp $dst,ST" %} | |
| 9730 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9731 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9732 OpcP, RegOpc(dst) ); | |
| 9733 ins_pipe( fpu_reg_mem ); | |
| 9734 %} | |
| 9735 | |
| 9736 // add-to-memory | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9737 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9738 predicate(UseSSE<=1); |
| 9739 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9740 ins_cost(150); | |
| 9741 | |
| 9742 format %{ "FLD_D $dst\n\t" | |
| 9743 "DADD ST,$src\n\t" | |
| 9744 "FST_D $dst" %} | |
| 9745 opcode(0xDD, 0x0); | |
| 9746 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9747 Opcode(0xD8), RegOpc(src), | |
| 9748 set_instruction_start, | |
| 9749 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9750 ins_pipe( fpu_reg_mem ); | |
| 9751 %} | |
| 9752 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9753 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9754 predicate(UseSSE<=1); |
| 2008 | 9755 match(Set dst (AddD dst con)); |
| 0 | 9756 ins_cost(125); |
| 9757 format %{ "FLD1\n\t" | |
| 9758 "DADDp $dst,ST" %} | |
| 2008 | 9759 ins_encode %{ |
| 9760 __ fld1(); | |
| 9761 __ faddp($dst$$reg); | |
| 9762 %} | |
| 9763 ins_pipe(fpu_reg); | |
| 9764 %} | |
| 9765 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9766 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9767 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9768 match(Set dst (AddD dst con)); |
| 0 | 9769 ins_cost(200); |
| 2008 | 9770 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9771 "DADDp $dst,ST" %} |
| 2008 | 9772 ins_encode %{ |
| 9773 __ fld_d($constantaddress($con)); | |
| 9774 __ faddp($dst$$reg); | |
| 9775 %} | |
| 9776 ins_pipe(fpu_reg_mem); | |
| 0 | 9777 %} |
| 9778 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9779 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9780 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9781 match(Set dst (RoundDouble (AddD src con))); | |
| 9782 ins_cost(200); | |
| 2008 | 9783 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9784 "DADD ST,$src\n\t" |
| 9785 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9786 ins_encode %{ |
| 9787 __ fld_d($constantaddress($con)); | |
| 9788 __ fadd($src$$reg); | |
| 9789 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9790 %} | |
| 9791 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9792 %} |
| 9793 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9794 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9795 predicate(UseSSE<=1); |
| 9796 match(Set dst (MulD dst src)); | |
| 9797 format %{ "FLD $src\n\t" | |
| 9798 "DMULp $dst,ST" %} | |
| 9799 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9800 ins_cost(150); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9801 ins_encode( Push_Reg_DPR(src), |
| 0 | 9802 OpcP, RegOpc(dst) ); |
| 9803 ins_pipe( fpu_reg_reg ); | |
| 9804 %} | |
| 9805 | |
| 9806 // Strict FP instruction biases argument before multiply then | |
| 9807 // biases result to avoid double rounding of subnormals. | |
| 9808 // | |
| 9809 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9810 // load arg2 | |
| 9811 // multiply scaled arg1 by arg2 | |
| 9812 // rescale product by 2^(15360) | |
| 9813 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9814 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9815 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9816 match(Set dst (MulD dst src)); | |
| 9817 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9818 | |
| 9819 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9820 "DMULp $dst,ST\n\t" | |
| 9821 "FLD $src\n\t" | |
| 9822 "DMULp $dst,ST\n\t" | |
| 9823 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9824 "DMULp $dst,ST\n\t" %} | |
| 9825 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9826 ins_encode( strictfp_bias1(dst), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9827 Push_Reg_DPR(src), |
| 0 | 9828 OpcP, RegOpc(dst), |
| 9829 strictfp_bias2(dst) ); | |
| 9830 ins_pipe( fpu_reg_reg ); | |
| 9831 %} | |
| 9832 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9833 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9834 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9835 match(Set dst (MulD dst con)); |
| 0 | 9836 ins_cost(200); |
| 2008 | 9837 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9838 "DMULp $dst,ST" %} |
| 2008 | 9839 ins_encode %{ |
| 9840 __ fld_d($constantaddress($con)); | |
| 9841 __ fmulp($dst$$reg); | |
| 9842 %} | |
| 9843 ins_pipe(fpu_reg_mem); | |
| 0 | 9844 %} |
| 9845 | |
| 9846 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9847 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9848 predicate( UseSSE<=1 ); |
| 9849 match(Set dst (MulD dst (LoadD src))); | |
| 9850 ins_cost(200); | |
| 9851 format %{ "FLD_D $src\n\t" | |
| 9852 "DMULp $dst,ST" %} | |
| 9853 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9854 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9855 OpcP, RegOpc(dst) ); | |
| 9856 ins_pipe( fpu_reg_mem ); | |
| 9857 %} | |
| 9858 | |
| 9859 // | |
| 9860 // Cisc-alternate to reg-reg multiply | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9861 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9862 predicate( UseSSE<=1 ); |
| 9863 match(Set dst (MulD src (LoadD mem))); | |
| 9864 ins_cost(250); | |
| 9865 format %{ "FLD_D $mem\n\t" | |
| 9866 "DMUL ST,$src\n\t" | |
| 9867 "FSTP_D $dst" %} | |
| 9868 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9869 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9870 OpcReg_FPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9871 Pop_Reg_DPR(dst) ); |
| 0 | 9872 ins_pipe( fpu_reg_reg_mem ); |
| 9873 %} | |
| 9874 | |
| 9875 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9876 // MACRO3 -- addDPR a mulDPR |
| 0 | 9877 // This instruction is a '2-address' instruction in that the result goes |
| 9878 // back to src2. This eliminates a move from the macro; possibly the | |
| 9879 // register allocator will have to add it back (and maybe not). | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9880 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9881 predicate( UseSSE<=1 ); |
| 9882 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9883 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9884 "DMUL ST,$src1\n\t" | |
| 9885 "DADDp $src2,ST" %} | |
| 9886 ins_cost(250); | |
| 9887 opcode(0xDD); /* LoadD DD /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9888 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9889 FMul_ST_reg(src1), |
| 9890 FAddP_reg_ST(src2) ); | |
| 9891 ins_pipe( fpu_reg_reg_reg ); | |
| 9892 %} | |
| 9893 | |
| 9894 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9895 // MACRO3 -- subDPR a mulDPR |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9896 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9897 predicate( UseSSE<=1 ); |
| 9898 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9899 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9900 "DMUL ST,$src1\n\t" | |
| 9901 "DSUBRp $src2,ST" %} | |
| 9902 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9903 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9904 FMul_ST_reg(src1), |
| 9905 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9906 ins_pipe( fpu_reg_reg_reg ); | |
| 9907 %} | |
| 9908 | |
| 9909 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9910 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9911 predicate( UseSSE<=1 ); |
| 9912 match(Set dst (DivD dst src)); | |
| 9913 | |
| 9914 format %{ "FLD $src\n\t" | |
| 9915 "FDIVp $dst,ST" %} | |
| 9916 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9917 ins_cost(150); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9918 ins_encode( Push_Reg_DPR(src), |
| 0 | 9919 OpcP, RegOpc(dst) ); |
| 9920 ins_pipe( fpu_reg_reg ); | |
| 9921 %} | |
| 9922 | |
| 9923 // Strict FP instruction biases argument before division then | |
| 9924 // biases result, to avoid double rounding of subnormals. | |
| 9925 // | |
| 9926 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9927 // load divisor | |
| 9928 // divide scaled dividend by divisor | |
| 9929 // rescale quotient by 2^(15360) | |
| 9930 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9931 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9932 predicate (UseSSE<=1); |
| 9933 match(Set dst (DivD dst src)); | |
| 9934 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9935 ins_cost(01); | |
| 9936 | |
| 9937 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9938 "DMULp $dst,ST\n\t" | |
| 9939 "FLD $src\n\t" | |
| 9940 "FDIVp $dst,ST\n\t" | |
| 9941 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9942 "DMULp $dst,ST\n\t" %} | |
| 9943 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9944 ins_encode( strictfp_bias1(dst), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9945 Push_Reg_DPR(src), |
| 0 | 9946 OpcP, RegOpc(dst), |
| 9947 strictfp_bias2(dst) ); | |
| 9948 ins_pipe( fpu_reg_reg ); | |
| 9949 %} | |
| 9950 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9951 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9952 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9953 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9954 | |
| 9955 format %{ "FLD $src1\n\t" | |
| 9956 "FDIV ST,$src2\n\t" | |
| 9957 "FSTP_D $dst\t# D-round" %} | |
| 9958 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9959 ins_encode( Push_Reg_DPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9960 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9961 ins_pipe( fpu_mem_reg_reg ); |
| 9962 %} | |
| 9963 | |
| 9964 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9965 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9966 predicate(UseSSE<=1); |
| 9967 match(Set dst (ModD dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9968 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9969 |
| 9970 format %{ "DMOD $dst,$src" %} | |
| 9971 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9972 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9973 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9974 Push_Result_Mod_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9975 Pop_Reg_DPR(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9976 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9977 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9978 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9979 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9980 predicate(UseSSE>=2); |
| 9981 match(Set dst (ModD src0 src1)); | |
| 9982 effect(KILL rax, KILL cr); | |
| 9983 | |
| 9984 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9985 "\tMOVSD [ESP+0],$src1\n" | |
| 9986 "\tFLD_D [ESP+0]\n" | |
| 9987 "\tMOVSD [ESP+0],$src0\n" | |
| 9988 "\tFLD_D [ESP+0]\n" | |
| 9989 "loop:\tFPREM\n" | |
| 9990 "\tFWAIT\n" | |
| 9991 "\tFNSTSW AX\n" | |
| 9992 "\tSAHF\n" | |
| 9993 "\tJP loop\n" | |
| 9994 "\tFSTP_D [ESP+0]\n" | |
| 9995 "\tMOVSD $dst,[ESP+0]\n" | |
| 9996 "\tADD ESP,8\n" | |
| 9997 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9998 %} | |
| 9999 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10000 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10001 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10002 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10003 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10004 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10005 predicate (UseSSE<=1); |
| 10006 match(Set dst (SinD src)); | |
| 10007 ins_cost(1800); | |
| 10008 format %{ "DSIN $dst" %} | |
| 10009 opcode(0xD9, 0xFE); | |
| 10010 ins_encode( OpcP, OpcS ); | |
| 10011 ins_pipe( pipe_slow ); | |
| 10012 %} | |
| 10013 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10014 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 10015 predicate (UseSSE>=2); |
| 10016 match(Set dst (SinD dst)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10017 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10018 ins_cost(1800); |
| 10019 format %{ "DSIN $dst" %} | |
| 10020 opcode(0xD9, 0xFE); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10021 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10022 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10023 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10024 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10025 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10026 predicate (UseSSE<=1); |
| 10027 match(Set dst (CosD src)); | |
| 10028 ins_cost(1800); | |
| 10029 format %{ "DCOS $dst" %} | |
| 10030 opcode(0xD9, 0xFF); | |
| 10031 ins_encode( OpcP, OpcS ); | |
| 10032 ins_pipe( pipe_slow ); | |
| 10033 %} | |
| 10034 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10035 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 10036 predicate (UseSSE>=2); |
| 10037 match(Set dst (CosD dst)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10038 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10039 ins_cost(1800); |
| 10040 format %{ "DCOS $dst" %} | |
| 10041 opcode(0xD9, 0xFF); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10042 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10043 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10044 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10045 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10046 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10047 predicate (UseSSE<=1); |
| 10048 match(Set dst(TanD src)); | |
| 10049 format %{ "DTAN $dst" %} | |
| 10050 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10051 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 10052 ins_pipe( pipe_slow ); | |
| 10053 %} | |
| 10054 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10055 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 10056 predicate (UseSSE>=2); |
| 10057 match(Set dst(TanD dst)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10058 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10059 format %{ "DTAN $dst" %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10060 ins_encode( Push_SrcD(dst), |
| 0 | 10061 Opcode(0xD9), Opcode(0xF2), // fptan |
| 10062 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10063 Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10064 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10065 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10066 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10067 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 10068 predicate (UseSSE<=1); |
| 10069 match(Set dst(AtanD dst src)); | |
| 10070 format %{ "DATA $dst,$src" %} | |
| 10071 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10072 ins_encode( Push_Reg_DPR(src), |
| 0 | 10073 OpcP, OpcS, RegOpc(dst) ); |
| 10074 ins_pipe( pipe_slow ); | |
| 10075 %} | |
| 10076 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10077 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10078 predicate (UseSSE>=2); |
| 10079 match(Set dst(AtanD dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10080 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10081 format %{ "DATA $dst,$src" %} |
| 10082 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10083 ins_encode( Push_SrcD(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10084 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10085 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10086 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10087 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10088 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 10089 predicate (UseSSE<=1); |
| 10090 match(Set dst (SqrtD src)); | |
| 10091 format %{ "DSQRT $dst,$src" %} | |
| 10092 opcode(0xFA, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10093 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10094 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10095 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10096 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10097 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10098 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10099 predicate (UseSSE<=1); |
| 10100 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10101 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10102 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10103 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10104 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10105 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10106 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10107 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10108 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10109 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10110 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10111 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10112 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10113 predicate (UseSSE>=2); |
| 10114 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10115 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10116 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10117 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10118 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10119 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10120 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10121 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10122 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10123 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10124 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10125 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10126 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10127 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10128 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10129 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10130 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10131 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10132 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10133 predicate (UseSSE<=1); |
| 10134 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10135 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10136 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10137 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10138 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10139 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10140 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10141 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10142 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10143 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10144 predicate (UseSSE>=2); |
| 10145 match(Set dst (ExpD src)); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10146 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10147 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10148 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10149 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10150 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10151 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10152 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10153 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10154 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10155 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10156 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10157 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10158 %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10159 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10160 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10161 predicate (UseSSE<=1); |
| 10162 // The source Double operand on FPU stack | |
| 10163 match(Set dst (Log10D src)); | |
| 10164 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10165 // fxch ; swap ST(0) with ST(1) | |
| 10166 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10167 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10168 "FXCH \n\t" | |
| 10169 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10170 %} | |
| 10171 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10172 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10173 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10174 | |
| 10175 ins_pipe( pipe_slow ); | |
| 10176 %} | |
| 10177 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10178 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10179 predicate (UseSSE>=2); |
| 10180 effect(KILL cr); | |
| 10181 match(Set dst (Log10D src)); | |
| 10182 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10183 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10184 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10185 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10186 %} | |
| 10187 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10188 Push_SrcD(src), |
| 0 | 10189 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10190 Push_ResultD(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10191 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10192 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10193 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10194 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10195 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10196 predicate (UseSSE<=1); |
| 10197 // The source Double operand on FPU stack | |
| 10198 match(Set dst (LogD src)); | |
| 10199 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10200 // fxch ; swap ST(0) with ST(1) | |
| 10201 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10202 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10203 "FXCH \n\t" | |
| 10204 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10205 %} | |
| 10206 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10207 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10208 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10209 | |
| 10210 ins_pipe( pipe_slow ); | |
| 10211 %} | |
| 10212 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10213 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10214 predicate (UseSSE>=2); |
| 10215 effect(KILL cr); | |
| 10216 // The source and result Double operands in XMM registers | |
| 10217 match(Set dst (LogD src)); | |
| 10218 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10219 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10220 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10221 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10222 %} | |
| 10223 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10224 Push_SrcD(src), |
| 0 | 10225 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10226 Push_ResultD(dst)); |
| 0 | 10227 ins_pipe( pipe_slow ); |
| 10228 %} | |
| 10229 | |
| 10230 //-------------Float Instructions------------------------------- | |
| 10231 // Float Math | |
| 10232 | |
| 10233 // Code for float compare: | |
| 10234 // fcompp(); | |
| 10235 // fwait(); fnstsw_ax(); | |
| 10236 // sahf(); | |
| 10237 // movl(dst, unordered_result); | |
| 10238 // jcc(Assembler::parity, exit); | |
| 10239 // movl(dst, less_result); | |
| 10240 // jcc(Assembler::below, exit); | |
| 10241 // movl(dst, equal_result); | |
| 10242 // jcc(Assembler::equal, exit); | |
| 10243 // movl(dst, greater_result); | |
| 10244 // exit: | |
| 10245 | |
| 10246 // P6 version of float compare, sets condition codes in EFLAGS | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10247 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10248 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10249 match(Set cr (CmpF src1 src2)); | |
| 10250 effect(KILL rax); | |
| 10251 ins_cost(150); | |
| 10252 format %{ "FLD $src1\n\t" | |
| 10253 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10254 "JNP exit\n\t" | |
| 10255 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10256 "SAHF\n" | |
| 10257 "exit:\tNOP // avoid branch to branch" %} | |
| 10258 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10259 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10260 OpcP, RegOpc(src2), |
| 10261 cmpF_P6_fixup ); | |
| 10262 ins_pipe( pipe_slow ); | |
| 10263 %} | |
| 10264 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10265 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10266 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10267 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10268 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10269 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10270 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10271 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10272 ins_encode( Push_Reg_DPR(src1), |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10273 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10274 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10275 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10276 |
| 0 | 10277 |
| 10278 // Compare & branch | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10279 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10280 predicate(UseSSE == 0); |
| 10281 match(Set cr (CmpF src1 src2)); | |
| 10282 effect(KILL rax); | |
| 10283 ins_cost(200); | |
| 10284 format %{ "FLD $src1\n\t" | |
| 10285 "FCOMp $src2\n\t" | |
| 10286 "FNSTSW AX\n\t" | |
| 10287 "TEST AX,0x400\n\t" | |
| 10288 "JZ,s flags\n\t" | |
| 10289 "MOV AH,1\t# unordered treat as LT\n" | |
| 10290 "flags:\tSAHF" %} | |
| 10291 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10292 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10293 OpcP, RegOpc(src2), |
| 10294 fpu_flags); | |
| 10295 ins_pipe( pipe_slow ); | |
| 10296 %} | |
| 10297 | |
| 10298 // Compare vs zero into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10299 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10300 predicate(UseSSE == 0); |
| 10301 match(Set dst (CmpF3 src1 zero)); | |
| 10302 effect(KILL cr, KILL rax); | |
| 10303 ins_cost(280); | |
| 10304 format %{ "FTSTF $dst,$src1" %} | |
| 10305 opcode(0xE4, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10306 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10307 OpcS, OpcP, PopFPU, |
| 10308 CmpF_Result(dst)); | |
| 10309 ins_pipe( pipe_slow ); | |
| 10310 %} | |
| 10311 | |
| 10312 // Compare into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10313 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10314 predicate(UseSSE == 0); |
| 10315 match(Set dst (CmpF3 src1 src2)); | |
| 10316 effect(KILL cr, KILL rax); | |
| 10317 ins_cost(300); | |
| 10318 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10319 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10320 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10321 OpcP, RegOpc(src2), |
| 10322 CmpF_Result(dst)); | |
| 10323 ins_pipe( pipe_slow ); | |
| 10324 %} | |
| 10325 | |
| 10326 // float compare and set condition codes in EFLAGS by XMM regs | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10327 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10328 predicate(UseSSE>=1); |
| 4759 | 10329 match(Set cr (CmpF src1 src2)); |
| 0 | 10330 ins_cost(145); |
| 4759 | 10331 format %{ "UCOMISS $src1,$src2\n\t" |
| 10332 "JNP,s exit\n\t" | |
| 10333 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10334 "AND [rsp], #0xffffff2b\n\t" | |
| 10335 "POPF\n" | |
| 10336 "exit:" %} | |
| 10337 ins_encode %{ | |
| 10338 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10339 emit_cmpfp_fixup(_masm); | |
| 10340 %} | |
| 10341 ins_pipe( pipe_slow ); | |
| 10342 %} | |
| 10343 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10344 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10345 predicate(UseSSE>=1); |
| 4759 | 10346 match(Set cr (CmpF src1 src2)); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10347 ins_cost(100); |
| 4759 | 10348 format %{ "UCOMISS $src1,$src2" %} |
| 10349 ins_encode %{ | |
| 10350 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10351 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10352 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10353 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10354 |
| 0 | 10355 // float compare and set condition codes in EFLAGS by XMM regs |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10356 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10357 predicate(UseSSE>=1); |
| 4759 | 10358 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10359 ins_cost(165); |
| 4759 | 10360 format %{ "UCOMISS $src1,$src2\n\t" |
| 10361 "JNP,s exit\n\t" | |
| 10362 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10363 "AND [rsp], #0xffffff2b\n\t" | |
| 10364 "POPF\n" | |
| 10365 "exit:" %} | |
| 10366 ins_encode %{ | |
| 10367 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10368 emit_cmpfp_fixup(_masm); | |
| 10369 %} | |
| 10370 ins_pipe( pipe_slow ); | |
| 10371 %} | |
| 10372 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10373 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10374 predicate(UseSSE>=1); |
| 4759 | 10375 match(Set cr (CmpF src1 (LoadF src2))); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10376 ins_cost(100); |
| 4759 | 10377 format %{ "UCOMISS $src1,$src2" %} |
| 10378 ins_encode %{ | |
| 10379 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10380 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10381 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10382 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10383 |
| 0 | 10384 // Compare into -1,0,1 in XMM |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10385 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10386 predicate(UseSSE>=1); |
| 10387 match(Set dst (CmpF3 src1 src2)); | |
| 10388 effect(KILL cr); | |
| 10389 ins_cost(255); | |
| 4759 | 10390 format %{ "UCOMISS $src1, $src2\n\t" |
| 10391 "MOV $dst, #-1\n\t" | |
| 10392 "JP,s done\n\t" | |
| 10393 "JB,s done\n\t" | |
| 10394 "SETNE $dst\n\t" | |
| 10395 "MOVZB $dst, $dst\n" | |
| 10396 "done:" %} | |
| 10397 ins_encode %{ | |
| 10398 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10399 emit_cmpfp3(_masm, $dst$$Register); | |
| 10400 %} | |
| 0 | 10401 ins_pipe( pipe_slow ); |
| 10402 %} | |
| 10403 | |
| 10404 // Compare into -1,0,1 in XMM and memory | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10405 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10406 predicate(UseSSE>=1); |
| 4759 | 10407 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10408 effect(KILL cr); |
| 10409 ins_cost(275); | |
| 4759 | 10410 format %{ "UCOMISS $src1, $src2\n\t" |
| 10411 "MOV $dst, #-1\n\t" | |
| 10412 "JP,s done\n\t" | |
| 10413 "JB,s done\n\t" | |
| 10414 "SETNE $dst\n\t" | |
| 10415 "MOVZB $dst, $dst\n" | |
| 10416 "done:" %} | |
| 10417 ins_encode %{ | |
| 10418 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10419 emit_cmpfp3(_masm, $dst$$Register); | |
| 10420 %} | |
| 0 | 10421 ins_pipe( pipe_slow ); |
| 10422 %} | |
| 10423 | |
| 10424 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10425 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10426 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10427 match(Set dst (SubF src1 src2)); | |
| 10428 | |
| 10429 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10430 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10431 ins_encode( Push_Reg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10432 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10433 Pop_Mem_FPR(dst) ); |
| 0 | 10434 ins_pipe( fpu_mem_reg_reg ); |
| 10435 %} | |
| 10436 // | |
| 10437 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10438 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10439 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10440 match(Set dst (SubF dst src)); | |
| 10441 | |
| 10442 format %{ "FSUB $dst,$src" %} | |
| 10443 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10444 ins_encode( Push_Reg_FPR(src), |
| 0 | 10445 OpcP, RegOpc(dst) ); |
| 10446 ins_pipe( fpu_reg_reg ); | |
| 10447 %} | |
| 10448 | |
| 10449 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10450 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10451 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10452 match(Set dst (AddF src1 src2)); | |
| 10453 | |
| 10454 format %{ "FADD $dst,$src1,$src2" %} | |
| 10455 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10456 ins_encode( Push_Reg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10457 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10458 Pop_Mem_FPR(dst) ); |
| 0 | 10459 ins_pipe( fpu_mem_reg_reg ); |
| 10460 %} | |
| 10461 // | |
| 10462 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10463 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10464 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10465 match(Set dst (AddF dst src)); | |
| 10466 | |
| 10467 format %{ "FLD $src\n\t" | |
| 10468 "FADDp $dst,ST" %} | |
| 10469 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10470 ins_encode( Push_Reg_FPR(src), |
| 0 | 10471 OpcP, RegOpc(dst) ); |
| 10472 ins_pipe( fpu_reg_reg ); | |
| 10473 %} | |
| 10474 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10475 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10476 predicate(UseSSE==0); |
| 10477 match(Set dst (AbsF src)); | |
| 10478 ins_cost(100); | |
| 10479 format %{ "FABS" %} | |
| 10480 opcode(0xE1, 0xD9); | |
| 10481 ins_encode( OpcS, OpcP ); | |
| 10482 ins_pipe( fpu_reg_reg ); | |
| 10483 %} | |
| 10484 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10485 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10486 predicate(UseSSE==0); |
| 10487 match(Set dst (NegF src)); | |
| 10488 ins_cost(100); | |
| 10489 format %{ "FCHS" %} | |
| 10490 opcode(0xE0, 0xD9); | |
| 10491 ins_encode( OpcS, OpcP ); | |
| 10492 ins_pipe( fpu_reg_reg ); | |
| 10493 %} | |
| 10494 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10495 // Cisc-alternate to addFPR_reg |
| 0 | 10496 // Spill to obtain 24-bit precision |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10497 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10498 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10499 match(Set dst (AddF src1 (LoadF src2))); | |
| 10500 | |
| 10501 format %{ "FLD $src2\n\t" | |
| 10502 "FADD ST,$src1\n\t" | |
| 10503 "FSTP_S $dst" %} | |
| 10504 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10505 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10506 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10507 Pop_Mem_FPR(dst) ); |
| 0 | 10508 ins_pipe( fpu_mem_reg_mem ); |
| 10509 %} | |
| 10510 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10511 // Cisc-alternate to addFPR_reg |
| 0 | 10512 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10513 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10514 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10515 match(Set dst (AddF dst (LoadF src))); | |
| 10516 | |
| 10517 format %{ "FADD $dst,$src" %} | |
| 10518 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10519 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10520 OpcP, RegOpc(dst) ); | |
| 10521 ins_pipe( fpu_reg_mem ); | |
| 10522 %} | |
| 10523 | |
| 10524 // // Following two instructions for _222_mpegaudio | |
| 10525 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10526 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10527 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10528 match(Set dst (AddF src1 src2)); | |
| 10529 | |
| 10530 format %{ "FADD $dst,$src1,$src2" %} | |
| 10531 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10532 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10533 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10534 Pop_Mem_FPR(dst) ); |
| 0 | 10535 ins_pipe( fpu_mem_reg_mem ); |
| 10536 %} | |
| 10537 | |
| 10538 // Cisc-spill variant | |
| 10539 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10540 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10541 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10542 match(Set dst (AddF src1 (LoadF src2))); | |
| 10543 | |
| 10544 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10545 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10546 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10547 set_instruction_start, | |
| 10548 OpcP, RMopc_Mem(secondary,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10549 Pop_Mem_FPR(dst) ); |
| 0 | 10550 ins_pipe( fpu_mem_mem_mem ); |
| 10551 %} | |
| 10552 | |
| 10553 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10554 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10555 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10556 match(Set dst (AddF src1 src2)); | |
| 10557 | |
| 10558 format %{ "FADD $dst,$src1,$src2" %} | |
| 10559 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10560 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10561 set_instruction_start, | |
| 10562 OpcP, RMopc_Mem(secondary,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10563 Pop_Mem_FPR(dst) ); |
| 0 | 10564 ins_pipe( fpu_mem_mem_mem ); |
| 10565 %} | |
| 10566 | |
| 10567 | |
| 10568 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10569 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10570 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10571 match(Set dst (AddF src con)); |
| 10572 format %{ "FLD $src\n\t" | |
| 10573 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10574 "FSTP_S $dst" %} |
| 2008 | 10575 ins_encode %{ |
| 10576 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10577 __ fadd_s($constantaddress($con)); | |
| 10578 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10579 %} | |
| 10580 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10581 %} |
| 10582 // | |
| 10583 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10584 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10585 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10586 match(Set dst (AddF src con)); |
| 10587 format %{ "FLD $src\n\t" | |
| 10588 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10589 "FSTP $dst" %} | |
| 10590 ins_encode %{ | |
| 10591 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10592 __ fadd_s($constantaddress($con)); | |
| 10593 __ fstp_d($dst$$reg); | |
| 10594 %} | |
| 10595 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10596 %} |
| 10597 | |
| 10598 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10599 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10600 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10601 match(Set dst (MulF src1 src2)); | |
| 10602 | |
| 10603 format %{ "FLD $src1\n\t" | |
| 10604 "FMUL $src2\n\t" | |
| 10605 "FSTP_S $dst" %} | |
| 10606 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10607 ins_encode( Push_Reg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10608 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10609 Pop_Mem_FPR(dst) ); |
| 0 | 10610 ins_pipe( fpu_mem_reg_reg ); |
| 10611 %} | |
| 10612 // | |
| 10613 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10614 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10615 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10616 match(Set dst (MulF src1 src2)); | |
| 10617 | |
| 10618 format %{ "FLD $src1\n\t" | |
| 10619 "FMUL $src2\n\t" | |
| 10620 "FSTP_S $dst" %} | |
| 10621 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10622 ins_encode( Push_Reg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10623 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10624 Pop_Reg_FPR(dst) ); |
| 0 | 10625 ins_pipe( fpu_reg_reg_reg ); |
| 10626 %} | |
| 10627 | |
| 10628 | |
| 10629 // Spill to obtain 24-bit precision | |
| 10630 // Cisc-alternate to reg-reg multiply | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10631 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10632 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10633 match(Set dst (MulF src1 (LoadF src2))); | |
| 10634 | |
| 10635 format %{ "FLD_S $src2\n\t" | |
| 10636 "FMUL $src1\n\t" | |
| 10637 "FSTP_S $dst" %} | |
| 10638 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10639 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10640 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10641 Pop_Mem_FPR(dst) ); |
| 0 | 10642 ins_pipe( fpu_mem_reg_mem ); |
| 10643 %} | |
| 10644 // | |
| 10645 // This instruction does not round to 24-bits | |
| 10646 // Cisc-alternate to reg-reg multiply | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10647 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10648 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10649 match(Set dst (MulF src1 (LoadF src2))); | |
| 10650 | |
| 10651 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10652 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10653 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10654 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10655 Pop_Reg_FPR(dst) ); |
| 0 | 10656 ins_pipe( fpu_reg_reg_mem ); |
| 10657 %} | |
| 10658 | |
| 10659 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10660 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10661 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10662 match(Set dst (MulF src1 src2)); | |
| 10663 | |
| 10664 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10665 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10666 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10667 set_instruction_start, | |
| 10668 OpcP, RMopc_Mem(secondary,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10669 Pop_Mem_FPR(dst) ); |
| 0 | 10670 ins_pipe( fpu_mem_mem_mem ); |
| 10671 %} | |
| 10672 | |
| 10673 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10674 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10675 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10676 match(Set dst (MulF src con)); |
| 10677 | |
| 10678 format %{ "FLD $src\n\t" | |
| 10679 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10680 "FSTP_S $dst" %} | |
| 10681 ins_encode %{ | |
| 10682 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10683 __ fmul_s($constantaddress($con)); | |
| 10684 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10685 %} | |
| 10686 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10687 %} |
| 10688 // | |
| 10689 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10690 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10691 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10692 match(Set dst (MulF src con)); |
| 10693 | |
| 10694 format %{ "FLD $src\n\t" | |
| 10695 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10696 "FSTP $dst" %} | |
| 10697 ins_encode %{ | |
| 10698 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10699 __ fmul_s($constantaddress($con)); | |
| 10700 __ fstp_d($dst$$reg); | |
| 10701 %} | |
| 10702 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10703 %} |
| 10704 | |
| 10705 | |
| 10706 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10707 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10708 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10709 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10710 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10711 match(Set dst (MulF (LoadF mem1) src)); | |
| 10712 | |
| 10713 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10714 "FMUL ST,$src\n\t" | |
| 10715 "FSTP $dst" %} | |
| 10716 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10717 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10718 OpcReg_FPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10719 Pop_Reg_FPR(dst) ); |
| 0 | 10720 ins_pipe( fpu_reg_reg_mem ); |
| 10721 %} | |
| 10722 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10723 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10724 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10725 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10726 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10727 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10728 ins_cost(95); | |
| 10729 | |
| 10730 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10731 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10732 "FADD ST,$src2\n\t" |
| 10733 "FSTP $dst" %} | |
| 10734 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10735 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10736 FMul_ST_reg(src1), | |
| 10737 FAdd_ST_reg(src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10738 Pop_Reg_FPR(dst) ); |
| 0 | 10739 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10740 %} | |
| 10741 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10742 // MACRO3 -- addFPR a mulFPR |
| 0 | 10743 // This instruction does not round to 24-bits. It is a '2-address' |
| 10744 // instruction in that the result goes back to src2. This eliminates | |
| 10745 // a move from the macro; possibly the register allocator will have | |
| 10746 // to add it back (and maybe not). | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10747 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10748 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10749 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10750 | |
| 10751 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10752 "FMUL ST,$src1\n\t" | |
| 10753 "FADDP $src2,ST" %} | |
| 10754 opcode(0xD9); /* LoadF D9 /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10755 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10756 FMul_ST_reg(src1), |
| 10757 FAddP_reg_ST(src2) ); | |
| 10758 ins_pipe( fpu_reg_reg_reg ); | |
| 10759 %} | |
| 10760 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10761 // MACRO4 -- divFPR subFPR |
| 0 | 10762 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10763 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10764 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10765 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10766 | |
| 10767 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10768 "FSUB ST,$src1\n\t" | |
| 10769 "FDIV ST,$src3\n\t" | |
| 10770 "FSTP $dst" %} | |
| 10771 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10772 ins_encode( Push_Reg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10773 subFPR_divFPR_encode(src1,src3), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10774 Pop_Reg_FPR(dst) ); |
| 0 | 10775 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10776 %} | |
| 10777 | |
| 10778 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10779 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10780 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10781 match(Set dst (DivF src1 src2)); | |
| 10782 | |
| 10783 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10784 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10785 ins_encode( Push_Reg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10786 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10787 Pop_Mem_FPR(dst) ); |
| 0 | 10788 ins_pipe( fpu_mem_reg_reg ); |
| 10789 %} | |
| 10790 // | |
| 10791 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10792 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10793 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10794 match(Set dst (DivF dst src)); | |
| 10795 | |
| 10796 format %{ "FDIV $dst,$src" %} | |
| 10797 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10798 ins_encode( Push_Reg_FPR(src), |
| 0 | 10799 OpcP, RegOpc(dst) ); |
| 10800 ins_pipe( fpu_reg_reg ); | |
| 10801 %} | |
| 10802 | |
| 10803 | |
| 10804 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10805 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10806 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10807 match(Set dst (ModF src1 src2)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10808 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10809 |
| 10810 format %{ "FMOD $dst,$src1,$src2" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10811 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10812 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10813 Push_Result_Mod_DPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10814 Pop_Mem_FPR(dst)); |
| 0 | 10815 ins_pipe( pipe_slow ); |
| 10816 %} | |
| 10817 // | |
| 10818 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10819 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10820 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10821 match(Set dst (ModF dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10822 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10823 |
| 10824 format %{ "FMOD $dst,$src" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10825 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10826 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10827 Push_Result_Mod_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10828 Pop_Reg_FPR(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10829 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10830 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10831 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10832 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10833 predicate(UseSSE>=1); |
| 10834 match(Set dst (ModF src0 src1)); | |
| 10835 effect(KILL rax, KILL cr); | |
| 10836 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10837 "\tMOVSS [ESP+0],$src1\n" | |
| 10838 "\tFLD_S [ESP+0]\n" | |
| 10839 "\tMOVSS [ESP+0],$src0\n" | |
| 10840 "\tFLD_S [ESP+0]\n" | |
| 10841 "loop:\tFPREM\n" | |
| 10842 "\tFWAIT\n" | |
| 10843 "\tFNSTSW AX\n" | |
| 10844 "\tSAHF\n" | |
| 10845 "\tJP loop\n" | |
| 10846 "\tFSTP_S [ESP+0]\n" | |
| 10847 "\tMOVSS $dst,[ESP+0]\n" | |
| 10848 "\tADD ESP,4\n" | |
| 10849 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10850 %} | |
| 10851 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10852 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10853 ins_pipe( pipe_slow ); |
| 10854 %} | |
| 10855 | |
| 10856 | |
| 10857 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10858 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10859 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10860 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10861 predicate(UseSSE==0); |
| 10862 match(Set dst (RoundFloat src)); | |
| 10863 ins_cost(125); | |
| 10864 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10865 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10866 ins_pipe( fpu_mem_reg ); |
| 10867 %} | |
| 10868 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10869 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10870 predicate(UseSSE<=1); |
| 10871 match(Set dst (RoundDouble src)); | |
| 10872 ins_cost(125); | |
| 10873 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10874 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10875 ins_pipe( fpu_mem_reg ); |
| 10876 %} | |
| 10877 | |
| 10878 // Force rounding to 24-bit precision and 6-bit exponent | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10879 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10880 predicate(UseSSE==0); |
| 10881 match(Set dst (ConvD2F src)); | |
| 10882 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10883 expand %{ | |
| 10884 roundFloat_mem_reg(dst,src); | |
| 10885 %} | |
| 10886 %} | |
| 10887 | |
| 10888 // Force rounding to 24-bit precision and 6-bit exponent | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10889 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10890 predicate(UseSSE==1); |
| 10891 match(Set dst (ConvD2F src)); | |
| 10892 effect( KILL cr ); | |
| 10893 format %{ "SUB ESP,4\n\t" | |
| 10894 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10895 "MOVSS $dst,[ESP]\n\t" | |
| 10896 "ADD ESP,4" %} | |
| 4759 | 10897 ins_encode %{ |
| 10898 __ subptr(rsp, 4); | |
| 10899 if ($src$$reg != FPR1L_enc) { | |
| 10900 __ fld_s($src$$reg-1); | |
| 10901 __ fstp_s(Address(rsp, 0)); | |
| 10902 } else { | |
| 10903 __ fst_s(Address(rsp, 0)); | |
| 10904 } | |
| 10905 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10906 __ addptr(rsp, 4); | |
| 10907 %} | |
| 0 | 10908 ins_pipe( pipe_slow ); |
| 10909 %} | |
| 10910 | |
| 10911 // Force rounding double precision to single precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10912 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10913 predicate(UseSSE>=2); |
| 10914 match(Set dst (ConvD2F src)); | |
| 10915 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10916 ins_encode %{ |
| 10917 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10918 %} | |
| 0 | 10919 ins_pipe( pipe_slow ); |
| 10920 %} | |
| 10921 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10922 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10923 predicate(UseSSE==0); |
| 10924 match(Set dst (ConvF2D src)); | |
| 10925 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10926 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10927 ins_pipe( fpu_reg_reg ); |
| 10928 %} | |
| 10929 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10930 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10931 predicate(UseSSE==1); |
| 10932 match(Set dst (ConvF2D src)); | |
| 10933 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10934 expand %{ | |
| 10935 roundDouble_mem_reg(dst,src); | |
| 10936 %} | |
| 10937 %} | |
| 10938 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10939 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10940 predicate(UseSSE==1); |
| 10941 match(Set dst (ConvF2D src)); | |
| 10942 effect( KILL cr ); | |
| 10943 format %{ "SUB ESP,4\n\t" | |
| 10944 "MOVSS [ESP] $src\n\t" | |
| 10945 "FLD_S [ESP]\n\t" | |
| 10946 "ADD ESP,4\n\t" | |
| 10947 "FSTP $dst\t# D-round" %} | |
| 4759 | 10948 ins_encode %{ |
| 10949 __ subptr(rsp, 4); | |
| 10950 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10951 __ fld_s(Address(rsp, 0)); | |
| 10952 __ addptr(rsp, 4); | |
| 10953 __ fstp_d($dst$$reg); | |
| 10954 %} | |
| 0 | 10955 ins_pipe( pipe_slow ); |
| 10956 %} | |
| 10957 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10958 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10959 predicate(UseSSE>=2); |
| 10960 match(Set dst (ConvF2D src)); | |
| 10961 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10962 ins_encode %{ |
| 10963 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10964 %} | |
| 0 | 10965 ins_pipe( pipe_slow ); |
| 10966 %} | |
| 10967 | |
| 10968 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10969 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10970 predicate(UseSSE<=1); |
| 10971 match(Set dst (ConvD2I src)); | |
| 10972 effect( KILL tmp, KILL cr ); | |
| 10973 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10974 "FLDCW trunc mode\n\t" | |
| 10975 "SUB ESP,4\n\t" | |
| 10976 "FISTp [ESP + #0]\n\t" | |
| 10977 "FLDCW std/24-bit mode\n\t" | |
| 10978 "POP EAX\n\t" | |
| 10979 "CMP EAX,0x80000000\n\t" | |
| 10980 "JNE,s fast\n\t" | |
| 10981 "FLD_D $src\n\t" | |
| 10982 "CALL d2i_wrapper\n" | |
| 10983 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10984 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10985 ins_pipe( pipe_slow ); |
| 10986 %} | |
| 10987 | |
| 10988 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10989 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10990 predicate(UseSSE>=2); |
| 10991 match(Set dst (ConvD2I src)); | |
| 10992 effect( KILL tmp, KILL cr ); | |
| 10993 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10994 "CMP $dst,0x80000000\n\t" | |
| 10995 "JNE,s fast\n\t" | |
| 10996 "SUB ESP, 8\n\t" | |
| 10997 "MOVSD [ESP], $src\n\t" | |
| 10998 "FLD_D [ESP]\n\t" | |
| 10999 "ADD ESP, 8\n\t" | |
| 11000 "CALL d2i_wrapper\n" | |
| 11001 "fast:" %} | |
| 4759 | 11002 ins_encode %{ |
| 11003 Label fast; | |
| 11004 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 11005 __ cmpl($dst$$Register, 0x80000000); | |
| 11006 __ jccb(Assembler::notEqual, fast); | |
| 11007 __ subptr(rsp, 8); | |
| 11008 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 11009 __ fld_d(Address(rsp, 0)); | |
| 11010 __ addptr(rsp, 8); | |
| 11011 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 11012 __ bind(fast); | |
| 11013 %} | |
| 0 | 11014 ins_pipe( pipe_slow ); |
| 11015 %} | |
| 11016 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11017 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 11018 predicate(UseSSE<=1); |
| 11019 match(Set dst (ConvD2L src)); | |
| 11020 effect( KILL cr ); | |
| 11021 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 11022 "FLDCW trunc mode\n\t" | |
| 11023 "SUB ESP,8\n\t" | |
| 11024 "FISTp [ESP + #0]\n\t" | |
| 11025 "FLDCW std/24-bit mode\n\t" | |
| 11026 "POP EAX\n\t" | |
| 11027 "POP EDX\n\t" | |
| 11028 "CMP EDX,0x80000000\n\t" | |
| 11029 "JNE,s fast\n\t" | |
| 11030 "TEST EAX,EAX\n\t" | |
| 11031 "JNE,s fast\n\t" | |
| 11032 "FLD $src\n\t" | |
| 11033 "CALL d2l_wrapper\n" | |
| 11034 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11035 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 11036 ins_pipe( pipe_slow ); |
| 11037 %} | |
| 11038 | |
| 11039 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11040 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 11041 predicate (UseSSE>=2); |
| 11042 match(Set dst (ConvD2L src)); | |
| 11043 effect( KILL cr ); | |
| 11044 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 11045 "MOVSD [ESP],$src\n\t" | |
| 11046 "FLD_D [ESP]\n\t" | |
| 11047 "FLDCW trunc mode\n\t" | |
| 11048 "FISTp [ESP + #0]\n\t" | |
| 11049 "FLDCW std/24-bit mode\n\t" | |
| 11050 "POP EAX\n\t" | |
| 11051 "POP EDX\n\t" | |
| 11052 "CMP EDX,0x80000000\n\t" | |
| 11053 "JNE,s fast\n\t" | |
| 11054 "TEST EAX,EAX\n\t" | |
| 11055 "JNE,s fast\n\t" | |
| 11056 "SUB ESP,8\n\t" | |
| 11057 "MOVSD [ESP],$src\n\t" | |
| 11058 "FLD_D [ESP]\n\t" | |
| 4759 | 11059 "ADD ESP,8\n\t" |
| 0 | 11060 "CALL d2l_wrapper\n" |
| 11061 "fast:" %} | |
| 4759 | 11062 ins_encode %{ |
| 11063 Label fast; | |
| 11064 __ subptr(rsp, 8); | |
| 11065 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 11066 __ fld_d(Address(rsp, 0)); | |
| 11067 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11068 __ fistp_d(Address(rsp, 0)); | |
| 11069 // Restore the rounding mode, mask the exception | |
| 11070 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11071 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11072 } else { | |
| 11073 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11074 } | |
| 11075 // Load the converted long, adjust CPU stack | |
| 11076 __ pop(rax); | |
| 11077 __ pop(rdx); | |
| 11078 __ cmpl(rdx, 0x80000000); | |
| 11079 __ jccb(Assembler::notEqual, fast); | |
| 11080 __ testl(rax, rax); | |
| 11081 __ jccb(Assembler::notEqual, fast); | |
| 11082 __ subptr(rsp, 8); | |
| 11083 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 11084 __ fld_d(Address(rsp, 0)); | |
| 11085 __ addptr(rsp, 8); | |
| 11086 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11087 __ bind(fast); | |
| 11088 %} | |
| 0 | 11089 ins_pipe( pipe_slow ); |
| 11090 %} | |
| 11091 | |
| 11092 // Convert a double to an int. Java semantics require we do complex | |
| 11093 // manglations in the corner cases. So we set the rounding mode to | |
| 11094 // 'zero', store the darned double down as an int, and reset the | |
| 11095 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 11096 // if we would overflow or converted a NAN; we check for this and | |
| 11097 // and go the slow path if needed. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11098 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 11099 predicate(UseSSE==0); |
| 11100 match(Set dst (ConvF2I src)); | |
| 11101 effect( KILL tmp, KILL cr ); | |
| 11102 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 11103 "FLDCW trunc mode\n\t" | |
| 11104 "SUB ESP,4\n\t" | |
| 11105 "FISTp [ESP + #0]\n\t" | |
| 11106 "FLDCW std/24-bit mode\n\t" | |
| 11107 "POP EAX\n\t" | |
| 11108 "CMP EAX,0x80000000\n\t" | |
| 11109 "JNE,s fast\n\t" | |
| 11110 "FLD $src\n\t" | |
| 11111 "CALL d2i_wrapper\n" | |
| 11112 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11113 // DPR2I_encoding works for FPR2I |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11114 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 11115 ins_pipe( pipe_slow ); |
| 11116 %} | |
| 11117 | |
| 11118 // Convert a float in xmm to an int reg. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11119 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 11120 predicate(UseSSE>=1); |
| 11121 match(Set dst (ConvF2I src)); | |
| 11122 effect( KILL tmp, KILL cr ); | |
| 11123 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11124 "CMP $dst,0x80000000\n\t" | |
| 11125 "JNE,s fast\n\t" | |
| 11126 "SUB ESP, 4\n\t" | |
| 11127 "MOVSS [ESP], $src\n\t" | |
| 11128 "FLD [ESP]\n\t" | |
| 11129 "ADD ESP, 4\n\t" | |
| 11130 "CALL d2i_wrapper\n" | |
| 11131 "fast:" %} | |
| 4759 | 11132 ins_encode %{ |
| 11133 Label fast; | |
| 11134 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 11135 __ cmpl($dst$$Register, 0x80000000); | |
| 11136 __ jccb(Assembler::notEqual, fast); | |
| 11137 __ subptr(rsp, 4); | |
| 11138 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11139 __ fld_s(Address(rsp, 0)); | |
| 11140 __ addptr(rsp, 4); | |
| 11141 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 11142 __ bind(fast); | |
| 11143 %} | |
| 0 | 11144 ins_pipe( pipe_slow ); |
| 11145 %} | |
| 11146 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11147 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 11148 predicate(UseSSE==0); |
| 11149 match(Set dst (ConvF2L src)); | |
| 11150 effect( KILL cr ); | |
| 11151 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11152 "FLDCW trunc mode\n\t" | |
| 11153 "SUB ESP,8\n\t" | |
| 11154 "FISTp [ESP + #0]\n\t" | |
| 11155 "FLDCW std/24-bit mode\n\t" | |
| 11156 "POP EAX\n\t" | |
| 11157 "POP EDX\n\t" | |
| 11158 "CMP EDX,0x80000000\n\t" | |
| 11159 "JNE,s fast\n\t" | |
| 11160 "TEST EAX,EAX\n\t" | |
| 11161 "JNE,s fast\n\t" | |
| 11162 "FLD $src\n\t" | |
| 11163 "CALL d2l_wrapper\n" | |
| 11164 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11165 // DPR2L_encoding works for FPR2L |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11166 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 11167 ins_pipe( pipe_slow ); |
| 11168 %} | |
| 11169 | |
| 11170 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11171 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 11172 predicate (UseSSE>=1); |
| 11173 match(Set dst (ConvF2L src)); | |
| 11174 effect( KILL cr ); | |
| 11175 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11176 "MOVSS [ESP],$src\n\t" | |
| 11177 "FLD_S [ESP]\n\t" | |
| 11178 "FLDCW trunc mode\n\t" | |
| 11179 "FISTp [ESP + #0]\n\t" | |
| 11180 "FLDCW std/24-bit mode\n\t" | |
| 11181 "POP EAX\n\t" | |
| 11182 "POP EDX\n\t" | |
| 11183 "CMP EDX,0x80000000\n\t" | |
| 11184 "JNE,s fast\n\t" | |
| 11185 "TEST EAX,EAX\n\t" | |
| 11186 "JNE,s fast\n\t" | |
| 11187 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11188 "MOVSS [ESP],$src\n\t" | |
| 11189 "FLD_S [ESP]\n\t" | |
| 11190 "ADD ESP,4\n\t" | |
| 11191 "CALL d2l_wrapper\n" | |
| 11192 "fast:" %} | |
| 4759 | 11193 ins_encode %{ |
| 11194 Label fast; | |
| 11195 __ subptr(rsp, 8); | |
| 11196 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11197 __ fld_s(Address(rsp, 0)); | |
| 11198 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11199 __ fistp_d(Address(rsp, 0)); | |
| 11200 // Restore the rounding mode, mask the exception | |
| 11201 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11202 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11203 } else { | |
| 11204 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11205 } | |
| 11206 // Load the converted long, adjust CPU stack | |
| 11207 __ pop(rax); | |
| 11208 __ pop(rdx); | |
| 11209 __ cmpl(rdx, 0x80000000); | |
| 11210 __ jccb(Assembler::notEqual, fast); | |
| 11211 __ testl(rax, rax); | |
| 11212 __ jccb(Assembler::notEqual, fast); | |
| 11213 __ subptr(rsp, 4); | |
| 11214 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11215 __ fld_s(Address(rsp, 0)); | |
| 11216 __ addptr(rsp, 4); | |
| 11217 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11218 __ bind(fast); | |
| 11219 %} | |
| 0 | 11220 ins_pipe( pipe_slow ); |
| 11221 %} | |
| 11222 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11223 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11224 predicate( UseSSE<=1 ); |
| 11225 match(Set dst (ConvI2D src)); | |
| 11226 format %{ "FILD $src\n\t" | |
| 11227 "FSTP $dst" %} | |
| 11228 opcode(0xDB, 0x0); /* DB /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11229 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11230 ins_pipe( fpu_reg_mem ); |
| 11231 %} | |
| 11232 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11233 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11234 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11235 match(Set dst (ConvI2D src)); |
| 11236 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11237 ins_encode %{ |
| 11238 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11239 %} | |
| 0 | 11240 ins_pipe( pipe_slow ); |
| 11241 %} | |
| 11242 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11243 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11244 predicate( UseSSE>=2 ); |
| 11245 match(Set dst (ConvI2D (LoadI mem))); | |
| 11246 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11247 ins_encode %{ |
| 11248 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11249 %} | |
| 0 | 11250 ins_pipe( pipe_slow ); |
| 11251 %} | |
| 11252 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11253 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11254 %{ |
| 11255 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11256 match(Set dst (ConvI2D src)); | |
| 11257 | |
| 11258 format %{ "MOVD $dst,$src\n\t" | |
| 11259 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11260 ins_encode %{ | |
| 304 | 11261 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11262 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11263 %} | |
| 11264 ins_pipe(pipe_slow); // XXX | |
| 11265 %} | |
| 11266 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11267 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11268 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11269 match(Set dst (ConvI2D (LoadI mem))); | |
| 11270 format %{ "FILD $mem\n\t" | |
| 11271 "FSTP $dst" %} | |
| 11272 opcode(0xDB); /* DB /0 */ | |
| 11273 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11274 Pop_Reg_DPR(dst)); |
| 0 | 11275 ins_pipe( fpu_reg_mem ); |
| 11276 %} | |
| 11277 | |
| 11278 // Convert a byte to a float; no rounding step needed. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11279 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11280 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11281 match(Set dst (ConvI2F src)); | |
| 11282 format %{ "FILD $src\n\t" | |
| 11283 "FSTP $dst" %} | |
| 11284 | |
| 11285 opcode(0xDB, 0x0); /* DB /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11286 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11287 ins_pipe( fpu_reg_mem ); |
| 11288 %} | |
| 11289 | |
| 11290 // In 24-bit mode, force exponent rounding by storing back out | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11291 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11292 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11293 match(Set dst (ConvI2F src)); | |
| 11294 ins_cost(200); | |
| 11295 format %{ "FILD $src\n\t" | |
| 11296 "FSTP_S $dst" %} | |
| 11297 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11298 ins_encode( Push_Mem_I(src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11299 Pop_Mem_FPR(dst)); |
| 0 | 11300 ins_pipe( fpu_mem_mem ); |
| 11301 %} | |
| 11302 | |
| 11303 // In 24-bit mode, force exponent rounding by storing back out | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11304 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11305 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11306 match(Set dst (ConvI2F (LoadI mem))); | |
| 11307 ins_cost(200); | |
| 11308 format %{ "FILD $mem\n\t" | |
| 11309 "FSTP_S $dst" %} | |
| 11310 opcode(0xDB); /* DB /0 */ | |
| 11311 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11312 Pop_Mem_FPR(dst)); |
| 0 | 11313 ins_pipe( fpu_mem_mem ); |
| 11314 %} | |
| 11315 | |
| 11316 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11317 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11318 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11319 match(Set dst (ConvI2F src)); | |
| 11320 format %{ "FILD $src\n\t" | |
| 11321 "FSTP $dst" %} | |
| 11322 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11323 ins_encode( Push_Mem_I(src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11324 Pop_Reg_FPR(dst)); |
| 0 | 11325 ins_pipe( fpu_reg_mem ); |
| 11326 %} | |
| 11327 | |
| 11328 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11329 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11330 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11331 match(Set dst (ConvI2F (LoadI mem))); | |
| 11332 format %{ "FILD $mem\n\t" | |
| 11333 "FSTP $dst" %} | |
| 11334 opcode(0xDB); /* DB /0 */ | |
| 11335 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11336 Pop_Reg_FPR(dst)); |
| 0 | 11337 ins_pipe( fpu_reg_mem ); |
| 11338 %} | |
| 11339 | |
| 11340 // Convert an int to a float in xmm; no rounding step needed. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11341 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11342 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11343 match(Set dst (ConvI2F src)); |
| 11344 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11345 ins_encode %{ |
| 11346 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11347 %} | |
| 0 | 11348 ins_pipe( pipe_slow ); |
| 11349 %} | |
| 11350 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11351 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11352 %{ |
| 11353 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11354 match(Set dst (ConvI2F src)); | |
| 11355 | |
| 11356 format %{ "MOVD $dst,$src\n\t" | |
| 11357 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11358 ins_encode %{ | |
| 304 | 11359 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11360 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11361 %} | |
| 11362 ins_pipe(pipe_slow); // XXX | |
| 11363 %} | |
| 11364 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11365 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11366 match(Set dst (ConvI2L src)); |
| 11367 effect(KILL cr); | |
| 624 | 11368 ins_cost(375); |
| 0 | 11369 format %{ "MOV $dst.lo,$src\n\t" |
| 11370 "MOV $dst.hi,$src\n\t" | |
| 11371 "SAR $dst.hi,31" %} | |
| 11372 ins_encode(convert_int_long(dst,src)); | |
| 11373 ins_pipe( ialu_reg_reg_long ); | |
| 11374 %} | |
| 11375 | |
| 11376 // Zero-extend convert int to long | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11377 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11378 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11379 effect( KILL flags ); | |
| 624 | 11380 ins_cost(250); |
| 0 | 11381 format %{ "MOV $dst.lo,$src\n\t" |
| 11382 "XOR $dst.hi,$dst.hi" %} | |
| 11383 opcode(0x33); // XOR | |
| 11384 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11385 ins_pipe( ialu_reg_reg_long ); | |
| 11386 %} | |
| 11387 | |
| 11388 // Zero-extend long | |
| 11389 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11390 match(Set dst (AndL src mask) ); | |
| 11391 effect( KILL flags ); | |
| 624 | 11392 ins_cost(250); |
| 0 | 11393 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11394 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11395 opcode(0x33); // XOR | |
| 11396 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11397 ins_pipe( ialu_reg_reg_long ); | |
| 11398 %} | |
| 11399 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11400 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11401 predicate (UseSSE<=1); |
| 11402 match(Set dst (ConvL2D src)); | |
| 11403 effect( KILL cr ); | |
| 11404 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11405 "PUSH $src.lo\n\t" | |
| 11406 "FILD ST,[ESP + #0]\n\t" | |
| 11407 "ADD ESP,8\n\t" | |
| 11408 "FSTP_D $dst\t# D-round" %} | |
| 11409 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11410 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11411 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11412 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11413 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11414 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11415 predicate (UseSSE>=2); |
| 11416 match(Set dst (ConvL2D src)); | |
| 11417 effect( KILL cr ); | |
| 11418 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11419 "PUSH $src.lo\n\t" | |
| 11420 "FILD_D [ESP]\n\t" | |
| 11421 "FSTP_D [ESP]\n\t" | |
| 11422 "MOVSD $dst,[ESP]\n\t" | |
| 11423 "ADD ESP,8" %} | |
| 11424 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11425 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11426 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11427 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11428 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11429 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11430 predicate (UseSSE>=1); |
| 11431 match(Set dst (ConvL2F src)); | |
| 11432 effect( KILL cr ); | |
| 11433 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11434 "PUSH $src.lo\n\t" | |
| 11435 "FILD_D [ESP]\n\t" | |
| 11436 "FSTP_S [ESP]\n\t" | |
| 11437 "MOVSS $dst,[ESP]\n\t" | |
| 11438 "ADD ESP,8" %} | |
| 11439 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11440 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11441 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11442 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11443 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11444 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11445 match(Set dst (ConvL2F src)); |
| 11446 effect( KILL cr ); | |
| 11447 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11448 "PUSH $src.lo\n\t" | |
| 11449 "FILD ST,[ESP + #0]\n\t" | |
| 11450 "ADD ESP,8\n\t" | |
| 11451 "FSTP_S $dst\t# F-round" %} | |
| 11452 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11453 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11454 ins_pipe( pipe_slow ); |
| 11455 %} | |
| 11456 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11457 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11458 match(Set dst (ConvL2I src)); |
| 11459 effect( DEF dst, USE src ); | |
| 11460 format %{ "MOV $dst,$src.lo" %} | |
| 11461 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11462 ins_pipe( ialu_reg_reg ); | |
| 11463 %} | |
| 11464 | |
| 11465 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11466 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11467 match(Set dst (MoveF2I src)); |
| 11468 effect( DEF dst, USE src ); | |
| 11469 ins_cost(100); | |
| 11470 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11471 ins_encode %{ |
| 11472 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11473 %} | |
| 0 | 11474 ins_pipe( ialu_reg_mem ); |
| 11475 %} | |
| 11476 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11477 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11478 predicate(UseSSE==0); |
| 11479 match(Set dst (MoveF2I src)); | |
| 11480 effect( DEF dst, USE src ); | |
| 11481 | |
| 11482 ins_cost(125); | |
| 11483 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11484 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11485 ins_pipe( fpu_mem_reg ); |
| 11486 %} | |
| 11487 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11488 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11489 predicate(UseSSE>=1); |
| 11490 match(Set dst (MoveF2I src)); | |
| 11491 effect( DEF dst, USE src ); | |
| 11492 | |
| 11493 ins_cost(95); | |
| 11494 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11495 ins_encode %{ |
| 11496 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11497 %} | |
| 0 | 11498 ins_pipe( pipe_slow ); |
| 11499 %} | |
| 11500 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11501 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11502 predicate(UseSSE>=2); |
| 11503 match(Set dst (MoveF2I src)); | |
| 11504 effect( DEF dst, USE src ); | |
| 11505 ins_cost(85); | |
| 11506 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11507 ins_encode %{ |
| 11508 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11509 %} | |
| 0 | 11510 ins_pipe( pipe_slow ); |
| 11511 %} | |
| 11512 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11513 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11514 match(Set dst (MoveI2F src)); |
| 11515 effect( DEF dst, USE src ); | |
| 11516 | |
| 11517 ins_cost(100); | |
| 11518 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11519 ins_encode %{ |
| 11520 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11521 %} | |
| 0 | 11522 ins_pipe( ialu_mem_reg ); |
| 11523 %} | |
| 11524 | |
| 11525 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11526 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11527 predicate(UseSSE==0); |
| 11528 match(Set dst (MoveI2F src)); | |
| 11529 effect(DEF dst, USE src); | |
| 11530 | |
| 11531 ins_cost(125); | |
| 11532 format %{ "FLD_S $src\n\t" | |
| 11533 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11534 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11535 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11536 Pop_Reg_FPR(dst) ); |
| 0 | 11537 ins_pipe( fpu_reg_mem ); |
| 11538 %} | |
| 11539 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11540 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11541 predicate(UseSSE>=1); |
| 11542 match(Set dst (MoveI2F src)); | |
| 11543 effect( DEF dst, USE src ); | |
| 11544 | |
| 11545 ins_cost(95); | |
| 11546 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11547 ins_encode %{ |
| 11548 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11549 %} | |
| 0 | 11550 ins_pipe( pipe_slow ); |
| 11551 %} | |
| 11552 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11553 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11554 predicate(UseSSE>=2); |
| 11555 match(Set dst (MoveI2F src)); | |
| 11556 effect( DEF dst, USE src ); | |
| 11557 | |
| 11558 ins_cost(85); | |
| 11559 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11560 ins_encode %{ |
| 11561 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11562 %} | |
| 0 | 11563 ins_pipe( pipe_slow ); |
| 11564 %} | |
| 11565 | |
| 11566 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11567 match(Set dst (MoveD2L src)); | |
| 11568 effect(DEF dst, USE src); | |
| 11569 | |
| 11570 ins_cost(250); | |
| 11571 format %{ "MOV $dst.lo,$src\n\t" | |
| 11572 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11573 opcode(0x8B, 0x8B); | |
| 11574 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11575 ins_pipe( ialu_mem_long_reg ); | |
| 11576 %} | |
| 11577 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11578 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11579 predicate(UseSSE<=1); |
| 11580 match(Set dst (MoveD2L src)); | |
| 11581 effect(DEF dst, USE src); | |
| 11582 | |
| 11583 ins_cost(125); | |
| 11584 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11585 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11586 ins_pipe( fpu_mem_reg ); |
| 11587 %} | |
| 11588 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11589 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11590 predicate(UseSSE>=2); |
| 11591 match(Set dst (MoveD2L src)); | |
| 11592 effect(DEF dst, USE src); | |
| 11593 ins_cost(95); | |
| 11594 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11595 ins_encode %{ |
| 11596 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11597 %} | |
| 0 | 11598 ins_pipe( pipe_slow ); |
| 11599 %} | |
| 11600 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11601 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11602 predicate(UseSSE>=2); |
| 11603 match(Set dst (MoveD2L src)); | |
| 11604 effect(DEF dst, USE src, TEMP tmp); | |
| 11605 ins_cost(85); | |
| 11606 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11607 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11608 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11609 ins_encode %{ |
| 11610 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11611 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11612 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11613 %} | |
| 0 | 11614 ins_pipe( pipe_slow ); |
| 11615 %} | |
| 11616 | |
| 11617 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11618 match(Set dst (MoveL2D src)); | |
| 11619 effect(DEF dst, USE src); | |
| 11620 | |
| 11621 ins_cost(200); | |
| 11622 format %{ "MOV $dst,$src.lo\n\t" | |
| 11623 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11624 opcode(0x89, 0x89); | |
| 11625 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11626 ins_pipe( ialu_mem_long_reg ); | |
| 11627 %} | |
| 11628 | |
| 11629 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11630 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11631 predicate(UseSSE<=1); |
| 11632 match(Set dst (MoveL2D src)); | |
| 11633 effect(DEF dst, USE src); | |
| 11634 ins_cost(125); | |
| 11635 | |
| 11636 format %{ "FLD_D $src\n\t" | |
| 11637 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11638 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11639 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11640 Pop_Reg_DPR(dst) ); |
| 0 | 11641 ins_pipe( fpu_reg_mem ); |
| 11642 %} | |
| 11643 | |
| 11644 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11645 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11646 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11647 match(Set dst (MoveL2D src)); | |
| 11648 effect(DEF dst, USE src); | |
| 11649 | |
| 11650 ins_cost(95); | |
| 11651 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11652 ins_encode %{ |
| 11653 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11654 %} | |
| 0 | 11655 ins_pipe( pipe_slow ); |
| 11656 %} | |
| 11657 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11658 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11659 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11660 match(Set dst (MoveL2D src)); | |
| 11661 effect(DEF dst, USE src); | |
| 11662 | |
| 11663 ins_cost(95); | |
| 11664 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11665 ins_encode %{ |
| 11666 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11667 %} | |
| 0 | 11668 ins_pipe( pipe_slow ); |
| 11669 %} | |
| 11670 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11671 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11672 predicate(UseSSE>=2); |
| 11673 match(Set dst (MoveL2D src)); | |
| 11674 effect(TEMP dst, USE src, TEMP tmp); | |
| 11675 ins_cost(85); | |
| 11676 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11677 "MOVD $tmp,$src.hi\n\t" | |
| 11678 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11679 ins_encode %{ |
| 11680 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11681 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11682 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11683 %} | |
| 0 | 11684 ins_pipe( pipe_slow ); |
| 11685 %} | |
| 11686 | |
| 11687 | |
| 11688 // ======================================================================= | |
| 11689 // fast clearing of an array | |
| 11690 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11691 predicate(!UseFastStosb); |
| 0 | 11692 match(Set dummy (ClearArray cnt base)); |
| 11693 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11694 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11695 "SHL ECX,1\t# Convert doublewords to words\n\t" |
| 0 | 11696 "REP STOS\t# store EAX into [EDI++] while ECX--" %} |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11697 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11698 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11699 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11700 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11701 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11702 |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11703 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11704 predicate(UseFastStosb); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11705 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11706 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11707 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11708 "SHL ECX,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11709 "REP STOSB\t# store EAX into [EDI++] while ECX--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11710 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11711 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11712 %} |
| 0 | 11713 ins_pipe( pipe_slow ); |
| 11714 %} | |
| 11715 | |
| 2262 | 11716 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11717 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11718 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11719 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11720 | |
| 11721 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11722 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11723 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11724 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11725 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11726 %} |
| 681 | 11727 ins_pipe( pipe_slow ); |
| 11728 %} | |
| 11729 | |
| 11730 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11731 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11732 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11733 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11734 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11735 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11736 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11737 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11738 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11739 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11740 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11741 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11742 ins_pipe( pipe_slow ); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11743 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11744 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11745 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11746 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11747 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11748 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11749 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11750 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11751 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11752 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11753 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11754 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11755 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11756 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11757 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11758 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11759 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11760 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11761 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11762 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11763 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11764 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11765 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11766 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11767 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11768 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11769 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11770 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11771 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11772 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11773 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11774 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11775 predicate(UseSSE42Intrinsics); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11776 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11777 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11778 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11779 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11780 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11781 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11782 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11783 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11784 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11785 %} |
| 0 | 11786 ins_pipe( pipe_slow ); |
| 11787 %} | |
| 11788 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11789 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11790 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11791 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11792 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11793 match(Set result (AryEq ary1 ary2)); |
| 681 | 11794 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11795 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11796 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11797 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11798 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11799 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11800 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11801 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11802 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11803 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11804 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11805 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11806 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11807 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11808 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11809 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11810 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11811 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11812 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11813 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11814 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11815 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11816 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11817 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11818 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11819 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11820 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11821 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11822 |
| 0 | 11823 //----------Control Flow Instructions------------------------------------------ |
| 11824 // Signed compare Instructions | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11825 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11826 match(Set cr (CmpI op1 op2)); |
| 11827 effect( DEF cr, USE op1, USE op2 ); | |
| 11828 format %{ "CMP $op1,$op2" %} | |
| 11829 opcode(0x3B); /* Opcode 3B /r */ | |
| 11830 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11831 ins_pipe( ialu_cr_reg_reg ); | |
| 11832 %} | |
| 11833 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11834 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11835 match(Set cr (CmpI op1 op2)); |
| 11836 effect( DEF cr, USE op1 ); | |
| 11837 format %{ "CMP $op1,$op2" %} | |
| 11838 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11839 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11840 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11841 ins_pipe( ialu_cr_reg_imm ); | |
| 11842 %} | |
| 11843 | |
| 11844 // Cisc-spilled version of cmpI_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11845 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11846 match(Set cr (CmpI op1 (LoadI op2))); |
| 11847 | |
| 11848 format %{ "CMP $op1,$op2" %} | |
| 11849 ins_cost(500); | |
| 11850 opcode(0x3B); /* Opcode 3B /r */ | |
| 11851 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11852 ins_pipe( ialu_cr_reg_mem ); | |
| 11853 %} | |
| 11854 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11855 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11856 match(Set cr (CmpI src zero)); |
| 11857 effect( DEF cr, USE src ); | |
| 11858 | |
| 11859 format %{ "TEST $src,$src" %} | |
| 11860 opcode(0x85); | |
| 11861 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11862 ins_pipe( ialu_cr_reg_imm ); | |
| 11863 %} | |
| 11864 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11865 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11866 match(Set cr (CmpI (AndI src con) zero)); |
| 11867 | |
| 11868 format %{ "TEST $src,$con" %} | |
| 11869 opcode(0xF7,0x00); | |
| 11870 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11871 ins_pipe( ialu_cr_reg_imm ); | |
| 11872 %} | |
| 11873 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11874 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11875 match(Set cr (CmpI (AndI src mem) zero)); |
| 11876 | |
| 11877 format %{ "TEST $src,$mem" %} | |
| 11878 opcode(0x85); | |
| 11879 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11880 ins_pipe( ialu_cr_reg_mem ); | |
| 11881 %} | |
| 11882 | |
| 11883 // Unsigned compare Instructions; really, same as signed except they | |
| 11884 // produce an eFlagsRegU instead of eFlagsReg. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11885 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11886 match(Set cr (CmpU op1 op2)); |
| 11887 | |
| 11888 format %{ "CMPu $op1,$op2" %} | |
| 11889 opcode(0x3B); /* Opcode 3B /r */ | |
| 11890 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11891 ins_pipe( ialu_cr_reg_reg ); | |
| 11892 %} | |
| 11893 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11894 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11895 match(Set cr (CmpU op1 op2)); |
| 11896 | |
| 11897 format %{ "CMPu $op1,$op2" %} | |
| 11898 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11899 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11900 ins_pipe( ialu_cr_reg_imm ); | |
| 11901 %} | |
| 11902 | |
| 11903 // // Cisc-spilled version of cmpU_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11904 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11905 match(Set cr (CmpU op1 (LoadI op2))); |
| 11906 | |
| 11907 format %{ "CMPu $op1,$op2" %} | |
| 11908 ins_cost(500); | |
| 11909 opcode(0x3B); /* Opcode 3B /r */ | |
| 11910 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11911 ins_pipe( ialu_cr_reg_mem ); | |
| 11912 %} | |
| 11913 | |
| 11914 // // Cisc-spilled version of cmpU_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11915 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11916 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11917 // | |
| 11918 // format %{ "CMPu $op1,$op2" %} | |
| 11919 // ins_cost(500); | |
| 11920 // opcode(0x39); /* Opcode 39 /r */ | |
| 11921 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11922 //%} | |
| 11923 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11924 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11925 match(Set cr (CmpU src zero)); |
| 11926 | |
| 11927 format %{ "TESTu $src,$src" %} | |
| 11928 opcode(0x85); | |
| 11929 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11930 ins_pipe( ialu_cr_reg_imm ); | |
| 11931 %} | |
| 11932 | |
| 11933 // Unsigned pointer compare Instructions | |
| 11934 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11935 match(Set cr (CmpP op1 op2)); | |
| 11936 | |
| 11937 format %{ "CMPu $op1,$op2" %} | |
| 11938 opcode(0x3B); /* Opcode 3B /r */ | |
| 11939 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11940 ins_pipe( ialu_cr_reg_reg ); | |
| 11941 %} | |
| 11942 | |
| 11943 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11944 match(Set cr (CmpP op1 op2)); | |
| 11945 | |
| 11946 format %{ "CMPu $op1,$op2" %} | |
| 11947 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11948 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11949 ins_pipe( ialu_cr_reg_imm ); | |
| 11950 %} | |
| 11951 | |
| 11952 // // Cisc-spilled version of cmpP_eReg | |
| 11953 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11954 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11955 | |
| 11956 format %{ "CMPu $op1,$op2" %} | |
| 11957 ins_cost(500); | |
| 11958 opcode(0x3B); /* Opcode 3B /r */ | |
| 11959 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11960 ins_pipe( ialu_cr_reg_mem ); | |
| 11961 %} | |
| 11962 | |
| 11963 // // Cisc-spilled version of cmpP_eReg | |
| 11964 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11965 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11966 // | |
| 11967 // format %{ "CMPu $op1,$op2" %} | |
| 11968 // ins_cost(500); | |
| 11969 // opcode(0x39); /* Opcode 39 /r */ | |
| 11970 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11971 //%} | |
| 11972 | |
| 11973 // Compare raw pointer (used in out-of-heap check). | |
| 11974 // Only works because non-oop pointers must be raw pointers | |
| 11975 // and raw pointers have no anti-dependencies. | |
| 11976 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
11977 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11978 match(Set cr (CmpP op1 (LoadP op2))); |
| 11979 | |
| 11980 format %{ "CMPu $op1,$op2" %} | |
| 11981 opcode(0x3B); /* Opcode 3B /r */ | |
| 11982 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11983 ins_pipe( ialu_cr_reg_mem ); | |
| 11984 %} | |
| 11985 | |
| 11986 // | |
| 11987 // This will generate a signed flags result. This should be ok | |
| 11988 // since any compare to a zero should be eq/neq. | |
| 11989 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11990 match(Set cr (CmpP src zero)); | |
| 11991 | |
| 11992 format %{ "TEST $src,$src" %} | |
| 11993 opcode(0x85); | |
| 11994 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11995 ins_pipe( ialu_cr_reg_imm ); | |
| 11996 %} | |
| 11997 | |
| 11998 // Cisc-spilled version of testP_reg | |
| 11999 // This will generate a signed flags result. This should be ok | |
| 12000 // since any compare to a zero should be eq/neq. | |
| 12001 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 12002 match(Set cr (CmpP (LoadP op) zero)); | |
| 12003 | |
| 12004 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 12005 ins_cost(500); | |
| 12006 opcode(0xF7); /* Opcode F7 /0 */ | |
| 12007 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 12008 ins_pipe( ialu_cr_reg_imm ); | |
| 12009 %} | |
| 12010 | |
| 12011 // Yanked all unsigned pointer compare operations. | |
| 12012 // Pointer compares are done with CmpP which is already unsigned. | |
| 12013 | |
| 12014 //----------Max and Min-------------------------------------------------------- | |
| 12015 // Min Instructions | |
| 12016 //// | |
| 12017 // *** Min and Max using the conditional move are slower than the | |
| 12018 // *** branch version on a Pentium III. | |
| 12019 // // Conditional move for min | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12020 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 12021 // effect( USE_DEF op2, USE op1, USE cr ); |
| 12022 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 12023 // opcode(0x4C,0x0F); | |
| 12024 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12025 // ins_pipe( pipe_cmov_reg ); | |
| 12026 //%} | |
| 12027 // | |
| 12028 //// Min Register with Register (P6 version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12029 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 12030 // predicate(VM_Version::supports_cmov() ); |
| 12031 // match(Set op2 (MinI op1 op2)); | |
| 12032 // ins_cost(200); | |
| 12033 // expand %{ | |
| 12034 // eFlagsReg cr; | |
| 12035 // compI_eReg(cr,op1,op2); | |
| 12036 // cmovI_reg_lt(op2,op1,cr); | |
| 12037 // %} | |
| 12038 //%} | |
| 12039 | |
| 12040 // Min Register with Register (generic version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12041 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 12042 match(Set dst (MinI dst src)); |
| 12043 effect(KILL flags); | |
| 12044 ins_cost(300); | |
| 12045 | |
| 12046 format %{ "MIN $dst,$src" %} | |
| 12047 opcode(0xCC); | |
| 12048 ins_encode( min_enc(dst,src) ); | |
| 12049 ins_pipe( pipe_slow ); | |
| 12050 %} | |
| 12051 | |
| 12052 // Max Register with Register | |
| 12053 // *** Min and Max using the conditional move are slower than the | |
| 12054 // *** branch version on a Pentium III. | |
| 12055 // // Conditional move for max | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12056 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 12057 // effect( USE_DEF op2, USE op1, USE cr ); |
| 12058 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 12059 // opcode(0x4F,0x0F); | |
| 12060 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12061 // ins_pipe( pipe_cmov_reg ); | |
| 12062 //%} | |
| 12063 // | |
| 12064 // // Max Register with Register (P6 version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12065 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 12066 // predicate(VM_Version::supports_cmov() ); |
| 12067 // match(Set op2 (MaxI op1 op2)); | |
| 12068 // ins_cost(200); | |
| 12069 // expand %{ | |
| 12070 // eFlagsReg cr; | |
| 12071 // compI_eReg(cr,op1,op2); | |
| 12072 // cmovI_reg_gt(op2,op1,cr); | |
| 12073 // %} | |
| 12074 //%} | |
| 12075 | |
| 12076 // Max Register with Register (generic version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12077 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 12078 match(Set dst (MaxI dst src)); |
| 12079 effect(KILL flags); | |
| 12080 ins_cost(300); | |
| 12081 | |
| 12082 format %{ "MAX $dst,$src" %} | |
| 12083 opcode(0xCC); | |
| 12084 ins_encode( max_enc(dst,src) ); | |
| 12085 ins_pipe( pipe_slow ); | |
| 12086 %} | |
| 12087 | |
| 12088 // ============================================================================ | |
| 3345 | 12089 // Counted Loop limit node which represents exact final iterator value. |
| 12090 // Note: the resulting value should fit into integer range since | |
| 12091 // counted loops have limit check on overflow. | |
| 12092 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 12093 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 12094 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 12095 ins_cost(300); | |
| 12096 | |
| 12097 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 12098 ins_encode %{ | |
| 12099 int strd = (int)$stride$$constant; | |
| 12100 assert(strd != 1 && strd != -1, "sanity"); | |
| 12101 int m1 = (strd > 0) ? 1 : -1; | |
| 12102 // Convert limit to long (EAX:EDX) | |
| 12103 __ cdql(); | |
| 12104 // Convert init to long (init:tmp) | |
| 12105 __ movl($tmp$$Register, $init$$Register); | |
| 12106 __ sarl($tmp$$Register, 31); | |
| 12107 // $limit - $init | |
| 12108 __ subl($limit$$Register, $init$$Register); | |
| 12109 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 12110 // + ($stride - 1) | |
| 12111 if (strd > 0) { | |
| 12112 __ addl($limit$$Register, (strd - 1)); | |
| 12113 __ adcl($limit_hi$$Register, 0); | |
| 12114 __ movl($tmp$$Register, strd); | |
| 12115 } else { | |
| 12116 __ addl($limit$$Register, (strd + 1)); | |
| 12117 __ adcl($limit_hi$$Register, -1); | |
| 12118 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 12119 __ movl($tmp$$Register, -strd); | |
| 12120 } | |
| 12121 // signed devision: (EAX:EDX) / pos_stride | |
| 12122 __ idivl($tmp$$Register); | |
| 12123 if (strd < 0) { | |
| 12124 // restore sign | |
| 12125 __ negl($tmp$$Register); | |
| 12126 } | |
| 12127 // (EAX) * stride | |
| 12128 __ mull($tmp$$Register); | |
| 12129 // + init (ignore upper bits) | |
| 12130 __ addl($limit$$Register, $init$$Register); | |
| 12131 %} | |
| 12132 ins_pipe( pipe_slow ); | |
| 12133 %} | |
| 12134 | |
| 12135 // ============================================================================ | |
| 0 | 12136 // Branch Instructions |
| 12137 // Jump Table | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12138 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 12139 match(Jump switch_val); |
| 12140 ins_cost(350); | |
| 2008 | 12141 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 12142 ins_encode %{ | |
| 0 | 12143 // Jump to Address(table_base + switch_reg) |
| 12144 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 12145 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 12146 %} |
| 12147 ins_pipe(pipe_jmp); | |
| 12148 %} | |
| 12149 | |
| 12150 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12151 instruct jmpDir(label labl) %{ | |
| 12152 match(Goto); | |
| 12153 effect(USE labl); | |
| 12154 | |
| 12155 ins_cost(300); | |
| 12156 format %{ "JMP $labl" %} | |
| 12157 size(5); | |
| 3851 | 12158 ins_encode %{ |
| 12159 Label* L = $labl$$label; | |
| 12160 __ jmp(*L, false); // Always long jump | |
| 12161 %} | |
| 0 | 12162 ins_pipe( pipe_jmp ); |
| 12163 %} | |
| 12164 | |
| 12165 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12166 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12167 match(If cop cr); | |
| 12168 effect(USE labl); | |
| 12169 | |
| 12170 ins_cost(300); | |
| 12171 format %{ "J$cop $labl" %} | |
| 12172 size(6); | |
| 3851 | 12173 ins_encode %{ |
| 12174 Label* L = $labl$$label; | |
| 12175 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12176 %} | |
| 0 | 12177 ins_pipe( pipe_jcc ); |
| 12178 %} | |
| 12179 | |
| 12180 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12181 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12182 match(CountedLoopEnd cop cr); | |
| 12183 effect(USE labl); | |
| 12184 | |
| 12185 ins_cost(300); | |
| 12186 format %{ "J$cop $labl\t# Loop end" %} | |
| 12187 size(6); | |
| 3851 | 12188 ins_encode %{ |
| 12189 Label* L = $labl$$label; | |
| 12190 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12191 %} | |
| 0 | 12192 ins_pipe( pipe_jcc ); |
| 12193 %} | |
| 12194 | |
| 12195 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12196 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12197 match(CountedLoopEnd cop cmp); | |
| 12198 effect(USE labl); | |
| 12199 | |
| 12200 ins_cost(300); | |
| 12201 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12202 size(6); | |
| 3851 | 12203 ins_encode %{ |
| 12204 Label* L = $labl$$label; | |
| 12205 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12206 %} | |
| 0 | 12207 ins_pipe( pipe_jcc ); |
| 12208 %} | |
| 12209 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12210 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12211 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12212 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12213 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12214 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12215 format %{ "J$cop,u $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12216 size(6); |
| 3851 | 12217 ins_encode %{ |
| 12218 Label* L = $labl$$label; | |
| 12219 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12220 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12221 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12222 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12223 |
| 0 | 12224 // Jump Direct Conditional - using unsigned comparison |
| 12225 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12226 match(If cop cmp); | |
| 12227 effect(USE labl); | |
| 12228 | |
| 12229 ins_cost(300); | |
| 12230 format %{ "J$cop,u $labl" %} | |
| 12231 size(6); | |
| 3851 | 12232 ins_encode %{ |
| 12233 Label* L = $labl$$label; | |
| 12234 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12235 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12236 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12237 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12238 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12239 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12240 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12241 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12242 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12243 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12244 format %{ "J$cop,u $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12245 size(6); |
| 3851 | 12246 ins_encode %{ |
| 12247 Label* L = $labl$$label; | |
| 12248 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12249 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12250 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12251 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12252 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12253 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12254 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12255 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12256 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12257 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12258 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12259 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12260 $$emit$$"JP,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12261 $$emit$$"J$cop,u $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12262 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12263 $$emit$$"JP,u done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12264 $$emit$$"J$cop,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12265 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12266 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12267 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12268 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12269 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12270 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12271 __ jcc(Assembler::parity, *l, false); |
| 12272 __ jcc(Assembler::notEqual, *l, false); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12273 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12274 Label done; |
| 12275 __ jccb(Assembler::parity, done); | |
| 12276 __ jcc(Assembler::equal, *l, false); | |
| 12277 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12278 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12279 ShouldNotReachHere(); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12280 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12281 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12282 ins_pipe(pipe_jcc); |
| 0 | 12283 %} |
| 12284 | |
| 12285 // ============================================================================ | |
| 12286 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12287 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12288 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12289 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12290 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12291 match(Set result (PartialSubtypeCheck sub super)); | |
| 12292 effect( KILL rcx, KILL cr ); | |
| 12293 | |
| 12294 ins_cost(1100); // slightly larger than the next version | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12295 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12296 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12297 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12298 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12299 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12300 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12301 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12302 "miss:\t" %} | |
| 12303 | |
| 12304 opcode(0x1); // Force a XOR of EDI | |
| 12305 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12306 ins_pipe( pipe_slow ); | |
| 12307 %} | |
| 12308 | |
| 12309 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12310 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12311 effect( KILL rcx, KILL result ); | |
| 12312 | |
| 12313 ins_cost(1000); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12314 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12315 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12316 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12317 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12318 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12319 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12320 "miss:\t" %} | |
| 12321 | |
| 12322 opcode(0x0); // No need to XOR EDI | |
| 12323 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12324 ins_pipe( pipe_slow ); | |
| 12325 %} | |
| 12326 | |
| 12327 // ============================================================================ | |
| 12328 // Branch Instructions -- short offset versions | |
| 12329 // | |
| 12330 // These instructions are used to replace jumps of a long offset (the default | |
| 12331 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12332 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12333 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12334 // method in the MachNode which can be used to do in-place replacement of the | |
| 12335 // long variant with the shorter variant. The compiler will determine if a | |
| 12336 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12337 // specific code section of the file. | |
| 12338 | |
| 12339 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12340 instruct jmpDir_short(label labl) %{ | |
| 12341 match(Goto); | |
| 12342 effect(USE labl); | |
| 12343 | |
| 12344 ins_cost(300); | |
| 12345 format %{ "JMP,s $labl" %} | |
| 12346 size(2); | |
| 3851 | 12347 ins_encode %{ |
| 12348 Label* L = $labl$$label; | |
| 12349 __ jmpb(*L); | |
| 12350 %} | |
| 0 | 12351 ins_pipe( pipe_jmp ); |
| 12352 ins_short_branch(1); | |
| 12353 %} | |
| 12354 | |
| 12355 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12356 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12357 match(If cop cr); | |
| 12358 effect(USE labl); | |
| 12359 | |
| 12360 ins_cost(300); | |
| 12361 format %{ "J$cop,s $labl" %} | |
| 12362 size(2); | |
| 3851 | 12363 ins_encode %{ |
| 12364 Label* L = $labl$$label; | |
| 12365 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12366 %} | |
| 0 | 12367 ins_pipe( pipe_jcc ); |
| 12368 ins_short_branch(1); | |
| 12369 %} | |
| 12370 | |
| 12371 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12372 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12373 match(CountedLoopEnd cop cr); | |
| 12374 effect(USE labl); | |
| 12375 | |
| 12376 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12377 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12378 size(2); |
| 3851 | 12379 ins_encode %{ |
| 12380 Label* L = $labl$$label; | |
| 12381 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12382 %} | |
| 0 | 12383 ins_pipe( pipe_jcc ); |
| 12384 ins_short_branch(1); | |
| 12385 %} | |
| 12386 | |
| 12387 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12388 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12389 match(CountedLoopEnd cop cmp); | |
| 12390 effect(USE labl); | |
| 12391 | |
| 12392 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12393 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12394 size(2); |
| 3851 | 12395 ins_encode %{ |
| 12396 Label* L = $labl$$label; | |
| 12397 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12398 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12399 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12400 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12401 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12402 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12403 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12404 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12405 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12406 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12407 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12408 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12409 size(2); |
| 3851 | 12410 ins_encode %{ |
| 12411 Label* L = $labl$$label; | |
| 12412 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12413 %} | |
| 0 | 12414 ins_pipe( pipe_jcc ); |
| 12415 ins_short_branch(1); | |
| 12416 %} | |
| 12417 | |
| 12418 // Jump Direct Conditional - using unsigned comparison | |
| 12419 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12420 match(If cop cmp); | |
| 12421 effect(USE labl); | |
| 12422 | |
| 12423 ins_cost(300); | |
| 12424 format %{ "J$cop,us $labl" %} | |
| 12425 size(2); | |
| 3851 | 12426 ins_encode %{ |
| 12427 Label* L = $labl$$label; | |
| 12428 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12429 %} | |
| 0 | 12430 ins_pipe( pipe_jcc ); |
| 12431 ins_short_branch(1); | |
| 12432 %} | |
| 12433 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12434 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12435 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12436 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12437 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12438 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12439 format %{ "J$cop,us $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12440 size(2); |
| 3851 | 12441 ins_encode %{ |
| 12442 Label* L = $labl$$label; | |
| 12443 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12444 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12445 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12446 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12447 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12448 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12449 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12450 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12451 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12452 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12453 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12454 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12455 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12456 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12457 $$emit$$"J$cop,u,s $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12458 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12459 $$emit$$"JP,u,s done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12460 $$emit$$"J$cop,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12461 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12462 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12463 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12464 size(4); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12465 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12466 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12467 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12468 __ jccb(Assembler::parity, *l); |
| 12469 __ jccb(Assembler::notEqual, *l); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12470 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12471 Label done; |
| 12472 __ jccb(Assembler::parity, done); | |
| 12473 __ jccb(Assembler::equal, *l); | |
| 12474 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12475 } else { |
| 3851 | 12476 ShouldNotReachHere(); |
| 12477 } | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12478 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12479 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12480 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12481 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12482 |
| 0 | 12483 // ============================================================================ |
| 12484 // Long Compare | |
| 12485 // | |
| 12486 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12487 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12488 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12489 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12490 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12491 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12492 // NE test is negated from that. | |
| 12493 | |
| 12494 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12495 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12496 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12497 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12498 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12499 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12500 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12501 // both forms beat the trinary form of long-compare and both are very useful | |
| 12502 // on Intel which has so few registers. | |
| 12503 | |
| 12504 // Manifest a CmpL result in an integer register. Very painful. | |
| 12505 // This is the test to avoid. | |
| 12506 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12507 match(Set dst (CmpL3 src1 src2)); | |
| 12508 effect( KILL flags ); | |
| 12509 ins_cost(1000); | |
| 12510 format %{ "XOR $dst,$dst\n\t" | |
| 12511 "CMP $src1.hi,$src2.hi\n\t" | |
| 12512 "JLT,s m_one\n\t" | |
| 12513 "JGT,s p_one\n\t" | |
| 12514 "CMP $src1.lo,$src2.lo\n\t" | |
| 12515 "JB,s m_one\n\t" | |
| 12516 "JEQ,s done\n" | |
| 12517 "p_one:\tINC $dst\n\t" | |
| 12518 "JMP,s done\n" | |
| 12519 "m_one:\tDEC $dst\n" | |
| 12520 "done:" %} | |
| 12521 ins_encode %{ | |
| 12522 Label p_one, m_one, done; | |
| 304 | 12523 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12524 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12525 __ jccb(Assembler::less, m_one); | |
| 12526 __ jccb(Assembler::greater, p_one); | |
| 12527 __ cmpl($src1$$Register, $src2$$Register); | |
| 12528 __ jccb(Assembler::below, m_one); | |
| 12529 __ jccb(Assembler::equal, done); | |
| 12530 __ bind(p_one); | |
| 304 | 12531 __ incrementl($dst$$Register); |
| 0 | 12532 __ jmpb(done); |
| 12533 __ bind(m_one); | |
| 304 | 12534 __ decrementl($dst$$Register); |
| 0 | 12535 __ bind(done); |
| 12536 %} | |
| 12537 ins_pipe( pipe_slow ); | |
| 12538 %} | |
| 12539 | |
| 12540 //====== | |
| 12541 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12542 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12543 // NOT GOOD FOR EQ/NE tests. | |
| 12544 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12545 match( Set flags (CmpL src zero )); | |
| 12546 ins_cost(100); | |
| 12547 format %{ "TEST $src.hi,$src.hi" %} | |
| 12548 opcode(0x85); | |
| 12549 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12550 ins_pipe( ialu_cr_reg_reg ); | |
| 12551 %} | |
| 12552 | |
| 12553 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12554 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12555 // NOT GOOD FOR EQ/NE tests. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12556 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12557 match( Set flags (CmpL src1 src2 )); |
| 12558 effect( TEMP tmp ); | |
| 12559 ins_cost(300); | |
| 12560 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12561 "MOV $tmp,$src1.hi\n\t" | |
| 12562 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12563 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12564 ins_pipe( ialu_cr_reg_reg ); | |
| 12565 %} | |
| 12566 | |
| 12567 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12568 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12569 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12570 match(If cmp flags); | |
| 12571 effect(USE labl); | |
| 12572 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12573 expand %{ | |
| 12574 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12575 %} | |
| 12576 %} | |
| 12577 | |
| 12578 // Compare 2 longs and CMOVE longs. | |
| 12579 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12580 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12581 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12582 ins_cost(400); | |
| 12583 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12584 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12585 opcode(0x0F,0x40); | |
| 12586 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12587 ins_pipe( pipe_cmov_reg_long ); | |
| 12588 %} | |
| 12589 | |
| 12590 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12591 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12592 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12593 ins_cost(500); | |
| 12594 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12595 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12596 opcode(0x0F,0x40); | |
| 12597 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12598 ins_pipe( pipe_cmov_reg_long ); | |
| 12599 %} | |
| 12600 | |
| 12601 // Compare 2 longs and CMOVE ints. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12602 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12603 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12604 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12605 ins_cost(200); | |
| 12606 format %{ "CMOV$cmp $dst,$src" %} | |
| 12607 opcode(0x0F,0x40); | |
| 12608 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12609 ins_pipe( pipe_cmov_reg ); | |
| 12610 %} | |
| 12611 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12612 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12613 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12614 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12615 ins_cost(250); | |
| 12616 format %{ "CMOV$cmp $dst,$src" %} | |
| 12617 opcode(0x0F,0x40); | |
| 12618 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12619 ins_pipe( pipe_cmov_mem ); | |
| 12620 %} | |
| 12621 | |
| 12622 // Compare 2 longs and CMOVE ints. | |
| 12623 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12624 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12625 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12626 ins_cost(200); | |
| 12627 format %{ "CMOV$cmp $dst,$src" %} | |
| 12628 opcode(0x0F,0x40); | |
| 12629 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12630 ins_pipe( pipe_cmov_reg ); | |
| 12631 %} | |
| 12632 | |
| 12633 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12634 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12635 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12636 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12637 ins_cost(200); | |
| 12638 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12639 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12640 %} |
| 12641 %} | |
| 12642 | |
| 12643 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12644 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12645 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12646 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12647 ins_cost(200); | |
| 12648 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12649 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12650 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12651 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12652 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12653 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12654 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12655 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12656 ins_cost(200); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12657 expand %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12658 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12659 %} |
| 12660 %} | |
| 12661 | |
| 12662 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12663 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12664 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12665 ins_cost(200); | |
| 12666 expand %{ | |
| 12667 fcmovF_regS(cmp,flags,dst,src); | |
| 12668 %} | |
| 12669 %} | |
| 12670 | |
| 12671 //====== | |
| 12672 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12673 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12674 match( Set flags (CmpL src zero )); |
| 12675 effect(TEMP tmp); | |
| 12676 ins_cost(200); | |
| 12677 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12678 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12679 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12680 ins_pipe( ialu_reg_reg_long ); | |
| 12681 %} | |
| 12682 | |
| 12683 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12684 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12685 match( Set flags (CmpL src1 src2 )); | |
| 12686 ins_cost(200+300); | |
| 12687 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12688 "JNE,s skip\n\t" | |
| 12689 "CMP $src1.hi,$src2.hi\n\t" | |
| 12690 "skip:\t" %} | |
| 12691 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12692 ins_pipe( ialu_cr_reg_reg ); | |
| 12693 %} | |
| 12694 | |
| 12695 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12696 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12697 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12698 match(If cmp flags); | |
| 12699 effect(USE labl); | |
| 12700 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12701 expand %{ | |
| 12702 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12703 %} | |
| 12704 %} | |
| 12705 | |
| 12706 // Compare 2 longs and CMOVE longs. | |
| 12707 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12708 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12709 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12710 ins_cost(400); | |
| 12711 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12712 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12713 opcode(0x0F,0x40); | |
| 12714 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12715 ins_pipe( pipe_cmov_reg_long ); | |
| 12716 %} | |
| 12717 | |
| 12718 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12719 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12720 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12721 ins_cost(500); | |
| 12722 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12723 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12724 opcode(0x0F,0x40); | |
| 12725 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12726 ins_pipe( pipe_cmov_reg_long ); | |
| 12727 %} | |
| 12728 | |
| 12729 // Compare 2 longs and CMOVE ints. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12730 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12731 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12732 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12733 ins_cost(200); | |
| 12734 format %{ "CMOV$cmp $dst,$src" %} | |
| 12735 opcode(0x0F,0x40); | |
| 12736 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12737 ins_pipe( pipe_cmov_reg ); | |
| 12738 %} | |
| 12739 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12740 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12741 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12742 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12743 ins_cost(250); | |
| 12744 format %{ "CMOV$cmp $dst,$src" %} | |
| 12745 opcode(0x0F,0x40); | |
| 12746 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12747 ins_pipe( pipe_cmov_mem ); | |
| 12748 %} | |
| 12749 | |
| 12750 // Compare 2 longs and CMOVE ints. | |
| 12751 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12752 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12753 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12754 ins_cost(200); | |
| 12755 format %{ "CMOV$cmp $dst,$src" %} | |
| 12756 opcode(0x0F,0x40); | |
| 12757 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12758 ins_pipe( pipe_cmov_reg ); | |
| 12759 %} | |
| 12760 | |
| 12761 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12762 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12763 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12764 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12765 ins_cost(200); | |
| 12766 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12767 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12768 %} |
| 12769 %} | |
| 12770 | |
| 12771 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12772 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12773 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12774 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12775 ins_cost(200); | |
| 12776 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12777 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12778 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12779 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12780 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12781 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12782 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12783 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12784 ins_cost(200); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12785 expand %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12786 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12787 %} |
| 12788 %} | |
| 12789 | |
| 12790 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12791 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12792 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12793 ins_cost(200); | |
| 12794 expand %{ | |
| 12795 fcmovF_regS(cmp,flags,dst,src); | |
| 12796 %} | |
| 12797 %} | |
| 12798 | |
| 12799 //====== | |
| 12800 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12801 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12802 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12803 match( Set flags (CmpL src zero )); |
| 12804 effect( TEMP tmp ); | |
| 12805 ins_cost(300); | |
| 12806 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12807 "CMP $tmp,$src.lo\n\t" | |
| 12808 "SBB $tmp,$src.hi\n\t" %} | |
| 12809 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12810 ins_pipe( ialu_reg_reg_long ); | |
| 12811 %} | |
| 12812 | |
| 12813 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12814 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12815 // requires a commuted test to get the same result. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12816 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12817 match( Set flags (CmpL src1 src2 )); |
| 12818 effect( TEMP tmp ); | |
| 12819 ins_cost(300); | |
| 12820 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12821 "MOV $tmp,$src2.hi\n\t" | |
| 12822 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12823 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12824 ins_pipe( ialu_cr_reg_reg ); | |
| 12825 %} | |
| 12826 | |
| 12827 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12828 // Just a wrapper for a normal branch, plus the predicate test | |
| 12829 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12830 match(If cmp flags); | |
| 12831 effect(USE labl); | |
| 12832 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12833 ins_cost(300); | |
| 12834 expand %{ | |
| 12835 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12836 %} | |
| 12837 %} | |
| 12838 | |
| 12839 // Compare 2 longs and CMOVE longs. | |
| 12840 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12841 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12842 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12843 ins_cost(400); | |
| 12844 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12845 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12846 opcode(0x0F,0x40); | |
| 12847 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12848 ins_pipe( pipe_cmov_reg_long ); | |
| 12849 %} | |
| 12850 | |
| 12851 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12852 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12853 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12854 ins_cost(500); | |
| 12855 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12856 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12857 opcode(0x0F,0x40); | |
| 12858 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12859 ins_pipe( pipe_cmov_reg_long ); | |
| 12860 %} | |
| 12861 | |
| 12862 // Compare 2 longs and CMOVE ints. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12863 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12864 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12865 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12866 ins_cost(200); | |
| 12867 format %{ "CMOV$cmp $dst,$src" %} | |
| 12868 opcode(0x0F,0x40); | |
| 12869 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12870 ins_pipe( pipe_cmov_reg ); | |
| 12871 %} | |
| 12872 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12873 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12874 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12875 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12876 ins_cost(250); | |
| 12877 format %{ "CMOV$cmp $dst,$src" %} | |
| 12878 opcode(0x0F,0x40); | |
| 12879 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12880 ins_pipe( pipe_cmov_mem ); | |
| 12881 %} | |
| 12882 | |
| 12883 // Compare 2 longs and CMOVE ptrs. | |
| 12884 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12885 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12886 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12887 ins_cost(200); | |
| 12888 format %{ "CMOV$cmp $dst,$src" %} | |
| 12889 opcode(0x0F,0x40); | |
| 12890 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12891 ins_pipe( pipe_cmov_reg ); | |
| 12892 %} | |
| 12893 | |
| 12894 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12895 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12896 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12897 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12898 ins_cost(200); | |
| 12899 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12900 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12901 %} |
| 12902 %} | |
| 12903 | |
| 12904 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12905 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12906 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12907 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12908 ins_cost(200); | |
| 12909 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12910 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12911 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12912 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12913 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12914 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12915 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12916 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12917 ins_cost(200); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12918 expand %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12919 fcmovFPR_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12920 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12921 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12922 |
| 0 | 12923 |
| 12924 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12925 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12926 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12927 ins_cost(200); | |
| 12928 expand %{ | |
| 12929 fcmovF_regS(cmp,flags,dst,src); | |
| 12930 %} | |
| 12931 %} | |
| 12932 | |
| 12933 | |
| 12934 // ============================================================================ | |
| 12935 // Procedure Call/Return Instructions | |
| 12936 // Call Java Static Instruction | |
| 12937 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12938 // compute_padding() functions will have to be adjusted. | |
| 12939 instruct CallStaticJavaDirect(method meth) %{ | |
| 12940 match(CallStaticJava); | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12941 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 12942 effect(USE meth); |
| 12943 | |
| 12944 ins_cost(300); | |
| 12945 format %{ "CALL,static " %} | |
| 12946 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12947 ins_encode( pre_call_resets, |
| 0 | 12948 Java_Static_Call( meth ), |
| 12949 call_epilog, | |
| 12950 post_call_FPU ); | |
| 12951 ins_pipe( pipe_slow ); | |
| 12952 ins_alignment(4); | |
| 12953 %} | |
| 12954 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12955 // Call Java Static Instruction (method handle version) |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12956 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12957 // compute_padding() functions will have to be adjusted. |
| 1567 | 12958 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12959 match(CallStaticJava); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12960 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12961 effect(USE meth); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12962 // EBP is saved by all callees (for interpreter stack correction). |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12963 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12964 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12965 ins_cost(300); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12966 format %{ "CALL,static/MethodHandle " %} |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12967 opcode(0xE8); /* E8 cd */ |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12968 ins_encode( pre_call_resets, |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12969 preserve_SP, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12970 Java_Static_Call( meth ), |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12971 restore_SP, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12972 call_epilog, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12973 post_call_FPU ); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12974 ins_pipe( pipe_slow ); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12975 ins_alignment(4); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12976 %} |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12977 |
| 0 | 12978 // Call Java Dynamic Instruction |
| 12979 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12980 // compute_padding() functions will have to be adjusted. | |
| 12981 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12982 match(CallDynamicJava); | |
| 12983 effect(USE meth); | |
| 12984 | |
| 12985 ins_cost(300); | |
| 12986 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12987 "CALL,dynamic" %} | |
| 12988 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12989 ins_encode( pre_call_resets, |
| 0 | 12990 Java_Dynamic_Call( meth ), |
| 12991 call_epilog, | |
| 12992 post_call_FPU ); | |
| 12993 ins_pipe( pipe_slow ); | |
| 12994 ins_alignment(4); | |
| 12995 %} | |
| 12996 | |
| 12997 // Call Runtime Instruction | |
| 12998 instruct CallRuntimeDirect(method meth) %{ | |
| 12999 match(CallRuntime ); | |
| 13000 effect(USE meth); | |
| 13001 | |
| 13002 ins_cost(300); | |
| 13003 format %{ "CALL,runtime " %} | |
| 13004 opcode(0xE8); /* E8 cd */ | |
| 13005 // Use FFREEs to clear entries in float stack | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
13006 ins_encode( pre_call_resets, |
| 0 | 13007 FFree_Float_Stack_All, |
| 13008 Java_To_Runtime( meth ), | |
| 13009 post_call_FPU ); | |
| 13010 ins_pipe( pipe_slow ); | |
| 13011 %} | |
| 13012 | |
| 13013 // Call runtime without safepoint | |
| 13014 instruct CallLeafDirect(method meth) %{ | |
| 13015 match(CallLeaf); | |
| 13016 effect(USE meth); | |
| 13017 | |
| 13018 ins_cost(300); | |
| 13019 format %{ "CALL_LEAF,runtime " %} | |
| 13020 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
13021 ins_encode( pre_call_resets, |
| 0 | 13022 FFree_Float_Stack_All, |
| 13023 Java_To_Runtime( meth ), | |
| 13024 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 13025 ins_pipe( pipe_slow ); | |
| 13026 %} | |
| 13027 | |
| 13028 instruct CallLeafNoFPDirect(method meth) %{ | |
| 13029 match(CallLeafNoFP); | |
| 13030 effect(USE meth); | |
| 13031 | |
| 13032 ins_cost(300); | |
| 13033 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 13034 opcode(0xE8); /* E8 cd */ | |
| 13035 ins_encode(Java_To_Runtime(meth)); | |
| 13036 ins_pipe( pipe_slow ); | |
| 13037 %} | |
| 13038 | |
| 13039 | |
| 13040 // Return Instruction | |
| 13041 // Remove the return address & jump to it. | |
| 13042 instruct Ret() %{ | |
| 13043 match(Return); | |
| 13044 format %{ "RET" %} | |
| 13045 opcode(0xC3); | |
| 13046 ins_encode(OpcP); | |
| 13047 ins_pipe( pipe_jmp ); | |
| 13048 %} | |
| 13049 | |
| 13050 // Tail Call; Jump from runtime stub to Java code. | |
| 13051 // Also known as an 'interprocedural jump'. | |
| 13052 // Target of jump will eventually return to caller. | |
| 13053 // TailJump below removes the return address. | |
| 13054 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 13055 match(TailCall jump_target method_oop ); | |
| 13056 ins_cost(300); | |
| 13057 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 13058 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13059 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 13060 ins_pipe( pipe_jmp ); | |
| 13061 %} | |
| 13062 | |
| 13063 | |
| 13064 // Tail Jump; remove the return address; jump to target. | |
| 13065 // TailCall above leaves the return address around. | |
| 13066 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13067 match( TailJump jump_target ex_oop ); | |
| 13068 ins_cost(300); | |
| 13069 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13070 "JMP $jump_target " %} | |
| 13071 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13072 ins_encode( enc_pop_rdx, | |
| 13073 OpcP, RegOpc(jump_target) ); | |
| 13074 ins_pipe( pipe_jmp ); | |
| 13075 %} | |
| 13076 | |
| 13077 // Create exception oop: created by stack-crawling runtime code. | |
| 13078 // Created exception is now available to this handler, and is setup | |
| 13079 // just prior to jumping to this handler. No code emitted. | |
| 13080 instruct CreateException( eAXRegP ex_oop ) | |
| 13081 %{ | |
| 13082 match(Set ex_oop (CreateEx)); | |
| 13083 | |
| 13084 size(0); | |
| 13085 // use the following format syntax | |
| 13086 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13087 ins_encode(); | |
| 13088 ins_pipe( empty ); | |
| 13089 %} | |
| 13090 | |
| 13091 | |
| 13092 // Rethrow exception: | |
| 13093 // The exception oop will come in the first argument position. | |
| 13094 // Then JUMP (not call) to the rethrow stub code. | |
| 13095 instruct RethrowException() | |
| 13096 %{ | |
| 13097 match(Rethrow); | |
| 13098 | |
| 13099 // use the following format syntax | |
| 13100 format %{ "JMP rethrow_stub" %} | |
| 13101 ins_encode(enc_rethrow); | |
| 13102 ins_pipe( pipe_jmp ); | |
| 13103 %} | |
| 13104 | |
| 13105 // inlined locking and unlocking | |
| 13106 | |
| 13107 | |
| 4777 | 13108 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 0 | 13109 match( Set cr (FastLock object box) ); |
| 4777 | 13110 effect( TEMP tmp, TEMP scr, USE_KILL box ); |
| 0 | 13111 ins_cost(300); |
| 4777 | 13112 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 13113 ins_encode( Fast_Lock(object,box,tmp,scr) ); |
| 13114 ins_pipe( pipe_slow ); | |
| 13115 %} | |
| 13116 | |
| 13117 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 13118 match( Set cr (FastUnlock object box) ); | |
| 4777 | 13119 effect( TEMP tmp, USE_KILL box ); |
| 0 | 13120 ins_cost(300); |
| 4777 | 13121 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
| 0 | 13122 ins_encode( Fast_Unlock(object,box,tmp) ); |
| 13123 ins_pipe( pipe_slow ); | |
| 13124 %} | |
| 13125 | |
| 13126 | |
| 13127 | |
| 13128 // ============================================================================ | |
| 13129 // Safepoint Instruction | |
| 13130 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 13131 match(SafePoint); | |
| 13132 effect(KILL cr); | |
| 13133 | |
| 13134 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 13135 // On SPARC that might be acceptable as we can generate the address with | |
| 13136 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 13137 // putting additional pressure on the index-0 in the D$. Because of | |
| 13138 // alignment (just like the situation at hand) the lower indices tend | |
| 13139 // to see more traffic. It'd be better to change the polling address | |
| 13140 // to offset 0 of the last $line in the polling page. | |
| 13141 | |
| 13142 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 13143 ins_cost(125); | |
| 13144 size(6) ; | |
| 13145 ins_encode( Safepoint_Poll() ); | |
| 13146 ins_pipe( ialu_reg_mem ); | |
| 13147 %} | |
| 13148 | |
| 4950 | 13149 |
| 13150 // ============================================================================ | |
| 13151 // This name is KNOWN by the ADLC and cannot be changed. | |
| 13152 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 13153 // for this guy. | |
| 13154 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 13155 match(Set dst (ThreadLocal)); | |
| 13156 effect(DEF dst, KILL cr); | |
| 13157 | |
| 13158 format %{ "MOV $dst, Thread::current()" %} | |
| 13159 ins_encode %{ | |
| 13160 Register dstReg = as_Register($dst$$reg); | |
| 13161 __ get_thread(dstReg); | |
| 13162 %} | |
| 13163 ins_pipe( ialu_reg_fat ); | |
| 13164 %} | |
| 13165 | |
| 13166 | |
| 13167 | |
| 0 | 13168 //----------PEEPHOLE RULES----------------------------------------------------- |
| 13169 // These must follow all instruction definitions as they use the names | |
| 13170 // defined in the instructions definitions. | |
| 13171 // | |
| 605 | 13172 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13173 // |
| 13174 // peepconstraint %{ | |
| 13175 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13176 // [, ...] ); | |
| 13177 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13178 // | |
| 13179 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13180 // // provide an instruction_number.operand_name for each operand that appears | |
| 13181 // // in the replacement instruction's match rule | |
| 13182 // | |
| 13183 // ---------VM FLAGS--------------------------------------------------------- | |
| 13184 // | |
| 13185 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 13186 // | |
| 13187 // Each peephole rule is given an identifying number starting with zero and | |
| 13188 // increasing by one in the order seen by the parser. An individual peephole | |
| 13189 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13190 // on the command-line. | |
| 13191 // | |
| 13192 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13193 // | |
| 13194 // Only match adjacent instructions in same basic block | |
| 13195 // Only equality constraints | |
| 13196 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13197 // Only one replacement instruction | |
| 13198 // | |
| 13199 // ---------EXAMPLE---------------------------------------------------------- | |
| 13200 // | |
| 13201 // // pertinent parts of existing instructions in architecture description | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13202 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 13203 // match(Set dst (CopyI src)); |
| 13204 // %} | |
| 13205 // | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13206 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 13207 // match(Set dst (AddI dst src)); |
| 13208 // effect(KILL cr); | |
| 13209 // %} | |
| 13210 // | |
| 13211 // // Change (inc mov) to lea | |
| 13212 // peephole %{ | |
| 13213 // // increment preceeded by register-register move | |
| 13214 // peepmatch ( incI_eReg movI ); | |
| 13215 // // require that the destination register of the increment | |
| 13216 // // match the destination register of the move | |
| 13217 // peepconstraint ( 0.dst == 1.dst ); | |
| 13218 // // construct a replacement instruction that sets | |
| 13219 // // the destination to ( move's source register + one ) | |
| 13220 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13221 // %} | |
| 13222 // | |
| 13223 // Implementation no longer uses movX instructions since | |
| 13224 // machine-independent system no longer uses CopyX nodes. | |
| 13225 // | |
| 13226 // peephole %{ | |
| 13227 // peepmatch ( incI_eReg movI ); | |
| 13228 // peepconstraint ( 0.dst == 1.dst ); | |
| 13229 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13230 // %} | |
| 13231 // | |
| 13232 // peephole %{ | |
| 13233 // peepmatch ( decI_eReg movI ); | |
| 13234 // peepconstraint ( 0.dst == 1.dst ); | |
| 13235 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13236 // %} | |
| 13237 // | |
| 13238 // peephole %{ | |
| 13239 // peepmatch ( addI_eReg_imm movI ); | |
| 13240 // peepconstraint ( 0.dst == 1.dst ); | |
| 13241 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13242 // %} | |
| 13243 // | |
| 13244 // peephole %{ | |
| 13245 // peepmatch ( addP_eReg_imm movP ); | |
| 13246 // peepconstraint ( 0.dst == 1.dst ); | |
| 13247 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13248 // %} | |
| 13249 | |
| 13250 // // Change load of spilled value to only a spill | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13251 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13252 // match(Set mem (StoreI mem src)); |
| 13253 // %} | |
| 13254 // | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13255 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13256 // match(Set dst (LoadI mem)); |
| 13257 // %} | |
| 13258 // | |
| 13259 peephole %{ | |
| 13260 peepmatch ( loadI storeI ); | |
| 13261 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13262 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13263 %} | |
| 13264 | |
| 13265 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13266 // These must follow all instruction definitions as they use the names | |
| 13267 // defined in the instructions definitions. |