Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 6948:e522a00b91aa
Merge with http://hg.openjdk.java.net/hsx/hsx25/hotspot/ after NPG - C++ build works
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Mon, 12 Nov 2012 23:14:12 +0100 |
| parents | c38f13903fdf a3ecd773a7b9 |
| children | 291ffc492eb6 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_x86.inline.hpp" | |
| 27 #include "gc_interface/collectedHeap.inline.hpp" | |
| 28 #include "interpreter/interpreter.hpp" | |
| 29 #include "memory/cardTableModRefBS.hpp" | |
| 30 #include "memory/resourceArea.hpp" | |
| 31 #include "prims/methodHandles.hpp" | |
| 32 #include "runtime/biasedLocking.hpp" | |
| 33 #include "runtime/interfaceSupport.hpp" | |
| 34 #include "runtime/objectMonitor.hpp" | |
| 35 #include "runtime/os.hpp" | |
| 36 #include "runtime/sharedRuntime.hpp" | |
| 37 #include "runtime/stubRoutines.hpp" | |
| 38 #ifndef SERIALGC | |
| 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 41 #include "gc_implementation/g1/heapRegion.hpp" | |
| 42 #endif | |
| 0 | 43 |
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44 #ifdef PRODUCT |
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45 #define BLOCK_COMMENT(str) /* nothing */ |
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46 #define STOP(error) stop(error) |
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47 #else |
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48 #define BLOCK_COMMENT(str) block_comment(str) |
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49 #define STOP(error) block_comment(error); stop(error) |
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50 #endif |
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51 |
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52 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
| 0 | 53 // Implementation of AddressLiteral |
| 54 | |
| 55 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 56 _is_lval = false; | |
| 57 _target = target; | |
| 58 switch (rtype) { | |
| 59 case relocInfo::oop_type: | |
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60 case relocInfo::metadata_type: |
| 0 | 61 // Oops are a special case. Normally they would be their own section |
| 62 // but in cases like icBuffer they are literals in the code stream that | |
| 63 // we don't have a section for. We use none so that we get a literal address | |
| 64 // which is always patchable. | |
| 65 break; | |
| 66 case relocInfo::external_word_type: | |
| 67 _rspec = external_word_Relocation::spec(target); | |
| 68 break; | |
| 69 case relocInfo::internal_word_type: | |
| 70 _rspec = internal_word_Relocation::spec(target); | |
| 71 break; | |
| 72 case relocInfo::opt_virtual_call_type: | |
| 73 _rspec = opt_virtual_call_Relocation::spec(); | |
| 74 break; | |
| 75 case relocInfo::static_call_type: | |
| 76 _rspec = static_call_Relocation::spec(); | |
| 77 break; | |
| 78 case relocInfo::runtime_call_type: | |
| 79 _rspec = runtime_call_Relocation::spec(); | |
| 80 break; | |
| 81 case relocInfo::poll_type: | |
| 82 case relocInfo::poll_return_type: | |
| 83 _rspec = Relocation::spec_simple(rtype); | |
| 84 break; | |
| 85 case relocInfo::none: | |
| 86 break; | |
| 87 default: | |
| 88 ShouldNotReachHere(); | |
| 89 break; | |
| 90 } | |
| 91 } | |
| 92 | |
| 93 // Implementation of Address | |
| 94 | |
| 304 | 95 #ifdef _LP64 |
| 96 | |
| 0 | 97 Address Address::make_array(ArrayAddress adr) { |
| 98 // Not implementable on 64bit machines | |
| 99 // Should have been handled higher up the call chain. | |
| 100 ShouldNotReachHere(); | |
| 304 | 101 return Address(); |
| 102 } | |
| 103 | |
| 104 // exceedingly dangerous constructor | |
| 105 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 106 _base = noreg; | |
| 107 _index = noreg; | |
| 108 _scale = no_scale; | |
| 109 _disp = disp; | |
| 110 switch (rtype) { | |
| 111 case relocInfo::external_word_type: | |
| 112 _rspec = external_word_Relocation::spec(loc); | |
| 113 break; | |
| 114 case relocInfo::internal_word_type: | |
| 115 _rspec = internal_word_Relocation::spec(loc); | |
| 116 break; | |
| 117 case relocInfo::runtime_call_type: | |
| 118 // HMM | |
| 119 _rspec = runtime_call_Relocation::spec(); | |
| 120 break; | |
| 121 case relocInfo::poll_type: | |
| 122 case relocInfo::poll_return_type: | |
| 123 _rspec = Relocation::spec_simple(rtype); | |
| 124 break; | |
| 125 case relocInfo::none: | |
| 126 break; | |
| 127 default: | |
| 128 ShouldNotReachHere(); | |
| 129 } | |
| 130 } | |
| 131 #else // LP64 | |
| 132 | |
| 133 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 134 AddressLiteral base = adr.base(); |
| 135 Address index = adr.index(); | |
| 136 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 137 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 138 array._rspec = base._rspec; | |
| 139 return array; | |
| 304 | 140 } |
| 0 | 141 |
| 142 // exceedingly dangerous constructor | |
| 143 Address::Address(address loc, RelocationHolder spec) { | |
| 144 _base = noreg; | |
| 145 _index = noreg; | |
| 146 _scale = no_scale; | |
| 147 _disp = (intptr_t) loc; | |
| 148 _rspec = spec; | |
| 149 } | |
| 304 | 150 |
| 0 | 151 #endif // _LP64 |
| 152 | |
| 304 | 153 |
| 154 | |
| 0 | 155 // Convert the raw encoding form into the form expected by the constructor for |
| 156 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 157 // that to noreg for the Address constructor. | |
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158 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
| 624 | 159 RelocationHolder rspec; |
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160 if (disp_reloc != relocInfo::none) { |
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161 rspec = Relocation::spec_simple(disp_reloc); |
| 624 | 162 } |
| 0 | 163 bool valid_index = index != rsp->encoding(); |
| 164 if (valid_index) { | |
| 165 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 166 madr._rspec = rspec; |
| 0 | 167 return madr; |
| 168 } else { | |
| 169 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 170 madr._rspec = rspec; |
| 0 | 171 return madr; |
| 172 } | |
| 173 } | |
| 174 | |
| 175 // Implementation of Assembler | |
| 176 | |
| 177 int AbstractAssembler::code_fill_byte() { | |
| 178 return (u_char)'\xF4'; // hlt | |
| 179 } | |
| 180 | |
| 181 // make this go away someday | |
| 182 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 183 if (rtype == relocInfo::none) | |
| 184 emit_long(data); | |
| 185 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 186 } | |
| 187 | |
| 188 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 189 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 190 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 191 if (rspec.type() != relocInfo::none) { | |
| 192 #ifdef ASSERT | |
| 193 check_relocation(rspec, format); | |
| 194 #endif | |
| 195 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 196 // embedded words. Instead, relocate to the enclosing instruction. | |
| 197 | |
| 198 // hack. call32 is too wide for mask so use disp32 | |
| 199 if (format == call32_operand) | |
| 200 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 201 else | |
| 202 code_section()->relocate(inst_mark(), rspec, format); | |
| 203 } | |
| 204 emit_long(data); | |
| 205 } | |
| 206 | |
| 304 | 207 static int encode(Register r) { |
| 208 int enc = r->encoding(); | |
| 209 if (enc >= 8) { | |
| 210 enc -= 8; | |
| 211 } | |
| 212 return enc; | |
| 213 } | |
| 214 | |
| 215 static int encode(XMMRegister r) { | |
| 216 int enc = r->encoding(); | |
| 217 if (enc >= 8) { | |
| 218 enc -= 8; | |
| 219 } | |
| 220 return enc; | |
| 221 } | |
| 0 | 222 |
| 223 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 224 assert(dst->has_byte_register(), "must have byte register"); | |
| 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 226 assert(isByte(imm8), "not a byte"); | |
| 227 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 228 emit_byte(op1); | |
| 304 | 229 emit_byte(op2 | encode(dst)); |
| 0 | 230 emit_byte(imm8); |
| 231 } | |
| 232 | |
| 233 | |
| 304 | 234 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 235 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 236 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 237 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 238 if (is8bit(imm32)) { | |
| 239 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 240 emit_byte(op2 | encode(dst)); |
| 0 | 241 emit_byte(imm32 & 0xFF); |
| 242 } else { | |
| 243 emit_byte(op1); | |
| 304 | 244 emit_byte(op2 | encode(dst)); |
| 0 | 245 emit_long(imm32); |
| 246 } | |
| 247 } | |
| 248 | |
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249 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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250 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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251 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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252 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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253 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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254 emit_byte(op1); |
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255 emit_byte(op2 | encode(dst)); |
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256 emit_long(imm32); |
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257 } |
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258 |
| 0 | 259 // immediate-to-memory forms |
| 304 | 260 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 261 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 263 if (is8bit(imm32)) { | |
| 264 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 265 emit_operand(rm, adr, 1); |
| 0 | 266 emit_byte(imm32 & 0xFF); |
| 267 } else { | |
| 268 emit_byte(op1); | |
| 304 | 269 emit_operand(rm, adr, 4); |
| 0 | 270 emit_long(imm32); |
| 271 } | |
| 272 } | |
| 273 | |
| 274 | |
| 275 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 276 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 277 emit_byte(op1); | |
| 304 | 278 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 279 } | |
| 280 | |
| 281 | |
| 282 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 283 Address::ScaleFactor scale, int disp, | |
| 284 RelocationHolder const& rspec, | |
| 285 int rip_relative_correction) { | |
| 0 | 286 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 287 |
| 288 // Encode the registers as needed in the fields they are used in | |
| 289 | |
| 290 int regenc = encode(reg) << 3; | |
| 291 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 292 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 293 | |
| 0 | 294 if (base->is_valid()) { |
| 295 if (index->is_valid()) { | |
| 296 assert(scale != Address::no_scale, "inconsistent address"); | |
| 297 // [base + index*scale + disp] | |
| 304 | 298 if (disp == 0 && rtype == relocInfo::none && |
| 299 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 300 // [base + index*scale] |
| 301 // [00 reg 100][ss index base] | |
| 302 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 303 emit_byte(0x04 | regenc); |
| 304 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 305 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 306 // [base + index*scale + imm8] | |
| 307 // [01 reg 100][ss index base] imm8 | |
| 308 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 309 emit_byte(0x44 | regenc); |
| 310 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 311 emit_byte(disp & 0xFF); |
| 312 } else { | |
| 304 | 313 // [base + index*scale + disp32] |
| 314 // [10 reg 100][ss index base] disp32 | |
| 0 | 315 assert(index != rsp, "illegal addressing mode"); |
| 304 | 316 emit_byte(0x84 | regenc); |
| 317 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 318 emit_data(disp, rspec, disp32_operand); |
| 319 } | |
| 304 | 320 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 321 // [rsp + disp] | |
| 0 | 322 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 323 // [rsp] |
| 0 | 324 // [00 reg 100][00 100 100] |
| 304 | 325 emit_byte(0x04 | regenc); |
| 0 | 326 emit_byte(0x24); |
| 327 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 328 // [rsp + imm8] |
| 329 // [01 reg 100][00 100 100] disp8 | |
| 330 emit_byte(0x44 | regenc); | |
| 0 | 331 emit_byte(0x24); |
| 332 emit_byte(disp & 0xFF); | |
| 333 } else { | |
| 304 | 334 // [rsp + imm32] |
| 335 // [10 reg 100][00 100 100] disp32 | |
| 336 emit_byte(0x84 | regenc); | |
| 0 | 337 emit_byte(0x24); |
| 338 emit_data(disp, rspec, disp32_operand); | |
| 339 } | |
| 340 } else { | |
| 341 // [base + disp] | |
| 304 | 342 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 343 if (disp == 0 && rtype == relocInfo::none && | |
| 344 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 345 // [base] |
| 346 // [00 reg base] | |
| 304 | 347 emit_byte(0x00 | regenc | baseenc); |
| 0 | 348 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 349 // [base + disp8] |
| 350 // [01 reg base] disp8 | |
| 351 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 352 emit_byte(disp & 0xFF); |
| 353 } else { | |
| 304 | 354 // [base + disp32] |
| 355 // [10 reg base] disp32 | |
| 356 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 357 emit_data(disp, rspec, disp32_operand); |
| 358 } | |
| 359 } | |
| 360 } else { | |
| 361 if (index->is_valid()) { | |
| 362 assert(scale != Address::no_scale, "inconsistent address"); | |
| 363 // [index*scale + disp] | |
| 304 | 364 // [00 reg 100][ss index 101] disp32 |
| 0 | 365 assert(index != rsp, "illegal addressing mode"); |
| 304 | 366 emit_byte(0x04 | regenc); |
| 367 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 368 emit_data(disp, rspec, disp32_operand); |
| 304 | 369 } else if (rtype != relocInfo::none ) { |
| 370 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 371 // [00 000 101] disp32 | |
| 372 | |
| 373 emit_byte(0x05 | regenc); | |
| 374 // Note that the RIP-rel. correction applies to the generated | |
| 375 // disp field, but _not_ to the target address in the rspec. | |
| 376 | |
| 377 // disp was created by converting the target address minus the pc | |
| 378 // at the start of the instruction. That needs more correction here. | |
| 379 // intptr_t disp = target - next_ip; | |
| 380 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 381 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 382 int64_t adjusted = disp; | |
| 383 // Do rip-rel adjustment for 64bit | |
| 384 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 385 assert(is_simm32(adjusted), | |
| 386 "must be 32bit offset (RIP relative address)"); | |
| 387 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 388 | |
| 0 | 389 } else { |
| 304 | 390 // 32bit never did this, did everything as the rip-rel/disp code above |
| 391 // [disp] ABSOLUTE | |
| 392 // [00 reg 100][00 100 101] disp32 | |
| 393 emit_byte(0x04 | regenc); | |
| 394 emit_byte(0x25); | |
| 0 | 395 emit_data(disp, rspec, disp32_operand); |
| 396 } | |
| 397 } | |
| 398 } | |
| 399 | |
| 304 | 400 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 401 Address::ScaleFactor scale, int disp, | |
| 402 RelocationHolder const& rspec) { | |
| 403 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 404 } | |
| 405 | |
| 0 | 406 // Secret local extension to Assembler::WhichOperand: |
| 407 #define end_pc_operand (_WhichOperand_limit) | |
| 408 | |
| 409 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 410 // Decode the given instruction, and return the address of | |
| 411 // an embedded 32-bit operand word. | |
| 412 | |
| 413 // If "which" is disp32_operand, selects the displacement portion | |
| 414 // of an effective address specifier. | |
| 304 | 415 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 416 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 417 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 418 // and that it is 32/64 bits wide. |
| 0 | 419 |
| 420 // If "which" is end_pc_operand, find the end of the instruction. | |
| 421 | |
| 422 address ip = inst; | |
| 304 | 423 bool is_64bit = false; |
| 424 | |
| 425 debug_only(bool has_disp32 = false); | |
| 426 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 427 | |
| 428 again_after_prefix: | |
| 0 | 429 switch (0xFF & *ip++) { |
| 430 | |
| 431 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 432 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 433 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 434 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 435 #define REP16(x) REP8((x)+0): \ |
| 0 | 436 case REP8((x)+8) |
| 437 | |
| 438 case CS_segment: | |
| 439 case SS_segment: | |
| 440 case DS_segment: | |
| 441 case ES_segment: | |
| 442 case FS_segment: | |
| 443 case GS_segment: | |
| 304 | 444 // Seems dubious |
| 445 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 446 assert(ip == inst+1, "only one prefix allowed"); |
| 447 goto again_after_prefix; | |
| 448 | |
| 304 | 449 case 0x67: |
| 450 case REX: | |
| 451 case REX_B: | |
| 452 case REX_X: | |
| 453 case REX_XB: | |
| 454 case REX_R: | |
| 455 case REX_RB: | |
| 456 case REX_RX: | |
| 457 case REX_RXB: | |
| 458 NOT_LP64(assert(false, "64bit prefixes")); | |
| 459 goto again_after_prefix; | |
| 460 | |
| 461 case REX_W: | |
| 462 case REX_WB: | |
| 463 case REX_WX: | |
| 464 case REX_WXB: | |
| 465 case REX_WR: | |
| 466 case REX_WRB: | |
| 467 case REX_WRX: | |
| 468 case REX_WRXB: | |
| 469 NOT_LP64(assert(false, "64bit prefixes")); | |
| 470 is_64bit = true; | |
| 471 goto again_after_prefix; | |
| 472 | |
| 473 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 474 case 0x88: // movb a, r |
| 475 case 0x89: // movl a, r | |
| 476 case 0x8A: // movb r, a | |
| 477 case 0x8B: // movl r, a | |
| 478 case 0x8F: // popl a | |
| 304 | 479 debug_only(has_disp32 = true); |
| 0 | 480 break; |
| 481 | |
| 304 | 482 case 0x68: // pushq #32 |
| 483 if (which == end_pc_operand) { | |
| 484 return ip + 4; | |
| 485 } | |
| 486 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 487 return ip; // not produced by emit_operand |
| 488 | |
| 489 case 0x66: // movw ... (size prefix) | |
| 304 | 490 again_after_size_prefix2: |
| 0 | 491 switch (0xFF & *ip++) { |
| 304 | 492 case REX: |
| 493 case REX_B: | |
| 494 case REX_X: | |
| 495 case REX_XB: | |
| 496 case REX_R: | |
| 497 case REX_RB: | |
| 498 case REX_RX: | |
| 499 case REX_RXB: | |
| 500 case REX_W: | |
| 501 case REX_WB: | |
| 502 case REX_WX: | |
| 503 case REX_WXB: | |
| 504 case REX_WR: | |
| 505 case REX_WRB: | |
| 506 case REX_WRX: | |
| 507 case REX_WRXB: | |
| 508 NOT_LP64(assert(false, "64bit prefix found")); | |
| 509 goto again_after_size_prefix2; | |
| 0 | 510 case 0x8B: // movw r, a |
| 511 case 0x89: // movw a, r | |
| 304 | 512 debug_only(has_disp32 = true); |
| 0 | 513 break; |
| 514 case 0xC7: // movw a, #16 | |
| 304 | 515 debug_only(has_disp32 = true); |
| 0 | 516 tail_size = 2; // the imm16 |
| 517 break; | |
| 518 case 0x0F: // several SSE/SSE2 variants | |
| 519 ip--; // reparse the 0x0F | |
| 520 goto again_after_prefix; | |
| 521 default: | |
| 522 ShouldNotReachHere(); | |
| 523 } | |
| 524 break; | |
| 525 | |
| 304 | 526 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 527 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 528 // these asserts are somewhat nonsensical | |
| 529 #ifndef _LP64 | |
| 5984 | 530 assert(which == imm_operand || which == disp32_operand, |
| 531 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
| 304 | 532 #else |
| 533 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 5984 | 534 which == narrow_oop_operand && !is_64bit, |
| 535 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
| 304 | 536 #endif // _LP64 |
| 0 | 537 return ip; |
| 538 | |
| 539 case 0x69: // imul r, a, #32 | |
| 540 case 0xC7: // movl a, #32(oop?) | |
| 541 tail_size = 4; | |
| 304 | 542 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 543 break; |
| 544 | |
| 545 case 0x0F: // movx..., etc. | |
| 546 switch (0xFF & *ip++) { | |
| 4759 | 547 case 0x3A: // pcmpestri |
| 548 tail_size = 1; | |
| 549 case 0x38: // ptest, pmovzxbw | |
| 550 ip++; // skip opcode | |
| 551 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 552 break; | |
| 553 | |
| 554 case 0x70: // pshufd r, r/a, #8 | |
| 555 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 556 case 0x73: // psrldq r, #8 | |
| 557 tail_size = 1; | |
| 558 break; | |
| 559 | |
| 0 | 560 case 0x12: // movlps |
| 561 case 0x28: // movaps | |
| 562 case 0x2E: // ucomiss | |
| 563 case 0x2F: // comiss | |
| 564 case 0x54: // andps | |
| 565 case 0x55: // andnps | |
| 566 case 0x56: // orps | |
| 567 case 0x57: // xorps | |
| 568 case 0x6E: // movd | |
| 569 case 0x7E: // movd | |
| 4759 | 570 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
| 304 | 571 debug_only(has_disp32 = true); |
| 0 | 572 break; |
| 573 | |
| 574 case 0xAD: // shrd r, a, %cl | |
| 575 case 0xAF: // imul r, a | |
| 304 | 576 case 0xBE: // movsbl r, a (movsxb) |
| 577 case 0xBF: // movswl r, a (movsxw) | |
| 578 case 0xB6: // movzbl r, a (movzxb) | |
| 579 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 580 case REP16(0x40): // cmovl cc, r, a |
| 581 case 0xB0: // cmpxchgb | |
| 582 case 0xB1: // cmpxchg | |
| 583 case 0xC1: // xaddl | |
| 584 case 0xC7: // cmpxchg8 | |
| 585 case REP16(0x90): // setcc a | |
| 304 | 586 debug_only(has_disp32 = true); |
| 0 | 587 // fall out of the switch to decode the address |
| 588 break; | |
| 304 | 589 |
| 4759 | 590 case 0xC4: // pinsrw r, a, #8 |
| 591 debug_only(has_disp32 = true); | |
| 592 case 0xC5: // pextrw r, r, #8 | |
| 593 tail_size = 1; // the imm8 | |
| 594 break; | |
| 595 | |
| 0 | 596 case 0xAC: // shrd r, a, #8 |
| 304 | 597 debug_only(has_disp32 = true); |
| 0 | 598 tail_size = 1; // the imm8 |
| 599 break; | |
| 304 | 600 |
| 0 | 601 case REP16(0x80): // jcc rdisp32 |
| 602 if (which == end_pc_operand) return ip + 4; | |
| 304 | 603 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 604 return ip; |
| 605 default: | |
| 606 ShouldNotReachHere(); | |
| 607 } | |
| 608 break; | |
| 609 | |
| 610 case 0x81: // addl a, #32; addl r, #32 | |
| 611 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 612 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 613 tail_size = 4; |
| 304 | 614 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 615 break; |
| 616 | |
| 617 case 0x83: // addl a, #8; addl r, #8 | |
| 618 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 619 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 620 tail_size = 1; |
| 621 break; | |
| 622 | |
| 623 case 0x9B: | |
| 624 switch (0xFF & *ip++) { | |
| 625 case 0xD9: // fnstcw a | |
| 304 | 626 debug_only(has_disp32 = true); |
| 0 | 627 break; |
| 628 default: | |
| 629 ShouldNotReachHere(); | |
| 630 } | |
| 631 break; | |
| 632 | |
| 633 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 634 case REP4(0x10): // adc... | |
| 635 case REP4(0x20): // and... | |
| 636 case REP4(0x30): // xor... | |
| 637 case REP4(0x08): // or... | |
| 638 case REP4(0x18): // sbb... | |
| 639 case REP4(0x28): // sub... | |
| 304 | 640 case 0xF7: // mull a |
| 641 case 0x8D: // lea r, a | |
| 642 case 0x87: // xchg r, a | |
| 0 | 643 case REP4(0x38): // cmp... |
| 304 | 644 case 0x85: // test r, a |
| 645 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 646 break; |
| 647 | |
| 648 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 649 case 0xC6: // movb a, #8 | |
| 650 case 0x80: // cmpb a, #8 | |
| 651 case 0x6B: // imul r, a, #8 | |
| 304 | 652 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 653 tail_size = 1; // the imm8 |
| 654 break; | |
| 655 | |
| 4759 | 656 case 0xC4: // VEX_3bytes |
| 657 case 0xC5: // VEX_2bytes | |
| 658 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
| 659 assert(ip == inst+1, "no prefixes allowed"); | |
| 660 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
| 661 // but they have prefix 0x0F and processed when 0x0F processed above. | |
| 662 // | |
| 663 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
| 664 // instructions (these instructions are not supported in 64-bit mode). | |
| 665 // To distinguish them bits [7:6] are set in the VEX second byte since | |
| 666 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
| 667 // those VEX bits REX and vvvv bits are inverted. | |
| 668 // | |
| 669 // Fortunately C2 doesn't generate these instructions so we don't need | |
| 670 // to check for them in product version. | |
| 671 | |
| 672 // Check second byte | |
| 673 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
| 674 | |
| 675 // First byte | |
| 676 if ((0xFF & *inst) == VEX_3bytes) { | |
| 677 ip++; // third byte | |
| 678 is_64bit = ((VEX_W & *ip) == VEX_W); | |
| 679 } | |
| 680 ip++; // opcode | |
| 681 // To find the end of instruction (which == end_pc_operand). | |
| 682 switch (0xFF & *ip) { | |
| 683 case 0x61: // pcmpestri r, r/a, #8 | |
| 684 case 0x70: // pshufd r, r/a, #8 | |
| 685 case 0x73: // psrldq r, #8 | |
| 686 tail_size = 1; // the imm8 | |
| 687 break; | |
| 688 default: | |
| 689 break; | |
| 690 } | |
| 691 ip++; // skip opcode | |
| 692 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 693 break; | |
| 0 | 694 |
| 695 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 696 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 697 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 698 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 699 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 700 case 0xDF: // fild_d a; fistp_d a | |
| 701 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 702 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 703 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 704 debug_only(has_disp32 = true); |
| 0 | 705 break; |
| 706 | |
| 4759 | 707 case 0xE8: // call rdisp32 |
| 708 case 0xE9: // jmp rdisp32 | |
| 709 if (which == end_pc_operand) return ip + 4; | |
| 710 assert(which == call32_operand, "call has no disp32 or imm"); | |
| 711 return ip; | |
| 712 | |
|
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713 case 0xF0: // Lock |
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714 assert(os::is_MP(), "only on MP"); |
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715 goto again_after_prefix; |
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716 |
| 0 | 717 case 0xF3: // For SSE |
| 718 case 0xF2: // For SSE2 | |
| 304 | 719 switch (0xFF & *ip++) { |
| 720 case REX: | |
| 721 case REX_B: | |
| 722 case REX_X: | |
| 723 case REX_XB: | |
| 724 case REX_R: | |
| 725 case REX_RB: | |
| 726 case REX_RX: | |
| 727 case REX_RXB: | |
| 728 case REX_W: | |
| 729 case REX_WB: | |
| 730 case REX_WX: | |
| 731 case REX_WXB: | |
| 732 case REX_WR: | |
| 733 case REX_WRB: | |
| 734 case REX_WRX: | |
| 735 case REX_WRXB: | |
| 736 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 737 ip++; | |
| 738 default: | |
| 739 ip++; | |
| 740 } | |
| 741 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 742 break; |
| 743 | |
| 744 default: | |
| 745 ShouldNotReachHere(); | |
| 746 | |
| 304 | 747 #undef REP8 |
| 748 #undef REP16 | |
| 0 | 749 } |
| 750 | |
| 751 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 752 #ifdef _LP64 |
| 753 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 754 #else | |
| 755 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 756 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 757 #endif // LP64 | |
| 758 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 759 |
| 760 // parse the output of emit_operand | |
| 761 int op2 = 0xFF & *ip++; | |
| 762 int base = op2 & 0x07; | |
| 763 int op3 = -1; | |
| 764 const int b100 = 4; | |
| 765 const int b101 = 5; | |
| 766 if (base == b100 && (op2 >> 6) != 3) { | |
| 767 op3 = 0xFF & *ip++; | |
| 768 base = op3 & 0x07; // refetch the base | |
| 769 } | |
| 770 // now ip points at the disp (if any) | |
| 771 | |
| 772 switch (op2 >> 6) { | |
| 773 case 0: | |
| 774 // [00 reg 100][ss index base] | |
| 304 | 775 // [00 reg 100][00 100 esp] |
| 0 | 776 // [00 reg base] |
| 777 // [00 reg 100][ss index 101][disp32] | |
| 778 // [00 reg 101] [disp32] | |
| 779 | |
| 780 if (base == b101) { | |
| 781 if (which == disp32_operand) | |
| 782 return ip; // caller wants the disp32 | |
| 783 ip += 4; // skip the disp32 | |
| 784 } | |
| 785 break; | |
| 786 | |
| 787 case 1: | |
| 788 // [01 reg 100][ss index base][disp8] | |
| 304 | 789 // [01 reg 100][00 100 esp][disp8] |
| 0 | 790 // [01 reg base] [disp8] |
| 791 ip += 1; // skip the disp8 | |
| 792 break; | |
| 793 | |
| 794 case 2: | |
| 795 // [10 reg 100][ss index base][disp32] | |
| 304 | 796 // [10 reg 100][00 100 esp][disp32] |
| 0 | 797 // [10 reg base] [disp32] |
| 798 if (which == disp32_operand) | |
| 799 return ip; // caller wants the disp32 | |
| 800 ip += 4; // skip the disp32 | |
| 801 break; | |
| 802 | |
| 803 case 3: | |
| 804 // [11 reg base] (not a memory addressing mode) | |
| 805 break; | |
| 806 } | |
| 807 | |
| 808 if (which == end_pc_operand) { | |
| 809 return ip + tail_size; | |
| 810 } | |
| 811 | |
| 304 | 812 #ifdef _LP64 |
|
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813 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 814 #else |
| 815 assert(which == imm_operand, "instruction has only an imm field"); | |
| 816 #endif // LP64 | |
| 0 | 817 return ip; |
| 818 } | |
| 819 | |
| 820 address Assembler::locate_next_instruction(address inst) { | |
| 821 // Secretly share code with locate_operand: | |
| 822 return locate_operand(inst, end_pc_operand); | |
| 823 } | |
| 824 | |
| 825 | |
| 826 #ifdef ASSERT | |
| 827 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 828 address inst = inst_mark(); | |
| 829 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 830 address opnd; | |
| 831 | |
| 832 Relocation* r = rspec.reloc(); | |
| 833 if (r->type() == relocInfo::none) { | |
| 834 return; | |
| 835 } else if (r->is_call() || format == call32_operand) { | |
| 836 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 837 opnd = locate_operand(inst, call32_operand); | |
| 838 } else if (r->is_data()) { | |
| 304 | 839 assert(format == imm_operand || format == disp32_operand |
| 840 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 841 opnd = locate_operand(inst, (WhichOperand)format); |
| 842 } else { | |
| 304 | 843 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 844 return; |
| 845 } | |
| 846 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 847 } | |
| 304 | 848 #endif // ASSERT |
| 849 | |
| 850 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 851 assert(reg->encoding() < 8, "no extended registers"); | |
| 852 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 854 adr._rspec); | |
| 855 } | |
| 856 | |
| 857 void Assembler::emit_operand(Register reg, Address adr, | |
| 858 int rip_relative_correction) { | |
| 859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 860 adr._rspec, | |
| 861 rip_relative_correction); | |
| 862 } | |
| 863 | |
| 864 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 865 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 866 adr._rspec); | |
| 867 } | |
| 868 | |
| 869 // MMX operations | |
| 870 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 873 } | |
| 874 | |
| 875 // work around gcc (3.2.1-7a) bug | |
| 876 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 877 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 878 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 879 } |
| 880 | |
| 881 | |
| 882 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 883 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 884 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 885 emit_byte(b1); | |
| 886 emit_byte(b2 + i); | |
| 887 } | |
| 888 | |
| 889 | |
|
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890 // Now the Assembler instructions (identical for 32/64 bits) |
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891 |
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892 void Assembler::adcl(Address dst, int32_t imm32) { |
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893 InstructionMark im(this); |
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894 prefix(dst); |
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895 emit_arith_operand(0x81, rdx, dst, imm32); |
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896 } |
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897 |
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898 void Assembler::adcl(Address dst, Register src) { |
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899 InstructionMark im(this); |
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900 prefix(dst, src); |
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901 emit_byte(0x11); |
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902 emit_operand(src, dst); |
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903 } |
| 304 | 904 |
| 905 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 906 prefix(dst); | |
| 0 | 907 emit_arith(0x81, 0xD0, dst, imm32); |
| 908 } | |
| 909 | |
| 910 void Assembler::adcl(Register dst, Address src) { | |
| 911 InstructionMark im(this); | |
| 304 | 912 prefix(src, dst); |
| 0 | 913 emit_byte(0x13); |
| 914 emit_operand(dst, src); | |
| 915 } | |
| 916 | |
| 917 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 918 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 919 emit_arith(0x13, 0xC0, dst, src); |
| 920 } | |
| 921 | |
| 304 | 922 void Assembler::addl(Address dst, int32_t imm32) { |
| 923 InstructionMark im(this); | |
| 924 prefix(dst); | |
| 925 emit_arith_operand(0x81, rax, dst, imm32); | |
| 926 } | |
| 0 | 927 |
| 928 void Assembler::addl(Address dst, Register src) { | |
| 929 InstructionMark im(this); | |
| 304 | 930 prefix(dst, src); |
| 0 | 931 emit_byte(0x01); |
| 932 emit_operand(src, dst); | |
| 933 } | |
| 934 | |
| 304 | 935 void Assembler::addl(Register dst, int32_t imm32) { |
| 936 prefix(dst); | |
| 0 | 937 emit_arith(0x81, 0xC0, dst, imm32); |
| 938 } | |
| 939 | |
| 940 void Assembler::addl(Register dst, Address src) { | |
| 941 InstructionMark im(this); | |
| 304 | 942 prefix(src, dst); |
| 0 | 943 emit_byte(0x03); |
| 944 emit_operand(dst, src); | |
| 945 } | |
| 946 | |
| 947 void Assembler::addl(Register dst, Register src) { | |
| 304 | 948 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 949 emit_arith(0x03, 0xC0, dst, src); |
| 950 } | |
| 951 | |
| 952 void Assembler::addr_nop_4() { | |
|
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953 assert(UseAddressNop, "no CPU support"); |
| 0 | 954 // 4 bytes: NOP DWORD PTR [EAX+0] |
| 955 emit_byte(0x0F); | |
| 956 emit_byte(0x1F); | |
| 957 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 958 emit_byte(0); // 8-bits offset (1 byte) | |
| 959 } | |
| 960 | |
| 961 void Assembler::addr_nop_5() { | |
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962 assert(UseAddressNop, "no CPU support"); |
| 0 | 963 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
| 964 emit_byte(0x0F); | |
| 965 emit_byte(0x1F); | |
| 966 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 967 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 968 emit_byte(0); // 8-bits offset (1 byte) | |
| 969 } | |
| 970 | |
| 971 void Assembler::addr_nop_7() { | |
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972 assert(UseAddressNop, "no CPU support"); |
| 0 | 973 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
| 974 emit_byte(0x0F); | |
| 975 emit_byte(0x1F); | |
| 976 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 977 emit_long(0); // 32-bits offset (4 bytes) | |
| 978 } | |
| 979 | |
| 980 void Assembler::addr_nop_8() { | |
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981 assert(UseAddressNop, "no CPU support"); |
| 0 | 982 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
| 983 emit_byte(0x0F); | |
| 984 emit_byte(0x1F); | |
| 985 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 986 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 987 emit_long(0); // 32-bits offset (4 bytes) | |
| 988 } | |
| 989 | |
| 304 | 990 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 991 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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992 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
| 304 | 993 } |
| 994 | |
| 995 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 996 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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997 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
| 304 | 998 } |
| 999 | |
| 1000 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 1001 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1002 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
| 304 | 1003 } |
| 1004 | |
| 1005 void Assembler::addss(XMMRegister dst, Address src) { | |
| 1006 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1007 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
| 304 | 1008 } |
| 1009 | |
| 6894 | 1010 void Assembler::aesdec(XMMRegister dst, Address src) { |
| 1011 assert(VM_Version::supports_aes(), ""); | |
| 1012 InstructionMark im(this); | |
| 1013 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1014 emit_byte(0xde); | |
| 1015 emit_operand(dst, src); | |
| 1016 } | |
| 1017 | |
| 1018 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |
| 1019 assert(VM_Version::supports_aes(), ""); | |
| 1020 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1021 emit_byte(0xde); | |
| 1022 emit_byte(0xC0 | encode); | |
| 1023 } | |
| 1024 | |
| 1025 void Assembler::aesdeclast(XMMRegister dst, Address src) { | |
| 1026 assert(VM_Version::supports_aes(), ""); | |
| 1027 InstructionMark im(this); | |
| 1028 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1029 emit_byte(0xdf); | |
| 1030 emit_operand(dst, src); | |
| 1031 } | |
| 1032 | |
| 1033 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |
| 1034 assert(VM_Version::supports_aes(), ""); | |
| 1035 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1036 emit_byte(0xdf); | |
| 1037 emit_byte(0xC0 | encode); | |
| 1038 } | |
| 1039 | |
| 1040 void Assembler::aesenc(XMMRegister dst, Address src) { | |
| 1041 assert(VM_Version::supports_aes(), ""); | |
| 1042 InstructionMark im(this); | |
| 1043 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1044 emit_byte(0xdc); | |
| 1045 emit_operand(dst, src); | |
| 1046 } | |
| 1047 | |
| 1048 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |
| 1049 assert(VM_Version::supports_aes(), ""); | |
| 1050 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1051 emit_byte(0xdc); | |
| 1052 emit_byte(0xC0 | encode); | |
| 1053 } | |
| 1054 | |
| 1055 void Assembler::aesenclast(XMMRegister dst, Address src) { | |
| 1056 assert(VM_Version::supports_aes(), ""); | |
| 1057 InstructionMark im(this); | |
| 1058 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1059 emit_byte(0xdd); | |
| 1060 emit_operand(dst, src); | |
| 1061 } | |
| 1062 | |
| 1063 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |
| 1064 assert(VM_Version::supports_aes(), ""); | |
| 1065 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 1066 emit_byte(0xdd); | |
| 1067 emit_byte(0xC0 | encode); | |
| 1068 } | |
| 1069 | |
| 1070 | |
| 4759 | 1071 void Assembler::andl(Address dst, int32_t imm32) { |
| 1072 InstructionMark im(this); | |
| 1073 prefix(dst); | |
| 1074 emit_byte(0x81); | |
| 1075 emit_operand(rsp, dst, 4); | |
| 1076 emit_long(imm32); | |
| 1077 } | |
| 1078 | |
| 304 | 1079 void Assembler::andl(Register dst, int32_t imm32) { |
| 1080 prefix(dst); | |
| 1081 emit_arith(0x81, 0xE0, dst, imm32); | |
| 1082 } | |
| 1083 | |
| 1084 void Assembler::andl(Register dst, Address src) { | |
| 1085 InstructionMark im(this); | |
| 1086 prefix(src, dst); | |
| 1087 emit_byte(0x23); | |
| 1088 emit_operand(dst, src); | |
| 1089 } | |
| 1090 | |
| 1091 void Assembler::andl(Register dst, Register src) { | |
| 1092 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1093 emit_arith(0x23, 0xC0, dst, src); | |
| 1094 } | |
| 1095 | |
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1096 void Assembler::bsfl(Register dst, Register src) { |
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1097 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1098 emit_byte(0x0F); |
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1099 emit_byte(0xBC); |
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1100 emit_byte(0xC0 | encode); |
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1101 } |
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1102 |
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1103 void Assembler::bsrl(Register dst, Register src) { |
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1104 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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1105 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1106 emit_byte(0x0F); |
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1107 emit_byte(0xBD); |
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1108 emit_byte(0xC0 | encode); |
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1109 } |
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1110 |
| 304 | 1111 void Assembler::bswapl(Register reg) { // bswap |
| 1112 int encode = prefix_and_encode(reg->encoding()); | |
| 1113 emit_byte(0x0F); | |
| 1114 emit_byte(0xC8 | encode); | |
| 1115 } | |
| 1116 | |
| 1117 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1118 // suspect disp32 is always good | |
| 1119 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1120 | |
| 1121 if (L.is_bound()) { | |
| 1122 const int long_size = 5; | |
| 1123 int offs = (int)( target(L) - pc() ); | |
| 1124 assert(offs <= 0, "assembler error"); | |
| 1125 InstructionMark im(this); | |
| 1126 // 1110 1000 #32-bit disp | |
| 1127 emit_byte(0xE8); | |
| 1128 emit_data(offs - long_size, rtype, operand); | |
| 1129 } else { | |
| 1130 InstructionMark im(this); | |
| 1131 // 1110 1000 #32-bit disp | |
| 1132 L.add_patch_at(code(), locator()); | |
| 1133 | |
| 1134 emit_byte(0xE8); | |
| 1135 emit_data(int(0), rtype, operand); | |
| 1136 } | |
| 1137 } | |
| 1138 | |
| 1139 void Assembler::call(Register dst) { | |
| 4759 | 1140 int encode = prefix_and_encode(dst->encoding()); |
| 304 | 1141 emit_byte(0xFF); |
| 1142 emit_byte(0xD0 | encode); | |
| 1143 } | |
| 1144 | |
| 1145 | |
| 1146 void Assembler::call(Address adr) { | |
| 1147 InstructionMark im(this); | |
| 1148 prefix(adr); | |
| 1149 emit_byte(0xFF); | |
| 1150 emit_operand(rdx, adr); | |
| 1151 } | |
| 1152 | |
| 1153 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1154 assert(entry != NULL, "call most probably wrong"); | |
| 1155 InstructionMark im(this); | |
| 1156 emit_byte(0xE8); | |
| 1157 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1158 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1159 // Technically, should use call32_operand, but this format is | |
| 1160 // implied by the fact that we're emitting a call instruction. | |
| 1161 | |
| 1162 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1163 emit_data((int) disp, rspec, operand); | |
| 1164 } | |
| 1165 | |
| 1166 void Assembler::cdql() { | |
| 1167 emit_byte(0x99); | |
| 1168 } | |
| 1169 | |
| 1170 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1171 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1172 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1173 emit_byte(0x0F); | |
| 1174 emit_byte(0x40 | cc); | |
| 1175 emit_byte(0xC0 | encode); | |
| 1176 } | |
| 1177 | |
| 1178 | |
| 1179 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1180 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1181 prefix(src, dst); | |
| 1182 emit_byte(0x0F); | |
| 1183 emit_byte(0x40 | cc); | |
| 1184 emit_operand(dst, src); | |
| 1185 } | |
| 1186 | |
| 1187 void Assembler::cmpb(Address dst, int imm8) { | |
| 1188 InstructionMark im(this); | |
| 1189 prefix(dst); | |
| 1190 emit_byte(0x80); | |
| 1191 emit_operand(rdi, dst, 1); | |
| 1192 emit_byte(imm8); | |
| 1193 } | |
| 1194 | |
| 1195 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1196 InstructionMark im(this); | |
| 1197 prefix(dst); | |
| 1198 emit_byte(0x81); | |
| 1199 emit_operand(rdi, dst, 4); | |
| 1200 emit_long(imm32); | |
| 1201 } | |
| 1202 | |
| 1203 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1204 prefix(dst); | |
| 1205 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1206 } | |
| 1207 | |
| 1208 void Assembler::cmpl(Register dst, Register src) { | |
| 1209 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1210 emit_arith(0x3B, 0xC0, dst, src); | |
| 1211 } | |
| 1212 | |
| 1213 | |
| 1214 void Assembler::cmpl(Register dst, Address src) { | |
| 1215 InstructionMark im(this); | |
| 1216 prefix(src, dst); | |
| 1217 emit_byte(0x3B); | |
| 1218 emit_operand(dst, src); | |
| 1219 } | |
| 1220 | |
| 1221 void Assembler::cmpw(Address dst, int imm16) { | |
| 1222 InstructionMark im(this); | |
| 1223 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1224 emit_byte(0x66); | |
| 1225 emit_byte(0x81); | |
| 1226 emit_operand(rdi, dst, 2); | |
| 1227 emit_word(imm16); | |
| 1228 } | |
| 1229 | |
| 1230 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1231 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1232 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1233 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 6834 | 1234 InstructionMark im(this); |
| 1235 prefix(adr, reg); | |
| 1236 emit_byte(0x0F); | |
| 1237 emit_byte(0xB1); | |
| 1238 emit_operand(reg, adr); | |
| 304 | 1239 } |
| 1240 | |
| 1241 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1242 // NOTE: dbx seems to decode this as comiss even though the | |
| 1243 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1244 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1245 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
| 4759 | 1246 } |
| 1247 | |
| 1248 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
| 1249 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1250 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
| 304 | 1251 } |
| 1252 | |
| 1253 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1254 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1255 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
| 304 | 1256 } |
| 1257 | |
| 4759 | 1258 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
| 1259 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1260 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
| 4759 | 1261 } |
| 1262 | |
| 304 | 1263 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
| 1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1265 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
| 304 | 1266 } |
| 1267 | |
| 1268 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1269 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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1270 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
| 304 | 1271 } |
| 1272 | |
| 1273 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1275 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
| 304 | 1276 } |
| 1277 | |
| 4759 | 1278 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
| 1279 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1280 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
| 4759 | 1281 } |
| 1282 | |
| 304 | 1283 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
| 1284 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1286 emit_byte(0x2A); |
| 1287 emit_byte(0xC0 | encode); | |
| 1288 } | |
| 1289 | |
| 4759 | 1290 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
| 1291 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1292 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
| 4759 | 1293 } |
| 1294 | |
| 304 | 1295 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
| 1296 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1298 emit_byte(0x2A); |
| 1299 emit_byte(0xC0 | encode); | |
| 1300 } | |
| 1301 | |
| 4759 | 1302 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
| 1303 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1304 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
| 4759 | 1305 } |
| 1306 | |
| 304 | 1307 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
| 1308 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1309 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
| 304 | 1310 } |
| 1311 | |
| 4759 | 1312 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
| 1313 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1314 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
| 4759 | 1315 } |
| 1316 | |
| 1317 | |
| 304 | 1318 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
| 1319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1320 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
| 304 | 1321 emit_byte(0x2C); |
| 1322 emit_byte(0xC0 | encode); | |
| 1323 } | |
| 1324 | |
| 1325 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1326 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1327 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 304 | 1328 emit_byte(0x2C); |
| 1329 emit_byte(0xC0 | encode); | |
| 1330 } | |
| 1331 | |
| 1332 void Assembler::decl(Address dst) { | |
| 1333 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1334 InstructionMark im(this); | |
| 1335 prefix(dst); | |
| 1336 emit_byte(0xFF); | |
| 1337 emit_operand(rcx, dst); | |
| 1338 } | |
| 1339 | |
| 1340 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1341 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1342 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
| 304 | 1343 } |
| 1344 | |
| 1345 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1346 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1347 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
| 304 | 1348 } |
| 1349 | |
| 1350 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1351 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1352 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
| 304 | 1353 } |
| 1354 | |
| 1355 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1356 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1357 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
| 304 | 1358 } |
| 1359 | |
| 1360 void Assembler::emms() { | |
| 1361 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1362 emit_byte(0x0F); | |
| 1363 emit_byte(0x77); | |
| 1364 } | |
| 1365 | |
| 1366 void Assembler::hlt() { | |
| 1367 emit_byte(0xF4); | |
| 1368 } | |
| 1369 | |
| 1370 void Assembler::idivl(Register src) { | |
| 1371 int encode = prefix_and_encode(src->encoding()); | |
| 1372 emit_byte(0xF7); | |
| 1373 emit_byte(0xF8 | encode); | |
| 1374 } | |
| 1375 | |
| 1920 | 1376 void Assembler::divl(Register src) { // Unsigned |
| 1377 int encode = prefix_and_encode(src->encoding()); | |
| 1378 emit_byte(0xF7); | |
| 1379 emit_byte(0xF0 | encode); | |
| 1380 } | |
| 1381 | |
| 304 | 1382 void Assembler::imull(Register dst, Register src) { |
| 1383 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1384 emit_byte(0x0F); | |
| 1385 emit_byte(0xAF); | |
| 1386 emit_byte(0xC0 | encode); | |
| 1387 } | |
| 1388 | |
| 1389 | |
| 1390 void Assembler::imull(Register dst, Register src, int value) { | |
| 1391 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1392 if (is8bit(value)) { | |
| 1393 emit_byte(0x6B); | |
| 1394 emit_byte(0xC0 | encode); | |
|
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1395 emit_byte(value & 0xFF); |
| 304 | 1396 } else { |
| 1397 emit_byte(0x69); | |
| 1398 emit_byte(0xC0 | encode); | |
| 1399 emit_long(value); | |
| 1400 } | |
| 1401 } | |
| 1402 | |
| 1403 void Assembler::incl(Address dst) { | |
| 1404 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1405 InstructionMark im(this); | |
| 1406 prefix(dst); | |
| 1407 emit_byte(0xFF); | |
| 1408 emit_operand(rax, dst); | |
| 1409 } | |
| 1410 | |
| 3851 | 1411 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
| 1412 InstructionMark im(this); | |
| 304 | 1413 assert((0 <= cc) && (cc < 16), "illegal cc"); |
| 1414 if (L.is_bound()) { | |
| 1415 address dst = target(L); | |
| 1416 assert(dst != NULL, "jcc most probably wrong"); | |
| 1417 | |
| 1418 const int short_size = 2; | |
| 1419 const int long_size = 6; | |
| 1420 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 3851 | 1421 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1422 // 0111 tttn #8-bit disp |
| 1423 emit_byte(0x70 | cc); | |
| 1424 emit_byte((offs - short_size) & 0xFF); | |
| 1425 } else { | |
| 1426 // 0000 1111 1000 tttn #32-bit disp | |
| 1427 assert(is_simm32(offs - long_size), | |
| 1428 "must be 32bit offset (call4)"); | |
| 1429 emit_byte(0x0F); | |
| 1430 emit_byte(0x80 | cc); | |
| 1431 emit_long(offs - long_size); | |
| 1432 } | |
| 1433 } else { | |
| 1434 // Note: could eliminate cond. jumps to this jump if condition | |
| 1435 // is the same however, seems to be rather unlikely case. | |
| 1436 // Note: use jccb() if label to be bound is very close to get | |
| 1437 // an 8-bit displacement | |
| 1438 L.add_patch_at(code(), locator()); | |
| 1439 emit_byte(0x0F); | |
| 1440 emit_byte(0x80 | cc); | |
| 1441 emit_long(0); | |
| 1442 } | |
| 1443 } | |
| 1444 | |
| 1445 void Assembler::jccb(Condition cc, Label& L) { | |
| 1446 if (L.is_bound()) { | |
| 1447 const int short_size = 2; | |
| 1448 address entry = target(L); | |
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1449 #ifdef ASSERT |
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1450 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); |
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1451 intptr_t delta = short_branch_delta(); |
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1452 if (delta != 0) { |
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1453 dist += (dist < 0 ? (-delta) :delta); |
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1454 } |
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1455 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1456 #endif |
| 304 | 1457 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; |
| 1458 // 0111 tttn #8-bit disp | |
| 1459 emit_byte(0x70 | cc); | |
| 1460 emit_byte((offs - short_size) & 0xFF); | |
| 1461 } else { | |
| 1462 InstructionMark im(this); | |
| 1463 L.add_patch_at(code(), locator()); | |
| 1464 emit_byte(0x70 | cc); | |
| 1465 emit_byte(0); | |
| 1466 } | |
| 1467 } | |
| 1468 | |
| 1469 void Assembler::jmp(Address adr) { | |
| 1470 InstructionMark im(this); | |
| 1471 prefix(adr); | |
| 1472 emit_byte(0xFF); | |
| 1473 emit_operand(rsp, adr); | |
| 1474 } | |
| 1475 | |
| 3851 | 1476 void Assembler::jmp(Label& L, bool maybe_short) { |
| 304 | 1477 if (L.is_bound()) { |
| 1478 address entry = target(L); | |
| 1479 assert(entry != NULL, "jmp most probably wrong"); | |
| 1480 InstructionMark im(this); | |
| 1481 const int short_size = 2; | |
| 1482 const int long_size = 5; | |
| 1483 intptr_t offs = entry - _code_pos; | |
| 3851 | 1484 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1485 emit_byte(0xEB); |
| 1486 emit_byte((offs - short_size) & 0xFF); | |
| 1487 } else { | |
| 1488 emit_byte(0xE9); | |
| 1489 emit_long(offs - long_size); | |
| 1490 } | |
| 1491 } else { | |
| 1492 // By default, forward jumps are always 32-bit displacements, since | |
| 1493 // we can't yet know where the label will be bound. If you're sure that | |
| 1494 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1495 // force an 8-bit displacement. | |
| 1496 InstructionMark im(this); | |
| 1497 L.add_patch_at(code(), locator()); | |
| 1498 emit_byte(0xE9); | |
| 1499 emit_long(0); | |
| 1500 } | |
| 1501 } | |
| 1502 | |
| 1503 void Assembler::jmp(Register entry) { | |
| 1504 int encode = prefix_and_encode(entry->encoding()); | |
| 1505 emit_byte(0xFF); | |
| 1506 emit_byte(0xE0 | encode); | |
| 1507 } | |
| 1508 | |
| 1509 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1510 InstructionMark im(this); | |
| 1511 emit_byte(0xE9); | |
| 1512 assert(dest != NULL, "must have a target"); | |
| 1513 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1514 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1515 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1516 } | |
| 1517 | |
| 1518 void Assembler::jmpb(Label& L) { | |
| 1519 if (L.is_bound()) { | |
| 1520 const int short_size = 2; | |
| 1521 address entry = target(L); | |
| 1522 assert(entry != NULL, "jmp most probably wrong"); | |
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1523 #ifdef ASSERT |
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1524 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); |
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1525 intptr_t delta = short_branch_delta(); |
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1526 if (delta != 0) { |
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1527 dist += (dist < 0 ? (-delta) :delta); |
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1528 } |
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1529 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1530 #endif |
| 304 | 1531 intptr_t offs = entry - _code_pos; |
| 1532 emit_byte(0xEB); | |
| 1533 emit_byte((offs - short_size) & 0xFF); | |
| 1534 } else { | |
| 1535 InstructionMark im(this); | |
| 1536 L.add_patch_at(code(), locator()); | |
| 1537 emit_byte(0xEB); | |
| 1538 emit_byte(0); | |
| 1539 } | |
| 1540 } | |
| 1541 | |
| 1542 void Assembler::ldmxcsr( Address src) { | |
| 1543 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1544 InstructionMark im(this); | |
| 1545 prefix(src); | |
| 1546 emit_byte(0x0F); | |
| 1547 emit_byte(0xAE); | |
| 1548 emit_operand(as_Register(2), src); | |
| 1549 } | |
| 1550 | |
| 1551 void Assembler::leal(Register dst, Address src) { | |
| 1552 InstructionMark im(this); | |
| 1553 #ifdef _LP64 | |
| 1554 emit_byte(0x67); // addr32 | |
| 1555 prefix(src, dst); | |
| 1556 #endif // LP64 | |
| 1557 emit_byte(0x8D); | |
| 1558 emit_operand(dst, src); | |
| 1559 } | |
| 1560 | |
| 1561 void Assembler::lock() { | |
| 6834 | 1562 emit_byte(0xF0); |
| 304 | 1563 } |
| 1564 | |
|
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1565 void Assembler::lzcntl(Register dst, Register src) { |
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1566 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1567 emit_byte(0xF3); |
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1568 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1569 emit_byte(0x0F); |
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1570 emit_byte(0xBD); |
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1571 emit_byte(0xC0 | encode); |
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1572 } |
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1573 |
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1574 // Emit mfence instruction |
| 304 | 1575 void Assembler::mfence() { |
|
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1576 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1577 emit_byte( 0x0F ); |
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1578 emit_byte( 0xAE ); |
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1579 emit_byte( 0xF0 ); |
| 304 | 1580 } |
| 1581 | |
| 1582 void Assembler::mov(Register dst, Register src) { | |
| 1583 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1584 } | |
| 1585 | |
| 1586 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1587 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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1588 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
| 304 | 1589 } |
| 1590 | |
| 1591 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1592 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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1593 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
| 304 | 1594 } |
| 1595 | |
|
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1596 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
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1597 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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1598 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
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1599 emit_byte(0x16); |
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1600 emit_byte(0xC0 | encode); |
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1601 } |
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1602 |
| 304 | 1603 void Assembler::movb(Register dst, Address src) { |
| 1604 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1605 InstructionMark im(this); | |
| 1606 prefix(src, dst, true); | |
| 1607 emit_byte(0x8A); | |
| 1608 emit_operand(dst, src); | |
| 1609 } | |
| 1610 | |
| 1611 | |
| 1612 void Assembler::movb(Address dst, int imm8) { | |
| 1613 InstructionMark im(this); | |
| 1614 prefix(dst); | |
| 1615 emit_byte(0xC6); | |
| 1616 emit_operand(rax, dst, 1); | |
| 1617 emit_byte(imm8); | |
| 1618 } | |
| 1619 | |
| 1620 | |
| 1621 void Assembler::movb(Address dst, Register src) { | |
| 1622 assert(src->has_byte_register(), "must have byte register"); | |
| 1623 InstructionMark im(this); | |
| 1624 prefix(dst, src, true); | |
| 1625 emit_byte(0x88); | |
| 1626 emit_operand(src, dst); | |
| 1627 } | |
| 1628 | |
| 1629 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1630 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1631 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1632 emit_byte(0x6E); |
| 1633 emit_byte(0xC0 | encode); | |
| 1634 } | |
| 1635 | |
| 1636 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1637 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1638 // swap src/dst to get correct prefix | |
| 4759 | 1639 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
| 304 | 1640 emit_byte(0x7E); |
| 1641 emit_byte(0xC0 | encode); | |
| 1642 } | |
| 1643 | |
|
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1644 void Assembler::movdl(XMMRegister dst, Address src) { |
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1645 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1646 InstructionMark im(this); |
| 4759 | 1647 simd_prefix(dst, src, VEX_SIMD_66); |
|
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1648 emit_byte(0x6E); |
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1649 emit_operand(dst, src); |
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1650 } |
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1651 |
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1652 void Assembler::movdl(Address dst, XMMRegister src) { |
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1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1654 InstructionMark im(this); |
|
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1655 simd_prefix(dst, src, VEX_SIMD_66); |
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1656 emit_byte(0x7E); |
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1657 emit_operand(src, dst); |
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1658 } |
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1659 |
| 304 | 1660 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
| 1661 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1662 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
| 304 | 1663 } |
| 1664 | |
| 405 | 1665 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1666 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1667 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
| 405 | 1668 } |
| 1669 | |
| 1670 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1671 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1672 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
| 405 | 1673 } |
| 1674 | |
| 1675 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1676 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1677 InstructionMark im(this); | |
| 4759 | 1678 simd_prefix(dst, src, VEX_SIMD_F3); |
| 405 | 1679 emit_byte(0x7F); |
| 1680 emit_operand(src, dst); | |
| 1681 } | |
| 1682 | |
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1683 // Move Unaligned 256bit Vector |
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1684 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
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1685 assert(UseAVX, ""); |
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1686 bool vector256 = true; |
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1687 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1688 emit_byte(0x6F); |
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1689 emit_byte(0xC0 | encode); |
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1690 } |
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1691 |
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1692 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
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1693 assert(UseAVX, ""); |
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1694 InstructionMark im(this); |
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1695 bool vector256 = true; |
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1696 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1697 emit_byte(0x6F); |
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1698 emit_operand(dst, src); |
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1699 } |
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1700 |
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1701 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
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1702 assert(UseAVX, ""); |
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1703 InstructionMark im(this); |
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1704 bool vector256 = true; |
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1705 // swap src<->dst for encoding |
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1706 assert(src != xnoreg, "sanity"); |
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1707 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
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1708 emit_byte(0x7F); |
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1709 emit_operand(src, dst); |
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1710 } |
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1711 |
| 304 | 1712 // Uses zero extension on 64bit |
| 1713 | |
| 1714 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1715 int encode = prefix_and_encode(dst->encoding()); | |
| 1716 emit_byte(0xB8 | encode); | |
| 1717 emit_long(imm32); | |
| 1718 } | |
| 1719 | |
| 1720 void Assembler::movl(Register dst, Register src) { | |
| 1721 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1722 emit_byte(0x8B); | |
| 1723 emit_byte(0xC0 | encode); | |
| 1724 } | |
| 1725 | |
| 1726 void Assembler::movl(Register dst, Address src) { | |
| 1727 InstructionMark im(this); | |
| 1728 prefix(src, dst); | |
| 1729 emit_byte(0x8B); | |
| 1730 emit_operand(dst, src); | |
| 1731 } | |
| 1732 | |
| 1733 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1734 InstructionMark im(this); | |
| 1735 prefix(dst); | |
| 1736 emit_byte(0xC7); | |
| 1737 emit_operand(rax, dst, 4); | |
| 1738 emit_long(imm32); | |
| 1739 } | |
| 1740 | |
| 1741 void Assembler::movl(Address dst, Register src) { | |
| 1742 InstructionMark im(this); | |
| 1743 prefix(dst, src); | |
| 1744 emit_byte(0x89); | |
| 1745 emit_operand(src, dst); | |
| 1746 } | |
| 1747 | |
| 1748 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1749 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1750 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1751 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1752 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1753 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
| 304 | 1754 } |
| 1755 | |
| 1756 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1757 assert( VM_Version::supports_mmx(), "" ); | |
| 1758 emit_byte(0x0F); | |
| 1759 emit_byte(0x6F); | |
| 1760 emit_operand(dst, src); | |
| 1761 } | |
| 1762 | |
| 1763 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1764 assert( VM_Version::supports_mmx(), "" ); | |
| 1765 emit_byte(0x0F); | |
| 1766 emit_byte(0x7F); | |
| 1767 // workaround gcc (3.2.1-7a) bug | |
| 1768 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1769 // gcc will tail jump and try and reverse the parameters completely | |
| 1770 // obliterating dst in the process. By having a version available | |
| 1771 // that doesn't need to swap the args at the tail jump the bug is | |
| 1772 // avoided. | |
| 1773 emit_operand(dst, src); | |
| 1774 } | |
| 1775 | |
| 1776 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1778 InstructionMark im(this); | |
| 4759 | 1779 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1780 emit_byte(0x7E); |
| 1781 emit_operand(dst, src); | |
| 1782 } | |
| 1783 | |
| 1784 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1785 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1786 InstructionMark im(this); | |
| 4759 | 1787 simd_prefix(dst, src, VEX_SIMD_66); |
| 304 | 1788 emit_byte(0xD6); |
| 1789 emit_operand(src, dst); | |
| 1790 } | |
| 1791 | |
| 1792 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1793 InstructionMark im(this); | |
| 1794 prefix(src, dst); | |
| 1795 emit_byte(0x0F); | |
| 1796 emit_byte(0xBE); | |
| 1797 emit_operand(dst, src); | |
| 1798 } | |
| 1799 | |
| 1800 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1801 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1802 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1803 emit_byte(0x0F); | |
| 1804 emit_byte(0xBE); | |
| 1805 emit_byte(0xC0 | encode); | |
| 1806 } | |
| 1807 | |
| 1808 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1809 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1810 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
| 304 | 1811 } |
| 1812 | |
| 1813 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1814 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1815 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
| 304 | 1816 } |
| 1817 | |
| 1818 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1819 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1820 InstructionMark im(this); | |
| 4759 | 1821 simd_prefix(dst, src, VEX_SIMD_F2); |
| 304 | 1822 emit_byte(0x11); |
| 1823 emit_operand(src, dst); | |
| 1824 } | |
| 1825 | |
| 1826 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1827 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1828 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
| 304 | 1829 } |
| 1830 | |
| 1831 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1832 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1833 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
| 304 | 1834 } |
| 1835 | |
| 1836 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1837 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1838 InstructionMark im(this); | |
| 4759 | 1839 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1840 emit_byte(0x11); |
| 1841 emit_operand(src, dst); | |
| 1842 } | |
| 1843 | |
| 1844 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1845 InstructionMark im(this); | |
| 1846 prefix(src, dst); | |
| 1847 emit_byte(0x0F); | |
| 1848 emit_byte(0xBF); | |
| 1849 emit_operand(dst, src); | |
| 1850 } | |
| 1851 | |
| 1852 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1853 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1854 emit_byte(0x0F); | |
| 1855 emit_byte(0xBF); | |
| 1856 emit_byte(0xC0 | encode); | |
| 1857 } | |
| 1858 | |
| 1859 void Assembler::movw(Address dst, int imm16) { | |
| 1860 InstructionMark im(this); | |
| 1861 | |
| 1862 emit_byte(0x66); // switch to 16-bit mode | |
| 1863 prefix(dst); | |
| 1864 emit_byte(0xC7); | |
| 1865 emit_operand(rax, dst, 2); | |
| 1866 emit_word(imm16); | |
| 1867 } | |
| 1868 | |
| 1869 void Assembler::movw(Register dst, Address src) { | |
| 1870 InstructionMark im(this); | |
| 1871 emit_byte(0x66); | |
| 1872 prefix(src, dst); | |
| 1873 emit_byte(0x8B); | |
| 1874 emit_operand(dst, src); | |
| 1875 } | |
| 1876 | |
| 1877 void Assembler::movw(Address dst, Register src) { | |
| 1878 InstructionMark im(this); | |
| 1879 emit_byte(0x66); | |
| 1880 prefix(dst, src); | |
| 1881 emit_byte(0x89); | |
| 1882 emit_operand(src, dst); | |
| 1883 } | |
| 1884 | |
| 1885 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1886 InstructionMark im(this); | |
| 1887 prefix(src, dst); | |
| 1888 emit_byte(0x0F); | |
| 1889 emit_byte(0xB6); | |
| 1890 emit_operand(dst, src); | |
| 1891 } | |
| 1892 | |
| 1893 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1894 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1895 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1896 emit_byte(0x0F); | |
| 1897 emit_byte(0xB6); | |
| 1898 emit_byte(0xC0 | encode); | |
| 1899 } | |
| 1900 | |
| 1901 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1902 InstructionMark im(this); | |
| 1903 prefix(src, dst); | |
| 1904 emit_byte(0x0F); | |
| 1905 emit_byte(0xB7); | |
| 1906 emit_operand(dst, src); | |
| 1907 } | |
| 1908 | |
| 1909 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1910 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1911 emit_byte(0x0F); | |
| 1912 emit_byte(0xB7); | |
| 1913 emit_byte(0xC0 | encode); | |
| 1914 } | |
| 1915 | |
| 1916 void Assembler::mull(Address src) { | |
| 1917 InstructionMark im(this); | |
| 1918 prefix(src); | |
| 1919 emit_byte(0xF7); | |
| 1920 emit_operand(rsp, src); | |
| 1921 } | |
| 1922 | |
| 1923 void Assembler::mull(Register src) { | |
| 1924 int encode = prefix_and_encode(src->encoding()); | |
| 1925 emit_byte(0xF7); | |
| 1926 emit_byte(0xE0 | encode); | |
| 1927 } | |
| 1928 | |
| 1929 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1931 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
| 304 | 1932 } |
| 1933 | |
| 1934 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1935 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1936 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
| 304 | 1937 } |
| 1938 | |
| 1939 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1940 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1941 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
| 304 | 1942 } |
| 1943 | |
| 1944 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1945 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1946 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
| 304 | 1947 } |
| 1948 | |
| 1949 void Assembler::negl(Register dst) { | |
| 1950 int encode = prefix_and_encode(dst->encoding()); | |
| 1951 emit_byte(0xF7); | |
| 1952 emit_byte(0xD8 | encode); | |
| 1953 } | |
| 1954 | |
| 0 | 1955 void Assembler::nop(int i) { |
| 304 | 1956 #ifdef ASSERT |
| 0 | 1957 assert(i > 0, " "); |
| 304 | 1958 // The fancy nops aren't currently recognized by debuggers making it a |
| 1959 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1960 // speed is not an issue so simply use the single byte traditional nop | |
| 1961 // to do alignment. | |
| 1962 | |
| 1963 for (; i > 0 ; i--) emit_byte(0x90); | |
| 1964 return; | |
| 1965 | |
| 1966 #endif // ASSERT | |
| 1967 | |
| 0 | 1968 if (UseAddressNop && VM_Version::is_intel()) { |
| 1969 // | |
| 1970 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1971 // 1: 0x90 | |
| 1972 // 2: 0x66 0x90 | |
| 1973 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1974 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1975 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1976 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1977 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1978 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1979 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1980 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1981 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1982 | |
| 1983 // The rest coding is Intel specific - don't use consecutive address nops | |
| 1984 | |
| 1985 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1986 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1987 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1988 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1989 | |
| 1990 while(i >= 15) { | |
| 1991 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 1992 i -= 15; | |
| 1993 emit_byte(0x66); // size prefix | |
| 1994 emit_byte(0x66); // size prefix | |
| 1995 emit_byte(0x66); // size prefix | |
| 1996 addr_nop_8(); | |
| 1997 emit_byte(0x66); // size prefix | |
| 1998 emit_byte(0x66); // size prefix | |
| 1999 emit_byte(0x66); // size prefix | |
| 2000 emit_byte(0x90); // nop | |
| 2001 } | |
| 2002 switch (i) { | |
| 2003 case 14: | |
| 2004 emit_byte(0x66); // size prefix | |
| 2005 case 13: | |
| 2006 emit_byte(0x66); // size prefix | |
| 2007 case 12: | |
| 2008 addr_nop_8(); | |
| 2009 emit_byte(0x66); // size prefix | |
| 2010 emit_byte(0x66); // size prefix | |
| 2011 emit_byte(0x66); // size prefix | |
| 2012 emit_byte(0x90); // nop | |
| 2013 break; | |
| 2014 case 11: | |
| 2015 emit_byte(0x66); // size prefix | |
| 2016 case 10: | |
| 2017 emit_byte(0x66); // size prefix | |
| 2018 case 9: | |
| 2019 emit_byte(0x66); // size prefix | |
| 2020 case 8: | |
| 2021 addr_nop_8(); | |
| 2022 break; | |
| 2023 case 7: | |
| 2024 addr_nop_7(); | |
| 2025 break; | |
| 2026 case 6: | |
| 2027 emit_byte(0x66); // size prefix | |
| 2028 case 5: | |
| 2029 addr_nop_5(); | |
| 2030 break; | |
| 2031 case 4: | |
| 2032 addr_nop_4(); | |
| 2033 break; | |
| 2034 case 3: | |
| 2035 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2036 emit_byte(0x66); // size prefix | |
| 2037 case 2: | |
| 2038 emit_byte(0x66); // size prefix | |
| 2039 case 1: | |
| 2040 emit_byte(0x90); // nop | |
| 2041 break; | |
| 2042 default: | |
| 2043 assert(i == 0, " "); | |
| 2044 } | |
| 2045 return; | |
| 2046 } | |
| 2047 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2048 // | |
| 2049 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2050 // 1: 0x90 | |
| 2051 // 2: 0x66 0x90 | |
| 2052 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2053 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2054 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2055 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2056 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2057 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2058 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2059 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2060 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2061 | |
| 2062 // The rest coding is AMD specific - use consecutive address nops | |
| 2063 | |
| 2064 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2065 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2066 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2067 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2068 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2069 // Size prefixes (0x66) are added for larger sizes | |
| 2070 | |
| 2071 while(i >= 22) { | |
| 2072 i -= 11; | |
| 2073 emit_byte(0x66); // size prefix | |
| 2074 emit_byte(0x66); // size prefix | |
| 2075 emit_byte(0x66); // size prefix | |
| 2076 addr_nop_8(); | |
| 2077 } | |
| 2078 // Generate first nop for size between 21-12 | |
| 2079 switch (i) { | |
| 2080 case 21: | |
| 2081 i -= 1; | |
| 2082 emit_byte(0x66); // size prefix | |
| 2083 case 20: | |
| 2084 case 19: | |
| 2085 i -= 1; | |
| 2086 emit_byte(0x66); // size prefix | |
| 2087 case 18: | |
| 2088 case 17: | |
| 2089 i -= 1; | |
| 2090 emit_byte(0x66); // size prefix | |
| 2091 case 16: | |
| 2092 case 15: | |
| 2093 i -= 8; | |
| 2094 addr_nop_8(); | |
| 2095 break; | |
| 2096 case 14: | |
| 2097 case 13: | |
| 2098 i -= 7; | |
| 2099 addr_nop_7(); | |
| 2100 break; | |
| 2101 case 12: | |
| 2102 i -= 6; | |
| 2103 emit_byte(0x66); // size prefix | |
| 2104 addr_nop_5(); | |
| 2105 break; | |
| 2106 default: | |
| 2107 assert(i < 12, " "); | |
| 2108 } | |
| 2109 | |
| 2110 // Generate second nop for size between 11-1 | |
| 2111 switch (i) { | |
| 2112 case 11: | |
| 2113 emit_byte(0x66); // size prefix | |
| 2114 case 10: | |
| 2115 emit_byte(0x66); // size prefix | |
| 2116 case 9: | |
| 2117 emit_byte(0x66); // size prefix | |
| 2118 case 8: | |
| 2119 addr_nop_8(); | |
| 2120 break; | |
| 2121 case 7: | |
| 2122 addr_nop_7(); | |
| 2123 break; | |
| 2124 case 6: | |
| 2125 emit_byte(0x66); // size prefix | |
| 2126 case 5: | |
| 2127 addr_nop_5(); | |
| 2128 break; | |
| 2129 case 4: | |
| 2130 addr_nop_4(); | |
| 2131 break; | |
| 2132 case 3: | |
| 2133 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2134 emit_byte(0x66); // size prefix | |
| 2135 case 2: | |
| 2136 emit_byte(0x66); // size prefix | |
| 2137 case 1: | |
| 2138 emit_byte(0x90); // nop | |
| 2139 break; | |
| 2140 default: | |
| 2141 assert(i == 0, " "); | |
| 2142 } | |
| 2143 return; | |
| 2144 } | |
| 2145 | |
| 2146 // Using nops with size prefixes "0x66 0x90". | |
| 2147 // From AMD Optimization Guide: | |
| 2148 // 1: 0x90 | |
| 2149 // 2: 0x66 0x90 | |
| 2150 // 3: 0x66 0x66 0x90 | |
| 2151 // 4: 0x66 0x66 0x66 0x90 | |
| 2152 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2153 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2154 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2155 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2156 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2157 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2158 // | |
| 2159 while(i > 12) { | |
| 2160 i -= 4; | |
| 2161 emit_byte(0x66); // size prefix | |
| 2162 emit_byte(0x66); | |
| 2163 emit_byte(0x66); | |
| 2164 emit_byte(0x90); // nop | |
| 2165 } | |
| 2166 // 1 - 12 nops | |
| 2167 if(i > 8) { | |
| 2168 if(i > 9) { | |
| 2169 i -= 1; | |
| 2170 emit_byte(0x66); | |
| 2171 } | |
| 2172 i -= 3; | |
| 2173 emit_byte(0x66); | |
| 2174 emit_byte(0x66); | |
| 2175 emit_byte(0x90); | |
| 2176 } | |
| 2177 // 1 - 8 nops | |
| 2178 if(i > 4) { | |
| 2179 if(i > 6) { | |
| 2180 i -= 1; | |
| 2181 emit_byte(0x66); | |
| 2182 } | |
| 2183 i -= 3; | |
| 2184 emit_byte(0x66); | |
| 2185 emit_byte(0x66); | |
| 2186 emit_byte(0x90); | |
| 2187 } | |
| 2188 switch (i) { | |
| 2189 case 4: | |
| 2190 emit_byte(0x66); | |
| 2191 case 3: | |
| 2192 emit_byte(0x66); | |
| 2193 case 2: | |
| 2194 emit_byte(0x66); | |
| 2195 case 1: | |
| 2196 emit_byte(0x90); | |
| 2197 break; | |
| 2198 default: | |
| 2199 assert(i == 0, " "); | |
| 2200 } | |
| 2201 } | |
| 2202 | |
| 304 | 2203 void Assembler::notl(Register dst) { |
| 2204 int encode = prefix_and_encode(dst->encoding()); | |
| 2205 emit_byte(0xF7); | |
| 2206 emit_byte(0xD0 | encode ); | |
| 2207 } | |
| 2208 | |
| 2209 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2210 InstructionMark im(this); | |
| 2211 prefix(dst); | |
|
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2212 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2213 } |
| 2214 | |
| 2215 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2216 prefix(dst); | |
| 2217 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2218 } | |
| 2219 | |
| 2220 void Assembler::orl(Register dst, Address src) { | |
| 2221 InstructionMark im(this); | |
| 2222 prefix(src, dst); | |
| 2223 emit_byte(0x0B); | |
| 2224 emit_operand(dst, src); | |
| 2225 } | |
| 2226 | |
| 2227 void Assembler::orl(Register dst, Register src) { | |
| 2228 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2229 emit_arith(0x0B, 0xC0, dst, src); | |
| 2230 } | |
| 2231 | |
| 4759 | 2232 void Assembler::packuswb(XMMRegister dst, Address src) { |
| 2233 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2234 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2235 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
| 4759 | 2236 } |
| 2237 | |
| 2238 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
| 2239 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2240 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
| 4759 | 2241 } |
| 2242 | |
| 681 | 2243 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2244 assert(VM_Version::supports_sse4_2(), ""); | |
| 4759 | 2245 InstructionMark im(this); |
| 2246 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
| 681 | 2247 emit_byte(0x61); |
| 2248 emit_operand(dst, src); | |
| 2249 emit_byte(imm8); | |
| 2250 } | |
| 2251 | |
| 2252 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2253 assert(VM_Version::supports_sse4_2(), ""); | |
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2254 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
| 681 | 2255 emit_byte(0x61); |
| 2256 emit_byte(0xC0 | encode); | |
| 2257 emit_byte(imm8); | |
| 2258 } | |
| 2259 | |
| 4759 | 2260 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
| 2261 assert(VM_Version::supports_sse4_1(), ""); | |
| 2262 InstructionMark im(this); | |
| 2263 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2264 emit_byte(0x30); | |
| 2265 emit_operand(dst, src); | |
| 2266 } | |
| 2267 | |
| 2268 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
| 2269 assert(VM_Version::supports_sse4_1(), ""); | |
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2270 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
| 4759 | 2271 emit_byte(0x30); |
| 2272 emit_byte(0xC0 | encode); | |
| 2273 } | |
| 2274 | |
| 304 | 2275 // generic |
| 2276 void Assembler::pop(Register dst) { | |
| 2277 int encode = prefix_and_encode(dst->encoding()); | |
| 2278 emit_byte(0x58 | encode); | |
| 2279 } | |
| 2280 | |
|
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2281 void Assembler::popcntl(Register dst, Address src) { |
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2282 assert(VM_Version::supports_popcnt(), "must support"); |
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2283 InstructionMark im(this); |
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2284 emit_byte(0xF3); |
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2285 prefix(src, dst); |
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2286 emit_byte(0x0F); |
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2287 emit_byte(0xB8); |
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2288 emit_operand(dst, src); |
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2289 } |
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2290 |
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2291 void Assembler::popcntl(Register dst, Register src) { |
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2292 assert(VM_Version::supports_popcnt(), "must support"); |
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2293 emit_byte(0xF3); |
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2294 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2295 emit_byte(0x0F); |
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2296 emit_byte(0xB8); |
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|
2297 emit_byte(0xC0 | encode); |
|
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2298 } |
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2299 |
| 304 | 2300 void Assembler::popf() { |
| 2301 emit_byte(0x9D); | |
| 2302 } | |
| 2303 | |
| 1060 | 2304 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2305 void Assembler::popl(Address dst) { |
| 2306 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2307 InstructionMark im(this); | |
| 2308 prefix(dst); | |
| 2309 emit_byte(0x8F); | |
| 2310 emit_operand(rax, dst); | |
| 2311 } | |
| 1060 | 2312 #endif |
| 304 | 2313 |
| 2314 void Assembler::prefetch_prefix(Address src) { | |
| 2315 prefix(src); | |
| 2316 emit_byte(0x0F); | |
| 2317 } | |
| 2318 | |
| 2319 void Assembler::prefetchnta(Address src) { | |
|
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|
2320 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
| 304 | 2321 InstructionMark im(this); |
| 2322 prefetch_prefix(src); | |
| 2323 emit_byte(0x18); | |
| 2324 emit_operand(rax, src); // 0, src | |
| 2325 } | |
| 2326 | |
| 2327 void Assembler::prefetchr(Address src) { | |
| 3854 | 2328 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2329 InstructionMark im(this); |
| 2330 prefetch_prefix(src); | |
| 2331 emit_byte(0x0D); | |
| 2332 emit_operand(rax, src); // 0, src | |
| 2333 } | |
| 2334 | |
| 2335 void Assembler::prefetcht0(Address src) { | |
| 2336 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2337 InstructionMark im(this); | |
| 2338 prefetch_prefix(src); | |
| 2339 emit_byte(0x18); | |
| 2340 emit_operand(rcx, src); // 1, src | |
| 2341 } | |
| 2342 | |
| 2343 void Assembler::prefetcht1(Address src) { | |
| 2344 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2345 InstructionMark im(this); | |
| 2346 prefetch_prefix(src); | |
| 2347 emit_byte(0x18); | |
| 2348 emit_operand(rdx, src); // 2, src | |
| 2349 } | |
| 2350 | |
| 2351 void Assembler::prefetcht2(Address src) { | |
| 2352 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2353 InstructionMark im(this); | |
| 2354 prefetch_prefix(src); | |
| 2355 emit_byte(0x18); | |
| 2356 emit_operand(rbx, src); // 3, src | |
| 2357 } | |
| 2358 | |
| 2359 void Assembler::prefetchw(Address src) { | |
| 3854 | 2360 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2361 InstructionMark im(this); |
| 2362 prefetch_prefix(src); | |
| 2363 emit_byte(0x0D); | |
| 2364 emit_operand(rcx, src); // 1, src | |
| 2365 } | |
| 2366 | |
| 2367 void Assembler::prefix(Prefix p) { | |
| 2368 a_byte(p); | |
| 2369 } | |
| 2370 | |
| 6894 | 2371 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
| 2372 assert(VM_Version::supports_ssse3(), ""); | |
| 2373 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2374 emit_byte(0x00); | |
| 2375 emit_byte(0xC0 | encode); | |
| 2376 } | |
| 2377 | |
| 2378 void Assembler::pshufb(XMMRegister dst, Address src) { | |
| 2379 assert(VM_Version::supports_ssse3(), ""); | |
| 2380 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2381 InstructionMark im(this); | |
| 2382 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2383 emit_byte(0x00); | |
| 2384 emit_operand(dst, src); | |
| 2385 } | |
| 2386 | |
| 304 | 2387 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
| 2388 assert(isByte(mode), "invalid value"); | |
| 2389 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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2390 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
| 304 | 2391 emit_byte(mode & 0xFF); |
| 2392 | |
| 2393 } | |
| 2394 | |
| 2395 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2396 assert(isByte(mode), "invalid value"); | |
| 2397 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2398 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2399 InstructionMark im(this); | |
| 2400 simd_prefix(dst, src, VEX_SIMD_66); | |
| 304 | 2401 emit_byte(0x70); |
| 2402 emit_operand(dst, src); | |
| 2403 emit_byte(mode & 0xFF); | |
| 2404 } | |
| 2405 | |
| 2406 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2407 assert(isByte(mode), "invalid value"); | |
| 2408 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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2409 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
| 304 | 2410 emit_byte(mode & 0xFF); |
| 2411 } | |
| 2412 | |
| 2413 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2414 assert(isByte(mode), "invalid value"); | |
| 2415 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2416 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2417 InstructionMark im(this); | |
| 2418 simd_prefix(dst, src, VEX_SIMD_F2); | |
| 304 | 2419 emit_byte(0x70); |
| 2420 emit_operand(dst, src); | |
| 2421 emit_byte(mode & 0xFF); | |
| 2422 } | |
| 2423 | |
|
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2424 void Assembler::psrldq(XMMRegister dst, int shift) { |
|
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2425 // Shift 128 bit value in xmm register by number of bytes. |
|
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2426 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4759 | 2427 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
|
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2428 emit_byte(0x73); |
|
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2429 emit_byte(0xC0 | encode); |
|
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2430 emit_byte(shift); |
|
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|
2431 } |
|
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|
2432 |
| 681 | 2433 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2434 assert(VM_Version::supports_sse4_1(), ""); | |
| 4759 | 2435 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2436 InstructionMark im(this); | |
| 2437 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 681 | 2438 emit_byte(0x17); |
| 2439 emit_operand(dst, src); | |
| 2440 } | |
| 2441 | |
| 2442 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2443 assert(VM_Version::supports_sse4_1(), ""); | |
|
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2444 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
| 681 | 2445 emit_byte(0x17); |
| 2446 emit_byte(0xC0 | encode); | |
| 2447 } | |
| 2448 | |
| 4759 | 2449 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
| 2450 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2451 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
|
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|
2452 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
| 4759 | 2453 } |
| 2454 | |
| 304 | 2455 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2456 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2457 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
| 304 | 2458 } |
| 2459 | |
| 4759 | 2460 void Assembler::punpckldq(XMMRegister dst, Address src) { |
| 2461 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2462 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
|
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|
2463 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
| 4759 | 2464 } |
| 2465 | |
| 2466 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
| 2467 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2468 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
| 4759 | 2469 } |
| 2470 | |
| 6225 | 2471 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
| 2472 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2473 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
| 6225 | 2474 } |
| 2475 | |
| 304 | 2476 void Assembler::push(int32_t imm32) { |
| 2477 // in 64bits we push 64bits onto the stack but only | |
| 2478 // take a 32bit immediate | |
| 2479 emit_byte(0x68); | |
| 2480 emit_long(imm32); | |
| 2481 } | |
| 2482 | |
| 2483 void Assembler::push(Register src) { | |
| 2484 int encode = prefix_and_encode(src->encoding()); | |
| 2485 | |
| 2486 emit_byte(0x50 | encode); | |
| 2487 } | |
| 2488 | |
| 2489 void Assembler::pushf() { | |
| 2490 emit_byte(0x9C); | |
| 2491 } | |
| 2492 | |
| 1060 | 2493 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2494 void Assembler::pushl(Address src) { |
| 2495 // Note this will push 64bit on 64bit | |
| 2496 InstructionMark im(this); | |
| 2497 prefix(src); | |
| 2498 emit_byte(0xFF); | |
| 2499 emit_operand(rsi, src); | |
| 2500 } | |
| 1060 | 2501 #endif |
| 304 | 2502 |
| 2503 void Assembler::rcll(Register dst, int imm8) { | |
| 2504 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2505 int encode = prefix_and_encode(dst->encoding()); | |
| 2506 if (imm8 == 1) { | |
| 2507 emit_byte(0xD1); | |
| 2508 emit_byte(0xD0 | encode); | |
| 2509 } else { | |
| 2510 emit_byte(0xC1); | |
| 2511 emit_byte(0xD0 | encode); | |
| 2512 emit_byte(imm8); | |
| 2513 } | |
| 2514 } | |
| 2515 | |
| 2516 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2517 // generic | |
| 2518 void Assembler::rep_mov() { | |
| 2519 emit_byte(0xF3); | |
| 2520 // MOVSQ | |
| 2521 LP64_ONLY(prefix(REX_W)); | |
| 2522 emit_byte(0xA5); | |
| 2523 } | |
| 2524 | |
| 2525 // sets rcx pointer sized words with rax, value at [edi] | |
| 2526 // generic | |
| 2527 void Assembler::rep_set() { // rep_set | |
| 2528 emit_byte(0xF3); | |
| 2529 // STOSQ | |
| 2530 LP64_ONLY(prefix(REX_W)); | |
| 2531 emit_byte(0xAB); | |
| 2532 } | |
| 2533 | |
| 2534 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2535 // generic | |
| 2536 void Assembler::repne_scan() { // repne_scan | |
| 2537 emit_byte(0xF2); | |
| 2538 // SCASQ | |
| 2539 LP64_ONLY(prefix(REX_W)); | |
| 2540 emit_byte(0xAF); | |
| 2541 } | |
| 2542 | |
| 2543 #ifdef _LP64 | |
| 2544 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2545 // generic | |
| 2546 void Assembler::repne_scanl() { // repne_scan | |
| 2547 emit_byte(0xF2); | |
| 2548 // SCASL | |
| 2549 emit_byte(0xAF); | |
| 2550 } | |
| 2551 #endif | |
| 2552 | |
| 0 | 2553 void Assembler::ret(int imm16) { |
| 2554 if (imm16 == 0) { | |
| 2555 emit_byte(0xC3); | |
| 2556 } else { | |
| 2557 emit_byte(0xC2); | |
| 2558 emit_word(imm16); | |
| 2559 } | |
| 2560 } | |
| 2561 | |
| 304 | 2562 void Assembler::sahf() { |
| 2563 #ifdef _LP64 | |
| 2564 // Not supported in 64bit mode | |
| 2565 ShouldNotReachHere(); | |
| 2566 #endif | |
| 2567 emit_byte(0x9E); | |
| 2568 } | |
| 2569 | |
| 2570 void Assembler::sarl(Register dst, int imm8) { | |
| 2571 int encode = prefix_and_encode(dst->encoding()); | |
| 2572 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2573 if (imm8 == 1) { | |
| 2574 emit_byte(0xD1); | |
| 2575 emit_byte(0xF8 | encode); | |
| 2576 } else { | |
| 2577 emit_byte(0xC1); | |
| 2578 emit_byte(0xF8 | encode); | |
| 2579 emit_byte(imm8); | |
| 2580 } | |
| 2581 } | |
| 2582 | |
| 2583 void Assembler::sarl(Register dst) { | |
| 2584 int encode = prefix_and_encode(dst->encoding()); | |
| 2585 emit_byte(0xD3); | |
| 2586 emit_byte(0xF8 | encode); | |
| 2587 } | |
| 2588 | |
| 2589 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2590 InstructionMark im(this); | |
| 2591 prefix(dst); | |
| 2592 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2593 } | |
| 2594 | |
| 2595 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2596 prefix(dst); | |
| 2597 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2598 } | |
| 2599 | |
| 2600 | |
| 2601 void Assembler::sbbl(Register dst, Address src) { | |
| 2602 InstructionMark im(this); | |
| 2603 prefix(src, dst); | |
| 2604 emit_byte(0x1B); | |
| 2605 emit_operand(dst, src); | |
| 2606 } | |
| 2607 | |
| 2608 void Assembler::sbbl(Register dst, Register src) { | |
| 2609 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2610 emit_arith(0x1B, 0xC0, dst, src); | |
| 2611 } | |
| 2612 | |
| 2613 void Assembler::setb(Condition cc, Register dst) { | |
| 2614 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2615 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2616 emit_byte(0x0F); |
| 304 | 2617 emit_byte(0x90 | cc); |
| 2618 emit_byte(0xC0 | encode); | |
| 2619 } | |
| 2620 | |
| 2621 void Assembler::shll(Register dst, int imm8) { | |
| 2622 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2623 int encode = prefix_and_encode(dst->encoding()); | |
| 2624 if (imm8 == 1 ) { | |
| 2625 emit_byte(0xD1); | |
| 2626 emit_byte(0xE0 | encode); | |
| 2627 } else { | |
| 2628 emit_byte(0xC1); | |
| 2629 emit_byte(0xE0 | encode); | |
| 2630 emit_byte(imm8); | |
| 2631 } | |
| 2632 } | |
| 2633 | |
| 2634 void Assembler::shll(Register dst) { | |
| 2635 int encode = prefix_and_encode(dst->encoding()); | |
| 2636 emit_byte(0xD3); | |
| 2637 emit_byte(0xE0 | encode); | |
| 2638 } | |
| 2639 | |
| 2640 void Assembler::shrl(Register dst, int imm8) { | |
| 2641 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2642 int encode = prefix_and_encode(dst->encoding()); | |
| 2643 emit_byte(0xC1); | |
| 2644 emit_byte(0xE8 | encode); | |
| 2645 emit_byte(imm8); | |
| 2646 } | |
| 2647 | |
| 2648 void Assembler::shrl(Register dst) { | |
| 2649 int encode = prefix_and_encode(dst->encoding()); | |
| 2650 emit_byte(0xD3); | |
| 2651 emit_byte(0xE8 | encode); | |
| 2652 } | |
| 0 | 2653 |
| 2654 // copies a single word from [esi] to [edi] | |
| 2655 void Assembler::smovl() { | |
| 2656 emit_byte(0xA5); | |
| 2657 } | |
| 2658 | |
| 304 | 2659 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2660 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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2661 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
| 304 | 2662 } |
| 2663 | |
| 2008 | 2664 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2665 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2666 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
| 2008 | 2667 } |
| 2668 | |
| 2669 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 4759 | 2670 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
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2671 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
| 2008 | 2672 } |
| 2673 | |
| 2674 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
| 4759 | 2675 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
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2676 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
| 2008 | 2677 } |
| 2678 | |
| 304 | 2679 void Assembler::stmxcsr( Address dst) { |
| 2680 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2681 InstructionMark im(this); | |
| 2682 prefix(dst); | |
| 2683 emit_byte(0x0F); | |
| 2684 emit_byte(0xAE); | |
| 2685 emit_operand(as_Register(3), dst); | |
| 2686 } | |
| 2687 | |
| 2688 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2689 InstructionMark im(this); | |
| 2690 prefix(dst); | |
|
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2691 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2692 } |
| 2693 | |
| 2694 void Assembler::subl(Address dst, Register src) { | |
| 2695 InstructionMark im(this); | |
| 2696 prefix(dst, src); | |
| 2697 emit_byte(0x29); | |
| 2698 emit_operand(src, dst); | |
| 2699 } | |
| 2700 | |
|
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2701 void Assembler::subl(Register dst, int32_t imm32) { |
|
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2702 prefix(dst); |
|
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|
2703 emit_arith(0x81, 0xE8, dst, imm32); |
|
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|
2704 } |
|
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|
2705 |
|
4947
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changeset
|
2706 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
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|
2707 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
2708 prefix(dst); |
|
fd8114661503
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|
2709 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
2710 } |
|
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|
2711 |
| 304 | 2712 void Assembler::subl(Register dst, Address src) { |
| 2713 InstructionMark im(this); | |
| 2714 prefix(src, dst); | |
| 2715 emit_byte(0x2B); | |
| 2716 emit_operand(dst, src); | |
| 2717 } | |
| 2718 | |
| 2719 void Assembler::subl(Register dst, Register src) { | |
| 2720 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2721 emit_arith(0x2B, 0xC0, dst, src); | |
| 2722 } | |
| 2723 | |
| 2724 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2725 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2726 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
| 304 | 2727 } |
| 2728 | |
| 2729 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2730 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2731 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
| 304 | 2732 } |
| 2733 | |
| 2734 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2735 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2736 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
| 304 | 2737 } |
| 2738 | |
| 2739 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2740 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2741 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
| 304 | 2742 } |
| 2743 | |
| 2744 void Assembler::testb(Register dst, int imm8) { | |
| 2745 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2746 (void) prefix_and_encode(dst->encoding(), true); | |
| 2747 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2748 } | |
| 2749 | |
| 2750 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2751 // not using emit_arith because test | |
| 2752 // doesn't support sign-extension of | |
| 2753 // 8bit operands | |
| 2754 int encode = dst->encoding(); | |
| 2755 if (encode == 0) { | |
| 2756 emit_byte(0xA9); | |
| 2757 } else { | |
| 2758 encode = prefix_and_encode(encode); | |
| 2759 emit_byte(0xF7); | |
| 2760 emit_byte(0xC0 | encode); | |
| 2761 } | |
| 2762 emit_long(imm32); | |
| 2763 } | |
| 2764 | |
| 2765 void Assembler::testl(Register dst, Register src) { | |
| 2766 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2767 emit_arith(0x85, 0xC0, dst, src); | |
| 2768 } | |
| 2769 | |
| 2770 void Assembler::testl(Register dst, Address src) { | |
| 2771 InstructionMark im(this); | |
| 2772 prefix(src, dst); | |
| 2773 emit_byte(0x85); | |
| 2774 emit_operand(dst, src); | |
| 2775 } | |
| 2776 | |
| 2777 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2778 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2779 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
| 304 | 2780 } |
| 2781 | |
| 2782 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2784 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
| 304 | 2785 } |
| 2786 | |
| 2787 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2788 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2789 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
| 304 | 2790 } |
| 2791 | |
| 2792 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2793 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2794 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
| 304 | 2795 } |
| 2796 | |
| 2797 | |
| 2798 void Assembler::xaddl(Address dst, Register src) { | |
| 2799 InstructionMark im(this); | |
| 2800 prefix(dst, src); | |
| 0 | 2801 emit_byte(0x0F); |
| 304 | 2802 emit_byte(0xC1); |
| 2803 emit_operand(src, dst); | |
| 2804 } | |
| 2805 | |
| 2806 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2807 InstructionMark im(this); | |
| 2808 prefix(src, dst); | |
| 2809 emit_byte(0x87); | |
| 2810 emit_operand(dst, src); | |
| 2811 } | |
| 2812 | |
| 2813 void Assembler::xchgl(Register dst, Register src) { | |
| 2814 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2815 emit_byte(0x87); | |
| 2816 emit_byte(0xc0 | encode); | |
| 2817 } | |
| 2818 | |
| 2819 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2820 prefix(dst); | |
| 2821 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2822 } | |
| 2823 | |
| 2824 void Assembler::xorl(Register dst, Address src) { | |
| 2825 InstructionMark im(this); | |
| 2826 prefix(src, dst); | |
| 2827 emit_byte(0x33); | |
| 2828 emit_operand(dst, src); | |
| 2829 } | |
| 2830 | |
| 2831 void Assembler::xorl(Register dst, Register src) { | |
| 2832 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2833 emit_arith(0x33, 0xC0, dst, src); | |
| 2834 } | |
| 2835 | |
|
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|
2836 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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|
2837 // AVX 3-operands scalar float-point arithmetic instructions |
|
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2838 |
|
65149e74c706
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|
2839 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2840 assert(VM_Version::supports_avx(), ""); |
|
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|
2841 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
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|
2842 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2843 |
|
65149e74c706
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|
2844 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2845 assert(VM_Version::supports_avx(), ""); |
|
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|
2846 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
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|
2847 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2848 |
|
65149e74c706
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|
2849 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2850 assert(VM_Version::supports_avx(), ""); |
|
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|
2851 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
65149e74c706
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|
2852 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2853 |
|
65149e74c706
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|
2854 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2855 assert(VM_Version::supports_avx(), ""); |
|
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|
2856 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
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|
2857 } |
|
65149e74c706
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|
2858 |
|
65149e74c706
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|
2859 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2860 assert(VM_Version::supports_avx(), ""); |
|
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|
2861 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
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|
2862 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2863 |
|
65149e74c706
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|
2864 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2865 assert(VM_Version::supports_avx(), ""); |
|
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|
2866 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
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|
2867 } |
|
65149e74c706
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|
2868 |
|
65149e74c706
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|
2869 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2870 assert(VM_Version::supports_avx(), ""); |
|
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|
2871 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
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|
2872 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2873 |
|
65149e74c706
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|
2874 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2875 assert(VM_Version::supports_avx(), ""); |
|
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|
2876 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
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|
2877 } |
|
65149e74c706
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|
2878 |
|
65149e74c706
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|
2879 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
2880 assert(VM_Version::supports_avx(), ""); |
|
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|
2881 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
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|
2882 } |
|
65149e74c706
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|
2883 |
|
65149e74c706
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|
2884 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2885 assert(VM_Version::supports_avx(), ""); |
|
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|
2886 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
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|
2887 } |
|
65149e74c706
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|
2888 |
|
65149e74c706
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|
2889 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
|
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|
2890 assert(VM_Version::supports_avx(), ""); |
|
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|
2891 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
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|
2892 } |
|
65149e74c706
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|
2893 |
|
65149e74c706
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|
2894 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2895 assert(VM_Version::supports_avx(), ""); |
|
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|
2896 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
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|
2897 } |
|
4761
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|
2898 |
|
65149e74c706
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|
2899 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
2900 assert(VM_Version::supports_avx(), ""); |
|
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|
2901 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
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|
2902 } |
|
65149e74c706
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|
2903 |
|
65149e74c706
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|
2904 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2905 assert(VM_Version::supports_avx(), ""); |
|
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changeset
|
2906 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2907 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2908 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2909 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2910 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2911 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2912 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2913 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2914 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2915 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2916 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2917 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2918 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2919 //====================VECTOR ARITHMETIC===================================== |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2920 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2921 // Float-point vector arithmetic |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2922 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2923 void Assembler::addpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2924 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2925 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2926 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2927 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2928 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2930 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2931 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2932 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2933 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2934 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2935 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2936 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2937 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2938 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2939 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2940 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2941 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2942 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2943 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2944 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2945 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2946 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2947 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2948 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2949 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2950 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2951 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2952 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2953 void Assembler::subpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2954 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2955 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2956 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2957 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2958 void Assembler::subps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2959 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2960 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2961 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2962 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2963 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2964 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2965 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2966 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2967 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2968 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2969 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2970 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2971 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2972 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2973 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2974 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2975 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2976 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2977 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2978 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2979 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2980 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2981 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2982 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2983 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2984 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2985 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2986 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2987 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2988 void Assembler::mulps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2989 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2990 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2991 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2992 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2993 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2994 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2995 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2996 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2997 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2998 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2999 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3000 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3001 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3002 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3003 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3004 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3005 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3006 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3007 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3008 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3009 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3010 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3011 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3012 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3013 void Assembler::divpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3014 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3015 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3016 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3017 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3018 void Assembler::divps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3019 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3020 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3021 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3022 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3023 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3024 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3025 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3026 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3027 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3028 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3029 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3030 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3031 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3032 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3033 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3034 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3035 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3036 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3037 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3038 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3039 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3040 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3041 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3042 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3043 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3044 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3045 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3046 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3047 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3048 void Assembler::andps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3049 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3050 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3051 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3052 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3053 void Assembler::andps(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3054 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3055 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3056 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3057 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3058 void Assembler::andpd(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3059 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3060 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3061 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3062 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3063 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3064 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3065 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3066 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3067 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3068 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3069 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3070 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3071 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3072 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3073 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3074 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3075 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3076 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3077 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3078 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3079 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3080 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3081 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3082 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3083 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3084 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3085 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3086 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3087 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3088 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3089 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3090 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3091 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3092 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3093 void Assembler::xorpd(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3094 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3095 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3096 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3097 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3098 void Assembler::xorps(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3099 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3100 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3101 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3102 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3103 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3104 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3105 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3106 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3107 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3108 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3109 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3110 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3111 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3112 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3113 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3114 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3115 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3116 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3117 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3118 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3119 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3120 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3121 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3122 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3123 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3124 // Integer vector arithmetic |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3125 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3126 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3127 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3128 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3129 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3130 void Assembler::paddw(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3131 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3132 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3133 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3134 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3135 void Assembler::paddd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3136 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3137 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3138 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3139 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3140 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3141 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3142 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3143 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3144 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3145 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3146 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3147 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3148 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3149 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3150 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3151 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3152 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3153 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3154 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3155 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3156 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3157 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3158 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3159 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3160 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3161 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3162 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3163 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3164 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3165 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3166 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3167 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3168 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3169 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3170 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3171 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3172 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3173 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3174 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3175 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3176 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3177 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3178 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3179 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3180 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3181 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3182 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3183 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3184 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3185 void Assembler::psubb(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3186 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3187 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3188 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3189 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3190 void Assembler::psubw(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3191 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3192 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3193 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3194 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3195 void Assembler::psubd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3196 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3197 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3198 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3199 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3200 void Assembler::psubq(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3202 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3203 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3204 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3205 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3206 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3207 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3208 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3209 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3210 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3211 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3212 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3213 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3214 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3215 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3216 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3217 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3218 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3219 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3220 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3221 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3222 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3223 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3224 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3225 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3226 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3227 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3228 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3229 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3230 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3231 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3232 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3233 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3234 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3235 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3236 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3237 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3238 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3239 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3240 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3241 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3242 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3243 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3244 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3245 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3246 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3247 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3248 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3249 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3250 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3251 assert(VM_Version::supports_sse4_1(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3252 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3253 emit_byte(0x40); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3254 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3255 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3256 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3257 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3258 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3259 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3260 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3261 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3262 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3263 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3264 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3265 emit_byte(0x40); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3266 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3267 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3268 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3269 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3270 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3271 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3272 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3273 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3274 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3275 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3276 InstructionMark im(this); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3277 int dst_enc = dst->encoding(); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3278 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3279 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3280 emit_byte(0x40); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3281 emit_operand(dst, src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3282 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3283 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3284 // Shift packed integers left by specified number of bits. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3285 void Assembler::psllw(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3286 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3287 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3288 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3289 emit_byte(0x71); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3290 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3291 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3292 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3293 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3294 void Assembler::pslld(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3295 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3296 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3297 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3298 emit_byte(0x72); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3299 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3300 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3301 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3302 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3303 void Assembler::psllq(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3304 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3305 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3306 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3307 emit_byte(0x73); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3308 emit_byte(0xC0 | encode); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3309 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3310 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3311 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3312 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3313 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3314 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3315 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3316 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3317 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3318 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3319 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3320 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3321 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3322 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3323 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3324 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3325 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3326 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3327 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3328 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3329 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3330 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3331 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3332 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3333 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3334 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3335 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3336 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3337 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3338 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3339 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3340 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3341 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3342 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3343 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3344 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3345 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3346 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3347 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3348 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3349 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3350 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3351 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3352 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3353 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3354 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3355 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3356 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3357 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3358 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3359 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3360 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3361 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3362 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3363 // Shift packed integers logically right by specified number of bits. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3364 void Assembler::psrlw(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3365 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3366 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3367 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3368 emit_byte(0x71); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3369 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3370 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3371 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3372 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3373 void Assembler::psrld(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3375 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3376 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3377 emit_byte(0x72); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3378 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3379 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3380 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3381 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3382 void Assembler::psrlq(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3383 // Do not confuse it with psrldq SSE2 instruction which |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3384 // shifts 128 bit value in xmm register by number of bytes. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3385 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3386 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3387 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3388 emit_byte(0x73); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3389 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3390 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3391 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3392 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3393 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3394 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3395 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3396 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3397 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3398 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3399 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3400 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3401 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3402 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3403 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3404 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3405 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3406 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3407 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3408 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3409 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3410 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3411 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3412 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3413 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3414 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3415 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3416 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3417 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3418 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3419 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3420 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3421 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3422 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3423 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3424 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3425 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3426 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3427 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3428 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3429 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3430 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3431 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3432 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3433 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3434 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3435 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3436 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3437 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3438 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3439 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3440 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3441 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3442 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3443 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3444 // Shift packed integers arithmetically right by specified number of bits. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3445 void Assembler::psraw(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3446 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3447 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3448 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3449 emit_byte(0x71); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3450 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3451 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3452 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3453 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3454 void Assembler::psrad(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3455 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3456 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3457 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3458 emit_byte(0x72); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3459 emit_byte(0xC0 | encode); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3460 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3461 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3462 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3463 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3464 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3465 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3466 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3467 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3468 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3469 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3470 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3471 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3472 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3473 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3474 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3475 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3476 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3477 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3478 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3479 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3480 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3481 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3482 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3483 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3484 emit_byte(shift & 0xFF); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3485 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3486 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3487 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3488 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3489 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3490 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3491 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3492 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3493 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3494 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3495 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3496 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3497 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3498 // AND packed integers |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3499 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3500 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3501 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3502 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3503 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3504 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3505 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3506 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3507 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3508 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3509 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3510 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3511 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3512 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3513 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3514 void Assembler::por(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3515 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3516 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3517 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3518 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3519 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3520 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3521 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3522 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3523 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3524 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3525 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3526 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3527 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3528 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3529 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3530 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3531 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3532 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3533 |
| 6225 | 3534 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3535 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3536 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3537 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3538 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3539 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3540 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3541 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3542 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3543 |
| 6225 | 3544 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3545 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3546 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3547 bool vector256 = true; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3548 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3549 emit_byte(0x18); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3550 emit_byte(0xC0 | encode); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3551 // 0x00 - insert into lower 128 bits |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3552 // 0x01 - insert into upper 128 bits |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3553 emit_byte(0x01); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3554 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3555 |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3556 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3557 assert(VM_Version::supports_avx(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3558 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3559 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3560 assert(dst != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3561 int dst_enc = dst->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3562 // swap src<->dst for encoding |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3563 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3564 emit_byte(0x18); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3565 emit_operand(dst, src); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3566 // 0x01 - insert into upper 128 bits |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3567 emit_byte(0x01); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3568 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3569 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3570 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3571 assert(VM_Version::supports_avx(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3572 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3573 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3574 assert(src != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3575 int src_enc = src->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3576 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3577 emit_byte(0x19); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3578 emit_operand(src, dst); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3579 // 0x01 - extract from upper 128 bits |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3580 emit_byte(0x01); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3581 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3582 |
| 6225 | 3583 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
| 3584 assert(VM_Version::supports_avx2(), ""); | |
| 3585 bool vector256 = true; | |
| 3586 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
| 3587 emit_byte(0x38); | |
| 3588 emit_byte(0xC0 | encode); | |
| 3589 // 0x00 - insert into lower 128 bits | |
| 3590 // 0x01 - insert into upper 128 bits | |
| 3591 emit_byte(0x01); | |
| 3592 } | |
| 3593 | |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3594 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3595 assert(VM_Version::supports_avx2(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3596 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3597 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3598 assert(dst != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3599 int dst_enc = dst->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3600 // swap src<->dst for encoding |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3601 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3602 emit_byte(0x38); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3603 emit_operand(dst, src); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3604 // 0x01 - insert into upper 128 bits |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3605 emit_byte(0x01); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3606 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3607 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3608 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3609 assert(VM_Version::supports_avx2(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3610 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3611 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3612 assert(src != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3613 int src_enc = src->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3614 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3615 emit_byte(0x39); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3616 emit_operand(src, dst); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3617 // 0x01 - extract from upper 128 bits |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3618 emit_byte(0x01); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3619 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3620 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3621 void Assembler::vzeroupper() { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3622 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3623 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3624 emit_byte(0x77); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3625 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3626 |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3627 |
| 304 | 3628 #ifndef _LP64 |
| 3629 // 32bit only pieces of the assembler | |
| 3630 | |
| 3631 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 3632 // NO PREFIX AS NEVER 64BIT | |
| 3633 InstructionMark im(this); | |
| 3634 emit_byte(0x81); | |
| 3635 emit_byte(0xF8 | src1->encoding()); | |
| 3636 emit_data(imm32, rspec, 0); | |
| 3637 } | |
| 3638 | |
| 3639 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 3640 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 3641 InstructionMark im(this); | |
| 3642 emit_byte(0x81); | |
| 3643 emit_operand(rdi, src1); | |
| 3644 emit_data(imm32, rspec, 0); | |
| 3645 } | |
| 3646 | |
| 3647 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 3648 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 3649 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 3650 void Assembler::cmpxchg8(Address adr) { | |
| 3651 InstructionMark im(this); | |
| 3652 emit_byte(0x0F); | |
| 3653 emit_byte(0xc7); | |
| 3654 emit_operand(rcx, adr); | |
| 3655 } | |
| 3656 | |
| 3657 void Assembler::decl(Register dst) { | |
| 3658 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 3659 emit_byte(0x48 | dst->encoding()); | |
| 3660 } | |
| 3661 | |
| 3662 #endif // _LP64 | |
| 3663 | |
| 3664 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 3665 | |
| 3666 void Assembler::fabs() { | |
| 3667 emit_byte(0xD9); | |
| 3668 emit_byte(0xE1); | |
| 3669 } | |
| 3670 | |
| 3671 void Assembler::fadd(int i) { | |
| 3672 emit_farith(0xD8, 0xC0, i); | |
| 3673 } | |
| 3674 | |
| 3675 void Assembler::fadd_d(Address src) { | |
| 3676 InstructionMark im(this); | |
| 3677 emit_byte(0xDC); | |
| 3678 emit_operand32(rax, src); | |
| 3679 } | |
| 3680 | |
| 3681 void Assembler::fadd_s(Address src) { | |
| 3682 InstructionMark im(this); | |
| 3683 emit_byte(0xD8); | |
| 3684 emit_operand32(rax, src); | |
| 3685 } | |
| 3686 | |
| 3687 void Assembler::fadda(int i) { | |
| 3688 emit_farith(0xDC, 0xC0, i); | |
| 3689 } | |
| 3690 | |
| 3691 void Assembler::faddp(int i) { | |
| 3692 emit_farith(0xDE, 0xC0, i); | |
| 3693 } | |
| 3694 | |
| 3695 void Assembler::fchs() { | |
| 3696 emit_byte(0xD9); | |
| 3697 emit_byte(0xE0); | |
| 3698 } | |
| 3699 | |
| 3700 void Assembler::fcom(int i) { | |
| 3701 emit_farith(0xD8, 0xD0, i); | |
| 3702 } | |
| 3703 | |
| 3704 void Assembler::fcomp(int i) { | |
| 3705 emit_farith(0xD8, 0xD8, i); | |
| 3706 } | |
| 3707 | |
| 3708 void Assembler::fcomp_d(Address src) { | |
| 3709 InstructionMark im(this); | |
| 3710 emit_byte(0xDC); | |
| 3711 emit_operand32(rbx, src); | |
| 3712 } | |
| 3713 | |
| 3714 void Assembler::fcomp_s(Address src) { | |
| 3715 InstructionMark im(this); | |
| 3716 emit_byte(0xD8); | |
| 3717 emit_operand32(rbx, src); | |
| 3718 } | |
| 3719 | |
| 3720 void Assembler::fcompp() { | |
| 3721 emit_byte(0xDE); | |
| 3722 emit_byte(0xD9); | |
| 3723 } | |
| 3724 | |
| 3725 void Assembler::fcos() { | |
| 3726 emit_byte(0xD9); | |
| 0 | 3727 emit_byte(0xFF); |
| 304 | 3728 } |
| 3729 | |
| 3730 void Assembler::fdecstp() { | |
| 3731 emit_byte(0xD9); | |
| 3732 emit_byte(0xF6); | |
| 3733 } | |
| 3734 | |
| 3735 void Assembler::fdiv(int i) { | |
| 3736 emit_farith(0xD8, 0xF0, i); | |
| 3737 } | |
| 3738 | |
| 3739 void Assembler::fdiv_d(Address src) { | |
| 3740 InstructionMark im(this); | |
| 3741 emit_byte(0xDC); | |
| 3742 emit_operand32(rsi, src); | |
| 3743 } | |
| 3744 | |
| 3745 void Assembler::fdiv_s(Address src) { | |
| 3746 InstructionMark im(this); | |
| 3747 emit_byte(0xD8); | |
| 3748 emit_operand32(rsi, src); | |
| 3749 } | |
| 3750 | |
| 3751 void Assembler::fdiva(int i) { | |
| 3752 emit_farith(0xDC, 0xF8, i); | |
| 3753 } | |
| 3754 | |
| 3755 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3756 // is erroneous for some of the floating-point instructions below. | |
| 3757 | |
| 3758 void Assembler::fdivp(int i) { | |
| 3759 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3760 } | |
| 3761 | |
| 3762 void Assembler::fdivr(int i) { | |
| 3763 emit_farith(0xD8, 0xF8, i); | |
| 3764 } | |
| 3765 | |
| 3766 void Assembler::fdivr_d(Address src) { | |
| 3767 InstructionMark im(this); | |
| 3768 emit_byte(0xDC); | |
| 3769 emit_operand32(rdi, src); | |
| 3770 } | |
| 3771 | |
| 3772 void Assembler::fdivr_s(Address src) { | |
| 3773 InstructionMark im(this); | |
| 3774 emit_byte(0xD8); | |
| 3775 emit_operand32(rdi, src); | |
| 3776 } | |
| 3777 | |
| 3778 void Assembler::fdivra(int i) { | |
| 3779 emit_farith(0xDC, 0xF0, i); | |
| 3780 } | |
| 3781 | |
| 3782 void Assembler::fdivrp(int i) { | |
| 3783 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3784 } | |
| 3785 | |
| 3786 void Assembler::ffree(int i) { | |
| 3787 emit_farith(0xDD, 0xC0, i); | |
| 3788 } | |
| 3789 | |
| 3790 void Assembler::fild_d(Address adr) { | |
| 3791 InstructionMark im(this); | |
| 3792 emit_byte(0xDF); | |
| 3793 emit_operand32(rbp, adr); | |
| 3794 } | |
| 3795 | |
| 3796 void Assembler::fild_s(Address adr) { | |
| 3797 InstructionMark im(this); | |
| 3798 emit_byte(0xDB); | |
| 3799 emit_operand32(rax, adr); | |
| 3800 } | |
| 3801 | |
| 3802 void Assembler::fincstp() { | |
| 3803 emit_byte(0xD9); | |
| 3804 emit_byte(0xF7); | |
| 3805 } | |
| 3806 | |
| 3807 void Assembler::finit() { | |
| 3808 emit_byte(0x9B); | |
| 3809 emit_byte(0xDB); | |
| 3810 emit_byte(0xE3); | |
| 3811 } | |
| 3812 | |
| 3813 void Assembler::fist_s(Address adr) { | |
| 3814 InstructionMark im(this); | |
| 3815 emit_byte(0xDB); | |
| 3816 emit_operand32(rdx, adr); | |
| 3817 } | |
| 3818 | |
| 3819 void Assembler::fistp_d(Address adr) { | |
| 3820 InstructionMark im(this); | |
| 3821 emit_byte(0xDF); | |
| 3822 emit_operand32(rdi, adr); | |
| 3823 } | |
| 3824 | |
| 3825 void Assembler::fistp_s(Address adr) { | |
| 3826 InstructionMark im(this); | |
| 3827 emit_byte(0xDB); | |
| 3828 emit_operand32(rbx, adr); | |
| 3829 } | |
| 0 | 3830 |
| 3831 void Assembler::fld1() { | |
| 3832 emit_byte(0xD9); | |
| 3833 emit_byte(0xE8); | |
| 3834 } | |
| 3835 | |
| 304 | 3836 void Assembler::fld_d(Address adr) { |
| 3837 InstructionMark im(this); | |
| 3838 emit_byte(0xDD); | |
| 3839 emit_operand32(rax, adr); | |
| 3840 } | |
| 0 | 3841 |
| 3842 void Assembler::fld_s(Address adr) { | |
| 3843 InstructionMark im(this); | |
| 3844 emit_byte(0xD9); | |
| 304 | 3845 emit_operand32(rax, adr); |
| 3846 } | |
| 3847 | |
| 3848 | |
| 3849 void Assembler::fld_s(int index) { | |
| 0 | 3850 emit_farith(0xD9, 0xC0, index); |
| 3851 } | |
| 3852 | |
| 3853 void Assembler::fld_x(Address adr) { | |
| 3854 InstructionMark im(this); | |
| 3855 emit_byte(0xDB); | |
| 304 | 3856 emit_operand32(rbp, adr); |
| 3857 } | |
| 3858 | |
| 3859 void Assembler::fldcw(Address src) { | |
| 3860 InstructionMark im(this); | |
| 3861 emit_byte(0xd9); | |
| 3862 emit_operand32(rbp, src); | |
| 3863 } | |
| 3864 | |
| 3865 void Assembler::fldenv(Address src) { | |
| 0 | 3866 InstructionMark im(this); |
| 3867 emit_byte(0xD9); | |
| 304 | 3868 emit_operand32(rsp, src); |
| 3869 } | |
| 3870 | |
| 3871 void Assembler::fldlg2() { | |
| 0 | 3872 emit_byte(0xD9); |
| 304 | 3873 emit_byte(0xEC); |
| 3874 } | |
| 0 | 3875 |
| 3876 void Assembler::fldln2() { | |
| 3877 emit_byte(0xD9); | |
| 3878 emit_byte(0xED); | |
| 3879 } | |
| 3880 | |
| 304 | 3881 void Assembler::fldz() { |
| 0 | 3882 emit_byte(0xD9); |
| 304 | 3883 emit_byte(0xEE); |
| 3884 } | |
| 0 | 3885 |
| 3886 void Assembler::flog() { | |
| 3887 fldln2(); | |
| 3888 fxch(); | |
| 3889 fyl2x(); | |
| 3890 } | |
| 3891 | |
| 3892 void Assembler::flog10() { | |
| 3893 fldlg2(); | |
| 3894 fxch(); | |
| 3895 fyl2x(); | |
| 3896 } | |
| 3897 | |
| 304 | 3898 void Assembler::fmul(int i) { |
| 3899 emit_farith(0xD8, 0xC8, i); | |
| 3900 } | |
| 3901 | |
| 3902 void Assembler::fmul_d(Address src) { | |
| 3903 InstructionMark im(this); | |
| 3904 emit_byte(0xDC); | |
| 3905 emit_operand32(rcx, src); | |
| 3906 } | |
| 3907 | |
| 3908 void Assembler::fmul_s(Address src) { | |
| 3909 InstructionMark im(this); | |
| 3910 emit_byte(0xD8); | |
| 3911 emit_operand32(rcx, src); | |
| 3912 } | |
| 3913 | |
| 3914 void Assembler::fmula(int i) { | |
| 3915 emit_farith(0xDC, 0xC8, i); | |
| 3916 } | |
| 3917 | |
| 3918 void Assembler::fmulp(int i) { | |
| 3919 emit_farith(0xDE, 0xC8, i); | |
| 3920 } | |
| 3921 | |
| 3922 void Assembler::fnsave(Address dst) { | |
| 3923 InstructionMark im(this); | |
| 3924 emit_byte(0xDD); | |
| 3925 emit_operand32(rsi, dst); | |
| 3926 } | |
| 3927 | |
| 3928 void Assembler::fnstcw(Address src) { | |
| 3929 InstructionMark im(this); | |
| 3930 emit_byte(0x9B); | |
| 3931 emit_byte(0xD9); | |
| 3932 emit_operand32(rdi, src); | |
| 3933 } | |
| 3934 | |
| 3935 void Assembler::fnstsw_ax() { | |
| 3936 emit_byte(0xdF); | |
| 3937 emit_byte(0xE0); | |
| 3938 } | |
| 3939 | |
| 3940 void Assembler::fprem() { | |
| 3941 emit_byte(0xD9); | |
| 3942 emit_byte(0xF8); | |
| 3943 } | |
| 3944 | |
| 3945 void Assembler::fprem1() { | |
| 3946 emit_byte(0xD9); | |
| 3947 emit_byte(0xF5); | |
| 3948 } | |
| 3949 | |
| 3950 void Assembler::frstor(Address src) { | |
| 3951 InstructionMark im(this); | |
| 3952 emit_byte(0xDD); | |
| 3953 emit_operand32(rsp, src); | |
| 3954 } | |
| 0 | 3955 |
| 3956 void Assembler::fsin() { | |
| 3957 emit_byte(0xD9); | |
| 3958 emit_byte(0xFE); | |
| 3959 } | |
| 3960 | |
| 304 | 3961 void Assembler::fsqrt() { |
| 3962 emit_byte(0xD9); | |
| 3963 emit_byte(0xFA); | |
| 3964 } | |
| 3965 | |
| 3966 void Assembler::fst_d(Address adr) { | |
| 3967 InstructionMark im(this); | |
| 3968 emit_byte(0xDD); | |
| 3969 emit_operand32(rdx, adr); | |
| 3970 } | |
| 3971 | |
| 3972 void Assembler::fst_s(Address adr) { | |
| 3973 InstructionMark im(this); | |
| 3974 emit_byte(0xD9); | |
| 3975 emit_operand32(rdx, adr); | |
| 3976 } | |
| 3977 | |
| 3978 void Assembler::fstp_d(Address adr) { | |
| 3979 InstructionMark im(this); | |
| 3980 emit_byte(0xDD); | |
| 3981 emit_operand32(rbx, adr); | |
| 3982 } | |
| 3983 | |
| 3984 void Assembler::fstp_d(int index) { | |
| 3985 emit_farith(0xDD, 0xD8, index); | |
| 3986 } | |
| 3987 | |
| 3988 void Assembler::fstp_s(Address adr) { | |
| 3989 InstructionMark im(this); | |
| 0 | 3990 emit_byte(0xD9); |
| 304 | 3991 emit_operand32(rbx, adr); |
| 3992 } | |
| 3993 | |
| 3994 void Assembler::fstp_x(Address adr) { | |
| 3995 InstructionMark im(this); | |
| 3996 emit_byte(0xDB); | |
| 3997 emit_operand32(rdi, adr); | |
| 3998 } | |
| 3999 | |
| 4000 void Assembler::fsub(int i) { | |
| 4001 emit_farith(0xD8, 0xE0, i); | |
| 4002 } | |
| 4003 | |
| 4004 void Assembler::fsub_d(Address src) { | |
| 4005 InstructionMark im(this); | |
| 4006 emit_byte(0xDC); | |
| 4007 emit_operand32(rsp, src); | |
| 4008 } | |
| 4009 | |
| 4010 void Assembler::fsub_s(Address src) { | |
| 4011 InstructionMark im(this); | |
| 4012 emit_byte(0xD8); | |
| 4013 emit_operand32(rsp, src); | |
| 4014 } | |
| 4015 | |
| 4016 void Assembler::fsuba(int i) { | |
| 4017 emit_farith(0xDC, 0xE8, i); | |
| 4018 } | |
| 4019 | |
| 4020 void Assembler::fsubp(int i) { | |
| 4021 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 4022 } | |
| 4023 | |
| 4024 void Assembler::fsubr(int i) { | |
| 4025 emit_farith(0xD8, 0xE8, i); | |
| 4026 } | |
| 4027 | |
| 4028 void Assembler::fsubr_d(Address src) { | |
| 4029 InstructionMark im(this); | |
| 4030 emit_byte(0xDC); | |
| 4031 emit_operand32(rbp, src); | |
| 4032 } | |
| 4033 | |
| 4034 void Assembler::fsubr_s(Address src) { | |
| 4035 InstructionMark im(this); | |
| 4036 emit_byte(0xD8); | |
| 4037 emit_operand32(rbp, src); | |
| 4038 } | |
| 4039 | |
| 4040 void Assembler::fsubra(int i) { | |
| 4041 emit_farith(0xDC, 0xE0, i); | |
| 4042 } | |
| 4043 | |
| 4044 void Assembler::fsubrp(int i) { | |
| 4045 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 4046 } |
| 4047 | |
| 4048 void Assembler::ftan() { | |
| 4049 emit_byte(0xD9); | |
| 4050 emit_byte(0xF2); | |
| 4051 emit_byte(0xDD); | |
| 4052 emit_byte(0xD8); | |
| 4053 } | |
| 4054 | |
| 304 | 4055 void Assembler::ftst() { |
| 0 | 4056 emit_byte(0xD9); |
| 304 | 4057 emit_byte(0xE4); |
| 4058 } | |
| 0 | 4059 |
| 4060 void Assembler::fucomi(int i) { | |
| 4061 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 4062 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 4063 emit_farith(0xDB, 0xE8, i); | |
| 4064 } | |
| 4065 | |
| 4066 void Assembler::fucomip(int i) { | |
| 4067 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 4068 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 4069 emit_farith(0xDF, 0xE8, i); | |
| 4070 } | |
| 4071 | |
| 4072 void Assembler::fwait() { | |
| 4073 emit_byte(0x9B); | |
| 4074 } | |
| 4075 | |
| 304 | 4076 void Assembler::fxch(int i) { |
| 4077 emit_farith(0xD9, 0xC8, i); | |
| 4078 } | |
| 4079 | |
| 4080 void Assembler::fyl2x() { | |
| 0 | 4081 emit_byte(0xD9); |
| 304 | 4082 emit_byte(0xF1); |
| 4083 } | |
| 4084 | |
|
6084
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4085 void Assembler::frndint() { |
|
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|
4086 emit_byte(0xD9); |
|
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|
4087 emit_byte(0xFC); |
|
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|
4088 } |
|
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|
4089 |
|
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|
4090 void Assembler::f2xm1() { |
|
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|
4091 emit_byte(0xD9); |
|
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|
4092 emit_byte(0xF0); |
|
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|
4093 } |
|
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|
4094 |
|
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|
4095 void Assembler::fldl2e() { |
|
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|
4096 emit_byte(0xD9); |
|
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|
4097 emit_byte(0xEA); |
|
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|
4098 } |
|
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|
4099 |
| 4759 | 4100 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
| 4101 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
| 4102 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
| 4103 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
| 4104 | |
| 4105 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
| 4106 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 4107 if (pre > 0) { | |
| 4108 emit_byte(simd_pre[pre]); | |
| 4109 } | |
| 4110 if (rex_w) { | |
| 4111 prefixq(adr, xreg); | |
| 4112 } else { | |
| 4113 prefix(adr, xreg); | |
| 4114 } | |
| 4115 if (opc > 0) { | |
| 4116 emit_byte(0x0F); | |
| 4117 int opc2 = simd_opc[opc]; | |
| 4118 if (opc2 > 0) { | |
| 4119 emit_byte(opc2); | |
| 4120 } | |
| 4121 } | |
| 4122 } | |
| 4123 | |
| 4124 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 4125 if (pre > 0) { | |
| 4126 emit_byte(simd_pre[pre]); | |
| 4127 } | |
| 4128 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
| 4129 prefix_and_encode(dst_enc, src_enc); | |
| 4130 if (opc > 0) { | |
| 4131 emit_byte(0x0F); | |
| 4132 int opc2 = simd_opc[opc]; | |
| 4133 if (opc2 > 0) { | |
| 4134 emit_byte(opc2); | |
| 4135 } | |
| 4136 } | |
| 4137 return encode; | |
| 4138 } | |
| 4139 | |
| 4140 | |
| 4141 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
| 4142 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
| 4143 prefix(VEX_3bytes); | |
| 4144 | |
| 4145 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
| 4146 byte1 = (~byte1) & 0xE0; | |
| 4147 byte1 |= opc; | |
| 4148 a_byte(byte1); | |
| 4149 | |
| 4150 int byte2 = ((~nds_enc) & 0xf) << 3; | |
| 4151 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
| 4152 emit_byte(byte2); | |
| 4153 } else { | |
| 4154 prefix(VEX_2bytes); | |
| 4155 | |
| 4156 int byte1 = vex_r ? VEX_R : 0; | |
| 4157 byte1 = (~byte1) & 0x80; | |
| 4158 byte1 |= ((~nds_enc) & 0xf) << 3; | |
| 4159 byte1 |= (vector256 ? 4 : 0) | pre; | |
| 4160 emit_byte(byte1); | |
| 4161 } | |
| 4162 } | |
| 4163 | |
| 4164 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
| 4165 bool vex_r = (xreg_enc >= 8); | |
| 4166 bool vex_b = adr.base_needs_rex(); | |
| 4167 bool vex_x = adr.index_needs_rex(); | |
| 4168 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 4169 } | |
| 4170 | |
| 4171 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
| 4172 bool vex_r = (dst_enc >= 8); | |
| 4173 bool vex_b = (src_enc >= 8); | |
| 4174 bool vex_x = false; | |
| 4175 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 4176 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
| 4177 } | |
| 4178 | |
| 4179 | |
| 4180 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 4181 if (UseAVX > 0) { | |
| 4182 int xreg_enc = xreg->encoding(); | |
| 4183 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 4184 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
| 4185 } else { | |
| 4186 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
| 4187 rex_prefix(adr, xreg, pre, opc, rex_w); | |
| 4188 } | |
| 4189 } | |
| 4190 | |
| 4191 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 4192 int dst_enc = dst->encoding(); | |
| 4193 int src_enc = src->encoding(); | |
| 4194 if (UseAVX > 0) { | |
| 4195 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 4196 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
| 4197 } else { | |
| 4198 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
| 4199 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
| 4200 } | |
| 4201 } | |
| 304 | 4202 |
|
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4203 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
|
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4204 InstructionMark im(this); |
|
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|
4205 simd_prefix(dst, dst, src, pre); |
|
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|
4206 emit_byte(opcode); |
|
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|
4207 emit_operand(dst, src); |
|
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|
4208 } |
|
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|
4209 |
|
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|
4210 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
|
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4211 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
|
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4212 emit_byte(opcode); |
|
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|
4213 emit_byte(0xC0 | encode); |
|
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|
4214 } |
|
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|
4215 |
|
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|
4216 // Versions with no second source register (non-destructive source). |
|
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|
4217 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
|
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4218 InstructionMark im(this); |
|
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|
4219 simd_prefix(dst, xnoreg, src, pre); |
|
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|
4220 emit_byte(opcode); |
|
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|
4221 emit_operand(dst, src); |
|
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|
4222 } |
|
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|
4223 |
|
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|
4224 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
|
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4225 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
|
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|
4226 emit_byte(opcode); |
|
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|
4227 emit_byte(0xC0 | encode); |
|
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|
4228 } |
|
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|
4229 |
|
006050192a5a
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|
4230 // 3-operands AVX instructions |
|
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|
4231 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
|
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|
4232 Address src, VexSimdPrefix pre, bool vector256) { |
|
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|
4233 InstructionMark im(this); |
|
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|
4234 vex_prefix(dst, nds, src, pre, vector256); |
|
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|
4235 emit_byte(opcode); |
|
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|
4236 emit_operand(dst, src); |
|
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|
4237 } |
|
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|
4238 |
|
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|
4239 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
|
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|
4240 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
|
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|
4241 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
|
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|
4242 emit_byte(opcode); |
|
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|
4243 emit_byte(0xC0 | encode); |
|
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|
4244 } |
|
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|
4245 |
| 304 | 4246 #ifndef _LP64 |
| 4247 | |
| 4248 void Assembler::incl(Register dst) { | |
| 4249 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4759 | 4250 emit_byte(0x40 | dst->encoding()); |
| 304 | 4251 } |
| 4252 | |
| 4253 void Assembler::lea(Register dst, Address src) { | |
| 4254 leal(dst, src); | |
| 4255 } | |
| 4256 | |
| 4257 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 4258 InstructionMark im(this); | |
| 4259 emit_byte(0xC7); | |
| 4260 emit_operand(rax, dst); | |
| 4261 emit_data((int)imm32, rspec, 0); | |
| 4262 } | |
| 4263 | |
|
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|
4264 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
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|
4265 InstructionMark im(this); |
|
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|
4266 int encode = prefix_and_encode(dst->encoding()); |
|
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|
4267 emit_byte(0xB8 | encode); |
|
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|
4268 emit_data((int)imm32, rspec, 0); |
|
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|
4269 } |
| 304 | 4270 |
| 4271 void Assembler::popa() { // 32bit | |
| 4272 emit_byte(0x61); | |
| 4273 } | |
| 4274 | |
| 4275 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 4276 InstructionMark im(this); | |
| 4277 emit_byte(0x68); | |
| 4278 emit_data(imm32, rspec, 0); | |
| 4279 } | |
| 4280 | |
| 4281 void Assembler::pusha() { // 32bit | |
| 4282 emit_byte(0x60); | |
| 4283 } | |
| 4284 | |
| 4285 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 4286 emit_byte(0x0F); |
| 304 | 4287 emit_byte(0x95); |
| 4288 emit_byte(0xE0 | dst->encoding()); | |
| 4289 } | |
| 4290 | |
| 4291 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 4292 emit_byte(0x0F); |
| 304 | 4293 emit_byte(0xA5); |
| 4294 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 4295 } | |
| 4296 | |
| 4297 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 4298 emit_byte(0x0F); |
| 304 | 4299 emit_byte(0xAD); |
| 4300 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 4301 } | |
| 4302 | |
| 4303 #else // LP64 | |
| 4304 | |
| 1369 | 4305 void Assembler::set_byte_if_not_zero(Register dst) { |
| 4306 int enc = prefix_and_encode(dst->encoding(), true); | |
| 4307 emit_byte(0x0F); | |
| 4308 emit_byte(0x95); | |
| 4309 emit_byte(0xE0 | enc); | |
| 4310 } | |
| 4311 | |
| 304 | 4312 // 64bit only pieces of the assembler |
| 4313 // This should only be used by 64bit instructions that can use rip-relative | |
| 4314 // it cannot be used by instructions that want an immediate value. | |
| 4315 | |
| 4316 bool Assembler::reachable(AddressLiteral adr) { | |
| 4317 int64_t disp; | |
| 4318 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 4319 // for something that will be patched later and we need to certain it will | |
| 4320 // always be reachable. | |
| 4321 if (adr.reloc() == relocInfo::none) { | |
| 4322 return false; | |
| 4323 } | |
| 4324 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 4325 // This should be rip relative and easily reachable. | |
| 4326 return true; | |
| 4327 } | |
| 4328 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 4329 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 4330 adr.reloc() == relocInfo::static_call_type || | |
| 4331 adr.reloc() == relocInfo::static_stub_type ) { | |
| 4332 // This should be rip relative within the code cache and easily | |
| 4333 // reachable until we get huge code caches. (At which point | |
| 4334 // ic code is going to have issues). | |
| 4335 return true; | |
| 4336 } | |
| 4337 if (adr.reloc() != relocInfo::external_word_type && | |
| 4338 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 4339 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 4340 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 4341 return false; | |
| 4342 } | |
| 4343 | |
| 4344 // Stress the correction code | |
| 4345 if (ForceUnreachable) { | |
| 4346 // Must be runtimecall reloc, see if it is in the codecache | |
| 4347 // Flipping stuff in the codecache to be unreachable causes issues | |
| 4348 // with things like inline caches where the additional instructions | |
| 4349 // are not handled. | |
| 4350 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 4351 return false; | |
| 4352 } | |
| 4353 } | |
| 4354 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 4355 // are now (possibly a temp buffer) and where we might end up | |
| 4356 // anywhere in the codeCache then we are always reachable. | |
| 4357 // This would have to change if we ever save/restore shared code | |
| 4358 // to be more pessimistic. | |
| 4359 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 4360 if (!is_simm32(disp)) return false; | |
| 4361 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 4362 if (!is_simm32(disp)) return false; | |
| 4363 | |
| 4364 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 4365 | |
| 4366 // Because rip relative is a disp + address_of_next_instruction and we | |
| 4367 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 4368 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 4369 // We don't have to fudge the checks above here because they are already worst case. | |
| 4370 | |
| 4371 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 4372 // + 4 because better safe than sorry. | |
| 4373 const int fudge = 12 + 4; | |
| 4374 if (disp < 0) { | |
| 4375 disp -= fudge; | |
| 4376 } else { | |
| 4377 disp += fudge; | |
| 4378 } | |
| 4379 return is_simm32(disp); | |
| 4380 } | |
| 4381 | |
|
2404
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6964776: c2 should ensure the polling page is reachable on 64 bit
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2357
diff
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|
4382 // Check if the polling page is not reachable from the code cache using rip-relative |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
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2357
diff
changeset
|
4383 // addressing. |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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2357
diff
changeset
|
4384 bool Assembler::is_polling_page_far() { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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2357
diff
changeset
|
4385 intptr_t addr = (intptr_t)os::get_polling_page(); |
|
4118
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
3938
diff
changeset
|
4386 return ForceUnreachable || |
|
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
3938
diff
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|
4387 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
|
2404
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|
4388 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
|
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6964776: c2 should ensure the polling page is reachable on 64 bit
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diff
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|
4389 } |
|
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|
4390 |
| 304 | 4391 void Assembler::emit_data64(jlong data, |
| 4392 relocInfo::relocType rtype, | |
| 4393 int format) { | |
| 4394 if (rtype == relocInfo::none) { | |
| 4395 emit_long64(data); | |
| 4396 } else { | |
| 4397 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 4398 } | |
| 4399 } | |
| 4400 | |
| 4401 void Assembler::emit_data64(jlong data, | |
| 4402 RelocationHolder const& rspec, | |
| 4403 int format) { | |
| 4404 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 4405 assert(imm_operand == format, "must be immediate"); | |
| 4406 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 4407 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 4408 // embedded words. Instead, relocate to the enclosing instruction. | |
| 4409 code_section()->relocate(inst_mark(), rspec, format); | |
| 4410 #ifdef ASSERT | |
| 4411 check_relocation(rspec, format); | |
| 4412 #endif | |
| 4413 emit_long64(data); | |
| 4414 } | |
| 4415 | |
| 4416 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 4417 if (reg_enc >= 8) { | |
| 4418 prefix(REX_B); | |
| 4419 reg_enc -= 8; | |
| 4420 } else if (byteinst && reg_enc >= 4) { | |
| 4421 prefix(REX); | |
| 4422 } | |
| 4423 return reg_enc; | |
| 4424 } | |
| 4425 | |
| 4426 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 4427 if (reg_enc < 8) { | |
| 4428 prefix(REX_W); | |
| 4429 } else { | |
| 4430 prefix(REX_WB); | |
| 4431 reg_enc -= 8; | |
| 4432 } | |
| 4433 return reg_enc; | |
| 4434 } | |
| 4435 | |
| 4436 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 4437 if (dst_enc < 8) { | |
| 4438 if (src_enc >= 8) { | |
| 4439 prefix(REX_B); | |
| 4440 src_enc -= 8; | |
| 4441 } else if (byteinst && src_enc >= 4) { | |
| 4442 prefix(REX); | |
| 4443 } | |
| 4444 } else { | |
| 4445 if (src_enc < 8) { | |
| 4446 prefix(REX_R); | |
| 4447 } else { | |
| 4448 prefix(REX_RB); | |
| 4449 src_enc -= 8; | |
| 4450 } | |
| 4451 dst_enc -= 8; | |
| 4452 } | |
| 4453 return dst_enc << 3 | src_enc; | |
| 4454 } | |
| 4455 | |
| 4456 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 4457 if (dst_enc < 8) { | |
| 4458 if (src_enc < 8) { | |
| 4459 prefix(REX_W); | |
| 4460 } else { | |
| 4461 prefix(REX_WB); | |
| 4462 src_enc -= 8; | |
| 4463 } | |
| 4464 } else { | |
| 4465 if (src_enc < 8) { | |
| 4466 prefix(REX_WR); | |
| 4467 } else { | |
| 4468 prefix(REX_WRB); | |
| 4469 src_enc -= 8; | |
| 4470 } | |
| 4471 dst_enc -= 8; | |
| 4472 } | |
| 4473 return dst_enc << 3 | src_enc; | |
| 4474 } | |
| 4475 | |
| 4476 void Assembler::prefix(Register reg) { | |
| 4477 if (reg->encoding() >= 8) { | |
| 4478 prefix(REX_B); | |
| 4479 } | |
| 4480 } | |
| 4481 | |
| 4482 void Assembler::prefix(Address adr) { | |
| 4483 if (adr.base_needs_rex()) { | |
| 4484 if (adr.index_needs_rex()) { | |
| 4485 prefix(REX_XB); | |
| 4486 } else { | |
| 4487 prefix(REX_B); | |
| 4488 } | |
| 4489 } else { | |
| 4490 if (adr.index_needs_rex()) { | |
| 4491 prefix(REX_X); | |
| 4492 } | |
| 4493 } | |
| 4494 } | |
| 4495 | |
| 4496 void Assembler::prefixq(Address adr) { | |
| 4497 if (adr.base_needs_rex()) { | |
| 4498 if (adr.index_needs_rex()) { | |
| 4499 prefix(REX_WXB); | |
| 4500 } else { | |
| 4501 prefix(REX_WB); | |
| 4502 } | |
| 4503 } else { | |
| 4504 if (adr.index_needs_rex()) { | |
| 4505 prefix(REX_WX); | |
| 4506 } else { | |
| 4507 prefix(REX_W); | |
| 4508 } | |
| 4509 } | |
| 4510 } | |
| 4511 | |
| 4512 | |
| 4513 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 4514 if (reg->encoding() < 8) { | |
| 4515 if (adr.base_needs_rex()) { | |
| 4516 if (adr.index_needs_rex()) { | |
| 4517 prefix(REX_XB); | |
| 4518 } else { | |
| 4519 prefix(REX_B); | |
| 4520 } | |
| 4521 } else { | |
| 4522 if (adr.index_needs_rex()) { | |
| 4523 prefix(REX_X); | |
| 3855 | 4524 } else if (byteinst && reg->encoding() >= 4 ) { |
| 304 | 4525 prefix(REX); |
| 4526 } | |
| 4527 } | |
| 4528 } else { | |
| 4529 if (adr.base_needs_rex()) { | |
| 4530 if (adr.index_needs_rex()) { | |
| 4531 prefix(REX_RXB); | |
| 4532 } else { | |
| 4533 prefix(REX_RB); | |
| 4534 } | |
| 4535 } else { | |
| 4536 if (adr.index_needs_rex()) { | |
| 4537 prefix(REX_RX); | |
| 4538 } else { | |
| 4539 prefix(REX_R); | |
| 4540 } | |
| 4541 } | |
| 4542 } | |
| 4543 } | |
| 4544 | |
| 4545 void Assembler::prefixq(Address adr, Register src) { | |
| 4546 if (src->encoding() < 8) { | |
| 4547 if (adr.base_needs_rex()) { | |
| 4548 if (adr.index_needs_rex()) { | |
| 4549 prefix(REX_WXB); | |
| 4550 } else { | |
| 4551 prefix(REX_WB); | |
| 4552 } | |
| 4553 } else { | |
| 4554 if (adr.index_needs_rex()) { | |
| 4555 prefix(REX_WX); | |
| 4556 } else { | |
| 4557 prefix(REX_W); | |
| 4558 } | |
| 4559 } | |
| 4560 } else { | |
| 4561 if (adr.base_needs_rex()) { | |
| 4562 if (adr.index_needs_rex()) { | |
| 4563 prefix(REX_WRXB); | |
| 4564 } else { | |
| 4565 prefix(REX_WRB); | |
| 4566 } | |
| 4567 } else { | |
| 4568 if (adr.index_needs_rex()) { | |
| 4569 prefix(REX_WRX); | |
| 4570 } else { | |
| 4571 prefix(REX_WR); | |
| 4572 } | |
| 4573 } | |
| 4574 } | |
| 4575 } | |
| 4576 | |
| 4577 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 4578 if (reg->encoding() < 8) { | |
| 4579 if (adr.base_needs_rex()) { | |
| 4580 if (adr.index_needs_rex()) { | |
| 4581 prefix(REX_XB); | |
| 4582 } else { | |
| 4583 prefix(REX_B); | |
| 4584 } | |
| 4585 } else { | |
| 4586 if (adr.index_needs_rex()) { | |
| 4587 prefix(REX_X); | |
| 4588 } | |
| 4589 } | |
| 4590 } else { | |
| 4591 if (adr.base_needs_rex()) { | |
| 4592 if (adr.index_needs_rex()) { | |
| 4593 prefix(REX_RXB); | |
| 4594 } else { | |
| 4595 prefix(REX_RB); | |
| 4596 } | |
| 4597 } else { | |
| 4598 if (adr.index_needs_rex()) { | |
| 4599 prefix(REX_RX); | |
| 4600 } else { | |
| 4601 prefix(REX_R); | |
| 4602 } | |
| 4603 } | |
| 4604 } | |
| 4605 } | |
| 4606 | |
| 4759 | 4607 void Assembler::prefixq(Address adr, XMMRegister src) { |
| 4608 if (src->encoding() < 8) { | |
| 4609 if (adr.base_needs_rex()) { | |
| 4610 if (adr.index_needs_rex()) { | |
| 4611 prefix(REX_WXB); | |
| 4612 } else { | |
| 4613 prefix(REX_WB); | |
| 4614 } | |
| 4615 } else { | |
| 4616 if (adr.index_needs_rex()) { | |
| 4617 prefix(REX_WX); | |
| 4618 } else { | |
| 4619 prefix(REX_W); | |
| 4620 } | |
| 4621 } | |
| 4622 } else { | |
| 4623 if (adr.base_needs_rex()) { | |
| 4624 if (adr.index_needs_rex()) { | |
| 4625 prefix(REX_WRXB); | |
| 4626 } else { | |
| 4627 prefix(REX_WRB); | |
| 4628 } | |
| 4629 } else { | |
| 4630 if (adr.index_needs_rex()) { | |
| 4631 prefix(REX_WRX); | |
| 4632 } else { | |
| 4633 prefix(REX_WR); | |
| 4634 } | |
| 4635 } | |
| 4636 } | |
| 4637 } | |
| 4638 | |
| 304 | 4639 void Assembler::adcq(Register dst, int32_t imm32) { |
| 4640 (void) prefixq_and_encode(dst->encoding()); | |
| 4641 emit_arith(0x81, 0xD0, dst, imm32); | |
| 4642 } | |
| 4643 | |
| 4644 void Assembler::adcq(Register dst, Address src) { | |
| 4645 InstructionMark im(this); | |
| 4646 prefixq(src, dst); | |
| 4647 emit_byte(0x13); | |
| 4648 emit_operand(dst, src); | |
| 4649 } | |
| 4650 | |
| 4651 void Assembler::adcq(Register dst, Register src) { | |
| 4652 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4653 emit_arith(0x13, 0xC0, dst, src); | |
| 4654 } | |
| 4655 | |
| 4656 void Assembler::addq(Address dst, int32_t imm32) { | |
| 4657 InstructionMark im(this); | |
| 4658 prefixq(dst); | |
| 4659 emit_arith_operand(0x81, rax, dst,imm32); | |
| 4660 } | |
| 4661 | |
| 4662 void Assembler::addq(Address dst, Register src) { | |
| 4663 InstructionMark im(this); | |
| 4664 prefixq(dst, src); | |
| 4665 emit_byte(0x01); | |
| 4666 emit_operand(src, dst); | |
| 4667 } | |
| 4668 | |
| 4669 void Assembler::addq(Register dst, int32_t imm32) { | |
| 4670 (void) prefixq_and_encode(dst->encoding()); | |
| 4671 emit_arith(0x81, 0xC0, dst, imm32); | |
| 4672 } | |
| 4673 | |
| 4674 void Assembler::addq(Register dst, Address src) { | |
| 4675 InstructionMark im(this); | |
| 4676 prefixq(src, dst); | |
| 4677 emit_byte(0x03); | |
| 4678 emit_operand(dst, src); | |
| 4679 } | |
| 4680 | |
| 4681 void Assembler::addq(Register dst, Register src) { | |
| 4682 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4683 emit_arith(0x03, 0xC0, dst, src); | |
| 4684 } | |
| 4685 | |
| 3457 | 4686 void Assembler::andq(Address dst, int32_t imm32) { |
| 4687 InstructionMark im(this); | |
| 4688 prefixq(dst); | |
| 4689 emit_byte(0x81); | |
| 4690 emit_operand(rsp, dst, 4); | |
| 4691 emit_long(imm32); | |
| 4692 } | |
| 4693 | |
| 304 | 4694 void Assembler::andq(Register dst, int32_t imm32) { |
| 4695 (void) prefixq_and_encode(dst->encoding()); | |
| 4696 emit_arith(0x81, 0xE0, dst, imm32); | |
| 4697 } | |
| 4698 | |
| 4699 void Assembler::andq(Register dst, Address src) { | |
| 4700 InstructionMark im(this); | |
| 4701 prefixq(src, dst); | |
| 4702 emit_byte(0x23); | |
| 4703 emit_operand(dst, src); | |
| 4704 } | |
| 4705 | |
| 4706 void Assembler::andq(Register dst, Register src) { | |
| 4707 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4708 emit_arith(0x23, 0xC0, dst, src); | |
| 4709 } | |
| 4710 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4711 void Assembler::bsfq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4712 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4713 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4714 emit_byte(0xBC); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4715 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4716 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4717 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4718 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4719 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4720 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4721 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4722 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4723 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4724 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4725 |
| 304 | 4726 void Assembler::bswapq(Register reg) { |
| 4727 int encode = prefixq_and_encode(reg->encoding()); | |
| 4728 emit_byte(0x0F); | |
| 4729 emit_byte(0xC8 | encode); | |
| 4730 } | |
| 4731 | |
| 4732 void Assembler::cdqq() { | |
| 4733 prefix(REX_W); | |
| 4734 emit_byte(0x99); | |
| 4735 } | |
| 4736 | |
| 4737 void Assembler::clflush(Address adr) { | |
| 4738 prefix(adr); | |
| 4739 emit_byte(0x0F); | |
| 4740 emit_byte(0xAE); | |
| 4741 emit_operand(rdi, adr); | |
| 4742 } | |
| 4743 | |
| 4744 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 4745 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4746 emit_byte(0x0F); | |
| 4747 emit_byte(0x40 | cc); | |
| 4748 emit_byte(0xC0 | encode); | |
| 4749 } | |
| 4750 | |
| 4751 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 4752 InstructionMark im(this); | |
| 4753 prefixq(src, dst); | |
| 4754 emit_byte(0x0F); | |
| 4755 emit_byte(0x40 | cc); | |
| 4756 emit_operand(dst, src); | |
| 4757 } | |
| 4758 | |
| 4759 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 4760 InstructionMark im(this); | |
| 4761 prefixq(dst); | |
| 4762 emit_byte(0x81); | |
| 4763 emit_operand(rdi, dst, 4); | |
| 4764 emit_long(imm32); | |
| 4765 } | |
| 4766 | |
| 4767 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 4768 (void) prefixq_and_encode(dst->encoding()); | |
| 4769 emit_arith(0x81, 0xF8, dst, imm32); | |
| 4770 } | |
| 4771 | |
| 4772 void Assembler::cmpq(Address dst, Register src) { | |
| 4773 InstructionMark im(this); | |
| 4774 prefixq(dst, src); | |
| 4775 emit_byte(0x3B); | |
| 4776 emit_operand(src, dst); | |
| 4777 } | |
| 4778 | |
| 4779 void Assembler::cmpq(Register dst, Register src) { | |
| 4780 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4781 emit_arith(0x3B, 0xC0, dst, src); | |
| 4782 } | |
| 4783 | |
| 4784 void Assembler::cmpq(Register dst, Address src) { | |
| 4785 InstructionMark im(this); | |
| 4786 prefixq(src, dst); | |
| 4787 emit_byte(0x3B); | |
| 4788 emit_operand(dst, src); | |
| 4789 } | |
| 4790 | |
| 4791 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 4792 InstructionMark im(this); | |
| 4793 prefixq(adr, reg); | |
| 4794 emit_byte(0x0F); | |
| 4795 emit_byte(0xB1); | |
| 4796 emit_operand(reg, adr); | |
| 4797 } | |
| 4798 | |
| 4799 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 4800 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4801 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
| 304 | 4802 emit_byte(0x2A); |
| 4803 emit_byte(0xC0 | encode); | |
| 4804 } | |
| 4805 | |
| 4759 | 4806 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
| 4807 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4808 InstructionMark im(this); | |
| 4809 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
| 4810 emit_byte(0x2A); | |
| 4811 emit_operand(dst, src); | |
| 4812 } | |
| 4813 | |
| 304 | 4814 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
| 4815 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4816 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
| 304 | 4817 emit_byte(0x2A); |
| 4818 emit_byte(0xC0 | encode); | |
| 4819 } | |
| 4820 | |
| 4759 | 4821 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
| 4822 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4823 InstructionMark im(this); | |
| 4824 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
| 4825 emit_byte(0x2A); | |
| 4826 emit_operand(dst, src); | |
| 4827 } | |
| 4828 | |
| 304 | 4829 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
| 4830 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4831 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
| 304 | 4832 emit_byte(0x2C); |
| 4833 emit_byte(0xC0 | encode); | |
| 4834 } | |
| 4835 | |
| 4836 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 4837 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4838 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
| 304 | 4839 emit_byte(0x2C); |
| 4840 emit_byte(0xC0 | encode); | |
| 4841 } | |
| 4842 | |
| 4843 void Assembler::decl(Register dst) { | |
| 4844 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 4845 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 4846 int encode = prefix_and_encode(dst->encoding()); | |
| 4847 emit_byte(0xFF); | |
| 4848 emit_byte(0xC8 | encode); | |
| 4849 } | |
| 4850 | |
| 4851 void Assembler::decq(Register dst) { | |
| 4852 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4853 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4854 int encode = prefixq_and_encode(dst->encoding()); | |
| 4855 emit_byte(0xFF); | |
| 4856 emit_byte(0xC8 | encode); | |
| 4857 } | |
| 4858 | |
| 4859 void Assembler::decq(Address dst) { | |
| 4860 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4861 InstructionMark im(this); | |
| 4862 prefixq(dst); | |
| 4863 emit_byte(0xFF); | |
| 4864 emit_operand(rcx, dst); | |
| 4865 } | |
| 4866 | |
| 4867 void Assembler::fxrstor(Address src) { | |
| 4868 prefixq(src); | |
| 4869 emit_byte(0x0F); | |
| 4870 emit_byte(0xAE); | |
| 4871 emit_operand(as_Register(1), src); | |
| 4872 } | |
| 4873 | |
| 4874 void Assembler::fxsave(Address dst) { | |
| 4875 prefixq(dst); | |
| 4876 emit_byte(0x0F); | |
| 4877 emit_byte(0xAE); | |
| 4878 emit_operand(as_Register(0), dst); | |
| 4879 } | |
| 4880 | |
| 4881 void Assembler::idivq(Register src) { | |
| 4882 int encode = prefixq_and_encode(src->encoding()); | |
| 4883 emit_byte(0xF7); | |
| 4884 emit_byte(0xF8 | encode); | |
| 4885 } | |
| 4886 | |
| 4887 void Assembler::imulq(Register dst, Register src) { | |
| 4888 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4889 emit_byte(0x0F); | |
| 4890 emit_byte(0xAF); | |
| 4891 emit_byte(0xC0 | encode); | |
| 4892 } | |
| 4893 | |
| 4894 void Assembler::imulq(Register dst, Register src, int value) { | |
| 4895 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4896 if (is8bit(value)) { | |
| 4897 emit_byte(0x6B); | |
| 4898 emit_byte(0xC0 | encode); | |
|
1914
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diff
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|
4899 emit_byte(value & 0xFF); |
| 304 | 4900 } else { |
| 4901 emit_byte(0x69); | |
| 4902 emit_byte(0xC0 | encode); | |
| 4903 emit_long(value); | |
| 4904 } | |
| 4905 } | |
| 4906 | |
| 4907 void Assembler::incl(Register dst) { | |
| 4908 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4909 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4910 int encode = prefix_and_encode(dst->encoding()); | |
| 4911 emit_byte(0xFF); | |
| 4912 emit_byte(0xC0 | encode); | |
| 4913 } | |
| 4914 | |
| 4915 void Assembler::incq(Register dst) { | |
| 4916 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4917 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4918 int encode = prefixq_and_encode(dst->encoding()); | |
| 4919 emit_byte(0xFF); | |
| 4920 emit_byte(0xC0 | encode); | |
| 4921 } | |
| 4922 | |
| 4923 void Assembler::incq(Address dst) { | |
| 4924 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4925 InstructionMark im(this); | |
| 4926 prefixq(dst); | |
| 4927 emit_byte(0xFF); | |
| 4928 emit_operand(rax, dst); | |
| 4929 } | |
| 4930 | |
| 4931 void Assembler::lea(Register dst, Address src) { | |
| 4932 leaq(dst, src); | |
| 4933 } | |
| 4934 | |
| 4935 void Assembler::leaq(Register dst, Address src) { | |
| 4936 InstructionMark im(this); | |
| 4937 prefixq(src, dst); | |
| 4938 emit_byte(0x8D); | |
| 4939 emit_operand(dst, src); | |
| 4940 } | |
| 4941 | |
| 4942 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4943 InstructionMark im(this); | |
| 4944 int encode = prefixq_and_encode(dst->encoding()); | |
| 4945 emit_byte(0xB8 | encode); | |
| 4946 emit_long64(imm64); | |
| 4947 } | |
| 4948 | |
| 4949 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4950 InstructionMark im(this); | |
| 4951 int encode = prefixq_and_encode(dst->encoding()); | |
| 4952 emit_byte(0xB8 | encode); | |
| 4953 emit_data64(imm64, rspec); | |
| 4954 } | |
| 4955 | |
|
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|
4956 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
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4957 InstructionMark im(this); |
|
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|
4958 int encode = prefix_and_encode(dst->encoding()); |
|
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|
4959 emit_byte(0xB8 | encode); |
|
660978a2a31a
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diff
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|
4960 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
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|
4961 } |
|
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|
4962 |
|
660978a2a31a
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|
4963 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
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|
4964 InstructionMark im(this); |
|
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624
diff
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|
4965 prefix(dst); |
|
660978a2a31a
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|
4966 emit_byte(0xC7); |
|
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diff
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|
4967 emit_operand(rax, dst, 4); |
|
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|
4968 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
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|
4969 } |
|
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|
4970 |
|
660978a2a31a
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|
4971 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
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|
4972 InstructionMark im(this); |
|
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|
4973 int encode = prefix_and_encode(src1->encoding()); |
|
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|
4974 emit_byte(0x81); |
|
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|
4975 emit_byte(0xF8 | encode); |
|
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diff
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|
4976 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
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|
4977 } |
|
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|
4978 |
|
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|
4979 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
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|
4980 InstructionMark im(this); |
|
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624
diff
changeset
|
4981 prefix(src1); |
|
660978a2a31a
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|
4982 emit_byte(0x81); |
|
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|
4983 emit_operand(rax, src1, 4); |
|
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|
4984 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
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|
4985 } |
|
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|
4986 |
|
775
93c14e5562c4
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|
4987 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
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diff
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|
4988 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
93c14e5562c4
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diff
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|
4989 emit_byte(0xF3); |
|
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diff
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|
4990 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
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|
4991 emit_byte(0x0F); |
|
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twisti
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|
4992 emit_byte(0xBD); |
|
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|
4993 emit_byte(0xC0 | encode); |
|
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|
4994 } |
|
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|
4995 |
| 304 | 4996 void Assembler::movdq(XMMRegister dst, Register src) { |
| 4997 // table D-1 says MMX/SSE2 | |
| 4759 | 4998 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4999 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
| 304 | 5000 emit_byte(0x6E); |
| 5001 emit_byte(0xC0 | encode); | |
| 5002 } | |
| 5003 | |
| 5004 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 5005 // table D-1 says MMX/SSE2 | |
| 4759 | 5006 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 304 | 5007 // swap src/dst to get correct prefix |
| 4759 | 5008 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
| 0 | 5009 emit_byte(0x7E); |
| 304 | 5010 emit_byte(0xC0 | encode); |
| 5011 } | |
| 5012 | |
| 5013 void Assembler::movq(Register dst, Register src) { | |
| 5014 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5015 emit_byte(0x8B); | |
| 5016 emit_byte(0xC0 | encode); | |
| 5017 } | |
| 5018 | |
| 5019 void Assembler::movq(Register dst, Address src) { | |
| 5020 InstructionMark im(this); | |
| 5021 prefixq(src, dst); | |
| 5022 emit_byte(0x8B); | |
| 5023 emit_operand(dst, src); | |
| 5024 } | |
| 5025 | |
| 5026 void Assembler::movq(Address dst, Register src) { | |
| 5027 InstructionMark im(this); | |
| 5028 prefixq(dst, src); | |
| 5029 emit_byte(0x89); | |
| 5030 emit_operand(src, dst); | |
| 5031 } | |
| 5032 | |
| 624 | 5033 void Assembler::movsbq(Register dst, Address src) { |
| 5034 InstructionMark im(this); | |
| 5035 prefixq(src, dst); | |
| 5036 emit_byte(0x0F); | |
| 5037 emit_byte(0xBE); | |
| 5038 emit_operand(dst, src); | |
| 5039 } | |
| 5040 | |
| 5041 void Assembler::movsbq(Register dst, Register src) { | |
| 5042 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5043 emit_byte(0x0F); | |
| 5044 emit_byte(0xBE); | |
| 5045 emit_byte(0xC0 | encode); | |
| 5046 } | |
| 5047 | |
| 304 | 5048 void Assembler::movslq(Register dst, int32_t imm32) { |
| 5049 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 5050 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 5051 // as a result we shouldn't use until tested at runtime... | |
| 5052 ShouldNotReachHere(); | |
| 5053 InstructionMark im(this); | |
| 5054 int encode = prefixq_and_encode(dst->encoding()); | |
| 5055 emit_byte(0xC7 | encode); | |
| 5056 emit_long(imm32); | |
| 5057 } | |
| 5058 | |
| 5059 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 5060 assert(is_simm32(imm32), "lost bits"); | |
| 5061 InstructionMark im(this); | |
| 5062 prefixq(dst); | |
| 5063 emit_byte(0xC7); | |
| 5064 emit_operand(rax, dst, 4); | |
| 5065 emit_long(imm32); | |
| 5066 } | |
| 5067 | |
| 5068 void Assembler::movslq(Register dst, Address src) { | |
| 5069 InstructionMark im(this); | |
| 5070 prefixq(src, dst); | |
| 5071 emit_byte(0x63); | |
| 5072 emit_operand(dst, src); | |
| 5073 } | |
| 5074 | |
| 5075 void Assembler::movslq(Register dst, Register src) { | |
| 5076 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5077 emit_byte(0x63); | |
| 5078 emit_byte(0xC0 | encode); | |
| 5079 } | |
| 5080 | |
| 624 | 5081 void Assembler::movswq(Register dst, Address src) { |
| 5082 InstructionMark im(this); | |
| 5083 prefixq(src, dst); | |
| 5084 emit_byte(0x0F); | |
| 5085 emit_byte(0xBF); | |
| 5086 emit_operand(dst, src); | |
| 5087 } | |
| 5088 | |
| 5089 void Assembler::movswq(Register dst, Register src) { | |
| 5090 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5091 emit_byte(0x0F); | |
| 5092 emit_byte(0xBF); | |
| 5093 emit_byte(0xC0 | encode); | |
| 5094 } | |
| 5095 | |
| 5096 void Assembler::movzbq(Register dst, Address src) { | |
| 5097 InstructionMark im(this); | |
| 5098 prefixq(src, dst); | |
| 5099 emit_byte(0x0F); | |
| 5100 emit_byte(0xB6); | |
| 5101 emit_operand(dst, src); | |
| 5102 } | |
| 5103 | |
| 5104 void Assembler::movzbq(Register dst, Register src) { | |
| 5105 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5106 emit_byte(0x0F); | |
| 5107 emit_byte(0xB6); | |
| 5108 emit_byte(0xC0 | encode); | |
| 5109 } | |
| 5110 | |
| 5111 void Assembler::movzwq(Register dst, Address src) { | |
| 5112 InstructionMark im(this); | |
| 5113 prefixq(src, dst); | |
| 5114 emit_byte(0x0F); | |
| 5115 emit_byte(0xB7); | |
| 5116 emit_operand(dst, src); | |
| 5117 } | |
| 5118 | |
| 5119 void Assembler::movzwq(Register dst, Register src) { | |
| 5120 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5121 emit_byte(0x0F); | |
| 5122 emit_byte(0xB7); | |
| 5123 emit_byte(0xC0 | encode); | |
| 5124 } | |
| 5125 | |
| 304 | 5126 void Assembler::negq(Register dst) { |
| 5127 int encode = prefixq_and_encode(dst->encoding()); | |
| 5128 emit_byte(0xF7); | |
| 5129 emit_byte(0xD8 | encode); | |
| 5130 } | |
| 5131 | |
| 5132 void Assembler::notq(Register dst) { | |
| 5133 int encode = prefixq_and_encode(dst->encoding()); | |
| 5134 emit_byte(0xF7); | |
| 5135 emit_byte(0xD0 | encode); | |
| 5136 } | |
| 5137 | |
| 5138 void Assembler::orq(Address dst, int32_t imm32) { | |
| 5139 InstructionMark im(this); | |
| 5140 prefixq(dst); | |
| 5141 emit_byte(0x81); | |
| 5142 emit_operand(rcx, dst, 4); | |
| 5143 emit_long(imm32); | |
| 5144 } | |
| 5145 | |
| 5146 void Assembler::orq(Register dst, int32_t imm32) { | |
| 5147 (void) prefixq_and_encode(dst->encoding()); | |
| 5148 emit_arith(0x81, 0xC8, dst, imm32); | |
| 5149 } | |
| 5150 | |
| 5151 void Assembler::orq(Register dst, Address src) { | |
| 5152 InstructionMark im(this); | |
| 5153 prefixq(src, dst); | |
| 5154 emit_byte(0x0B); | |
| 5155 emit_operand(dst, src); | |
| 5156 } | |
| 5157 | |
| 5158 void Assembler::orq(Register dst, Register src) { | |
| 5159 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5160 emit_arith(0x0B, 0xC0, dst, src); | |
| 5161 } | |
| 5162 | |
| 5163 void Assembler::popa() { // 64bit | |
| 5164 movq(r15, Address(rsp, 0)); | |
| 5165 movq(r14, Address(rsp, wordSize)); | |
| 5166 movq(r13, Address(rsp, 2 * wordSize)); | |
| 5167 movq(r12, Address(rsp, 3 * wordSize)); | |
| 5168 movq(r11, Address(rsp, 4 * wordSize)); | |
| 5169 movq(r10, Address(rsp, 5 * wordSize)); | |
| 5170 movq(r9, Address(rsp, 6 * wordSize)); | |
| 5171 movq(r8, Address(rsp, 7 * wordSize)); | |
| 5172 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 5173 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 5174 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 5175 // skip rsp | |
| 5176 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 5177 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 5178 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 5179 movq(rax, Address(rsp, 15 * wordSize)); | |
| 5180 | |
| 5181 addq(rsp, 16 * wordSize); | |
| 5182 } | |
| 5183 | |
|
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5184 void Assembler::popcntq(Register dst, Address src) { |
|
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5185 assert(VM_Version::supports_popcnt(), "must support"); |
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5186 InstructionMark im(this); |
|
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5187 emit_byte(0xF3); |
|
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|
5188 prefixq(src, dst); |
|
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5189 emit_byte(0x0F); |
|
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5190 emit_byte(0xB8); |
|
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5191 emit_operand(dst, src); |
|
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5192 } |
|
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5193 |
|
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5194 void Assembler::popcntq(Register dst, Register src) { |
|
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5195 assert(VM_Version::supports_popcnt(), "must support"); |
|
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5196 emit_byte(0xF3); |
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5197 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
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5198 emit_byte(0x0F); |
|
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5199 emit_byte(0xB8); |
|
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5200 emit_byte(0xC0 | encode); |
|
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5201 } |
|
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|
5202 |
| 304 | 5203 void Assembler::popq(Address dst) { |
| 5204 InstructionMark im(this); | |
| 5205 prefixq(dst); | |
| 5206 emit_byte(0x8F); | |
| 5207 emit_operand(rax, dst); | |
| 5208 } | |
| 5209 | |
| 5210 void Assembler::pusha() { // 64bit | |
| 5211 // we have to store original rsp. ABI says that 128 bytes | |
| 5212 // below rsp are local scratch. | |
| 5213 movq(Address(rsp, -5 * wordSize), rsp); | |
| 5214 | |
| 5215 subq(rsp, 16 * wordSize); | |
| 5216 | |
| 5217 movq(Address(rsp, 15 * wordSize), rax); | |
| 5218 movq(Address(rsp, 14 * wordSize), rcx); | |
| 5219 movq(Address(rsp, 13 * wordSize), rdx); | |
| 5220 movq(Address(rsp, 12 * wordSize), rbx); | |
| 5221 // skip rsp | |
| 5222 movq(Address(rsp, 10 * wordSize), rbp); | |
| 5223 movq(Address(rsp, 9 * wordSize), rsi); | |
| 5224 movq(Address(rsp, 8 * wordSize), rdi); | |
| 5225 movq(Address(rsp, 7 * wordSize), r8); | |
| 5226 movq(Address(rsp, 6 * wordSize), r9); | |
| 5227 movq(Address(rsp, 5 * wordSize), r10); | |
| 5228 movq(Address(rsp, 4 * wordSize), r11); | |
| 5229 movq(Address(rsp, 3 * wordSize), r12); | |
| 5230 movq(Address(rsp, 2 * wordSize), r13); | |
| 5231 movq(Address(rsp, wordSize), r14); | |
| 5232 movq(Address(rsp, 0), r15); | |
| 5233 } | |
| 5234 | |
| 5235 void Assembler::pushq(Address src) { | |
| 5236 InstructionMark im(this); | |
| 5237 prefixq(src); | |
| 5238 emit_byte(0xFF); | |
| 5239 emit_operand(rsi, src); | |
| 5240 } | |
| 5241 | |
| 5242 void Assembler::rclq(Register dst, int imm8) { | |
| 5243 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5244 int encode = prefixq_and_encode(dst->encoding()); | |
| 5245 if (imm8 == 1) { | |
| 5246 emit_byte(0xD1); | |
| 5247 emit_byte(0xD0 | encode); | |
| 5248 } else { | |
| 5249 emit_byte(0xC1); | |
| 5250 emit_byte(0xD0 | encode); | |
| 5251 emit_byte(imm8); | |
| 5252 } | |
| 5253 } | |
| 5254 void Assembler::sarq(Register dst, int imm8) { | |
| 5255 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5256 int encode = prefixq_and_encode(dst->encoding()); | |
| 5257 if (imm8 == 1) { | |
| 5258 emit_byte(0xD1); | |
| 5259 emit_byte(0xF8 | encode); | |
| 5260 } else { | |
| 5261 emit_byte(0xC1); | |
| 5262 emit_byte(0xF8 | encode); | |
| 5263 emit_byte(imm8); | |
| 5264 } | |
| 5265 } | |
| 5266 | |
| 5267 void Assembler::sarq(Register dst) { | |
| 5268 int encode = prefixq_and_encode(dst->encoding()); | |
| 5269 emit_byte(0xD3); | |
| 5270 emit_byte(0xF8 | encode); | |
| 5271 } | |
|
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|
5272 |
| 304 | 5273 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 5274 InstructionMark im(this); | |
| 5275 prefixq(dst); | |
| 5276 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 5277 } | |
| 5278 | |
| 5279 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 5280 (void) prefixq_and_encode(dst->encoding()); | |
| 5281 emit_arith(0x81, 0xD8, dst, imm32); | |
| 5282 } | |
| 5283 | |
| 5284 void Assembler::sbbq(Register dst, Address src) { | |
| 5285 InstructionMark im(this); | |
| 5286 prefixq(src, dst); | |
| 5287 emit_byte(0x1B); | |
| 5288 emit_operand(dst, src); | |
| 5289 } | |
| 5290 | |
| 5291 void Assembler::sbbq(Register dst, Register src) { | |
| 5292 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5293 emit_arith(0x1B, 0xC0, dst, src); | |
| 5294 } | |
| 5295 | |
| 5296 void Assembler::shlq(Register dst, int imm8) { | |
| 5297 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5298 int encode = prefixq_and_encode(dst->encoding()); | |
| 5299 if (imm8 == 1) { | |
| 5300 emit_byte(0xD1); | |
| 5301 emit_byte(0xE0 | encode); | |
| 5302 } else { | |
| 5303 emit_byte(0xC1); | |
| 5304 emit_byte(0xE0 | encode); | |
| 5305 emit_byte(imm8); | |
| 5306 } | |
| 5307 } | |
| 5308 | |
| 5309 void Assembler::shlq(Register dst) { | |
| 5310 int encode = prefixq_and_encode(dst->encoding()); | |
| 5311 emit_byte(0xD3); | |
| 5312 emit_byte(0xE0 | encode); | |
| 5313 } | |
| 5314 | |
| 5315 void Assembler::shrq(Register dst, int imm8) { | |
| 5316 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5317 int encode = prefixq_and_encode(dst->encoding()); | |
| 5318 emit_byte(0xC1); | |
| 5319 emit_byte(0xE8 | encode); | |
| 5320 emit_byte(imm8); | |
| 5321 } | |
| 5322 | |
| 5323 void Assembler::shrq(Register dst) { | |
| 5324 int encode = prefixq_and_encode(dst->encoding()); | |
| 5325 emit_byte(0xD3); | |
| 5326 emit_byte(0xE8 | encode); | |
| 5327 } | |
| 5328 | |
| 5329 void Assembler::subq(Address dst, int32_t imm32) { | |
| 5330 InstructionMark im(this); | |
| 5331 prefixq(dst); | |
|
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|
5332 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 5333 } |
| 5334 | |
| 5335 void Assembler::subq(Address dst, Register src) { | |
| 5336 InstructionMark im(this); | |
| 5337 prefixq(dst, src); | |
| 5338 emit_byte(0x29); | |
| 5339 emit_operand(src, dst); | |
| 5340 } | |
| 5341 | |
|
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|
5342 void Assembler::subq(Register dst, int32_t imm32) { |
|
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|
5343 (void) prefixq_and_encode(dst->encoding()); |
|
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|
5344 emit_arith(0x81, 0xE8, dst, imm32); |
|
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|
5345 } |
|
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|
5346 |
|
4947
fd8114661503
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diff
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|
5347 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
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|
5348 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
|
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|
5349 (void) prefixq_and_encode(dst->encoding()); |
|
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|
5350 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
|
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|
5351 } |
|
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|
5352 |
| 304 | 5353 void Assembler::subq(Register dst, Address src) { |
| 5354 InstructionMark im(this); | |
| 5355 prefixq(src, dst); | |
| 5356 emit_byte(0x2B); | |
| 5357 emit_operand(dst, src); | |
| 5358 } | |
| 5359 | |
| 5360 void Assembler::subq(Register dst, Register src) { | |
| 5361 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5362 emit_arith(0x2B, 0xC0, dst, src); | |
| 5363 } | |
| 5364 | |
| 5365 void Assembler::testq(Register dst, int32_t imm32) { | |
| 5366 // not using emit_arith because test | |
| 5367 // doesn't support sign-extension of | |
| 5368 // 8bit operands | |
| 5369 int encode = dst->encoding(); | |
| 5370 if (encode == 0) { | |
| 5371 prefix(REX_W); | |
| 5372 emit_byte(0xA9); | |
| 5373 } else { | |
| 5374 encode = prefixq_and_encode(encode); | |
| 5375 emit_byte(0xF7); | |
| 5376 emit_byte(0xC0 | encode); | |
| 5377 } | |
| 5378 emit_long(imm32); | |
| 5379 } | |
| 5380 | |
| 5381 void Assembler::testq(Register dst, Register src) { | |
| 5382 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5383 emit_arith(0x85, 0xC0, dst, src); | |
| 5384 } | |
| 5385 | |
| 5386 void Assembler::xaddq(Address dst, Register src) { | |
| 5387 InstructionMark im(this); | |
| 5388 prefixq(dst, src); | |
| 71 | 5389 emit_byte(0x0F); |
| 304 | 5390 emit_byte(0xC1); |
| 5391 emit_operand(src, dst); | |
| 5392 } | |
| 5393 | |
| 5394 void Assembler::xchgq(Register dst, Address src) { | |
| 5395 InstructionMark im(this); | |
| 5396 prefixq(src, dst); | |
| 5397 emit_byte(0x87); | |
| 5398 emit_operand(dst, src); | |
| 5399 } | |
| 5400 | |
| 5401 void Assembler::xchgq(Register dst, Register src) { | |
| 5402 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5403 emit_byte(0x87); | |
| 5404 emit_byte(0xc0 | encode); | |
| 5405 } | |
| 5406 | |
| 5407 void Assembler::xorq(Register dst, Register src) { | |
| 5408 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5409 emit_arith(0x33, 0xC0, dst, src); | |
| 5410 } | |
| 5411 | |
| 5412 void Assembler::xorq(Register dst, Address src) { | |
| 5413 InstructionMark im(this); | |
| 5414 prefixq(src, dst); | |
| 5415 emit_byte(0x33); | |
| 5416 emit_operand(dst, src); | |
| 5417 } | |
| 5418 | |
| 5419 #endif // !LP64 | |
| 5420 | |
| 5421 static Assembler::Condition reverse[] = { | |
| 5422 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 5423 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 5424 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 5425 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 5426 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 5427 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 5428 Assembler::above /* belowEqual = 0x6 */ , | |
| 5429 Assembler::belowEqual /* above = 0x7 */ , | |
| 5430 Assembler::positive /* negative = 0x8 */ , | |
| 5431 Assembler::negative /* positive = 0x9 */ , | |
| 5432 Assembler::noParity /* parity = 0xa */ , | |
| 5433 Assembler::parity /* noParity = 0xb */ , | |
| 5434 Assembler::greaterEqual /* less = 0xc */ , | |
| 5435 Assembler::less /* greaterEqual = 0xd */ , | |
| 5436 Assembler::greater /* lessEqual = 0xe */ , | |
| 5437 Assembler::lessEqual /* greater = 0xf, */ | |
| 5438 | |
| 5439 }; | |
| 5440 | |
| 0 | 5441 |
| 5442 // Implementation of MacroAssembler | |
| 5443 | |
| 304 | 5444 // First all the versions that have distinct versions depending on 32/64 bit |
| 5445 // Unless the difference is trivial (1 line or so). | |
| 5446 | |
| 5447 #ifndef _LP64 | |
| 5448 | |
| 5449 // 32bit versions | |
| 5450 | |
| 0 | 5451 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 5452 return Address(adr.target(), adr.rspec()); | |
| 5453 } | |
| 5454 | |
| 5455 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 5456 return Address::make_array(adr); | |
| 5457 } | |
| 5458 | |
| 304 | 5459 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 5460 Register obj_reg, | |
| 5461 Register swap_reg, | |
| 5462 Register tmp_reg, | |
| 5463 bool swap_reg_contains_mark, | |
| 5464 Label& done, | |
| 5465 Label* slow_case, | |
| 5466 BiasedLockingCounters* counters) { | |
| 5467 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5468 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 5469 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 5470 | |
| 5471 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5472 counters = BiasedLocking::counters(); | |
| 5473 | |
| 5474 bool need_tmp_reg = false; | |
| 5475 if (tmp_reg == noreg) { | |
| 5476 need_tmp_reg = true; | |
| 5477 tmp_reg = lock_reg; | |
| 5478 } else { | |
| 5479 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5480 } | |
| 5481 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5482 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5483 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 5484 Address saved_mark_addr(lock_reg, 0); | |
| 5485 | |
| 5486 // Biased locking | |
| 5487 // See whether the lock is currently biased toward our thread and | |
| 5488 // whether the epoch is still valid | |
| 5489 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5490 // pointers to allow age to be placed into low bits | |
| 5491 // First check to see whether biasing is even enabled for this object | |
| 5492 Label cas_label; | |
| 5493 int null_check_offset = -1; | |
| 5494 if (!swap_reg_contains_mark) { | |
| 5495 null_check_offset = offset(); | |
| 5496 movl(swap_reg, mark_addr); | |
| 5497 } | |
| 5498 if (need_tmp_reg) { | |
| 5499 push(tmp_reg); | |
| 5500 } | |
| 5501 movl(tmp_reg, swap_reg); | |
| 5502 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5503 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5504 if (need_tmp_reg) { | |
| 5505 pop(tmp_reg); | |
| 5506 } | |
| 5507 jcc(Assembler::notEqual, cas_label); | |
| 5508 // The bias pattern is present in the object's header. Need to check | |
| 5509 // whether the bias owner and the epoch are both still current. | |
| 5510 // Note that because there is no current thread register on x86 we | |
| 5511 // need to store off the mark word we read out of the object to | |
| 5512 // avoid reloading it and needing to recheck invariants below. This | |
| 5513 // store is unfortunate but it makes the overall code shorter and | |
| 5514 // simpler. | |
| 5515 movl(saved_mark_addr, swap_reg); | |
| 5516 if (need_tmp_reg) { | |
| 5517 push(tmp_reg); | |
| 5518 } | |
| 5519 get_thread(tmp_reg); | |
| 5520 xorl(swap_reg, tmp_reg); | |
| 5521 if (swap_reg_contains_mark) { | |
| 5522 null_check_offset = offset(); | |
| 5523 } | |
| 5524 movl(tmp_reg, klass_addr); | |
|
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|
5525 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
| 304 | 5526 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); |
| 5527 if (need_tmp_reg) { | |
| 5528 pop(tmp_reg); | |
| 5529 } | |
| 5530 if (counters != NULL) { | |
| 5531 cond_inc32(Assembler::zero, | |
| 5532 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 5533 } | |
| 5534 jcc(Assembler::equal, done); | |
| 5535 | |
| 5536 Label try_revoke_bias; | |
| 5537 Label try_rebias; | |
| 5538 | |
| 5539 // At this point we know that the header has the bias pattern and | |
| 5540 // that we are not the bias owner in the current epoch. We need to | |
| 5541 // figure out more details about the state of the header in order to | |
| 5542 // know what operations can be legally performed on the object's | |
| 5543 // header. | |
| 5544 | |
| 5545 // If the low three bits in the xor result aren't clear, that means | |
| 5546 // the prototype header is no longer biased and we have to revoke | |
| 5547 // the bias on this object. | |
| 5548 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5549 jcc(Assembler::notZero, try_revoke_bias); | |
| 5550 | |
| 5551 // Biasing is still enabled for this data type. See whether the | |
| 5552 // epoch of the current bias is still valid, meaning that the epoch | |
| 5553 // bits of the mark word are equal to the epoch bits of the | |
| 5554 // prototype header. (Note that the prototype header's epoch bits | |
| 5555 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5556 // toward the current thread. Note that we must be absolutely sure | |
| 5557 // that the current epoch is invalid in order to do this because | |
| 5558 // otherwise the manipulations it performs on the mark word are | |
| 5559 // illegal. | |
| 5560 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 5561 jcc(Assembler::notZero, try_rebias); | |
| 5562 | |
| 5563 // The epoch of the current bias is still valid but we know nothing | |
| 5564 // about the owner; it might be set or it might be clear. Try to | |
| 5565 // acquire the bias of the object using an atomic operation. If this | |
| 5566 // fails we will go in to the runtime to revoke the object's bias. | |
| 5567 // Note that we first construct the presumed unbiased header so we | |
| 5568 // don't accidentally blow away another thread's valid bias. | |
| 5569 movl(swap_reg, saved_mark_addr); | |
| 5570 andl(swap_reg, | |
| 5571 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5572 if (need_tmp_reg) { | |
| 5573 push(tmp_reg); | |
| 5574 } | |
| 5575 get_thread(tmp_reg); | |
| 5576 orl(tmp_reg, swap_reg); | |
| 5577 if (os::is_MP()) { | |
| 5578 lock(); | |
| 5579 } | |
| 5580 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 5581 if (need_tmp_reg) { | |
| 5582 pop(tmp_reg); | |
| 5583 } | |
| 5584 // If the biasing toward our thread failed, this means that | |
| 5585 // another thread succeeded in biasing it toward itself and we | |
| 5586 // need to revoke that bias. The revocation will occur in the | |
| 5587 // interpreter runtime in the slow case. | |
| 5588 if (counters != NULL) { | |
| 5589 cond_inc32(Assembler::zero, | |
| 5590 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 5591 } | |
| 5592 if (slow_case != NULL) { | |
| 5593 jcc(Assembler::notZero, *slow_case); | |
| 5594 } | |
| 5595 jmp(done); | |
| 5596 | |
| 5597 bind(try_rebias); | |
| 5598 // At this point we know the epoch has expired, meaning that the | |
| 5599 // current "bias owner", if any, is actually invalid. Under these | |
| 5600 // circumstances _only_, we are allowed to use the current header's | |
| 5601 // value as the comparison value when doing the cas to acquire the | |
| 5602 // bias in the current epoch. In other words, we allow transfer of | |
| 5603 // the bias from one thread to another directly in this situation. | |
| 5604 // | |
| 5605 // FIXME: due to a lack of registers we currently blow away the age | |
| 5606 // bits in this situation. Should attempt to preserve them. | |
| 5607 if (need_tmp_reg) { | |
| 5608 push(tmp_reg); | |
| 5609 } | |
| 5610 get_thread(tmp_reg); | |
| 5611 movl(swap_reg, klass_addr); | |
|
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5612 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset())); |
| 304 | 5613 movl(swap_reg, saved_mark_addr); |
| 5614 if (os::is_MP()) { | |
| 5615 lock(); | |
| 5616 } | |
| 5617 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 5618 if (need_tmp_reg) { | |
| 5619 pop(tmp_reg); | |
| 5620 } | |
| 5621 // If the biasing toward our thread failed, then another thread | |
| 5622 // succeeded in biasing it toward itself and we need to revoke that | |
| 5623 // bias. The revocation will occur in the runtime in the slow case. | |
| 5624 if (counters != NULL) { | |
| 5625 cond_inc32(Assembler::zero, | |
| 5626 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 5627 } | |
| 5628 if (slow_case != NULL) { | |
| 5629 jcc(Assembler::notZero, *slow_case); | |
| 5630 } | |
| 5631 jmp(done); | |
| 5632 | |
| 5633 bind(try_revoke_bias); | |
| 5634 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5635 // more, indicating that objects of this data type are not supposed | |
| 5636 // to be biased any more. We are going to try to reset the mark of | |
| 5637 // this object to the prototype value and fall through to the | |
| 5638 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5639 // that another thread raced us for the privilege of revoking the | |
| 5640 // bias of this particular object, so it's okay to continue in the | |
| 5641 // normal locking code. | |
| 5642 // | |
| 5643 // FIXME: due to a lack of registers we currently blow away the age | |
| 5644 // bits in this situation. Should attempt to preserve them. | |
| 5645 movl(swap_reg, saved_mark_addr); | |
| 5646 if (need_tmp_reg) { | |
| 5647 push(tmp_reg); | |
| 5648 } | |
| 5649 movl(tmp_reg, klass_addr); | |
|
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5650 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
| 304 | 5651 if (os::is_MP()) { |
| 5652 lock(); | |
| 5653 } | |
| 5654 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 5655 if (need_tmp_reg) { | |
| 5656 pop(tmp_reg); | |
| 5657 } | |
| 5658 // Fall through to the normal CAS-based lock, because no matter what | |
| 5659 // the result of the above CAS, some thread must have succeeded in | |
| 5660 // removing the bias bit from the object's header. | |
| 5661 if (counters != NULL) { | |
| 5662 cond_inc32(Assembler::zero, | |
| 5663 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 5664 } | |
| 5665 | |
| 5666 bind(cas_label); | |
| 5667 | |
| 5668 return null_check_offset; | |
| 5669 } | |
| 5670 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 5671 int number_of_arguments) { | |
| 5672 call(RuntimeAddress(entry_point)); | |
| 5673 increment(rsp, number_of_arguments * wordSize); | |
| 5674 } | |
| 5675 | |
|
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5676 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { |
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5677 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); |
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5678 } |
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5679 |
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5680 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { |
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5681 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); |
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5682 } |
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5683 |
| 304 | 5684 void MacroAssembler::cmpoop(Address src1, jobject obj) { |
| 5685 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5686 } | |
| 5687 | |
| 5688 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 5689 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5690 } | |
| 5691 | |
| 5692 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 5693 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 5694 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 5695 cdql(); | |
| 5696 } else { | |
| 5697 movl(hi, lo); | |
| 5698 sarl(hi, 31); | |
| 5699 } | |
| 5700 } | |
| 5701 | |
| 5702 void MacroAssembler::jC2(Register tmp, Label& L) { | |
| 5703 // set parity bit if FPU flag C2 is set (via rax) | |
| 5704 save_rax(tmp); | |
| 5705 fwait(); fnstsw_ax(); | |
| 5706 sahf(); | |
| 5707 restore_rax(tmp); | |
| 5708 // branch | |
| 5709 jcc(Assembler::parity, L); | |
| 5710 } | |
| 5711 | |
| 5712 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 5713 // set parity bit if FPU flag C2 is set (via rax) | |
| 5714 save_rax(tmp); | |
| 5715 fwait(); fnstsw_ax(); | |
| 5716 sahf(); | |
| 5717 restore_rax(tmp); | |
| 5718 // branch | |
| 5719 jcc(Assembler::noParity, L); | |
| 5720 } | |
| 5721 | |
| 0 | 5722 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 5723 // to be installed in the Address class | |
| 5724 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5725 jmp(as_Address(entry)); | |
| 5726 } | |
| 5727 | |
| 304 | 5728 // Note: y_lo will be destroyed |
| 5729 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5730 // Long compare for Java (semantics as described in JVM spec.) | |
| 5731 Label high, low, done; | |
| 5732 | |
| 5733 cmpl(x_hi, y_hi); | |
| 5734 jcc(Assembler::less, low); | |
| 5735 jcc(Assembler::greater, high); | |
| 5736 // x_hi is the return register | |
| 5737 xorl(x_hi, x_hi); | |
| 5738 cmpl(x_lo, y_lo); | |
| 5739 jcc(Assembler::below, low); | |
| 5740 jcc(Assembler::equal, done); | |
| 5741 | |
| 5742 bind(high); | |
| 5743 xorl(x_hi, x_hi); | |
| 5744 increment(x_hi); | |
| 5745 jmp(done); | |
| 5746 | |
| 5747 bind(low); | |
| 5748 xorl(x_hi, x_hi); | |
| 5749 decrementl(x_hi); | |
| 5750 | |
| 5751 bind(done); | |
| 5752 } | |
| 5753 | |
| 5754 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5755 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 5756 } |
| 5757 | |
| 5758 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5759 // leal(dst, as_Address(adr)); | |
| 304 | 5760 // see note in movl as to why we must use a move |
| 0 | 5761 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 5762 } | |
| 5763 | |
| 5764 void MacroAssembler::leave() { | |
| 304 | 5765 mov(rsp, rbp); |
| 5766 pop(rbp); | |
| 5767 } | |
| 0 | 5768 |
| 5769 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 5770 // Multiplication of two Java long values stored on the stack | |
| 5771 // as illustrated below. Result is in rdx:rax. | |
| 5772 // | |
| 5773 // rsp ---> [ ?? ] \ \ | |
| 5774 // .... | y_rsp_offset | | |
| 5775 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 5776 // [ y_hi ] | (in bytes) | |
| 5777 // .... | | |
| 5778 // [ x_lo ] / | |
| 5779 // [ x_hi ] | |
| 5780 // .... | |
| 5781 // | |
| 5782 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 5783 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 5784 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 5785 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 5786 Label quick; | |
| 5787 // load x_hi, y_hi and check if quick | |
| 5788 // multiplication is possible | |
| 5789 movl(rbx, x_hi); | |
| 5790 movl(rcx, y_hi); | |
| 5791 movl(rax, rbx); | |
| 5792 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 5793 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 5794 // do full multiplication | |
| 5795 // 1st step | |
| 5796 mull(y_lo); // x_hi * y_lo | |
| 5797 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 5798 // 2nd step | |
| 5799 movl(rax, x_lo); | |
| 5800 mull(rcx); // x_lo * y_hi | |
| 5801 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 5802 // 3rd step | |
| 5803 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 5804 movl(rax, x_lo); | |
| 5805 mull(y_lo); // x_lo * y_lo | |
| 5806 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 5807 } | |
| 5808 | |
| 304 | 5809 void MacroAssembler::lneg(Register hi, Register lo) { |
| 5810 negl(lo); | |
| 5811 adcl(hi, 0); | |
| 5812 negl(hi); | |
| 5813 } | |
| 0 | 5814 |
| 5815 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 5816 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 5817 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 5818 // shift value is in rcx ! | |
| 5819 assert(hi != rcx, "must not use rcx"); | |
| 5820 assert(lo != rcx, "must not use rcx"); | |
| 5821 const Register s = rcx; // shift count | |
| 5822 const int n = BitsPerWord; | |
| 5823 Label L; | |
| 5824 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 5825 cmpl(s, n); // if (s < n) | |
| 5826 jcc(Assembler::less, L); // else (s >= n) | |
| 5827 movl(hi, lo); // x := x << n | |
| 5828 xorl(lo, lo); | |
| 5829 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 5830 bind(L); // s (mod n) < n | |
| 5831 shldl(hi, lo); // x := x << s | |
| 5832 shll(lo); | |
| 5833 } | |
| 5834 | |
| 5835 | |
| 5836 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 5837 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 5838 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 5839 assert(hi != rcx, "must not use rcx"); | |
| 5840 assert(lo != rcx, "must not use rcx"); | |
| 5841 const Register s = rcx; // shift count | |
| 5842 const int n = BitsPerWord; | |
| 5843 Label L; | |
| 5844 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 5845 cmpl(s, n); // if (s < n) | |
| 5846 jcc(Assembler::less, L); // else (s >= n) | |
| 5847 movl(lo, hi); // x := x >> n | |
| 5848 if (sign_extension) sarl(hi, 31); | |
| 5849 else xorl(hi, hi); | |
| 5850 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 5851 bind(L); // s (mod n) < n | |
| 5852 shrdl(lo, hi); // x := x >> s | |
| 5853 if (sign_extension) sarl(hi); | |
| 5854 else shrl(hi); | |
| 5855 } | |
| 5856 | |
| 304 | 5857 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 5858 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5859 } | |
| 5860 | |
| 5861 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5862 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5863 } | |
| 5864 | |
|
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5865 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { |
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5866 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); |
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5867 } |
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5868 |
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5869 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { |
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5870 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); |
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5871 } |
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5872 |
| 304 | 5873 void MacroAssembler::movptr(Register dst, AddressLiteral src) { |
| 5874 if (src.is_lval()) { | |
| 5875 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 5876 } else { | |
| 5877 movl(dst, as_Address(src)); | |
| 5878 } | |
| 5879 } | |
| 5880 | |
| 5881 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5882 movl(as_Address(dst), src); | |
| 5883 } | |
| 5884 | |
| 5885 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5886 movl(dst, as_Address(src)); | |
| 5887 } | |
| 5888 | |
| 5889 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5890 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5891 movl(dst, src); | |
| 5892 } | |
| 5893 | |
| 5894 | |
| 5895 void MacroAssembler::pop_callee_saved_registers() { | |
| 5896 pop(rcx); | |
| 5897 pop(rdx); | |
| 5898 pop(rdi); | |
| 5899 pop(rsi); | |
| 5900 } | |
| 5901 | |
| 5902 void MacroAssembler::pop_fTOS() { | |
| 5903 fld_d(Address(rsp, 0)); | |
| 5904 addl(rsp, 2 * wordSize); | |
| 5905 } | |
| 5906 | |
| 5907 void MacroAssembler::push_callee_saved_registers() { | |
| 5908 push(rsi); | |
| 5909 push(rdi); | |
| 5910 push(rdx); | |
| 5911 push(rcx); | |
| 5912 } | |
| 5913 | |
| 5914 void MacroAssembler::push_fTOS() { | |
| 5915 subl(rsp, 2 * wordSize); | |
| 5916 fstp_d(Address(rsp, 0)); | |
| 5917 } | |
| 5918 | |
| 5919 | |
| 5920 void MacroAssembler::pushoop(jobject obj) { | |
| 5921 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5922 } | |
| 5923 | |
|
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5924 void MacroAssembler::pushklass(Metadata* obj) { |
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5925 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); |
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5926 } |
| 304 | 5927 |
| 5928 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5929 if (src.is_lval()) { | |
| 5930 push_literal32((int32_t)src.target(), src.rspec()); | |
| 5931 } else { | |
| 5932 pushl(as_Address(src)); | |
| 5933 } | |
| 5934 } | |
| 5935 | |
| 5936 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 5937 xorl(dst, dst); | |
| 5938 set_byte_if_not_zero(dst); | |
| 5939 } | |
| 5940 | |
| 5941 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5942 masm->push(arg); | |
| 5943 } | |
| 5944 | |
| 5945 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5946 masm->push(arg); | |
| 5947 } | |
| 5948 | |
| 5949 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5950 masm->push(arg); | |
| 5951 } | |
| 5952 | |
| 5953 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5954 masm->push(arg); | |
| 5955 } | |
| 5956 | |
| 5957 #ifndef PRODUCT | |
| 5958 extern "C" void findpc(intptr_t x); | |
| 5959 #endif | |
| 5960 | |
| 5961 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 5962 // In order to get locks to work, we need to fake a in_VM state | |
| 5963 JavaThread* thread = JavaThread::current(); | |
| 5964 JavaThreadState saved_state = thread->thread_state(); | |
| 5965 thread->set_thread_state(_thread_in_vm); | |
| 5966 if (ShowMessageBoxOnError) { | |
| 5967 JavaThread* thread = JavaThread::current(); | |
| 5968 JavaThreadState saved_state = thread->thread_state(); | |
| 5969 thread->set_thread_state(_thread_in_vm); | |
| 5970 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5971 ttyLocker ttyl; | |
| 5972 BytecodeCounter::print(); | |
| 5973 } | |
| 5974 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5975 // This is the value of eip which points to where verify_oop will return. | |
| 5976 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
|
6266
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5977 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); |
| 304 | 5978 BREAKPOINT; |
| 5979 } | |
| 5980 } else { | |
| 5981 ttyLocker ttyl; | |
| 5982 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
|
6725
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5983 } |
|
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5984 // Don't assert holding the ttyLock |
|
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5985 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 5986 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 5987 } | |
| 5988 | |
|
6266
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5989 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { |
|
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5990 ttyLocker ttyl; |
|
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5991 FlagSetting fs(Debugging, true); |
|
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5992 tty->print_cr("eip = 0x%08x", eip); |
|
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5993 #ifndef PRODUCT |
|
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5994 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
|
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5995 tty->cr(); |
|
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5996 findpc(eip); |
|
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5997 tty->cr(); |
|
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5998 } |
|
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5999 #endif |
|
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|
6000 #define PRINT_REG(rax) \ |
|
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6001 { tty->print("%s = ", #rax); os::print_location(tty, rax); } |
|
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6002 PRINT_REG(rax); |
|
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6003 PRINT_REG(rbx); |
|
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6004 PRINT_REG(rcx); |
|
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6005 PRINT_REG(rdx); |
|
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|
6006 PRINT_REG(rdi); |
|
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6007 PRINT_REG(rsi); |
|
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|
6008 PRINT_REG(rbp); |
|
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6009 PRINT_REG(rsp); |
|
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6010 #undef PRINT_REG |
|
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|
6011 // Print some words near top of staack. |
|
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6012 int* dump_sp = (int*) rsp; |
|
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6013 for (int col1 = 0; col1 < 8; col1++) { |
|
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6014 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); |
|
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|
6015 os::print_location(tty, *dump_sp++); |
|
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6016 } |
|
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|
6017 for (int row = 0; row < 16; row++) { |
|
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|
6018 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); |
|
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6019 for (int col = 0; col < 8; col++) { |
|
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6020 tty->print(" 0x%08x", *dump_sp++); |
|
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6021 } |
|
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|
6022 tty->cr(); |
|
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|
6023 } |
|
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|
6024 // Print some instructions around pc: |
|
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6025 Disassembler::decode((address)eip-64, (address)eip); |
|
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6026 tty->print_cr("--------"); |
|
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6027 Disassembler::decode((address)eip, (address)eip+32); |
|
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|
6028 } |
|
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|
6029 |
| 304 | 6030 void MacroAssembler::stop(const char* msg) { |
| 6031 ExternalAddress message((address)msg); | |
| 6032 // push address of message | |
| 6033 pushptr(message.addr()); | |
| 6034 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
|
6266
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6035 pusha(); // push registers |
| 304 | 6036 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); |
| 6037 hlt(); | |
| 6038 } | |
| 6039 | |
| 6040 void MacroAssembler::warn(const char* msg) { | |
| 6041 push_CPU_state(); | |
| 6042 | |
| 6043 ExternalAddress message((address) msg); | |
| 6044 // push address of message | |
| 6045 pushptr(message.addr()); | |
| 6046 | |
| 6047 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 6048 addl(rsp, wordSize); // discard argument | |
| 6049 pop_CPU_state(); | |
| 6050 } | |
| 6051 | |
|
6266
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6052 void MacroAssembler::print_state() { |
|
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6053 { Label L; call(L, relocInfo::none); bind(L); } // push eip |
|
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|
6054 pusha(); // push registers |
|
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|
6055 |
|
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|
6056 push_CPU_state(); |
|
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|
6057 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); |
|
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|
6058 pop_CPU_state(); |
|
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|
6059 |
|
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|
6060 popa(); |
|
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|
6061 addl(rsp, wordSize); |
|
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|
6062 } |
|
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|
6063 |
| 304 | 6064 #else // _LP64 |
| 6065 | |
| 6066 // 64 bit versions | |
| 6067 | |
| 6068 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 6069 // amd64 always does this as a pc-rel | |
| 6070 // we can be absolute or disp based on the instruction type | |
| 6071 // jmp/call are displacements others are absolute | |
| 6072 assert(!adr.is_lval(), "must be rval"); | |
| 6073 assert(reachable(adr), "must be"); | |
| 6074 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 6075 | |
| 6076 } | |
| 6077 | |
| 6078 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 6079 AddressLiteral base = adr.base(); | |
| 6080 lea(rscratch1, base); | |
| 6081 Address index = adr.index(); | |
| 6082 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 6083 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 6084 return array; | |
| 6085 } | |
| 6086 | |
| 6087 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 6088 Register obj_reg, | |
| 6089 Register swap_reg, | |
| 6090 Register tmp_reg, | |
| 6091 bool swap_reg_contains_mark, | |
| 6092 Label& done, | |
| 6093 Label* slow_case, | |
| 6094 BiasedLockingCounters* counters) { | |
| 6095 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 6096 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 6097 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 6098 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 6099 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 6100 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 6101 Address saved_mark_addr(lock_reg, 0); | |
| 6102 | |
| 6103 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 6104 counters = BiasedLocking::counters(); | |
| 6105 | |
| 6106 // Biased locking | |
| 6107 // See whether the lock is currently biased toward our thread and | |
| 6108 // whether the epoch is still valid | |
| 6109 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 6110 // pointers to allow age to be placed into low bits | |
| 6111 // First check to see whether biasing is even enabled for this object | |
| 6112 Label cas_label; | |
| 6113 int null_check_offset = -1; | |
| 6114 if (!swap_reg_contains_mark) { | |
| 6115 null_check_offset = offset(); | |
| 6116 movq(swap_reg, mark_addr); | |
| 6117 } | |
| 6118 movq(tmp_reg, swap_reg); | |
| 6119 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 6120 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 6121 jcc(Assembler::notEqual, cas_label); | |
| 6122 // The bias pattern is present in the object's header. Need to check | |
| 6123 // whether the bias owner and the epoch are both still current. | |
| 6124 load_prototype_header(tmp_reg, obj_reg); | |
| 6125 orq(tmp_reg, r15_thread); | |
| 6126 xorq(tmp_reg, swap_reg); | |
| 6127 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 6128 if (counters != NULL) { | |
| 6129 cond_inc32(Assembler::zero, | |
| 6130 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 6131 } | |
| 0 | 6132 jcc(Assembler::equal, done); |
| 6133 | |
| 304 | 6134 Label try_revoke_bias; |
| 6135 Label try_rebias; | |
| 6136 | |
| 6137 // At this point we know that the header has the bias pattern and | |
| 6138 // that we are not the bias owner in the current epoch. We need to | |
| 6139 // figure out more details about the state of the header in order to | |
| 6140 // know what operations can be legally performed on the object's | |
| 6141 // header. | |
| 6142 | |
| 6143 // If the low three bits in the xor result aren't clear, that means | |
| 6144 // the prototype header is no longer biased and we have to revoke | |
| 6145 // the bias on this object. | |
| 6146 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 6147 jcc(Assembler::notZero, try_revoke_bias); | |
| 6148 | |
| 6149 // Biasing is still enabled for this data type. See whether the | |
| 6150 // epoch of the current bias is still valid, meaning that the epoch | |
| 6151 // bits of the mark word are equal to the epoch bits of the | |
| 6152 // prototype header. (Note that the prototype header's epoch bits | |
| 6153 // only change at a safepoint.) If not, attempt to rebias the object | |
| 6154 // toward the current thread. Note that we must be absolutely sure | |
| 6155 // that the current epoch is invalid in order to do this because | |
| 6156 // otherwise the manipulations it performs on the mark word are | |
| 6157 // illegal. | |
| 6158 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 6159 jcc(Assembler::notZero, try_rebias); | |
| 6160 | |
| 6161 // The epoch of the current bias is still valid but we know nothing | |
| 6162 // about the owner; it might be set or it might be clear. Try to | |
| 6163 // acquire the bias of the object using an atomic operation. If this | |
| 6164 // fails we will go in to the runtime to revoke the object's bias. | |
| 6165 // Note that we first construct the presumed unbiased header so we | |
| 6166 // don't accidentally blow away another thread's valid bias. | |
| 6167 andq(swap_reg, | |
| 6168 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 6169 movq(tmp_reg, swap_reg); | |
| 6170 orq(tmp_reg, r15_thread); | |
| 6171 if (os::is_MP()) { | |
| 6172 lock(); | |
| 6173 } | |
| 6174 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 6175 // If the biasing toward our thread failed, this means that | |
| 6176 // another thread succeeded in biasing it toward itself and we | |
| 6177 // need to revoke that bias. The revocation will occur in the | |
| 6178 // interpreter runtime in the slow case. | |
| 6179 if (counters != NULL) { | |
| 6180 cond_inc32(Assembler::zero, | |
| 6181 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 6182 } | |
| 6183 if (slow_case != NULL) { | |
| 6184 jcc(Assembler::notZero, *slow_case); | |
| 6185 } | |
| 0 | 6186 jmp(done); |
| 6187 | |
| 304 | 6188 bind(try_rebias); |
| 6189 // At this point we know the epoch has expired, meaning that the | |
| 6190 // current "bias owner", if any, is actually invalid. Under these | |
| 6191 // circumstances _only_, we are allowed to use the current header's | |
| 6192 // value as the comparison value when doing the cas to acquire the | |
| 6193 // bias in the current epoch. In other words, we allow transfer of | |
| 6194 // the bias from one thread to another directly in this situation. | |
| 6195 // | |
| 6196 // FIXME: due to a lack of registers we currently blow away the age | |
| 6197 // bits in this situation. Should attempt to preserve them. | |
| 6198 load_prototype_header(tmp_reg, obj_reg); | |
| 6199 orq(tmp_reg, r15_thread); | |
| 6200 if (os::is_MP()) { | |
| 6201 lock(); | |
| 6202 } | |
| 6203 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 6204 // If the biasing toward our thread failed, then another thread | |
| 6205 // succeeded in biasing it toward itself and we need to revoke that | |
| 6206 // bias. The revocation will occur in the runtime in the slow case. | |
| 6207 if (counters != NULL) { | |
| 6208 cond_inc32(Assembler::zero, | |
| 6209 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 6210 } | |
| 6211 if (slow_case != NULL) { | |
| 6212 jcc(Assembler::notZero, *slow_case); | |
| 0 | 6213 } |
| 6214 jmp(done); | |
| 6215 | |
| 304 | 6216 bind(try_revoke_bias); |
| 6217 // The prototype mark in the klass doesn't have the bias bit set any | |
| 6218 // more, indicating that objects of this data type are not supposed | |
| 6219 // to be biased any more. We are going to try to reset the mark of | |
| 6220 // this object to the prototype value and fall through to the | |
| 6221 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 6222 // that another thread raced us for the privilege of revoking the | |
| 6223 // bias of this particular object, so it's okay to continue in the | |
| 6224 // normal locking code. | |
| 6225 // | |
| 6226 // FIXME: due to a lack of registers we currently blow away the age | |
| 6227 // bits in this situation. Should attempt to preserve them. | |
| 6228 load_prototype_header(tmp_reg, obj_reg); | |
| 6229 if (os::is_MP()) { | |
| 6230 lock(); | |
| 6231 } | |
| 6232 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 6233 // Fall through to the normal CAS-based lock, because no matter what | |
| 6234 // the result of the above CAS, some thread must have succeeded in | |
| 6235 // removing the bias bit from the object's header. | |
| 6236 if (counters != NULL) { | |
| 6237 cond_inc32(Assembler::zero, | |
| 6238 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 6239 } | |
| 6240 | |
| 6241 bind(cas_label); | |
| 6242 | |
| 6243 return null_check_offset; | |
| 6244 } | |
| 6245 | |
| 6246 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 6247 Label L, E; | |
| 6248 | |
| 6249 #ifdef _WIN64 | |
| 6250 // Windows always allocates space for it's register args | |
| 6251 assert(num_args <= 4, "only register arguments supported"); | |
| 6252 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 6253 #endif | |
| 6254 | |
| 6255 // Align stack if necessary | |
| 6256 testl(rsp, 15); | |
| 6257 jcc(Assembler::zero, L); | |
| 6258 | |
| 6259 subq(rsp, 8); | |
| 6260 { | |
| 6261 call(RuntimeAddress(entry_point)); | |
| 6262 } | |
| 6263 addq(rsp, 8); | |
| 6264 jmp(E); | |
| 6265 | |
| 6266 bind(L); | |
| 6267 { | |
| 6268 call(RuntimeAddress(entry_point)); | |
| 6269 } | |
| 6270 | |
| 6271 bind(E); | |
| 6272 | |
| 6273 #ifdef _WIN64 | |
| 6274 // restore stack pointer | |
| 6275 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 6276 #endif | |
| 6277 | |
| 6278 } | |
| 6279 | |
| 6280 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 6281 assert(!src2.is_lval(), "should use cmpptr"); | |
| 6282 | |
| 6283 if (reachable(src2)) { | |
| 6284 cmpq(src1, as_Address(src2)); | |
| 6285 } else { | |
| 6286 lea(rscratch1, src2); | |
| 6287 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 6288 } | |
| 6289 } | |
| 6290 | |
| 6291 int MacroAssembler::corrected_idivq(Register reg) { | |
| 6292 // Full implementation of Java ldiv and lrem; checks for special | |
| 6293 // case as described in JVM spec., p.243 & p.271. The function | |
| 6294 // returns the (pc) offset of the idivl instruction - may be needed | |
| 6295 // for implicit exceptions. | |
| 6296 // | |
| 6297 // normal case special case | |
| 6298 // | |
| 6299 // input : rax: dividend min_long | |
| 6300 // reg: divisor (may not be eax/edx) -1 | |
| 6301 // | |
| 6302 // output: rax: quotient (= rax idiv reg) min_long | |
| 6303 // rdx: remainder (= rax irem reg) 0 | |
| 6304 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 6305 static const int64_t min_long = 0x8000000000000000; | |
| 6306 Label normal_case, special_case; | |
| 6307 | |
| 6308 // check for special case | |
| 6309 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 6310 jcc(Assembler::notEqual, normal_case); | |
| 6311 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 6312 // remainder = 0) | |
| 6313 cmpq(reg, -1); | |
| 6314 jcc(Assembler::equal, special_case); | |
| 6315 | |
| 6316 // handle normal case | |
| 6317 bind(normal_case); | |
| 6318 cdqq(); | |
| 6319 int idivq_offset = offset(); | |
| 6320 idivq(reg); | |
| 6321 | |
| 6322 // normal and special case exit | |
| 6323 bind(special_case); | |
| 6324 | |
| 6325 return idivq_offset; | |
| 6326 } | |
| 6327 | |
| 6328 void MacroAssembler::decrementq(Register reg, int value) { | |
| 6329 if (value == min_jint) { subq(reg, value); return; } | |
| 6330 if (value < 0) { incrementq(reg, -value); return; } | |
| 6331 if (value == 0) { ; return; } | |
| 6332 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 6333 /* else */ { subq(reg, value) ; return; } | |
| 6334 } | |
| 6335 | |
| 6336 void MacroAssembler::decrementq(Address dst, int value) { | |
| 6337 if (value == min_jint) { subq(dst, value); return; } | |
| 6338 if (value < 0) { incrementq(dst, -value); return; } | |
| 6339 if (value == 0) { ; return; } | |
| 6340 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 6341 /* else */ { subq(dst, value) ; return; } | |
| 6342 } | |
| 6343 | |
| 6344 void MacroAssembler::incrementq(Register reg, int value) { | |
| 6345 if (value == min_jint) { addq(reg, value); return; } | |
| 6346 if (value < 0) { decrementq(reg, -value); return; } | |
| 6347 if (value == 0) { ; return; } | |
| 6348 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 6349 /* else */ { addq(reg, value) ; return; } | |
| 6350 } | |
| 6351 | |
| 6352 void MacroAssembler::incrementq(Address dst, int value) { | |
| 6353 if (value == min_jint) { addq(dst, value); return; } | |
| 6354 if (value < 0) { decrementq(dst, -value); return; } | |
| 6355 if (value == 0) { ; return; } | |
| 6356 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 6357 /* else */ { addq(dst, value) ; return; } | |
| 6358 } | |
| 6359 | |
| 6360 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 6361 // to be installed in the Address class | |
| 6362 void MacroAssembler::jump(ArrayAddress entry) { | |
| 6363 lea(rscratch1, entry.base()); | |
| 6364 Address dispatch = entry.index(); | |
| 6365 assert(dispatch._base == noreg, "must be"); | |
| 6366 dispatch._base = rscratch1; | |
| 6367 jmp(dispatch); | |
| 6368 } | |
| 6369 | |
| 6370 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 6371 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 6372 cmpq(x_lo, y_lo); | |
| 6373 } | |
| 6374 | |
| 6375 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 6376 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 6377 } | |
| 6378 | |
| 6379 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 6380 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 6381 movptr(dst, rscratch1); | |
| 6382 } | |
| 6383 | |
| 6384 void MacroAssembler::leave() { | |
| 6385 // %%% is this really better? Why not on 32bit too? | |
| 6386 emit_byte(0xC9); // LEAVE | |
| 6387 } | |
| 6388 | |
| 6389 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 6390 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 6391 negq(lo); | |
| 6392 } | |
| 6393 | |
| 6394 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 6395 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 6396 } | |
| 6397 | |
| 6398 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 6399 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 6400 movq(dst, rscratch1); | |
| 6401 } | |
| 6402 | |
|
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6403 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { |
|
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6404 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); |
|
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|
6405 } |
|
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|
6406 |
|
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|
6407 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { |
|
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|
6408 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); |
|
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|
6409 movq(dst, rscratch1); |
|
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|
6410 } |
|
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|
6411 |
| 304 | 6412 void MacroAssembler::movptr(Register dst, AddressLiteral src) { |
| 6413 if (src.is_lval()) { | |
| 6414 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 6415 } else { | |
| 6416 if (reachable(src)) { | |
| 6417 movq(dst, as_Address(src)); | |
| 6418 } else { | |
| 6419 lea(rscratch1, src); | |
| 6420 movq(dst, Address(rscratch1,0)); | |
| 0 | 6421 } |
| 304 | 6422 } |
| 6423 } | |
| 6424 | |
| 6425 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 6426 movq(as_Address(dst), src); | |
| 6427 } | |
| 6428 | |
| 6429 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 6430 movq(dst, as_Address(src)); | |
| 6431 } | |
| 6432 | |
| 6433 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 6434 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 6435 mov64(rscratch1, src); | |
| 6436 movq(dst, rscratch1); | |
| 6437 } | |
| 6438 | |
| 6439 // These are mostly for initializing NULL | |
| 6440 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 6441 movslq(dst, src); | |
| 6442 } | |
| 6443 | |
| 6444 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 6445 mov64(dst, (intptr_t)src); | |
| 6446 } | |
| 6447 | |
| 6448 void MacroAssembler::pushoop(jobject obj) { | |
| 6449 movoop(rscratch1, obj); | |
| 6450 push(rscratch1); | |
| 6451 } | |
| 6452 | |
|
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|
6453 void MacroAssembler::pushklass(Metadata* obj) { |
|
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|
6454 mov_metadata(rscratch1, obj); |
|
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|
6455 push(rscratch1); |
|
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|
6456 } |
|
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|
6457 |
| 304 | 6458 void MacroAssembler::pushptr(AddressLiteral src) { |
| 6459 lea(rscratch1, src); | |
| 6460 if (src.is_lval()) { | |
| 6461 push(rscratch1); | |
| 6462 } else { | |
| 6463 pushq(Address(rscratch1, 0)); | |
| 6464 } | |
| 6465 } | |
| 6466 | |
| 6467 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 6468 bool clear_pc) { | |
| 6469 // we must set sp to zero to clear frame | |
|
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|
6470 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 6471 // must clear fp, so that compiled frames are not confused; it is |
| 6472 // possible that we need it only for debugging | |
| 6473 if (clear_fp) { | |
|
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|
6474 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 6475 } |
| 6476 | |
| 6477 if (clear_pc) { | |
|
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|
6478 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 6479 } |
| 6480 } | |
| 6481 | |
| 6482 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 6483 Register last_java_fp, | |
| 6484 address last_java_pc) { | |
| 6485 // determine last_java_sp register | |
| 6486 if (!last_java_sp->is_valid()) { | |
| 6487 last_java_sp = rsp; | |
| 6488 } | |
| 6489 | |
| 6490 // last_java_fp is optional | |
| 6491 if (last_java_fp->is_valid()) { | |
| 6492 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 6493 last_java_fp); | |
| 6494 } | |
| 6495 | |
| 6496 // last_java_pc is optional | |
| 6497 if (last_java_pc != NULL) { | |
| 6498 Address java_pc(r15_thread, | |
| 6499 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 6500 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 6501 movptr(java_pc, rscratch1); | |
| 6502 } | |
| 6503 | |
| 6504 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 6505 } | |
| 6506 | |
| 6507 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 6508 if (c_rarg0 != arg ) { | |
| 6509 masm->mov(c_rarg0, arg); | |
| 6510 } | |
| 6511 } | |
| 6512 | |
| 6513 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 6514 if (c_rarg1 != arg ) { | |
| 6515 masm->mov(c_rarg1, arg); | |
| 6516 } | |
| 6517 } | |
| 6518 | |
| 6519 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 6520 if (c_rarg2 != arg ) { | |
| 6521 masm->mov(c_rarg2, arg); | |
| 6522 } | |
| 6523 } | |
| 6524 | |
| 6525 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 6526 if (c_rarg3 != arg ) { | |
| 6527 masm->mov(c_rarg3, arg); | |
| 6528 } | |
| 6529 } | |
| 6530 | |
| 6531 void MacroAssembler::stop(const char* msg) { | |
| 6532 address rip = pc(); | |
| 6533 pusha(); // get regs on stack | |
| 6534 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 6535 lea(c_rarg1, InternalAddress(rip)); | |
| 6536 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 6537 andq(rsp, -16); // align stack as required by ABI | |
| 6538 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 6539 hlt(); | |
| 6540 } | |
| 6541 | |
| 6542 void MacroAssembler::warn(const char* msg) { | |
|
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6543 push(rbp); |
|
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|
6544 movq(rbp, rsp); |
| 304 | 6545 andq(rsp, -16); // align stack as required by push_CPU_state and call |
| 6546 push_CPU_state(); // keeps alignment at 16 bytes | |
| 6547 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 6548 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 6549 pop_CPU_state(); | |
|
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|
6550 mov(rsp, rbp); |
|
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|
6551 pop(rbp); |
|
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|
6552 } |
|
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|
6553 |
|
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6554 void MacroAssembler::print_state() { |
|
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|
6555 address rip = pc(); |
|
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|
6556 pusha(); // get regs on stack |
|
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|
6557 push(rbp); |
|
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|
6558 movq(rbp, rsp); |
|
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6559 andq(rsp, -16); // align stack as required by push_CPU_state and call |
|
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6560 push_CPU_state(); // keeps alignment at 16 bytes |
|
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6561 |
|
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6562 lea(c_rarg0, InternalAddress(rip)); |
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6563 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array |
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6564 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); |
|
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6565 |
|
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|
6566 pop_CPU_state(); |
|
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|
6567 mov(rsp, rbp); |
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6568 pop(rbp); |
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|
6569 popa(); |
| 304 | 6570 } |
| 6571 | |
| 6572 #ifndef PRODUCT | |
| 6573 extern "C" void findpc(intptr_t x); | |
| 6574 #endif | |
| 6575 | |
| 6576 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 6577 // In order to get locks to work, we need to fake a in_VM state | |
|
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6578 if (ShowMessageBoxOnError) { |
| 304 | 6579 JavaThread* thread = JavaThread::current(); |
| 6580 JavaThreadState saved_state = thread->thread_state(); | |
| 6581 thread->set_thread_state(_thread_in_vm); | |
| 6582 #ifndef PRODUCT | |
| 6583 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 6584 ttyLocker ttyl; | |
| 6585 BytecodeCounter::print(); | |
| 0 | 6586 } |
| 304 | 6587 #endif |
| 6588 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 6589 // XXX correct this offset for amd64 | |
| 6590 // This is the value of eip which points to where verify_oop will return. | |
| 6591 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
|
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6592 print_state64(pc, regs); |
| 304 | 6593 BREAKPOINT; |
|
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|
6594 assert(false, "start up GDB"); |
| 0 | 6595 } |
| 304 | 6596 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 6597 } else { | |
| 6598 ttyLocker ttyl; | |
| 6599 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 6600 msg); | |
|
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|
6601 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 6602 } |
| 6603 } | |
| 6604 | |
|
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6605 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { |
|
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6606 ttyLocker ttyl; |
|
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6607 FlagSetting fs(Debugging, true); |
|
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6608 tty->print_cr("rip = 0x%016lx", pc); |
|
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|
6609 #ifndef PRODUCT |
|
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|
6610 tty->cr(); |
|
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|
6611 findpc(pc); |
|
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6612 tty->cr(); |
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6613 #endif |
|
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6614 #define PRINT_REG(rax, value) \ |
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6615 { tty->print("%s = ", #rax); os::print_location(tty, value); } |
|
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6616 PRINT_REG(rax, regs[15]); |
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6617 PRINT_REG(rbx, regs[12]); |
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6618 PRINT_REG(rcx, regs[14]); |
|
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6619 PRINT_REG(rdx, regs[13]); |
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6620 PRINT_REG(rdi, regs[8]); |
|
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6621 PRINT_REG(rsi, regs[9]); |
|
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6622 PRINT_REG(rbp, regs[10]); |
|
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6623 PRINT_REG(rsp, regs[11]); |
|
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6624 PRINT_REG(r8 , regs[7]); |
|
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6625 PRINT_REG(r9 , regs[6]); |
|
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6626 PRINT_REG(r10, regs[5]); |
|
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6627 PRINT_REG(r11, regs[4]); |
|
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6628 PRINT_REG(r12, regs[3]); |
|
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6629 PRINT_REG(r13, regs[2]); |
|
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6630 PRINT_REG(r14, regs[1]); |
|
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6631 PRINT_REG(r15, regs[0]); |
|
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6632 #undef PRINT_REG |
|
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6633 // Print some words near top of staack. |
|
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6634 int64_t* rsp = (int64_t*) regs[11]; |
|
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6635 int64_t* dump_sp = rsp; |
|
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6636 for (int col1 = 0; col1 < 8; col1++) { |
|
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6637 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); |
|
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6638 os::print_location(tty, *dump_sp++); |
|
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6639 } |
|
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6640 for (int row = 0; row < 25; row++) { |
|
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6641 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); |
|
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6642 for (int col = 0; col < 4; col++) { |
|
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6643 tty->print(" 0x%016lx", *dump_sp++); |
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6644 } |
|
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|
6645 tty->cr(); |
|
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|
6646 } |
|
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6647 // Print some instructions around pc: |
|
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6648 Disassembler::decode((address)pc-64, (address)pc); |
|
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6649 tty->print_cr("--------"); |
|
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6650 Disassembler::decode((address)pc, (address)pc+32); |
|
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6651 } |
|
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|
6652 |
| 304 | 6653 #endif // _LP64 |
| 6654 | |
| 6655 // Now versions that are common to 32/64 bit | |
| 6656 | |
| 6657 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 6658 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 6659 } | |
| 6660 | |
| 6661 void MacroAssembler::addptr(Register dst, Register src) { | |
| 6662 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 6663 } | |
| 6664 | |
| 6665 void MacroAssembler::addptr(Address dst, Register src) { | |
| 6666 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 6667 } | |
| 6668 | |
| 4759 | 6669 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { |
| 6670 if (reachable(src)) { | |
| 6671 Assembler::addsd(dst, as_Address(src)); | |
| 6672 } else { | |
| 6673 lea(rscratch1, src); | |
| 6674 Assembler::addsd(dst, Address(rscratch1, 0)); | |
| 6675 } | |
| 6676 } | |
| 6677 | |
| 6678 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { | |
| 6679 if (reachable(src)) { | |
| 6680 addss(dst, as_Address(src)); | |
| 6681 } else { | |
| 6682 lea(rscratch1, src); | |
| 6683 addss(dst, Address(rscratch1, 0)); | |
| 6684 } | |
| 6685 } | |
| 6686 | |
| 304 | 6687 void MacroAssembler::align(int modulus) { |
| 6688 if (offset() % modulus != 0) { | |
| 6689 nop(modulus - (offset() % modulus)); | |
| 6690 } | |
| 6691 } | |
| 6692 | |
| 6693 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 4759 | 6694 // Used in sign-masking with aligned address. |
| 6695 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 1060 | 6696 if (reachable(src)) { |
| 4759 | 6697 Assembler::andpd(dst, as_Address(src)); |
| 1060 | 6698 } else { |
| 6699 lea(rscratch1, src); | |
| 4759 | 6700 Assembler::andpd(dst, Address(rscratch1, 0)); |
| 6701 } | |
| 6702 } | |
| 6703 | |
| 6704 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { | |
| 6705 // Used in sign-masking with aligned address. | |
| 6706 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 6707 if (reachable(src)) { | |
| 6708 Assembler::andps(dst, as_Address(src)); | |
| 6709 } else { | |
| 6710 lea(rscratch1, src); | |
| 6711 Assembler::andps(dst, Address(rscratch1, 0)); | |
| 1060 | 6712 } |
| 304 | 6713 } |
| 6714 | |
| 6715 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 6716 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 6717 } | |
| 6718 | |
| 6719 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 6720 pushf(); | |
| 6721 if (os::is_MP()) | |
| 6722 lock(); | |
| 6723 incrementl(counter_addr); | |
| 6724 popf(); | |
| 6725 } | |
| 6726 | |
| 6727 // Writes to stack successive pages until offset reached to check for | |
| 6728 // stack overflow + shadow pages. This clobbers tmp. | |
| 6729 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 6730 movptr(tmp, rsp); | |
| 6731 // Bang stack for total size given plus shadow page size. | |
| 6732 // Bang one page at a time because large size can bang beyond yellow and | |
| 6733 // red zones. | |
| 6734 Label loop; | |
| 6735 bind(loop); | |
| 6736 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 6737 subptr(tmp, os::vm_page_size()); | |
| 6738 subl(size, os::vm_page_size()); | |
| 6739 jcc(Assembler::greater, loop); | |
| 6740 | |
| 6741 // Bang down shadow pages too. | |
| 6742 // The -1 because we already subtracted 1 page. | |
| 6743 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 6744 // this could be any sized move but this is can be a debugging crumb | |
| 6745 // so the bigger the better. | |
| 6746 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 6747 } | |
| 6748 } | |
| 6749 | |
| 6750 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 6751 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 6752 | |
| 6753 // Check for biased locking unlock case, which is a no-op | |
| 6754 // Note: we do not have to check the thread ID for two reasons. | |
| 6755 // First, the interpreter checks for IllegalMonitorStateException at | |
| 6756 // a higher level. Second, if the bias was revoked while we held the | |
| 6757 // lock, the object could not be rebiased toward another thread, so | |
| 6758 // the bias bit would be clear. | |
| 6759 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 6760 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 6761 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 6762 jcc(Assembler::equal, done); | |
| 6763 } | |
| 6764 | |
| 6765 void MacroAssembler::c2bool(Register x) { | |
| 6766 // implements x == 0 ? 0 : 1 | |
| 6767 // note: must only look at least-significant byte of x | |
| 6768 // since C-style booleans are stored in one byte | |
| 6769 // only! (was bug) | |
| 6770 andl(x, 0xFF); | |
| 6771 setb(Assembler::notZero, x); | |
| 6772 } | |
| 6773 | |
| 6774 // Wouldn't need if AddressLiteral version had new name | |
| 6775 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 6776 Assembler::call(L, rtype); | |
| 6777 } | |
| 6778 | |
| 6779 void MacroAssembler::call(Register entry) { | |
| 6780 Assembler::call(entry); | |
| 6781 } | |
| 6782 | |
| 6783 void MacroAssembler::call(AddressLiteral entry) { | |
| 6784 if (reachable(entry)) { | |
| 6785 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 6786 } else { | |
| 6787 lea(rscratch1, entry); | |
| 6788 Assembler::call(rscratch1); | |
| 6789 } | |
| 6790 } | |
| 6791 | |
|
6725
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|
6792 void MacroAssembler::ic_call(address entry) { |
|
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|
6793 RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
|
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6794 movptr(rax, (intptr_t)Universe::non_oop_word()); |
|
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|
6795 call(AddressLiteral(entry, rh)); |
|
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|
6796 } |
|
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|
6797 |
| 304 | 6798 // Implementation of call_VM versions |
| 6799 | |
| 6800 void MacroAssembler::call_VM(Register oop_result, | |
| 6801 address entry_point, | |
| 6802 bool check_exceptions) { | |
| 6803 Label C, E; | |
| 6804 call(C, relocInfo::none); | |
| 6805 jmp(E); | |
| 6806 | |
| 6807 bind(C); | |
| 6808 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 6809 ret(0); | |
| 6810 | |
| 6811 bind(E); | |
| 6812 } | |
| 6813 | |
| 6814 void MacroAssembler::call_VM(Register oop_result, | |
| 6815 address entry_point, | |
| 6816 Register arg_1, | |
| 6817 bool check_exceptions) { | |
| 6818 Label C, E; | |
| 6819 call(C, relocInfo::none); | |
| 6820 jmp(E); | |
| 6821 | |
| 6822 bind(C); | |
| 6823 pass_arg1(this, arg_1); | |
| 6824 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 6825 ret(0); | |
| 6826 | |
| 6827 bind(E); | |
| 6828 } | |
| 6829 | |
| 6830 void MacroAssembler::call_VM(Register oop_result, | |
| 6831 address entry_point, | |
| 6832 Register arg_1, | |
| 6833 Register arg_2, | |
| 6834 bool check_exceptions) { | |
| 6835 Label C, E; | |
| 6836 call(C, relocInfo::none); | |
| 6837 jmp(E); | |
| 6838 | |
| 6839 bind(C); | |
| 6840 | |
| 6841 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6842 | |
| 6843 pass_arg2(this, arg_2); | |
| 6844 pass_arg1(this, arg_1); | |
| 6845 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 6846 ret(0); | |
| 6847 | |
| 6848 bind(E); | |
| 6849 } | |
| 6850 | |
| 6851 void MacroAssembler::call_VM(Register oop_result, | |
| 6852 address entry_point, | |
| 6853 Register arg_1, | |
| 6854 Register arg_2, | |
| 6855 Register arg_3, | |
| 6856 bool check_exceptions) { | |
| 6857 Label C, E; | |
| 6858 call(C, relocInfo::none); | |
| 6859 jmp(E); | |
| 6860 | |
| 6861 bind(C); | |
| 6862 | |
| 6863 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 6864 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 6865 pass_arg3(this, arg_3); | |
| 6866 | |
| 6867 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6868 pass_arg2(this, arg_2); | |
| 6869 | |
| 6870 pass_arg1(this, arg_1); | |
| 6871 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 6872 ret(0); | |
| 6873 | |
| 6874 bind(E); | |
| 6875 } | |
| 6876 | |
| 6877 void MacroAssembler::call_VM(Register oop_result, | |
| 6878 Register last_java_sp, | |
| 6879 address entry_point, | |
| 6880 int number_of_arguments, | |
| 6881 bool check_exceptions) { | |
| 6882 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 6883 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 6884 } | |
| 6885 | |
| 6886 void MacroAssembler::call_VM(Register oop_result, | |
| 6887 Register last_java_sp, | |
| 6888 address entry_point, | |
| 6889 Register arg_1, | |
| 6890 bool check_exceptions) { | |
| 6891 pass_arg1(this, arg_1); | |
| 6892 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 6893 } | |
| 6894 | |
| 6895 void MacroAssembler::call_VM(Register oop_result, | |
| 6896 Register last_java_sp, | |
| 6897 address entry_point, | |
| 6898 Register arg_1, | |
| 6899 Register arg_2, | |
| 6900 bool check_exceptions) { | |
| 6901 | |
| 6902 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6903 pass_arg2(this, arg_2); | |
| 6904 pass_arg1(this, arg_1); | |
| 6905 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 6906 } | |
| 6907 | |
| 6908 void MacroAssembler::call_VM(Register oop_result, | |
| 6909 Register last_java_sp, | |
| 6910 address entry_point, | |
| 6911 Register arg_1, | |
| 6912 Register arg_2, | |
| 6913 Register arg_3, | |
| 6914 bool check_exceptions) { | |
| 6915 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 6916 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 6917 pass_arg3(this, arg_3); | |
| 6918 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6919 pass_arg2(this, arg_2); | |
| 6920 pass_arg1(this, arg_1); | |
| 6921 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 6922 } | |
| 6923 | |
|
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6924 void MacroAssembler::super_call_VM(Register oop_result, |
|
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|
6925 Register last_java_sp, |
|
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|
6926 address entry_point, |
|
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|
6927 int number_of_arguments, |
|
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|
6928 bool check_exceptions) { |
|
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|
6929 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); |
|
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|
6930 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
|
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|
6931 } |
|
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|
6932 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6933 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6934 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6935 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6936 Register arg_1, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6937 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6938 pass_arg1(this, arg_1); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6939 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6940 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6941 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6942 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6943 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6944 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6945 Register arg_1, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6946 Register arg_2, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6947 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6948 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6949 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6950 pass_arg2(this, arg_2); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6951 pass_arg1(this, arg_1); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6952 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6953 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6954 |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6955 void MacroAssembler::super_call_VM(Register oop_result, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6956 Register last_java_sp, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6957 address entry_point, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6958 Register arg_1, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6959 Register arg_2, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6960 Register arg_3, |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6961 bool check_exceptions) { |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6962 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6963 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6964 pass_arg3(this, arg_3); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6965 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6966 pass_arg2(this, arg_2); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6967 pass_arg1(this, arg_1); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6968 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6969 } |
|
07c2e7ffd1fc
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3442
diff
changeset
|
6970 |
| 304 | 6971 void MacroAssembler::call_VM_base(Register oop_result, |
| 6972 Register java_thread, | |
| 6973 Register last_java_sp, | |
| 6974 address entry_point, | |
| 6975 int number_of_arguments, | |
| 6976 bool check_exceptions) { | |
| 6977 // determine java_thread register | |
| 6978 if (!java_thread->is_valid()) { | |
| 6979 #ifdef _LP64 | |
| 6980 java_thread = r15_thread; | |
| 6981 #else | |
| 6982 java_thread = rdi; | |
| 6983 get_thread(java_thread); | |
| 6984 #endif // LP64 | |
| 6985 } | |
| 6986 // determine last_java_sp register | |
| 6987 if (!last_java_sp->is_valid()) { | |
| 6988 last_java_sp = rsp; | |
| 6989 } | |
| 6990 // debugging support | |
| 6991 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 6992 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
6993 #ifdef ASSERT |
|
4714
96ce4c27112f
7122939: TraceBytecodes broken with UseCompressedOops
coleenp
parents:
4118
diff
changeset
|
6994 // TraceBytecodes does not use r12 but saves it over the call, so don't verify |
|
96ce4c27112f
7122939: TraceBytecodes broken with UseCompressedOops
coleenp
parents:
4118
diff
changeset
|
6995 // r12 is the heapbase. |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
6996 LP64_ONLY(if ((UseCompressedOops || UseCompressedKlassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
6997 #endif // ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
6998 |
| 304 | 6999 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
| 7000 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 7001 | |
| 7002 // push java thread (becomes first argument of C function) | |
| 7003 | |
| 7004 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 7005 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 7006 | |
| 7007 // set last Java frame before call | |
| 7008 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 7009 | |
| 7010 // Only interpreter should have to set fp | |
| 7011 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 7012 | |
| 7013 // do the call, remove parameters | |
| 7014 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 7015 | |
| 7016 // restore the thread (cannot use the pushed argument since arguments | |
| 7017 // may be overwritten by C code generated by an optimizing compiler); | |
| 7018 // however can use the register value directly if it is callee saved. | |
| 7019 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 7020 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 7021 #ifdef ASSERT | |
| 7022 guarantee(java_thread != rax, "change this code"); | |
| 7023 push(rax); | |
| 7024 { Label L; | |
| 7025 get_thread(rax); | |
| 7026 cmpptr(java_thread, rax); | |
| 7027 jcc(Assembler::equal, L); | |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
7028 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); |
| 304 | 7029 bind(L); |
| 0 | 7030 } |
| 304 | 7031 pop(rax); |
| 7032 #endif | |
| 7033 } else { | |
| 7034 get_thread(java_thread); | |
| 7035 } | |
| 7036 // reset last Java frame | |
| 7037 // Only interpreter should have to clear fp | |
| 7038 reset_last_Java_frame(java_thread, true, false); | |
| 7039 | |
| 7040 #ifndef CC_INTERP | |
| 7041 // C++ interp handles this in the interpreter | |
| 7042 check_and_handle_popframe(java_thread); | |
| 7043 check_and_handle_earlyret(java_thread); | |
| 7044 #endif /* CC_INTERP */ | |
| 7045 | |
| 7046 if (check_exceptions) { | |
| 7047 // check for pending exceptions (java_thread is set upon return) | |
| 7048 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 7049 #ifndef _LP64 | |
| 7050 jump_cc(Assembler::notEqual, | |
| 7051 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 7052 #else | |
| 7053 // This used to conditionally jump to forward_exception however it is | |
| 7054 // possible if we relocate that the branch will not reach. So we must jump | |
| 7055 // around so we can always reach | |
| 7056 | |
| 7057 Label ok; | |
| 7058 jcc(Assembler::equal, ok); | |
| 7059 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 7060 bind(ok); | |
| 7061 #endif // LP64 | |
| 7062 } | |
| 7063 | |
| 7064 // get oop result if there is one and reset the value in the thread | |
| 7065 if (oop_result->is_valid()) { | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7066 get_vm_result(oop_result, java_thread); |
| 304 | 7067 } |
| 7068 } | |
| 7069 | |
| 7070 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 7071 | |
| 7072 // Calculate the value for last_Java_sp | |
| 7073 // somewhat subtle. call_VM does an intermediate call | |
| 7074 // which places a return address on the stack just under the | |
| 7075 // stack pointer as the user finsihed with it. This allows | |
| 7076 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 7077 // On 32bit we then have to push additional args on the stack to accomplish | |
| 7078 // the actual requested call. On 64bit call_VM only can use register args | |
| 7079 // so the only extra space is the return address that call_VM created. | |
| 7080 // This hopefully explains the calculations here. | |
| 7081 | |
| 7082 #ifdef _LP64 | |
| 7083 // We've pushed one address, correct last_Java_sp | |
| 7084 lea(rax, Address(rsp, wordSize)); | |
| 7085 #else | |
| 7086 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 7087 #endif // LP64 | |
| 7088 | |
| 7089 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 7090 | |
| 7091 } | |
| 7092 | |
| 7093 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 7094 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 7095 } | |
| 7096 | |
| 7097 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 7098 pass_arg0(this, arg_0); | |
| 7099 call_VM_leaf(entry_point, 1); | |
| 7100 } | |
| 7101 | |
| 7102 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 7103 | |
| 7104 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 7105 pass_arg1(this, arg_1); | |
| 7106 pass_arg0(this, arg_0); | |
| 7107 call_VM_leaf(entry_point, 2); | |
| 7108 } | |
| 7109 | |
| 7110 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 7111 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 7112 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 7113 pass_arg2(this, arg_2); | |
| 7114 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 7115 pass_arg1(this, arg_1); | |
| 7116 pass_arg0(this, arg_0); | |
| 7117 call_VM_leaf(entry_point, 3); | |
| 7118 } | |
| 7119 | |
|
3336
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7120 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7121 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7122 MacroAssembler::call_VM_leaf_base(entry_point, 1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7123 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7124 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7125 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7126 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7127 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7128 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7129 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7130 MacroAssembler::call_VM_leaf_base(entry_point, 2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7131 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7132 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7133 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7134 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7135 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7136 pass_arg2(this, arg_2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7137 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7138 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7139 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7140 MacroAssembler::call_VM_leaf_base(entry_point, 3); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7141 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7142 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7143 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7144 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7145 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7146 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7147 pass_arg3(this, arg_3); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7148 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7149 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7150 pass_arg2(this, arg_2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7151 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7152 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7153 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7154 MacroAssembler::call_VM_leaf_base(entry_point, 4); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7155 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
7156 |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7157 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7158 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7159 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7160 verify_oop(oop_result, "broken oop in call_VM_base"); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7161 } |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7162 |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
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6614
diff
changeset
|
7163 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7164 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
7165 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
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6614
diff
changeset
|
7166 } |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
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6614
diff
changeset
|
7167 |
| 304 | 7168 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { |
| 7169 } | |
| 7170 | |
| 7171 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 7172 } | |
| 7173 | |
| 7174 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 7175 if (reachable(src1)) { | |
| 7176 cmpl(as_Address(src1), imm); | |
| 7177 } else { | |
| 7178 lea(rscratch1, src1); | |
| 7179 cmpl(Address(rscratch1, 0), imm); | |
| 7180 } | |
| 7181 } | |
| 7182 | |
| 7183 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 7184 assert(!src2.is_lval(), "use cmpptr"); | |
| 7185 if (reachable(src2)) { | |
| 7186 cmpl(src1, as_Address(src2)); | |
| 7187 } else { | |
| 7188 lea(rscratch1, src2); | |
| 7189 cmpl(src1, Address(rscratch1, 0)); | |
| 7190 } | |
| 7191 } | |
| 7192 | |
| 7193 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 7194 Assembler::cmpl(src1, imm); | |
| 7195 } | |
| 7196 | |
| 7197 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 7198 Assembler::cmpl(src1, src2); | |
| 7199 } | |
| 7200 | |
| 7201 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 7202 ucomisd(opr1, opr2); | |
| 7203 | |
| 7204 Label L; | |
| 7205 if (unordered_is_less) { | |
| 7206 movl(dst, -1); | |
| 7207 jcc(Assembler::parity, L); | |
| 7208 jcc(Assembler::below , L); | |
| 7209 movl(dst, 0); | |
| 7210 jcc(Assembler::equal , L); | |
| 7211 increment(dst); | |
| 7212 } else { // unordered is greater | |
| 7213 movl(dst, 1); | |
| 7214 jcc(Assembler::parity, L); | |
| 7215 jcc(Assembler::above , L); | |
| 7216 movl(dst, 0); | |
| 7217 jcc(Assembler::equal , L); | |
| 7218 decrementl(dst); | |
| 7219 } | |
| 7220 bind(L); | |
| 7221 } | |
| 7222 | |
| 7223 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 7224 ucomiss(opr1, opr2); | |
| 7225 | |
| 7226 Label L; | |
| 7227 if (unordered_is_less) { | |
| 7228 movl(dst, -1); | |
| 7229 jcc(Assembler::parity, L); | |
| 7230 jcc(Assembler::below , L); | |
| 7231 movl(dst, 0); | |
| 7232 jcc(Assembler::equal , L); | |
| 7233 increment(dst); | |
| 7234 } else { // unordered is greater | |
| 7235 movl(dst, 1); | |
| 7236 jcc(Assembler::parity, L); | |
| 7237 jcc(Assembler::above , L); | |
| 7238 movl(dst, 0); | |
| 7239 jcc(Assembler::equal , L); | |
| 7240 decrementl(dst); | |
| 7241 } | |
| 7242 bind(L); | |
| 7243 } | |
| 7244 | |
| 7245 | |
| 7246 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 7247 if (reachable(src1)) { | |
| 7248 cmpb(as_Address(src1), imm); | |
| 7249 } else { | |
| 7250 lea(rscratch1, src1); | |
| 7251 cmpb(Address(rscratch1, 0), imm); | |
| 7252 } | |
| 7253 } | |
| 7254 | |
| 7255 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 7256 #ifdef _LP64 | |
| 7257 if (src2.is_lval()) { | |
| 7258 movptr(rscratch1, src2); | |
| 7259 Assembler::cmpq(src1, rscratch1); | |
| 7260 } else if (reachable(src2)) { | |
| 7261 cmpq(src1, as_Address(src2)); | |
| 7262 } else { | |
| 7263 lea(rscratch1, src2); | |
| 7264 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 7265 } | |
| 7266 #else | |
| 7267 if (src2.is_lval()) { | |
| 7268 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 7269 } else { | |
| 7270 cmpl(src1, as_Address(src2)); | |
| 7271 } | |
| 7272 #endif // _LP64 | |
| 7273 } | |
| 7274 | |
| 7275 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 7276 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 7277 #ifdef _LP64 | |
| 7278 // moves src2's literal address | |
| 7279 movptr(rscratch1, src2); | |
| 7280 Assembler::cmpq(src1, rscratch1); | |
| 7281 #else | |
| 7282 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 7283 #endif // _LP64 | |
| 7284 } | |
| 7285 | |
| 7286 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 7287 if (reachable(adr)) { | |
| 7288 if (os::is_MP()) | |
| 7289 lock(); | |
| 7290 cmpxchgptr(reg, as_Address(adr)); | |
| 7291 } else { | |
| 7292 lea(rscratch1, adr); | |
| 7293 if (os::is_MP()) | |
| 7294 lock(); | |
| 7295 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 7296 } | |
| 7297 } | |
| 7298 | |
| 7299 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 7300 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 7301 } | |
| 7302 | |
| 7303 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 7304 if (reachable(src)) { |
| 4759 | 7305 Assembler::comisd(dst, as_Address(src)); |
| 1060 | 7306 } else { |
| 7307 lea(rscratch1, src); | |
| 4759 | 7308 Assembler::comisd(dst, Address(rscratch1, 0)); |
| 1060 | 7309 } |
| 304 | 7310 } |
| 7311 | |
| 7312 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 7313 if (reachable(src)) { |
| 4759 | 7314 Assembler::comiss(dst, as_Address(src)); |
| 1060 | 7315 } else { |
| 7316 lea(rscratch1, src); | |
| 4759 | 7317 Assembler::comiss(dst, Address(rscratch1, 0)); |
| 1060 | 7318 } |
| 304 | 7319 } |
| 7320 | |
| 7321 | |
| 7322 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 7323 Condition negated_cond = negate_condition(cond); | |
| 7324 Label L; | |
| 7325 jcc(negated_cond, L); | |
| 7326 atomic_incl(counter_addr); | |
| 7327 bind(L); | |
| 7328 } | |
| 7329 | |
| 7330 int MacroAssembler::corrected_idivl(Register reg) { | |
| 7331 // Full implementation of Java idiv and irem; checks for | |
| 7332 // special case as described in JVM spec., p.243 & p.271. | |
| 7333 // The function returns the (pc) offset of the idivl | |
| 7334 // instruction - may be needed for implicit exceptions. | |
| 7335 // | |
| 7336 // normal case special case | |
| 7337 // | |
| 7338 // input : rax,: dividend min_int | |
| 7339 // reg: divisor (may not be rax,/rdx) -1 | |
| 7340 // | |
| 7341 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 7342 // rdx: remainder (= rax, irem reg) 0 | |
| 7343 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 7344 const int min_int = 0x80000000; | |
| 7345 Label normal_case, special_case; | |
| 7346 | |
| 7347 // check for special case | |
| 7348 cmpl(rax, min_int); | |
| 7349 jcc(Assembler::notEqual, normal_case); | |
| 7350 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 7351 cmpl(reg, -1); | |
| 7352 jcc(Assembler::equal, special_case); | |
| 7353 | |
| 7354 // handle normal case | |
| 7355 bind(normal_case); | |
| 7356 cdql(); | |
| 7357 int idivl_offset = offset(); | |
| 7358 idivl(reg); | |
| 7359 | |
| 7360 // normal and special case exit | |
| 7361 bind(special_case); | |
| 7362 | |
| 7363 return idivl_offset; | |
| 7364 } | |
| 7365 | |
| 7366 | |
| 7367 | |
| 7368 void MacroAssembler::decrementl(Register reg, int value) { | |
| 7369 if (value == min_jint) {subl(reg, value) ; return; } | |
| 7370 if (value < 0) { incrementl(reg, -value); return; } | |
| 7371 if (value == 0) { ; return; } | |
| 7372 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 7373 /* else */ { subl(reg, value) ; return; } | |
| 7374 } | |
| 7375 | |
| 7376 void MacroAssembler::decrementl(Address dst, int value) { | |
| 7377 if (value == min_jint) {subl(dst, value) ; return; } | |
| 7378 if (value < 0) { incrementl(dst, -value); return; } | |
| 7379 if (value == 0) { ; return; } | |
| 7380 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 7381 /* else */ { subl(dst, value) ; return; } | |
| 7382 } | |
| 7383 | |
| 7384 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 7385 assert (shift_value > 0, "illegal shift value"); | |
| 7386 Label _is_positive; | |
| 7387 testl (reg, reg); | |
| 7388 jcc (Assembler::positive, _is_positive); | |
| 7389 int offset = (1 << shift_value) - 1 ; | |
| 7390 | |
| 7391 if (offset == 1) { | |
| 7392 incrementl(reg); | |
| 7393 } else { | |
| 7394 addl(reg, offset); | |
| 7395 } | |
| 7396 | |
| 7397 bind (_is_positive); | |
| 7398 sarl(reg, shift_value); | |
| 7399 } | |
| 7400 | |
| 4759 | 7401 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { |
| 7402 if (reachable(src)) { | |
| 7403 Assembler::divsd(dst, as_Address(src)); | |
| 7404 } else { | |
| 7405 lea(rscratch1, src); | |
| 7406 Assembler::divsd(dst, Address(rscratch1, 0)); | |
| 7407 } | |
| 7408 } | |
| 7409 | |
| 7410 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { | |
| 7411 if (reachable(src)) { | |
| 7412 Assembler::divss(dst, as_Address(src)); | |
| 7413 } else { | |
| 7414 lea(rscratch1, src); | |
| 7415 Assembler::divss(dst, Address(rscratch1, 0)); | |
| 7416 } | |
| 7417 } | |
| 7418 | |
| 304 | 7419 // !defined(COMPILER2) is because of stupid core builds |
| 7420 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 7421 void MacroAssembler::empty_FPU_stack() { | |
| 7422 if (VM_Version::supports_mmx()) { | |
| 7423 emms(); | |
| 7424 } else { | |
| 7425 for (int i = 8; i-- > 0; ) ffree(i); | |
| 7426 } | |
| 7427 } | |
| 7428 #endif // !LP64 || C1 || !C2 | |
| 7429 | |
| 7430 | |
| 7431 // Defines obj, preserves var_size_in_bytes | |
| 7432 void MacroAssembler::eden_allocate(Register obj, | |
| 7433 Register var_size_in_bytes, | |
| 7434 int con_size_in_bytes, | |
| 7435 Register t1, | |
| 7436 Label& slow_case) { | |
| 7437 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 7438 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 7439 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 7440 jmp(slow_case); | |
| 304 | 7441 } else { |
| 362 | 7442 Register end = t1; |
| 7443 Label retry; | |
| 7444 bind(retry); | |
| 7445 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 7446 movptr(obj, heap_top); | |
| 7447 if (var_size_in_bytes == noreg) { | |
| 7448 lea(end, Address(obj, con_size_in_bytes)); | |
| 7449 } else { | |
| 7450 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 7451 } | |
| 7452 // if end < obj then we wrapped around => object too long => slow case | |
| 7453 cmpptr(end, obj); | |
| 7454 jcc(Assembler::below, slow_case); | |
| 7455 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 7456 jcc(Assembler::above, slow_case); | |
| 7457 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 7458 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 7459 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 7460 locked_cmpxchgptr(end, heap_top); | |
| 7461 jcc(Assembler::notEqual, retry); | |
| 7462 } | |
| 304 | 7463 } |
| 7464 | |
| 7465 void MacroAssembler::enter() { | |
| 7466 push(rbp); | |
| 7467 mov(rbp, rsp); | |
| 7468 } | |
| 0 | 7469 |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7470 // A 5 byte nop that is safe for patching (see patch_verified_entry) |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7471 void MacroAssembler::fat_nop() { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7472 if (UseAddressNop) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7473 addr_nop_5(); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7474 } else { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7475 emit_byte(0x26); // es: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7476 emit_byte(0x2e); // cs: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7477 emit_byte(0x64); // fs: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7478 emit_byte(0x65); // gs: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7479 emit_byte(0x90); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7480 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
7481 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
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4770
diff
changeset
|
7482 |
| 0 | 7483 void MacroAssembler::fcmp(Register tmp) { |
| 7484 fcmp(tmp, 1, true, true); | |
| 7485 } | |
| 7486 | |
| 7487 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 7488 assert(!pop_right || pop_left, "usage error"); | |
| 7489 if (VM_Version::supports_cmov()) { | |
| 7490 assert(tmp == noreg, "unneeded temp"); | |
| 7491 if (pop_left) { | |
| 7492 fucomip(index); | |
| 7493 } else { | |
| 7494 fucomi(index); | |
| 7495 } | |
| 7496 if (pop_right) { | |
| 7497 fpop(); | |
| 7498 } | |
| 7499 } else { | |
| 7500 assert(tmp != noreg, "need temp"); | |
| 7501 if (pop_left) { | |
| 7502 if (pop_right) { | |
| 7503 fcompp(); | |
| 7504 } else { | |
| 7505 fcomp(index); | |
| 7506 } | |
| 7507 } else { | |
| 7508 fcom(index); | |
| 7509 } | |
| 7510 // convert FPU condition into eflags condition via rax, | |
| 7511 save_rax(tmp); | |
| 7512 fwait(); fnstsw_ax(); | |
| 7513 sahf(); | |
| 7514 restore_rax(tmp); | |
| 7515 } | |
| 7516 // condition codes set as follows: | |
| 7517 // | |
| 7518 // CF (corresponds to C0) if x < y | |
| 7519 // PF (corresponds to C2) if unordered | |
| 7520 // ZF (corresponds to C3) if x = y | |
| 7521 } | |
| 7522 | |
| 7523 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 7524 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 7525 } | |
| 7526 | |
| 7527 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 7528 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 7529 Label L; | |
| 7530 if (unordered_is_less) { | |
| 7531 movl(dst, -1); | |
| 7532 jcc(Assembler::parity, L); | |
| 7533 jcc(Assembler::below , L); | |
| 7534 movl(dst, 0); | |
| 7535 jcc(Assembler::equal , L); | |
| 7536 increment(dst); | |
| 7537 } else { // unordered is greater | |
| 7538 movl(dst, 1); | |
| 7539 jcc(Assembler::parity, L); | |
| 7540 jcc(Assembler::above , L); | |
| 7541 movl(dst, 0); | |
| 7542 jcc(Assembler::equal , L); | |
| 304 | 7543 decrementl(dst); |
| 0 | 7544 } |
| 7545 bind(L); | |
| 7546 } | |
| 7547 | |
| 304 | 7548 void MacroAssembler::fld_d(AddressLiteral src) { |
| 7549 fld_d(as_Address(src)); | |
| 7550 } | |
| 7551 | |
| 7552 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 7553 fld_s(as_Address(src)); | |
| 7554 } | |
| 7555 | |
| 7556 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 7557 Assembler::fld_x(as_Address(src)); | |
| 7558 } | |
| 7559 | |
| 7560 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 7561 Assembler::fldcw(as_Address(src)); | |
| 7562 } | |
| 0 | 7563 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7564 void MacroAssembler::pow_exp_core_encoding() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7565 // kills rax, rcx, rdx |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7566 subptr(rsp,sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7567 // computes 2^X. Stack: X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7568 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7569 // keep it on the thread's stack to compute 2^int(X) later |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7570 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7571 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7572 fld_s(0); // Stack: X X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7573 frndint(); // Stack: int(X) X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7574 fsuba(1); // Stack: int(X) X-int(X) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7575 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7576 f2xm1(); // Stack: 2^(X-int(X))-1 ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7577 fld1(); // Stack: 1 2^(X-int(X))-1 ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7578 faddp(1); // Stack: 2^(X-int(X)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7579 // computes 2^(int(X)): add exponent bias (1023) to int(X), then |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7580 // shift int(X)+1023 to exponent position. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7581 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7582 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7583 // values so detect them and set result to NaN. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7584 movl(rax,Address(rsp,0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7585 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7586 addl(rax, 1023); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7587 movl(rdx,rax); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7588 shll(rax,20); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7589 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7590 addl(rdx,1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7591 // Check that 1 < int(X)+1023+1 < 2048 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7592 // in 3 steps: |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7593 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7594 // 2- (int(X)+1023+1)&-2048 != 0 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7595 // 3- (int(X)+1023+1)&-2048 != 1 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7596 // Do 2- first because addl just updated the flags. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7597 cmov32(Assembler::equal,rax,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7598 cmpl(rdx,1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7599 cmov32(Assembler::equal,rax,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7600 testl(rdx,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7601 cmov32(Assembler::notEqual,rax,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7602 movl(Address(rsp,4),rax); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7603 movl(Address(rsp,0),0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7604 fmul_d(Address(rsp,0)); // Stack: 2^X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7605 addptr(rsp,sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7606 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7607 |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7608 void MacroAssembler::increase_precision() { |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7609 subptr(rsp, BytesPerWord); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7610 fnstcw(Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7611 movl(rax, Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7612 orl(rax, 0x300); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7613 push(rax); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7614 fldcw(Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7615 pop(rax); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7616 } |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7617 |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7618 void MacroAssembler::restore_precision() { |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7619 fldcw(Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7620 addptr(rsp, BytesPerWord); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7621 } |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7622 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7623 void MacroAssembler::fast_pow() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7624 // computes X^Y = 2^(Y * log2(X)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7625 // if fast computation is not possible, result is NaN. Requires |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7626 // fallback from user of this macro. |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7627 // increase precision for intermediate steps of the computation |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7628 increase_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7629 fyl2x(); // Stack: (Y*log2(X)) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7630 pow_exp_core_encoding(); // Stack: exp(X) ... |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7631 restore_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7632 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7633 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7634 void MacroAssembler::fast_exp() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7635 // computes exp(X) = 2^(X * log2(e)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7636 // if fast computation is not possible, result is NaN. Requires |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7637 // fallback from user of this macro. |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7638 // increase precision for intermediate steps of the computation |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7639 increase_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7640 fldl2e(); // Stack: log2(e) X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7641 fmulp(1); // Stack: (X*log2(e)) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7642 pow_exp_core_encoding(); // Stack: exp(X) ... |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7643 restore_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7644 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7645 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7646 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7647 // kills rax, rcx, rdx |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7648 // pow and exp needs 2 extra registers on the fpu stack. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7649 Label slow_case, done; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7650 Register tmp = noreg; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7651 if (!VM_Version::supports_cmov()) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7652 // fcmp needs a temporary so preserve rdx, |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7653 tmp = rdx; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7654 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7655 Register tmp2 = rax; |
|
6087
e2961d14584b
7169934: pow(x,y) or x64 computes incorrect result when x<0 and y is an odd integer
roland
parents:
6084
diff
changeset
|
7656 Register tmp3 = rcx; |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7657 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7658 if (is_exp) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7659 // Stack: X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7660 fld_s(0); // duplicate argument for runtime call. Stack: X X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7661 fast_exp(); // Stack: exp(X) X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7662 fcmp(tmp, 0, false, false); // Stack: exp(X) X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7663 // exp(X) not equal to itself: exp(X) is NaN go to slow case. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7664 jcc(Assembler::parity, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7665 // get rid of duplicate argument. Stack: exp(X) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7666 if (num_fpu_regs_in_use > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7667 fxch(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7668 fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7669 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7670 ffree(1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7671 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7672 jmp(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7673 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7674 // Stack: X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7675 Label x_negative, y_odd; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7676 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7677 fldz(); // Stack: 0 X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7678 fcmp(tmp, 1, true, false); // Stack: X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7679 jcc(Assembler::above, x_negative); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7680 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7681 // X >= 0 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7682 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7683 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7684 fld_s(1); // Stack: X Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7685 fast_pow(); // Stack: X^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7686 fcmp(tmp, 0, false, false); // Stack: X^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7687 // X^Y not equal to itself: X^Y is NaN go to slow case. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7688 jcc(Assembler::parity, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7689 // get rid of duplicate arguments. Stack: X^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7690 if (num_fpu_regs_in_use > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7691 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7692 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7693 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7694 ffree(2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7695 ffree(1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7696 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7697 jmp(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7698 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7699 // X <= 0 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7700 bind(x_negative); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7701 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7702 fld_s(1); // Stack: Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7703 frndint(); // Stack: int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7704 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7705 jcc(Assembler::notEqual, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7706 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7707 subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7708 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7709 // For X^Y, when X < 0, Y has to be an integer and the final |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7710 // result depends on whether it's odd or even. We just checked |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7711 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7712 // integer to test its parity. If int(Y) is huge and doesn't fit |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7713 // in the 64 bit integer range, the integer indefinite value will |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7714 // end up in the gp registers. Huge numbers are all even, the |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7715 // integer indefinite number is even so it's fine. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7716 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7717 #ifdef ASSERT |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7718 // Let's check we don't end up with an integer indefinite number |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7719 // when not expected. First test for huge numbers: check whether |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7720 // int(Y)+1 == int(Y) which is true for very large numbers and |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7721 // those are all even. A 64 bit integer is guaranteed to not |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7722 // overflow for numbers where y+1 != y (when precision is set to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7723 // double precision). |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7724 Label y_not_huge; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7725 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7726 fld1(); // Stack: 1 int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7727 fadd(1); // Stack: 1+int(Y) int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7728 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7729 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7730 // trip to memory to force the precision down from double extended |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7731 // precision |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7732 fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7733 fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7734 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7735 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7736 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7737 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7738 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7739 // move int(Y) as 64 bit integer to thread's stack |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7740 fistp_d(Address(rsp,0)); // Stack: X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7741 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7742 #ifdef ASSERT |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7743 jcc(Assembler::notEqual, y_not_huge); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7744 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7745 // Y is huge so we know it's even. It may not fit in a 64 bit |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7746 // integer and we don't want the debug code below to see the |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7747 // integer indefinite value so overwrite int(Y) on the thread's |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7748 // stack with 0. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7749 movl(Address(rsp, 0), 0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7750 movl(Address(rsp, 4), 0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7751 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7752 bind(y_not_huge); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7753 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7754 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7755 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7756 fld_s(1); // Stack: X Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7757 fabs(); // Stack: abs(X) Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7758 fast_pow(); // Stack: abs(X)^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7759 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7760 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7761 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7762 pop(tmp2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7763 NOT_LP64(pop(tmp3)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7764 jcc(Assembler::parity, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7765 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7766 #ifdef ASSERT |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7767 // Check that int(Y) is not integer indefinite value (int |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7768 // overflow). Shouldn't happen because for values that would |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7769 // overflow, 1+int(Y)==Y which was tested earlier. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7770 #ifndef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7771 { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7772 Label integer; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7773 testl(tmp2, tmp2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7774 jcc(Assembler::notZero, integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7775 cmpl(tmp3, 0x80000000); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7776 jcc(Assembler::notZero, integer); |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
7777 STOP("integer indefinite value shouldn't be seen here"); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7778 bind(integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7779 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7780 #else |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7781 { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7782 Label integer; |
|
6087
e2961d14584b
7169934: pow(x,y) or x64 computes incorrect result when x<0 and y is an odd integer
roland
parents:
6084
diff
changeset
|
7783 mov(tmp3, tmp2); // preserve tmp2 for parity check below |
|
e2961d14584b
7169934: pow(x,y) or x64 computes incorrect result when x<0 and y is an odd integer
roland
parents:
6084
diff
changeset
|
7784 shlq(tmp3, 1); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7785 jcc(Assembler::carryClear, integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7786 jcc(Assembler::notZero, integer); |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
7787 STOP("integer indefinite value shouldn't be seen here"); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7788 bind(integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7789 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7790 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7791 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7792 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7793 // get rid of duplicate arguments. Stack: X^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7794 if (num_fpu_regs_in_use > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7795 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7796 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7797 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7798 ffree(2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7799 ffree(1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7800 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7801 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7802 testl(tmp2, 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7803 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7804 // X <= 0, Y even: X^Y = -abs(X)^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7805 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7806 fchs(); // Stack: -abs(X)^Y Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7807 jmp(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7808 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7809 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7810 // slow case: runtime call |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7811 bind(slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7812 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7813 fpop(); // pop incorrect result or int(Y) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7814 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7815 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow), |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7816 is_exp ? 1 : 2, num_fpu_regs_in_use); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7817 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7818 // Come here with result in F-TOS |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7819 bind(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7820 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7821 |
| 0 | 7822 void MacroAssembler::fpop() { |
| 7823 ffree(); | |
| 7824 fincstp(); | |
| 7825 } | |
| 7826 | |
| 304 | 7827 void MacroAssembler::fremr(Register tmp) { |
| 7828 save_rax(tmp); | |
| 7829 { Label L; | |
| 7830 bind(L); | |
| 7831 fprem(); | |
| 7832 fwait(); fnstsw_ax(); | |
| 7833 #ifdef _LP64 | |
| 7834 testl(rax, 0x400); | |
| 7835 jcc(Assembler::notEqual, L); | |
| 7836 #else | |
| 7837 sahf(); | |
| 7838 jcc(Assembler::parity, L); | |
| 7839 #endif // _LP64 | |
| 7840 } | |
| 7841 restore_rax(tmp); | |
| 7842 // Result is in ST0. | |
| 7843 // Note: fxch & fpop to get rid of ST1 | |
| 7844 // (otherwise FPU stack could overflow eventually) | |
| 7845 fxch(1); | |
| 7846 fpop(); | |
| 7847 } | |
| 7848 | |
| 7849 | |
| 7850 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 7851 if (reachable(dst)) { | |
| 7852 incrementl(as_Address(dst)); | |
| 0 | 7853 } else { |
| 304 | 7854 lea(rscratch1, dst); |
| 7855 incrementl(Address(rscratch1, 0)); | |
| 7856 } | |
| 7857 } | |
| 7858 | |
| 7859 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 7860 incrementl(as_Address(dst)); | |
| 7861 } | |
| 7862 | |
| 7863 void MacroAssembler::incrementl(Register reg, int value) { | |
| 7864 if (value == min_jint) {addl(reg, value) ; return; } | |
| 7865 if (value < 0) { decrementl(reg, -value); return; } | |
| 7866 if (value == 0) { ; return; } | |
| 7867 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 7868 /* else */ { addl(reg, value) ; return; } | |
| 7869 } | |
| 7870 | |
| 7871 void MacroAssembler::incrementl(Address dst, int value) { | |
| 7872 if (value == min_jint) {addl(dst, value) ; return; } | |
| 7873 if (value < 0) { decrementl(dst, -value); return; } | |
| 7874 if (value == 0) { ; return; } | |
| 7875 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 7876 /* else */ { addl(dst, value) ; return; } | |
| 7877 } | |
| 7878 | |
| 7879 void MacroAssembler::jump(AddressLiteral dst) { | |
| 7880 if (reachable(dst)) { | |
| 7881 jmp_literal(dst.target(), dst.rspec()); | |
| 7882 } else { | |
| 7883 lea(rscratch1, dst); | |
| 7884 jmp(rscratch1); | |
| 7885 } | |
| 7886 } | |
| 7887 | |
| 7888 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 7889 if (reachable(dst)) { | |
| 7890 InstructionMark im(this); | |
| 7891 relocate(dst.reloc()); | |
| 7892 const int short_size = 2; | |
| 7893 const int long_size = 6; | |
| 7894 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 7895 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 7896 // 0111 tttn #8-bit disp | |
| 7897 emit_byte(0x70 | cc); | |
| 7898 emit_byte((offs - short_size) & 0xFF); | |
| 7899 } else { | |
| 7900 // 0000 1111 1000 tttn #32-bit disp | |
| 7901 emit_byte(0x0F); | |
| 7902 emit_byte(0x80 | cc); | |
| 7903 emit_long(offs - long_size); | |
| 7904 } | |
| 0 | 7905 } else { |
| 304 | 7906 #ifdef ASSERT |
| 7907 warning("reversing conditional branch"); | |
| 7908 #endif /* ASSERT */ | |
| 7909 Label skip; | |
| 7910 jccb(reverse[cc], skip); | |
| 7911 lea(rscratch1, dst); | |
| 7912 Assembler::jmp(rscratch1); | |
| 7913 bind(skip); | |
| 7914 } | |
| 7915 } | |
| 7916 | |
| 7917 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 7918 if (reachable(src)) { | |
| 7919 Assembler::ldmxcsr(as_Address(src)); | |
| 7920 } else { | |
| 7921 lea(rscratch1, src); | |
| 7922 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 7923 } | |
| 7924 } | |
| 7925 | |
| 7926 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 7927 int off; | |
| 7928 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 7929 off = offset(); | |
| 7930 movsbl(dst, src); // movsxb | |
| 7931 } else { | |
| 7932 off = load_unsigned_byte(dst, src); | |
| 7933 shll(dst, 24); | |
| 7934 sarl(dst, 24); | |
| 7935 } | |
| 7936 return off; | |
| 7937 } | |
| 7938 | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7939 // Note: load_signed_short used to be called load_signed_word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7940 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7941 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7942 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7943 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 7944 int off; |
| 7945 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 7946 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 7947 // version but this is what 64bit has always done. This seems to imply | |
| 7948 // that users are only using 32bits worth. | |
| 7949 off = offset(); | |
| 7950 movswl(dst, src); // movsxw | |
| 7951 } else { | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7952 off = load_unsigned_short(dst, src); |
| 304 | 7953 shll(dst, 16); |
| 7954 sarl(dst, 16); | |
| 7955 } | |
| 7956 return off; | |
| 7957 } | |
| 7958 | |
| 7959 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 7960 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 7961 // and "3.9 Partial Register Penalties", p. 22). | |
| 7962 int off; | |
| 7963 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 7964 off = offset(); | |
| 7965 movzbl(dst, src); // movzxb | |
| 7966 } else { | |
| 7967 xorl(dst, dst); | |
| 7968 off = offset(); | |
| 7969 movb(dst, src); | |
| 7970 } | |
| 7971 return off; | |
| 7972 } | |
| 7973 | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7974 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7975 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 7976 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 7977 // and "3.9 Partial Register Penalties", p. 22). | |
| 7978 int off; | |
| 7979 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 7980 off = offset(); | |
| 7981 movzwl(dst, src); // movzxw | |
| 7982 } else { | |
| 7983 xorl(dst, dst); | |
| 7984 off = offset(); | |
| 7985 movw(dst, src); | |
| 7986 } | |
| 7987 return off; | |
| 7988 } | |
| 7989 | |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7990 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { |
| 1503 | 7991 switch (size_in_bytes) { |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7992 #ifndef _LP64 |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7993 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7994 assert(dst2 != noreg, "second dest register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7995 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7996 movl(dst2, src.plus_disp(BytesPerInt)); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7997 break; |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7998 #else |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7999 case 8: movq(dst, src); break; |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
8000 #endif |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8001 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8002 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8003 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8004 default: ShouldNotReachHere(); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8005 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8006 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8007 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8008 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8009 switch (size_in_bytes) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8010 #ifndef _LP64 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8011 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8012 assert(src2 != noreg, "second source register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8013 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8014 movl(dst.plus_disp(BytesPerInt), src2); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8015 break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8016 #else |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8017 case 8: movq(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8018 #endif |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8019 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8020 case 2: movw(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8021 case 1: movb(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
8022 default: ShouldNotReachHere(); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
8023 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
8024 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
8025 |
| 304 | 8026 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 8027 if (reachable(dst)) { | |
| 8028 movl(as_Address(dst), src); | |
| 8029 } else { | |
| 8030 lea(rscratch1, dst); | |
| 8031 movl(Address(rscratch1, 0), src); | |
| 8032 } | |
| 8033 } | |
| 8034 | |
| 8035 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 8036 if (reachable(src)) { | |
| 8037 movl(dst, as_Address(src)); | |
| 8038 } else { | |
| 8039 lea(rscratch1, src); | |
| 8040 movl(dst, Address(rscratch1, 0)); | |
| 8041 } | |
| 0 | 8042 } |
| 8043 | |
| 8044 // C++ bool manipulation | |
| 8045 | |
| 8046 void MacroAssembler::movbool(Register dst, Address src) { | |
| 8047 if(sizeof(bool) == 1) | |
| 8048 movb(dst, src); | |
| 8049 else if(sizeof(bool) == 2) | |
| 8050 movw(dst, src); | |
| 8051 else if(sizeof(bool) == 4) | |
| 8052 movl(dst, src); | |
| 8053 else | |
| 8054 // unsupported | |
| 8055 ShouldNotReachHere(); | |
| 8056 } | |
| 8057 | |
| 8058 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 8059 if(sizeof(bool) == 1) | |
| 8060 movb(dst, (int) boolconst); | |
| 8061 else if(sizeof(bool) == 2) | |
| 8062 movw(dst, (int) boolconst); | |
| 8063 else if(sizeof(bool) == 4) | |
| 8064 movl(dst, (int) boolconst); | |
| 8065 else | |
| 8066 // unsupported | |
| 8067 ShouldNotReachHere(); | |
| 8068 } | |
| 8069 | |
| 8070 void MacroAssembler::movbool(Address dst, Register src) { | |
| 8071 if(sizeof(bool) == 1) | |
| 8072 movb(dst, src); | |
| 8073 else if(sizeof(bool) == 2) | |
| 8074 movw(dst, src); | |
| 8075 else if(sizeof(bool) == 4) | |
| 8076 movl(dst, src); | |
| 8077 else | |
| 8078 // unsupported | |
| 8079 ShouldNotReachHere(); | |
| 8080 } | |
| 8081 | |
| 304 | 8082 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 8083 movb(as_Address(dst), src); | |
| 8084 } | |
| 8085 | |
| 6225 | 8086 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { |
| 8087 if (reachable(src)) { | |
| 8088 movdl(dst, as_Address(src)); | |
| 8089 } else { | |
| 8090 lea(rscratch1, src); | |
| 8091 movdl(dst, Address(rscratch1, 0)); | |
| 8092 } | |
| 8093 } | |
| 8094 | |
| 8095 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { | |
| 8096 if (reachable(src)) { | |
| 8097 movq(dst, as_Address(src)); | |
| 8098 } else { | |
| 8099 lea(rscratch1, src); | |
| 8100 movq(dst, Address(rscratch1, 0)); | |
| 8101 } | |
| 8102 } | |
| 8103 | |
| 304 | 8104 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { |
| 8105 if (reachable(src)) { | |
| 8106 if (UseXmmLoadAndClearUpper) { | |
| 8107 movsd (dst, as_Address(src)); | |
| 8108 } else { | |
| 8109 movlpd(dst, as_Address(src)); | |
| 8110 } | |
| 8111 } else { | |
| 8112 lea(rscratch1, src); | |
| 8113 if (UseXmmLoadAndClearUpper) { | |
| 8114 movsd (dst, Address(rscratch1, 0)); | |
| 8115 } else { | |
| 8116 movlpd(dst, Address(rscratch1, 0)); | |
| 8117 } | |
| 8118 } | |
| 8119 } | |
| 8120 | |
| 8121 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 8122 if (reachable(src)) { | |
| 8123 movss(dst, as_Address(src)); | |
| 8124 } else { | |
| 8125 lea(rscratch1, src); | |
| 8126 movss(dst, Address(rscratch1, 0)); | |
| 8127 } | |
| 8128 } | |
| 8129 | |
| 8130 void MacroAssembler::movptr(Register dst, Register src) { | |
| 8131 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 8132 } | |
| 8133 | |
| 8134 void MacroAssembler::movptr(Register dst, Address src) { | |
| 8135 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 8136 } | |
| 8137 | |
| 8138 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 8139 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 8140 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 8141 } | |
| 8142 | |
| 8143 void MacroAssembler::movptr(Address dst, Register src) { | |
| 8144 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 8145 } | |
| 8146 | |
| 6894 | 8147 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { |
| 8148 if (reachable(src)) { | |
| 8149 Assembler::movdqu(dst, as_Address(src)); | |
| 8150 } else { | |
| 8151 lea(rscratch1, src); | |
| 8152 Assembler::movdqu(dst, Address(rscratch1, 0)); | |
| 8153 } | |
| 8154 } | |
| 8155 | |
| 4759 | 8156 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { |
| 8157 if (reachable(src)) { | |
| 8158 Assembler::movsd(dst, as_Address(src)); | |
| 8159 } else { | |
| 8160 lea(rscratch1, src); | |
| 8161 Assembler::movsd(dst, Address(rscratch1, 0)); | |
| 8162 } | |
| 8163 } | |
| 8164 | |
| 304 | 8165 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
| 8166 if (reachable(src)) { | |
| 4759 | 8167 Assembler::movss(dst, as_Address(src)); |
| 304 | 8168 } else { |
| 8169 lea(rscratch1, src); | |
| 4759 | 8170 Assembler::movss(dst, Address(rscratch1, 0)); |
| 8171 } | |
| 8172 } | |
| 8173 | |
| 8174 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { | |
| 8175 if (reachable(src)) { | |
| 8176 Assembler::mulsd(dst, as_Address(src)); | |
| 8177 } else { | |
| 8178 lea(rscratch1, src); | |
| 8179 Assembler::mulsd(dst, Address(rscratch1, 0)); | |
| 8180 } | |
| 8181 } | |
| 8182 | |
| 8183 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { | |
| 8184 if (reachable(src)) { | |
| 8185 Assembler::mulss(dst, as_Address(src)); | |
| 8186 } else { | |
| 8187 lea(rscratch1, src); | |
| 8188 Assembler::mulss(dst, Address(rscratch1, 0)); | |
| 304 | 8189 } |
| 8190 } | |
| 8191 | |
| 8192 void MacroAssembler::null_check(Register reg, int offset) { | |
| 8193 if (needs_explicit_null_check(offset)) { | |
| 8194 // provoke OS NULL exception if reg = NULL by | |
| 8195 // accessing M[reg] w/o changing any (non-CC) registers | |
| 8196 // NOTE: cmpl is plenty here to provoke a segv | |
| 8197 cmpptr(rax, Address(reg, 0)); | |
| 8198 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 8199 // may be shorter code (however, this version of | |
| 8200 // testl needs to be implemented first) | |
| 8201 } else { | |
| 8202 // nothing to do, (later) access of M[reg + offset] | |
| 8203 // will provoke OS NULL exception if reg = NULL | |
| 8204 } | |
| 8205 } | |
| 8206 | |
| 8207 void MacroAssembler::os_breakpoint() { | |
| 8208 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 8209 // (e.g., MSVC can't call ps() otherwise) | |
| 8210 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 8211 } | |
| 8212 | |
| 8213 void MacroAssembler::pop_CPU_state() { | |
| 8214 pop_FPU_state(); | |
| 8215 pop_IU_state(); | |
| 8216 } | |
| 8217 | |
| 8218 void MacroAssembler::pop_FPU_state() { | |
| 8219 NOT_LP64(frstor(Address(rsp, 0));) | |
| 8220 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 8221 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 8222 } | |
| 8223 | |
| 8224 void MacroAssembler::pop_IU_state() { | |
| 8225 popa(); | |
| 8226 LP64_ONLY(addq(rsp, 8)); | |
| 8227 popf(); | |
| 8228 } | |
| 8229 | |
| 8230 // Save Integer and Float state | |
| 8231 // Warning: Stack must be 16 byte aligned (64bit) | |
| 8232 void MacroAssembler::push_CPU_state() { | |
| 8233 push_IU_state(); | |
| 8234 push_FPU_state(); | |
| 8235 } | |
| 8236 | |
| 8237 void MacroAssembler::push_FPU_state() { | |
| 8238 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 8239 #ifndef _LP64 | |
| 8240 fnsave(Address(rsp, 0)); | |
| 8241 fwait(); | |
| 8242 #else | |
| 8243 fxsave(Address(rsp, 0)); | |
| 8244 #endif // LP64 | |
| 8245 } | |
| 8246 | |
| 8247 void MacroAssembler::push_IU_state() { | |
| 8248 // Push flags first because pusha kills them | |
| 8249 pushf(); | |
| 8250 // Make sure rsp stays 16-byte aligned | |
| 8251 LP64_ONLY(subq(rsp, 8)); | |
| 8252 pusha(); | |
| 8253 } | |
| 8254 | |
| 8255 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 8256 // determine java_thread register | |
| 8257 if (!java_thread->is_valid()) { | |
| 8258 java_thread = rdi; | |
| 8259 get_thread(java_thread); | |
| 8260 } | |
| 8261 // we must set sp to zero to clear frame | |
|
512
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|
8262 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 8263 if (clear_fp) { |
|
512
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|
8264 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 8265 } |
| 8266 | |
| 8267 if (clear_pc) | |
|
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|
8268 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 8269 |
| 8270 } | |
| 8271 | |
| 8272 void MacroAssembler::restore_rax(Register tmp) { | |
| 8273 if (tmp == noreg) pop(rax); | |
| 8274 else if (tmp != rax) mov(rax, tmp); | |
| 8275 } | |
| 8276 | |
| 8277 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 8278 addptr(reg, modulus - 1); | |
| 8279 andptr(reg, -modulus); | |
| 8280 } | |
| 8281 | |
| 8282 void MacroAssembler::save_rax(Register tmp) { | |
| 8283 if (tmp == noreg) push(rax); | |
| 8284 else if (tmp != rax) mov(tmp, rax); | |
| 8285 } | |
| 8286 | |
| 8287 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 8288 // We use the current thread pointer to calculate a thread specific | |
| 8289 // offset to write to within the page. This minimizes bus traffic | |
| 8290 // due to cache line collision. | |
| 8291 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 8292 movl(tmp, thread); | |
| 8293 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 8294 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 8295 | |
| 8296 Address index(noreg, tmp, Address::times_1); | |
| 8297 ExternalAddress page(os::get_memory_serialize_page()); | |
| 8298 | |
|
606
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|
8299 // Size of store must match masking code above |
|
19962e74284f
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|
8300 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 8301 } |
| 8302 | |
| 8303 // Calls to C land | |
| 8304 // | |
| 8305 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 8306 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 8307 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 8308 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 8309 Register last_java_sp, | |
| 8310 Register last_java_fp, | |
| 8311 address last_java_pc) { | |
| 8312 // determine java_thread register | |
| 8313 if (!java_thread->is_valid()) { | |
| 8314 java_thread = rdi; | |
| 8315 get_thread(java_thread); | |
| 8316 } | |
| 8317 // determine last_java_sp register | |
| 8318 if (!last_java_sp->is_valid()) { | |
| 8319 last_java_sp = rsp; | |
| 8320 } | |
| 8321 | |
| 8322 // last_java_fp is optional | |
| 8323 | |
| 8324 if (last_java_fp->is_valid()) { | |
| 8325 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 8326 } | |
| 8327 | |
| 8328 // last_java_pc is optional | |
| 8329 | |
| 8330 if (last_java_pc != NULL) { | |
| 8331 lea(Address(java_thread, | |
| 8332 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 8333 InternalAddress(last_java_pc)); | |
| 8334 | |
| 8335 } | |
| 8336 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 8337 } | |
| 8338 | |
| 8339 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 8340 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 8341 } | |
| 8342 | |
| 8343 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 8344 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 8345 } | |
| 8346 | |
| 8347 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 8348 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 8349 movsbl(reg, reg); // movsxb | |
| 8350 } else { | |
| 8351 shll(reg, 24); | |
| 8352 sarl(reg, 24); | |
| 8353 } | |
| 8354 } | |
| 8355 | |
| 8356 void MacroAssembler::sign_extend_short(Register reg) { | |
| 8357 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 8358 movswl(reg, reg); // movsxw | |
| 8359 } else { | |
| 8360 shll(reg, 16); | |
| 8361 sarl(reg, 16); | |
| 8362 } | |
| 8363 } | |
| 8364 | |
|
2404
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|
8365 void MacroAssembler::testl(Register dst, AddressLiteral src) { |
|
b40d4fa697bf
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diff
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|
8366 assert(reachable(src), "Address should be reachable"); |
|
b40d4fa697bf
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|
8367 testl(dst, as_Address(src)); |
|
b40d4fa697bf
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|
8368 } |
|
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|
8369 |
| 4759 | 8370 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { |
| 8371 if (reachable(src)) { | |
| 8372 Assembler::sqrtsd(dst, as_Address(src)); | |
| 8373 } else { | |
| 8374 lea(rscratch1, src); | |
| 8375 Assembler::sqrtsd(dst, Address(rscratch1, 0)); | |
| 8376 } | |
| 8377 } | |
| 8378 | |
| 8379 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { | |
| 8380 if (reachable(src)) { | |
| 8381 Assembler::sqrtss(dst, as_Address(src)); | |
| 8382 } else { | |
| 8383 lea(rscratch1, src); | |
| 8384 Assembler::sqrtss(dst, Address(rscratch1, 0)); | |
| 8385 } | |
| 8386 } | |
| 8387 | |
| 8388 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { | |
| 8389 if (reachable(src)) { | |
| 8390 Assembler::subsd(dst, as_Address(src)); | |
| 8391 } else { | |
| 8392 lea(rscratch1, src); | |
| 8393 Assembler::subsd(dst, Address(rscratch1, 0)); | |
| 8394 } | |
| 8395 } | |
| 8396 | |
| 8397 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { | |
| 8398 if (reachable(src)) { | |
| 8399 Assembler::subss(dst, as_Address(src)); | |
| 8400 } else { | |
| 8401 lea(rscratch1, src); | |
| 8402 Assembler::subss(dst, Address(rscratch1, 0)); | |
| 8403 } | |
| 8404 } | |
| 8405 | |
|
4761
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
8406 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
8407 if (reachable(src)) { |
|
65149e74c706
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diff
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|
8408 Assembler::ucomisd(dst, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
8409 } else { |
|
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|
8410 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
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|
8411 Assembler::ucomisd(dst, Address(rscratch1, 0)); |
|
65149e74c706
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|
8412 } |
|
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|
8413 } |
|
65149e74c706
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|
8414 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
8415 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
8416 if (reachable(src)) { |
|
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|
8417 Assembler::ucomiss(dst, as_Address(src)); |
|
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|
8418 } else { |
|
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|
8419 lea(rscratch1, src); |
|
65149e74c706
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|
8420 Assembler::ucomiss(dst, Address(rscratch1, 0)); |
|
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|
8421 } |
|
65149e74c706
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|
8422 } |
|
65149e74c706
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|
8423 |
|
65149e74c706
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|
8424 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
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|
8425 // Used in sign-bit flipping with aligned address. |
|
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|
8426 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
8427 if (reachable(src)) { |
|
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|
8428 Assembler::xorpd(dst, as_Address(src)); |
|
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|
8429 } else { |
|
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|
8430 lea(rscratch1, src); |
|
65149e74c706
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|
8431 Assembler::xorpd(dst, Address(rscratch1, 0)); |
|
65149e74c706
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|
8432 } |
|
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|
8433 } |
|
65149e74c706
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|
8434 |
|
65149e74c706
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|
8435 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
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|
8436 // Used in sign-bit flipping with aligned address. |
|
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|
8437 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
|
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|
8438 if (reachable(src)) { |
|
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|
8439 Assembler::xorps(dst, as_Address(src)); |
|
65149e74c706
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changeset
|
8440 } else { |
|
65149e74c706
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changeset
|
8441 lea(rscratch1, src); |
|
65149e74c706
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changeset
|
8442 Assembler::xorps(dst, Address(rscratch1, 0)); |
|
65149e74c706
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changeset
|
8443 } |
|
65149e74c706
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diff
changeset
|
8444 } |
|
65149e74c706
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changeset
|
8445 |
| 6894 | 8446 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { |
| 8447 // Used in sign-bit flipping with aligned address. | |
| 8448 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 8449 if (reachable(src)) { | |
| 8450 Assembler::pshufb(dst, as_Address(src)); | |
| 8451 } else { | |
| 8452 lea(rscratch1, src); | |
| 8453 Assembler::pshufb(dst, Address(rscratch1, 0)); | |
| 8454 } | |
| 8455 } | |
| 8456 | |
|
4761
65149e74c706
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changeset
|
8457 // AVX 3-operands instructions |
|
65149e74c706
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changeset
|
8458 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
8459 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
8460 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
8461 vaddsd(dst, nds, as_Address(src)); |
|
65149e74c706
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changeset
|
8462 } else { |
|
65149e74c706
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changeset
|
8463 lea(rscratch1, src); |
|
65149e74c706
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changeset
|
8464 vaddsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
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changeset
|
8465 } |
|
65149e74c706
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diff
changeset
|
8466 } |
|
65149e74c706
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diff
changeset
|
8467 |
|
65149e74c706
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changeset
|
8468 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
8469 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
8470 vaddss(dst, nds, as_Address(src)); |
|
65149e74c706
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|
8471 } else { |
|
65149e74c706
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changeset
|
8472 lea(rscratch1, src); |
|
65149e74c706
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changeset
|
8473 vaddss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
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|
8474 } |
|
65149e74c706
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diff
changeset
|
8475 } |
|
65149e74c706
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changeset
|
8476 |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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|
8477 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
|
4761
65149e74c706
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changeset
|
8478 if (reachable(src)) { |
|
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
8479 vandpd(dst, nds, as_Address(src), vector256); |
|
4761
65149e74c706
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|
8480 } else { |
|
65149e74c706
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changeset
|
8481 lea(rscratch1, src); |
|
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
8482 vandpd(dst, nds, Address(rscratch1, 0), vector256); |
|
006050192a5a
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changeset
|
8483 } |
|
006050192a5a
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diff
changeset
|
8484 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
8485 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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|
8486 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
|
4761
65149e74c706
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changeset
|
8487 if (reachable(src)) { |
|
6614
006050192a5a
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diff
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|
8488 vandps(dst, nds, as_Address(src), vector256); |
|
4761
65149e74c706
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|
8489 } else { |
|
65149e74c706
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changeset
|
8490 lea(rscratch1, src); |
|
6614
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changeset
|
8491 vandps(dst, nds, Address(rscratch1, 0), vector256); |
|
4761
65149e74c706
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diff
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|
8492 } |
|
65149e74c706
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4759
diff
changeset
|
8493 } |
|
65149e74c706
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diff
changeset
|
8494 |
|
65149e74c706
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diff
changeset
|
8495 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
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changeset
|
8496 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
8497 vdivsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
8498 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8499 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
8500 vdivsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
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kvn
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diff
changeset
|
8501 } |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
8502 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8503 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
8504 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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changeset
|
8505 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
8506 vdivss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
8507 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8508 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8509 vdivss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
8510 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8511 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8512 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8513 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8514 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8515 vmulsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8516 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8517 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8518 vmulsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8519 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8520 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8521 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8522 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8523 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8524 vmulss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8525 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8526 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8527 vmulss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8528 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8529 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8530 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8531 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8532 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
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changeset
|
8533 vsubsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8534 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8535 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8536 vsubsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8537 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8538 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8539 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8540 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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changeset
|
8541 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
8542 vsubss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8543 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8544 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
8545 vsubss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8546 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8547 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
8548 |
|
6614
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6340864: Implement vectorization optimizations in hotspot-server
kvn
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changeset
|
8549 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
8550 if (reachable(src)) { |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
8551 vxorpd(dst, nds, as_Address(src), vector256); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8552 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8553 lea(rscratch1, src); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
8554 vxorpd(dst, nds, Address(rscratch1, 0), vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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changeset
|
8555 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
8556 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
8557 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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changeset
|
8558 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8559 if (reachable(src)) { |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
8560 vxorps(dst, nds, as_Address(src), vector256); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8561 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8562 lea(rscratch1, src); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
8563 vxorps(dst, nds, Address(rscratch1, 0), vector256); |
|
4761
65149e74c706
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kvn
parents:
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diff
changeset
|
8564 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
8565 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
8566 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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changeset
|
8567 |
| 362 | 8568 ////////////////////////////////////////////////////////////////////////////////// |
| 8569 #ifndef SERIALGC | |
| 8570 | |
| 8571 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8572 Register pre_val, |
| 362 | 8573 Register thread, |
| 8574 Register tmp, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8575 bool tosca_live, |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8576 bool expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8577 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8578 // If expand_call is true then we expand the call_VM_leaf macro |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8579 // directly to skip generating the check by |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8580 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8581 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8582 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8583 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8584 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8585 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8586 Label done; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8587 Label runtime; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8588 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8589 assert(pre_val != noreg, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8590 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8591 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8592 assert_different_registers(obj, pre_val, tmp); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8593 assert(pre_val != rax, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8594 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8595 |
| 362 | 8596 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
| 8597 PtrQueue::byte_offset_of_active())); | |
| 8598 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 8599 PtrQueue::byte_offset_of_index())); | |
| 8600 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 8601 PtrQueue::byte_offset_of_buf())); | |
| 8602 | |
| 8603 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8604 // Is marking active? |
| 362 | 8605 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
| 8606 cmpl(in_progress, 0); | |
| 8607 } else { | |
| 8608 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 8609 cmpb(in_progress, 0); | |
| 8610 } | |
| 8611 jcc(Assembler::equal, done); | |
| 8612 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8613 // Do we need to load the previous value? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8614 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8615 load_heap_oop(pre_val, Address(obj, 0)); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8616 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8617 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8618 // Is the previous value null? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8619 cmpptr(pre_val, (int32_t) NULL_WORD); |
| 362 | 8620 jcc(Assembler::equal, done); |
| 8621 | |
| 8622 // Can we store original value in the thread's buffer? | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8623 // Is index == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8624 // (The index field is typed as size_t.) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8625 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8626 movptr(tmp, index); // tmp := *index_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8627 cmpptr(tmp, 0); // tmp == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8628 jcc(Assembler::equal, runtime); // If yes, goto runtime |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8629 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8630 subptr(tmp, wordSize); // tmp := tmp - wordSize |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8631 movptr(index, tmp); // *index_adr := tmp |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8632 addptr(tmp, buffer); // tmp := tmp + *buffer_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8633 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8634 // Record the previous value |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8635 movptr(Address(tmp, 0), pre_val); |
| 362 | 8636 jmp(done); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8637 |
| 362 | 8638 bind(runtime); |
| 8639 // save the live input values | |
| 8640 if(tosca_live) push(rax); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8641 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8642 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8643 push(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8644 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8645 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8646 push(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8647 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8648 // Calling the runtime using the regular call_VM_leaf mechanism generates |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8649 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8650 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8651 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8652 // If we care generating the pre-barrier without a frame (e.g. in the |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8653 // intrinsified Reference.get() routine) then ebp might be pointing to |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8654 // the caller frame and so this check will most likely fail at runtime. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8655 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8656 // Expanding the call directly bypasses the generation of the check. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8657 // So when we do not have have a full interpreter frame on the stack |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8658 // expand_call should be passed true. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8659 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8660 NOT_LP64( push(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8661 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8662 if (expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8663 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8664 pass_arg1(this, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8665 pass_arg0(this, pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8666 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8667 } else { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8668 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8669 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8670 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8671 NOT_LP64( pop(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8672 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8673 // save the live input values |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8674 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8675 pop(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8676 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8677 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8678 pop(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8679 |
| 362 | 8680 if(tosca_live) pop(rax); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8681 |
| 362 | 8682 bind(done); |
| 8683 } | |
| 8684 | |
| 8685 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 8686 Register new_val, | |
| 8687 Register thread, | |
| 8688 Register tmp, | |
| 8689 Register tmp2) { | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8690 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8691 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8692 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8693 |
| 362 | 8694 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + |
| 8695 PtrQueue::byte_offset_of_index())); | |
| 8696 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 8697 PtrQueue::byte_offset_of_buf())); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8698 |
| 362 | 8699 BarrierSet* bs = Universe::heap()->barrier_set(); |
| 8700 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 8701 Label done; | |
| 8702 Label runtime; | |
| 8703 | |
| 8704 // Does store cross heap regions? | |
| 8705 | |
| 8706 movptr(tmp, store_addr); | |
| 8707 xorptr(tmp, new_val); | |
| 8708 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 8709 jcc(Assembler::equal, done); | |
| 8710 | |
| 8711 // crosses regions, storing NULL? | |
| 8712 | |
| 8713 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 8714 jcc(Assembler::equal, done); | |
| 8715 | |
| 8716 // storing region crossing non-NULL, is card already dirty? | |
| 8717 | |
| 8718 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 8719 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 8720 #ifdef _LP64 | |
| 8721 const Register card_addr = tmp; | |
| 8722 | |
| 8723 movq(card_addr, store_addr); | |
| 8724 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 8725 | |
| 8726 lea(tmp2, cardtable); | |
| 8727 | |
| 8728 // get the address of the card | |
| 8729 addq(card_addr, tmp2); | |
| 8730 #else | |
| 8731 const Register card_index = tmp; | |
| 8732 | |
| 8733 movl(card_index, store_addr); | |
| 8734 shrl(card_index, CardTableModRefBS::card_shift); | |
| 8735 | |
| 8736 Address index(noreg, card_index, Address::times_1); | |
| 8737 const Register card_addr = tmp; | |
| 8738 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 8739 #endif | |
| 8740 cmpb(Address(card_addr, 0), 0); | |
| 8741 jcc(Assembler::equal, done); | |
| 8742 | |
| 8743 // storing a region crossing, non-NULL oop, card is clean. | |
| 8744 // dirty card and log. | |
| 8745 | |
| 8746 movb(Address(card_addr, 0), 0); | |
| 8747 | |
| 8748 cmpl(queue_index, 0); | |
| 8749 jcc(Assembler::equal, runtime); | |
| 8750 subl(queue_index, wordSize); | |
| 8751 movptr(tmp2, buffer); | |
| 8752 #ifdef _LP64 | |
| 8753 movslq(rscratch1, queue_index); | |
| 8754 addq(tmp2, rscratch1); | |
| 8755 movq(Address(tmp2, 0), card_addr); | |
| 8756 #else | |
| 8757 addl(tmp2, queue_index); | |
| 8758 movl(Address(tmp2, 0), card_index); | |
| 8759 #endif | |
| 8760 jmp(done); | |
| 8761 | |
| 8762 bind(runtime); | |
| 8763 // save the live input values | |
| 8764 push(store_addr); | |
| 8765 push(new_val); | |
| 8766 #ifdef _LP64 | |
| 8767 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 8768 #else | |
| 8769 push(thread); | |
| 8770 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 8771 pop(thread); | |
| 8772 #endif | |
| 8773 pop(new_val); | |
| 8774 pop(store_addr); | |
| 8775 | |
| 8776 bind(done); | |
| 8777 } | |
| 8778 | |
| 8779 #endif // SERIALGC | |
| 8780 ////////////////////////////////////////////////////////////////////////////////// | |
| 8781 | |
| 8782 | |
| 304 | 8783 void MacroAssembler::store_check(Register obj) { |
| 8784 // Does a store check for the oop in register obj. The content of | |
| 8785 // register obj is destroyed afterwards. | |
| 8786 store_check_part_1(obj); | |
| 8787 store_check_part_2(obj); | |
| 8788 } | |
| 8789 | |
| 8790 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 8791 store_check(obj); | |
| 8792 } | |
| 8793 | |
| 8794 | |
| 8795 // split the store check operation so that other instructions can be scheduled inbetween | |
| 8796 void MacroAssembler::store_check_part_1(Register obj) { | |
| 8797 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 8798 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 8799 shrptr(obj, CardTableModRefBS::card_shift); | |
| 8800 } | |
| 8801 | |
| 8802 void MacroAssembler::store_check_part_2(Register obj) { | |
| 8803 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 8804 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 8805 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 8806 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 8807 | |
| 8808 // The calculation for byte_map_base is as follows: | |
| 8809 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 8810 // So this essentially converts an address to a displacement and | |
| 8811 // it will never need to be relocated. On 64bit however the value may be too | |
| 8812 // large for a 32bit displacement | |
| 8813 | |
| 8814 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 8815 if (is_simm32(disp)) { | |
| 8816 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 8817 movb(cardtable, 0); | |
| 8818 } else { | |
| 8819 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 8820 // displacement and done in a single instruction given favorable mapping and | |
| 8821 // a smarter version of as_Address. Worst case it is two instructions which | |
| 8822 // is no worse off then loading disp into a register and doing as a simple | |
| 8823 // Address() as above. | |
| 8824 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 8825 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 8826 // in some cases we'll get a single instruction version. | |
| 8827 | |
| 8828 ExternalAddress cardtable((address)disp); | |
| 8829 Address index(noreg, obj, Address::times_1); | |
| 8830 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 8831 } | |
| 8832 } | |
| 8833 | |
| 8834 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 8835 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 8836 } | |
| 8837 | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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diff
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|
8838 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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4770
diff
changeset
|
8839 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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parents:
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|
8840 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
8841 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
8842 |
| 304 | 8843 void MacroAssembler::subptr(Register dst, Register src) { |
| 8844 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 8845 } | |
| 8846 | |
| 8847 // C++ bool manipulation | |
| 0 | 8848 void MacroAssembler::testbool(Register dst) { |
| 8849 if(sizeof(bool) == 1) | |
| 304 | 8850 testb(dst, 0xff); |
| 0 | 8851 else if(sizeof(bool) == 2) { |
| 8852 // testw implementation needed for two byte bools | |
| 8853 ShouldNotReachHere(); | |
| 8854 } else if(sizeof(bool) == 4) | |
| 8855 testl(dst, dst); | |
| 8856 else | |
| 8857 // unsupported | |
| 8858 ShouldNotReachHere(); | |
| 8859 } | |
| 8860 | |
| 304 | 8861 void MacroAssembler::testptr(Register dst, Register src) { |
| 8862 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 8863 } | |
| 8864 | |
| 8865 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 8866 void MacroAssembler::tlab_allocate(Register obj, | |
| 8867 Register var_size_in_bytes, | |
| 8868 int con_size_in_bytes, | |
| 8869 Register t1, | |
| 8870 Register t2, | |
| 8871 Label& slow_case) { | |
| 8872 assert_different_registers(obj, t1, t2); | |
| 8873 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 8874 Register end = t2; | |
| 8875 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 8876 | |
| 8877 verify_tlab(); | |
| 8878 | |
| 8879 NOT_LP64(get_thread(thread)); | |
| 8880 | |
| 8881 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 8882 if (var_size_in_bytes == noreg) { | |
| 8883 lea(end, Address(obj, con_size_in_bytes)); | |
| 8884 } else { | |
| 8885 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 8886 } | |
| 8887 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 8888 jcc(Assembler::above, slow_case); | |
| 8889 | |
| 8890 // update the tlab top pointer | |
| 8891 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 8892 | |
| 8893 // recover var_size_in_bytes if necessary | |
| 8894 if (var_size_in_bytes == end) { | |
| 8895 subptr(var_size_in_bytes, obj); | |
| 8896 } | |
| 8897 verify_tlab(); | |
| 8898 } | |
| 8899 | |
| 8900 // Preserves rbx, and rdx. | |
|
2100
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diff
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|
8901 Register MacroAssembler::tlab_refill(Label& retry, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
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|
8902 Label& try_eden, |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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diff
changeset
|
8903 Label& slow_case) { |
| 304 | 8904 Register top = rax; |
| 8905 Register t1 = rcx; | |
| 8906 Register t2 = rsi; | |
| 8907 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 8908 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 8909 Label do_refill, discard_tlab; | |
| 8910 | |
| 8911 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 8912 // No allocation in the shared eden. | |
| 8913 jmp(slow_case); | |
| 8914 } | |
| 8915 | |
| 8916 NOT_LP64(get_thread(thread_reg)); | |
| 8917 | |
| 8918 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 8919 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 8920 | |
| 8921 // calculate amount of free space | |
| 8922 subptr(t1, top); | |
| 8923 shrptr(t1, LogHeapWordSize); | |
| 8924 | |
| 8925 // Retain tlab and allocate object in shared space if | |
| 8926 // the amount free in the tlab is too large to discard. | |
| 8927 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 8928 jcc(Assembler::lessEqual, discard_tlab); | |
| 8929 | |
| 8930 // Retain | |
| 8931 // %%% yuck as movptr... | |
| 8932 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 8933 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 8934 if (TLABStats) { | |
| 8935 // increment number of slow_allocations | |
| 8936 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 8937 } | |
| 8938 jmp(try_eden); | |
| 8939 | |
| 8940 bind(discard_tlab); | |
| 8941 if (TLABStats) { | |
| 8942 // increment number of refills | |
| 8943 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 8944 // accumulate wastage -- t1 is amount free in tlab | |
| 8945 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 8946 } | |
| 8947 | |
| 8948 // if tlab is currently allocated (top or end != null) then | |
| 8949 // fill [top, end + alignment_reserve) with array object | |
|
2100
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|
8950 testptr(top, top); |
| 304 | 8951 jcc(Assembler::zero, do_refill); |
| 8952 | |
| 8953 // set up the mark word | |
| 8954 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 8955 // set the length to the remaining space | |
| 8956 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 8957 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 8958 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 1690 | 8959 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
| 304 | 8960 // set klass to intArrayKlass |
| 8961 // dubious reloc why not an oop reloc? | |
|
2100
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|
8962 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); |
| 304 | 8963 // store klass last. concurrent gcs assumes klass length is valid if |
| 8964 // klass field is not null. | |
| 8965 store_klass(top, t1); | |
| 8966 | |
|
2100
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diff
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|
8967 movptr(t1, top); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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2014
diff
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|
8968 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
|
b1a2afa37ec4
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diff
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|
8969 incr_allocated_bytes(thread_reg, t1, 0); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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changeset
|
8970 |
| 304 | 8971 // refill the tlab with an eden allocation |
| 8972 bind(do_refill); | |
| 8973 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 8974 shlptr(t1, LogHeapWordSize); | |
|
2100
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diff
changeset
|
8975 // allocate new tlab, address returned in top |
| 304 | 8976 eden_allocate(top, t1, 0, t2, slow_case); |
| 8977 | |
| 8978 // Check that t1 was preserved in eden_allocate. | |
| 8979 #ifdef ASSERT | |
| 8980 if (UseTLAB) { | |
| 8981 Label ok; | |
| 8982 Register tsize = rsi; | |
| 8983 assert_different_registers(tsize, thread_reg, t1); | |
| 8984 push(tsize); | |
| 8985 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 8986 shlptr(tsize, LogHeapWordSize); | |
| 8987 cmpptr(t1, tsize); | |
| 8988 jcc(Assembler::equal, ok); | |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
8989 STOP("assert(t1 != tlab size)"); |
| 304 | 8990 should_not_reach_here(); |
| 8991 | |
| 8992 bind(ok); | |
| 8993 pop(tsize); | |
| 8994 } | |
| 8995 #endif | |
| 8996 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 8997 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 8998 addptr(top, t1); | |
| 8999 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 9000 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 9001 verify_tlab(); | |
| 9002 jmp(retry); | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
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diff
changeset
|
9003 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
changeset
|
9004 return thread_reg; // for use by caller |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
9005 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
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diff
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|
9006 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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|
9007 void MacroAssembler::incr_allocated_bytes(Register thread, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
9008 Register var_size_in_bytes, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
9009 int con_size_in_bytes, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
9010 Register t1) { |
|
4770
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9011 if (!thread->is_valid()) { |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9012 #ifdef _LP64 |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9013 thread = r15_thread; |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9014 #else |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9015 assert(t1->is_valid(), "need temp reg"); |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9016 thread = t1; |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9017 get_thread(thread); |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9018 #endif |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9019 } |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
9020 |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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|
9021 #ifdef _LP64 |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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changeset
|
9022 if (var_size_in_bytes->is_valid()) { |
|
b1a2afa37ec4
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diff
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|
9023 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
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diff
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|
9024 } else { |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
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|
9025 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
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diff
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|
9026 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
changeset
|
9027 #else |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
changeset
|
9028 if (var_size_in_bytes->is_valid()) { |
|
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diff
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|
9029 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
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diff
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|
9030 } else { |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
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|
9031 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
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|
9032 } |
|
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|
9033 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); |
|
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|
9034 #endif |
| 304 | 9035 } |
| 9036 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9037 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9038 pusha(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9039 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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diff
changeset
|
9040 // if we are coming from c1, xmm registers may be live |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9041 int off = 0; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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5984
diff
changeset
|
9042 if (UseSSE == 1) { |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
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6725
diff
changeset
|
9043 subptr(rsp, sizeof(jdouble)*8); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9044 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
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diff
changeset
|
9045 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9046 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9047 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9048 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9049 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9050 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9051 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9052 } else if (UseSSE >= 2) { |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9053 #ifdef COMPILER2 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9054 if (MaxVectorSize > 16) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9055 assert(UseAVX > 0, "256bit vectors are supported only with AVX"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9056 // Save upper half of YMM registes |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9057 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9058 vextractf128h(Address(rsp, 0),xmm0); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9059 vextractf128h(Address(rsp, 16),xmm1); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9060 vextractf128h(Address(rsp, 32),xmm2); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9061 vextractf128h(Address(rsp, 48),xmm3); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9062 vextractf128h(Address(rsp, 64),xmm4); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9063 vextractf128h(Address(rsp, 80),xmm5); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9064 vextractf128h(Address(rsp, 96),xmm6); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9065 vextractf128h(Address(rsp,112),xmm7); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9066 #ifdef _LP64 |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9067 vextractf128h(Address(rsp,128),xmm8); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9068 vextractf128h(Address(rsp,144),xmm9); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9069 vextractf128h(Address(rsp,160),xmm10); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9070 vextractf128h(Address(rsp,176),xmm11); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9071 vextractf128h(Address(rsp,192),xmm12); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9072 vextractf128h(Address(rsp,208),xmm13); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9073 vextractf128h(Address(rsp,224),xmm14); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9074 vextractf128h(Address(rsp,240),xmm15); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9075 #endif |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9076 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9077 #endif |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9078 // Save whole 128bit (16 bytes) XMM regiters |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9079 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9080 movdqu(Address(rsp,off++*16),xmm0); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9081 movdqu(Address(rsp,off++*16),xmm1); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9082 movdqu(Address(rsp,off++*16),xmm2); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9083 movdqu(Address(rsp,off++*16),xmm3); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9084 movdqu(Address(rsp,off++*16),xmm4); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9085 movdqu(Address(rsp,off++*16),xmm5); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9086 movdqu(Address(rsp,off++*16),xmm6); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9087 movdqu(Address(rsp,off++*16),xmm7); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9088 #ifdef _LP64 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9089 movdqu(Address(rsp,off++*16),xmm8); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9090 movdqu(Address(rsp,off++*16),xmm9); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9091 movdqu(Address(rsp,off++*16),xmm10); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9092 movdqu(Address(rsp,off++*16),xmm11); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9093 movdqu(Address(rsp,off++*16),xmm12); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9094 movdqu(Address(rsp,off++*16),xmm13); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9095 movdqu(Address(rsp,off++*16),xmm14); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9096 movdqu(Address(rsp,off++*16),xmm15); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9097 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9098 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9099 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9100 // Preserve registers across runtime call |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9101 int incoming_argument_and_return_value_offset = -1; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9102 if (num_fpu_regs_in_use > 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9103 // Must preserve all other FPU regs (could alternatively convert |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9104 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9105 // FPU state, but can not trust C compiler) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9106 NEEDS_CLEANUP; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9107 // NOTE that in this case we also push the incoming argument(s) to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9108 // the stack and restore it later; we also use this stack slot to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9109 // hold the return value from dsin, dcos etc. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9110 for (int i = 0; i < num_fpu_regs_in_use; i++) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9111 subptr(rsp, sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9112 fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9113 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9114 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9115 for (int i = nb_args-1; i >= 0; i--) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9116 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9117 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9118 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9119 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9120 subptr(rsp, nb_args*sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9121 for (int i = 0; i < nb_args; i++) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9122 fstp_d(Address(rsp, i*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9123 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9124 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9125 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9126 if (nb_args > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9127 movdbl(xmm0, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9128 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9129 if (nb_args > 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9130 movdbl(xmm1, Address(rsp, sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9131 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9132 assert(nb_args <= 2, "unsupported number of args"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9133 #endif // _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9134 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9135 // NOTE: we must not use call_VM_leaf here because that requires a |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9136 // complete interpreter frame in debug mode -- same bug as 4387334 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9137 // MacroAssembler::call_VM_leaf_base is perfectly safe and will |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9138 // do proper 64bit abi |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9139 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9140 NEEDS_CLEANUP; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9141 // Need to add stack banging before this runtime call if it needs to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9142 // be taken; however, there is no generic stack banging routine at |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9143 // the MacroAssembler level |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9144 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9145 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9146 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9147 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9148 movsd(Address(rsp, 0), xmm0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9149 fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9150 #endif // _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9151 addptr(rsp, sizeof(jdouble) * nb_args); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9152 if (num_fpu_regs_in_use > 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9153 // Must save return value to stack and then restore entire FPU |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9154 // stack except incoming arguments |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9155 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9156 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9157 fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9158 addptr(rsp, sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9159 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9160 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9161 addptr(rsp, sizeof(jdouble) * nb_args); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9162 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9163 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9164 off = 0; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9165 if (UseSSE == 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9166 movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9167 movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9168 movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9169 movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9170 movflt(xmm4, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9171 movflt(xmm5, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9172 movflt(xmm6, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9173 movflt(xmm7, Address(rsp,off++*sizeof(jdouble))); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9174 addptr(rsp, sizeof(jdouble)*8); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9175 } else if (UseSSE >= 2) { |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9176 // Restore whole 128bit (16 bytes) XMM regiters |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9177 movdqu(xmm0, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9178 movdqu(xmm1, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9179 movdqu(xmm2, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9180 movdqu(xmm3, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9181 movdqu(xmm4, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9182 movdqu(xmm5, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9183 movdqu(xmm6, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9184 movdqu(xmm7, Address(rsp,off++*16)); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9185 #ifdef _LP64 |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9186 movdqu(xmm8, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9187 movdqu(xmm9, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9188 movdqu(xmm10, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9189 movdqu(xmm11, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9190 movdqu(xmm12, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9191 movdqu(xmm13, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9192 movdqu(xmm14, Address(rsp,off++*16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9193 movdqu(xmm15, Address(rsp,off++*16)); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9194 #endif |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9195 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9196 #ifdef COMPILER2 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9197 if (MaxVectorSize > 16) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9198 // Restore upper half of YMM registes. |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9199 vinsertf128h(xmm0, Address(rsp, 0)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9200 vinsertf128h(xmm1, Address(rsp, 16)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9201 vinsertf128h(xmm2, Address(rsp, 32)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9202 vinsertf128h(xmm3, Address(rsp, 48)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9203 vinsertf128h(xmm4, Address(rsp, 64)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9204 vinsertf128h(xmm5, Address(rsp, 80)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9205 vinsertf128h(xmm6, Address(rsp, 96)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9206 vinsertf128h(xmm7, Address(rsp,112)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9207 #ifdef _LP64 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9208 vinsertf128h(xmm8, Address(rsp,128)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9209 vinsertf128h(xmm9, Address(rsp,144)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9210 vinsertf128h(xmm10, Address(rsp,160)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9211 vinsertf128h(xmm11, Address(rsp,176)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9212 vinsertf128h(xmm12, Address(rsp,192)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9213 vinsertf128h(xmm13, Address(rsp,208)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9214 vinsertf128h(xmm14, Address(rsp,224)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9215 vinsertf128h(xmm15, Address(rsp,240)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9216 #endif |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9217 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9218 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
9219 #endif |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9220 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9221 popa(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9222 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9223 |
| 304 | 9224 static const double pi_4 = 0.7853981633974483; |
| 9225 | |
| 9226 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 9227 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 9228 // was attempted in this code; unfortunately it appears that the | |
| 9229 // switch to 80-bit precision and back causes this to be | |
| 9230 // unprofitable compared with simply performing a runtime call if | |
| 9231 // the argument is out of the (-pi/4, pi/4) range. | |
| 9232 | |
| 9233 Register tmp = noreg; | |
| 9234 if (!VM_Version::supports_cmov()) { | |
| 9235 // fcmp needs a temporary so preserve rbx, | |
| 9236 tmp = rbx; | |
| 9237 push(tmp); | |
| 9238 } | |
| 9239 | |
| 9240 Label slow_case, done; | |
| 9241 | |
|
520
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9242 ExternalAddress pi4_adr = (address)&pi_4; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9243 if (reachable(pi4_adr)) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9244 // x ?<= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9245 fld_d(pi4_adr); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9246 fld_s(1); // Stack: X PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9247 fabs(); // Stack: |X| PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9248 fcmp(tmp); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9249 jcc(Assembler::above, slow_case); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9250 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9251 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9252 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9253 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9254 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9255 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9256 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9257 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9258 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9259 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9260 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9261 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9262 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9263 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9264 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9265 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9266 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
9267 } |
| 304 | 9268 |
| 9269 // slow case: runtime call | |
| 9270 bind(slow_case); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9271 |
| 304 | 9272 switch(trig) { |
| 9273 case 's': | |
| 9274 { | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9275 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); |
| 304 | 9276 } |
| 9277 break; | |
| 9278 case 'c': | |
| 9279 { | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9280 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); |
| 304 | 9281 } |
| 9282 break; | |
| 9283 case 't': | |
| 9284 { | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9285 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); |
| 304 | 9286 } |
| 9287 break; | |
| 9288 default: | |
| 9289 assert(false, "bad intrinsic"); | |
| 9290 break; | |
| 9291 } | |
| 9292 | |
| 9293 // Come here with result in F-TOS | |
| 9294 bind(done); | |
| 9295 | |
| 9296 if (tmp != noreg) { | |
| 9297 pop(tmp); | |
| 9298 } | |
| 9299 } | |
| 9300 | |
| 9301 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9302 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9303 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9304 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9305 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9306 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9307 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9308 Register intf_klass, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9309 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9310 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9311 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9312 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9313 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9314 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9315 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9316 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9317 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9318 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9319 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9320 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9321 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9322 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9323 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9324 |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9325 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9326 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9327 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9328 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9329 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9330 // Round up to align_object_offset boundary |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9331 // see code for InstanceKlass::start_of_itable! |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9332 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9333 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9334 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9335 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9336 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9337 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9338 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9339 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9340 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9341 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9342 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9343 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9344 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9345 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9346 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9347 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9348 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9349 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9350 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9351 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9352 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9353 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9354 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9355 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9356 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9357 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9358 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9359 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9360 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9361 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9362 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9363 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9364 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9365 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9366 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9367 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9368 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9369 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9370 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9371 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9372 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9373 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9374 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9375 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
9376 |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9377 // virtual method calling |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9378 void MacroAssembler::lookup_virtual_method(Register recv_klass, |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9379 RegisterOrConstant vtable_index, |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9380 Register method_result) { |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9381 const int base = InstanceKlass::vtable_start_offset() * wordSize; |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9382 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9383 Address vtable_entry_addr(recv_klass, |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9384 vtable_index, Address::times_ptr, |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9385 base + vtableEntry::method_offset_in_bytes()); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9386 movptr(method_result, vtable_entry_addr); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9387 } |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9388 |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9389 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9390 void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9391 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9392 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9393 Label& L_success) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9394 Label L_failure; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9395 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9396 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9397 bind(L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9398 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9399 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9400 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9401 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9402 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9403 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9404 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9405 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9406 Label* L_slow_path, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9407 RegisterOrConstant super_check_offset) { |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9408 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9409 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9410 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9411 assert_different_registers(sub_klass, super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9412 super_check_offset.as_register()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9413 } else if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9414 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9415 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9416 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9417 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9418 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9419 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9420 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9421 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9422 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9423 |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9424 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
|
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9425 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9426 Address super_check_offset_addr(super_klass, sco_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9427 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9428 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9429 // range of a jccb. If this routine grows larger, reconsider at |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9430 // least some of these. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9431 #define local_jcc(assembler_cond, label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9432 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9433 else jcc( assembler_cond, label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9434 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9435 // Hacked jmp, which may only be used just before L_fallthrough. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9436 #define final_jmp(label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9437 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9438 else jmp(label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9439 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9440 // If the pointers are equal, we are done (e.g., String[] elements). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9441 // This self-check enables sharing of secondary supertype arrays among |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9442 // non-primary types such as array-of-interface. Otherwise, each such |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9443 // type would need its own customized SSA. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9444 // We move this check to the front of the fast path because many |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9445 // type checks are in fact trivially successful in this manner, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9446 // so we get a nicely predicted branch right at the start of the check. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9447 cmpptr(sub_klass, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9448 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9449 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9450 // Check the supertype display: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9451 if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9452 // Positive movl does right thing on LP64. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9453 movl(temp_reg, super_check_offset_addr); |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9454 super_check_offset = RegisterOrConstant(temp_reg); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9455 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9456 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9457 cmpptr(super_klass, super_check_addr); // load displayed supertype |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9458 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9459 // This check has worked decisively for primary supers. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9460 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9461 // (Secondary supers are interfaces and very deeply nested subtypes.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9462 // This works in the same check above because of a tricky aliasing |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9463 // between the super_cache and the primary super display elements. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9464 // (The 'super_check_addr' can address either, as the case requires.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9465 // Note that the cache is updated below if it does not help us find |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9466 // what we need immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9467 // So if it was a primary super, we can just fail immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9468 // Otherwise, it's the slow path for us (no success at this point). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9469 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9470 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9471 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9472 cmpl(super_check_offset.as_register(), sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9473 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9474 local_jcc(Assembler::equal, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9475 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9476 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9477 final_jmp(*L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9478 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9479 } else if (super_check_offset.as_constant() == sc_offset) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9480 // Need a slow path; fast failure is impossible. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9481 if (L_slow_path == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9482 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9483 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9484 local_jcc(Assembler::notEqual, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9485 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9486 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9487 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9488 // No slow path; it's a fast decision. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9489 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9490 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9491 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9492 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9493 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9494 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9495 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9496 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9497 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9498 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9499 #undef local_jcc |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9500 #undef final_jmp |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9501 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9502 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9503 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9504 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9505 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9506 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9507 Register temp2_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9508 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9509 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9510 bool set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9511 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9512 if (temp2_reg != noreg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9513 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9514 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9515 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9516 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9517 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9518 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9519 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9520 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9521 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9522 // a couple of useful fields in sub_klass: |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9523 int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
|
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9524 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9525 Address secondary_supers_addr(sub_klass, ss_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9526 Address super_cache_addr( sub_klass, sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9527 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9528 // Do a linear scan of the secondary super-klass chain. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9529 // This code is rarely used, so simplicity is a virtue here. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9530 // The repne_scan instruction uses fixed registers, which we must spill. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9531 // Don't worry too much about pre-existing connections with the input regs. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9532 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9533 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9534 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9535 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9536 // Get super_klass value into rax (even if it was in rdi or rcx). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9537 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9538 if (super_klass != rax || UseCompressedOops) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9539 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9540 mov(rax, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9541 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9542 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9543 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9544 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9545 #ifndef PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9546 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9547 ExternalAddress pst_counter_addr((address) pst_counter); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9548 NOT_LP64( incrementl(pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9549 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9550 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9551 #endif //PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9552 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9553 // We will consult the secondary-super array. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9554 movptr(rdi, secondary_supers_addr); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9555 // Load the array length. (Positive movl does right thing on LP64.) |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9556 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9557 // Skip to start of data. |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9558 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9559 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9560 // Scan RCX words at [RDI] for an occurrence of RAX. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9561 // Set NZ/Z based on last compare. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9562 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9563 // not change flags (only scas instruction which is repeated sets flags). |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9564 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9565 |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9566 testptr(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9567 repne_scan(); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
9568 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9569 // Unspill the temp. registers: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9570 if (pushed_rdi) pop(rdi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9571 if (pushed_rcx) pop(rcx); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9572 if (pushed_rax) pop(rax); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9573 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9574 if (set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9575 // Special hack for the AD files: rdi is guaranteed non-zero. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9576 assert(!pushed_rdi, "rdi must be left non-NULL"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9577 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9578 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9579 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9580 if (L_failure == &L_fallthrough) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9581 jccb(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9582 else jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9583 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9584 // Success. Cache the super we found and proceed in triumph. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9585 movptr(super_cache_addr, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9586 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9587 if (L_success != &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9588 jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9589 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9590 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9591 #undef IS_A_TEMP |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9592 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9593 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9594 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9595 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
9596 |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9597 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9598 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9599 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9600 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9601 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9602 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9603 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9604 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9605 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9606 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9607 |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9608 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9609 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9610 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9611 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9612 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9613 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9614 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9615 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9616 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9617 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9618 |
| 0 | 9619 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 9620 if (!VerifyOops) return; | |
| 304 | 9621 |
| 0 | 9622 // Pass register number to verify_oop_subroutine |
| 9623 char* b = new char[strlen(s) + 50]; | |
| 9624 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9625 BLOCK_COMMENT("verify_oop {"); |
| 1583 | 9626 #ifdef _LP64 |
| 9627 push(rscratch1); // save r10, trashed by movptr() | |
| 9628 #endif | |
| 304 | 9629 push(rax); // save rax, |
| 9630 push(reg); // pass register argument | |
| 0 | 9631 ExternalAddress buffer((address) b); |
| 304 | 9632 // avoid using pushptr, as it modifies scratch registers |
| 9633 // and our contract is not to modify anything | |
| 9634 movptr(rax, buffer.addr()); | |
| 9635 push(rax); | |
| 0 | 9636 // call indirectly to solve generation ordering problem |
| 9637 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 9638 call(rax); | |
| 1583 | 9639 // Caller pops the arguments (oop, message) and restores rax, r10 |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9640 BLOCK_COMMENT("} verify_oop"); |
| 0 | 9641 } |
| 9642 | |
| 9643 | |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9644 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9645 Register tmp, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9646 int offset) { |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9647 intptr_t value = *delayed_value_addr; |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9648 if (value != 0) |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
9649 return RegisterOrConstant(value + offset); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9650 |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9651 // load indirectly to solve generation ordering problem |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9652 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9653 |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
9654 #ifdef ASSERT |
|
1793
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9655 { Label L; |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9656 testptr(tmp, tmp); |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9657 if (WizardMode) { |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9658 jcc(Assembler::notZero, L); |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9659 char* buf = new char[40]; |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9660 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
9661 STOP(buf); |
|
1793
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9662 } else { |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9663 jccb(Assembler::notZero, L); |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9664 hlt(); |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
parents:
1763
diff
changeset
|
9665 } |
|
d257356e35f0
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|
9666 bind(L); |
|
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|
9667 } |
|
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|
9668 #endif |
|
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|
9669 |
|
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|
9670 if (offset != 0) |
|
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|
9671 addptr(tmp, offset); |
|
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|
9672 |
|
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|
9673 return RegisterOrConstant(tmp); |
|
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|
9674 } |
|
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|
9675 |
|
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|
9676 |
| 710 | 9677 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, |
| 9678 int extra_slot_offset) { | |
| 9679 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
| 1506 | 9680 int stackElementSize = Interpreter::stackElementSize; |
| 710 | 9681 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
| 9682 #ifdef ASSERT | |
| 9683 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
| 9684 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
| 9685 #endif | |
| 9686 Register scale_reg = noreg; | |
| 9687 Address::ScaleFactor scale_factor = Address::no_scale; | |
| 9688 if (arg_slot.is_constant()) { | |
| 9689 offset += arg_slot.as_constant() * stackElementSize; | |
| 9690 } else { | |
| 9691 scale_reg = arg_slot.as_register(); | |
| 9692 scale_factor = Address::times(stackElementSize); | |
| 9693 } | |
| 9694 offset += wordSize; // return PC is on stack | |
| 9695 return Address(rsp, scale_reg, scale_factor, offset); | |
| 9696 } | |
| 9697 | |
| 9698 | |
| 0 | 9699 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 9700 if (!VerifyOops) return; | |
| 304 | 9701 |
| 0 | 9702 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 9703 // Pass register number to verify_oop_subroutine | |
| 9704 char* b = new char[strlen(s) + 50]; | |
| 9705 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 9706 |
| 1583 | 9707 #ifdef _LP64 |
| 9708 push(rscratch1); // save r10, trashed by movptr() | |
| 9709 #endif | |
| 304 | 9710 push(rax); // save rax, |
| 0 | 9711 // addr may contain rsp so we will have to adjust it based on the push |
|
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|
9712 // we just did (and on 64 bit we do two pushes) |
| 304 | 9713 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 9714 // stores rax into addr which is backwards of what was intended. | |
| 0 | 9715 if (addr.uses(rsp)) { |
| 304 | 9716 lea(rax, addr); |
|
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|
9717 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); |
| 0 | 9718 } else { |
| 304 | 9719 pushptr(addr); |
| 9720 } | |
| 9721 | |
| 0 | 9722 ExternalAddress buffer((address) b); |
| 9723 // pass msg argument | |
| 304 | 9724 // avoid using pushptr, as it modifies scratch registers |
| 9725 // and our contract is not to modify anything | |
| 9726 movptr(rax, buffer.addr()); | |
| 9727 push(rax); | |
| 9728 | |
| 0 | 9729 // call indirectly to solve generation ordering problem |
| 9730 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 9731 call(rax); | |
| 1583 | 9732 // Caller pops the arguments (addr, message) and restores rax, r10. |
| 0 | 9733 } |
| 9734 | |
| 304 | 9735 void MacroAssembler::verify_tlab() { |
| 9736 #ifdef ASSERT | |
| 9737 if (UseTLAB && VerifyOops) { | |
| 9738 Label next, ok; | |
| 9739 Register t1 = rsi; | |
| 9740 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 9741 | |
| 9742 push(t1); | |
| 9743 NOT_LP64(push(thread_reg)); | |
| 9744 NOT_LP64(get_thread(thread_reg)); | |
| 9745 | |
| 9746 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 9747 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 9748 jcc(Assembler::aboveEqual, next); | |
|
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|
9749 STOP("assert(top >= start)"); |
| 304 | 9750 should_not_reach_here(); |
| 9751 | |
| 9752 bind(next); | |
| 9753 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 9754 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 9755 jcc(Assembler::aboveEqual, ok); | |
|
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|
9756 STOP("assert(top <= end)"); |
| 304 | 9757 should_not_reach_here(); |
| 9758 | |
| 9759 bind(ok); | |
| 9760 NOT_LP64(pop(thread_reg)); | |
| 9761 pop(t1); | |
| 9762 } | |
| 9763 #endif | |
| 9764 } | |
| 0 | 9765 |
| 9766 class ControlWord { | |
| 9767 public: | |
| 9768 int32_t _value; | |
| 9769 | |
| 9770 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 9771 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 9772 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 9773 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 9774 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 9775 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 9776 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 9777 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 9778 | |
| 9779 void print() const { | |
| 9780 // rounding control | |
| 9781 const char* rc; | |
| 9782 switch (rounding_control()) { | |
| 9783 case 0: rc = "round near"; break; | |
| 9784 case 1: rc = "round down"; break; | |
| 9785 case 2: rc = "round up "; break; | |
| 9786 case 3: rc = "chop "; break; | |
| 9787 }; | |
| 9788 // precision control | |
| 9789 const char* pc; | |
| 9790 switch (precision_control()) { | |
| 9791 case 0: pc = "24 bits "; break; | |
| 9792 case 1: pc = "reserved"; break; | |
| 9793 case 2: pc = "53 bits "; break; | |
| 9794 case 3: pc = "64 bits "; break; | |
| 9795 }; | |
| 9796 // flags | |
| 9797 char f[9]; | |
| 9798 f[0] = ' '; | |
| 9799 f[1] = ' '; | |
| 9800 f[2] = (precision ()) ? 'P' : 'p'; | |
| 9801 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 9802 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 9803 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 9804 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 9805 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 9806 f[8] = '\x0'; | |
| 9807 // output | |
| 9808 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 9809 } | |
| 9810 | |
| 9811 }; | |
| 9812 | |
| 9813 class StatusWord { | |
| 9814 public: | |
| 9815 int32_t _value; | |
| 9816 | |
| 9817 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 9818 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 9819 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 9820 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 9821 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 9822 int top() const { return (_value >> 11) & 7 ; } | |
| 9823 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 9824 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 9825 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 9826 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 9827 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 9828 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 9829 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 9830 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 9831 | |
| 9832 void print() const { | |
| 9833 // condition codes | |
| 9834 char c[5]; | |
| 9835 c[0] = (C3()) ? '3' : '-'; | |
| 9836 c[1] = (C2()) ? '2' : '-'; | |
| 9837 c[2] = (C1()) ? '1' : '-'; | |
| 9838 c[3] = (C0()) ? '0' : '-'; | |
| 9839 c[4] = '\x0'; | |
| 9840 // flags | |
| 9841 char f[9]; | |
| 9842 f[0] = (error_status()) ? 'E' : '-'; | |
| 9843 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 9844 f[2] = (precision ()) ? 'P' : '-'; | |
| 9845 f[3] = (underflow ()) ? 'U' : '-'; | |
| 9846 f[4] = (overflow ()) ? 'O' : '-'; | |
| 9847 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 9848 f[6] = (denormalized()) ? 'D' : '-'; | |
| 9849 f[7] = (invalid ()) ? 'I' : '-'; | |
| 9850 f[8] = '\x0'; | |
| 9851 // output | |
| 9852 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 9853 } | |
| 9854 | |
| 9855 }; | |
| 9856 | |
| 9857 class TagWord { | |
| 9858 public: | |
| 9859 int32_t _value; | |
| 9860 | |
| 9861 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 9862 | |
| 9863 void print() const { | |
| 9864 printf("%04x", _value & 0xFFFF); | |
| 9865 } | |
| 9866 | |
| 9867 }; | |
| 9868 | |
| 9869 class FPU_Register { | |
| 9870 public: | |
| 9871 int32_t _m0; | |
| 9872 int32_t _m1; | |
| 9873 int16_t _ex; | |
| 9874 | |
| 9875 bool is_indefinite() const { | |
| 9876 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 9877 } | |
| 9878 | |
| 9879 void print() const { | |
| 9880 char sign = (_ex < 0) ? '-' : '+'; | |
| 9881 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 9882 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 9883 }; | |
| 9884 | |
| 9885 }; | |
| 9886 | |
| 9887 class FPU_State { | |
| 9888 public: | |
| 9889 enum { | |
| 9890 register_size = 10, | |
| 9891 number_of_registers = 8, | |
| 9892 register_mask = 7 | |
| 9893 }; | |
| 9894 | |
| 9895 ControlWord _control_word; | |
| 9896 StatusWord _status_word; | |
| 9897 TagWord _tag_word; | |
| 9898 int32_t _error_offset; | |
| 9899 int32_t _error_selector; | |
| 9900 int32_t _data_offset; | |
| 9901 int32_t _data_selector; | |
| 9902 int8_t _register[register_size * number_of_registers]; | |
| 9903 | |
| 9904 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 9905 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 9906 | |
| 9907 const char* tag_as_string(int tag) const { | |
| 9908 switch (tag) { | |
| 9909 case 0: return "valid"; | |
| 9910 case 1: return "zero"; | |
| 9911 case 2: return "special"; | |
| 9912 case 3: return "empty"; | |
| 9913 } | |
|
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|
9914 ShouldNotReachHere(); |
| 0 | 9915 return NULL; |
| 9916 } | |
| 9917 | |
| 9918 void print() const { | |
| 9919 // print computation registers | |
| 9920 { int t = _status_word.top(); | |
| 9921 for (int i = 0; i < number_of_registers; i++) { | |
| 9922 int j = (i - t) & register_mask; | |
| 9923 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 9924 st(j)->print(); | |
| 9925 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 9926 } | |
| 9927 } | |
| 9928 printf("\n"); | |
| 9929 // print control registers | |
| 9930 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 9931 printf("stat = "); _status_word .print(); printf("\n"); | |
| 9932 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 9933 } | |
| 9934 | |
| 9935 }; | |
| 9936 | |
| 9937 class Flag_Register { | |
| 9938 public: | |
| 9939 int32_t _value; | |
| 9940 | |
| 9941 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 9942 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 9943 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 9944 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 9945 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 9946 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 9947 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 9948 | |
| 9949 void print() const { | |
| 9950 // flags | |
| 9951 char f[8]; | |
| 9952 f[0] = (overflow ()) ? 'O' : '-'; | |
| 9953 f[1] = (direction ()) ? 'D' : '-'; | |
| 9954 f[2] = (sign ()) ? 'S' : '-'; | |
| 9955 f[3] = (zero ()) ? 'Z' : '-'; | |
| 9956 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 9957 f[5] = (parity ()) ? 'P' : '-'; | |
| 9958 f[6] = (carry ()) ? 'C' : '-'; | |
| 9959 f[7] = '\x0'; | |
| 9960 // output | |
| 9961 printf("%08x flags = %s", _value, f); | |
| 9962 } | |
| 9963 | |
| 9964 }; | |
| 9965 | |
| 9966 class IU_Register { | |
| 9967 public: | |
| 9968 int32_t _value; | |
| 9969 | |
| 9970 void print() const { | |
| 9971 printf("%08x %11d", _value, _value); | |
| 9972 } | |
| 9973 | |
| 9974 }; | |
| 9975 | |
| 9976 class IU_State { | |
| 9977 public: | |
| 9978 Flag_Register _eflags; | |
| 9979 IU_Register _rdi; | |
| 9980 IU_Register _rsi; | |
| 9981 IU_Register _rbp; | |
| 9982 IU_Register _rsp; | |
| 9983 IU_Register _rbx; | |
| 9984 IU_Register _rdx; | |
| 9985 IU_Register _rcx; | |
| 9986 IU_Register _rax; | |
| 9987 | |
| 9988 void print() const { | |
| 9989 // computation registers | |
| 9990 printf("rax, = "); _rax.print(); printf("\n"); | |
| 9991 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 9992 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 9993 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 9994 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 9995 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 9996 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 9997 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 9998 printf("\n"); | |
| 9999 // control registers | |
| 10000 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 10001 } | |
| 10002 }; | |
| 10003 | |
| 10004 | |
| 10005 class CPU_State { | |
| 10006 public: | |
| 10007 FPU_State _fpu_state; | |
| 10008 IU_State _iu_state; | |
| 10009 | |
| 10010 void print() const { | |
| 10011 printf("--------------------------------------------------\n"); | |
| 10012 _iu_state .print(); | |
| 10013 printf("\n"); | |
| 10014 _fpu_state.print(); | |
| 10015 printf("--------------------------------------------------\n"); | |
| 10016 } | |
| 10017 | |
| 10018 }; | |
| 10019 | |
| 10020 | |
| 10021 static void _print_CPU_state(CPU_State* state) { | |
| 10022 state->print(); | |
| 10023 }; | |
| 10024 | |
| 10025 | |
| 10026 void MacroAssembler::print_CPU_state() { | |
| 10027 push_CPU_state(); | |
| 304 | 10028 push(rsp); // pass CPU state |
| 0 | 10029 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 10030 addptr(rsp, wordSize); // discard argument |
| 0 | 10031 pop_CPU_state(); |
| 10032 } | |
| 10033 | |
| 10034 | |
| 10035 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 10036 static int counter = 0; | |
| 10037 FPU_State* fs = &state->_fpu_state; | |
| 10038 counter++; | |
| 10039 // For leaf calls, only verify that the top few elements remain empty. | |
| 10040 // We only need 1 empty at the top for C2 code. | |
| 10041 if( stack_depth < 0 ) { | |
| 10042 if( fs->tag_for_st(7) != 3 ) { | |
| 10043 printf("FPR7 not empty\n"); | |
| 10044 state->print(); | |
| 10045 assert(false, "error"); | |
| 10046 return false; | |
| 10047 } | |
| 10048 return true; // All other stack states do not matter | |
| 10049 } | |
| 10050 | |
| 10051 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 10052 "bad FPU control word"); | |
| 10053 | |
| 10054 // compute stack depth | |
| 10055 int i = 0; | |
| 10056 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 10057 int d = i; | |
| 10058 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 10059 // verify findings | |
| 10060 if (i != FPU_State::number_of_registers) { | |
| 10061 // stack not contiguous | |
| 10062 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 10063 state->print(); | |
| 10064 assert(false, "error"); | |
| 10065 return false; | |
| 10066 } | |
| 10067 // check if computed stack depth corresponds to expected stack depth | |
| 10068 if (stack_depth < 0) { | |
| 10069 // expected stack depth is -stack_depth or less | |
| 10070 if (d > -stack_depth) { | |
| 10071 // too many elements on the stack | |
| 10072 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 10073 state->print(); | |
| 10074 assert(false, "error"); | |
| 10075 return false; | |
| 10076 } | |
| 10077 } else { | |
| 10078 // expected stack depth is stack_depth | |
| 10079 if (d != stack_depth) { | |
| 10080 // wrong stack depth | |
| 10081 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 10082 state->print(); | |
| 10083 assert(false, "error"); | |
| 10084 return false; | |
| 10085 } | |
| 10086 } | |
| 10087 // everything is cool | |
| 10088 return true; | |
| 10089 } | |
| 10090 | |
| 10091 | |
| 10092 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 10093 if (!VerifyFPU) return; | |
| 10094 push_CPU_state(); | |
| 304 | 10095 push(rsp); // pass CPU state |
| 0 | 10096 ExternalAddress msg((address) s); |
| 10097 // pass message string s | |
| 10098 pushptr(msg.addr()); | |
| 304 | 10099 push(stack_depth); // pass stack depth |
| 0 | 10100 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 10101 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 10102 // check for error |
| 10103 { Label L; | |
| 10104 testl(rax, rax); | |
| 10105 jcc(Assembler::notZero, L); | |
| 10106 int3(); // break if error condition | |
| 10107 bind(L); | |
| 10108 } | |
| 10109 pop_CPU_state(); | |
| 10110 } | |
| 10111 | |
| 304 | 10112 void MacroAssembler::load_klass(Register dst, Register src) { |
| 10113 #ifdef _LP64 | |
|
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10114 if (UseCompressedKlassPointers) { |
| 304 | 10115 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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10116 decode_klass_not_null(dst); |
| 304 | 10117 } else |
| 10118 #endif | |
| 10119 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 10120 } | |
| 10121 | |
| 10122 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 10123 #ifdef _LP64 | |
|
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10124 if (UseCompressedKlassPointers) { |
|
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10125 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 10126 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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|
10127 if (Universe::narrow_klass_shift() != 0) { |
|
8e47bac5643a
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|
10128 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
8e47bac5643a
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|
10129 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); |
|
8e47bac5643a
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|
10130 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset())); |
|
642
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|
10131 } else { |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
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|
10132 movq(dst, Address(dst, Klass::prototype_header_offset())); |
|
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|
10133 } |
| 304 | 10134 } else |
| 10135 #endif | |
|
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|
10136 { |
|
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|
10137 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
4762
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|
10138 movptr(dst, Address(dst, Klass::prototype_header_offset())); |
|
642
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|
10139 } |
| 304 | 10140 } |
| 10141 | |
| 10142 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 10143 #ifdef _LP64 | |
|
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|
10144 if (UseCompressedKlassPointers) { |
|
6848
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|
10145 encode_klass_not_null(src); |
| 304 | 10146 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); |
| 10147 } else | |
| 10148 #endif | |
| 10149 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 10150 } | |
| 10151 | |
| 1846 | 10152 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
| 10153 #ifdef _LP64 | |
|
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|
10154 // FIXME: Must change all places where we try to load the klass. |
| 1846 | 10155 if (UseCompressedOops) { |
| 10156 movl(dst, src); | |
| 10157 decode_heap_oop(dst); | |
| 10158 } else | |
| 10159 #endif | |
| 10160 movptr(dst, src); | |
| 10161 } | |
| 10162 | |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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|
10163 // Doesn't do verfication, generates fixed size code |
|
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7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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|
10164 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { |
|
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|
10165 #ifdef _LP64 |
|
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|
10166 if (UseCompressedOops) { |
|
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|
10167 movl(dst, src); |
|
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|
10168 decode_heap_oop_not_null(dst); |
|
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|
10169 } else |
|
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7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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|
10170 #endif |
|
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|
10171 movptr(dst, src); |
|
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|
10172 } |
|
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7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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|
10173 |
| 1846 | 10174 void MacroAssembler::store_heap_oop(Address dst, Register src) { |
| 10175 #ifdef _LP64 | |
| 10176 if (UseCompressedOops) { | |
| 10177 assert(!dst.uses(src), "not enough registers"); | |
| 10178 encode_heap_oop(src); | |
| 10179 movl(dst, src); | |
| 10180 } else | |
| 10181 #endif | |
| 10182 movptr(dst, src); | |
| 10183 } | |
| 10184 | |
|
6266
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|
10185 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
10186 assert_different_registers(src1, tmp); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
10187 #ifdef _LP64 |
|
1d7922586cf6
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|
10188 if (UseCompressedOops) { |
|
1d7922586cf6
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|
10189 bool did_push = false; |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
10190 if (tmp == noreg) { |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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6225
diff
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|
10191 tmp = rax; |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
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6225
diff
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|
10192 push(tmp); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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6225
diff
changeset
|
10193 did_push = true; |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
changeset
|
10194 assert(!src2.uses(rsp), "can't push"); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
10195 } |
|
1d7922586cf6
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|
10196 load_heap_oop(tmp, src2); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
10197 cmpptr(src1, tmp); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
10198 if (did_push) pop(tmp); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
10199 } else |
|
1d7922586cf6
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diff
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|
10200 #endif |
|
1d7922586cf6
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|
10201 cmpptr(src1, src2); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
10202 } |
|
1d7922586cf6
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|
10203 |
| 1846 | 10204 // Used for storing NULLs. |
| 10205 void MacroAssembler::store_heap_oop_null(Address dst) { | |
| 10206 #ifdef _LP64 | |
| 10207 if (UseCompressedOops) { | |
| 10208 movl(dst, (int32_t)NULL_WORD); | |
| 10209 } else { | |
| 10210 movslq(dst, (int32_t)NULL_WORD); | |
| 10211 } | |
| 10212 #else | |
| 10213 movl(dst, (int32_t)NULL_WORD); | |
| 10214 #endif | |
| 10215 } | |
| 10216 | |
| 304 | 10217 #ifdef _LP64 |
| 10218 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
|
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|
10219 if (UseCompressedKlassPointers) { |
| 304 | 10220 // Store to klass gap in destination |
| 10221 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 10222 } | |
| 10223 } | |
| 10224 | |
|
1684
66c5dadb4d61
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|
10225 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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|
10226 void MacroAssembler::verify_heapbase(const char* msg) { |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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diff
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|
10227 assert (UseCompressedOops || UseCompressedKlassPointers, "should be compressed"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
10228 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
10229 if (CheckCompressedOops) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
10230 Label ok; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
10231 push(rscratch1); // cmpptr trashes rscratch1 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
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6792
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changeset
|
10232 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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|
10233 jcc(Assembler::equal, ok); |
|
6266
1d7922586cf6
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|
10234 STOP(msg); |
|
1684
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6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10235 bind(ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10236 pop(rscratch1); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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|
10237 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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|
10238 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10239 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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|
10240 |
| 304 | 10241 // Algorithm must match oop.inline.hpp encode_heap_oop. |
| 10242 void MacroAssembler::encode_heap_oop(Register r) { | |
|
1684
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6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10243 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10244 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10245 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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changeset
|
10246 verify_oop(r, "broken oop in encode_heap_oop"); |
|
642
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|
10247 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
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changeset
|
10248 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
10249 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
10250 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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|
10251 } |
|
660978a2a31a
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|
10252 return; |
|
660978a2a31a
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|
10253 } |
| 304 | 10254 testq(r, r); |
| 10255 cmovq(Assembler::equal, r, r12_heapbase); | |
| 10256 subq(r, r12_heapbase); | |
| 10257 shrq(r, LogMinObjAlignmentInBytes); | |
| 10258 } | |
| 10259 | |
| 10260 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 0 | 10261 #ifdef ASSERT |
|
1684
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changeset
|
10262 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
| 304 | 10263 if (CheckCompressedOops) { |
| 0 | 10264 Label ok; |
| 304 | 10265 testq(r, r); |
| 10266 jcc(Assembler::notEqual, ok); | |
|
6266
1d7922586cf6
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|
10267 STOP("null oop passed to encode_heap_oop_not_null"); |
| 0 | 10268 bind(ok); |
| 304 | 10269 } |
| 10270 #endif | |
| 10271 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
|
642
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changeset
|
10272 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
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changeset
|
10273 subq(r, r12_heapbase); |
|
660978a2a31a
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|
10274 } |
|
660978a2a31a
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changeset
|
10275 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
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changeset
|
10276 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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changeset
|
10277 shrq(r, LogMinObjAlignmentInBytes); |
|
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|
10278 } |
| 304 | 10279 } |
| 10280 | |
| 10281 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 10282 #ifdef ASSERT | |
|
1684
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changeset
|
10283 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
| 304 | 10284 if (CheckCompressedOops) { |
| 10285 Label ok; | |
| 10286 testq(src, src); | |
| 10287 jcc(Assembler::notEqual, ok); | |
|
6266
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changeset
|
10288 STOP("null oop passed to encode_heap_oop_not_null2"); |
| 304 | 10289 bind(ok); |
| 0 | 10290 } |
| 10291 #endif | |
| 304 | 10292 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 10293 if (dst != src) { | |
| 10294 movq(dst, src); | |
| 10295 } | |
|
642
660978a2a31a
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changeset
|
10296 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
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changeset
|
10297 subq(dst, r12_heapbase); |
|
660978a2a31a
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|
10298 } |
|
660978a2a31a
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changeset
|
10299 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
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diff
changeset
|
10300 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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changeset
|
10301 shrq(dst, LogMinObjAlignmentInBytes); |
|
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|
10302 } |
| 304 | 10303 } |
| 10304 | |
| 10305 void MacroAssembler::decode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10306 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10307 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10308 #endif |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10309 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10310 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10311 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10312 shlq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10313 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10314 } else { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10315 Label done; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10316 shlq(r, LogMinObjAlignmentInBytes); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10317 jccb(Assembler::equal, done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10318 addq(r, r12_heapbase); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10319 bind(done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10320 } |
| 304 | 10321 verify_oop(r, "broken oop in decode_heap_oop"); |
| 10322 } | |
| 10323 | |
| 10324 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10325 // Note: it will change flags |
| 304 | 10326 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10327 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 10328 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 10329 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 10330 // Also do not verify_oop as this is called by verify_oop. | |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
10331 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10332 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10333 shlq(r, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10334 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10335 addq(r, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10336 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10337 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
10338 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10339 } |
| 304 | 10340 } |
| 10341 | |
| 10342 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10343 // Note: it will change flags |
| 304 | 10344 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10345 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 10346 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 10347 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 10348 // Also do not verify_oop as this is called by verify_oop. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10349 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10350 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10351 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10352 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10353 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10354 if (dst != src) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10355 movq(dst, src); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10356 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10357 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10358 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10359 addq(dst, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10360 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
10361 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10362 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
10363 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10364 if (dst != src) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10365 movq(dst, src); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
10366 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10367 } |
| 304 | 10368 } |
| 10369 | |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10370 void MacroAssembler::encode_klass_not_null(Register r) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10371 assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10372 #ifdef ASSERT |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10373 verify_heapbase("MacroAssembler::encode_klass_not_null: heap base corrupted?"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10374 #endif |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10375 if (Universe::narrow_klass_base() != NULL) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10376 subq(r, r12_heapbase); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10377 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10378 if (Universe::narrow_klass_shift() != 0) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10379 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10380 shrq(r, LogKlassAlignmentInBytes); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10381 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10382 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10383 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10384 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10385 assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10386 #ifdef ASSERT |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10387 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10388 #endif |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10389 if (dst != src) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10390 movq(dst, src); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10391 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10392 if (Universe::narrow_klass_base() != NULL) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10393 subq(dst, r12_heapbase); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10394 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10395 if (Universe::narrow_klass_shift() != 0) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10396 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10397 shrq(dst, LogKlassAlignmentInBytes); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10398 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10399 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10400 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10401 void MacroAssembler::decode_klass_not_null(Register r) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10402 assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10403 // Note: it will change flags |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10404 assert (UseCompressedKlassPointers, "should only be used for compressed headers"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10405 // Cannot assert, unverified entry point counts instructions (see .ad file) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10406 // vtableStubs also counts instructions in pd_code_size_limit. |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10407 // Also do not verify_oop as this is called by verify_oop. |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10408 if (Universe::narrow_klass_shift() != 0) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10409 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10410 shlq(r, LogKlassAlignmentInBytes); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10411 if (Universe::narrow_klass_base() != NULL) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10412 addq(r, r12_heapbase); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10413 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10414 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10415 assert (Universe::narrow_klass_base() == NULL, "sanity"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10416 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10417 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10418 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10419 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10420 assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10421 // Note: it will change flags |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10422 assert (UseCompressedKlassPointers, "should only be used for compressed headers"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10423 // Cannot assert, unverified entry point counts instructions (see .ad file) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10424 // vtableStubs also counts instructions in pd_code_size_limit. |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10425 // Also do not verify_oop as this is called by verify_oop. |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10426 if (Universe::narrow_klass_shift() != 0) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10427 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10428 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10429 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10430 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10431 assert (Universe::narrow_klass_base() == NULL, "sanity"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10432 if (dst != src) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10433 movq(dst, src); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10434 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10435 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10436 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10437 |
| 304 | 10438 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10439 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10440 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10441 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10442 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10443 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10444 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10445 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10446 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10447 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10448 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10449 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10450 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
| 304 | 10451 int oop_index = oop_recorder()->find_index(obj); |
| 10452 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10453 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10454 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10455 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10456 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10457 assert (UseCompressedKlassPointers, "should only be used for compressed headers"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10458 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10459 int klass_index = oop_recorder()->find_index(k); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10460 RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10461 mov_narrow_oop(dst, oopDesc::encode_klass(k), rspec); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10462 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10463 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10464 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10465 assert (UseCompressedKlassPointers, "should only be used for compressed headers"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10466 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10467 int klass_index = oop_recorder()->find_index(k); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10468 RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10469 mov_narrow_oop(dst, oopDesc::encode_klass(k), rspec); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10470 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10471 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10472 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10473 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10474 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10475 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10476 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10477 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10478 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10479 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10480 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10481 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10482 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10483 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10484 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10485 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10486 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10487 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
| 304 | 10488 } |
| 10489 | |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10490 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10491 assert (UseCompressedKlassPointers, "should only be used for compressed headers"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10492 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10493 int klass_index = oop_recorder()->find_index(k); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10494 RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10495 Assembler::cmp_narrow_oop(dst, oopDesc::encode_klass(k), rspec); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10496 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10497 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10498 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10499 assert (UseCompressedKlassPointers, "should only be used for compressed headers"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10500 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10501 int klass_index = oop_recorder()->find_index(k); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10502 RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10503 Assembler::cmp_narrow_oop(dst, oopDesc::encode_klass(k), rspec); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10504 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10505 |
| 304 | 10506 void MacroAssembler::reinit_heapbase() { |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10507 if (UseCompressedOops || UseCompressedKlassPointers) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6792
diff
changeset
|
10508 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); |
| 304 | 10509 } |
| 10510 } | |
| 10511 #endif // _LP64 | |
| 0 | 10512 |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10513 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10514 // C2 compiled method's prolog code. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10515 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10516 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10517 // WARNING: Initial instruction MUST be 5 bytes or longer so that |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10518 // NativeJump::patch_verified_entry will be able to patch out the entry |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10519 // code safely. The push to verify stack depth is ok at 5 bytes, |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10520 // the frame allocation can be either 3 or 6 bytes. So if we don't do |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10521 // stack bang then we must use the 6 byte frame allocation even if |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10522 // we have no frame. :-( |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10523 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10524 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10525 // Remove word for return addr |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10526 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10527 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10528 // Calls to C2R adapters often do not accept exceptional returns. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10529 // We require that their callers must bang for them. But be careful, because |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10530 // some VM calls (such as call site linkage) can use several kilobytes of |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10531 // stack. But the stack safety zone should account for that. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10532 // See bugs 4446381, 4468289, 4497237. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10533 if (stack_bang) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10534 generate_stack_overflow_check(framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10535 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10536 // We always push rbp, so that on return to interpreter rbp, will be |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10537 // restored correctly and we can correct the stack. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10538 push(rbp); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10539 // Remove word for ebp |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10540 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10541 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10542 // Create frame |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10543 if (framesize) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10544 subptr(rsp, framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10545 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10546 } else { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10547 // Create frame (force generation of a 4 byte immediate value) |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10548 subptr_imm32(rsp, framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10549 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10550 // Save RBP register now. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10551 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10552 movptr(Address(rsp, framesize), rbp); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10553 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10554 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10555 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10556 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10557 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10558 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10559 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10560 #ifndef _LP64 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10561 // If method sets FPU control word do it now |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10562 if (fp_mode_24b) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10563 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10564 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10565 if (UseSSE >= 2 && VerifyFPU) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10566 verify_FPU(0, "FPU stack must be clean on entry"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10567 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10568 #endif |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10569 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10570 #ifdef ASSERT |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10571 if (VerifyStackAtCalls) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10572 Label L; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10573 push(rax); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10574 mov(rax, rsp); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10575 andptr(rax, StackAlignmentInBytes-1); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10576 cmpptr(rax, StackAlignmentInBytes-wordSize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10577 pop(rax); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10578 jcc(Assembler::equal, L); |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6225
diff
changeset
|
10579 STOP("Stack is not properly aligned!"); |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10580 bind(L); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10581 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10582 #endif |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10583 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10584 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10585 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
10586 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10587 // IndexOf for constant substrings with size >= 8 chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10588 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10589 void MacroAssembler::string_indexofC8(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10590 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10591 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10592 XMMRegister vec, Register tmp) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
10593 ShortBranchVerifier sbv(this); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10594 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10595 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10596 // This method uses pcmpestri inxtruction with bound registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10597 // inputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10598 // xmm - substring |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10599 // rax - substring length (elements count) |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10600 // mem - scanned string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10601 // rdx - string length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10602 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10603 // outputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10604 // rcx - matched index in string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10605 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10606 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10607 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10608 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10609 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10610 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10611 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10612 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10613 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10614 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10615 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10616 // Load substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10617 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10618 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10619 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10620 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10621 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10622 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10623 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10624 // Reload substr for rescan, this code |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10625 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10626 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10627 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10628 negptr(cnt2); // Jumped here with negative cnt2, convert to positive |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10629 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10630 bind(RELOAD_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10631 // We came here after the beginning of the substring was |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10632 // matched but the rest of it was not so we need to search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10633 // again. Start from the next element after the previous match. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10634 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10635 // cnt2 is number of substring reminding elements and |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10636 // cnt1 is number of string reminding elements when cmp failed. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10637 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10638 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10639 addl(cnt1, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10640 movl(cnt2, int_cnt2); // Now restore cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10641 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10642 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10643 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10644 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10645 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10646 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10647 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10648 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10649 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10650 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10651 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10652 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10653 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10654 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10655 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10656 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10657 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10658 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10659 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10660 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10661 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10662 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10663 // Matched whole vector if first element matched (tmp(rcx) == 0). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10664 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10665 jccb(Assembler::overflow, RET_FOUND); // OF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10666 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10667 jccb(Assembler::overflow, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10668 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10669 // After pcmpestri tmp(rcx) contains matched element index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10670 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10671 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10672 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10673 // Make sure string is still long enough |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10674 subl(cnt1, tmp); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10675 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10676 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10677 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10678 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10679 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10680 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10681 // Left less then substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10682 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10683 bind(RET_NOT_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10684 movl(result, -1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10685 jmpb(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10686 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10687 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10688 // This code is optimized for the case when whole substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10689 // is matched if its head is matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10690 bind(MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10691 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10692 // Reload only string if does not match |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10693 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10694 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10695 Label CONT_SCAN_SUBSTR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10696 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10697 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10698 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10699 negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10700 addptr(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10701 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10702 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10703 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10704 cmpl(cnt2, -8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10705 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10706 // Back-up strings to avoid reading beyond substring: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10707 // cnt1 = cnt1 - cnt2 + 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10708 addl(cnt1, cnt2); // cnt2 is negative |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10709 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10710 movl(cnt2, 8); negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10711 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10712 if (int_cnt2 < (int)G) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10713 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10714 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10715 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10716 // calculate index in register to avoid integer overflow (int_cnt2*2) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10717 movl(tmp, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10718 addptr(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10719 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10720 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10721 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10722 // Need to reload strings pointers if not matched whole vector |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
10723 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10724 addptr(cnt2, 8); |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
10725 jcc(Assembler::negative, SCAN_SUBSTR); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10726 // Fall through if found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10727 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10728 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10729 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10730 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10731 // Found result if we matched full small substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10732 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10733 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10734 shrl(result, 1); // index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10735 bind(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10736 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10737 } // string_indexofC8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10738 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10739 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10740 void MacroAssembler::string_indexof(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10741 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10742 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10743 XMMRegister vec, Register tmp) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
10744 ShortBranchVerifier sbv(this); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10745 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10746 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10747 // int_cnt2 is length of small (< 8 chars) constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10748 // or (-1) for non constant substring in which case its length |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10749 // is in cnt2 register. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10750 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10751 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10752 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10753 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10754 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10755 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10756 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10757 // This method uses pcmpestri inxtruction with bound registers |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10758 // inputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10759 // xmm - substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10760 // rax - substring length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10761 // mem - scanned string |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10762 // rdx - string length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10763 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10764 // outputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10765 // rcx - matched index in string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10766 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10767 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10768 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10769 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10770 FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10771 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10772 { //======================================================== |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10773 // We don't know where these strings are located |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10774 // and we can't read beyond them. Load them through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10775 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10776 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10777 movptr(tmp, rsp); // save old SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10778 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10779 if (int_cnt2 > 0) { // small (< 8 chars) constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10780 if (int_cnt2 == 1) { // One char |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10781 load_unsigned_short(result, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10782 movdl(vec, result); // move 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10783 } else if (int_cnt2 == 2) { // Two chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10784 movdl(vec, Address(str2, 0)); // move 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10785 } else if (int_cnt2 == 4) { // Four chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10786 movq(vec, Address(str2, 0)); // move 64 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10787 } else { // cnt2 = { 3, 5, 6, 7 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10788 // Array header size is 12 bytes in 32-bit VM |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10789 // + 6 bytes for 3 chars == 18 bytes, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10790 // enough space to load vec and shift. |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
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6792
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changeset
|
10791 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); |
|
2320
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|
10792 movdqu(vec, Address(str2, (int_cnt2*2)-16)); |
|
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|
10793 psrldq(vec, 16-(int_cnt2*2)); |
|
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|
10794 } |
|
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|
10795 } else { // not constant substring |
|
41d4973cf100
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changeset
|
10796 cmpl(cnt2, 8); |
|
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|
10797 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough |
|
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|
10798 |
|
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changeset
|
10799 // We can read beyond string if srt+16 does not cross page boundary |
|
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|
10800 // since heaps are aligned and mapped by pages. |
|
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|
10801 assert(os::vm_page_size() < (int)G, "default page should be small"); |
|
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|
10802 movl(result, str2); // We need only low 32 bits |
|
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|
10803 andl(result, (os::vm_page_size()-1)); |
|
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|
10804 cmpl(result, (os::vm_page_size()-16)); |
|
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|
10805 jccb(Assembler::belowEqual, CHECK_STR); |
|
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changeset
|
10806 |
|
41d4973cf100
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changeset
|
10807 // Move small strings to stack to allow load 16 bytes into vec. |
|
41d4973cf100
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|
10808 subptr(rsp, 16); |
|
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|
10809 int stk_offset = wordSize-2; |
|
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changeset
|
10810 push(cnt2); |
|
41d4973cf100
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changeset
|
10811 |
|
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changeset
|
10812 bind(COPY_SUBSTR); |
|
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|
10813 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); |
|
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|
10814 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
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|
10815 decrement(cnt2); |
|
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|
10816 jccb(Assembler::notZero, COPY_SUBSTR); |
|
41d4973cf100
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|
10817 |
|
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changeset
|
10818 pop(cnt2); |
|
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|
10819 movptr(str2, rsp); // New substring address |
|
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|
10820 } // non constant |
|
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changeset
|
10821 |
|
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changeset
|
10822 bind(CHECK_STR); |
|
41d4973cf100
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|
10823 cmpl(cnt1, 8); |
|
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|
10824 jccb(Assembler::aboveEqual, BIG_STRINGS); |
|
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|
10825 |
|
41d4973cf100
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changeset
|
10826 // Check cross page boundary. |
|
41d4973cf100
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|
10827 movl(result, str1); // We need only low 32 bits |
|
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|
10828 andl(result, (os::vm_page_size()-1)); |
|
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|
10829 cmpl(result, (os::vm_page_size()-16)); |
|
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|
10830 jccb(Assembler::belowEqual, BIG_STRINGS); |
|
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changeset
|
10831 |
|
41d4973cf100
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changeset
|
10832 subptr(rsp, 16); |
|
41d4973cf100
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changeset
|
10833 int stk_offset = -2; |
|
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|
10834 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
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changeset
|
10835 push(cnt2); |
|
41d4973cf100
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changeset
|
10836 stk_offset += wordSize; |
|
41d4973cf100
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changeset
|
10837 } |
|
41d4973cf100
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changeset
|
10838 movl(cnt2, cnt1); |
|
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changeset
|
10839 |
|
41d4973cf100
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changeset
|
10840 bind(COPY_STR); |
|
41d4973cf100
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changeset
|
10841 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); |
|
41d4973cf100
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|
10842 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
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changeset
|
10843 decrement(cnt2); |
|
41d4973cf100
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changeset
|
10844 jccb(Assembler::notZero, COPY_STR); |
|
41d4973cf100
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changeset
|
10845 |
|
41d4973cf100
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changeset
|
10846 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
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diff
changeset
|
10847 pop(cnt2); |
|
41d4973cf100
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diff
changeset
|
10848 } |
|
41d4973cf100
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changeset
|
10849 movptr(str1, rsp); // New string address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10850 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10851 bind(BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10852 // Load substring. |
|
41d4973cf100
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changeset
|
10853 if (int_cnt2 < 0) { // -1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10854 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
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changeset
|
10855 push(cnt2); // substr count |
|
41d4973cf100
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changeset
|
10856 push(str2); // substr addr |
|
41d4973cf100
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changeset
|
10857 push(str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10858 } else { |
|
41d4973cf100
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diff
changeset
|
10859 // Small (< 8 chars) constant substrings are loaded already. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10860 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10861 } |
|
41d4973cf100
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diff
changeset
|
10862 push(tmp); // original SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10863 |
|
41d4973cf100
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diff
changeset
|
10864 } // Finished loading |
|
41d4973cf100
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changeset
|
10865 |
|
41d4973cf100
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diff
changeset
|
10866 //======================================================== |
|
41d4973cf100
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changeset
|
10867 // Start search |
|
41d4973cf100
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diff
changeset
|
10868 // |
|
41d4973cf100
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diff
changeset
|
10869 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10870 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10871 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10872 if (int_cnt2 < 0) { // Only for non constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10873 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10874 |
|
41d4973cf100
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changeset
|
10875 // SP saved at sp+0 |
|
41d4973cf100
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changeset
|
10876 // String saved at sp+1*wordSize |
|
41d4973cf100
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changeset
|
10877 // Substr saved at sp+2*wordSize |
|
41d4973cf100
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changeset
|
10878 // Substr count saved at sp+3*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10879 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10880 // Reload substr for rescan, this code |
|
41d4973cf100
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changeset
|
10881 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10882 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10883 movptr(str2, Address(rsp, 2*wordSize)); |
|
41d4973cf100
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changeset
|
10884 movl(cnt2, Address(rsp, 3*wordSize)); |
|
41d4973cf100
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changeset
|
10885 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
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changeset
|
10886 // We came here after the beginning of the substring was |
|
41d4973cf100
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changeset
|
10887 // matched but the rest of it was not so we need to search |
|
41d4973cf100
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changeset
|
10888 // again. Start from the next element after the previous match. |
|
41d4973cf100
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changeset
|
10889 subptr(str1, result); // Restore counter |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10890 shrl(str1, 1); |
|
41d4973cf100
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changeset
|
10891 addl(cnt1, str1); |
|
41d4973cf100
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changeset
|
10892 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
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changeset
|
10893 cmpl(cnt1, cnt2); |
|
41d4973cf100
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changeset
|
10894 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
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changeset
|
10895 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10896 addptr(result, 2); |
|
41d4973cf100
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diff
changeset
|
10897 } // non constant |
|
41d4973cf100
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diff
changeset
|
10898 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10899 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
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changeset
|
10900 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
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changeset
|
10901 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
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changeset
|
10902 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
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changeset
|
10903 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
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changeset
|
10904 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10905 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10906 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10907 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
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diff
changeset
|
10908 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10909 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10910 bind(ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10911 cmpl(cnt1, 8); // Do not read beyond string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10912 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10913 // Back-up string to avoid reading beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10914 lea(result, Address(result, cnt1, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10915 movl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10916 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10917 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10918 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10919 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10920 // After pcmpestri tmp(rcx) contains matched element index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10921 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10922 // Make sure string is still long enough |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10923 subl(cnt1, tmp); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10924 cmpl(cnt1, cnt2); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10925 jccb(Assembler::greaterEqual, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10926 // Left less then substring. |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10927 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10928 bind(RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10929 movl(result, -1); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10930 jmpb(CLEANUP); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10931 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10932 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10933 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10934 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10935 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10936 if (int_cnt2 > 0) { // Constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10937 // Repeat search for small substring (< 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10938 // from new point without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10939 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10940 cmpl(tmp, 8-int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10941 jccb(Assembler::greater, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10942 // Fall through if matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10943 } else { // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10944 assert(int_cnt2 == -1, "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10945 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10946 addl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10947 // Found result if we matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10948 cmpl(tmp, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10949 jccb(Assembler::lessEqual, RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10950 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10951 // Repeat search for small substring (<= 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10952 // from new point 'str1' without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10953 cmpl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10954 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10955 jccb(Assembler::lessEqual, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10956 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10957 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10958 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10959 movptr(str1, result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10960 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10961 cmpl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10962 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10963 jccb(Assembler::equal, CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10964 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10965 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10966 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10967 // Need to reload strings pointers if not matched whole vector |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10968 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10969 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10970 bind(CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10971 subl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10972 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10973 addptr(str1, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10974 addptr(str2, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10975 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10976 cmpl(cnt2, 8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10977 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10978 // Back-up strings to avoid reading beyond substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10979 lea(str2, Address(str2, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10980 lea(str1, Address(str1, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10981 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10982 movl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10983 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10984 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10985 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10986 jmpb(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10987 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10988 bind(RET_FOUND_LONG); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10989 movptr(str1, Address(rsp, wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10990 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10991 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10992 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10993 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10994 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10995 shrl(result, 1); // index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10996 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10997 bind(CLEANUP); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10998 pop(rsp); // restore SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10999 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11000 } // string_indexof |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11001 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11002 // Compare strings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11003 void MacroAssembler::string_compare(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11004 Register cnt1, Register cnt2, Register result, |
| 2262 | 11005 XMMRegister vec1) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
11006 ShortBranchVerifier sbv(this); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11007 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11008 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11009 // Compute the minimum of the string lengths and the |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11010 // difference of the string lengths (stack). |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11011 // Do the conditional move stuff |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11012 movl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11013 subl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11014 push(cnt1); |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
11015 cmov32(Assembler::lessEqual, cnt2, result); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11016 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11017 // Is the minimum length zero? |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11018 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11019 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11020 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11021 // Load first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11022 load_unsigned_short(result, Address(str1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11023 load_unsigned_short(cnt1, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11024 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11025 // Compare first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11026 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11027 jcc(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11028 decrementl(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11029 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11030 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11031 { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
11032 // Check after comparing first character to see if strings are equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
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|
11033 Label LSkip2; |
|
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|
11034 // Check if the strings start at same location |
|
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|
11035 cmpptr(str1, str2); |
|
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|
11036 jccb(Assembler::notEqual, LSkip2); |
|
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|
11037 |
|
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|
11038 // Check if the length difference is zero (from stack) |
|
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|
11039 cmpl(Address(rsp, 0), 0x0); |
|
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|
11040 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
|
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|
11041 |
|
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|
11042 // Strings might not be equivalent |
|
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|
11043 bind(LSkip2); |
|
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|
11044 } |
|
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|
11045 |
| 2262 | 11046 Address::ScaleFactor scale = Address::times_2; |
| 11047 int stride = 8; | |
| 11048 | |
| 11049 // Advance to next element | |
| 11050 addptr(str1, 16/stride); | |
| 11051 addptr(str2, 16/stride); | |
|
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|
11052 |
|
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|
11053 if (UseSSE42Intrinsics) { |
| 2262 | 11054 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
| 11055 int pcmpmask = 0x19; | |
|
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|
11056 // Setup to compare 16-byte vectors |
| 2262 | 11057 movl(result, cnt2); |
| 11058 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count | |
|
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|
11059 jccb(Assembler::zero, COMPARE_TAIL); |
|
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|
11060 |
| 2262 | 11061 lea(str1, Address(str1, result, scale)); |
| 11062 lea(str2, Address(str2, result, scale)); | |
| 11063 negptr(result); | |
| 11064 | |
| 11065 // pcmpestri | |
| 11066 // inputs: | |
| 11067 // vec1- substring | |
| 11068 // rax - negative string length (elements count) | |
| 11069 // mem - scaned string | |
| 11070 // rdx - string length (elements count) | |
| 11071 // pcmpmask - cmp mode: 11000 (string compare with negated result) | |
| 11072 // + 00 (unsigned bytes) or + 01 (unsigned shorts) | |
| 11073 // outputs: | |
| 11074 // rcx - first mismatched element index | |
| 11075 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); | |
| 11076 | |
| 11077 bind(COMPARE_WIDE_VECTORS); | |
| 11078 movdqu(vec1, Address(str1, result, scale)); | |
| 11079 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 11080 // After pcmpestri cnt1(rcx) contains mismatched element index | |
| 11081 | |
| 11082 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 | |
| 11083 addptr(result, stride); | |
| 11084 subptr(cnt2, stride); | |
| 11085 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
| 11086 | |
| 11087 // compare wide vectors tail | |
| 11088 testl(result, result); | |
| 11089 jccb(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 11090 | |
| 11091 movl(cnt2, stride); | |
| 11092 movl(result, stride); | |
| 11093 negptr(result); | |
| 11094 movdqu(vec1, Address(str1, result, scale)); | |
| 11095 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 11096 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); | |
|
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|
11097 |
|
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|
11098 // Mismatched characters in the vectors |
|
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|
11099 bind(VECTOR_NOT_EQUAL); |
| 2262 | 11100 addptr(result, cnt1); |
| 11101 movptr(cnt2, result); | |
| 11102 load_unsigned_short(result, Address(str1, cnt2, scale)); | |
| 11103 load_unsigned_short(cnt1, Address(str2, cnt2, scale)); | |
| 11104 subl(result, cnt1); | |
| 11105 jmpb(POP_LABEL); | |
| 11106 | |
| 11107 bind(COMPARE_TAIL); // limit is zero | |
| 11108 movl(cnt2, result); | |
|
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|
11109 // Fallthru to tail compare |
|
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|
11110 } |
|
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|
11111 |
|
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|
11112 // Shift str2 and str1 to the end of the arrays, negate min |
| 2262 | 11113 lea(str1, Address(str1, cnt2, scale, 0)); |
| 11114 lea(str2, Address(str2, cnt2, scale, 0)); | |
|
986
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|
11115 negptr(cnt2); |
|
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|
11116 |
| 2262 | 11117 // Compare the rest of the elements |
|
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|
11118 bind(WHILE_HEAD_LABEL); |
| 2262 | 11119 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); |
| 11120 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); | |
|
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|
11121 subl(result, cnt1); |
|
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|
11122 jccb(Assembler::notZero, POP_LABEL); |
|
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|
11123 increment(cnt2); |
| 2262 | 11124 jccb(Assembler::notZero, WHILE_HEAD_LABEL); |
|
986
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|
11125 |
|
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|
11126 // Strings are equal up to min length. Return the length difference. |
|
62001a362ce9
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|
11127 bind(LENGTH_DIFF_LABEL); |
|
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|
11128 pop(result); |
|
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|
11129 jmpb(DONE_LABEL); |
|
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|
11130 |
|
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|
11131 // Discard the stored length difference |
|
62001a362ce9
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|
11132 bind(POP_LABEL); |
| 2262 | 11133 pop(cnt1); |
|
986
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|
11134 |
|
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|
11135 // That's it |
|
62001a362ce9
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|
11136 bind(DONE_LABEL); |
|
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|
11137 } |
|
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|
11138 |
|
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|
11139 // Compare char[] arrays aligned to 4 bytes or substrings. |
|
62001a362ce9
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|
11140 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
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|
11141 Register limit, Register result, Register chr, |
|
62001a362ce9
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|
11142 XMMRegister vec1, XMMRegister vec2) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
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|
11143 ShortBranchVerifier sbv(this); |
|
986
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|
11144 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
|
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|
11145 |
|
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|
11146 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
11147 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
62001a362ce9
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|
11148 |
|
62001a362ce9
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diff
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|
11149 // Check the input args |
|
62001a362ce9
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diff
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|
11150 cmpptr(ary1, ary2); |
|
62001a362ce9
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|
11151 jcc(Assembler::equal, TRUE_LABEL); |
|
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|
11152 |
|
62001a362ce9
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|
11153 if (is_array_equ) { |
|
62001a362ce9
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|
11154 // Need additional checks for arrays_equals. |
| 1016 | 11155 testptr(ary1, ary1); |
| 11156 jcc(Assembler::zero, FALSE_LABEL); | |
| 11157 testptr(ary2, ary2); | |
| 11158 jcc(Assembler::zero, FALSE_LABEL); | |
|
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|
11159 |
|
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|
11160 // Check the lengths |
|
62001a362ce9
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diff
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|
11161 movl(limit, Address(ary1, length_offset)); |
|
62001a362ce9
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|
11162 cmpl(limit, Address(ary2, length_offset)); |
|
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|
11163 jcc(Assembler::notEqual, FALSE_LABEL); |
|
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|
11164 } |
|
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|
11165 |
|
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diff
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|
11166 // count == 0 |
|
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diff
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|
11167 testl(limit, limit); |
|
62001a362ce9
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|
11168 jcc(Assembler::zero, TRUE_LABEL); |
|
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|
11169 |
|
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|
11170 if (is_array_equ) { |
|
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|
11171 // Load array address |
|
62001a362ce9
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|
11172 lea(ary1, Address(ary1, base_offset)); |
|
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|
11173 lea(ary2, Address(ary2, base_offset)); |
|
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|
11174 } |
|
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|
11175 |
|
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|
11176 shll(limit, 1); // byte count != 0 |
|
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|
11177 movl(result, limit); // copy |
|
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|
11178 |
|
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|
11179 if (UseSSE42Intrinsics) { |
|
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|
11180 // With SSE4.2, use double quad vector compare |
|
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|
11181 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
| 2262 | 11182 |
|
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|
11183 // Compare 16-byte vectors |
|
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|
11184 andl(result, 0x0000000e); // tail count (in bytes) |
|
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|
11185 andl(limit, 0xfffffff0); // vector count (in bytes) |
|
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|
11186 jccb(Assembler::zero, COMPARE_TAIL); |
|
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|
11187 |
|
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|
11188 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
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|
11189 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
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|
11190 negptr(limit); |
|
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|
11191 |
|
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|
11192 bind(COMPARE_WIDE_VECTORS); |
|
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|
11193 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
|
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|
11194 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
|
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|
11195 pxor(vec1, vec2); |
| 2262 | 11196 |
|
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|
11197 ptest(vec1, vec1); |
|
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|
11198 jccb(Assembler::notZero, FALSE_LABEL); |
|
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|
11199 addptr(limit, 16); |
|
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|
11200 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
|
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|
11201 |
| 2262 | 11202 testl(result, result); |
| 11203 jccb(Assembler::zero, TRUE_LABEL); | |
| 11204 | |
| 11205 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); | |
| 11206 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); | |
| 11207 pxor(vec1, vec2); | |
| 11208 | |
| 11209 ptest(vec1, vec1); | |
| 11210 jccb(Assembler::notZero, FALSE_LABEL); | |
| 11211 jmpb(TRUE_LABEL); | |
| 11212 | |
|
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|
11213 bind(COMPARE_TAIL); // limit is zero |
|
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|
11214 movl(limit, result); |
|
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|
11215 // Fallthru to tail compare |
|
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|
11216 } |
|
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|
11217 |
|
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|
11218 // Compare 4-byte vectors |
|
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|
11219 andl(limit, 0xfffffffc); // vector count (in bytes) |
|
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|
11220 jccb(Assembler::zero, COMPARE_CHAR); |
|
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|
11221 |
|
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|
11222 lea(ary1, Address(ary1, limit, Address::times_1)); |
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11223 lea(ary2, Address(ary2, limit, Address::times_1)); |
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11224 negptr(limit); |
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11225 |
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11226 bind(COMPARE_VECTORS); |
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11227 movl(chr, Address(ary1, limit, Address::times_1)); |
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11228 cmpl(chr, Address(ary2, limit, Address::times_1)); |
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11229 jccb(Assembler::notEqual, FALSE_LABEL); |
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11230 addptr(limit, 4); |
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11231 jcc(Assembler::notZero, COMPARE_VECTORS); |
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11232 |
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11233 // Compare trailing char (final 2 bytes), if any |
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11234 bind(COMPARE_CHAR); |
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11235 testl(result, 0x2); // tail char |
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11236 jccb(Assembler::zero, TRUE_LABEL); |
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11237 load_unsigned_short(chr, Address(ary1, 0)); |
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11238 load_unsigned_short(limit, Address(ary2, 0)); |
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11239 cmpl(chr, limit); |
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11240 jccb(Assembler::notEqual, FALSE_LABEL); |
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11241 |
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11242 bind(TRUE_LABEL); |
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11243 movl(result, 1); // return true |
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11244 jmpb(DONE); |
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11245 |
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11246 bind(FALSE_LABEL); |
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11247 xorl(result, result); // return false |
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11248 |
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11249 // That's it |
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11250 bind(DONE); |
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11251 } |
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11252 |
| 1763 | 11253 void MacroAssembler::generate_fill(BasicType t, bool aligned, |
| 11254 Register to, Register value, Register count, | |
| 11255 Register rtmp, XMMRegister xtmp) { | |
|
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11256 ShortBranchVerifier sbv(this); |
| 1763 | 11257 assert_different_registers(to, value, count, rtmp); |
| 11258 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
| 11259 Label L_fill_2_bytes, L_fill_4_bytes; | |
| 11260 | |
| 11261 int shift = -1; | |
| 11262 switch (t) { | |
| 11263 case T_BYTE: | |
| 11264 shift = 2; | |
| 11265 break; | |
| 11266 case T_SHORT: | |
| 11267 shift = 1; | |
| 11268 break; | |
| 11269 case T_INT: | |
| 11270 shift = 0; | |
| 11271 break; | |
| 11272 default: ShouldNotReachHere(); | |
| 11273 } | |
| 11274 | |
| 11275 if (t == T_BYTE) { | |
| 11276 andl(value, 0xff); | |
| 11277 movl(rtmp, value); | |
| 11278 shll(rtmp, 8); | |
| 11279 orl(value, rtmp); | |
| 11280 } | |
| 11281 if (t == T_SHORT) { | |
| 11282 andl(value, 0xffff); | |
| 11283 } | |
| 11284 if (t == T_BYTE || t == T_SHORT) { | |
| 11285 movl(rtmp, value); | |
| 11286 shll(rtmp, 16); | |
| 11287 orl(value, rtmp); | |
| 11288 } | |
| 11289 | |
| 11290 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
| 11291 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
| 11292 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
| 11293 // align source address at 4 bytes address boundary | |
| 11294 if (t == T_BYTE) { | |
| 11295 // One byte misalignment happens only for byte arrays | |
| 11296 testptr(to, 1); | |
| 11297 jccb(Assembler::zero, L_skip_align1); | |
| 11298 movb(Address(to, 0), value); | |
| 11299 increment(to); | |
| 11300 decrement(count); | |
| 11301 BIND(L_skip_align1); | |
| 11302 } | |
| 11303 // Two bytes misalignment happens only for byte and short (char) arrays | |
| 11304 testptr(to, 2); | |
| 11305 jccb(Assembler::zero, L_skip_align2); | |
| 11306 movw(Address(to, 0), value); | |
| 11307 addptr(to, 2); | |
| 11308 subl(count, 1<<(shift-1)); | |
| 11309 BIND(L_skip_align2); | |
| 11310 } | |
| 11311 if (UseSSE < 2) { | |
| 11312 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 11313 // Fill 32-byte chunks | |
| 11314 subl(count, 8 << shift); | |
| 11315 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 11316 align(16); | |
| 11317 | |
| 11318 BIND(L_fill_32_bytes_loop); | |
| 11319 | |
| 11320 for (int i = 0; i < 32; i += 4) { | |
| 11321 movl(Address(to, i), value); | |
| 11322 } | |
| 11323 | |
| 11324 addptr(to, 32); | |
| 11325 subl(count, 8 << shift); | |
| 11326 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 11327 BIND(L_check_fill_8_bytes); | |
| 11328 addl(count, 8 << shift); | |
| 11329 jccb(Assembler::zero, L_exit); | |
| 11330 jmpb(L_fill_8_bytes); | |
| 11331 | |
| 11332 // | |
| 11333 // length is too short, just fill qwords | |
| 11334 // | |
| 11335 BIND(L_fill_8_bytes_loop); | |
| 11336 movl(Address(to, 0), value); | |
| 11337 movl(Address(to, 4), value); | |
| 11338 addptr(to, 8); | |
| 11339 BIND(L_fill_8_bytes); | |
| 11340 subl(count, 1 << (shift + 1)); | |
| 11341 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 11342 // fall through to fill 4 bytes | |
| 11343 } else { | |
| 11344 Label L_fill_32_bytes; | |
| 11345 if (!UseUnalignedLoadStores) { | |
| 11346 // align to 8 bytes, we know we are 4 byte aligned to start | |
| 11347 testptr(to, 4); | |
| 11348 jccb(Assembler::zero, L_fill_32_bytes); | |
| 11349 movl(Address(to, 0), value); | |
| 11350 addptr(to, 4); | |
| 11351 subl(count, 1<<shift); | |
| 11352 } | |
| 11353 BIND(L_fill_32_bytes); | |
| 11354 { | |
| 11355 assert( UseSSE >= 2, "supported cpu only" ); | |
| 11356 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 11357 // Fill 32-byte chunks | |
| 11358 movdl(xtmp, value); | |
| 11359 pshufd(xtmp, xtmp, 0); | |
| 11360 | |
| 11361 subl(count, 8 << shift); | |
| 11362 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 11363 align(16); | |
| 11364 | |
| 11365 BIND(L_fill_32_bytes_loop); | |
| 11366 | |
| 11367 if (UseUnalignedLoadStores) { | |
| 11368 movdqu(Address(to, 0), xtmp); | |
| 11369 movdqu(Address(to, 16), xtmp); | |
| 11370 } else { | |
| 11371 movq(Address(to, 0), xtmp); | |
| 11372 movq(Address(to, 8), xtmp); | |
| 11373 movq(Address(to, 16), xtmp); | |
| 11374 movq(Address(to, 24), xtmp); | |
| 11375 } | |
| 11376 | |
| 11377 addptr(to, 32); | |
| 11378 subl(count, 8 << shift); | |
| 11379 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 11380 BIND(L_check_fill_8_bytes); | |
| 11381 addl(count, 8 << shift); | |
| 11382 jccb(Assembler::zero, L_exit); | |
| 11383 jmpb(L_fill_8_bytes); | |
| 11384 | |
| 11385 // | |
| 11386 // length is too short, just fill qwords | |
| 11387 // | |
| 11388 BIND(L_fill_8_bytes_loop); | |
| 11389 movq(Address(to, 0), xtmp); | |
| 11390 addptr(to, 8); | |
| 11391 BIND(L_fill_8_bytes); | |
| 11392 subl(count, 1 << (shift + 1)); | |
| 11393 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 11394 } | |
| 11395 } | |
| 11396 // fill trailing 4 bytes | |
| 11397 BIND(L_fill_4_bytes); | |
| 11398 testl(count, 1<<shift); | |
| 11399 jccb(Assembler::zero, L_fill_2_bytes); | |
| 11400 movl(Address(to, 0), value); | |
| 11401 if (t == T_BYTE || t == T_SHORT) { | |
| 11402 addptr(to, 4); | |
| 11403 BIND(L_fill_2_bytes); | |
| 11404 // fill trailing 2 bytes | |
| 11405 testl(count, 1<<(shift-1)); | |
| 11406 jccb(Assembler::zero, L_fill_byte); | |
| 11407 movw(Address(to, 0), value); | |
| 11408 if (t == T_BYTE) { | |
| 11409 addptr(to, 2); | |
| 11410 BIND(L_fill_byte); | |
| 11411 // fill trailing byte | |
| 11412 testl(count, 1); | |
| 11413 jccb(Assembler::zero, L_exit); | |
| 11414 movb(Address(to, 0), value); | |
| 11415 } else { | |
| 11416 BIND(L_fill_byte); | |
| 11417 } | |
| 11418 } else { | |
| 11419 BIND(L_fill_2_bytes); | |
| 11420 } | |
| 11421 BIND(L_exit); | |
| 11422 } | |
| 11423 #undef BIND | |
| 11424 #undef BLOCK_COMMENT | |
| 11425 | |
| 11426 | |
| 0 | 11427 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
| 11428 switch (cond) { | |
| 11429 // Note some conditions are synonyms for others | |
| 11430 case Assembler::zero: return Assembler::notZero; | |
| 11431 case Assembler::notZero: return Assembler::zero; | |
| 11432 case Assembler::less: return Assembler::greaterEqual; | |
| 11433 case Assembler::lessEqual: return Assembler::greater; | |
| 11434 case Assembler::greater: return Assembler::lessEqual; | |
| 11435 case Assembler::greaterEqual: return Assembler::less; | |
| 11436 case Assembler::below: return Assembler::aboveEqual; | |
| 11437 case Assembler::belowEqual: return Assembler::above; | |
| 11438 case Assembler::above: return Assembler::belowEqual; | |
| 11439 case Assembler::aboveEqual: return Assembler::below; | |
| 11440 case Assembler::overflow: return Assembler::noOverflow; | |
| 11441 case Assembler::noOverflow: return Assembler::overflow; | |
| 11442 case Assembler::negative: return Assembler::positive; | |
| 11443 case Assembler::positive: return Assembler::negative; | |
| 11444 case Assembler::parity: return Assembler::noParity; | |
| 11445 case Assembler::noParity: return Assembler::parity; | |
| 11446 } | |
| 11447 ShouldNotReachHere(); return Assembler::overflow; | |
| 11448 } | |
| 11449 | |
| 11450 SkipIfEqual::SkipIfEqual( | |
| 11451 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 11452 _masm = masm; | |
| 11453 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 11454 _masm->jcc(Assembler::equal, _label); | |
| 11455 } | |
| 11456 | |
| 11457 SkipIfEqual::~SkipIfEqual() { | |
| 11458 _masm->bind(_label); | |
| 11459 } |