Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 7790:2c6d04c5e60f
Enable invokedynamic and make bytecode known to Graal.
author | Andreas Woess <andreas.woess@jku.at> |
---|---|
date | Fri, 15 Feb 2013 00:43:40 +0100 |
parents | 3ac7d10a6572 |
children | 5fc51c1ecdeb |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
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27 #include "asm/assembler.inline.hpp" |
1972 | 28 #include "gc_interface/collectedHeap.inline.hpp" |
29 #include "interpreter/interpreter.hpp" | |
30 #include "memory/cardTableModRefBS.hpp" | |
31 #include "memory/resourceArea.hpp" | |
32 #include "prims/methodHandles.hpp" | |
33 #include "runtime/biasedLocking.hpp" | |
34 #include "runtime/interfaceSupport.hpp" | |
35 #include "runtime/objectMonitor.hpp" | |
36 #include "runtime/os.hpp" | |
37 #include "runtime/sharedRuntime.hpp" | |
38 #include "runtime/stubRoutines.hpp" | |
39 #ifndef SERIALGC | |
40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
42 #include "gc_implementation/g1/heapRegion.hpp" | |
43 #endif | |
0 | 44 |
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45 #ifdef PRODUCT |
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46 #define BLOCK_COMMENT(str) /* nothing */ |
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47 #define STOP(error) stop(error) |
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48 #else |
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49 #define BLOCK_COMMENT(str) block_comment(str) |
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50 #define STOP(error) block_comment(error); stop(error) |
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51 #endif |
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52 |
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53 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
0 | 54 // Implementation of AddressLiteral |
55 | |
56 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
57 _is_lval = false; | |
58 _target = target; | |
59 switch (rtype) { | |
60 case relocInfo::oop_type: | |
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61 case relocInfo::metadata_type: |
0 | 62 // Oops are a special case. Normally they would be their own section |
63 // but in cases like icBuffer they are literals in the code stream that | |
64 // we don't have a section for. We use none so that we get a literal address | |
65 // which is always patchable. | |
66 break; | |
67 case relocInfo::external_word_type: | |
68 _rspec = external_word_Relocation::spec(target); | |
69 break; | |
70 case relocInfo::internal_word_type: | |
71 _rspec = internal_word_Relocation::spec(target); | |
72 break; | |
73 case relocInfo::opt_virtual_call_type: | |
74 _rspec = opt_virtual_call_Relocation::spec(); | |
75 break; | |
76 case relocInfo::static_call_type: | |
77 _rspec = static_call_Relocation::spec(); | |
78 break; | |
79 case relocInfo::runtime_call_type: | |
80 _rspec = runtime_call_Relocation::spec(); | |
81 break; | |
82 case relocInfo::poll_type: | |
83 case relocInfo::poll_return_type: | |
84 _rspec = Relocation::spec_simple(rtype); | |
85 break; | |
86 case relocInfo::none: | |
87 break; | |
88 default: | |
89 ShouldNotReachHere(); | |
90 break; | |
91 } | |
92 } | |
93 | |
94 // Implementation of Address | |
95 | |
304 | 96 #ifdef _LP64 |
97 | |
0 | 98 Address Address::make_array(ArrayAddress adr) { |
99 // Not implementable on 64bit machines | |
100 // Should have been handled higher up the call chain. | |
101 ShouldNotReachHere(); | |
304 | 102 return Address(); |
103 } | |
104 | |
105 // exceedingly dangerous constructor | |
106 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
107 _base = noreg; | |
108 _index = noreg; | |
109 _scale = no_scale; | |
110 _disp = disp; | |
111 switch (rtype) { | |
112 case relocInfo::external_word_type: | |
113 _rspec = external_word_Relocation::spec(loc); | |
114 break; | |
115 case relocInfo::internal_word_type: | |
116 _rspec = internal_word_Relocation::spec(loc); | |
117 break; | |
118 case relocInfo::runtime_call_type: | |
119 // HMM | |
120 _rspec = runtime_call_Relocation::spec(); | |
121 break; | |
122 case relocInfo::poll_type: | |
123 case relocInfo::poll_return_type: | |
124 _rspec = Relocation::spec_simple(rtype); | |
125 break; | |
126 case relocInfo::none: | |
127 break; | |
128 default: | |
129 ShouldNotReachHere(); | |
130 } | |
131 } | |
132 #else // LP64 | |
133 | |
134 Address Address::make_array(ArrayAddress adr) { | |
0 | 135 AddressLiteral base = adr.base(); |
136 Address index = adr.index(); | |
137 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
138 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
139 array._rspec = base._rspec; | |
140 return array; | |
304 | 141 } |
0 | 142 |
143 // exceedingly dangerous constructor | |
144 Address::Address(address loc, RelocationHolder spec) { | |
145 _base = noreg; | |
146 _index = noreg; | |
147 _scale = no_scale; | |
148 _disp = (intptr_t) loc; | |
149 _rspec = spec; | |
150 } | |
304 | 151 |
0 | 152 #endif // _LP64 |
153 | |
304 | 154 |
155 | |
0 | 156 // Convert the raw encoding form into the form expected by the constructor for |
157 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
158 // that to noreg for the Address constructor. | |
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159 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
624 | 160 RelocationHolder rspec; |
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161 if (disp_reloc != relocInfo::none) { |
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162 rspec = Relocation::spec_simple(disp_reloc); |
624 | 163 } |
0 | 164 bool valid_index = index != rsp->encoding(); |
165 if (valid_index) { | |
166 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 167 madr._rspec = rspec; |
0 | 168 return madr; |
169 } else { | |
170 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 171 madr._rspec = rspec; |
0 | 172 return madr; |
173 } | |
174 } | |
175 | |
176 // Implementation of Assembler | |
177 | |
178 int AbstractAssembler::code_fill_byte() { | |
179 return (u_char)'\xF4'; // hlt | |
180 } | |
181 | |
182 // make this go away someday | |
183 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
184 if (rtype == relocInfo::none) | |
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185 emit_int32(data); |
0 | 186 else emit_data(data, Relocation::spec_simple(rtype), format); |
187 } | |
188 | |
189 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 190 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 191 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
192 if (rspec.type() != relocInfo::none) { | |
193 #ifdef ASSERT | |
194 check_relocation(rspec, format); | |
195 #endif | |
196 // Do not use AbstractAssembler::relocate, which is not intended for | |
197 // embedded words. Instead, relocate to the enclosing instruction. | |
198 | |
199 // hack. call32 is too wide for mask so use disp32 | |
200 if (format == call32_operand) | |
201 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
202 else | |
203 code_section()->relocate(inst_mark(), rspec, format); | |
204 } | |
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205 emit_int32(data); |
0 | 206 } |
207 | |
304 | 208 static int encode(Register r) { |
209 int enc = r->encoding(); | |
210 if (enc >= 8) { | |
211 enc -= 8; | |
212 } | |
213 return enc; | |
214 } | |
215 | |
216 static int encode(XMMRegister r) { | |
217 int enc = r->encoding(); | |
218 if (enc >= 8) { | |
219 enc -= 8; | |
220 } | |
221 return enc; | |
222 } | |
0 | 223 |
224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
225 assert(dst->has_byte_register(), "must have byte register"); | |
226 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
227 assert(isByte(imm8), "not a byte"); | |
228 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
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229 emit_int8(op1); |
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230 emit_int8(op2 | encode(dst)); |
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231 emit_int8(imm8); |
0 | 232 } |
233 | |
234 | |
304 | 235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 236 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
237 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
238 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
239 if (is8bit(imm32)) { | |
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240 emit_int8(op1 | 0x02); // set sign bit |
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241 emit_int8(op2 | encode(dst)); |
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242 emit_int8(imm32 & 0xFF); |
0 | 243 } else { |
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244 emit_int8(op1); |
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245 emit_int8(op2 | encode(dst)); |
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246 emit_int32(imm32); |
0 | 247 } |
248 } | |
249 | |
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250 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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252 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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253 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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254 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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255 emit_int8(op1); |
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256 emit_int8(op2 | encode(dst)); |
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257 emit_int32(imm32); |
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258 } |
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259 |
0 | 260 // immediate-to-memory forms |
304 | 261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 262 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
263 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
264 if (is8bit(imm32)) { | |
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265 emit_int8(op1 | 0x02); // set sign bit |
304 | 266 emit_operand(rm, adr, 1); |
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267 emit_int8(imm32 & 0xFF); |
0 | 268 } else { |
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269 emit_int8(op1); |
304 | 270 emit_operand(rm, adr, 4); |
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271 emit_int32(imm32); |
0 | 272 } |
273 } | |
274 | |
275 | |
276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
277 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
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278 emit_int8(op1); |
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279 emit_int8(op2 | encode(dst) << 3 | encode(src)); |
304 | 280 } |
281 | |
282 | |
283 void Assembler::emit_operand(Register reg, Register base, Register index, | |
284 Address::ScaleFactor scale, int disp, | |
285 RelocationHolder const& rspec, | |
286 int rip_relative_correction) { | |
0 | 287 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 288 |
289 // Encode the registers as needed in the fields they are used in | |
290 | |
291 int regenc = encode(reg) << 3; | |
292 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
293 int baseenc = base->is_valid() ? encode(base) : 0; | |
294 | |
0 | 295 if (base->is_valid()) { |
296 if (index->is_valid()) { | |
297 assert(scale != Address::no_scale, "inconsistent address"); | |
298 // [base + index*scale + disp] | |
304 | 299 if (disp == 0 && rtype == relocInfo::none && |
300 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 301 // [base + index*scale] |
302 // [00 reg 100][ss index base] | |
303 assert(index != rsp, "illegal addressing mode"); | |
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304 emit_int8(0x04 | regenc); |
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305 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 306 } else if (is8bit(disp) && rtype == relocInfo::none) { |
307 // [base + index*scale + imm8] | |
308 // [01 reg 100][ss index base] imm8 | |
309 assert(index != rsp, "illegal addressing mode"); | |
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310 emit_int8(0x44 | regenc); |
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311 emit_int8(scale << 6 | indexenc | baseenc); |
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312 emit_int8(disp & 0xFF); |
0 | 313 } else { |
304 | 314 // [base + index*scale + disp32] |
315 // [10 reg 100][ss index base] disp32 | |
0 | 316 assert(index != rsp, "illegal addressing mode"); |
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317 emit_int8(0x84 | regenc); |
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318 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 319 emit_data(disp, rspec, disp32_operand); |
320 } | |
304 | 321 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
322 // [rsp + disp] | |
0 | 323 if (disp == 0 && rtype == relocInfo::none) { |
304 | 324 // [rsp] |
0 | 325 // [00 reg 100][00 100 100] |
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326 emit_int8(0x04 | regenc); |
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327 emit_int8(0x24); |
0 | 328 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 329 // [rsp + imm8] |
330 // [01 reg 100][00 100 100] disp8 | |
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331 emit_int8(0x44 | regenc); |
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332 emit_int8(0x24); |
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333 emit_int8(disp & 0xFF); |
0 | 334 } else { |
304 | 335 // [rsp + imm32] |
336 // [10 reg 100][00 100 100] disp32 | |
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337 emit_int8(0x84 | regenc); |
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338 emit_int8(0x24); |
0 | 339 emit_data(disp, rspec, disp32_operand); |
340 } | |
341 } else { | |
342 // [base + disp] | |
304 | 343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
344 if (disp == 0 && rtype == relocInfo::none && | |
345 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 346 // [base] |
347 // [00 reg base] | |
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348 emit_int8(0x00 | regenc | baseenc); |
0 | 349 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 350 // [base + disp8] |
351 // [01 reg base] disp8 | |
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352 emit_int8(0x40 | regenc | baseenc); |
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353 emit_int8(disp & 0xFF); |
0 | 354 } else { |
304 | 355 // [base + disp32] |
356 // [10 reg base] disp32 | |
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357 emit_int8(0x80 | regenc | baseenc); |
0 | 358 emit_data(disp, rspec, disp32_operand); |
359 } | |
360 } | |
361 } else { | |
362 if (index->is_valid()) { | |
363 assert(scale != Address::no_scale, "inconsistent address"); | |
364 // [index*scale + disp] | |
304 | 365 // [00 reg 100][ss index 101] disp32 |
0 | 366 assert(index != rsp, "illegal addressing mode"); |
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367 emit_int8(0x04 | regenc); |
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368 emit_int8(scale << 6 | indexenc | 0x05); |
0 | 369 emit_data(disp, rspec, disp32_operand); |
304 | 370 } else if (rtype != relocInfo::none ) { |
371 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
372 // [00 000 101] disp32 | |
373 | |
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374 emit_int8(0x05 | regenc); |
304 | 375 // Note that the RIP-rel. correction applies to the generated |
376 // disp field, but _not_ to the target address in the rspec. | |
377 | |
378 // disp was created by converting the target address minus the pc | |
379 // at the start of the instruction. That needs more correction here. | |
380 // intptr_t disp = target - next_ip; | |
381 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
382 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
383 int64_t adjusted = disp; | |
384 // Do rip-rel adjustment for 64bit | |
385 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
386 assert(is_simm32(adjusted), | |
387 "must be 32bit offset (RIP relative address)"); | |
388 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
389 | |
0 | 390 } else { |
304 | 391 // 32bit never did this, did everything as the rip-rel/disp code above |
392 // [disp] ABSOLUTE | |
393 // [00 reg 100][00 100 101] disp32 | |
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394 emit_int8(0x04 | regenc); |
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395 emit_int8(0x25); |
0 | 396 emit_data(disp, rspec, disp32_operand); |
397 } | |
398 } | |
399 } | |
400 | |
304 | 401 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
402 Address::ScaleFactor scale, int disp, | |
403 RelocationHolder const& rspec) { | |
404 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
405 } | |
406 | |
0 | 407 // Secret local extension to Assembler::WhichOperand: |
408 #define end_pc_operand (_WhichOperand_limit) | |
409 | |
410 address Assembler::locate_operand(address inst, WhichOperand which) { | |
411 // Decode the given instruction, and return the address of | |
412 // an embedded 32-bit operand word. | |
413 | |
414 // If "which" is disp32_operand, selects the displacement portion | |
415 // of an effective address specifier. | |
304 | 416 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 417 // If "which" is call32_operand, selects the displacement of a call or jump. |
418 // Caller is responsible for ensuring that there is such an operand, | |
304 | 419 // and that it is 32/64 bits wide. |
0 | 420 |
421 // If "which" is end_pc_operand, find the end of the instruction. | |
422 | |
423 address ip = inst; | |
304 | 424 bool is_64bit = false; |
425 | |
426 debug_only(bool has_disp32 = false); | |
427 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
428 | |
429 again_after_prefix: | |
0 | 430 switch (0xFF & *ip++) { |
431 | |
432 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 433 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
434 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 435 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 436 #define REP16(x) REP8((x)+0): \ |
0 | 437 case REP8((x)+8) |
438 | |
439 case CS_segment: | |
440 case SS_segment: | |
441 case DS_segment: | |
442 case ES_segment: | |
443 case FS_segment: | |
444 case GS_segment: | |
304 | 445 // Seems dubious |
446 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 447 assert(ip == inst+1, "only one prefix allowed"); |
448 goto again_after_prefix; | |
449 | |
304 | 450 case 0x67: |
451 case REX: | |
452 case REX_B: | |
453 case REX_X: | |
454 case REX_XB: | |
455 case REX_R: | |
456 case REX_RB: | |
457 case REX_RX: | |
458 case REX_RXB: | |
459 NOT_LP64(assert(false, "64bit prefixes")); | |
460 goto again_after_prefix; | |
461 | |
462 case REX_W: | |
463 case REX_WB: | |
464 case REX_WX: | |
465 case REX_WXB: | |
466 case REX_WR: | |
467 case REX_WRB: | |
468 case REX_WRX: | |
469 case REX_WRXB: | |
470 NOT_LP64(assert(false, "64bit prefixes")); | |
471 is_64bit = true; | |
472 goto again_after_prefix; | |
473 | |
474 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 475 case 0x88: // movb a, r |
476 case 0x89: // movl a, r | |
477 case 0x8A: // movb r, a | |
478 case 0x8B: // movl r, a | |
479 case 0x8F: // popl a | |
304 | 480 debug_only(has_disp32 = true); |
0 | 481 break; |
482 | |
304 | 483 case 0x68: // pushq #32 |
484 if (which == end_pc_operand) { | |
485 return ip + 4; | |
486 } | |
487 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 488 return ip; // not produced by emit_operand |
489 | |
490 case 0x66: // movw ... (size prefix) | |
304 | 491 again_after_size_prefix2: |
0 | 492 switch (0xFF & *ip++) { |
304 | 493 case REX: |
494 case REX_B: | |
495 case REX_X: | |
496 case REX_XB: | |
497 case REX_R: | |
498 case REX_RB: | |
499 case REX_RX: | |
500 case REX_RXB: | |
501 case REX_W: | |
502 case REX_WB: | |
503 case REX_WX: | |
504 case REX_WXB: | |
505 case REX_WR: | |
506 case REX_WRB: | |
507 case REX_WRX: | |
508 case REX_WRXB: | |
509 NOT_LP64(assert(false, "64bit prefix found")); | |
510 goto again_after_size_prefix2; | |
0 | 511 case 0x8B: // movw r, a |
512 case 0x89: // movw a, r | |
304 | 513 debug_only(has_disp32 = true); |
0 | 514 break; |
515 case 0xC7: // movw a, #16 | |
304 | 516 debug_only(has_disp32 = true); |
0 | 517 tail_size = 2; // the imm16 |
518 break; | |
519 case 0x0F: // several SSE/SSE2 variants | |
520 ip--; // reparse the 0x0F | |
521 goto again_after_prefix; | |
522 default: | |
523 ShouldNotReachHere(); | |
524 } | |
525 break; | |
526 | |
304 | 527 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
528 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
529 // these asserts are somewhat nonsensical | |
530 #ifndef _LP64 | |
5984 | 531 assert(which == imm_operand || which == disp32_operand, |
532 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
304 | 533 #else |
534 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
5984 | 535 which == narrow_oop_operand && !is_64bit, |
536 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
304 | 537 #endif // _LP64 |
0 | 538 return ip; |
539 | |
540 case 0x69: // imul r, a, #32 | |
541 case 0xC7: // movl a, #32(oop?) | |
542 tail_size = 4; | |
304 | 543 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 544 break; |
545 | |
546 case 0x0F: // movx..., etc. | |
547 switch (0xFF & *ip++) { | |
4759 | 548 case 0x3A: // pcmpestri |
549 tail_size = 1; | |
550 case 0x38: // ptest, pmovzxbw | |
551 ip++; // skip opcode | |
552 debug_only(has_disp32 = true); // has both kinds of operands! | |
553 break; | |
554 | |
555 case 0x70: // pshufd r, r/a, #8 | |
556 debug_only(has_disp32 = true); // has both kinds of operands! | |
557 case 0x73: // psrldq r, #8 | |
558 tail_size = 1; | |
559 break; | |
560 | |
0 | 561 case 0x12: // movlps |
562 case 0x28: // movaps | |
563 case 0x2E: // ucomiss | |
564 case 0x2F: // comiss | |
565 case 0x54: // andps | |
566 case 0x55: // andnps | |
567 case 0x56: // orps | |
568 case 0x57: // xorps | |
569 case 0x6E: // movd | |
570 case 0x7E: // movd | |
4759 | 571 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
304 | 572 debug_only(has_disp32 = true); |
0 | 573 break; |
574 | |
575 case 0xAD: // shrd r, a, %cl | |
576 case 0xAF: // imul r, a | |
304 | 577 case 0xBE: // movsbl r, a (movsxb) |
578 case 0xBF: // movswl r, a (movsxw) | |
579 case 0xB6: // movzbl r, a (movzxb) | |
580 case 0xB7: // movzwl r, a (movzxw) | |
0 | 581 case REP16(0x40): // cmovl cc, r, a |
582 case 0xB0: // cmpxchgb | |
583 case 0xB1: // cmpxchg | |
584 case 0xC1: // xaddl | |
585 case 0xC7: // cmpxchg8 | |
586 case REP16(0x90): // setcc a | |
304 | 587 debug_only(has_disp32 = true); |
0 | 588 // fall out of the switch to decode the address |
589 break; | |
304 | 590 |
4759 | 591 case 0xC4: // pinsrw r, a, #8 |
592 debug_only(has_disp32 = true); | |
593 case 0xC5: // pextrw r, r, #8 | |
594 tail_size = 1; // the imm8 | |
595 break; | |
596 | |
0 | 597 case 0xAC: // shrd r, a, #8 |
304 | 598 debug_only(has_disp32 = true); |
0 | 599 tail_size = 1; // the imm8 |
600 break; | |
304 | 601 |
0 | 602 case REP16(0x80): // jcc rdisp32 |
603 if (which == end_pc_operand) return ip + 4; | |
304 | 604 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 605 return ip; |
606 default: | |
607 ShouldNotReachHere(); | |
608 } | |
609 break; | |
610 | |
611 case 0x81: // addl a, #32; addl r, #32 | |
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 613 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 614 tail_size = 4; |
304 | 615 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 616 break; |
617 | |
618 case 0x83: // addl a, #8; addl r, #8 | |
619 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 620 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 621 tail_size = 1; |
622 break; | |
623 | |
624 case 0x9B: | |
625 switch (0xFF & *ip++) { | |
626 case 0xD9: // fnstcw a | |
304 | 627 debug_only(has_disp32 = true); |
0 | 628 break; |
629 default: | |
630 ShouldNotReachHere(); | |
631 } | |
632 break; | |
633 | |
634 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
635 case REP4(0x10): // adc... | |
636 case REP4(0x20): // and... | |
637 case REP4(0x30): // xor... | |
638 case REP4(0x08): // or... | |
639 case REP4(0x18): // sbb... | |
640 case REP4(0x28): // sub... | |
304 | 641 case 0xF7: // mull a |
642 case 0x8D: // lea r, a | |
643 case 0x87: // xchg r, a | |
0 | 644 case REP4(0x38): // cmp... |
304 | 645 case 0x85: // test r, a |
646 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 647 break; |
648 | |
649 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
650 case 0xC6: // movb a, #8 | |
651 case 0x80: // cmpb a, #8 | |
652 case 0x6B: // imul r, a, #8 | |
304 | 653 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 654 tail_size = 1; // the imm8 |
655 break; | |
656 | |
4759 | 657 case 0xC4: // VEX_3bytes |
658 case 0xC5: // VEX_2bytes | |
659 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
660 assert(ip == inst+1, "no prefixes allowed"); | |
661 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
662 // but they have prefix 0x0F and processed when 0x0F processed above. | |
663 // | |
664 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
665 // instructions (these instructions are not supported in 64-bit mode). | |
666 // To distinguish them bits [7:6] are set in the VEX second byte since | |
667 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
668 // those VEX bits REX and vvvv bits are inverted. | |
669 // | |
670 // Fortunately C2 doesn't generate these instructions so we don't need | |
671 // to check for them in product version. | |
672 | |
673 // Check second byte | |
674 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
675 | |
676 // First byte | |
677 if ((0xFF & *inst) == VEX_3bytes) { | |
678 ip++; // third byte | |
679 is_64bit = ((VEX_W & *ip) == VEX_W); | |
680 } | |
681 ip++; // opcode | |
682 // To find the end of instruction (which == end_pc_operand). | |
683 switch (0xFF & *ip) { | |
684 case 0x61: // pcmpestri r, r/a, #8 | |
685 case 0x70: // pshufd r, r/a, #8 | |
686 case 0x73: // psrldq r, #8 | |
687 tail_size = 1; // the imm8 | |
688 break; | |
689 default: | |
690 break; | |
691 } | |
692 ip++; // skip opcode | |
693 debug_only(has_disp32 = true); // has both kinds of operands! | |
694 break; | |
0 | 695 |
696 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
697 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
698 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
699 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
700 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
701 case 0xDF: // fild_d a; fistp_d a | |
702 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
703 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
704 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 705 debug_only(has_disp32 = true); |
0 | 706 break; |
707 | |
4759 | 708 case 0xE8: // call rdisp32 |
709 case 0xE9: // jmp rdisp32 | |
710 if (which == end_pc_operand) return ip + 4; | |
711 assert(which == call32_operand, "call has no disp32 or imm"); | |
712 return ip; | |
713 | |
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714 case 0xF0: // Lock |
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715 assert(os::is_MP(), "only on MP"); |
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716 goto again_after_prefix; |
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717 |
0 | 718 case 0xF3: // For SSE |
719 case 0xF2: // For SSE2 | |
304 | 720 switch (0xFF & *ip++) { |
721 case REX: | |
722 case REX_B: | |
723 case REX_X: | |
724 case REX_XB: | |
725 case REX_R: | |
726 case REX_RB: | |
727 case REX_RX: | |
728 case REX_RXB: | |
729 case REX_W: | |
730 case REX_WB: | |
731 case REX_WX: | |
732 case REX_WXB: | |
733 case REX_WR: | |
734 case REX_WRB: | |
735 case REX_WRX: | |
736 case REX_WRXB: | |
737 NOT_LP64(assert(false, "found 64bit prefix")); | |
738 ip++; | |
739 default: | |
740 ip++; | |
741 } | |
742 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 743 break; |
744 | |
745 default: | |
746 ShouldNotReachHere(); | |
747 | |
304 | 748 #undef REP8 |
749 #undef REP16 | |
0 | 750 } |
751 | |
752 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 753 #ifdef _LP64 |
754 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
755 #else | |
756 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
757 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
758 #endif // LP64 | |
759 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 760 |
761 // parse the output of emit_operand | |
762 int op2 = 0xFF & *ip++; | |
763 int base = op2 & 0x07; | |
764 int op3 = -1; | |
765 const int b100 = 4; | |
766 const int b101 = 5; | |
767 if (base == b100 && (op2 >> 6) != 3) { | |
768 op3 = 0xFF & *ip++; | |
769 base = op3 & 0x07; // refetch the base | |
770 } | |
771 // now ip points at the disp (if any) | |
772 | |
773 switch (op2 >> 6) { | |
774 case 0: | |
775 // [00 reg 100][ss index base] | |
304 | 776 // [00 reg 100][00 100 esp] |
0 | 777 // [00 reg base] |
778 // [00 reg 100][ss index 101][disp32] | |
779 // [00 reg 101] [disp32] | |
780 | |
781 if (base == b101) { | |
782 if (which == disp32_operand) | |
783 return ip; // caller wants the disp32 | |
784 ip += 4; // skip the disp32 | |
785 } | |
786 break; | |
787 | |
788 case 1: | |
789 // [01 reg 100][ss index base][disp8] | |
304 | 790 // [01 reg 100][00 100 esp][disp8] |
0 | 791 // [01 reg base] [disp8] |
792 ip += 1; // skip the disp8 | |
793 break; | |
794 | |
795 case 2: | |
796 // [10 reg 100][ss index base][disp32] | |
304 | 797 // [10 reg 100][00 100 esp][disp32] |
0 | 798 // [10 reg base] [disp32] |
799 if (which == disp32_operand) | |
800 return ip; // caller wants the disp32 | |
801 ip += 4; // skip the disp32 | |
802 break; | |
803 | |
804 case 3: | |
805 // [11 reg base] (not a memory addressing mode) | |
806 break; | |
807 } | |
808 | |
809 if (which == end_pc_operand) { | |
810 return ip + tail_size; | |
811 } | |
812 | |
304 | 813 #ifdef _LP64 |
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814 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 815 #else |
816 assert(which == imm_operand, "instruction has only an imm field"); | |
817 #endif // LP64 | |
0 | 818 return ip; |
819 } | |
820 | |
821 address Assembler::locate_next_instruction(address inst) { | |
822 // Secretly share code with locate_operand: | |
823 return locate_operand(inst, end_pc_operand); | |
824 } | |
825 | |
826 | |
827 #ifdef ASSERT | |
828 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
829 address inst = inst_mark(); | |
830 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
831 address opnd; | |
832 | |
833 Relocation* r = rspec.reloc(); | |
834 if (r->type() == relocInfo::none) { | |
835 return; | |
836 } else if (r->is_call() || format == call32_operand) { | |
837 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
838 opnd = locate_operand(inst, call32_operand); | |
839 } else if (r->is_data()) { | |
304 | 840 assert(format == imm_operand || format == disp32_operand |
841 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 842 opnd = locate_operand(inst, (WhichOperand)format); |
843 } else { | |
304 | 844 assert(format == imm_operand, "cannot specify a format"); |
0 | 845 return; |
846 } | |
847 assert(opnd == pc(), "must put operand where relocs can find it"); | |
848 } | |
304 | 849 #endif // ASSERT |
850 | |
851 void Assembler::emit_operand32(Register reg, Address adr) { | |
852 assert(reg->encoding() < 8, "no extended registers"); | |
853 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
855 adr._rspec); | |
856 } | |
857 | |
858 void Assembler::emit_operand(Register reg, Address adr, | |
859 int rip_relative_correction) { | |
860 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
861 adr._rspec, | |
862 rip_relative_correction); | |
863 } | |
864 | |
865 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
866 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
867 adr._rspec); | |
868 } | |
869 | |
870 // MMX operations | |
871 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
872 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
873 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
874 } | |
875 | |
876 // work around gcc (3.2.1-7a) bug | |
877 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
878 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
879 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 880 } |
881 | |
882 | |
883 void Assembler::emit_farith(int b1, int b2, int i) { | |
884 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
885 assert(0 <= i && i < 8, "illegal stack offset"); | |
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886 emit_int8(b1); |
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887 emit_int8(b2 + i); |
0 | 888 } |
889 | |
890 | |
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891 // Now the Assembler instructions (identical for 32/64 bits) |
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892 |
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893 void Assembler::adcl(Address dst, int32_t imm32) { |
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894 InstructionMark im(this); |
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895 prefix(dst); |
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896 emit_arith_operand(0x81, rdx, dst, imm32); |
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897 } |
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898 |
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899 void Assembler::adcl(Address dst, Register src) { |
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900 InstructionMark im(this); |
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901 prefix(dst, src); |
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902 emit_int8(0x11); |
2100
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903 emit_operand(src, dst); |
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904 } |
304 | 905 |
906 void Assembler::adcl(Register dst, int32_t imm32) { | |
907 prefix(dst); | |
0 | 908 emit_arith(0x81, 0xD0, dst, imm32); |
909 } | |
910 | |
911 void Assembler::adcl(Register dst, Address src) { | |
912 InstructionMark im(this); | |
304 | 913 prefix(src, dst); |
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914 emit_int8(0x13); |
0 | 915 emit_operand(dst, src); |
916 } | |
917 | |
918 void Assembler::adcl(Register dst, Register src) { | |
304 | 919 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 920 emit_arith(0x13, 0xC0, dst, src); |
921 } | |
922 | |
304 | 923 void Assembler::addl(Address dst, int32_t imm32) { |
924 InstructionMark im(this); | |
925 prefix(dst); | |
926 emit_arith_operand(0x81, rax, dst, imm32); | |
927 } | |
0 | 928 |
929 void Assembler::addl(Address dst, Register src) { | |
930 InstructionMark im(this); | |
304 | 931 prefix(dst, src); |
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932 emit_int8(0x01); |
0 | 933 emit_operand(src, dst); |
934 } | |
935 | |
304 | 936 void Assembler::addl(Register dst, int32_t imm32) { |
937 prefix(dst); | |
0 | 938 emit_arith(0x81, 0xC0, dst, imm32); |
939 } | |
940 | |
941 void Assembler::addl(Register dst, Address src) { | |
942 InstructionMark im(this); | |
304 | 943 prefix(src, dst); |
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944 emit_int8(0x03); |
0 | 945 emit_operand(dst, src); |
946 } | |
947 | |
948 void Assembler::addl(Register dst, Register src) { | |
304 | 949 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 950 emit_arith(0x03, 0xC0, dst, src); |
951 } | |
952 | |
953 void Assembler::addr_nop_4() { | |
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954 assert(UseAddressNop, "no CPU support"); |
0 | 955 // 4 bytes: NOP DWORD PTR [EAX+0] |
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956 emit_int8(0x0F); |
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957 emit_int8(0x1F); |
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958 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
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959 emit_int8(0); // 8-bits offset (1 byte) |
0 | 960 } |
961 | |
962 void Assembler::addr_nop_5() { | |
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963 assert(UseAddressNop, "no CPU support"); |
0 | 964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
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965 emit_int8(0x0F); |
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966 emit_int8(0x1F); |
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967 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
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968 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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969 emit_int8(0); // 8-bits offset (1 byte) |
0 | 970 } |
971 | |
972 void Assembler::addr_nop_7() { | |
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973 assert(UseAddressNop, "no CPU support"); |
0 | 974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
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975 emit_int8(0x0F); |
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976 emit_int8(0x1F); |
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977 emit_int8((unsigned char)0x80); |
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978 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
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979 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 980 } |
981 | |
982 void Assembler::addr_nop_8() { | |
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983 assert(UseAddressNop, "no CPU support"); |
0 | 984 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
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985 emit_int8(0x0F); |
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986 emit_int8(0x1F); |
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987 emit_int8((unsigned char)0x84); |
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988 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
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989 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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990 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 991 } |
992 | |
304 | 993 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
994 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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995 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 996 } |
997 | |
998 void Assembler::addsd(XMMRegister dst, Address src) { | |
999 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1000 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 1001 } |
1002 | |
1003 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
1004 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1005 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1006 } |
1007 | |
1008 void Assembler::addss(XMMRegister dst, Address src) { | |
1009 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1010 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1011 } |
1012 | |
6894 | 1013 void Assembler::aesdec(XMMRegister dst, Address src) { |
1014 assert(VM_Version::supports_aes(), ""); | |
1015 InstructionMark im(this); | |
1016 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1017 emit_int8((unsigned char)0xDE); |
6894 | 1018 emit_operand(dst, src); |
1019 } | |
1020 | |
1021 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |
1022 assert(VM_Version::supports_aes(), ""); | |
1023 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1024 emit_int8((unsigned char)0xDE); |
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1025 emit_int8(0xC0 | encode); |
6894 | 1026 } |
1027 | |
1028 void Assembler::aesdeclast(XMMRegister dst, Address src) { | |
1029 assert(VM_Version::supports_aes(), ""); | |
1030 InstructionMark im(this); | |
1031 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1032 emit_int8((unsigned char)0xDF); |
6894 | 1033 emit_operand(dst, src); |
1034 } | |
1035 | |
1036 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |
1037 assert(VM_Version::supports_aes(), ""); | |
1038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1039 emit_int8((unsigned char)0xDF); |
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1040 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1041 } |
1042 | |
1043 void Assembler::aesenc(XMMRegister dst, Address src) { | |
1044 assert(VM_Version::supports_aes(), ""); | |
1045 InstructionMark im(this); | |
1046 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1047 emit_int8((unsigned char)0xDC); |
6894 | 1048 emit_operand(dst, src); |
1049 } | |
1050 | |
1051 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |
1052 assert(VM_Version::supports_aes(), ""); | |
1053 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1054 emit_int8((unsigned char)0xDC); |
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1055 emit_int8(0xC0 | encode); |
6894 | 1056 } |
1057 | |
1058 void Assembler::aesenclast(XMMRegister dst, Address src) { | |
1059 assert(VM_Version::supports_aes(), ""); | |
1060 InstructionMark im(this); | |
1061 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1062 emit_int8((unsigned char)0xDD); |
6894 | 1063 emit_operand(dst, src); |
1064 } | |
1065 | |
1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |
1067 assert(VM_Version::supports_aes(), ""); | |
1068 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1069 emit_int8((unsigned char)0xDD); |
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1070 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1071 } |
1072 | |
1073 | |
4759 | 1074 void Assembler::andl(Address dst, int32_t imm32) { |
1075 InstructionMark im(this); | |
1076 prefix(dst); | |
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1077 emit_int8((unsigned char)0x81); |
4759 | 1078 emit_operand(rsp, dst, 4); |
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1079 emit_int32(imm32); |
4759 | 1080 } |
1081 | |
304 | 1082 void Assembler::andl(Register dst, int32_t imm32) { |
1083 prefix(dst); | |
1084 emit_arith(0x81, 0xE0, dst, imm32); | |
1085 } | |
1086 | |
1087 void Assembler::andl(Register dst, Address src) { | |
1088 InstructionMark im(this); | |
1089 prefix(src, dst); | |
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1090 emit_int8(0x23); |
304 | 1091 emit_operand(dst, src); |
1092 } | |
1093 | |
1094 void Assembler::andl(Register dst, Register src) { | |
1095 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1096 emit_arith(0x23, 0xC0, dst, src); | |
1097 } | |
1098 | |
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1099 void Assembler::bsfl(Register dst, Register src) { |
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1100 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1101 emit_int8(0x0F); |
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1102 emit_int8((unsigned char)0xBC); |
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1103 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1104 } |
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1105 |
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1106 void Assembler::bsrl(Register dst, Register src) { |
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1107 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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1108 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1109 emit_int8(0x0F); |
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1110 emit_int8((unsigned char)0xBD); |
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1111 emit_int8((unsigned char)(0xC0 | encode)); |
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1112 } |
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1113 |
304 | 1114 void Assembler::bswapl(Register reg) { // bswap |
1115 int encode = prefix_and_encode(reg->encoding()); | |
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1116 emit_int8(0x0F); |
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1117 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 1118 } |
1119 | |
1120 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
1121 // suspect disp32 is always good | |
1122 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
1123 | |
1124 if (L.is_bound()) { | |
1125 const int long_size = 5; | |
1126 int offs = (int)( target(L) - pc() ); | |
1127 assert(offs <= 0, "assembler error"); | |
1128 InstructionMark im(this); | |
1129 // 1110 1000 #32-bit disp | |
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1130 emit_int8((unsigned char)0xE8); |
304 | 1131 emit_data(offs - long_size, rtype, operand); |
1132 } else { | |
1133 InstructionMark im(this); | |
1134 // 1110 1000 #32-bit disp | |
1135 L.add_patch_at(code(), locator()); | |
1136 | |
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1137 emit_int8((unsigned char)0xE8); |
304 | 1138 emit_data(int(0), rtype, operand); |
1139 } | |
1140 } | |
1141 | |
1142 void Assembler::call(Register dst) { | |
4759 | 1143 int encode = prefix_and_encode(dst->encoding()); |
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1144 emit_int8((unsigned char)0xFF); |
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1145 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 1146 } |
1147 | |
1148 | |
1149 void Assembler::call(Address adr) { | |
1150 InstructionMark im(this); | |
1151 prefix(adr); | |
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1152 emit_int8((unsigned char)0xFF); |
304 | 1153 emit_operand(rdx, adr); |
1154 } | |
1155 | |
1156 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1157 assert(entry != NULL, "call most probably wrong"); | |
1158 InstructionMark im(this); | |
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1159 emit_int8((unsigned char)0xE8); |
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1160 intptr_t disp = entry - (pc() + sizeof(int32_t)); |
304 | 1161 assert(is_simm32(disp), "must be 32bit offset (call2)"); |
1162 // Technically, should use call32_operand, but this format is | |
1163 // implied by the fact that we're emitting a call instruction. | |
1164 | |
1165 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1166 emit_data((int) disp, rspec, operand); | |
1167 } | |
1168 | |
1169 void Assembler::cdql() { | |
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1170 emit_int8((unsigned char)0x99); |
304 | 1171 } |
1172 | |
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1173 void Assembler::cld() { |
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1174 emit_int8((unsigned char)0xFC); |
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1175 } |
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1176 |
304 | 1177 void Assembler::cmovl(Condition cc, Register dst, Register src) { |
1178 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1179 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1180 emit_int8(0x0F); |
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1181 emit_int8(0x40 | cc); |
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1182 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1183 } |
1184 | |
1185 | |
1186 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1187 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1188 prefix(src, dst); | |
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1189 emit_int8(0x0F); |
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1190 emit_int8(0x40 | cc); |
304 | 1191 emit_operand(dst, src); |
1192 } | |
1193 | |
1194 void Assembler::cmpb(Address dst, int imm8) { | |
1195 InstructionMark im(this); | |
1196 prefix(dst); | |
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1197 emit_int8((unsigned char)0x80); |
304 | 1198 emit_operand(rdi, dst, 1); |
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1199 emit_int8(imm8); |
304 | 1200 } |
1201 | |
1202 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1203 InstructionMark im(this); | |
1204 prefix(dst); | |
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1205 emit_int8((unsigned char)0x81); |
304 | 1206 emit_operand(rdi, dst, 4); |
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1207 emit_int32(imm32); |
304 | 1208 } |
1209 | |
1210 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1211 prefix(dst); | |
1212 emit_arith(0x81, 0xF8, dst, imm32); | |
1213 } | |
1214 | |
1215 void Assembler::cmpl(Register dst, Register src) { | |
1216 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1217 emit_arith(0x3B, 0xC0, dst, src); | |
1218 } | |
1219 | |
1220 | |
1221 void Assembler::cmpl(Register dst, Address src) { | |
1222 InstructionMark im(this); | |
1223 prefix(src, dst); | |
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1224 emit_int8((unsigned char)0x3B); |
304 | 1225 emit_operand(dst, src); |
1226 } | |
1227 | |
1228 void Assembler::cmpw(Address dst, int imm16) { | |
1229 InstructionMark im(this); | |
1230 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
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1231 emit_int8(0x66); |
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1232 emit_int8((unsigned char)0x81); |
304 | 1233 emit_operand(rdi, dst, 2); |
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1234 emit_int16(imm16); |
304 | 1235 } |
1236 | |
1237 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1238 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1239 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1240 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
6834 | 1241 InstructionMark im(this); |
1242 prefix(adr, reg); | |
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1243 emit_int8(0x0F); |
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1244 emit_int8((unsigned char)0xB1); |
6834 | 1245 emit_operand(reg, adr); |
304 | 1246 } |
1247 | |
1248 void Assembler::comisd(XMMRegister dst, Address src) { | |
1249 // NOTE: dbx seems to decode this as comiss even though the | |
1250 // 0x66 is there. Strangly ucomisd comes out correct | |
1251 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1252 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
4759 | 1253 } |
1254 | |
1255 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
1256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1257 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
304 | 1258 } |
1259 | |
1260 void Assembler::comiss(XMMRegister dst, Address src) { | |
1261 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1262 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
304 | 1263 } |
1264 | |
4759 | 1265 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
1266 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1267 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
4759 | 1268 } |
1269 | |
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1270 void Assembler::cpuid() { |
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1271 emit_int8(0x0F); |
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1272 emit_int8((unsigned char)0xA2); |
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1273 } |
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1274 |
304 | 1275 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1277 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
304 | 1278 } |
1279 | |
1280 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1281 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1282 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
304 | 1283 } |
1284 | |
1285 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1286 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1287 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
304 | 1288 } |
1289 | |
4759 | 1290 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
1291 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1292 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
4759 | 1293 } |
1294 | |
304 | 1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1296 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
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1298 emit_int8(0x2A); |
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1299 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1300 } |
1301 | |
4759 | 1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
1303 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1304 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
4759 | 1305 } |
1306 | |
304 | 1307 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1308 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
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1310 emit_int8(0x2A); |
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1311 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1312 } |
1313 | |
4759 | 1314 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
1315 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1316 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
4759 | 1317 } |
1318 | |
304 | 1319 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1320 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1321 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
304 | 1322 } |
1323 | |
4759 | 1324 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
1325 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1326 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
4759 | 1327 } |
1328 | |
1329 | |
304 | 1330 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1331 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1332 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
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1333 emit_int8(0x2C); |
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1334 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1335 } |
1336 | |
1337 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1338 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1339 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
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1340 emit_int8(0x2C); |
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1341 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1342 } |
1343 | |
1344 void Assembler::decl(Address dst) { | |
1345 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1346 InstructionMark im(this); | |
1347 prefix(dst); | |
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1348 emit_int8((unsigned char)0xFF); |
304 | 1349 emit_operand(rcx, dst); |
1350 } | |
1351 | |
1352 void Assembler::divsd(XMMRegister dst, Address src) { | |
1353 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1354 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1355 } |
1356 | |
1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1359 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1360 } |
1361 | |
1362 void Assembler::divss(XMMRegister dst, Address src) { | |
1363 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1364 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1365 } |
1366 | |
1367 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1368 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1369 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1370 } |
1371 | |
1372 void Assembler::emms() { | |
1373 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
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1374 emit_int8(0x0F); |
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1375 emit_int8(0x77); |
304 | 1376 } |
1377 | |
1378 void Assembler::hlt() { | |
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1379 emit_int8((unsigned char)0xF4); |
304 | 1380 } |
1381 | |
1382 void Assembler::idivl(Register src) { | |
1383 int encode = prefix_and_encode(src->encoding()); | |
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1384 emit_int8((unsigned char)0xF7); |
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1385 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 1386 } |
1387 | |
1920 | 1388 void Assembler::divl(Register src) { // Unsigned |
1389 int encode = prefix_and_encode(src->encoding()); | |
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1390 emit_int8((unsigned char)0xF7); |
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1391 emit_int8((unsigned char)(0xF0 | encode)); |
1920 | 1392 } |
1393 | |
304 | 1394 void Assembler::imull(Register dst, Register src) { |
1395 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1396 emit_int8(0x0F); |
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1397 emit_int8((unsigned char)0xAF); |
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1398 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1399 } |
1400 | |
1401 | |
1402 void Assembler::imull(Register dst, Register src, int value) { | |
1403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1404 if (is8bit(value)) { | |
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1405 emit_int8(0x6B); |
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1406 emit_int8((unsigned char)(0xC0 | encode)); |
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1407 emit_int8(value & 0xFF); |
304 | 1408 } else { |
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1409 emit_int8(0x69); |
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1410 emit_int8((unsigned char)(0xC0 | encode)); |
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1411 emit_int32(value); |
304 | 1412 } |
1413 } | |
1414 | |
1415 void Assembler::incl(Address dst) { | |
1416 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1417 InstructionMark im(this); | |
1418 prefix(dst); | |
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1419 emit_int8((unsigned char)0xFF); |
304 | 1420 emit_operand(rax, dst); |
1421 } | |
1422 | |
3851 | 1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
1424 InstructionMark im(this); | |
304 | 1425 assert((0 <= cc) && (cc < 16), "illegal cc"); |
1426 if (L.is_bound()) { | |
1427 address dst = target(L); | |
1428 assert(dst != NULL, "jcc most probably wrong"); | |
1429 | |
1430 const int short_size = 2; | |
1431 const int long_size = 6; | |
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1432 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); |
3851 | 1433 if (maybe_short && is8bit(offs - short_size)) { |
304 | 1434 // 0111 tttn #8-bit disp |
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1435 emit_int8(0x70 | cc); |
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1436 emit_int8((offs - short_size) & 0xFF); |
304 | 1437 } else { |
1438 // 0000 1111 1000 tttn #32-bit disp | |
1439 assert(is_simm32(offs - long_size), | |
1440 "must be 32bit offset (call4)"); | |
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1441 emit_int8(0x0F); |
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1442 emit_int8((unsigned char)(0x80 | cc)); |
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1443 emit_int32(offs - long_size); |
304 | 1444 } |
1445 } else { | |
1446 // Note: could eliminate cond. jumps to this jump if condition | |
1447 // is the same however, seems to be rather unlikely case. | |
1448 // Note: use jccb() if label to be bound is very close to get | |
1449 // an 8-bit displacement | |
1450 L.add_patch_at(code(), locator()); | |
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1451 emit_int8(0x0F); |
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1452 emit_int8((unsigned char)(0x80 | cc)); |
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1453 emit_int32(0); |
304 | 1454 } |
1455 } | |
1456 | |
1457 void Assembler::jccb(Condition cc, Label& L) { | |
1458 if (L.is_bound()) { | |
1459 const int short_size = 2; | |
1460 address entry = target(L); | |
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1461 #ifdef ASSERT |
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1462 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1463 intptr_t delta = short_branch_delta(); |
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1464 if (delta != 0) { |
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1465 dist += (dist < 0 ? (-delta) :delta); |
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1466 } |
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1467 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1468 #endif |
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1469 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); |
304 | 1470 // 0111 tttn #8-bit disp |
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1471 emit_int8(0x70 | cc); |
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1472 emit_int8((offs - short_size) & 0xFF); |
304 | 1473 } else { |
1474 InstructionMark im(this); | |
1475 L.add_patch_at(code(), locator()); | |
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1476 emit_int8(0x70 | cc); |
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1477 emit_int8(0); |
304 | 1478 } |
1479 } | |
1480 | |
1481 void Assembler::jmp(Address adr) { | |
1482 InstructionMark im(this); | |
1483 prefix(adr); | |
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1484 emit_int8((unsigned char)0xFF); |
304 | 1485 emit_operand(rsp, adr); |
1486 } | |
1487 | |
3851 | 1488 void Assembler::jmp(Label& L, bool maybe_short) { |
304 | 1489 if (L.is_bound()) { |
1490 address entry = target(L); | |
1491 assert(entry != NULL, "jmp most probably wrong"); | |
1492 InstructionMark im(this); | |
1493 const int short_size = 2; | |
1494 const int long_size = 5; | |
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1495 intptr_t offs = entry - pc(); |
3851 | 1496 if (maybe_short && is8bit(offs - short_size)) { |
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1497 emit_int8((unsigned char)0xEB); |
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1498 emit_int8((offs - short_size) & 0xFF); |
304 | 1499 } else { |
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1500 emit_int8((unsigned char)0xE9); |
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1501 emit_int32(offs - long_size); |
304 | 1502 } |
1503 } else { | |
1504 // By default, forward jumps are always 32-bit displacements, since | |
1505 // we can't yet know where the label will be bound. If you're sure that | |
1506 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1507 // force an 8-bit displacement. | |
1508 InstructionMark im(this); | |
1509 L.add_patch_at(code(), locator()); | |
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1510 emit_int8((unsigned char)0xE9); |
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1511 emit_int32(0); |
304 | 1512 } |
1513 } | |
1514 | |
1515 void Assembler::jmp(Register entry) { | |
1516 int encode = prefix_and_encode(entry->encoding()); | |
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1517 emit_int8((unsigned char)0xFF); |
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1518 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1519 } |
1520 | |
1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1522 InstructionMark im(this); | |
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1523 emit_int8((unsigned char)0xE9); |
304 | 1524 assert(dest != NULL, "must have a target"); |
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1525 intptr_t disp = dest - (pc() + sizeof(int32_t)); |
304 | 1526 assert(is_simm32(disp), "must be 32bit offset (jmp)"); |
1527 emit_data(disp, rspec.reloc(), call32_operand); | |
1528 } | |
1529 | |
1530 void Assembler::jmpb(Label& L) { | |
1531 if (L.is_bound()) { | |
1532 const int short_size = 2; | |
1533 address entry = target(L); | |
1534 assert(entry != NULL, "jmp most probably wrong"); | |
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1535 #ifdef ASSERT |
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1536 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1537 intptr_t delta = short_branch_delta(); |
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1538 if (delta != 0) { |
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1539 dist += (dist < 0 ? (-delta) :delta); |
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1540 } |
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1541 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1542 #endif |
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1543 intptr_t offs = entry - pc(); |
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1544 emit_int8((unsigned char)0xEB); |
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1545 emit_int8((offs - short_size) & 0xFF); |
304 | 1546 } else { |
1547 InstructionMark im(this); | |
1548 L.add_patch_at(code(), locator()); | |
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1549 emit_int8((unsigned char)0xEB); |
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1550 emit_int8(0); |
304 | 1551 } |
1552 } | |
1553 | |
1554 void Assembler::ldmxcsr( Address src) { | |
1555 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1556 InstructionMark im(this); | |
1557 prefix(src); | |
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1558 emit_int8(0x0F); |
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1559 emit_int8((unsigned char)0xAE); |
304 | 1560 emit_operand(as_Register(2), src); |
1561 } | |
1562 | |
1563 void Assembler::leal(Register dst, Address src) { | |
1564 InstructionMark im(this); | |
1565 #ifdef _LP64 | |
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1566 emit_int8(0x67); // addr32 |
304 | 1567 prefix(src, dst); |
1568 #endif // LP64 | |
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1569 emit_int8((unsigned char)0x8D); |
304 | 1570 emit_operand(dst, src); |
1571 } | |
1572 | |
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1573 void Assembler::lfence() { |
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1574 emit_int8(0x0F); |
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1575 emit_int8((unsigned char)0xAE); |
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1576 emit_int8((unsigned char)0xE8); |
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1577 } |
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1578 |
304 | 1579 void Assembler::lock() { |
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1580 emit_int8((unsigned char)0xF0); |
304 | 1581 } |
1582 | |
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1583 void Assembler::lzcntl(Register dst, Register src) { |
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1584 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1585 emit_int8((unsigned char)0xF3); |
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1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1587 emit_int8(0x0F); |
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1588 emit_int8((unsigned char)0xBD); |
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1589 emit_int8((unsigned char)(0xC0 | encode)); |
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1590 } |
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1591 |
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1592 // Emit mfence instruction |
304 | 1593 void Assembler::mfence() { |
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1594 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1595 emit_int8(0x0F); |
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1596 emit_int8((unsigned char)0xAE); |
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1597 emit_int8((unsigned char)0xF0); |
304 | 1598 } |
1599 | |
1600 void Assembler::mov(Register dst, Register src) { | |
1601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1602 } | |
1603 | |
1604 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1605 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1606 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
304 | 1607 } |
1608 | |
1609 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1610 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1611 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
304 | 1612 } |
1613 | |
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1614 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
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1615 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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1616 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
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1617 emit_int8(0x16); |
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1618 emit_int8((unsigned char)(0xC0 | encode)); |
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1619 } |
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1620 |
304 | 1621 void Assembler::movb(Register dst, Address src) { |
1622 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1623 InstructionMark im(this); | |
1624 prefix(src, dst, true); | |
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1625 emit_int8((unsigned char)0x8A); |
304 | 1626 emit_operand(dst, src); |
1627 } | |
1628 | |
1629 | |
1630 void Assembler::movb(Address dst, int imm8) { | |
1631 InstructionMark im(this); | |
1632 prefix(dst); | |
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1633 emit_int8((unsigned char)0xC6); |
304 | 1634 emit_operand(rax, dst, 1); |
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1635 emit_int8(imm8); |
304 | 1636 } |
1637 | |
1638 | |
1639 void Assembler::movb(Address dst, Register src) { | |
1640 assert(src->has_byte_register(), "must have byte register"); | |
1641 InstructionMark im(this); | |
1642 prefix(dst, src, true); | |
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1643 emit_int8((unsigned char)0x88); |
304 | 1644 emit_operand(src, dst); |
1645 } | |
1646 | |
1647 void Assembler::movdl(XMMRegister dst, Register src) { | |
1648 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1649 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
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1650 emit_int8(0x6E); |
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1651 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1652 } |
1653 | |
1654 void Assembler::movdl(Register dst, XMMRegister src) { | |
1655 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1656 // swap src/dst to get correct prefix | |
4759 | 1657 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
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1658 emit_int8(0x7E); |
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1659 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1660 } |
1661 | |
2320
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1662 void Assembler::movdl(XMMRegister dst, Address src) { |
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1663 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1664 InstructionMark im(this); |
4759 | 1665 simd_prefix(dst, src, VEX_SIMD_66); |
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1666 emit_int8(0x6E); |
2320
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1667 emit_operand(dst, src); |
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1668 } |
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1669 |
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1670 void Assembler::movdl(Address dst, XMMRegister src) { |
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1671 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1672 InstructionMark im(this); |
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1673 simd_prefix(dst, src, VEX_SIMD_66); |
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1674 emit_int8(0x7E); |
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1675 emit_operand(src, dst); |
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1676 } |
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1677 |
304 | 1678 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1679 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1680 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
304 | 1681 } |
1682 | |
405 | 1683 void Assembler::movdqu(XMMRegister dst, Address src) { |
1684 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1685 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1686 } |
1687 | |
1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1690 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1691 } |
1692 | |
1693 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1694 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1695 InstructionMark im(this); | |
4759 | 1696 simd_prefix(dst, src, VEX_SIMD_F3); |
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1697 emit_int8(0x7F); |
405 | 1698 emit_operand(src, dst); |
1699 } | |
1700 | |
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1701 // Move Unaligned 256bit Vector |
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1702 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
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1703 assert(UseAVX, ""); |
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1704 bool vector256 = true; |
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1705 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1706 emit_int8(0x6F); |
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1707 emit_int8((unsigned char)(0xC0 | encode)); |
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1708 } |
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1709 |
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1710 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
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1711 assert(UseAVX, ""); |
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1712 InstructionMark im(this); |
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1713 bool vector256 = true; |
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1714 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1715 emit_int8(0x6F); |
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1716 emit_operand(dst, src); |
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1717 } |
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1718 |
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1719 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
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1720 assert(UseAVX, ""); |
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1721 InstructionMark im(this); |
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1722 bool vector256 = true; |
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1723 // swap src<->dst for encoding |
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1724 assert(src != xnoreg, "sanity"); |
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1725 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
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1726 emit_int8(0x7F); |
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1727 emit_operand(src, dst); |
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1728 } |
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1729 |
304 | 1730 // Uses zero extension on 64bit |
1731 | |
1732 void Assembler::movl(Register dst, int32_t imm32) { | |
1733 int encode = prefix_and_encode(dst->encoding()); | |
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1734 emit_int8((unsigned char)(0xB8 | encode)); |
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1735 emit_int32(imm32); |
304 | 1736 } |
1737 | |
1738 void Assembler::movl(Register dst, Register src) { | |
1739 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1740 emit_int8((unsigned char)0x8B); |
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1741 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1742 } |
1743 | |
1744 void Assembler::movl(Register dst, Address src) { | |
1745 InstructionMark im(this); | |
1746 prefix(src, dst); | |
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1747 emit_int8((unsigned char)0x8B); |
304 | 1748 emit_operand(dst, src); |
1749 } | |
1750 | |
1751 void Assembler::movl(Address dst, int32_t imm32) { | |
1752 InstructionMark im(this); | |
1753 prefix(dst); | |
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1754 emit_int8((unsigned char)0xC7); |
304 | 1755 emit_operand(rax, dst, 4); |
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1756 emit_int32(imm32); |
304 | 1757 } |
1758 | |
1759 void Assembler::movl(Address dst, Register src) { | |
1760 InstructionMark im(this); | |
1761 prefix(dst, src); | |
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1762 emit_int8((unsigned char)0x89); |
304 | 1763 emit_operand(src, dst); |
1764 } | |
1765 | |
1766 // New cpus require to use movsd and movss to avoid partial register stall | |
1767 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1768 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1769 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1770 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1771 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
304 | 1772 } |
1773 | |
1774 void Assembler::movq( MMXRegister dst, Address src ) { | |
1775 assert( VM_Version::supports_mmx(), "" ); | |
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1776 emit_int8(0x0F); |
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1777 emit_int8(0x6F); |
304 | 1778 emit_operand(dst, src); |
1779 } | |
1780 | |
1781 void Assembler::movq( Address dst, MMXRegister src ) { | |
1782 assert( VM_Version::supports_mmx(), "" ); | |
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1783 emit_int8(0x0F); |
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1784 emit_int8(0x7F); |
304 | 1785 // workaround gcc (3.2.1-7a) bug |
1786 // In that version of gcc with only an emit_operand(MMX, Address) | |
1787 // gcc will tail jump and try and reverse the parameters completely | |
1788 // obliterating dst in the process. By having a version available | |
1789 // that doesn't need to swap the args at the tail jump the bug is | |
1790 // avoided. | |
1791 emit_operand(dst, src); | |
1792 } | |
1793 | |
1794 void Assembler::movq(XMMRegister dst, Address src) { | |
1795 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1796 InstructionMark im(this); | |
4759 | 1797 simd_prefix(dst, src, VEX_SIMD_F3); |
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1798 emit_int8(0x7E); |
304 | 1799 emit_operand(dst, src); |
1800 } | |
1801 | |
1802 void Assembler::movq(Address dst, XMMRegister src) { | |
1803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1804 InstructionMark im(this); | |
4759 | 1805 simd_prefix(dst, src, VEX_SIMD_66); |
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1806 emit_int8((unsigned char)0xD6); |
304 | 1807 emit_operand(src, dst); |
1808 } | |
1809 | |
1810 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1811 InstructionMark im(this); | |
1812 prefix(src, dst); | |
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1813 emit_int8(0x0F); |
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1814 emit_int8((unsigned char)0xBE); |
304 | 1815 emit_operand(dst, src); |
1816 } | |
1817 | |
1818 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1819 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1820 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
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1821 emit_int8(0x0F); |
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1822 emit_int8((unsigned char)0xBE); |
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1823 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1824 } |
1825 | |
1826 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1827 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1828 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
304 | 1829 } |
1830 | |
1831 void Assembler::movsd(XMMRegister dst, Address src) { | |
1832 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1833 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
304 | 1834 } |
1835 | |
1836 void Assembler::movsd(Address dst, XMMRegister src) { | |
1837 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1838 InstructionMark im(this); | |
4759 | 1839 simd_prefix(dst, src, VEX_SIMD_F2); |
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1840 emit_int8(0x11); |
304 | 1841 emit_operand(src, dst); |
1842 } | |
1843 | |
1844 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1845 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1846 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
304 | 1847 } |
1848 | |
1849 void Assembler::movss(XMMRegister dst, Address src) { | |
1850 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1851 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
304 | 1852 } |
1853 | |
1854 void Assembler::movss(Address dst, XMMRegister src) { | |
1855 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1856 InstructionMark im(this); | |
4759 | 1857 simd_prefix(dst, src, VEX_SIMD_F3); |
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1858 emit_int8(0x11); |
304 | 1859 emit_operand(src, dst); |
1860 } | |
1861 | |
1862 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1863 InstructionMark im(this); | |
1864 prefix(src, dst); | |
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1865 emit_int8(0x0F); |
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1866 emit_int8((unsigned char)0xBF); |
304 | 1867 emit_operand(dst, src); |
1868 } | |
1869 | |
1870 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1871 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1872 emit_int8(0x0F); |
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1873 emit_int8((unsigned char)0xBF); |
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1874 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1875 } |
1876 | |
1877 void Assembler::movw(Address dst, int imm16) { | |
1878 InstructionMark im(this); | |
1879 | |
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1880 emit_int8(0x66); // switch to 16-bit mode |
304 | 1881 prefix(dst); |
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1882 emit_int8((unsigned char)0xC7); |
304 | 1883 emit_operand(rax, dst, 2); |
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1884 emit_int16(imm16); |
304 | 1885 } |
1886 | |
1887 void Assembler::movw(Register dst, Address src) { | |
1888 InstructionMark im(this); | |
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1889 emit_int8(0x66); |
304 | 1890 prefix(src, dst); |
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1891 emit_int8((unsigned char)0x8B); |
304 | 1892 emit_operand(dst, src); |
1893 } | |
1894 | |
1895 void Assembler::movw(Address dst, Register src) { | |
1896 InstructionMark im(this); | |
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1897 emit_int8(0x66); |
304 | 1898 prefix(dst, src); |
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1899 emit_int8((unsigned char)0x89); |
304 | 1900 emit_operand(src, dst); |
1901 } | |
1902 | |
1903 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1904 InstructionMark im(this); | |
1905 prefix(src, dst); | |
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1906 emit_int8(0x0F); |
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1907 emit_int8((unsigned char)0xB6); |
304 | 1908 emit_operand(dst, src); |
1909 } | |
1910 | |
1911 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
1912 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1913 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
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1914 emit_int8(0x0F); |
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1915 emit_int8((unsigned char)0xB6); |
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1916 emit_int8(0xC0 | encode); |
304 | 1917 } |
1918 | |
1919 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
1920 InstructionMark im(this); | |
1921 prefix(src, dst); | |
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1922 emit_int8(0x0F); |
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1923 emit_int8((unsigned char)0xB7); |
304 | 1924 emit_operand(dst, src); |
1925 } | |
1926 | |
1927 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1929 emit_int8(0x0F); |
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1930 emit_int8((unsigned char)0xB7); |
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1931 emit_int8(0xC0 | encode); |
304 | 1932 } |
1933 | |
1934 void Assembler::mull(Address src) { | |
1935 InstructionMark im(this); | |
1936 prefix(src); | |
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1937 emit_int8((unsigned char)0xF7); |
304 | 1938 emit_operand(rsp, src); |
1939 } | |
1940 | |
1941 void Assembler::mull(Register src) { | |
1942 int encode = prefix_and_encode(src->encoding()); | |
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1943 emit_int8((unsigned char)0xF7); |
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1944 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1945 } |
1946 | |
1947 void Assembler::mulsd(XMMRegister dst, Address src) { | |
1948 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1949 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 1950 } |
1951 | |
1952 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
1953 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1954 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 1955 } |
1956 | |
1957 void Assembler::mulss(XMMRegister dst, Address src) { | |
1958 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1959 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 1960 } |
1961 | |
1962 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
1963 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1964 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 1965 } |
1966 | |
1967 void Assembler::negl(Register dst) { | |
1968 int encode = prefix_and_encode(dst->encoding()); | |
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1969 emit_int8((unsigned char)0xF7); |
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1970 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 1971 } |
1972 | |
0 | 1973 void Assembler::nop(int i) { |
304 | 1974 #ifdef ASSERT |
0 | 1975 assert(i > 0, " "); |
304 | 1976 // The fancy nops aren't currently recognized by debuggers making it a |
1977 // pain to disassemble code while debugging. If asserts are on clearly | |
1978 // speed is not an issue so simply use the single byte traditional nop | |
1979 // to do alignment. | |
1980 | |
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1981 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); |
304 | 1982 return; |
1983 | |
1984 #endif // ASSERT | |
1985 | |
0 | 1986 if (UseAddressNop && VM_Version::is_intel()) { |
1987 // | |
1988 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
1989 // 1: 0x90 | |
1990 // 2: 0x66 0x90 | |
1991 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
1992 // 4: 0x0F 0x1F 0x40 0x00 | |
1993 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
1994 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
1995 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
1996 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1997 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1998 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1999 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2000 | |
2001 // The rest coding is Intel specific - don't use consecutive address nops | |
2002 | |
2003 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2004 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2005 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2006 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2007 | |
2008 while(i >= 15) { | |
2009 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
2010 i -= 15; | |
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2011 emit_int8(0x66); // size prefix |
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2012 emit_int8(0x66); // size prefix |
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2013 emit_int8(0x66); // size prefix |
0 | 2014 addr_nop_8(); |
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2015 emit_int8(0x66); // size prefix |
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2016 emit_int8(0x66); // size prefix |
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2017 emit_int8(0x66); // size prefix |
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2018 emit_int8((unsigned char)0x90); |
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2019 // nop |
0 | 2020 } |
2021 switch (i) { | |
2022 case 14: | |
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2023 emit_int8(0x66); // size prefix |
0 | 2024 case 13: |
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2025 emit_int8(0x66); // size prefix |
0 | 2026 case 12: |
2027 addr_nop_8(); | |
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2028 emit_int8(0x66); // size prefix |
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2029 emit_int8(0x66); // size prefix |
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2030 emit_int8(0x66); // size prefix |
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2031 emit_int8((unsigned char)0x90); |
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2032 // nop |
0 | 2033 break; |
2034 case 11: | |
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2035 emit_int8(0x66); // size prefix |
0 | 2036 case 10: |
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2037 emit_int8(0x66); // size prefix |
0 | 2038 case 9: |
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2039 emit_int8(0x66); // size prefix |
0 | 2040 case 8: |
2041 addr_nop_8(); | |
2042 break; | |
2043 case 7: | |
2044 addr_nop_7(); | |
2045 break; | |
2046 case 6: | |
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2047 emit_int8(0x66); // size prefix |
0 | 2048 case 5: |
2049 addr_nop_5(); | |
2050 break; | |
2051 case 4: | |
2052 addr_nop_4(); | |
2053 break; | |
2054 case 3: | |
2055 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2056 emit_int8(0x66); // size prefix |
0 | 2057 case 2: |
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2058 emit_int8(0x66); // size prefix |
0 | 2059 case 1: |
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2060 emit_int8((unsigned char)0x90); |
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2061 // nop |
0 | 2062 break; |
2063 default: | |
2064 assert(i == 0, " "); | |
2065 } | |
2066 return; | |
2067 } | |
2068 if (UseAddressNop && VM_Version::is_amd()) { | |
2069 // | |
2070 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
2071 // 1: 0x90 | |
2072 // 2: 0x66 0x90 | |
2073 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2074 // 4: 0x0F 0x1F 0x40 0x00 | |
2075 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2076 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2077 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2078 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2079 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2080 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2081 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2082 | |
2083 // The rest coding is AMD specific - use consecutive address nops | |
2084 | |
2085 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2086 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2087 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2088 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2089 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2090 // Size prefixes (0x66) are added for larger sizes | |
2091 | |
2092 while(i >= 22) { | |
2093 i -= 11; | |
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2094 emit_int8(0x66); // size prefix |
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2095 emit_int8(0x66); // size prefix |
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2096 emit_int8(0x66); // size prefix |
0 | 2097 addr_nop_8(); |
2098 } | |
2099 // Generate first nop for size between 21-12 | |
2100 switch (i) { | |
2101 case 21: | |
2102 i -= 1; | |
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2103 emit_int8(0x66); // size prefix |
0 | 2104 case 20: |
2105 case 19: | |
2106 i -= 1; | |
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2107 emit_int8(0x66); // size prefix |
0 | 2108 case 18: |
2109 case 17: | |
2110 i -= 1; | |
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2111 emit_int8(0x66); // size prefix |
0 | 2112 case 16: |
2113 case 15: | |
2114 i -= 8; | |
2115 addr_nop_8(); | |
2116 break; | |
2117 case 14: | |
2118 case 13: | |
2119 i -= 7; | |
2120 addr_nop_7(); | |
2121 break; | |
2122 case 12: | |
2123 i -= 6; | |
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2124 emit_int8(0x66); // size prefix |
0 | 2125 addr_nop_5(); |
2126 break; | |
2127 default: | |
2128 assert(i < 12, " "); | |
2129 } | |
2130 | |
2131 // Generate second nop for size between 11-1 | |
2132 switch (i) { | |
2133 case 11: | |
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2134 emit_int8(0x66); // size prefix |
0 | 2135 case 10: |
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2136 emit_int8(0x66); // size prefix |
0 | 2137 case 9: |
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2138 emit_int8(0x66); // size prefix |
0 | 2139 case 8: |
2140 addr_nop_8(); | |
2141 break; | |
2142 case 7: | |
2143 addr_nop_7(); | |
2144 break; | |
2145 case 6: | |
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2146 emit_int8(0x66); // size prefix |
0 | 2147 case 5: |
2148 addr_nop_5(); | |
2149 break; | |
2150 case 4: | |
2151 addr_nop_4(); | |
2152 break; | |
2153 case 3: | |
2154 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2155 emit_int8(0x66); // size prefix |
0 | 2156 case 2: |
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2157 emit_int8(0x66); // size prefix |
0 | 2158 case 1: |
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2159 emit_int8((unsigned char)0x90); |
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|
2160 // nop |
0 | 2161 break; |
2162 default: | |
2163 assert(i == 0, " "); | |
2164 } | |
2165 return; | |
2166 } | |
2167 | |
2168 // Using nops with size prefixes "0x66 0x90". | |
2169 // From AMD Optimization Guide: | |
2170 // 1: 0x90 | |
2171 // 2: 0x66 0x90 | |
2172 // 3: 0x66 0x66 0x90 | |
2173 // 4: 0x66 0x66 0x66 0x90 | |
2174 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2175 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2176 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2177 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2178 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2179 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2180 // | |
2181 while(i > 12) { | |
2182 i -= 4; | |
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2183 emit_int8(0x66); // size prefix |
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2184 emit_int8(0x66); |
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2185 emit_int8(0x66); |
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2186 emit_int8((unsigned char)0x90); |
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2187 // nop |
0 | 2188 } |
2189 // 1 - 12 nops | |
2190 if(i > 8) { | |
2191 if(i > 9) { | |
2192 i -= 1; | |
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2193 emit_int8(0x66); |
0 | 2194 } |
2195 i -= 3; | |
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2196 emit_int8(0x66); |
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2197 emit_int8(0x66); |
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2198 emit_int8((unsigned char)0x90); |
0 | 2199 } |
2200 // 1 - 8 nops | |
2201 if(i > 4) { | |
2202 if(i > 6) { | |
2203 i -= 1; | |
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2204 emit_int8(0x66); |
0 | 2205 } |
2206 i -= 3; | |
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2207 emit_int8(0x66); |
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2208 emit_int8(0x66); |
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2209 emit_int8((unsigned char)0x90); |
0 | 2210 } |
2211 switch (i) { | |
2212 case 4: | |
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2213 emit_int8(0x66); |
0 | 2214 case 3: |
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2215 emit_int8(0x66); |
0 | 2216 case 2: |
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2217 emit_int8(0x66); |
0 | 2218 case 1: |
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|
2219 emit_int8((unsigned char)0x90); |
0 | 2220 break; |
2221 default: | |
2222 assert(i == 0, " "); | |
2223 } | |
2224 } | |
2225 | |
304 | 2226 void Assembler::notl(Register dst) { |
2227 int encode = prefix_and_encode(dst->encoding()); | |
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2228 emit_int8((unsigned char)0xF7); |
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|
2229 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2230 } |
2231 | |
2232 void Assembler::orl(Address dst, int32_t imm32) { | |
2233 InstructionMark im(this); | |
2234 prefix(dst); | |
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|
2235 emit_arith_operand(0x81, rcx, dst, imm32); |
304 | 2236 } |
2237 | |
2238 void Assembler::orl(Register dst, int32_t imm32) { | |
2239 prefix(dst); | |
2240 emit_arith(0x81, 0xC8, dst, imm32); | |
2241 } | |
2242 | |
2243 void Assembler::orl(Register dst, Address src) { | |
2244 InstructionMark im(this); | |
2245 prefix(src, dst); | |
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2246 emit_int8(0x0B); |
304 | 2247 emit_operand(dst, src); |
2248 } | |
2249 | |
2250 void Assembler::orl(Register dst, Register src) { | |
2251 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2252 emit_arith(0x0B, 0xC0, dst, src); | |
2253 } | |
2254 | |
4759 | 2255 void Assembler::packuswb(XMMRegister dst, Address src) { |
2256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2257 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2258 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2259 } |
2260 | |
2261 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
2262 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2263 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2264 } |
2265 | |
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2266 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
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2267 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
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2268 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256); |
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2269 } |
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2270 |
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2271 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) { |
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2272 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256); |
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2273 emit_int8(0x00); |
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2274 emit_int8(0xC0 | encode); |
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2275 emit_int8(imm8); |
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2276 } |
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2277 |
681 | 2278 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2279 assert(VM_Version::supports_sse4_2(), ""); | |
4759 | 2280 InstructionMark im(this); |
2281 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
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2282 emit_int8(0x61); |
681 | 2283 emit_operand(dst, src); |
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|
2284 emit_int8(imm8); |
681 | 2285 } |
2286 | |
2287 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
2288 assert(VM_Version::supports_sse4_2(), ""); | |
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2289 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
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2290 emit_int8(0x61); |
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2291 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2292 emit_int8(imm8); |
681 | 2293 } |
2294 | |
4759 | 2295 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
2296 assert(VM_Version::supports_sse4_1(), ""); | |
2297 InstructionMark im(this); | |
2298 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2299 emit_int8(0x30); |
4759 | 2300 emit_operand(dst, src); |
2301 } | |
2302 | |
2303 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
2304 assert(VM_Version::supports_sse4_1(), ""); | |
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2305 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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2306 emit_int8(0x30); |
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2307 emit_int8((unsigned char)(0xC0 | encode)); |
4759 | 2308 } |
2309 | |
304 | 2310 // generic |
2311 void Assembler::pop(Register dst) { | |
2312 int encode = prefix_and_encode(dst->encoding()); | |
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2313 emit_int8(0x58 | encode); |
304 | 2314 } |
2315 | |
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2316 void Assembler::popcntl(Register dst, Address src) { |
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2317 assert(VM_Version::supports_popcnt(), "must support"); |
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2318 InstructionMark im(this); |
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2319 emit_int8((unsigned char)0xF3); |
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2320 prefix(src, dst); |
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2321 emit_int8(0x0F); |
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2322 emit_int8((unsigned char)0xB8); |
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2323 emit_operand(dst, src); |
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2324 } |
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2325 |
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2326 void Assembler::popcntl(Register dst, Register src) { |
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2327 assert(VM_Version::supports_popcnt(), "must support"); |
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2328 emit_int8((unsigned char)0xF3); |
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2329 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2330 emit_int8(0x0F); |
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2331 emit_int8((unsigned char)0xB8); |
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2332 emit_int8((unsigned char)(0xC0 | encode)); |
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2333 } |
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2334 |
304 | 2335 void Assembler::popf() { |
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2336 emit_int8((unsigned char)0x9D); |
304 | 2337 } |
2338 | |
1060 | 2339 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2340 void Assembler::popl(Address dst) { |
2341 // NOTE: this will adjust stack by 8byte on 64bits | |
2342 InstructionMark im(this); | |
2343 prefix(dst); | |
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2344 emit_int8((unsigned char)0x8F); |
304 | 2345 emit_operand(rax, dst); |
2346 } | |
1060 | 2347 #endif |
304 | 2348 |
2349 void Assembler::prefetch_prefix(Address src) { | |
2350 prefix(src); | |
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2351 emit_int8(0x0F); |
304 | 2352 } |
2353 | |
2354 void Assembler::prefetchnta(Address src) { | |
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2355 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
304 | 2356 InstructionMark im(this); |
2357 prefetch_prefix(src); | |
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2358 emit_int8(0x18); |
304 | 2359 emit_operand(rax, src); // 0, src |
2360 } | |
2361 | |
2362 void Assembler::prefetchr(Address src) { | |
3854 | 2363 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2364 InstructionMark im(this); |
2365 prefetch_prefix(src); | |
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2366 emit_int8(0x0D); |
304 | 2367 emit_operand(rax, src); // 0, src |
2368 } | |
2369 | |
2370 void Assembler::prefetcht0(Address src) { | |
2371 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2372 InstructionMark im(this); | |
2373 prefetch_prefix(src); | |
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2374 emit_int8(0x18); |
304 | 2375 emit_operand(rcx, src); // 1, src |
2376 } | |
2377 | |
2378 void Assembler::prefetcht1(Address src) { | |
2379 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2380 InstructionMark im(this); | |
2381 prefetch_prefix(src); | |
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2382 emit_int8(0x18); |
304 | 2383 emit_operand(rdx, src); // 2, src |
2384 } | |
2385 | |
2386 void Assembler::prefetcht2(Address src) { | |
2387 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2388 InstructionMark im(this); | |
2389 prefetch_prefix(src); | |
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2390 emit_int8(0x18); |
304 | 2391 emit_operand(rbx, src); // 3, src |
2392 } | |
2393 | |
2394 void Assembler::prefetchw(Address src) { | |
3854 | 2395 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2396 InstructionMark im(this); |
2397 prefetch_prefix(src); | |
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2398 emit_int8(0x0D); |
304 | 2399 emit_operand(rcx, src); // 1, src |
2400 } | |
2401 | |
2402 void Assembler::prefix(Prefix p) { | |
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2403 emit_int8(p); |
304 | 2404 } |
2405 | |
6894 | 2406 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
2407 assert(VM_Version::supports_ssse3(), ""); | |
2408 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2409 emit_int8(0x00); |
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2410 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 2411 } |
2412 | |
2413 void Assembler::pshufb(XMMRegister dst, Address src) { | |
2414 assert(VM_Version::supports_ssse3(), ""); | |
2415 InstructionMark im(this); | |
2416 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2417 emit_int8(0x00); |
6894 | 2418 emit_operand(dst, src); |
2419 } | |
2420 | |
304 | 2421 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2422 assert(isByte(mode), "invalid value"); | |
2423 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2424 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
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2425 emit_int8(mode & 0xFF); |
304 | 2426 |
2427 } | |
2428 | |
2429 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2430 assert(isByte(mode), "invalid value"); | |
2431 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2432 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2433 InstructionMark im(this); | |
2434 simd_prefix(dst, src, VEX_SIMD_66); | |
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2435 emit_int8(0x70); |
304 | 2436 emit_operand(dst, src); |
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2437 emit_int8(mode & 0xFF); |
304 | 2438 } |
2439 | |
2440 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2441 assert(isByte(mode), "invalid value"); | |
2442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2443 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
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2444 emit_int8(mode & 0xFF); |
304 | 2445 } |
2446 | |
2447 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2448 assert(isByte(mode), "invalid value"); | |
2449 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2450 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2451 InstructionMark im(this); | |
2452 simd_prefix(dst, src, VEX_SIMD_F2); | |
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2453 emit_int8(0x70); |
304 | 2454 emit_operand(dst, src); |
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2455 emit_int8(mode & 0xFF); |
304 | 2456 } |
2457 | |
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2458 void Assembler::psrldq(XMMRegister dst, int shift) { |
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2459 // Shift 128 bit value in xmm register by number of bytes. |
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2460 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4759 | 2461 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
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2462 emit_int8(0x73); |
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2463 emit_int8((unsigned char)(0xC0 | encode)); |
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2464 emit_int8(shift); |
2320
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2465 } |
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2466 |
681 | 2467 void Assembler::ptest(XMMRegister dst, Address src) { |
2468 assert(VM_Version::supports_sse4_1(), ""); | |
4759 | 2469 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2470 InstructionMark im(this); | |
2471 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2472 emit_int8(0x17); |
681 | 2473 emit_operand(dst, src); |
2474 } | |
2475 | |
2476 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
2477 assert(VM_Version::supports_sse4_1(), ""); | |
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2478 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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2479 emit_int8(0x17); |
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2480 emit_int8((unsigned char)(0xC0 | encode)); |
681 | 2481 } |
2482 | |
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2483 void Assembler::vptest(XMMRegister dst, Address src) { |
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2484 assert(VM_Version::supports_avx(), ""); |
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2485 InstructionMark im(this); |
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2486 bool vector256 = true; |
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2487 assert(dst != xnoreg, "sanity"); |
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2488 int dst_enc = dst->encoding(); |
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|
2489 // swap src<->dst for encoding |
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2490 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
7477
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2491 emit_int8(0x17); |
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2492 emit_operand(dst, src); |
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2493 } |
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2494 |
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2495 void Assembler::vptest(XMMRegister dst, XMMRegister src) { |
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2496 assert(VM_Version::supports_avx(), ""); |
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|
2497 bool vector256 = true; |
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2498 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
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|
2499 emit_int8(0x17); |
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2500 emit_int8((unsigned char)(0xC0 | encode)); |
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2501 } |
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2502 |
4759 | 2503 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
2504 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2505 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2506 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
4759 | 2507 } |
2508 | |
304 | 2509 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2511 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
304 | 2512 } |
2513 | |
4759 | 2514 void Assembler::punpckldq(XMMRegister dst, Address src) { |
2515 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2516 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2517 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2518 } |
2519 | |
2520 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
2521 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2522 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2523 } |
2524 | |
6225 | 2525 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
2526 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2527 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
6225 | 2528 } |
2529 | |
304 | 2530 void Assembler::push(int32_t imm32) { |
2531 // in 64bits we push 64bits onto the stack but only | |
2532 // take a 32bit immediate | |
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2533 emit_int8(0x68); |
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2534 emit_int32(imm32); |
304 | 2535 } |
2536 | |
2537 void Assembler::push(Register src) { | |
2538 int encode = prefix_and_encode(src->encoding()); | |
2539 | |
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2540 emit_int8(0x50 | encode); |
304 | 2541 } |
2542 | |
2543 void Assembler::pushf() { | |
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2544 emit_int8((unsigned char)0x9C); |
304 | 2545 } |
2546 | |
1060 | 2547 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2548 void Assembler::pushl(Address src) { |
2549 // Note this will push 64bit on 64bit | |
2550 InstructionMark im(this); | |
2551 prefix(src); | |
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2552 emit_int8((unsigned char)0xFF); |
304 | 2553 emit_operand(rsi, src); |
2554 } | |
1060 | 2555 #endif |
304 | 2556 |
2557 void Assembler::rcll(Register dst, int imm8) { | |
2558 assert(isShiftCount(imm8), "illegal shift count"); | |
2559 int encode = prefix_and_encode(dst->encoding()); | |
2560 if (imm8 == 1) { | |
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2561 emit_int8((unsigned char)0xD1); |
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2562 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2563 } else { |
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2564 emit_int8((unsigned char)0xC1); |
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2565 emit_int8((unsigned char)0xD0 | encode); |
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2566 emit_int8(imm8); |
304 | 2567 } |
2568 } | |
2569 | |
2570 // copies data from [esi] to [edi] using rcx pointer sized words | |
2571 // generic | |
2572 void Assembler::rep_mov() { | |
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2573 emit_int8((unsigned char)0xF3); |
304 | 2574 // MOVSQ |
2575 LP64_ONLY(prefix(REX_W)); | |
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2576 emit_int8((unsigned char)0xA5); |
304 | 2577 } |
2578 | |
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2579 // sets rcx bytes with rax, value at [edi] |
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2580 void Assembler::rep_stosb() { |
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2581 emit_int8((unsigned char)0xF3); // REP |
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2582 LP64_ONLY(prefix(REX_W)); |
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2583 emit_int8((unsigned char)0xAA); // STOSB |
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2584 } |
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2585 |
304 | 2586 // sets rcx pointer sized words with rax, value at [edi] |
2587 // generic | |
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2588 void Assembler::rep_stos() { |
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2589 emit_int8((unsigned char)0xF3); // REP |
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2590 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD |
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2591 emit_int8((unsigned char)0xAB); |
304 | 2592 } |
2593 | |
2594 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2595 // generic | |
2596 void Assembler::repne_scan() { // repne_scan | |
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2597 emit_int8((unsigned char)0xF2); |
304 | 2598 // SCASQ |
2599 LP64_ONLY(prefix(REX_W)); | |
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2600 emit_int8((unsigned char)0xAF); |
304 | 2601 } |
2602 | |
2603 #ifdef _LP64 | |
2604 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2605 // generic | |
2606 void Assembler::repne_scanl() { // repne_scan | |
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2607 emit_int8((unsigned char)0xF2); |
304 | 2608 // SCASL |
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2609 emit_int8((unsigned char)0xAF); |
304 | 2610 } |
2611 #endif | |
2612 | |
0 | 2613 void Assembler::ret(int imm16) { |
2614 if (imm16 == 0) { | |
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2615 emit_int8((unsigned char)0xC3); |
0 | 2616 } else { |
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|
2617 emit_int8((unsigned char)0xC2); |
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2618 emit_int16(imm16); |
0 | 2619 } |
2620 } | |
2621 | |
304 | 2622 void Assembler::sahf() { |
2623 #ifdef _LP64 | |
2624 // Not supported in 64bit mode | |
2625 ShouldNotReachHere(); | |
2626 #endif | |
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2627 emit_int8((unsigned char)0x9E); |
304 | 2628 } |
2629 | |
2630 void Assembler::sarl(Register dst, int imm8) { | |
2631 int encode = prefix_and_encode(dst->encoding()); | |
2632 assert(isShiftCount(imm8), "illegal shift count"); | |
2633 if (imm8 == 1) { | |
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|
2634 emit_int8((unsigned char)0xD1); |
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|
2635 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2636 } else { |
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|
2637 emit_int8((unsigned char)0xC1); |
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|
2638 emit_int8((unsigned char)(0xF8 | encode)); |
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|
2639 emit_int8(imm8); |
304 | 2640 } |
2641 } | |
2642 | |
2643 void Assembler::sarl(Register dst) { | |
2644 int encode = prefix_and_encode(dst->encoding()); | |
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|
2645 emit_int8((unsigned char)0xD3); |
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2646 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2647 } |
2648 | |
2649 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2650 InstructionMark im(this); | |
2651 prefix(dst); | |
2652 emit_arith_operand(0x81, rbx, dst, imm32); | |
2653 } | |
2654 | |
2655 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2656 prefix(dst); | |
2657 emit_arith(0x81, 0xD8, dst, imm32); | |
2658 } | |
2659 | |
2660 | |
2661 void Assembler::sbbl(Register dst, Address src) { | |
2662 InstructionMark im(this); | |
2663 prefix(src, dst); | |
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|
2664 emit_int8(0x1B); |
304 | 2665 emit_operand(dst, src); |
2666 } | |
2667 | |
2668 void Assembler::sbbl(Register dst, Register src) { | |
2669 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2670 emit_arith(0x1B, 0xC0, dst, src); | |
2671 } | |
2672 | |
2673 void Assembler::setb(Condition cc, Register dst) { | |
2674 assert(0 <= cc && cc < 16, "illegal cc"); | |
2675 int encode = prefix_and_encode(dst->encoding(), true); | |
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|
2676 emit_int8(0x0F); |
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|
2677 emit_int8((unsigned char)0x90 | cc); |
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|
2678 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2679 } |
2680 | |
2681 void Assembler::shll(Register dst, int imm8) { | |
2682 assert(isShiftCount(imm8), "illegal shift count"); | |
2683 int encode = prefix_and_encode(dst->encoding()); | |
2684 if (imm8 == 1 ) { | |
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|
2685 emit_int8((unsigned char)0xD1); |
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|
2686 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2687 } else { |
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|
2688 emit_int8((unsigned char)0xC1); |
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changeset
|
2689 emit_int8((unsigned char)(0xE0 | encode)); |
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|
2690 emit_int8(imm8); |
304 | 2691 } |
2692 } | |
2693 | |
2694 void Assembler::shll(Register dst) { | |
2695 int encode = prefix_and_encode(dst->encoding()); | |
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|
2696 emit_int8((unsigned char)0xD3); |
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changeset
|
2697 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2698 } |
2699 | |
2700 void Assembler::shrl(Register dst, int imm8) { | |
2701 assert(isShiftCount(imm8), "illegal shift count"); | |
2702 int encode = prefix_and_encode(dst->encoding()); | |
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|
2703 emit_int8((unsigned char)0xC1); |
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|
2704 emit_int8((unsigned char)(0xE8 | encode)); |
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|
2705 emit_int8(imm8); |
304 | 2706 } |
2707 | |
2708 void Assembler::shrl(Register dst) { | |
2709 int encode = prefix_and_encode(dst->encoding()); | |
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|
2710 emit_int8((unsigned char)0xD3); |
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|
2711 emit_int8((unsigned char)(0xE8 | encode)); |
304 | 2712 } |
0 | 2713 |
2714 // copies a single word from [esi] to [edi] | |
2715 void Assembler::smovl() { | |
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2716 emit_int8((unsigned char)0xA5); |
0 | 2717 } |
2718 | |
304 | 2719 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2720 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2721 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
304 | 2722 } |
2723 | |
2008 | 2724 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2725 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2726 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2008 | 2727 } |
2728 | |
2729 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
4759 | 2730 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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2731 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2732 } |
2733 | |
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2734 void Assembler::std() { |
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|
2735 emit_int8((unsigned char)0xFD); |
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2736 } |
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2737 |
2008 | 2738 void Assembler::sqrtss(XMMRegister dst, Address src) { |
4759 | 2739 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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|
2740 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2741 } |
2742 | |
304 | 2743 void Assembler::stmxcsr( Address dst) { |
2744 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2745 InstructionMark im(this); | |
2746 prefix(dst); | |
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|
2747 emit_int8(0x0F); |
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|
2748 emit_int8((unsigned char)0xAE); |
304 | 2749 emit_operand(as_Register(3), dst); |
2750 } | |
2751 | |
2752 void Assembler::subl(Address dst, int32_t imm32) { | |
2753 InstructionMark im(this); | |
2754 prefix(dst); | |
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|
2755 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 2756 } |
2757 | |
2758 void Assembler::subl(Address dst, Register src) { | |
2759 InstructionMark im(this); | |
2760 prefix(dst, src); | |
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|
2761 emit_int8(0x29); |
304 | 2762 emit_operand(src, dst); |
2763 } | |
2764 | |
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2765 void Assembler::subl(Register dst, int32_t imm32) { |
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|
2766 prefix(dst); |
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|
2767 emit_arith(0x81, 0xE8, dst, imm32); |
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|
2768 } |
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changeset
|
2769 |
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2770 // Force generation of a 4 byte immediate value even if it fits into 8bit |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2771 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2772 prefix(dst); |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2773 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2774 } |
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changeset
|
2775 |
304 | 2776 void Assembler::subl(Register dst, Address src) { |
2777 InstructionMark im(this); | |
2778 prefix(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2779 emit_int8(0x2B); |
304 | 2780 emit_operand(dst, src); |
2781 } | |
2782 | |
2783 void Assembler::subl(Register dst, Register src) { | |
2784 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2785 emit_arith(0x2B, 0xC0, dst, src); | |
2786 } | |
2787 | |
2788 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2789 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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changeset
|
2790 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2791 } |
2792 | |
2793 void Assembler::subsd(XMMRegister dst, Address src) { | |
2794 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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changeset
|
2795 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2796 } |
2797 | |
2798 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2799 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2800 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2801 } |
2802 | |
2803 void Assembler::subss(XMMRegister dst, Address src) { | |
2804 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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changeset
|
2805 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2806 } |
2807 | |
2808 void Assembler::testb(Register dst, int imm8) { | |
2809 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2810 (void) prefix_and_encode(dst->encoding(), true); | |
2811 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2812 } | |
2813 | |
2814 void Assembler::testl(Register dst, int32_t imm32) { | |
2815 // not using emit_arith because test | |
2816 // doesn't support sign-extension of | |
2817 // 8bit operands | |
2818 int encode = dst->encoding(); | |
2819 if (encode == 0) { | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2820 emit_int8((unsigned char)0xA9); |
304 | 2821 } else { |
2822 encode = prefix_and_encode(encode); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2823 emit_int8((unsigned char)0xF7); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2824 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2825 } |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
2826 emit_int32(imm32); |
304 | 2827 } |
2828 | |
2829 void Assembler::testl(Register dst, Register src) { | |
2830 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2831 emit_arith(0x85, 0xC0, dst, src); | |
2832 } | |
2833 | |
2834 void Assembler::testl(Register dst, Address src) { | |
2835 InstructionMark im(this); | |
2836 prefix(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2837 emit_int8((unsigned char)0x85); |
304 | 2838 emit_operand(dst, src); |
2839 } | |
2840 | |
2841 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
2842 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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changeset
|
2843 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2844 } |
2845 | |
2846 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2847 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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changeset
|
2848 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2849 } |
2850 | |
2851 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2852 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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changeset
|
2853 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2854 } |
2855 | |
2856 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2857 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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changeset
|
2858 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2859 } |
2860 | |
2861 | |
2862 void Assembler::xaddl(Address dst, Register src) { | |
2863 InstructionMark im(this); | |
2864 prefix(dst, src); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
2865 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
2866 emit_int8((unsigned char)0xC1); |
304 | 2867 emit_operand(src, dst); |
2868 } | |
2869 | |
2870 void Assembler::xchgl(Register dst, Address src) { // xchg | |
2871 InstructionMark im(this); | |
2872 prefix(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2873 emit_int8((unsigned char)0x87); |
304 | 2874 emit_operand(dst, src); |
2875 } | |
2876 | |
2877 void Assembler::xchgl(Register dst, Register src) { | |
2878 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2879 emit_int8((unsigned char)0x87); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
2880 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2881 } |
2882 | |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
parents:
7198
diff
changeset
|
2883 void Assembler::xgetbv() { |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2884 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2885 emit_int8(0x01); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2886 emit_int8((unsigned char)0xD0); |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
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7198
diff
changeset
|
2887 } |
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
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7198
diff
changeset
|
2888 |
304 | 2889 void Assembler::xorl(Register dst, int32_t imm32) { |
2890 prefix(dst); | |
2891 emit_arith(0x81, 0xF0, dst, imm32); | |
2892 } | |
2893 | |
2894 void Assembler::xorl(Register dst, Address src) { | |
2895 InstructionMark im(this); | |
2896 prefix(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2897 emit_int8(0x33); |
304 | 2898 emit_operand(dst, src); |
2899 } | |
2900 | |
2901 void Assembler::xorl(Register dst, Register src) { | |
2902 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2903 emit_arith(0x33, 0xC0, dst, src); | |
2904 } | |
2905 | |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2906 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
2907 // AVX 3-operands scalar float-point arithmetic instructions |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
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|
2908 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2909 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
2910 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
2911 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
2912 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2913 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2914 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
2915 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
2916 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2917 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2918 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2919 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2920 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2921 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2922 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2923 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2924 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2925 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2926 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2927 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2928 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2929 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2930 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2931 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2932 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2933 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2934 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2935 assert(VM_Version::supports_avx(), ""); |
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6340864: Implement vectorization optimizations in hotspot-server
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|
2936 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
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|
2937 } |
65149e74c706
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changeset
|
2938 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2939 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2940 assert(VM_Version::supports_avx(), ""); |
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6340864: Implement vectorization optimizations in hotspot-server
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|
2941 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
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|
2942 } |
65149e74c706
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changeset
|
2943 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2944 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2945 assert(VM_Version::supports_avx(), ""); |
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|
2946 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
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|
2947 } |
65149e74c706
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changeset
|
2948 |
65149e74c706
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|
2949 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2950 assert(VM_Version::supports_avx(), ""); |
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changeset
|
2951 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
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|
2952 } |
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changeset
|
2953 |
65149e74c706
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changeset
|
2954 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2955 assert(VM_Version::supports_avx(), ""); |
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changeset
|
2956 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
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|
2957 } |
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|
2958 |
65149e74c706
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|
2959 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
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|
2960 assert(VM_Version::supports_avx(), ""); |
006050192a5a
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changeset
|
2961 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
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|
2962 } |
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|
2963 |
65149e74c706
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|
2964 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2965 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2966 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2967 } |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2968 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2969 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2970 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2971 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2972 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2973 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2974 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2975 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2976 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2977 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2978 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2979 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2980 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2981 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2982 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2983 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2984 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2985 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2986 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2987 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2988 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2989 //====================VECTOR ARITHMETIC===================================== |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2990 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2991 // Float-point vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2992 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2993 void Assembler::addpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2994 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2995 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2996 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2997 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2998 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2999 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3000 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3001 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3002 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3003 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3004 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3005 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3006 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3007 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3008 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3009 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3010 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3011 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3012 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3013 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3014 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3015 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3016 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3017 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3018 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3019 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3020 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3021 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3022 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3023 void Assembler::subpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3024 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3025 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3026 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3027 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3028 void Assembler::subps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3029 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3030 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3031 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3032 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3033 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3034 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3035 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3036 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3037 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3038 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3039 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3040 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3041 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3042 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3043 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3044 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3045 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3046 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3047 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3048 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3049 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3050 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3051 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3052 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3053 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3054 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3055 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3056 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3057 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3058 void Assembler::mulps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3059 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3060 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3061 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3062 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3063 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3064 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3065 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3066 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3067 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3068 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3069 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3070 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3071 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3072 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3073 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3074 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3075 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3076 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3077 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3078 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3079 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3080 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3081 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3082 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3083 void Assembler::divpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3084 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3085 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3086 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3087 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3088 void Assembler::divps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3089 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3090 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3091 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3092 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3093 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3094 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3095 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3096 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3097 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3098 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3099 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3100 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3101 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3102 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3103 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3104 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3105 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3106 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3107 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3108 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3109 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3110 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3111 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3112 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3113 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3114 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3115 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3116 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3117 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3118 void Assembler::andps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3119 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3120 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3121 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3122 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3123 void Assembler::andps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3124 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3125 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3126 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3127 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3128 void Assembler::andpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3129 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3130 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3131 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3132 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3133 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3134 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3135 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3136 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3137 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3138 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3139 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3140 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3141 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3142 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3143 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3144 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3145 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3146 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3147 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3148 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3149 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3150 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3151 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3152 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3153 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3154 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3155 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3156 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3157 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3158 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3159 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3160 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3161 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3162 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3163 void Assembler::xorpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3164 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3165 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3166 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3167 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3168 void Assembler::xorps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3169 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3170 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3171 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3172 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3173 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3174 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3175 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3176 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3177 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3178 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3179 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3180 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3181 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3182 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3183 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3184 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3185 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3186 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3187 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3188 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3189 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3190 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3191 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3192 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3193 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3194 // Integer vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3195 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3196 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3197 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3198 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3199 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3200 void Assembler::paddw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3202 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3203 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3204 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3205 void Assembler::paddd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3206 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3207 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3208 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3209 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3210 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3211 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3212 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3213 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3214 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3215 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3216 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3217 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3218 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3219 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3220 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3221 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3222 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3223 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3224 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3225 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3226 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3227 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3228 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3229 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3230 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3231 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3232 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3233 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3234 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3235 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3236 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3237 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3238 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3239 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3240 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3241 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3242 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3243 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3244 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3245 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3246 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3247 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3248 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3249 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3250 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3251 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3252 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3253 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3254 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3255 void Assembler::psubb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3257 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3258 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3259 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3260 void Assembler::psubw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3261 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3262 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3263 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3264 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3265 void Assembler::psubd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3266 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3267 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3268 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3269 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3270 void Assembler::psubq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3271 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3272 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3273 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3274 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3275 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3276 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3277 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3278 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3279 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3280 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3281 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3282 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3283 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3284 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3285 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3286 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3287 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3288 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3289 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3290 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3291 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3292 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3293 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3294 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3295 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3296 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3297 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3298 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3299 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3300 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3301 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3302 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3303 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3304 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3305 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3306 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3307 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3308 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3309 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3310 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3311 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3312 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3313 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3314 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3315 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3316 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3317 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3318 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3319 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3320 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3321 assert(VM_Version::supports_sse4_1(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3323 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3324 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3325 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3326 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3327 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3328 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3329 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3330 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3331 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3332 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3333 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3334 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3335 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3336 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3337 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3338 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3339 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3340 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3341 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3342 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3343 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3344 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3345 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3346 InstructionMark im(this); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3347 int dst_enc = dst->encoding(); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3348 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3349 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3350 emit_int8(0x40); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3351 emit_operand(dst, src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3352 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3353 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3354 // Shift packed integers left by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3355 void Assembler::psllw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3356 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3357 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3358 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3359 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3360 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3361 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3362 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3363 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3364 void Assembler::pslld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3365 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3366 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3367 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3368 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3369 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3370 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3371 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3372 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3373 void Assembler::psllq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3375 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3376 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3377 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3378 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3379 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3380 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3381 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3382 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3383 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3384 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3385 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3386 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3387 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3388 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3389 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3390 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3391 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3392 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3393 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3394 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3395 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3396 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3397 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3398 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3399 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3400 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3401 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3402 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3403 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3404 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3405 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3406 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3407 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3408 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3409 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3410 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3411 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3412 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3413 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3414 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3415 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3416 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3417 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3418 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3419 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3420 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3421 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3422 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3423 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3424 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3425 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3426 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3427 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3428 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3429 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3430 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3431 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3432 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3433 // Shift packed integers logically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3434 void Assembler::psrlw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3435 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3436 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3437 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3438 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3439 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3440 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3441 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3442 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3443 void Assembler::psrld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3444 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3445 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3446 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3447 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3448 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3449 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3450 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3451 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3452 void Assembler::psrlq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3453 // Do not confuse it with psrldq SSE2 instruction which |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3454 // shifts 128 bit value in xmm register by number of bytes. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3455 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3456 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3457 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3458 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3459 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3460 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3461 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3462 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3463 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3464 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3465 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3466 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3467 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3468 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3469 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3470 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3471 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3472 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3473 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3474 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3475 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3476 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3477 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3478 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3479 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3480 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3481 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3482 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3483 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3484 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3485 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3486 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3487 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3488 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3489 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3490 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3491 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3492 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3493 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3494 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3495 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3496 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3497 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3498 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3499 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3500 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3501 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3502 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3503 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3504 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3505 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3506 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3507 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3508 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3509 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3510 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3511 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3512 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3513 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3514 // Shift packed integers arithmetically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3515 void Assembler::psraw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3516 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3517 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3518 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3519 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3520 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3521 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3522 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3523 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3524 void Assembler::psrad(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3525 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3526 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3527 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3528 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3529 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3530 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3531 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3532 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3533 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3534 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3535 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3536 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3537 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3538 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3539 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3540 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3541 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3542 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3543 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3544 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3545 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3546 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3547 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3548 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3549 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3550 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3551 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3552 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3553 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3554 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3555 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3556 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3557 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3558 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3559 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3560 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3561 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3562 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3563 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3564 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3565 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3566 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3567 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3568 // AND packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3569 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3570 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3571 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3572 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3573 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3574 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3575 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3576 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3577 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3578 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3579 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3580 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3581 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3582 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3583 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3584 void Assembler::por(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3585 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3586 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3587 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3588 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3589 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3590 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3591 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3592 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3593 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3594 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3595 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3596 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3597 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3598 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3599 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3600 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3601 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3602 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3603 |
6225 | 3604 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3605 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3606 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3607 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3608 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3609 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3610 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3611 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3612 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3613 |
6225 | 3614 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3615 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3616 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3617 bool vector256 = true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3618 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3619 emit_int8(0x18); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3620 emit_int8((unsigned char)(0xC0 | encode)); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3621 // 0x00 - insert into lower 128 bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3622 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3623 emit_int8(0x01); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3624 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3625 |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3626 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3627 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3628 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3629 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3630 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3631 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3632 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3633 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3634 emit_int8(0x18); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3635 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3636 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3637 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3638 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3639 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3640 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3641 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3642 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3643 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3644 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3645 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3646 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3647 emit_int8(0x19); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3648 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3649 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3650 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3651 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3652 |
6225 | 3653 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3654 assert(VM_Version::supports_avx2(), ""); | |
3655 bool vector256 = true; | |
3656 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3657 emit_int8(0x38); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3658 emit_int8((unsigned char)(0xC0 | encode)); |
6225 | 3659 // 0x00 - insert into lower 128 bits |
3660 // 0x01 - insert into upper 128 bits | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3661 emit_int8(0x01); |
6225 | 3662 } |
3663 | |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3664 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3665 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3666 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3667 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3668 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3669 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3670 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3671 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3672 emit_int8(0x38); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3673 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3674 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
3675 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3676 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3677 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3678 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3679 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3680 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3681 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3682 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3683 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3684 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3685 emit_int8(0x39); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3686 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3687 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3688 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3689 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3690 |
7475
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3691 // duplicate 4-bytes integer data from src into 8 locations in dest |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3692 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3693 assert(VM_Version::supports_avx2(), ""); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3694 bool vector256 = true; |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3695 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3696 emit_int8(0x58); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3697 emit_int8((unsigned char)(0xC0 | encode)); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3698 } |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3699 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3700 void Assembler::vzeroupper() { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3701 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3702 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3703 emit_int8(0x77); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3704 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3705 |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3706 |
304 | 3707 #ifndef _LP64 |
3708 // 32bit only pieces of the assembler | |
3709 | |
3710 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
3711 // NO PREFIX AS NEVER 64BIT | |
3712 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3713 emit_int8((unsigned char)0x81); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3714 emit_int8((unsigned char)(0xF8 | src1->encoding())); |
304 | 3715 emit_data(imm32, rspec, 0); |
3716 } | |
3717 | |
3718 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
3719 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
3720 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3721 emit_int8((unsigned char)0x81); |
304 | 3722 emit_operand(rdi, src1); |
3723 emit_data(imm32, rspec, 0); | |
3724 } | |
3725 | |
3726 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
3727 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
3728 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
3729 void Assembler::cmpxchg8(Address adr) { | |
3730 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3731 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3732 emit_int8((unsigned char)0xC7); |
304 | 3733 emit_operand(rcx, adr); |
3734 } | |
3735 | |
3736 void Assembler::decl(Register dst) { | |
3737 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3738 emit_int8(0x48 | dst->encoding()); |
304 | 3739 } |
3740 | |
3741 #endif // _LP64 | |
3742 | |
3743 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
3744 | |
3745 void Assembler::fabs() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3746 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3747 emit_int8((unsigned char)0xE1); |
304 | 3748 } |
3749 | |
3750 void Assembler::fadd(int i) { | |
3751 emit_farith(0xD8, 0xC0, i); | |
3752 } | |
3753 | |
3754 void Assembler::fadd_d(Address src) { | |
3755 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3756 emit_int8((unsigned char)0xDC); |
304 | 3757 emit_operand32(rax, src); |
3758 } | |
3759 | |
3760 void Assembler::fadd_s(Address src) { | |
3761 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3762 emit_int8((unsigned char)0xD8); |
304 | 3763 emit_operand32(rax, src); |
3764 } | |
3765 | |
3766 void Assembler::fadda(int i) { | |
3767 emit_farith(0xDC, 0xC0, i); | |
3768 } | |
3769 | |
3770 void Assembler::faddp(int i) { | |
3771 emit_farith(0xDE, 0xC0, i); | |
3772 } | |
3773 | |
3774 void Assembler::fchs() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3775 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3776 emit_int8((unsigned char)0xE0); |
304 | 3777 } |
3778 | |
3779 void Assembler::fcom(int i) { | |
3780 emit_farith(0xD8, 0xD0, i); | |
3781 } | |
3782 | |
3783 void Assembler::fcomp(int i) { | |
3784 emit_farith(0xD8, 0xD8, i); | |
3785 } | |
3786 | |
3787 void Assembler::fcomp_d(Address src) { | |
3788 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3789 emit_int8((unsigned char)0xDC); |
304 | 3790 emit_operand32(rbx, src); |
3791 } | |
3792 | |
3793 void Assembler::fcomp_s(Address src) { | |
3794 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3795 emit_int8((unsigned char)0xD8); |
304 | 3796 emit_operand32(rbx, src); |
3797 } | |
3798 | |
3799 void Assembler::fcompp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3800 emit_int8((unsigned char)0xDE); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3801 emit_int8((unsigned char)0xD9); |
304 | 3802 } |
3803 | |
3804 void Assembler::fcos() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3805 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3806 emit_int8((unsigned char)0xFF); |
304 | 3807 } |
3808 | |
3809 void Assembler::fdecstp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3810 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3811 emit_int8((unsigned char)0xF6); |
304 | 3812 } |
3813 | |
3814 void Assembler::fdiv(int i) { | |
3815 emit_farith(0xD8, 0xF0, i); | |
3816 } | |
3817 | |
3818 void Assembler::fdiv_d(Address src) { | |
3819 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3820 emit_int8((unsigned char)0xDC); |
304 | 3821 emit_operand32(rsi, src); |
3822 } | |
3823 | |
3824 void Assembler::fdiv_s(Address src) { | |
3825 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3826 emit_int8((unsigned char)0xD8); |
304 | 3827 emit_operand32(rsi, src); |
3828 } | |
3829 | |
3830 void Assembler::fdiva(int i) { | |
3831 emit_farith(0xDC, 0xF8, i); | |
3832 } | |
3833 | |
3834 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
3835 // is erroneous for some of the floating-point instructions below. | |
3836 | |
3837 void Assembler::fdivp(int i) { | |
3838 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
3839 } | |
3840 | |
3841 void Assembler::fdivr(int i) { | |
3842 emit_farith(0xD8, 0xF8, i); | |
3843 } | |
3844 | |
3845 void Assembler::fdivr_d(Address src) { | |
3846 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3847 emit_int8((unsigned char)0xDC); |
304 | 3848 emit_operand32(rdi, src); |
3849 } | |
3850 | |
3851 void Assembler::fdivr_s(Address src) { | |
3852 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3853 emit_int8((unsigned char)0xD8); |
304 | 3854 emit_operand32(rdi, src); |
3855 } | |
3856 | |
3857 void Assembler::fdivra(int i) { | |
3858 emit_farith(0xDC, 0xF0, i); | |
3859 } | |
3860 | |
3861 void Assembler::fdivrp(int i) { | |
3862 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
3863 } | |
3864 | |
3865 void Assembler::ffree(int i) { | |
3866 emit_farith(0xDD, 0xC0, i); | |
3867 } | |
3868 | |
3869 void Assembler::fild_d(Address adr) { | |
3870 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3871 emit_int8((unsigned char)0xDF); |
304 | 3872 emit_operand32(rbp, adr); |
3873 } | |
3874 | |
3875 void Assembler::fild_s(Address adr) { | |
3876 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3877 emit_int8((unsigned char)0xDB); |
304 | 3878 emit_operand32(rax, adr); |
3879 } | |
3880 | |
3881 void Assembler::fincstp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3882 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3883 emit_int8((unsigned char)0xF7); |
304 | 3884 } |
3885 | |
3886 void Assembler::finit() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3887 emit_int8((unsigned char)0x9B); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3888 emit_int8((unsigned char)0xDB); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3889 emit_int8((unsigned char)0xE3); |
304 | 3890 } |
3891 | |
3892 void Assembler::fist_s(Address adr) { | |
3893 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3894 emit_int8((unsigned char)0xDB); |
304 | 3895 emit_operand32(rdx, adr); |
3896 } | |
3897 | |
3898 void Assembler::fistp_d(Address adr) { | |
3899 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3900 emit_int8((unsigned char)0xDF); |
304 | 3901 emit_operand32(rdi, adr); |
3902 } | |
3903 | |
3904 void Assembler::fistp_s(Address adr) { | |
3905 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3906 emit_int8((unsigned char)0xDB); |
304 | 3907 emit_operand32(rbx, adr); |
3908 } | |
0 | 3909 |
3910 void Assembler::fld1() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3911 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3912 emit_int8((unsigned char)0xE8); |
0 | 3913 } |
3914 | |
304 | 3915 void Assembler::fld_d(Address adr) { |
3916 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3917 emit_int8((unsigned char)0xDD); |
304 | 3918 emit_operand32(rax, adr); |
3919 } | |
0 | 3920 |
3921 void Assembler::fld_s(Address adr) { | |
3922 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3923 emit_int8((unsigned char)0xD9); |
304 | 3924 emit_operand32(rax, adr); |
3925 } | |
3926 | |
3927 | |
3928 void Assembler::fld_s(int index) { | |
0 | 3929 emit_farith(0xD9, 0xC0, index); |
3930 } | |
3931 | |
3932 void Assembler::fld_x(Address adr) { | |
3933 InstructionMark im(this); | |
7430
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parents:
7427
diff
changeset
|
3934 emit_int8((unsigned char)0xDB); |
304 | 3935 emit_operand32(rbp, adr); |
3936 } | |
3937 | |
3938 void Assembler::fldcw(Address src) { | |
3939 InstructionMark im(this); | |
7430
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3940 emit_int8((unsigned char)0xD9); |
304 | 3941 emit_operand32(rbp, src); |
3942 } | |
3943 | |
3944 void Assembler::fldenv(Address src) { | |
0 | 3945 InstructionMark im(this); |
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3946 emit_int8((unsigned char)0xD9); |
304 | 3947 emit_operand32(rsp, src); |
3948 } | |
3949 | |
3950 void Assembler::fldlg2() { | |
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3951 emit_int8((unsigned char)0xD9); |
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3952 emit_int8((unsigned char)0xEC); |
304 | 3953 } |
0 | 3954 |
3955 void Assembler::fldln2() { | |
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|
3956 emit_int8((unsigned char)0xD9); |
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|
3957 emit_int8((unsigned char)0xED); |
0 | 3958 } |
3959 | |
304 | 3960 void Assembler::fldz() { |
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|
3961 emit_int8((unsigned char)0xD9); |
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|
3962 emit_int8((unsigned char)0xEE); |
304 | 3963 } |
0 | 3964 |
3965 void Assembler::flog() { | |
3966 fldln2(); | |
3967 fxch(); | |
3968 fyl2x(); | |
3969 } | |
3970 | |
3971 void Assembler::flog10() { | |
3972 fldlg2(); | |
3973 fxch(); | |
3974 fyl2x(); | |
3975 } | |
3976 | |
304 | 3977 void Assembler::fmul(int i) { |
3978 emit_farith(0xD8, 0xC8, i); | |
3979 } | |
3980 | |
3981 void Assembler::fmul_d(Address src) { | |
3982 InstructionMark im(this); | |
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|
3983 emit_int8((unsigned char)0xDC); |
304 | 3984 emit_operand32(rcx, src); |
3985 } | |
3986 | |
3987 void Assembler::fmul_s(Address src) { | |
3988 InstructionMark im(this); | |
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|
3989 emit_int8((unsigned char)0xD8); |
304 | 3990 emit_operand32(rcx, src); |
3991 } | |
3992 | |
3993 void Assembler::fmula(int i) { | |
3994 emit_farith(0xDC, 0xC8, i); | |
3995 } | |
3996 | |
3997 void Assembler::fmulp(int i) { | |
3998 emit_farith(0xDE, 0xC8, i); | |
3999 } | |
4000 | |
4001 void Assembler::fnsave(Address dst) { | |
4002 InstructionMark im(this); | |
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4003 emit_int8((unsigned char)0xDD); |
304 | 4004 emit_operand32(rsi, dst); |
4005 } | |
4006 | |
4007 void Assembler::fnstcw(Address src) { | |
4008 InstructionMark im(this); | |
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4009 emit_int8((unsigned char)0x9B); |
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|
4010 emit_int8((unsigned char)0xD9); |
304 | 4011 emit_operand32(rdi, src); |
4012 } | |
4013 | |
4014 void Assembler::fnstsw_ax() { | |
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|
4015 emit_int8((unsigned char)0xDF); |
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4016 emit_int8((unsigned char)0xE0); |
304 | 4017 } |
4018 | |
4019 void Assembler::fprem() { | |
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|
4020 emit_int8((unsigned char)0xD9); |
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|
4021 emit_int8((unsigned char)0xF8); |
304 | 4022 } |
4023 | |
4024 void Assembler::fprem1() { | |
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|
4025 emit_int8((unsigned char)0xD9); |
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|
4026 emit_int8((unsigned char)0xF5); |
304 | 4027 } |
4028 | |
4029 void Assembler::frstor(Address src) { | |
4030 InstructionMark im(this); | |
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|
4031 emit_int8((unsigned char)0xDD); |
304 | 4032 emit_operand32(rsp, src); |
4033 } | |
0 | 4034 |
4035 void Assembler::fsin() { | |
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|
4036 emit_int8((unsigned char)0xD9); |
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|
4037 emit_int8((unsigned char)0xFE); |
0 | 4038 } |
4039 | |
304 | 4040 void Assembler::fsqrt() { |
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|
4041 emit_int8((unsigned char)0xD9); |
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|
4042 emit_int8((unsigned char)0xFA); |
304 | 4043 } |
4044 | |
4045 void Assembler::fst_d(Address adr) { | |
4046 InstructionMark im(this); | |
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|
4047 emit_int8((unsigned char)0xDD); |
304 | 4048 emit_operand32(rdx, adr); |
4049 } | |
4050 | |
4051 void Assembler::fst_s(Address adr) { | |
4052 InstructionMark im(this); | |
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|
4053 emit_int8((unsigned char)0xD9); |
304 | 4054 emit_operand32(rdx, adr); |
4055 } | |
4056 | |
4057 void Assembler::fstp_d(Address adr) { | |
4058 InstructionMark im(this); | |
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changeset
|
4059 emit_int8((unsigned char)0xDD); |
304 | 4060 emit_operand32(rbx, adr); |
4061 } | |
4062 | |
4063 void Assembler::fstp_d(int index) { | |
4064 emit_farith(0xDD, 0xD8, index); | |
4065 } | |
4066 | |
4067 void Assembler::fstp_s(Address adr) { | |
4068 InstructionMark im(this); | |
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|
4069 emit_int8((unsigned char)0xD9); |
304 | 4070 emit_operand32(rbx, adr); |
4071 } | |
4072 | |
4073 void Assembler::fstp_x(Address adr) { | |
4074 InstructionMark im(this); | |
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|
4075 emit_int8((unsigned char)0xDB); |
304 | 4076 emit_operand32(rdi, adr); |
4077 } | |
4078 | |
4079 void Assembler::fsub(int i) { | |
4080 emit_farith(0xD8, 0xE0, i); | |
4081 } | |
4082 | |
4083 void Assembler::fsub_d(Address src) { | |
4084 InstructionMark im(this); | |
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|
4085 emit_int8((unsigned char)0xDC); |
304 | 4086 emit_operand32(rsp, src); |
4087 } | |
4088 | |
4089 void Assembler::fsub_s(Address src) { | |
4090 InstructionMark im(this); | |
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|
4091 emit_int8((unsigned char)0xD8); |
304 | 4092 emit_operand32(rsp, src); |
4093 } | |
4094 | |
4095 void Assembler::fsuba(int i) { | |
4096 emit_farith(0xDC, 0xE8, i); | |
4097 } | |
4098 | |
4099 void Assembler::fsubp(int i) { | |
4100 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
4101 } | |
4102 | |
4103 void Assembler::fsubr(int i) { | |
4104 emit_farith(0xD8, 0xE8, i); | |
4105 } | |
4106 | |
4107 void Assembler::fsubr_d(Address src) { | |
4108 InstructionMark im(this); | |
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|
4109 emit_int8((unsigned char)0xDC); |
304 | 4110 emit_operand32(rbp, src); |
4111 } | |
4112 | |
4113 void Assembler::fsubr_s(Address src) { | |
4114 InstructionMark im(this); | |
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|
4115 emit_int8((unsigned char)0xD8); |
304 | 4116 emit_operand32(rbp, src); |
4117 } | |
4118 | |
4119 void Assembler::fsubra(int i) { | |
4120 emit_farith(0xDC, 0xE0, i); | |
4121 } | |
4122 | |
4123 void Assembler::fsubrp(int i) { | |
4124 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 4125 } |
4126 | |
4127 void Assembler::ftan() { | |
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|
4128 emit_int8((unsigned char)0xD9); |
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|
4129 emit_int8((unsigned char)0xF2); |
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|
4130 emit_int8((unsigned char)0xDD); |
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|
4131 emit_int8((unsigned char)0xD8); |
0 | 4132 } |
4133 | |
304 | 4134 void Assembler::ftst() { |
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changeset
|
4135 emit_int8((unsigned char)0xD9); |
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|
4136 emit_int8((unsigned char)0xE4); |
304 | 4137 } |
0 | 4138 |
4139 void Assembler::fucomi(int i) { | |
4140 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4141 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4142 emit_farith(0xDB, 0xE8, i); | |
4143 } | |
4144 | |
4145 void Assembler::fucomip(int i) { | |
4146 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4147 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4148 emit_farith(0xDF, 0xE8, i); | |
4149 } | |
4150 | |
4151 void Assembler::fwait() { | |
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changeset
|
4152 emit_int8((unsigned char)0x9B); |
0 | 4153 } |
4154 | |
304 | 4155 void Assembler::fxch(int i) { |
4156 emit_farith(0xD9, 0xC8, i); | |
4157 } | |
4158 | |
4159 void Assembler::fyl2x() { | |
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changeset
|
4160 emit_int8((unsigned char)0xD9); |
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changeset
|
4161 emit_int8((unsigned char)0xF1); |
304 | 4162 } |
4163 | |
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|
4164 void Assembler::frndint() { |
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changeset
|
4165 emit_int8((unsigned char)0xD9); |
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|
4166 emit_int8((unsigned char)0xFC); |
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|
4167 } |
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|
4168 |
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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|
4169 void Assembler::f2xm1() { |
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changeset
|
4170 emit_int8((unsigned char)0xD9); |
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changeset
|
4171 emit_int8((unsigned char)0xF0); |
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|
4172 } |
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|
4173 |
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|
4174 void Assembler::fldl2e() { |
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changeset
|
4175 emit_int8((unsigned char)0xD9); |
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|
4176 emit_int8((unsigned char)0xEA); |
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|
4177 } |
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4178 |
4759 | 4179 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
4180 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
4181 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
4182 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
4183 | |
4184 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
4185 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4186 if (pre > 0) { | |
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|
4187 emit_int8(simd_pre[pre]); |
4759 | 4188 } |
4189 if (rex_w) { | |
4190 prefixq(adr, xreg); | |
4191 } else { | |
4192 prefix(adr, xreg); | |
4193 } | |
4194 if (opc > 0) { | |
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|
4195 emit_int8(0x0F); |
4759 | 4196 int opc2 = simd_opc[opc]; |
4197 if (opc2 > 0) { | |
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|
4198 emit_int8(opc2); |
4759 | 4199 } |
4200 } | |
4201 } | |
4202 | |
4203 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4204 if (pre > 0) { | |
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|
4205 emit_int8(simd_pre[pre]); |
4759 | 4206 } |
4207 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
4208 prefix_and_encode(dst_enc, src_enc); | |
4209 if (opc > 0) { | |
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|
4210 emit_int8(0x0F); |
4759 | 4211 int opc2 = simd_opc[opc]; |
4212 if (opc2 > 0) { | |
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|
4213 emit_int8(opc2); |
4759 | 4214 } |
4215 } | |
4216 return encode; | |
4217 } | |
4218 | |
4219 | |
4220 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
4221 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
4222 prefix(VEX_3bytes); | |
4223 | |
4224 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
4225 byte1 = (~byte1) & 0xE0; | |
4226 byte1 |= opc; | |
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|
4227 emit_int8(byte1); |
4759 | 4228 |
4229 int byte2 = ((~nds_enc) & 0xf) << 3; | |
4230 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
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changeset
|
4231 emit_int8(byte2); |
4759 | 4232 } else { |
4233 prefix(VEX_2bytes); | |
4234 | |
4235 int byte1 = vex_r ? VEX_R : 0; | |
4236 byte1 = (~byte1) & 0x80; | |
4237 byte1 |= ((~nds_enc) & 0xf) << 3; | |
4238 byte1 |= (vector256 ? 4 : 0) | pre; | |
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4239 emit_int8(byte1); |
4759 | 4240 } |
4241 } | |
4242 | |
4243 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
4244 bool vex_r = (xreg_enc >= 8); | |
4245 bool vex_b = adr.base_needs_rex(); | |
4246 bool vex_x = adr.index_needs_rex(); | |
4247 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4248 } | |
4249 | |
4250 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
4251 bool vex_r = (dst_enc >= 8); | |
4252 bool vex_b = (src_enc >= 8); | |
4253 bool vex_x = false; | |
4254 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4255 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
4256 } | |
4257 | |
4258 | |
4259 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4260 if (UseAVX > 0) { | |
4261 int xreg_enc = xreg->encoding(); | |
4262 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4263 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
4264 } else { | |
4265 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
4266 rex_prefix(adr, xreg, pre, opc, rex_w); | |
4267 } | |
4268 } | |
4269 | |
4270 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4271 int dst_enc = dst->encoding(); | |
4272 int src_enc = src->encoding(); | |
4273 if (UseAVX > 0) { | |
4274 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4275 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
4276 } else { | |
4277 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
4278 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
4279 } | |
4280 } | |
304 | 4281 |
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4282 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4283 InstructionMark im(this); |
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4284 simd_prefix(dst, dst, src, pre); |
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4285 emit_int8(opcode); |
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4286 emit_operand(dst, src); |
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4287 } |
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4288 |
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4289 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4290 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
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4291 emit_int8(opcode); |
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4292 emit_int8((unsigned char)(0xC0 | encode)); |
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4293 } |
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4294 |
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4295 // Versions with no second source register (non-destructive source). |
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4296 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4297 InstructionMark im(this); |
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4298 simd_prefix(dst, xnoreg, src, pre); |
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4299 emit_int8(opcode); |
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4300 emit_operand(dst, src); |
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4301 } |
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4302 |
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4303 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4304 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
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4305 emit_int8(opcode); |
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4306 emit_int8((unsigned char)(0xC0 | encode)); |
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4307 } |
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4308 |
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4309 // 3-operands AVX instructions |
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4310 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4311 Address src, VexSimdPrefix pre, bool vector256) { |
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4312 InstructionMark im(this); |
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4313 vex_prefix(dst, nds, src, pre, vector256); |
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4314 emit_int8(opcode); |
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4315 emit_operand(dst, src); |
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4316 } |
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4317 |
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4318 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4319 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
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4320 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
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4321 emit_int8(opcode); |
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4322 emit_int8((unsigned char)(0xC0 | encode)); |
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4323 } |
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4324 |
304 | 4325 #ifndef _LP64 |
4326 | |
4327 void Assembler::incl(Register dst) { | |
4328 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
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4329 emit_int8(0x40 | dst->encoding()); |
304 | 4330 } |
4331 | |
4332 void Assembler::lea(Register dst, Address src) { | |
4333 leal(dst, src); | |
4334 } | |
4335 | |
4336 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
4337 InstructionMark im(this); | |
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4338 emit_int8((unsigned char)0xC7); |
304 | 4339 emit_operand(rax, dst); |
4340 emit_data((int)imm32, rspec, 0); | |
4341 } | |
4342 | |
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4343 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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4344 InstructionMark im(this); |
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4345 int encode = prefix_and_encode(dst->encoding()); |
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4346 emit_int8((unsigned char)(0xB8 | encode)); |
642
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4347 emit_data((int)imm32, rspec, 0); |
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4348 } |
304 | 4349 |
4350 void Assembler::popa() { // 32bit | |
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4351 emit_int8(0x61); |
304 | 4352 } |
4353 | |
4354 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
4355 InstructionMark im(this); | |
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4356 emit_int8(0x68); |
304 | 4357 emit_data(imm32, rspec, 0); |
4358 } | |
4359 | |
4360 void Assembler::pusha() { // 32bit | |
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4361 emit_int8(0x60); |
304 | 4362 } |
4363 | |
4364 void Assembler::set_byte_if_not_zero(Register dst) { | |
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4365 emit_int8(0x0F); |
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4366 emit_int8((unsigned char)0x95); |
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4367 emit_int8((unsigned char)(0xE0 | dst->encoding())); |
304 | 4368 } |
4369 | |
4370 void Assembler::shldl(Register dst, Register src) { | |
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4371 emit_int8(0x0F); |
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4372 emit_int8((unsigned char)0xA5); |
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4373 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4374 } |
4375 | |
4376 void Assembler::shrdl(Register dst, Register src) { | |
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4377 emit_int8(0x0F); |
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4378 emit_int8((unsigned char)0xAD); |
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4379 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4380 } |
4381 | |
4382 #else // LP64 | |
4383 | |
1369 | 4384 void Assembler::set_byte_if_not_zero(Register dst) { |
4385 int enc = prefix_and_encode(dst->encoding(), true); | |
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4386 emit_int8(0x0F); |
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4387 emit_int8((unsigned char)0x95); |
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4388 emit_int8((unsigned char)(0xE0 | enc)); |
1369 | 4389 } |
4390 | |
304 | 4391 // 64bit only pieces of the assembler |
4392 // This should only be used by 64bit instructions that can use rip-relative | |
4393 // it cannot be used by instructions that want an immediate value. | |
4394 | |
4395 bool Assembler::reachable(AddressLiteral adr) { | |
4396 int64_t disp; | |
4397 // None will force a 64bit literal to the code stream. Likely a placeholder | |
4398 // for something that will be patched later and we need to certain it will | |
4399 // always be reachable. | |
4400 if (adr.reloc() == relocInfo::none) { | |
4401 return false; | |
4402 } | |
4403 if (adr.reloc() == relocInfo::internal_word_type) { | |
4404 // This should be rip relative and easily reachable. | |
4405 return true; | |
4406 } | |
4407 if (adr.reloc() == relocInfo::virtual_call_type || | |
4408 adr.reloc() == relocInfo::opt_virtual_call_type || | |
4409 adr.reloc() == relocInfo::static_call_type || | |
4410 adr.reloc() == relocInfo::static_stub_type ) { | |
4411 // This should be rip relative within the code cache and easily | |
4412 // reachable until we get huge code caches. (At which point | |
4413 // ic code is going to have issues). | |
4414 return true; | |
4415 } | |
4416 if (adr.reloc() != relocInfo::external_word_type && | |
4417 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
4418 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
4419 adr.reloc() != relocInfo::runtime_call_type ) { | |
4420 return false; | |
4421 } | |
4422 | |
4423 // Stress the correction code | |
4424 if (ForceUnreachable) { | |
4425 // Must be runtimecall reloc, see if it is in the codecache | |
4426 // Flipping stuff in the codecache to be unreachable causes issues | |
4427 // with things like inline caches where the additional instructions | |
4428 // are not handled. | |
4429 if (CodeCache::find_blob(adr._target) == NULL) { | |
4430 return false; | |
4431 } | |
4432 } | |
4433 // For external_word_type/runtime_call_type if it is reachable from where we | |
4434 // are now (possibly a temp buffer) and where we might end up | |
4435 // anywhere in the codeCache then we are always reachable. | |
4436 // This would have to change if we ever save/restore shared code | |
4437 // to be more pessimistic. | |
4438 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
4439 if (!is_simm32(disp)) return false; | |
4440 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
4441 if (!is_simm32(disp)) return false; | |
4442 | |
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4443 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); |
304 | 4444 |
4445 // Because rip relative is a disp + address_of_next_instruction and we | |
4446 // don't know the value of address_of_next_instruction we apply a fudge factor | |
4447 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
4448 // We don't have to fudge the checks above here because they are already worst case. | |
4449 | |
4450 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
4451 // + 4 because better safe than sorry. | |
4452 const int fudge = 12 + 4; | |
4453 if (disp < 0) { | |
4454 disp -= fudge; | |
4455 } else { | |
4456 disp += fudge; | |
4457 } | |
4458 return is_simm32(disp); | |
4459 } | |
4460 | |
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4461 // Check if the polling page is not reachable from the code cache using rip-relative |
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4462 // addressing. |
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4463 bool Assembler::is_polling_page_far() { |
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4464 intptr_t addr = (intptr_t)os::get_polling_page(); |
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4465 return ForceUnreachable || |
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4466 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
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4467 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
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|
4468 } |
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4469 |
304 | 4470 void Assembler::emit_data64(jlong data, |
4471 relocInfo::relocType rtype, | |
4472 int format) { | |
4473 if (rtype == relocInfo::none) { | |
7198
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6894
diff
changeset
|
4474 emit_int64(data); |
304 | 4475 } else { |
4476 emit_data64(data, Relocation::spec_simple(rtype), format); | |
4477 } | |
4478 } | |
4479 | |
4480 void Assembler::emit_data64(jlong data, | |
4481 RelocationHolder const& rspec, | |
4482 int format) { | |
4483 assert(imm_operand == 0, "default format must be immediate in this file"); | |
4484 assert(imm_operand == format, "must be immediate"); | |
4485 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
4486 // Do not use AbstractAssembler::relocate, which is not intended for | |
4487 // embedded words. Instead, relocate to the enclosing instruction. | |
4488 code_section()->relocate(inst_mark(), rspec, format); | |
4489 #ifdef ASSERT | |
4490 check_relocation(rspec, format); | |
4491 #endif | |
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6ab62ad83507
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diff
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4492 emit_int64(data); |
304 | 4493 } |
4494 | |
4495 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
4496 if (reg_enc >= 8) { | |
4497 prefix(REX_B); | |
4498 reg_enc -= 8; | |
4499 } else if (byteinst && reg_enc >= 4) { | |
4500 prefix(REX); | |
4501 } | |
4502 return reg_enc; | |
4503 } | |
4504 | |
4505 int Assembler::prefixq_and_encode(int reg_enc) { | |
4506 if (reg_enc < 8) { | |
4507 prefix(REX_W); | |
4508 } else { | |
4509 prefix(REX_WB); | |
4510 reg_enc -= 8; | |
4511 } | |
4512 return reg_enc; | |
4513 } | |
4514 | |
4515 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
4516 if (dst_enc < 8) { | |
4517 if (src_enc >= 8) { | |
4518 prefix(REX_B); | |
4519 src_enc -= 8; | |
4520 } else if (byteinst && src_enc >= 4) { | |
4521 prefix(REX); | |
4522 } | |
4523 } else { | |
4524 if (src_enc < 8) { | |
4525 prefix(REX_R); | |
4526 } else { | |
4527 prefix(REX_RB); | |
4528 src_enc -= 8; | |
4529 } | |
4530 dst_enc -= 8; | |
4531 } | |
4532 return dst_enc << 3 | src_enc; | |
4533 } | |
4534 | |
4535 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
4536 if (dst_enc < 8) { | |
4537 if (src_enc < 8) { | |
4538 prefix(REX_W); | |
4539 } else { | |
4540 prefix(REX_WB); | |
4541 src_enc -= 8; | |
4542 } | |
4543 } else { | |
4544 if (src_enc < 8) { | |
4545 prefix(REX_WR); | |
4546 } else { | |
4547 prefix(REX_WRB); | |
4548 src_enc -= 8; | |
4549 } | |
4550 dst_enc -= 8; | |
4551 } | |
4552 return dst_enc << 3 | src_enc; | |
4553 } | |
4554 | |
4555 void Assembler::prefix(Register reg) { | |
4556 if (reg->encoding() >= 8) { | |
4557 prefix(REX_B); | |
4558 } | |
4559 } | |
4560 | |
4561 void Assembler::prefix(Address adr) { | |
4562 if (adr.base_needs_rex()) { | |
4563 if (adr.index_needs_rex()) { | |
4564 prefix(REX_XB); | |
4565 } else { | |
4566 prefix(REX_B); | |
4567 } | |
4568 } else { | |
4569 if (adr.index_needs_rex()) { | |
4570 prefix(REX_X); | |
4571 } | |
4572 } | |
4573 } | |
4574 | |
4575 void Assembler::prefixq(Address adr) { | |
4576 if (adr.base_needs_rex()) { | |
4577 if (adr.index_needs_rex()) { | |
4578 prefix(REX_WXB); | |
4579 } else { | |
4580 prefix(REX_WB); | |
4581 } | |
4582 } else { | |
4583 if (adr.index_needs_rex()) { | |
4584 prefix(REX_WX); | |
4585 } else { | |
4586 prefix(REX_W); | |
4587 } | |
4588 } | |
4589 } | |
4590 | |
4591 | |
4592 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
4593 if (reg->encoding() < 8) { | |
4594 if (adr.base_needs_rex()) { | |
4595 if (adr.index_needs_rex()) { | |
4596 prefix(REX_XB); | |
4597 } else { | |
4598 prefix(REX_B); | |
4599 } | |
4600 } else { | |
4601 if (adr.index_needs_rex()) { | |
4602 prefix(REX_X); | |
3855 | 4603 } else if (byteinst && reg->encoding() >= 4 ) { |
304 | 4604 prefix(REX); |
4605 } | |
4606 } | |
4607 } else { | |
4608 if (adr.base_needs_rex()) { | |
4609 if (adr.index_needs_rex()) { | |
4610 prefix(REX_RXB); | |
4611 } else { | |
4612 prefix(REX_RB); | |
4613 } | |
4614 } else { | |
4615 if (adr.index_needs_rex()) { | |
4616 prefix(REX_RX); | |
4617 } else { | |
4618 prefix(REX_R); | |
4619 } | |
4620 } | |
4621 } | |
4622 } | |
4623 | |
4624 void Assembler::prefixq(Address adr, Register src) { | |
4625 if (src->encoding() < 8) { | |
4626 if (adr.base_needs_rex()) { | |
4627 if (adr.index_needs_rex()) { | |
4628 prefix(REX_WXB); | |
4629 } else { | |
4630 prefix(REX_WB); | |
4631 } | |
4632 } else { | |
4633 if (adr.index_needs_rex()) { | |
4634 prefix(REX_WX); | |
4635 } else { | |
4636 prefix(REX_W); | |
4637 } | |
4638 } | |
4639 } else { | |
4640 if (adr.base_needs_rex()) { | |
4641 if (adr.index_needs_rex()) { | |
4642 prefix(REX_WRXB); | |
4643 } else { | |
4644 prefix(REX_WRB); | |
4645 } | |
4646 } else { | |
4647 if (adr.index_needs_rex()) { | |
4648 prefix(REX_WRX); | |
4649 } else { | |
4650 prefix(REX_WR); | |
4651 } | |
4652 } | |
4653 } | |
4654 } | |
4655 | |
4656 void Assembler::prefix(Address adr, XMMRegister reg) { | |
4657 if (reg->encoding() < 8) { | |
4658 if (adr.base_needs_rex()) { | |
4659 if (adr.index_needs_rex()) { | |
4660 prefix(REX_XB); | |
4661 } else { | |
4662 prefix(REX_B); | |
4663 } | |
4664 } else { | |
4665 if (adr.index_needs_rex()) { | |
4666 prefix(REX_X); | |
4667 } | |
4668 } | |
4669 } else { | |
4670 if (adr.base_needs_rex()) { | |
4671 if (adr.index_needs_rex()) { | |
4672 prefix(REX_RXB); | |
4673 } else { | |
4674 prefix(REX_RB); | |
4675 } | |
4676 } else { | |
4677 if (adr.index_needs_rex()) { | |
4678 prefix(REX_RX); | |
4679 } else { | |
4680 prefix(REX_R); | |
4681 } | |
4682 } | |
4683 } | |
4684 } | |
4685 | |
4759 | 4686 void Assembler::prefixq(Address adr, XMMRegister src) { |
4687 if (src->encoding() < 8) { | |
4688 if (adr.base_needs_rex()) { | |
4689 if (adr.index_needs_rex()) { | |
4690 prefix(REX_WXB); | |
4691 } else { | |
4692 prefix(REX_WB); | |
4693 } | |
4694 } else { | |
4695 if (adr.index_needs_rex()) { | |
4696 prefix(REX_WX); | |
4697 } else { | |
4698 prefix(REX_W); | |
4699 } | |
4700 } | |
4701 } else { | |
4702 if (adr.base_needs_rex()) { | |
4703 if (adr.index_needs_rex()) { | |
4704 prefix(REX_WRXB); | |
4705 } else { | |
4706 prefix(REX_WRB); | |
4707 } | |
4708 } else { | |
4709 if (adr.index_needs_rex()) { | |
4710 prefix(REX_WRX); | |
4711 } else { | |
4712 prefix(REX_WR); | |
4713 } | |
4714 } | |
4715 } | |
4716 } | |
4717 | |
304 | 4718 void Assembler::adcq(Register dst, int32_t imm32) { |
4719 (void) prefixq_and_encode(dst->encoding()); | |
4720 emit_arith(0x81, 0xD0, dst, imm32); | |
4721 } | |
4722 | |
4723 void Assembler::adcq(Register dst, Address src) { | |
4724 InstructionMark im(this); | |
4725 prefixq(src, dst); | |
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|
4726 emit_int8(0x13); |
304 | 4727 emit_operand(dst, src); |
4728 } | |
4729 | |
4730 void Assembler::adcq(Register dst, Register src) { | |
4731 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4732 emit_arith(0x13, 0xC0, dst, src); | |
4733 } | |
4734 | |
4735 void Assembler::addq(Address dst, int32_t imm32) { | |
4736 InstructionMark im(this); | |
4737 prefixq(dst); | |
4738 emit_arith_operand(0x81, rax, dst,imm32); | |
4739 } | |
4740 | |
4741 void Assembler::addq(Address dst, Register src) { | |
4742 InstructionMark im(this); | |
4743 prefixq(dst, src); | |
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diff
changeset
|
4744 emit_int8(0x01); |
304 | 4745 emit_operand(src, dst); |
4746 } | |
4747 | |
4748 void Assembler::addq(Register dst, int32_t imm32) { | |
4749 (void) prefixq_and_encode(dst->encoding()); | |
4750 emit_arith(0x81, 0xC0, dst, imm32); | |
4751 } | |
4752 | |
4753 void Assembler::addq(Register dst, Address src) { | |
4754 InstructionMark im(this); | |
4755 prefixq(src, dst); | |
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diff
changeset
|
4756 emit_int8(0x03); |
304 | 4757 emit_operand(dst, src); |
4758 } | |
4759 | |
4760 void Assembler::addq(Register dst, Register src) { | |
4761 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4762 emit_arith(0x03, 0xC0, dst, src); | |
4763 } | |
4764 | |
3457 | 4765 void Assembler::andq(Address dst, int32_t imm32) { |
4766 InstructionMark im(this); | |
4767 prefixq(dst); | |
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changeset
|
4768 emit_int8((unsigned char)0x81); |
3457 | 4769 emit_operand(rsp, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
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7475
diff
changeset
|
4770 emit_int32(imm32); |
3457 | 4771 } |
4772 | |
304 | 4773 void Assembler::andq(Register dst, int32_t imm32) { |
4774 (void) prefixq_and_encode(dst->encoding()); | |
4775 emit_arith(0x81, 0xE0, dst, imm32); | |
4776 } | |
4777 | |
4778 void Assembler::andq(Register dst, Address src) { | |
4779 InstructionMark im(this); | |
4780 prefixq(src, dst); | |
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7427
diff
changeset
|
4781 emit_int8(0x23); |
304 | 4782 emit_operand(dst, src); |
4783 } | |
4784 | |
4785 void Assembler::andq(Register dst, Register src) { | |
4786 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4787 emit_arith(0x23, 0xC0, dst, src); | |
4788 } | |
4789 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4790 void Assembler::bsfq(Register dst, Register src) { |
93c14e5562c4
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710
diff
changeset
|
4791 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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changeset
|
4792 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4793 emit_int8((unsigned char)0xBC); |
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7427
diff
changeset
|
4794 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
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twisti
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710
diff
changeset
|
4795 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
4796 |
93c14e5562c4
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diff
changeset
|
4797 void Assembler::bsrq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
|
4798 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
|
4799 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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|
4800 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4801 emit_int8((unsigned char)0xBD); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4802 emit_int8((unsigned char)(0xC0 | encode)); |
775
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diff
changeset
|
4803 } |
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diff
changeset
|
4804 |
304 | 4805 void Assembler::bswapq(Register reg) { |
4806 int encode = prefixq_and_encode(reg->encoding()); | |
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|
4807 emit_int8(0x0F); |
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diff
changeset
|
4808 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 4809 } |
4810 | |
4811 void Assembler::cdqq() { | |
4812 prefix(REX_W); | |
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changeset
|
4813 emit_int8((unsigned char)0x99); |
304 | 4814 } |
4815 | |
4816 void Assembler::clflush(Address adr) { | |
4817 prefix(adr); | |
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|
4818 emit_int8(0x0F); |
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changeset
|
4819 emit_int8((unsigned char)0xAE); |
304 | 4820 emit_operand(rdi, adr); |
4821 } | |
4822 | |
4823 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
4824 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
4825 emit_int8(0x0F); |
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diff
changeset
|
4826 emit_int8(0x40 | cc); |
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diff
changeset
|
4827 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4828 } |
4829 | |
4830 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
4831 InstructionMark im(this); | |
4832 prefixq(src, dst); | |
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|
4833 emit_int8(0x0F); |
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diff
changeset
|
4834 emit_int8(0x40 | cc); |
304 | 4835 emit_operand(dst, src); |
4836 } | |
4837 | |
4838 void Assembler::cmpq(Address dst, int32_t imm32) { | |
4839 InstructionMark im(this); | |
4840 prefixq(dst); | |
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changeset
|
4841 emit_int8((unsigned char)0x81); |
304 | 4842 emit_operand(rdi, dst, 4); |
7476
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diff
changeset
|
4843 emit_int32(imm32); |
304 | 4844 } |
4845 | |
4846 void Assembler::cmpq(Register dst, int32_t imm32) { | |
4847 (void) prefixq_and_encode(dst->encoding()); | |
4848 emit_arith(0x81, 0xF8, dst, imm32); | |
4849 } | |
4850 | |
4851 void Assembler::cmpq(Address dst, Register src) { | |
4852 InstructionMark im(this); | |
4853 prefixq(dst, src); | |
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diff
changeset
|
4854 emit_int8(0x3B); |
304 | 4855 emit_operand(src, dst); |
4856 } | |
4857 | |
4858 void Assembler::cmpq(Register dst, Register src) { | |
4859 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4860 emit_arith(0x3B, 0xC0, dst, src); | |
4861 } | |
4862 | |
4863 void Assembler::cmpq(Register dst, Address src) { | |
4864 InstructionMark im(this); | |
4865 prefixq(src, dst); | |
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diff
changeset
|
4866 emit_int8(0x3B); |
304 | 4867 emit_operand(dst, src); |
4868 } | |
4869 | |
4870 void Assembler::cmpxchgq(Register reg, Address adr) { | |
4871 InstructionMark im(this); | |
4872 prefixq(adr, reg); | |
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changeset
|
4873 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4874 emit_int8((unsigned char)0xB1); |
304 | 4875 emit_operand(reg, adr); |
4876 } | |
4877 | |
4878 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
4879 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 4880 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
7430
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7427
diff
changeset
|
4881 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4882 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4883 } |
4884 | |
4759 | 4885 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
4886 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4887 InstructionMark im(this); | |
4888 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4889 emit_int8(0x2A); |
4759 | 4890 emit_operand(dst, src); |
4891 } | |
4892 | |
304 | 4893 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
4894 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 4895 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4896 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4897 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4898 } |
4899 | |
4759 | 4900 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
4901 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4902 InstructionMark im(this); | |
4903 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4904 emit_int8(0x2A); |
4759 | 4905 emit_operand(dst, src); |
4906 } | |
4907 | |
304 | 4908 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
4909 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 4910 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4911 emit_int8(0x2C); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4912 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4913 } |
4914 | |
4915 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
4916 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 4917 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
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changeset
|
4918 emit_int8(0x2C); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4919 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4920 } |
4921 | |
4922 void Assembler::decl(Register dst) { | |
4923 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
4924 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
4925 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
4926 emit_int8((unsigned char)0xFF); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4927 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 4928 } |
4929 | |
4930 void Assembler::decq(Register dst) { | |
4931 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
4932 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4933 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
4934 emit_int8((unsigned char)0xFF); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4935 emit_int8(0xC8 | encode); |
304 | 4936 } |
4937 | |
4938 void Assembler::decq(Address dst) { | |
4939 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
4940 InstructionMark im(this); | |
4941 prefixq(dst); | |
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changeset
|
4942 emit_int8((unsigned char)0xFF); |
304 | 4943 emit_operand(rcx, dst); |
4944 } | |
4945 | |
4946 void Assembler::fxrstor(Address src) { | |
4947 prefixq(src); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4948 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4949 emit_int8((unsigned char)0xAE); |
304 | 4950 emit_operand(as_Register(1), src); |
4951 } | |
4952 | |
4953 void Assembler::fxsave(Address dst) { | |
4954 prefixq(dst); | |
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changeset
|
4955 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4956 emit_int8((unsigned char)0xAE); |
304 | 4957 emit_operand(as_Register(0), dst); |
4958 } | |
4959 | |
4960 void Assembler::idivq(Register src) { | |
4961 int encode = prefixq_and_encode(src->encoding()); | |
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changeset
|
4962 emit_int8((unsigned char)0xF7); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4963 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 4964 } |
4965 | |
4966 void Assembler::imulq(Register dst, Register src) { | |
4967 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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changeset
|
4968 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4969 emit_int8((unsigned char)0xAF); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4970 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4971 } |
4972 | |
4973 void Assembler::imulq(Register dst, Register src, int value) { | |
4974 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4975 if (is8bit(value)) { | |
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changeset
|
4976 emit_int8(0x6B); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4977 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
4978 emit_int8(value & 0xFF); |
304 | 4979 } else { |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4980 emit_int8(0x69); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4981 emit_int8((unsigned char)(0xC0 | encode)); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
4982 emit_int32(value); |
304 | 4983 } |
4984 } | |
4985 | |
4986 void Assembler::incl(Register dst) { | |
4987 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
4988 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4989 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
4990 emit_int8((unsigned char)0xFF); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4991 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4992 } |
4993 | |
4994 void Assembler::incq(Register dst) { | |
4995 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
4996 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4997 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
4998 emit_int8((unsigned char)0xFF); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4999 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5000 } |
5001 | |
5002 void Assembler::incq(Address dst) { | |
5003 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
5004 InstructionMark im(this); | |
5005 prefixq(dst); | |
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changeset
|
5006 emit_int8((unsigned char)0xFF); |
304 | 5007 emit_operand(rax, dst); |
5008 } | |
5009 | |
5010 void Assembler::lea(Register dst, Address src) { | |
5011 leaq(dst, src); | |
5012 } | |
5013 | |
5014 void Assembler::leaq(Register dst, Address src) { | |
5015 InstructionMark im(this); | |
5016 prefixq(src, dst); | |
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diff
changeset
|
5017 emit_int8((unsigned char)0x8D); |
304 | 5018 emit_operand(dst, src); |
5019 } | |
5020 | |
5021 void Assembler::mov64(Register dst, int64_t imm64) { | |
5022 InstructionMark im(this); | |
5023 int encode = prefixq_and_encode(dst->encoding()); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5024 emit_int8((unsigned char)(0xB8 | encode)); |
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
twisti
parents:
6894
diff
changeset
|
5025 emit_int64(imm64); |
304 | 5026 } |
5027 | |
5028 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
5029 InstructionMark im(this); | |
5030 int encode = prefixq_and_encode(dst->encoding()); | |
7430
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7427
diff
changeset
|
5031 emit_int8(0xB8 | encode); |
304 | 5032 emit_data64(imm64, rspec); |
5033 } | |
5034 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
5035 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5036 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5037 int encode = prefix_and_encode(dst->encoding()); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5038 emit_int8((unsigned char)(0xB8 | encode)); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
5039 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5040 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5041 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5042 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5043 InstructionMark im(this); |
660978a2a31a
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diff
changeset
|
5044 prefix(dst); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5045 emit_int8((unsigned char)0xC7); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5046 emit_operand(rax, dst, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
5047 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5048 } |
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624
diff
changeset
|
5049 |
660978a2a31a
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diff
changeset
|
5050 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5051 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5052 int encode = prefix_and_encode(src1->encoding()); |
7430
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7427
diff
changeset
|
5053 emit_int8((unsigned char)0x81); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5054 emit_int8((unsigned char)(0xF8 | encode)); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5055 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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624
diff
changeset
|
5056 } |
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624
diff
changeset
|
5057 |
660978a2a31a
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diff
changeset
|
5058 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5059 InstructionMark im(this); |
660978a2a31a
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diff
changeset
|
5060 prefix(src1); |
7430
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diff
changeset
|
5061 emit_int8((unsigned char)0x81); |
642
660978a2a31a
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624
diff
changeset
|
5062 emit_operand(rax, src1, 4); |
660978a2a31a
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diff
changeset
|
5063 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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diff
changeset
|
5064 } |
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diff
changeset
|
5065 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
5066 void Assembler::lzcntq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
5067 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
7430
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7427
diff
changeset
|
5068 emit_int8((unsigned char)0xF3); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5069 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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diff
changeset
|
5070 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5071 emit_int8((unsigned char)0xBD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5072 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
5073 } |
93c14e5562c4
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twisti
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710
diff
changeset
|
5074 |
304 | 5075 void Assembler::movdq(XMMRegister dst, Register src) { |
5076 // table D-1 says MMX/SSE2 | |
4759 | 5077 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
5078 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
7430
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7427
diff
changeset
|
5079 emit_int8(0x6E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5080 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5081 } |
5082 | |
5083 void Assembler::movdq(Register dst, XMMRegister src) { | |
5084 // table D-1 says MMX/SSE2 | |
4759 | 5085 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
304 | 5086 // swap src/dst to get correct prefix |
4759 | 5087 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
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7427
diff
changeset
|
5088 emit_int8(0x7E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5089 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5090 } |
5091 | |
5092 void Assembler::movq(Register dst, Register src) { | |
5093 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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diff
changeset
|
5094 emit_int8((unsigned char)0x8B); |
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5095 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5096 } |
5097 | |
5098 void Assembler::movq(Register dst, Address src) { | |
5099 InstructionMark im(this); | |
5100 prefixq(src, dst); | |
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|
5101 emit_int8((unsigned char)0x8B); |
304 | 5102 emit_operand(dst, src); |
5103 } | |
5104 | |
5105 void Assembler::movq(Address dst, Register src) { | |
5106 InstructionMark im(this); | |
5107 prefixq(dst, src); | |
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|
5108 emit_int8((unsigned char)0x89); |
304 | 5109 emit_operand(src, dst); |
5110 } | |
5111 | |
624 | 5112 void Assembler::movsbq(Register dst, Address src) { |
5113 InstructionMark im(this); | |
5114 prefixq(src, dst); | |
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|
5115 emit_int8(0x0F); |
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|
5116 emit_int8((unsigned char)0xBE); |
624 | 5117 emit_operand(dst, src); |
5118 } | |
5119 | |
5120 void Assembler::movsbq(Register dst, Register src) { | |
5121 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5122 emit_int8(0x0F); |
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|
5123 emit_int8((unsigned char)0xBE); |
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5124 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5125 } |
5126 | |
304 | 5127 void Assembler::movslq(Register dst, int32_t imm32) { |
5128 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
5129 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
5130 // as a result we shouldn't use until tested at runtime... | |
5131 ShouldNotReachHere(); | |
5132 InstructionMark im(this); | |
5133 int encode = prefixq_and_encode(dst->encoding()); | |
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5134 emit_int8((unsigned char)(0xC7 | encode)); |
7476
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|
5135 emit_int32(imm32); |
304 | 5136 } |
5137 | |
5138 void Assembler::movslq(Address dst, int32_t imm32) { | |
5139 assert(is_simm32(imm32), "lost bits"); | |
5140 InstructionMark im(this); | |
5141 prefixq(dst); | |
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5142 emit_int8((unsigned char)0xC7); |
304 | 5143 emit_operand(rax, dst, 4); |
7476
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5144 emit_int32(imm32); |
304 | 5145 } |
5146 | |
5147 void Assembler::movslq(Register dst, Address src) { | |
5148 InstructionMark im(this); | |
5149 prefixq(src, dst); | |
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|
5150 emit_int8(0x63); |
304 | 5151 emit_operand(dst, src); |
5152 } | |
5153 | |
5154 void Assembler::movslq(Register dst, Register src) { | |
5155 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5156 emit_int8(0x63); |
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|
5157 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5158 } |
5159 | |
624 | 5160 void Assembler::movswq(Register dst, Address src) { |
5161 InstructionMark im(this); | |
5162 prefixq(src, dst); | |
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|
5163 emit_int8(0x0F); |
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|
5164 emit_int8((unsigned char)0xBF); |
624 | 5165 emit_operand(dst, src); |
5166 } | |
5167 | |
5168 void Assembler::movswq(Register dst, Register src) { | |
5169 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5170 emit_int8((unsigned char)0x0F); |
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changeset
|
5171 emit_int8((unsigned char)0xBF); |
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|
5172 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5173 } |
5174 | |
5175 void Assembler::movzbq(Register dst, Address src) { | |
5176 InstructionMark im(this); | |
5177 prefixq(src, dst); | |
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changeset
|
5178 emit_int8((unsigned char)0x0F); |
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changeset
|
5179 emit_int8((unsigned char)0xB6); |
624 | 5180 emit_operand(dst, src); |
5181 } | |
5182 | |
5183 void Assembler::movzbq(Register dst, Register src) { | |
5184 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5185 emit_int8(0x0F); |
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changeset
|
5186 emit_int8((unsigned char)0xB6); |
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|
5187 emit_int8(0xC0 | encode); |
624 | 5188 } |
5189 | |
5190 void Assembler::movzwq(Register dst, Address src) { | |
5191 InstructionMark im(this); | |
5192 prefixq(src, dst); | |
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|
5193 emit_int8((unsigned char)0x0F); |
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|
5194 emit_int8((unsigned char)0xB7); |
624 | 5195 emit_operand(dst, src); |
5196 } | |
5197 | |
5198 void Assembler::movzwq(Register dst, Register src) { | |
5199 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5200 emit_int8((unsigned char)0x0F); |
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changeset
|
5201 emit_int8((unsigned char)0xB7); |
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5202 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5203 } |
5204 | |
304 | 5205 void Assembler::negq(Register dst) { |
5206 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5207 emit_int8((unsigned char)0xF7); |
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changeset
|
5208 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 5209 } |
5210 | |
5211 void Assembler::notq(Register dst) { | |
5212 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5213 emit_int8((unsigned char)0xF7); |
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changeset
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5214 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5215 } |
5216 | |
5217 void Assembler::orq(Address dst, int32_t imm32) { | |
5218 InstructionMark im(this); | |
5219 prefixq(dst); | |
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|
5220 emit_int8((unsigned char)0x81); |
304 | 5221 emit_operand(rcx, dst, 4); |
7476
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|
5222 emit_int32(imm32); |
304 | 5223 } |
5224 | |
5225 void Assembler::orq(Register dst, int32_t imm32) { | |
5226 (void) prefixq_and_encode(dst->encoding()); | |
5227 emit_arith(0x81, 0xC8, dst, imm32); | |
5228 } | |
5229 | |
5230 void Assembler::orq(Register dst, Address src) { | |
5231 InstructionMark im(this); | |
5232 prefixq(src, dst); | |
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changeset
|
5233 emit_int8(0x0B); |
304 | 5234 emit_operand(dst, src); |
5235 } | |
5236 | |
5237 void Assembler::orq(Register dst, Register src) { | |
5238 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5239 emit_arith(0x0B, 0xC0, dst, src); | |
5240 } | |
5241 | |
5242 void Assembler::popa() { // 64bit | |
5243 movq(r15, Address(rsp, 0)); | |
5244 movq(r14, Address(rsp, wordSize)); | |
5245 movq(r13, Address(rsp, 2 * wordSize)); | |
5246 movq(r12, Address(rsp, 3 * wordSize)); | |
5247 movq(r11, Address(rsp, 4 * wordSize)); | |
5248 movq(r10, Address(rsp, 5 * wordSize)); | |
5249 movq(r9, Address(rsp, 6 * wordSize)); | |
5250 movq(r8, Address(rsp, 7 * wordSize)); | |
5251 movq(rdi, Address(rsp, 8 * wordSize)); | |
5252 movq(rsi, Address(rsp, 9 * wordSize)); | |
5253 movq(rbp, Address(rsp, 10 * wordSize)); | |
5254 // skip rsp | |
5255 movq(rbx, Address(rsp, 12 * wordSize)); | |
5256 movq(rdx, Address(rsp, 13 * wordSize)); | |
5257 movq(rcx, Address(rsp, 14 * wordSize)); | |
5258 movq(rax, Address(rsp, 15 * wordSize)); | |
5259 | |
5260 addq(rsp, 16 * wordSize); | |
5261 } | |
5262 | |
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
5263 void Assembler::popcntq(Register dst, Address src) { |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5264 assert(VM_Version::supports_popcnt(), "must support"); |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5265 InstructionMark im(this); |
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|
5266 emit_int8((unsigned char)0xF3); |
643
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changeset
|
5267 prefixq(src, dst); |
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|
5268 emit_int8((unsigned char)0x0F); |
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changeset
|
5269 emit_int8((unsigned char)0xB8); |
643
c771b7f43bbf
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changeset
|
5270 emit_operand(dst, src); |
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changeset
|
5271 } |
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changeset
|
5272 |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5273 void Assembler::popcntq(Register dst, Register src) { |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5274 assert(VM_Version::supports_popcnt(), "must support"); |
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changeset
|
5275 emit_int8((unsigned char)0xF3); |
643
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changeset
|
5276 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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changeset
|
5277 emit_int8((unsigned char)0x0F); |
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changeset
|
5278 emit_int8((unsigned char)0xB8); |
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changeset
|
5279 emit_int8((unsigned char)(0xC0 | encode)); |
643
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changeset
|
5280 } |
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|
5281 |
304 | 5282 void Assembler::popq(Address dst) { |
5283 InstructionMark im(this); | |
5284 prefixq(dst); | |
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changeset
|
5285 emit_int8((unsigned char)0x8F); |
304 | 5286 emit_operand(rax, dst); |
5287 } | |
5288 | |
5289 void Assembler::pusha() { // 64bit | |
5290 // we have to store original rsp. ABI says that 128 bytes | |
5291 // below rsp are local scratch. | |
5292 movq(Address(rsp, -5 * wordSize), rsp); | |
5293 | |
5294 subq(rsp, 16 * wordSize); | |
5295 | |
5296 movq(Address(rsp, 15 * wordSize), rax); | |
5297 movq(Address(rsp, 14 * wordSize), rcx); | |
5298 movq(Address(rsp, 13 * wordSize), rdx); | |
5299 movq(Address(rsp, 12 * wordSize), rbx); | |
5300 // skip rsp | |
5301 movq(Address(rsp, 10 * wordSize), rbp); | |
5302 movq(Address(rsp, 9 * wordSize), rsi); | |
5303 movq(Address(rsp, 8 * wordSize), rdi); | |
5304 movq(Address(rsp, 7 * wordSize), r8); | |
5305 movq(Address(rsp, 6 * wordSize), r9); | |
5306 movq(Address(rsp, 5 * wordSize), r10); | |
5307 movq(Address(rsp, 4 * wordSize), r11); | |
5308 movq(Address(rsp, 3 * wordSize), r12); | |
5309 movq(Address(rsp, 2 * wordSize), r13); | |
5310 movq(Address(rsp, wordSize), r14); | |
5311 movq(Address(rsp, 0), r15); | |
5312 } | |
5313 | |
5314 void Assembler::pushq(Address src) { | |
5315 InstructionMark im(this); | |
5316 prefixq(src); | |
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|
5317 emit_int8((unsigned char)0xFF); |
304 | 5318 emit_operand(rsi, src); |
5319 } | |
5320 | |
5321 void Assembler::rclq(Register dst, int imm8) { | |
5322 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5323 int encode = prefixq_and_encode(dst->encoding()); | |
5324 if (imm8 == 1) { | |
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|
5325 emit_int8((unsigned char)0xD1); |
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changeset
|
5326 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5327 } else { |
7430
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changeset
|
5328 emit_int8((unsigned char)0xC1); |
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changeset
|
5329 emit_int8((unsigned char)(0xD0 | encode)); |
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changeset
|
5330 emit_int8(imm8); |
304 | 5331 } |
5332 } | |
5333 void Assembler::sarq(Register dst, int imm8) { | |
5334 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5335 int encode = prefixq_and_encode(dst->encoding()); | |
5336 if (imm8 == 1) { | |
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changeset
|
5337 emit_int8((unsigned char)0xD1); |
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changeset
|
5338 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5339 } else { |
7430
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changeset
|
5340 emit_int8((unsigned char)0xC1); |
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changeset
|
5341 emit_int8((unsigned char)(0xF8 | encode)); |
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changeset
|
5342 emit_int8(imm8); |
304 | 5343 } |
5344 } | |
5345 | |
5346 void Assembler::sarq(Register dst) { | |
5347 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5348 emit_int8((unsigned char)0xD3); |
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changeset
|
5349 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5350 } |
2100
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5351 |
304 | 5352 void Assembler::sbbq(Address dst, int32_t imm32) { |
5353 InstructionMark im(this); | |
5354 prefixq(dst); | |
5355 emit_arith_operand(0x81, rbx, dst, imm32); | |
5356 } | |
5357 | |
5358 void Assembler::sbbq(Register dst, int32_t imm32) { | |
5359 (void) prefixq_and_encode(dst->encoding()); | |
5360 emit_arith(0x81, 0xD8, dst, imm32); | |
5361 } | |
5362 | |
5363 void Assembler::sbbq(Register dst, Address src) { | |
5364 InstructionMark im(this); | |
5365 prefixq(src, dst); | |
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5366 emit_int8(0x1B); |
304 | 5367 emit_operand(dst, src); |
5368 } | |
5369 | |
5370 void Assembler::sbbq(Register dst, Register src) { | |
5371 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5372 emit_arith(0x1B, 0xC0, dst, src); | |
5373 } | |
5374 | |
5375 void Assembler::shlq(Register dst, int imm8) { | |
5376 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5377 int encode = prefixq_and_encode(dst->encoding()); | |
5378 if (imm8 == 1) { | |
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5379 emit_int8((unsigned char)0xD1); |
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5380 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5381 } else { |
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5382 emit_int8((unsigned char)0xC1); |
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5383 emit_int8((unsigned char)(0xE0 | encode)); |
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5384 emit_int8(imm8); |
304 | 5385 } |
5386 } | |
5387 | |
5388 void Assembler::shlq(Register dst) { | |
5389 int encode = prefixq_and_encode(dst->encoding()); | |
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5390 emit_int8((unsigned char)0xD3); |
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5391 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5392 } |
5393 | |
5394 void Assembler::shrq(Register dst, int imm8) { | |
5395 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5396 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5397 emit_int8((unsigned char)0xC1); |
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|
5398 emit_int8((unsigned char)(0xE8 | encode)); |
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|
5399 emit_int8(imm8); |
304 | 5400 } |
5401 | |
5402 void Assembler::shrq(Register dst) { | |
5403 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5404 emit_int8((unsigned char)0xD3); |
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|
5405 emit_int8(0xE8 | encode); |
304 | 5406 } |
5407 | |
5408 void Assembler::subq(Address dst, int32_t imm32) { | |
5409 InstructionMark im(this); | |
5410 prefixq(dst); | |
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5411 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 5412 } |
5413 | |
5414 void Assembler::subq(Address dst, Register src) { | |
5415 InstructionMark im(this); | |
5416 prefixq(dst, src); | |
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|
5417 emit_int8(0x29); |
304 | 5418 emit_operand(src, dst); |
5419 } | |
5420 | |
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5421 void Assembler::subq(Register dst, int32_t imm32) { |
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|
5422 (void) prefixq_and_encode(dst->encoding()); |
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|
5423 emit_arith(0x81, 0xE8, dst, imm32); |
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|
5424 } |
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|
5425 |
4947
fd8114661503
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|
5426 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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|
5427 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
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|
5428 (void) prefixq_and_encode(dst->encoding()); |
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|
5429 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
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|
5430 } |
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|
5431 |
304 | 5432 void Assembler::subq(Register dst, Address src) { |
5433 InstructionMark im(this); | |
5434 prefixq(src, dst); | |
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|
5435 emit_int8(0x2B); |
304 | 5436 emit_operand(dst, src); |
5437 } | |
5438 | |
5439 void Assembler::subq(Register dst, Register src) { | |
5440 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5441 emit_arith(0x2B, 0xC0, dst, src); | |
5442 } | |
5443 | |
5444 void Assembler::testq(Register dst, int32_t imm32) { | |
5445 // not using emit_arith because test | |
5446 // doesn't support sign-extension of | |
5447 // 8bit operands | |
5448 int encode = dst->encoding(); | |
5449 if (encode == 0) { | |
5450 prefix(REX_W); | |
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|
5451 emit_int8((unsigned char)0xA9); |
304 | 5452 } else { |
5453 encode = prefixq_and_encode(encode); | |
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|
5454 emit_int8((unsigned char)0xF7); |
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|
5455 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5456 } |
7476
ffa87474d7a4
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7475
diff
changeset
|
5457 emit_int32(imm32); |
304 | 5458 } |
5459 | |
5460 void Assembler::testq(Register dst, Register src) { | |
5461 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5462 emit_arith(0x85, 0xC0, dst, src); | |
5463 } | |
5464 | |
5465 void Assembler::xaddq(Address dst, Register src) { | |
5466 InstructionMark im(this); | |
5467 prefixq(dst, src); | |
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|
5468 emit_int8(0x0F); |
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|
5469 emit_int8((unsigned char)0xC1); |
304 | 5470 emit_operand(src, dst); |
5471 } | |
5472 | |
5473 void Assembler::xchgq(Register dst, Address src) { | |
5474 InstructionMark im(this); | |
5475 prefixq(src, dst); | |
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|
5476 emit_int8((unsigned char)0x87); |
304 | 5477 emit_operand(dst, src); |
5478 } | |
5479 | |
5480 void Assembler::xchgq(Register dst, Register src) { | |
5481 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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|
5482 emit_int8((unsigned char)0x87); |
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|
5483 emit_int8((unsigned char)(0xc0 | encode)); |
304 | 5484 } |
5485 | |
5486 void Assembler::xorq(Register dst, Register src) { | |
5487 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5488 emit_arith(0x33, 0xC0, dst, src); | |
5489 } | |
5490 | |
5491 void Assembler::xorq(Register dst, Address src) { | |
5492 InstructionMark im(this); | |
5493 prefixq(src, dst); | |
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|
5494 emit_int8(0x33); |
304 | 5495 emit_operand(dst, src); |
5496 } | |
5497 | |
5498 #endif // !LP64 |